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data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
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DemoSDRAM_system_ila_0_0_sim_netlist.v
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[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_daddr_o, \parallel_dout_reg[15]_0 , s_do_o, Q, \parallel_dout_reg[15]_1 , \parallel_dout_reg[14]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o); output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [5:0]s_daddr_o; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]Q; input [15:0]\parallel_dout_reg[15]_1 ; input \parallel_dout_reg[14]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [15:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__22_n_0 ; wire \current_state[3]_i_3__22_n_0 ; wire \current_state[3]_i_4__22_n_0 ; wire data_out_sel; wire data_out_sel_i_1__22_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__22_n_0 ; wire \shadow[10]_i_1__22_n_0 ; wire \shadow[11]_i_1__22_n_0 ; wire \shadow[12]_i_1__22_n_0 ; wire \shadow[13]_i_1__22_n_0 ; wire \shadow[14]_i_1__22_n_0 ; wire \shadow[15]_i_1__22_n_0 ; wire \shadow[1]_i_1__22_n_0 ; wire \shadow[2]_i_1__22_n_0 ; wire \shadow[3]_i_1__22_n_0 ; wire \shadow[4]_i_1__22_n_0 ; wire \shadow[5]_i_1__22_n_0 ; wire \shadow[6]_i_1__22_n_0 ; wire \shadow[7]_i_1__22_n_0 ; wire \shadow[8]_i_1__22_n_0 ; wire \shadow[9]_i_1__22_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__22_n_0; wire \slaveRegDo_mux_5[0]_i_10_n_0 ; wire \slaveRegDo_mux_5[10]_i_10_n_0 ; wire \slaveRegDo_mux_5[11]_i_10_n_0 ; wire \slaveRegDo_mux_5[12]_i_10_n_0 ; wire \slaveRegDo_mux_5[13]_i_10_n_0 ; wire \slaveRegDo_mux_5[14]_i_10_n_0 ; wire \slaveRegDo_mux_5[15]_i_10_n_0 ; wire \slaveRegDo_mux_5[1]_i_10_n_0 ; wire \slaveRegDo_mux_5[2]_i_10_n_0 ; wire \slaveRegDo_mux_5[3]_i_10_n_0 ; wire \slaveRegDo_mux_5[4]_i_10_n_0 ; wire \slaveRegDo_mux_5[5]_i_10_n_0 ; wire \slaveRegDo_mux_5[6]_i_10_n_0 ; wire \slaveRegDo_mux_5[7]_i_10_n_0 ; wire \slaveRegDo_mux_5[8]_i_10_n_0 ; wire \slaveRegDo_mux_5[9]_i_10_n_0 ; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5131]_21 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__22 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__22 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__22 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__22 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__22 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__22 (.I0(\current_state[3]_i_4__22_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__22_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__22_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__22 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__22_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__22 (.I0(current_state[1]), .I1(\current_state[3]_i_2__22_n_0 ), .I2(\current_state[3]_i_4__22_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__22 (.I0(\current_state[3]_i_2__22_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__22_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__22_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__22 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__22_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__22 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[5]), .O(\current_state[3]_i_3__22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__22 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__22_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__22 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__22_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__22_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [1]), .Q(\slaveRegDo_tcConfig[5131]_21 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [11]), .Q(\slaveRegDo_tcConfig[5131]_21 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [12]), .Q(\slaveRegDo_tcConfig[5131]_21 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [13]), .Q(\slaveRegDo_tcConfig[5131]_21 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [14]), .Q(\slaveRegDo_tcConfig[5131]_21 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [15]), .Q(\slaveRegDo_tcConfig[5131]_21 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5131]_21 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [2]), .Q(\slaveRegDo_tcConfig[5131]_21 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [3]), .Q(\slaveRegDo_tcConfig[5131]_21 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [4]), .Q(\slaveRegDo_tcConfig[5131]_21 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [5]), .Q(\slaveRegDo_tcConfig[5131]_21 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [6]), .Q(\slaveRegDo_tcConfig[5131]_21 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [7]), .Q(\slaveRegDo_tcConfig[5131]_21 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [8]), .Q(\slaveRegDo_tcConfig[5131]_21 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [9]), .Q(\slaveRegDo_tcConfig[5131]_21 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [10]), .Q(\slaveRegDo_tcConfig[5131]_21 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__22 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__22 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__22 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__22 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__22 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__22 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__22_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__22 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__22 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__22 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__22 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__22 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__22 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__22 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__22 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__22 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__22 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__22_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__22 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__22_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__22_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(Q[0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5[0]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(Q[10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5[10]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(Q[11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5[11]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(Q[12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5[12]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(Q[13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5[13]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(Q[14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5[14]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(Q[15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5[15]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(Q[1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5[1]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(Q[2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5[2]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(Q[3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5[3]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(Q[4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5[4]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(Q[5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5[5]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(Q[6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5[6]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(Q[7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5[7]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(Q[8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5[8]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(Q[9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5[9]_i_10_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_4 (.I0(\slaveRegDo_mux_5[0]_i_10_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_4 (.I0(\slaveRegDo_mux_5[10]_i_10_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_4 (.I0(\slaveRegDo_mux_5[11]_i_10_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_4 (.I0(\slaveRegDo_mux_5[12]_i_10_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_4 (.I0(\slaveRegDo_mux_5[13]_i_10_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_4 (.I0(\slaveRegDo_mux_5[14]_i_10_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_4 (.I0(\slaveRegDo_mux_5[15]_i_10_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_4 (.I0(\slaveRegDo_mux_5[1]_i_10_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_4 (.I0(\slaveRegDo_mux_5[2]_i_10_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_4 (.I0(\slaveRegDo_mux_5[3]_i_10_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_4 (.I0(\slaveRegDo_mux_5[4]_i_10_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_4 (.I0(\slaveRegDo_mux_5[5]_i_10_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_4 (.I0(\slaveRegDo_mux_5[6]_i_10_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_4 (.I0(\slaveRegDo_mux_5[7]_i_10_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_4 (.I0(\slaveRegDo_mux_5[8]_i_10_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_4 (.I0(\slaveRegDo_mux_5[9]_i_10_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9] ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__21 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_daddr_o, \parallel_dout_reg[15]_0 , s_do_o, Q, \parallel_dout_reg[15]_1 , \parallel_dout_reg[14]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o);
output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [5:0]s_daddr_o; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]Q; input [15:0]\parallel_dout_reg[15]_1 ; input \parallel_dout_reg[14]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [15:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__22_n_0 ; wire \current_state[3]_i_3__22_n_0 ; wire \current_state[3]_i_4__22_n_0 ; wire data_out_sel; wire data_out_sel_i_1__22_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__22_n_0 ; wire \shadow[10]_i_1__22_n_0 ; wire \shadow[11]_i_1__22_n_0 ; wire \shadow[12]_i_1__22_n_0 ; wire \shadow[13]_i_1__22_n_0 ; wire \shadow[14]_i_1__22_n_0 ; wire \shadow[15]_i_1__22_n_0 ; wire \shadow[1]_i_1__22_n_0 ; wire \shadow[2]_i_1__22_n_0 ; wire \shadow[3]_i_1__22_n_0 ; wire \shadow[4]_i_1__22_n_0 ; wire \shadow[5]_i_1__22_n_0 ; wire \shadow[6]_i_1__22_n_0 ; wire \shadow[7]_i_1__22_n_0 ; wire \shadow[8]_i_1__22_n_0 ; wire \shadow[9]_i_1__22_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__22_n_0; wire \slaveRegDo_mux_5[0]_i_10_n_0 ; wire \slaveRegDo_mux_5[10]_i_10_n_0 ; wire \slaveRegDo_mux_5[11]_i_10_n_0 ; wire \slaveRegDo_mux_5[12]_i_10_n_0 ; wire \slaveRegDo_mux_5[13]_i_10_n_0 ; wire \slaveRegDo_mux_5[14]_i_10_n_0 ; wire \slaveRegDo_mux_5[15]_i_10_n_0 ; wire \slaveRegDo_mux_5[1]_i_10_n_0 ; wire \slaveRegDo_mux_5[2]_i_10_n_0 ; wire \slaveRegDo_mux_5[3]_i_10_n_0 ; wire \slaveRegDo_mux_5[4]_i_10_n_0 ; wire \slaveRegDo_mux_5[5]_i_10_n_0 ; wire \slaveRegDo_mux_5[6]_i_10_n_0 ; wire \slaveRegDo_mux_5[7]_i_10_n_0 ; wire \slaveRegDo_mux_5[8]_i_10_n_0 ; wire \slaveRegDo_mux_5[9]_i_10_n_0 ; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5131]_21 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__22 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__22 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__22 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__22 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__22 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__22 (.I0(\current_state[3]_i_4__22_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__22_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__22_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__22 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__22_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__22 (.I0(current_state[1]), .I1(\current_state[3]_i_2__22_n_0 ), .I2(\current_state[3]_i_4__22_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__22 (.I0(\current_state[3]_i_2__22_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__22_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__22_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__22 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__22_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__22 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[5]), .O(\current_state[3]_i_3__22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__22 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__22_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__22 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__22_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__22_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [1]), .Q(\slaveRegDo_tcConfig[5131]_21 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [11]), .Q(\slaveRegDo_tcConfig[5131]_21 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [12]), .Q(\slaveRegDo_tcConfig[5131]_21 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [13]), .Q(\slaveRegDo_tcConfig[5131]_21 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [14]), .Q(\slaveRegDo_tcConfig[5131]_21 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [15]), .Q(\slaveRegDo_tcConfig[5131]_21 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5131]_21 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [2]), .Q(\slaveRegDo_tcConfig[5131]_21 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [3]), .Q(\slaveRegDo_tcConfig[5131]_21 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [4]), .Q(\slaveRegDo_tcConfig[5131]_21 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [5]), .Q(\slaveRegDo_tcConfig[5131]_21 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [6]), .Q(\slaveRegDo_tcConfig[5131]_21 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [7]), .Q(\slaveRegDo_tcConfig[5131]_21 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [8]), .Q(\slaveRegDo_tcConfig[5131]_21 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [9]), .Q(\slaveRegDo_tcConfig[5131]_21 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5131]_21 [10]), .Q(\slaveRegDo_tcConfig[5131]_21 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__22 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__22 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__22 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__22 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__22 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__22 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__22_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__22 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__22 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__22 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__22 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__22 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__22 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__22 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__22 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__22 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__22_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__22 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__22_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__22_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__22 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__22_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__22_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(Q[0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5[0]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(Q[10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5[10]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(Q[11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5[11]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(Q[12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5[12]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(Q[13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5[13]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(Q[14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5[14]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(Q[15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5[15]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(Q[1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5[1]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(Q[2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5[2]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(Q[3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5[3]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(Q[4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5[4]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(Q[5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5[5]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(Q[6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5[6]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(Q[7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5[7]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(Q[8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5[8]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_10 (.I0(\slaveRegDo_tcConfig[5131]_21 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(Q[9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5[9]_i_10_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_4 (.I0(\slaveRegDo_mux_5[0]_i_10_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_4 (.I0(\slaveRegDo_mux_5[10]_i_10_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_4 (.I0(\slaveRegDo_mux_5[11]_i_10_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_4 (.I0(\slaveRegDo_mux_5[12]_i_10_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_4 (.I0(\slaveRegDo_mux_5[13]_i_10_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_4 (.I0(\slaveRegDo_mux_5[14]_i_10_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_4 (.I0(\slaveRegDo_mux_5[15]_i_10_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_4 (.I0(\slaveRegDo_mux_5[1]_i_10_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_4 (.I0(\slaveRegDo_mux_5[2]_i_10_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_4 (.I0(\slaveRegDo_mux_5[3]_i_10_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_4 (.I0(\slaveRegDo_mux_5[4]_i_10_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_4 (.I0(\slaveRegDo_mux_5[5]_i_10_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_4 (.I0(\slaveRegDo_mux_5[6]_i_10_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_4 (.I0(\slaveRegDo_mux_5[7]_i_10_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_4 (.I0(\slaveRegDo_mux_5[8]_i_10_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_4 (.I0(\slaveRegDo_mux_5[9]_i_10_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9] ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__21 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,443
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__23_n_0 ; wire \current_state[3]_i_3__23_n_0 ; wire \current_state[3]_i_4__23_n_0 ; wire data_out_sel; wire data_out_sel_i_1__23_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__23_n_0 ; wire \shadow[10]_i_1__23_n_0 ; wire \shadow[11]_i_1__23_n_0 ; wire \shadow[12]_i_1__23_n_0 ; wire \shadow[13]_i_1__23_n_0 ; wire \shadow[14]_i_1__23_n_0 ; wire \shadow[15]_i_1__23_n_0 ; wire \shadow[1]_i_1__23_n_0 ; wire \shadow[2]_i_1__23_n_0 ; wire \shadow[3]_i_1__23_n_0 ; wire \shadow[4]_i_1__23_n_0 ; wire \shadow[5]_i_1__23_n_0 ; wire \shadow[6]_i_1__23_n_0 ; wire \shadow[7]_i_1__23_n_0 ; wire \shadow[8]_i_1__23_n_0 ; wire \shadow[9]_i_1__23_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__23_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__23 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__23 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__23 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__23 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__23 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__23 (.I0(\current_state[3]_i_4__23_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__23_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__23_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__23 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__23_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__23 (.I0(current_state[1]), .I1(\current_state[3]_i_2__23_n_0 ), .I2(\current_state[3]_i_4__23_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__23 (.I0(\current_state[3]_i_2__23_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__23_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__23_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__23 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__23 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__23 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__23_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__23 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__23_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__23_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__23 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__23 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__23 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__23 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__23 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__23 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__23_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__23 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__23 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__23 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__23 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__23 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__23 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__23 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__23 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__23 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__23 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__23_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__23 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__23_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__23_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__22 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__23_n_0 ; wire \current_state[3]_i_3__23_n_0 ; wire \current_state[3]_i_4__23_n_0 ; wire data_out_sel; wire data_out_sel_i_1__23_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__23_n_0 ; wire \shadow[10]_i_1__23_n_0 ; wire \shadow[11]_i_1__23_n_0 ; wire \shadow[12]_i_1__23_n_0 ; wire \shadow[13]_i_1__23_n_0 ; wire \shadow[14]_i_1__23_n_0 ; wire \shadow[15]_i_1__23_n_0 ; wire \shadow[1]_i_1__23_n_0 ; wire \shadow[2]_i_1__23_n_0 ; wire \shadow[3]_i_1__23_n_0 ; wire \shadow[4]_i_1__23_n_0 ; wire \shadow[5]_i_1__23_n_0 ; wire \shadow[6]_i_1__23_n_0 ; wire \shadow[7]_i_1__23_n_0 ; wire \shadow[8]_i_1__23_n_0 ; wire \shadow[9]_i_1__23_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__23_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__23 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__23 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__23 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__23 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__23 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__23 (.I0(\current_state[3]_i_4__23_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__23_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__23_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__23 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__23_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__23 (.I0(current_state[1]), .I1(\current_state[3]_i_2__23_n_0 ), .I2(\current_state[3]_i_4__23_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__23 (.I0(\current_state[3]_i_2__23_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__23_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__23_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__23 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__23_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__23 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__23 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__23_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__23 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__23_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__23_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__23 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__23 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__23 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__23 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__23 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__23 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__23_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__23 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__23 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__23 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__23 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__23 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__23 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__23 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__23 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__23 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__23_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__23 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__23_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__23_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__23 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__23_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__23_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__22 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,444
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__24_n_0 ; wire \current_state[3]_i_3__24_n_0 ; wire \current_state[3]_i_4__24_n_0 ; wire data_out_sel; wire data_out_sel_i_1__24_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__24_n_0 ; wire \shadow[10]_i_1__24_n_0 ; wire \shadow[11]_i_1__24_n_0 ; wire \shadow[12]_i_1__24_n_0 ; wire \shadow[13]_i_1__24_n_0 ; wire \shadow[14]_i_1__24_n_0 ; wire \shadow[15]_i_1__24_n_0 ; wire \shadow[1]_i_1__24_n_0 ; wire \shadow[2]_i_1__24_n_0 ; wire \shadow[3]_i_1__24_n_0 ; wire \shadow[4]_i_1__24_n_0 ; wire \shadow[5]_i_1__24_n_0 ; wire \shadow[6]_i_1__24_n_0 ; wire \shadow[7]_i_1__24_n_0 ; wire \shadow[8]_i_1__24_n_0 ; wire \shadow[9]_i_1__24_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__24_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__24 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__24 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__24 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__24 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__24 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__24 (.I0(\current_state[3]_i_4__24_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__24_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__24_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__24 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__24_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__24 (.I0(current_state[1]), .I1(\current_state[3]_i_2__24_n_0 ), .I2(\current_state[3]_i_4__24_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__24 (.I0(\current_state[3]_i_2__24_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__24_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__24_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__24 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__24 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__24 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__24_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__24 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__24_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__24_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__24 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__24 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__24 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__24 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__24 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__24 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__24_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__24 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__24 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__24 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__24 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__24 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__24 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__24 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__24 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__24 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__24 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__24_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__24 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__24_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__24_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__23 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__24_n_0 ; wire \current_state[3]_i_3__24_n_0 ; wire \current_state[3]_i_4__24_n_0 ; wire data_out_sel; wire data_out_sel_i_1__24_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__24_n_0 ; wire \shadow[10]_i_1__24_n_0 ; wire \shadow[11]_i_1__24_n_0 ; wire \shadow[12]_i_1__24_n_0 ; wire \shadow[13]_i_1__24_n_0 ; wire \shadow[14]_i_1__24_n_0 ; wire \shadow[15]_i_1__24_n_0 ; wire \shadow[1]_i_1__24_n_0 ; wire \shadow[2]_i_1__24_n_0 ; wire \shadow[3]_i_1__24_n_0 ; wire \shadow[4]_i_1__24_n_0 ; wire \shadow[5]_i_1__24_n_0 ; wire \shadow[6]_i_1__24_n_0 ; wire \shadow[7]_i_1__24_n_0 ; wire \shadow[8]_i_1__24_n_0 ; wire \shadow[9]_i_1__24_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__24_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__24 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__24 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__24 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__24 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__24 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__24 (.I0(\current_state[3]_i_4__24_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__24_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__24_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__24 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__24_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__24 (.I0(current_state[1]), .I1(\current_state[3]_i_2__24_n_0 ), .I2(\current_state[3]_i_4__24_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__24 (.I0(\current_state[3]_i_2__24_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__24_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__24_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__24 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__24 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__24 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__24_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__24 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__24_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__24_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__24 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__24 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__24 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__24 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__24 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__24 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__24_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__24 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__24 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__24 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__24 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__24 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__24 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__24 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__24 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__24 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__24_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__24 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__24_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__24_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__24 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__24_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__24_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__23 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,445
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__25_n_0 ; wire \current_state[3]_i_3__25_n_0 ; wire \current_state[3]_i_4__25_n_0 ; wire data_out_sel; wire data_out_sel_i_1__25_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__25_n_0 ; wire \shadow[10]_i_1__25_n_0 ; wire \shadow[11]_i_1__25_n_0 ; wire \shadow[12]_i_1__25_n_0 ; wire \shadow[13]_i_1__25_n_0 ; wire \shadow[14]_i_1__25_n_0 ; wire \shadow[15]_i_1__25_n_0 ; wire \shadow[1]_i_1__25_n_0 ; wire \shadow[2]_i_1__25_n_0 ; wire \shadow[3]_i_1__25_n_0 ; wire \shadow[4]_i_1__25_n_0 ; wire \shadow[5]_i_1__25_n_0 ; wire \shadow[6]_i_1__25_n_0 ; wire \shadow[7]_i_1__25_n_0 ; wire \shadow[8]_i_1__25_n_0 ; wire \shadow[9]_i_1__25_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__25_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__25 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__25 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__25 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__25 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__25 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__25 (.I0(\current_state[3]_i_4__25_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__25_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__25_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__25 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__25_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__25 (.I0(current_state[1]), .I1(\current_state[3]_i_2__25_n_0 ), .I2(\current_state[3]_i_4__25_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__25 (.I0(\current_state[3]_i_2__25_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__25_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__25_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__25 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__25 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__25 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__25_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__25 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__25_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__25_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__25 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__25 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__25 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__25 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__25 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__25 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__25_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__25 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__25 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__25 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__25 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__25 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__25 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__25 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__25 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__25 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__25 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__25_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__25 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__25_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__25_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__24 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__25_n_0 ; wire \current_state[3]_i_3__25_n_0 ; wire \current_state[3]_i_4__25_n_0 ; wire data_out_sel; wire data_out_sel_i_1__25_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__25_n_0 ; wire \shadow[10]_i_1__25_n_0 ; wire \shadow[11]_i_1__25_n_0 ; wire \shadow[12]_i_1__25_n_0 ; wire \shadow[13]_i_1__25_n_0 ; wire \shadow[14]_i_1__25_n_0 ; wire \shadow[15]_i_1__25_n_0 ; wire \shadow[1]_i_1__25_n_0 ; wire \shadow[2]_i_1__25_n_0 ; wire \shadow[3]_i_1__25_n_0 ; wire \shadow[4]_i_1__25_n_0 ; wire \shadow[5]_i_1__25_n_0 ; wire \shadow[6]_i_1__25_n_0 ; wire \shadow[7]_i_1__25_n_0 ; wire \shadow[8]_i_1__25_n_0 ; wire \shadow[9]_i_1__25_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__25_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__25 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__25 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__25 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__25 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__25 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__25 (.I0(\current_state[3]_i_4__25_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__25_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__25_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__25 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__25_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__25 (.I0(current_state[1]), .I1(\current_state[3]_i_2__25_n_0 ), .I2(\current_state[3]_i_4__25_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__25 (.I0(\current_state[3]_i_2__25_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__25_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__25_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__25 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__25_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFBF)) \current_state[3]_i_3__25 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__25 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__25_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__25 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__25_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__25_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__25 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__25 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__25 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__25 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__25 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__25 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__25_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__25 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__25 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__25 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__25 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__25 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__25 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__25 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__25 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__25 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__25_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__25 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__25_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__25_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__25 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__25_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__25_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__24 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,446
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o); output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [4:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__26_n_0 ; wire \current_state[3]_i_3__26_n_0 ; wire \current_state[3]_i_4__26_n_0 ; wire data_out_sel; wire data_out_sel_i_1__26_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__26_n_0 ; wire \shadow[10]_i_1__26_n_0 ; wire \shadow[11]_i_1__26_n_0 ; wire \shadow[12]_i_1__26_n_0 ; wire \shadow[13]_i_1__26_n_0 ; wire \shadow[14]_i_1__26_n_0 ; wire \shadow[15]_i_1__26_n_0 ; wire \shadow[1]_i_1__26_n_0 ; wire \shadow[2]_i_1__26_n_0 ; wire \shadow[3]_i_1__26_n_0 ; wire \shadow[4]_i_1__26_n_0 ; wire \shadow[5]_i_1__26_n_0 ; wire \shadow[6]_i_1__26_n_0 ; wire \shadow[7]_i_1__26_n_0 ; wire \shadow[8]_i_1__26_n_0 ; wire \shadow[9]_i_1__26_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__26_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5135]_25 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__26 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__26 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__26 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__26 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__26 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__26 (.I0(\current_state[3]_i_4__26_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__26_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__26_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__26 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__26_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__26 (.I0(current_state[1]), .I1(\current_state[3]_i_2__26_n_0 ), .I2(\current_state[3]_i_4__26_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__26 (.I0(\current_state[3]_i_2__26_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__26_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__26_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__26 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__26_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__26 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[2]), .I3(s_daddr_o[3]), .I4(s_den_o), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__26_n_0 )); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__26 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__26_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__26 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__26_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__26_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [1]), .Q(\slaveRegDo_tcConfig[5135]_25 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [11]), .Q(\slaveRegDo_tcConfig[5135]_25 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [12]), .Q(\slaveRegDo_tcConfig[5135]_25 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [13]), .Q(\slaveRegDo_tcConfig[5135]_25 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [14]), .Q(\slaveRegDo_tcConfig[5135]_25 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [15]), .Q(\slaveRegDo_tcConfig[5135]_25 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5135]_25 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [2]), .Q(\slaveRegDo_tcConfig[5135]_25 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [3]), .Q(\slaveRegDo_tcConfig[5135]_25 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [4]), .Q(\slaveRegDo_tcConfig[5135]_25 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [5]), .Q(\slaveRegDo_tcConfig[5135]_25 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [6]), .Q(\slaveRegDo_tcConfig[5135]_25 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [7]), .Q(\slaveRegDo_tcConfig[5135]_25 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [8]), .Q(\slaveRegDo_tcConfig[5135]_25 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [9]), .Q(\slaveRegDo_tcConfig[5135]_25 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [10]), .Q(\slaveRegDo_tcConfig[5135]_25 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__26 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__26 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__26 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__26 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__26 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__26 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__26_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__26 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__26 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__26 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__26 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__26 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__26 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__26 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__26 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__26 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__26 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__26_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__26 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__26_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__26_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__25 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o);
output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [4:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__26_n_0 ; wire \current_state[3]_i_3__26_n_0 ; wire \current_state[3]_i_4__26_n_0 ; wire data_out_sel; wire data_out_sel_i_1__26_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__26_n_0 ; wire \shadow[10]_i_1__26_n_0 ; wire \shadow[11]_i_1__26_n_0 ; wire \shadow[12]_i_1__26_n_0 ; wire \shadow[13]_i_1__26_n_0 ; wire \shadow[14]_i_1__26_n_0 ; wire \shadow[15]_i_1__26_n_0 ; wire \shadow[1]_i_1__26_n_0 ; wire \shadow[2]_i_1__26_n_0 ; wire \shadow[3]_i_1__26_n_0 ; wire \shadow[4]_i_1__26_n_0 ; wire \shadow[5]_i_1__26_n_0 ; wire \shadow[6]_i_1__26_n_0 ; wire \shadow[7]_i_1__26_n_0 ; wire \shadow[8]_i_1__26_n_0 ; wire \shadow[9]_i_1__26_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__26_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5135]_25 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__26 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__26 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__26 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__26 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__26 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__26 (.I0(\current_state[3]_i_4__26_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__26_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__26_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__26 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__26_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__26 (.I0(current_state[1]), .I1(\current_state[3]_i_2__26_n_0 ), .I2(\current_state[3]_i_4__26_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__26 (.I0(\current_state[3]_i_2__26_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__26_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__26_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__26 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__26_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__26 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[2]), .I3(s_daddr_o[3]), .I4(s_den_o), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__26_n_0 )); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__26 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__26_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__26 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__26_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__26_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [1]), .Q(\slaveRegDo_tcConfig[5135]_25 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [11]), .Q(\slaveRegDo_tcConfig[5135]_25 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [12]), .Q(\slaveRegDo_tcConfig[5135]_25 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [13]), .Q(\slaveRegDo_tcConfig[5135]_25 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [14]), .Q(\slaveRegDo_tcConfig[5135]_25 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [15]), .Q(\slaveRegDo_tcConfig[5135]_25 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5135]_25 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [2]), .Q(\slaveRegDo_tcConfig[5135]_25 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [3]), .Q(\slaveRegDo_tcConfig[5135]_25 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [4]), .Q(\slaveRegDo_tcConfig[5135]_25 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [5]), .Q(\slaveRegDo_tcConfig[5135]_25 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [6]), .Q(\slaveRegDo_tcConfig[5135]_25 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [7]), .Q(\slaveRegDo_tcConfig[5135]_25 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [8]), .Q(\slaveRegDo_tcConfig[5135]_25 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [9]), .Q(\slaveRegDo_tcConfig[5135]_25 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5135]_25 [10]), .Q(\slaveRegDo_tcConfig[5135]_25 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__26 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__26 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__26 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__26 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__26 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__26 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__26_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__26 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__26 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__26 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__26 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__26 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__26 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__26 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__26 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__26 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__26_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__26 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__26_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__26_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__26 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__26_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__26_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_11 (.I0(\slaveRegDo_tcConfig[5135]_25 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__25 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,447
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__27_n_0 ; wire \current_state[3]_i_3__27_n_0 ; wire \current_state[3]_i_4__27_n_0 ; wire data_out_sel; wire data_out_sel_i_1__27_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__27_n_0 ; wire \shadow[10]_i_1__27_n_0 ; wire \shadow[11]_i_1__27_n_0 ; wire \shadow[12]_i_1__27_n_0 ; wire \shadow[13]_i_1__27_n_0 ; wire \shadow[14]_i_1__27_n_0 ; wire \shadow[15]_i_1__27_n_0 ; wire \shadow[1]_i_1__27_n_0 ; wire \shadow[2]_i_1__27_n_0 ; wire \shadow[3]_i_1__27_n_0 ; wire \shadow[4]_i_1__27_n_0 ; wire \shadow[5]_i_1__27_n_0 ; wire \shadow[6]_i_1__27_n_0 ; wire \shadow[7]_i_1__27_n_0 ; wire \shadow[8]_i_1__27_n_0 ; wire \shadow[9]_i_1__27_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__27_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__27 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__27 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__27 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__27 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__27 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__27 (.I0(\current_state[3]_i_4__27_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__27_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__27_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__27 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__27_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__27 (.I0(current_state[1]), .I1(\current_state[3]_i_2__27_n_0 ), .I2(\current_state[3]_i_4__27_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__27 (.I0(\current_state[3]_i_2__27_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__27_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__27_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__27 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__27 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__27_n_0 )); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__27 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__27_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__27 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__27_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__27_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__27 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__27 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__27 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__27 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__27 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__27 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__27_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__27 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__27 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__27 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__27 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__27 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__27 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__27 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__27 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__27 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__27 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__27_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__27 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__27_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__27_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__26 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__27_n_0 ; wire \current_state[3]_i_3__27_n_0 ; wire \current_state[3]_i_4__27_n_0 ; wire data_out_sel; wire data_out_sel_i_1__27_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__27_n_0 ; wire \shadow[10]_i_1__27_n_0 ; wire \shadow[11]_i_1__27_n_0 ; wire \shadow[12]_i_1__27_n_0 ; wire \shadow[13]_i_1__27_n_0 ; wire \shadow[14]_i_1__27_n_0 ; wire \shadow[15]_i_1__27_n_0 ; wire \shadow[1]_i_1__27_n_0 ; wire \shadow[2]_i_1__27_n_0 ; wire \shadow[3]_i_1__27_n_0 ; wire \shadow[4]_i_1__27_n_0 ; wire \shadow[5]_i_1__27_n_0 ; wire \shadow[6]_i_1__27_n_0 ; wire \shadow[7]_i_1__27_n_0 ; wire \shadow[8]_i_1__27_n_0 ; wire \shadow[9]_i_1__27_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__27_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__27 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__27 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__27 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__27 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__27 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__27 (.I0(\current_state[3]_i_4__27_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__27_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__27_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__27 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__27_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__27 (.I0(current_state[1]), .I1(\current_state[3]_i_2__27_n_0 ), .I2(\current_state[3]_i_4__27_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__27 (.I0(\current_state[3]_i_2__27_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__27_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__27_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__27 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__27_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__27 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__27_n_0 )); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__27 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__27_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__27 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__27_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__27_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__27 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__27 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__27 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__27 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__27 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__27 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__27_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__27 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__27 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__27 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__27 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__27 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__27 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__27 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__27 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__27 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__27_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__27 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__27_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__27_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__27 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__27_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__27_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__26 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,448
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__28_n_0 ; wire \current_state[3]_i_3__28_n_0 ; wire \current_state[3]_i_4__28_n_0 ; wire data_out_sel; wire data_out_sel_i_1__28_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__28_n_0 ; wire \shadow[10]_i_1__28_n_0 ; wire \shadow[11]_i_1__28_n_0 ; wire \shadow[12]_i_1__28_n_0 ; wire \shadow[13]_i_1__28_n_0 ; wire \shadow[14]_i_1__28_n_0 ; wire \shadow[15]_i_1__28_n_0 ; wire \shadow[1]_i_1__28_n_0 ; wire \shadow[2]_i_1__28_n_0 ; wire \shadow[3]_i_1__28_n_0 ; wire \shadow[4]_i_1__28_n_0 ; wire \shadow[5]_i_1__28_n_0 ; wire \shadow[6]_i_1__28_n_0 ; wire \shadow[7]_i_1__28_n_0 ; wire \shadow[8]_i_1__28_n_0 ; wire \shadow[9]_i_1__28_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__28_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__28 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__28 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__28 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__28 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__28 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__28 (.I0(\current_state[3]_i_4__28_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__28_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__28_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__28 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__28_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__28 (.I0(current_state[1]), .I1(\current_state[3]_i_2__28_n_0 ), .I2(\current_state[3]_i_4__28_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__28 (.I0(\current_state[3]_i_2__28_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__28_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__28_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__28 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__28_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__28 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__28_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__28 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__28_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__28 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__28_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__28_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__28 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__28 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__28 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__28 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__28 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__28 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__28_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__28 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__28 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__28 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__28 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__28 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__28 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__28 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__28 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__28 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__28 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__28_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__28 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__28_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__28_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__27 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__28_n_0 ; wire \current_state[3]_i_3__28_n_0 ; wire \current_state[3]_i_4__28_n_0 ; wire data_out_sel; wire data_out_sel_i_1__28_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__28_n_0 ; wire \shadow[10]_i_1__28_n_0 ; wire \shadow[11]_i_1__28_n_0 ; wire \shadow[12]_i_1__28_n_0 ; wire \shadow[13]_i_1__28_n_0 ; wire \shadow[14]_i_1__28_n_0 ; wire \shadow[15]_i_1__28_n_0 ; wire \shadow[1]_i_1__28_n_0 ; wire \shadow[2]_i_1__28_n_0 ; wire \shadow[3]_i_1__28_n_0 ; wire \shadow[4]_i_1__28_n_0 ; wire \shadow[5]_i_1__28_n_0 ; wire \shadow[6]_i_1__28_n_0 ; wire \shadow[7]_i_1__28_n_0 ; wire \shadow[8]_i_1__28_n_0 ; wire \shadow[9]_i_1__28_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__28_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__28 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__28 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__28 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__28 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__28 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__28 (.I0(\current_state[3]_i_4__28_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__28_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__28_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__28 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__28_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__28 (.I0(current_state[1]), .I1(\current_state[3]_i_2__28_n_0 ), .I2(\current_state[3]_i_4__28_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__28 (.I0(\current_state[3]_i_2__28_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__28_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__28_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__28 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__28_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__28 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__28_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__28 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__28_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__28 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__28_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__28_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__28 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__28 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__28 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__28 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__28 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__28 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__28_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__28 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__28 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__28 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__28 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__28 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__28 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__28 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__28 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__28 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__28_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__28 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__28_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__28_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__28 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__28_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__28_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__27 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,449
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__29_n_0 ; wire \current_state[3]_i_3__29_n_0 ; wire \current_state[3]_i_4__29_n_0 ; wire data_out_sel; wire data_out_sel_i_1__29_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__29_n_0 ; wire \shadow[10]_i_1__29_n_0 ; wire \shadow[11]_i_1__29_n_0 ; wire \shadow[12]_i_1__29_n_0 ; wire \shadow[13]_i_1__29_n_0 ; wire \shadow[14]_i_1__29_n_0 ; wire \shadow[15]_i_1__29_n_0 ; wire \shadow[1]_i_1__29_n_0 ; wire \shadow[2]_i_1__29_n_0 ; wire \shadow[3]_i_1__29_n_0 ; wire \shadow[4]_i_1__29_n_0 ; wire \shadow[5]_i_1__29_n_0 ; wire \shadow[6]_i_1__29_n_0 ; wire \shadow[7]_i_1__29_n_0 ; wire \shadow[8]_i_1__29_n_0 ; wire \shadow[9]_i_1__29_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__29_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__29 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__29 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__29 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__29 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__29 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__29 (.I0(\current_state[3]_i_4__29_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__29_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__29_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__29 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__29_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__29 (.I0(current_state[1]), .I1(\current_state[3]_i_2__29_n_0 ), .I2(\current_state[3]_i_4__29_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__29 (.I0(\current_state[3]_i_2__29_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__29_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__29_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__29 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__29_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__29 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__29 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__29_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__29 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__29_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__29_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__29 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__29 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__29 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__29 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__29 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__29 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__29_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__29 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__29 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__29 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__29 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__29 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__29 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__29 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__29 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__29 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__29 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__29_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__29 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__29_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__29_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__28 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__29_n_0 ; wire \current_state[3]_i_3__29_n_0 ; wire \current_state[3]_i_4__29_n_0 ; wire data_out_sel; wire data_out_sel_i_1__29_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__29_n_0 ; wire \shadow[10]_i_1__29_n_0 ; wire \shadow[11]_i_1__29_n_0 ; wire \shadow[12]_i_1__29_n_0 ; wire \shadow[13]_i_1__29_n_0 ; wire \shadow[14]_i_1__29_n_0 ; wire \shadow[15]_i_1__29_n_0 ; wire \shadow[1]_i_1__29_n_0 ; wire \shadow[2]_i_1__29_n_0 ; wire \shadow[3]_i_1__29_n_0 ; wire \shadow[4]_i_1__29_n_0 ; wire \shadow[5]_i_1__29_n_0 ; wire \shadow[6]_i_1__29_n_0 ; wire \shadow[7]_i_1__29_n_0 ; wire \shadow[8]_i_1__29_n_0 ; wire \shadow[9]_i_1__29_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__29_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__29 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__29 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__29 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__29 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__29 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__29 (.I0(\current_state[3]_i_4__29_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__29_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__29_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__29 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__29_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__29 (.I0(current_state[1]), .I1(\current_state[3]_i_2__29_n_0 ), .I2(\current_state[3]_i_4__29_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__29 (.I0(\current_state[3]_i_2__29_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__29_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__29_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__29 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__29_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__29 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__29 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__29_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__29 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__29_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__29_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__29 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__29 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__29 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__29 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__29 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__29 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__29_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__29 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__29 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__29 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__29 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__29 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__29 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__29 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__29 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__29 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__29_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__29 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__29_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__29_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__29 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__29_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__29_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__28 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,450
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_daddr_o, \parallel_dout_reg[15]_0 , s_do_o, \parallel_dout_reg[15]_1 , \parallel_dout_reg[15]_2 , \parallel_dout_reg[14]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o); output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [5:0]s_daddr_o; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]\parallel_dout_reg[15]_2 ; input \parallel_dout_reg[14]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__30_n_0 ; wire \current_state[3]_i_3__30_n_0 ; wire \current_state[3]_i_4__30_n_0 ; wire data_out_sel; wire data_out_sel_i_1__30_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [15:0]\parallel_dout_reg[15]_2 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__30_n_0 ; wire \shadow[10]_i_1__30_n_0 ; wire \shadow[11]_i_1__30_n_0 ; wire \shadow[12]_i_1__30_n_0 ; wire \shadow[13]_i_1__30_n_0 ; wire \shadow[14]_i_1__30_n_0 ; wire \shadow[15]_i_1__30_n_0 ; wire \shadow[1]_i_1__30_n_0 ; wire \shadow[2]_i_1__30_n_0 ; wire \shadow[3]_i_1__30_n_0 ; wire \shadow[4]_i_1__30_n_0 ; wire \shadow[5]_i_1__30_n_0 ; wire \shadow[6]_i_1__30_n_0 ; wire \shadow[7]_i_1__30_n_0 ; wire \shadow[8]_i_1__30_n_0 ; wire \shadow[9]_i_1__30_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__30_n_0; wire \slaveRegDo_mux_5[0]_i_8_n_0 ; wire \slaveRegDo_mux_5[10]_i_8_n_0 ; wire \slaveRegDo_mux_5[11]_i_8_n_0 ; wire \slaveRegDo_mux_5[12]_i_8_n_0 ; wire \slaveRegDo_mux_5[13]_i_8_n_0 ; wire \slaveRegDo_mux_5[14]_i_8_n_0 ; wire \slaveRegDo_mux_5[15]_i_8_n_0 ; wire \slaveRegDo_mux_5[1]_i_8_n_0 ; wire \slaveRegDo_mux_5[2]_i_8_n_0 ; wire \slaveRegDo_mux_5[3]_i_8_n_0 ; wire \slaveRegDo_mux_5[4]_i_8_n_0 ; wire \slaveRegDo_mux_5[5]_i_8_n_0 ; wire \slaveRegDo_mux_5[6]_i_8_n_0 ; wire \slaveRegDo_mux_5[7]_i_8_n_0 ; wire \slaveRegDo_mux_5[8]_i_8_n_0 ; wire \slaveRegDo_mux_5[9]_i_8_n_0 ; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5139]_29 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__30 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__30 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__30 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__30 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__30 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__30 (.I0(\current_state[3]_i_4__30_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__30_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__30_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__30 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__30_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__30 (.I0(current_state[1]), .I1(\current_state[3]_i_2__30_n_0 ), .I2(\current_state[3]_i_4__30_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__30 (.I0(\current_state[3]_i_2__30_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__30_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__30_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__30 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__30 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__30 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__30_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__30 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__30_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__30_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [1]), .Q(\slaveRegDo_tcConfig[5139]_29 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [11]), .Q(\slaveRegDo_tcConfig[5139]_29 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [12]), .Q(\slaveRegDo_tcConfig[5139]_29 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [13]), .Q(\slaveRegDo_tcConfig[5139]_29 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [14]), .Q(\slaveRegDo_tcConfig[5139]_29 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [15]), .Q(\slaveRegDo_tcConfig[5139]_29 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5139]_29 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [2]), .Q(\slaveRegDo_tcConfig[5139]_29 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [3]), .Q(\slaveRegDo_tcConfig[5139]_29 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [4]), .Q(\slaveRegDo_tcConfig[5139]_29 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [5]), .Q(\slaveRegDo_tcConfig[5139]_29 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [6]), .Q(\slaveRegDo_tcConfig[5139]_29 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [7]), .Q(\slaveRegDo_tcConfig[5139]_29 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [8]), .Q(\slaveRegDo_tcConfig[5139]_29 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [9]), .Q(\slaveRegDo_tcConfig[5139]_29 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [10]), .Q(\slaveRegDo_tcConfig[5139]_29 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__30 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__30 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__30 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__30 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__30 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__30 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__30_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__30 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__30 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__30 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__30 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__30 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__30 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__30 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__30 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__30 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__30 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__30_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__30 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__30_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__30_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [0]), .O(\slaveRegDo_mux_5[0]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [10]), .O(\slaveRegDo_mux_5[10]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [11]), .O(\slaveRegDo_mux_5[11]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [12]), .O(\slaveRegDo_mux_5[12]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [13]), .O(\slaveRegDo_mux_5[13]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [14]), .O(\slaveRegDo_mux_5[14]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [15]), .O(\slaveRegDo_mux_5[15]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [1]), .O(\slaveRegDo_mux_5[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [2]), .O(\slaveRegDo_mux_5[2]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [3]), .O(\slaveRegDo_mux_5[3]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [4]), .O(\slaveRegDo_mux_5[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [5]), .O(\slaveRegDo_mux_5[5]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [6]), .O(\slaveRegDo_mux_5[6]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [7]), .O(\slaveRegDo_mux_5[7]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [8]), .O(\slaveRegDo_mux_5[8]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [9]), .O(\slaveRegDo_mux_5[9]_i_8_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_3 (.I0(\slaveRegDo_mux_5[0]_i_8_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_3 (.I0(\slaveRegDo_mux_5[10]_i_8_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_3 (.I0(\slaveRegDo_mux_5[11]_i_8_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_3 (.I0(\slaveRegDo_mux_5[12]_i_8_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_3 (.I0(\slaveRegDo_mux_5[13]_i_8_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_3 (.I0(\slaveRegDo_mux_5[14]_i_8_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_3 (.I0(\slaveRegDo_mux_5[15]_i_8_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_3 (.I0(\slaveRegDo_mux_5[1]_i_8_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_3 (.I0(\slaveRegDo_mux_5[2]_i_8_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_3 (.I0(\slaveRegDo_mux_5[3]_i_8_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_3 (.I0(\slaveRegDo_mux_5[4]_i_8_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_3 (.I0(\slaveRegDo_mux_5[5]_i_8_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_3 (.I0(\slaveRegDo_mux_5[6]_i_8_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_3 (.I0(\slaveRegDo_mux_5[7]_i_8_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_3 (.I0(\slaveRegDo_mux_5[8]_i_8_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_3 (.I0(\slaveRegDo_mux_5[9]_i_8_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9] ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__29 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_daddr_o, \parallel_dout_reg[15]_0 , s_do_o, \parallel_dout_reg[15]_1 , \parallel_dout_reg[15]_2 , \parallel_dout_reg[14]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o);
output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [5:0]s_daddr_o; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]\parallel_dout_reg[15]_2 ; input \parallel_dout_reg[14]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__30_n_0 ; wire \current_state[3]_i_3__30_n_0 ; wire \current_state[3]_i_4__30_n_0 ; wire data_out_sel; wire data_out_sel_i_1__30_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [15:0]\parallel_dout_reg[15]_2 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__30_n_0 ; wire \shadow[10]_i_1__30_n_0 ; wire \shadow[11]_i_1__30_n_0 ; wire \shadow[12]_i_1__30_n_0 ; wire \shadow[13]_i_1__30_n_0 ; wire \shadow[14]_i_1__30_n_0 ; wire \shadow[15]_i_1__30_n_0 ; wire \shadow[1]_i_1__30_n_0 ; wire \shadow[2]_i_1__30_n_0 ; wire \shadow[3]_i_1__30_n_0 ; wire \shadow[4]_i_1__30_n_0 ; wire \shadow[5]_i_1__30_n_0 ; wire \shadow[6]_i_1__30_n_0 ; wire \shadow[7]_i_1__30_n_0 ; wire \shadow[8]_i_1__30_n_0 ; wire \shadow[9]_i_1__30_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__30_n_0; wire \slaveRegDo_mux_5[0]_i_8_n_0 ; wire \slaveRegDo_mux_5[10]_i_8_n_0 ; wire \slaveRegDo_mux_5[11]_i_8_n_0 ; wire \slaveRegDo_mux_5[12]_i_8_n_0 ; wire \slaveRegDo_mux_5[13]_i_8_n_0 ; wire \slaveRegDo_mux_5[14]_i_8_n_0 ; wire \slaveRegDo_mux_5[15]_i_8_n_0 ; wire \slaveRegDo_mux_5[1]_i_8_n_0 ; wire \slaveRegDo_mux_5[2]_i_8_n_0 ; wire \slaveRegDo_mux_5[3]_i_8_n_0 ; wire \slaveRegDo_mux_5[4]_i_8_n_0 ; wire \slaveRegDo_mux_5[5]_i_8_n_0 ; wire \slaveRegDo_mux_5[6]_i_8_n_0 ; wire \slaveRegDo_mux_5[7]_i_8_n_0 ; wire \slaveRegDo_mux_5[8]_i_8_n_0 ; wire \slaveRegDo_mux_5[9]_i_8_n_0 ; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5139]_29 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__30 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__30 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__30 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__30 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__30 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__30 (.I0(\current_state[3]_i_4__30_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__30_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__30_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__30 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__30_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__30 (.I0(current_state[1]), .I1(\current_state[3]_i_2__30_n_0 ), .I2(\current_state[3]_i_4__30_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__30 (.I0(\current_state[3]_i_2__30_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__30_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__30_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__30 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \current_state[3]_i_3__30 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__30 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__30_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__30 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__30_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__30_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [1]), .Q(\slaveRegDo_tcConfig[5139]_29 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [11]), .Q(\slaveRegDo_tcConfig[5139]_29 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [12]), .Q(\slaveRegDo_tcConfig[5139]_29 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [13]), .Q(\slaveRegDo_tcConfig[5139]_29 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [14]), .Q(\slaveRegDo_tcConfig[5139]_29 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [15]), .Q(\slaveRegDo_tcConfig[5139]_29 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5139]_29 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [2]), .Q(\slaveRegDo_tcConfig[5139]_29 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [3]), .Q(\slaveRegDo_tcConfig[5139]_29 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [4]), .Q(\slaveRegDo_tcConfig[5139]_29 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [5]), .Q(\slaveRegDo_tcConfig[5139]_29 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [6]), .Q(\slaveRegDo_tcConfig[5139]_29 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [7]), .Q(\slaveRegDo_tcConfig[5139]_29 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [8]), .Q(\slaveRegDo_tcConfig[5139]_29 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [9]), .Q(\slaveRegDo_tcConfig[5139]_29 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5139]_29 [10]), .Q(\slaveRegDo_tcConfig[5139]_29 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__30 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__30 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__30 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__30 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__30 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__30 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__30_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__30 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__30 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__30 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__30 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__30 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__30 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__30 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__30 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__30 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__30_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__30 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__30_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__30_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__30 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__30_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__30_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [0]), .O(\slaveRegDo_mux_5[0]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [10]), .O(\slaveRegDo_mux_5[10]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [11]), .O(\slaveRegDo_mux_5[11]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [12]), .O(\slaveRegDo_mux_5[12]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [13]), .O(\slaveRegDo_mux_5[13]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [14]), .O(\slaveRegDo_mux_5[14]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [15]), .O(\slaveRegDo_mux_5[15]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [1]), .O(\slaveRegDo_mux_5[1]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [2]), .O(\slaveRegDo_mux_5[2]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [3]), .O(\slaveRegDo_mux_5[3]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [4]), .O(\slaveRegDo_mux_5[4]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [5]), .O(\slaveRegDo_mux_5[5]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [6]), .O(\slaveRegDo_mux_5[6]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [7]), .O(\slaveRegDo_mux_5[7]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [8]), .O(\slaveRegDo_mux_5[8]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_8 (.I0(\slaveRegDo_tcConfig[5139]_29 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [9]), .O(\slaveRegDo_mux_5[9]_i_8_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_3 (.I0(\slaveRegDo_mux_5[0]_i_8_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_3 (.I0(\slaveRegDo_mux_5[10]_i_8_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_3 (.I0(\slaveRegDo_mux_5[11]_i_8_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_3 (.I0(\slaveRegDo_mux_5[12]_i_8_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_3 (.I0(\slaveRegDo_mux_5[13]_i_8_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_3 (.I0(\slaveRegDo_mux_5[14]_i_8_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_3 (.I0(\slaveRegDo_mux_5[15]_i_8_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_3 (.I0(\slaveRegDo_mux_5[1]_i_8_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_3 (.I0(\slaveRegDo_mux_5[2]_i_8_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_3 (.I0(\slaveRegDo_mux_5[3]_i_8_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_3 (.I0(\slaveRegDo_mux_5[4]_i_8_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_3 (.I0(\slaveRegDo_mux_5[5]_i_8_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_3 (.I0(\slaveRegDo_mux_5[6]_i_8_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_3 (.I0(\slaveRegDo_mux_5[7]_i_8_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_3 (.I0(\slaveRegDo_mux_5[8]_i_8_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8] ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_3 (.I0(\slaveRegDo_mux_5[9]_i_8_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9] ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__29 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,451
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__31_n_0 ; wire \current_state[3]_i_3__31_n_0 ; wire \current_state[3]_i_4__31_n_0 ; wire data_out_sel; wire data_out_sel_i_1__31_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__31_n_0 ; wire \shadow[10]_i_1__31_n_0 ; wire \shadow[11]_i_1__31_n_0 ; wire \shadow[12]_i_1__31_n_0 ; wire \shadow[13]_i_1__31_n_0 ; wire \shadow[14]_i_1__31_n_0 ; wire \shadow[15]_i_1__31_n_0 ; wire \shadow[1]_i_1__31_n_0 ; wire \shadow[2]_i_1__31_n_0 ; wire \shadow[3]_i_1__31_n_0 ; wire \shadow[4]_i_1__31_n_0 ; wire \shadow[5]_i_1__31_n_0 ; wire \shadow[6]_i_1__31_n_0 ; wire \shadow[7]_i_1__31_n_0 ; wire \shadow[8]_i_1__31_n_0 ; wire \shadow[9]_i_1__31_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__31_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__31 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__31 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__31 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__31 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__31 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__31 (.I0(\current_state[3]_i_4__31_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__31_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__31_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__31 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__31_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__31 (.I0(current_state[1]), .I1(\current_state[3]_i_2__31_n_0 ), .I2(\current_state[3]_i_4__31_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__31 (.I0(\current_state[3]_i_2__31_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__31_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__31_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__31 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__31 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__31 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__31_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__31 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__31_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__31_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__31 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__31 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__31 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__31 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__31 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__31 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__31_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__31 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__31 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__31 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__31 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__31 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__31 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__31 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__31 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__31 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__31 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__31_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__31 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__31_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__31_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__30 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__31_n_0 ; wire \current_state[3]_i_3__31_n_0 ; wire \current_state[3]_i_4__31_n_0 ; wire data_out_sel; wire data_out_sel_i_1__31_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__31_n_0 ; wire \shadow[10]_i_1__31_n_0 ; wire \shadow[11]_i_1__31_n_0 ; wire \shadow[12]_i_1__31_n_0 ; wire \shadow[13]_i_1__31_n_0 ; wire \shadow[14]_i_1__31_n_0 ; wire \shadow[15]_i_1__31_n_0 ; wire \shadow[1]_i_1__31_n_0 ; wire \shadow[2]_i_1__31_n_0 ; wire \shadow[3]_i_1__31_n_0 ; wire \shadow[4]_i_1__31_n_0 ; wire \shadow[5]_i_1__31_n_0 ; wire \shadow[6]_i_1__31_n_0 ; wire \shadow[7]_i_1__31_n_0 ; wire \shadow[8]_i_1__31_n_0 ; wire \shadow[9]_i_1__31_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__31_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__31 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__31 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__31 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__31 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__31 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__31 (.I0(\current_state[3]_i_4__31_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__31_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__31_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__31 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__31_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__31 (.I0(current_state[1]), .I1(\current_state[3]_i_2__31_n_0 ), .I2(\current_state[3]_i_4__31_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__31 (.I0(\current_state[3]_i_2__31_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__31_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__31_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__31 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__31_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__31 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__31 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__31_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__31 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__31_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__31_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__31 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__31 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__31 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__31 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__31 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__31 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__31_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__31 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__31 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__31 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__31 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__31 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__31 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__31 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__31 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__31 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__31_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__31 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__31_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__31_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__31 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__31_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__31_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__30 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,452
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__5_n_0 ; wire \current_state[3]_i_3__5_n_0 ; wire \current_state[3]_i_4__5_n_0 ; wire data_out_sel; wire data_out_sel_i_1__5_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__5_n_0 ; wire \shadow[10]_i_1__5_n_0 ; wire \shadow[11]_i_1__5_n_0 ; wire \shadow[12]_i_1__5_n_0 ; wire \shadow[13]_i_1__5_n_0 ; wire \shadow[14]_i_1__5_n_0 ; wire \shadow[15]_i_1__5_n_0 ; wire \shadow[1]_i_1__5_n_0 ; wire \shadow[2]_i_1__5_n_0 ; wire \shadow[3]_i_1__5_n_0 ; wire \shadow[4]_i_1__5_n_0 ; wire \shadow[5]_i_1__5_n_0 ; wire \shadow[6]_i_1__5_n_0 ; wire \shadow[7]_i_1__5_n_0 ; wire \shadow[8]_i_1__5_n_0 ; wire \shadow[9]_i_1__5_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__5_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__5 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__5 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__5 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__5 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__5 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__5 (.I0(\current_state[3]_i_4__5_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__5_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__5_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__5 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__5_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__5_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__5 (.I0(current_state[1]), .I1(\current_state[3]_i_2__5_n_0 ), .I2(\current_state[3]_i_4__5_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__5 (.I0(\current_state[3]_i_2__5_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__5_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__5_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__5 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__5_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3__5 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3__5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__5 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__5_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__5 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__5_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__5_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__5 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__5 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__5 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__5 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__5 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__5 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__5_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__5 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__5 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__5 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__5 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__5 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__5 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__5 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__5 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__5 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__5 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__5_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__5 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__5_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__5_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__4 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__5_n_0 ; wire \current_state[3]_i_3__5_n_0 ; wire \current_state[3]_i_4__5_n_0 ; wire data_out_sel; wire data_out_sel_i_1__5_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__5_n_0 ; wire \shadow[10]_i_1__5_n_0 ; wire \shadow[11]_i_1__5_n_0 ; wire \shadow[12]_i_1__5_n_0 ; wire \shadow[13]_i_1__5_n_0 ; wire \shadow[14]_i_1__5_n_0 ; wire \shadow[15]_i_1__5_n_0 ; wire \shadow[1]_i_1__5_n_0 ; wire \shadow[2]_i_1__5_n_0 ; wire \shadow[3]_i_1__5_n_0 ; wire \shadow[4]_i_1__5_n_0 ; wire \shadow[5]_i_1__5_n_0 ; wire \shadow[6]_i_1__5_n_0 ; wire \shadow[7]_i_1__5_n_0 ; wire \shadow[8]_i_1__5_n_0 ; wire \shadow[9]_i_1__5_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__5_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__5 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__5 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__5 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__5 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__5 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__5 (.I0(\current_state[3]_i_4__5_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__5_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__5_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__5 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__5_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__5_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__5 (.I0(current_state[1]), .I1(\current_state[3]_i_2__5_n_0 ), .I2(\current_state[3]_i_4__5_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__5 (.I0(\current_state[3]_i_2__5_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__5_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__5_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__5 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__5_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3__5 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3__5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__5 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__5_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__5 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__5_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__5_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__5 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__5 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__5 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__5 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__5 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__5 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__5_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__5 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__5 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__5 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__5 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__5 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__5 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__5 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__5 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__5 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__5_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__5 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__5_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__5_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__5 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__5_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__5_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__4 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,453
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
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['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__32_n_0 ; wire \current_state[3]_i_3__32_n_0 ; wire \current_state[3]_i_4__32_n_0 ; wire data_out_sel; wire data_out_sel_i_1__32_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__32_n_0 ; wire \shadow[10]_i_1__32_n_0 ; wire \shadow[11]_i_1__32_n_0 ; wire \shadow[12]_i_1__32_n_0 ; wire \shadow[13]_i_1__32_n_0 ; wire \shadow[14]_i_1__32_n_0 ; wire \shadow[15]_i_1__32_n_0 ; wire \shadow[1]_i_1__32_n_0 ; wire \shadow[2]_i_1__32_n_0 ; wire \shadow[3]_i_1__32_n_0 ; wire \shadow[4]_i_1__32_n_0 ; wire \shadow[5]_i_1__32_n_0 ; wire \shadow[6]_i_1__32_n_0 ; wire \shadow[7]_i_1__32_n_0 ; wire \shadow[8]_i_1__32_n_0 ; wire \shadow[9]_i_1__32_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__32_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__32 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__32 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__32 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__32 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__32 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__32 (.I0(\current_state[3]_i_4__32_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__32_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__32_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__32 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__32_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__32 (.I0(current_state[1]), .I1(\current_state[3]_i_2__32_n_0 ), .I2(\current_state[3]_i_4__32_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__32 (.I0(\current_state[3]_i_2__32_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__32_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__32_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__32 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__32_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__32 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__32 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__32_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__32 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__32_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__32_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__32 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__32 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__32 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__32 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__32 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__32 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__32_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__32 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__32 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__32 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__32 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__32 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__32 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__32 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__32 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__32 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__32 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__32_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__32 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__32_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__32_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__31 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__32_n_0 ; wire \current_state[3]_i_3__32_n_0 ; wire \current_state[3]_i_4__32_n_0 ; wire data_out_sel; wire data_out_sel_i_1__32_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__32_n_0 ; wire \shadow[10]_i_1__32_n_0 ; wire \shadow[11]_i_1__32_n_0 ; wire \shadow[12]_i_1__32_n_0 ; wire \shadow[13]_i_1__32_n_0 ; wire \shadow[14]_i_1__32_n_0 ; wire \shadow[15]_i_1__32_n_0 ; wire \shadow[1]_i_1__32_n_0 ; wire \shadow[2]_i_1__32_n_0 ; wire \shadow[3]_i_1__32_n_0 ; wire \shadow[4]_i_1__32_n_0 ; wire \shadow[5]_i_1__32_n_0 ; wire \shadow[6]_i_1__32_n_0 ; wire \shadow[7]_i_1__32_n_0 ; wire \shadow[8]_i_1__32_n_0 ; wire \shadow[9]_i_1__32_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__32_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__32 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__32 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__32 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__32 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__32 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__32 (.I0(\current_state[3]_i_4__32_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__32_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__32_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__32 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__32_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__32 (.I0(current_state[1]), .I1(\current_state[3]_i_2__32_n_0 ), .I2(\current_state[3]_i_4__32_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__32 (.I0(\current_state[3]_i_2__32_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__32_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__32_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__32 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__32_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__32 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__32_n_0 )); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__32 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__32_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__32 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__32_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__32_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__32 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__32 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__32 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__32 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__32 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__32 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__32_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__32 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__32 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__32 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__32 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__32 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__32 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__32 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__32 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__32 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__32_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__32 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__32_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__32_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__32 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__32_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__32_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__31 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,454
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__33_n_0 ; wire \current_state[3]_i_3__33_n_0 ; wire \current_state[3]_i_4__33_n_0 ; wire data_out_sel; wire data_out_sel_i_1__33_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__33_n_0 ; wire \shadow[10]_i_1__33_n_0 ; wire \shadow[11]_i_1__33_n_0 ; wire \shadow[12]_i_1__33_n_0 ; wire \shadow[13]_i_1__33_n_0 ; wire \shadow[14]_i_1__33_n_0 ; wire \shadow[15]_i_1__33_n_0 ; wire \shadow[1]_i_1__33_n_0 ; wire \shadow[2]_i_1__33_n_0 ; wire \shadow[3]_i_1__33_n_0 ; wire \shadow[4]_i_1__33_n_0 ; wire \shadow[5]_i_1__33_n_0 ; wire \shadow[6]_i_1__33_n_0 ; wire \shadow[7]_i_1__33_n_0 ; wire \shadow[8]_i_1__33_n_0 ; wire \shadow[9]_i_1__33_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__33_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__33 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__33 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__33 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__33 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__33 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__33 (.I0(\current_state[3]_i_4__33_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__33_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__33_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__33 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__33_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__33 (.I0(current_state[1]), .I1(\current_state[3]_i_2__33_n_0 ), .I2(\current_state[3]_i_4__33_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__33 (.I0(\current_state[3]_i_2__33_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__33_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__33_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__33 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__33 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__33 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__33_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__33 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__33_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__33_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__33 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__33 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__33 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__33 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__33 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__33 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__33_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__33 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__33 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__33 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__33 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__33 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__33 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__33 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__33 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__33 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__33 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__33_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__33 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__33_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__33_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__32 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__33_n_0 ; wire \current_state[3]_i_3__33_n_0 ; wire \current_state[3]_i_4__33_n_0 ; wire data_out_sel; wire data_out_sel_i_1__33_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__33_n_0 ; wire \shadow[10]_i_1__33_n_0 ; wire \shadow[11]_i_1__33_n_0 ; wire \shadow[12]_i_1__33_n_0 ; wire \shadow[13]_i_1__33_n_0 ; wire \shadow[14]_i_1__33_n_0 ; wire \shadow[15]_i_1__33_n_0 ; wire \shadow[1]_i_1__33_n_0 ; wire \shadow[2]_i_1__33_n_0 ; wire \shadow[3]_i_1__33_n_0 ; wire \shadow[4]_i_1__33_n_0 ; wire \shadow[5]_i_1__33_n_0 ; wire \shadow[6]_i_1__33_n_0 ; wire \shadow[7]_i_1__33_n_0 ; wire \shadow[8]_i_1__33_n_0 ; wire \shadow[9]_i_1__33_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__33_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__33 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__33 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__33 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__33 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__33 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__33 (.I0(\current_state[3]_i_4__33_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__33_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__33_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__33 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__33_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__33 (.I0(current_state[1]), .I1(\current_state[3]_i_2__33_n_0 ), .I2(\current_state[3]_i_4__33_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__33 (.I0(\current_state[3]_i_2__33_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__33_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__33_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__33 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__33 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__33 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__33_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__33 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__33_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__33_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__33 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__33 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__33 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__33 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__33 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__33 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__33_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__33 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__33 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__33 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__33 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__33 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__33 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__33 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__33 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__33 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__33_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__33 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__33_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__33_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__33 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__33_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__33_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__32 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,455
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o); output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [5:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__34_n_0 ; wire \current_state[3]_i_3__34_n_0 ; wire \current_state[3]_i_4__34_n_0 ; wire data_out_sel; wire data_out_sel_i_1__34_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__34_n_0 ; wire \shadow[10]_i_1__34_n_0 ; wire \shadow[11]_i_1__34_n_0 ; wire \shadow[12]_i_1__34_n_0 ; wire \shadow[13]_i_1__34_n_0 ; wire \shadow[14]_i_1__34_n_0 ; wire \shadow[15]_i_1__34_n_0 ; wire \shadow[1]_i_1__34_n_0 ; wire \shadow[2]_i_1__34_n_0 ; wire \shadow[3]_i_1__34_n_0 ; wire \shadow[4]_i_1__34_n_0 ; wire \shadow[5]_i_1__34_n_0 ; wire \shadow[6]_i_1__34_n_0 ; wire \shadow[7]_i_1__34_n_0 ; wire \shadow[8]_i_1__34_n_0 ; wire \shadow[9]_i_1__34_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__34_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5143]_33 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__34 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__34 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__34 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__34 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__34 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__34 (.I0(\current_state[3]_i_4__34_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__34_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__34_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__34 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__34_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__34 (.I0(current_state[1]), .I1(\current_state[3]_i_2__34_n_0 ), .I2(\current_state[3]_i_4__34_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__34 (.I0(\current_state[3]_i_2__34_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__34_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__34_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__34 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__34_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__34 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__34 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__34_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__34 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__34_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__34_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [1]), .Q(\slaveRegDo_tcConfig[5143]_33 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [11]), .Q(\slaveRegDo_tcConfig[5143]_33 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [12]), .Q(\slaveRegDo_tcConfig[5143]_33 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [13]), .Q(\slaveRegDo_tcConfig[5143]_33 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [14]), .Q(\slaveRegDo_tcConfig[5143]_33 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [15]), .Q(\slaveRegDo_tcConfig[5143]_33 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5143]_33 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [2]), .Q(\slaveRegDo_tcConfig[5143]_33 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [3]), .Q(\slaveRegDo_tcConfig[5143]_33 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [4]), .Q(\slaveRegDo_tcConfig[5143]_33 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [5]), .Q(\slaveRegDo_tcConfig[5143]_33 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [6]), .Q(\slaveRegDo_tcConfig[5143]_33 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [7]), .Q(\slaveRegDo_tcConfig[5143]_33 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [8]), .Q(\slaveRegDo_tcConfig[5143]_33 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [9]), .Q(\slaveRegDo_tcConfig[5143]_33 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [10]), .Q(\slaveRegDo_tcConfig[5143]_33 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__34 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__34 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__34 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__34 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__34 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__34 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__34_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__34 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__34 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__34 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__34 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__34 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__34 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__34 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__34 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__34 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__34 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__34_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__34 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__34_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__34_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__33 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o);
output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [5:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__34_n_0 ; wire \current_state[3]_i_3__34_n_0 ; wire \current_state[3]_i_4__34_n_0 ; wire data_out_sel; wire data_out_sel_i_1__34_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__34_n_0 ; wire \shadow[10]_i_1__34_n_0 ; wire \shadow[11]_i_1__34_n_0 ; wire \shadow[12]_i_1__34_n_0 ; wire \shadow[13]_i_1__34_n_0 ; wire \shadow[14]_i_1__34_n_0 ; wire \shadow[15]_i_1__34_n_0 ; wire \shadow[1]_i_1__34_n_0 ; wire \shadow[2]_i_1__34_n_0 ; wire \shadow[3]_i_1__34_n_0 ; wire \shadow[4]_i_1__34_n_0 ; wire \shadow[5]_i_1__34_n_0 ; wire \shadow[6]_i_1__34_n_0 ; wire \shadow[7]_i_1__34_n_0 ; wire \shadow[8]_i_1__34_n_0 ; wire \shadow[9]_i_1__34_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__34_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5143]_33 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__34 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__34 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__34 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__34 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__34 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__34 (.I0(\current_state[3]_i_4__34_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__34_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__34_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__34 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__34_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__34 (.I0(current_state[1]), .I1(\current_state[3]_i_2__34_n_0 ), .I2(\current_state[3]_i_4__34_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__34 (.I0(\current_state[3]_i_2__34_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__34_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__34_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__34 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__34_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__34 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__34_n_0 )); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__34 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__34_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__34 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__34_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__34_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [1]), .Q(\slaveRegDo_tcConfig[5143]_33 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [11]), .Q(\slaveRegDo_tcConfig[5143]_33 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [12]), .Q(\slaveRegDo_tcConfig[5143]_33 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [13]), .Q(\slaveRegDo_tcConfig[5143]_33 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [14]), .Q(\slaveRegDo_tcConfig[5143]_33 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [15]), .Q(\slaveRegDo_tcConfig[5143]_33 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5143]_33 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [2]), .Q(\slaveRegDo_tcConfig[5143]_33 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [3]), .Q(\slaveRegDo_tcConfig[5143]_33 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [4]), .Q(\slaveRegDo_tcConfig[5143]_33 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [5]), .Q(\slaveRegDo_tcConfig[5143]_33 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [6]), .Q(\slaveRegDo_tcConfig[5143]_33 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [7]), .Q(\slaveRegDo_tcConfig[5143]_33 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [8]), .Q(\slaveRegDo_tcConfig[5143]_33 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [9]), .Q(\slaveRegDo_tcConfig[5143]_33 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5143]_33 [10]), .Q(\slaveRegDo_tcConfig[5143]_33 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__34 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__34 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__34 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__34 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__34 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__34 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__34_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__34 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__34 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__34 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__34 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__34 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__34 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__34 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__34 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__34 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__34_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__34 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__34_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__34_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__34 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__34_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__34_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_9 (.I0(\slaveRegDo_tcConfig[5143]_33 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__33 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,456
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__35_n_0 ; wire \current_state[3]_i_3__35_n_0 ; wire \current_state[3]_i_4__35_n_0 ; wire data_out_sel; wire data_out_sel_i_1__35_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__35_n_0 ; wire \shadow[10]_i_1__35_n_0 ; wire \shadow[11]_i_1__35_n_0 ; wire \shadow[12]_i_1__35_n_0 ; wire \shadow[13]_i_1__35_n_0 ; wire \shadow[14]_i_1__35_n_0 ; wire \shadow[15]_i_1__35_n_0 ; wire \shadow[1]_i_1__35_n_0 ; wire \shadow[2]_i_1__35_n_0 ; wire \shadow[3]_i_1__35_n_0 ; wire \shadow[4]_i_1__35_n_0 ; wire \shadow[5]_i_1__35_n_0 ; wire \shadow[6]_i_1__35_n_0 ; wire \shadow[7]_i_1__35_n_0 ; wire \shadow[8]_i_1__35_n_0 ; wire \shadow[9]_i_1__35_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__35_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__35 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__35 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__35 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__35 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__35 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__35 (.I0(\current_state[3]_i_4__35_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__35_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__35_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__35 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__35_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__35 (.I0(current_state[1]), .I1(\current_state[3]_i_2__35_n_0 ), .I2(\current_state[3]_i_4__35_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__35 (.I0(\current_state[3]_i_2__35_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__35_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__35_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__35 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__35 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__35 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__35_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__35 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__35_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__35_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__35 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__35 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__35 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__35 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__35 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__35 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__35_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__35 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__35 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__35 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__35 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__35 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__35 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__35 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__35 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__35 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__35 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__35_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__35 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__35_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__35_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__34 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__35_n_0 ; wire \current_state[3]_i_3__35_n_0 ; wire \current_state[3]_i_4__35_n_0 ; wire data_out_sel; wire data_out_sel_i_1__35_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__35_n_0 ; wire \shadow[10]_i_1__35_n_0 ; wire \shadow[11]_i_1__35_n_0 ; wire \shadow[12]_i_1__35_n_0 ; wire \shadow[13]_i_1__35_n_0 ; wire \shadow[14]_i_1__35_n_0 ; wire \shadow[15]_i_1__35_n_0 ; wire \shadow[1]_i_1__35_n_0 ; wire \shadow[2]_i_1__35_n_0 ; wire \shadow[3]_i_1__35_n_0 ; wire \shadow[4]_i_1__35_n_0 ; wire \shadow[5]_i_1__35_n_0 ; wire \shadow[6]_i_1__35_n_0 ; wire \shadow[7]_i_1__35_n_0 ; wire \shadow[8]_i_1__35_n_0 ; wire \shadow[9]_i_1__35_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__35_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__35 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__35 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__35 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__35 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__35 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__35 (.I0(\current_state[3]_i_4__35_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__35_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__35_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__35 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__35_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__35 (.I0(current_state[1]), .I1(\current_state[3]_i_2__35_n_0 ), .I2(\current_state[3]_i_4__35_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__35 (.I0(\current_state[3]_i_2__35_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__35_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__35_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__35 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__35_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__35 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__35_n_0 )); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__35 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__35_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__35 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__35_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__35_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__35 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__35 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__35 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__35 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__35 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__35 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__35_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__35 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__35 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__35 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__35 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__35 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__35 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__35 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__35 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__35 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__35_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__35 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__35_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__35_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__35 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__35_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__35_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__34 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,457
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__36_n_0 ; wire \current_state[3]_i_3__36_n_0 ; wire \current_state[3]_i_4__36_n_0 ; wire data_out_sel; wire data_out_sel_i_1__36_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__36_n_0 ; wire \shadow[10]_i_1__36_n_0 ; wire \shadow[11]_i_1__36_n_0 ; wire \shadow[12]_i_1__36_n_0 ; wire \shadow[13]_i_1__36_n_0 ; wire \shadow[14]_i_1__36_n_0 ; wire \shadow[15]_i_1__36_n_0 ; wire \shadow[1]_i_1__36_n_0 ; wire \shadow[2]_i_1__36_n_0 ; wire \shadow[3]_i_1__36_n_0 ; wire \shadow[4]_i_1__36_n_0 ; wire \shadow[5]_i_1__36_n_0 ; wire \shadow[6]_i_1__36_n_0 ; wire \shadow[7]_i_1__36_n_0 ; wire \shadow[8]_i_1__36_n_0 ; wire \shadow[9]_i_1__36_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__36_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__36 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__36 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__36 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__36 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__36 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__36 (.I0(\current_state[3]_i_4__36_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__36_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__36_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__36 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__36_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__36 (.I0(current_state[1]), .I1(\current_state[3]_i_2__36_n_0 ), .I2(\current_state[3]_i_4__36_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__36 (.I0(\current_state[3]_i_2__36_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__36_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__36_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__36 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__36_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__36 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__36 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__36_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__36 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__36_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__36_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__36 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__36 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__36 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__36 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__36 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__36 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__36_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__36 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__36 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__36 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__36 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__36 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__36 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__36 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__36 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__36 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__36 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__36_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__36 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__36_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__36_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__35 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__36_n_0 ; wire \current_state[3]_i_3__36_n_0 ; wire \current_state[3]_i_4__36_n_0 ; wire data_out_sel; wire data_out_sel_i_1__36_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__36_n_0 ; wire \shadow[10]_i_1__36_n_0 ; wire \shadow[11]_i_1__36_n_0 ; wire \shadow[12]_i_1__36_n_0 ; wire \shadow[13]_i_1__36_n_0 ; wire \shadow[14]_i_1__36_n_0 ; wire \shadow[15]_i_1__36_n_0 ; wire \shadow[1]_i_1__36_n_0 ; wire \shadow[2]_i_1__36_n_0 ; wire \shadow[3]_i_1__36_n_0 ; wire \shadow[4]_i_1__36_n_0 ; wire \shadow[5]_i_1__36_n_0 ; wire \shadow[6]_i_1__36_n_0 ; wire \shadow[7]_i_1__36_n_0 ; wire \shadow[8]_i_1__36_n_0 ; wire \shadow[9]_i_1__36_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__36_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__36 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__36 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__36 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__36 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__36 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__36 (.I0(\current_state[3]_i_4__36_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__36_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__36_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__36 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__36_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__36 (.I0(current_state[1]), .I1(\current_state[3]_i_2__36_n_0 ), .I2(\current_state[3]_i_4__36_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__36 (.I0(\current_state[3]_i_2__36_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__36_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__36_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__36 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__36_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__36 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__36_n_0 )); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__36 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__36_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__36 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__36_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__36_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__36 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__36 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__36 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__36 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__36 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__36 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__36_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__36 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__36 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__36 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__36 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__36 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__36 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__36 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__36 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__36 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__36_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__36 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__36_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__36_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__36 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__36_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__36_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__35 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,458
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__37_n_0 ; wire \current_state[3]_i_3__37_n_0 ; wire \current_state[3]_i_4__37_n_0 ; wire data_out_sel; wire data_out_sel_i_1__37_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__37_n_0 ; wire \shadow[10]_i_1__37_n_0 ; wire \shadow[11]_i_1__37_n_0 ; wire \shadow[12]_i_1__37_n_0 ; wire \shadow[13]_i_1__37_n_0 ; wire \shadow[14]_i_1__37_n_0 ; wire \shadow[15]_i_1__37_n_0 ; wire \shadow[1]_i_1__37_n_0 ; wire \shadow[2]_i_1__37_n_0 ; wire \shadow[3]_i_1__37_n_0 ; wire \shadow[4]_i_1__37_n_0 ; wire \shadow[5]_i_1__37_n_0 ; wire \shadow[6]_i_1__37_n_0 ; wire \shadow[7]_i_1__37_n_0 ; wire \shadow[8]_i_1__37_n_0 ; wire \shadow[9]_i_1__37_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__37_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__37 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__37 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__37 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__37 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__37 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__37 (.I0(\current_state[3]_i_4__37_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__37_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__37_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__37 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__37_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__37 (.I0(current_state[1]), .I1(\current_state[3]_i_2__37_n_0 ), .I2(\current_state[3]_i_4__37_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__37 (.I0(\current_state[3]_i_2__37_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__37_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__37_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__37 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__37 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__37_n_0 )); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__37 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__37_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__37 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__37_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__37_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__37 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__37 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__37 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__37 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__37 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__37 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__37_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__37 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__37 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__37 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__37 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__37 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__37 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__37 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__37 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__37 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__37 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__37_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__37 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__37_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__37_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__36 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__37_n_0 ; wire \current_state[3]_i_3__37_n_0 ; wire \current_state[3]_i_4__37_n_0 ; wire data_out_sel; wire data_out_sel_i_1__37_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__37_n_0 ; wire \shadow[10]_i_1__37_n_0 ; wire \shadow[11]_i_1__37_n_0 ; wire \shadow[12]_i_1__37_n_0 ; wire \shadow[13]_i_1__37_n_0 ; wire \shadow[14]_i_1__37_n_0 ; wire \shadow[15]_i_1__37_n_0 ; wire \shadow[1]_i_1__37_n_0 ; wire \shadow[2]_i_1__37_n_0 ; wire \shadow[3]_i_1__37_n_0 ; wire \shadow[4]_i_1__37_n_0 ; wire \shadow[5]_i_1__37_n_0 ; wire \shadow[6]_i_1__37_n_0 ; wire \shadow[7]_i_1__37_n_0 ; wire \shadow[8]_i_1__37_n_0 ; wire \shadow[9]_i_1__37_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__37_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__37 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__37 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__37 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__37 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__37 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__37 (.I0(\current_state[3]_i_4__37_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__37_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__37_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__37 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__37_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__37 (.I0(current_state[1]), .I1(\current_state[3]_i_2__37_n_0 ), .I2(\current_state[3]_i_4__37_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__37 (.I0(\current_state[3]_i_2__37_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__37_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__37_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__37 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__37_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__37 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[0]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__37_n_0 )); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__37 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__37_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__37 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__37_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__37_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__37 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__37 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__37 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__37 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__37 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__37 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__37_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__37 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__37 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__37 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__37 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__37 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__37 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__37 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__37 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__37 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__37_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__37 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__37_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__37_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__37 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__37_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__37_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__36 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,459
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36 (D, E, tc_config_cs_serial_output, \G_1PIPE_IFACE.s_daddr_r_reg[2] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 , \parallel_dout_reg[15]_0 , s_do_o, \parallel_dout_reg[15]_1 , \parallel_dout_reg[15]_2 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 , \parallel_dout_reg[14]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 , \parallel_dout_reg[13]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 , \parallel_dout_reg[12]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 , \parallel_dout_reg[11]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 , \parallel_dout_reg[10]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 , \parallel_dout_reg[9]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 , \parallel_dout_reg[8]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 , \parallel_dout_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 , \parallel_dout_reg[6]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 , \parallel_dout_reg[5]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 , \parallel_dout_reg[4]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 , \parallel_dout_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 , \parallel_dout_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 , \parallel_dout_reg[1]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o); output [15:0]D; output [0:0]E; output [0:0]tc_config_cs_serial_output; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [5:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]\parallel_dout_reg[15]_2 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ; input \parallel_dout_reg[14]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ; input \parallel_dout_reg[13]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ; input \parallel_dout_reg[12]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ; input \parallel_dout_reg[11]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ; input \parallel_dout_reg[10]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ; input \parallel_dout_reg[9]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ; input \parallel_dout_reg[8]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ; input \parallel_dout_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ; input \parallel_dout_reg[6]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ; input \parallel_dout_reg[5]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ; input \parallel_dout_reg[4]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ; input \parallel_dout_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ; input \parallel_dout_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ; input \parallel_dout_reg[1]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [15:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__38_n_0 ; wire \current_state[3]_i_3__38_n_0 ; wire \current_state[3]_i_4__38_n_0 ; wire data_out_sel; wire data_out_sel_i_1__38_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [15:0]\parallel_dout_reg[15]_2 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__38_n_0 ; wire \shadow[10]_i_1__38_n_0 ; wire \shadow[11]_i_1__38_n_0 ; wire \shadow[12]_i_1__38_n_0 ; wire \shadow[13]_i_1__38_n_0 ; wire \shadow[14]_i_1__38_n_0 ; wire \shadow[15]_i_1__38_n_0 ; wire \shadow[1]_i_1__38_n_0 ; wire \shadow[2]_i_1__38_n_0 ; wire \shadow[3]_i_1__38_n_0 ; wire \shadow[4]_i_1__38_n_0 ; wire \shadow[5]_i_1__38_n_0 ; wire \shadow[6]_i_1__38_n_0 ; wire \shadow[7]_i_1__38_n_0 ; wire \shadow[8]_i_1__38_n_0 ; wire \shadow[9]_i_1__38_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__38_n_0; wire \slaveRegDo_mux_5[0]_i_6_n_0 ; wire \slaveRegDo_mux_5[10]_i_6_n_0 ; wire \slaveRegDo_mux_5[11]_i_6_n_0 ; wire \slaveRegDo_mux_5[12]_i_6_n_0 ; wire \slaveRegDo_mux_5[13]_i_6_n_0 ; wire \slaveRegDo_mux_5[14]_i_6_n_0 ; wire \slaveRegDo_mux_5[15]_i_6_n_0 ; wire \slaveRegDo_mux_5[1]_i_6_n_0 ; wire \slaveRegDo_mux_5[2]_i_6_n_0 ; wire \slaveRegDo_mux_5[3]_i_6_n_0 ; wire \slaveRegDo_mux_5[4]_i_6_n_0 ; wire \slaveRegDo_mux_5[5]_i_6_n_0 ; wire \slaveRegDo_mux_5[6]_i_6_n_0 ; wire \slaveRegDo_mux_5[7]_i_6_n_0 ; wire \slaveRegDo_mux_5[8]_i_6_n_0 ; wire \slaveRegDo_mux_5[9]_i_6_n_0 ; wire \slaveRegDo_mux_5_reg[0]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[10]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[11]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[12]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[13]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[14]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[15]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[1]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[2]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[3]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[4]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[5]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[6]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[7]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[8]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[9]_i_2_n_0 ; wire [15:0]\slaveRegDo_tcConfig[5147]_37 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__38 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__38 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__38 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__38 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__38 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__38 (.I0(\current_state[3]_i_4__38_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__38_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__38_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__38 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__38_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__38 (.I0(current_state[1]), .I1(\current_state[3]_i_2__38_n_0 ), .I2(\current_state[3]_i_4__38_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__38 (.I0(\current_state[3]_i_2__38_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__38_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__38_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__38 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__38_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__38 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__38_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__38 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__38_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__38 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__38_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__38_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [1]), .Q(\slaveRegDo_tcConfig[5147]_37 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [11]), .Q(\slaveRegDo_tcConfig[5147]_37 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [12]), .Q(\slaveRegDo_tcConfig[5147]_37 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [13]), .Q(\slaveRegDo_tcConfig[5147]_37 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [14]), .Q(\slaveRegDo_tcConfig[5147]_37 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [15]), .Q(\slaveRegDo_tcConfig[5147]_37 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5147]_37 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [2]), .Q(\slaveRegDo_tcConfig[5147]_37 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [3]), .Q(\slaveRegDo_tcConfig[5147]_37 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [4]), .Q(\slaveRegDo_tcConfig[5147]_37 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [5]), .Q(\slaveRegDo_tcConfig[5147]_37 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [6]), .Q(\slaveRegDo_tcConfig[5147]_37 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [7]), .Q(\slaveRegDo_tcConfig[5147]_37 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [8]), .Q(\slaveRegDo_tcConfig[5147]_37 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [9]), .Q(\slaveRegDo_tcConfig[5147]_37 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [10]), .Q(\slaveRegDo_tcConfig[5147]_37 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__38 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__38 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__38 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__38 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__38 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__38 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__38_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__38 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__38 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__38 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__38 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__38 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__38 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__38 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__38 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__38 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__38 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__38_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__38 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__38_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__38_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_1 (.I0(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ), .O(D[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [0]), .O(\slaveRegDo_mux_5[0]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_1 (.I0(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ), .O(D[10])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [10]), .O(\slaveRegDo_mux_5[10]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_1 (.I0(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ), .O(D[11])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [11]), .O(\slaveRegDo_mux_5[11]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_1 (.I0(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ), .O(D[12])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [12]), .O(\slaveRegDo_mux_5[12]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_1 (.I0(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ), .O(D[13])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [13]), .O(\slaveRegDo_mux_5[13]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_1 (.I0(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ), .O(D[14])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [14]), .O(\slaveRegDo_mux_5[14]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_1 (.I0(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ), .O(D[15])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [15]), .O(\slaveRegDo_mux_5[15]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_1 (.I0(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ), .O(D[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [1]), .O(\slaveRegDo_mux_5[1]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_1 (.I0(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ), .O(D[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [2]), .O(\slaveRegDo_mux_5[2]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_1 (.I0(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ), .O(D[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [3]), .O(\slaveRegDo_mux_5[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_1 (.I0(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ), .O(D[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [4]), .O(\slaveRegDo_mux_5[4]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_1 (.I0(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ), .O(D[5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [5]), .O(\slaveRegDo_mux_5[5]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_1 (.I0(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ), .O(D[6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [6]), .O(\slaveRegDo_mux_5[6]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_1 (.I0(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ), .O(D[7])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [7]), .O(\slaveRegDo_mux_5[7]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_1 (.I0(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ), .O(D[8])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [8]), .O(\slaveRegDo_mux_5[8]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_1 (.I0(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ), .O(D[9])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [9]), .O(\slaveRegDo_mux_5[9]_i_6_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_2 (.I0(\slaveRegDo_mux_5[0]_i_6_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_2 (.I0(\slaveRegDo_mux_5[10]_i_6_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_2 (.I0(\slaveRegDo_mux_5[11]_i_6_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_2 (.I0(\slaveRegDo_mux_5[12]_i_6_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_2 (.I0(\slaveRegDo_mux_5[13]_i_6_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_2 (.I0(\slaveRegDo_mux_5[14]_i_6_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_2 (.I0(\slaveRegDo_mux_5[15]_i_6_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_2 (.I0(\slaveRegDo_mux_5[1]_i_6_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_2 (.I0(\slaveRegDo_mux_5[2]_i_6_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_2 (.I0(\slaveRegDo_mux_5[3]_i_6_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_2 (.I0(\slaveRegDo_mux_5[4]_i_6_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_2 (.I0(\slaveRegDo_mux_5[5]_i_6_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_2 (.I0(\slaveRegDo_mux_5[6]_i_6_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_2 (.I0(\slaveRegDo_mux_5[7]_i_6_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_2 (.I0(\slaveRegDo_mux_5[8]_i_6_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_2 (.I0(\slaveRegDo_mux_5[9]_i_6_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__37 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36 (D, E, tc_config_cs_serial_output, \G_1PIPE_IFACE.s_daddr_r_reg[2] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 , \parallel_dout_reg[15]_0 , s_do_o, \parallel_dout_reg[15]_1 , \parallel_dout_reg[15]_2 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 , \parallel_dout_reg[14]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 , \parallel_dout_reg[13]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 , \parallel_dout_reg[12]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 , \parallel_dout_reg[11]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 , \parallel_dout_reg[10]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 , \parallel_dout_reg[9]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 , \parallel_dout_reg[8]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 , \parallel_dout_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 , \parallel_dout_reg[6]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 , \parallel_dout_reg[5]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 , \parallel_dout_reg[4]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 , \parallel_dout_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 , \parallel_dout_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 , \parallel_dout_reg[1]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 , \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 , \parallel_dout_reg[0]_0 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o);
output [15:0]D; output [0:0]E; output [0:0]tc_config_cs_serial_output; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [5:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ; input \parallel_dout_reg[15]_0 ; input [15:0]s_do_o; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]\parallel_dout_reg[15]_2 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ; input \parallel_dout_reg[14]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ; input \parallel_dout_reg[13]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ; input \parallel_dout_reg[12]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ; input \parallel_dout_reg[11]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ; input \parallel_dout_reg[10]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ; input \parallel_dout_reg[9]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ; input \parallel_dout_reg[8]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ; input \parallel_dout_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ; input \parallel_dout_reg[6]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ; input \parallel_dout_reg[5]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ; input \parallel_dout_reg[4]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ; input \parallel_dout_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ; input \parallel_dout_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ; input \parallel_dout_reg[1]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ; input \parallel_dout_reg[0]_0 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [15:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__38_n_0 ; wire \current_state[3]_i_3__38_n_0 ; wire \current_state[3]_i_4__38_n_0 ; wire data_out_sel; wire data_out_sel_i_1__38_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [15:0]\parallel_dout_reg[15]_2 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__38_n_0 ; wire \shadow[10]_i_1__38_n_0 ; wire \shadow[11]_i_1__38_n_0 ; wire \shadow[12]_i_1__38_n_0 ; wire \shadow[13]_i_1__38_n_0 ; wire \shadow[14]_i_1__38_n_0 ; wire \shadow[15]_i_1__38_n_0 ; wire \shadow[1]_i_1__38_n_0 ; wire \shadow[2]_i_1__38_n_0 ; wire \shadow[3]_i_1__38_n_0 ; wire \shadow[4]_i_1__38_n_0 ; wire \shadow[5]_i_1__38_n_0 ; wire \shadow[6]_i_1__38_n_0 ; wire \shadow[7]_i_1__38_n_0 ; wire \shadow[8]_i_1__38_n_0 ; wire \shadow[9]_i_1__38_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__38_n_0; wire \slaveRegDo_mux_5[0]_i_6_n_0 ; wire \slaveRegDo_mux_5[10]_i_6_n_0 ; wire \slaveRegDo_mux_5[11]_i_6_n_0 ; wire \slaveRegDo_mux_5[12]_i_6_n_0 ; wire \slaveRegDo_mux_5[13]_i_6_n_0 ; wire \slaveRegDo_mux_5[14]_i_6_n_0 ; wire \slaveRegDo_mux_5[15]_i_6_n_0 ; wire \slaveRegDo_mux_5[1]_i_6_n_0 ; wire \slaveRegDo_mux_5[2]_i_6_n_0 ; wire \slaveRegDo_mux_5[3]_i_6_n_0 ; wire \slaveRegDo_mux_5[4]_i_6_n_0 ; wire \slaveRegDo_mux_5[5]_i_6_n_0 ; wire \slaveRegDo_mux_5[6]_i_6_n_0 ; wire \slaveRegDo_mux_5[7]_i_6_n_0 ; wire \slaveRegDo_mux_5[8]_i_6_n_0 ; wire \slaveRegDo_mux_5[9]_i_6_n_0 ; wire \slaveRegDo_mux_5_reg[0]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[10]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[11]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[12]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[13]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[14]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[15]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[1]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[2]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[3]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[4]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[5]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[6]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[7]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[8]_i_2_n_0 ; wire \slaveRegDo_mux_5_reg[9]_i_2_n_0 ; wire [15:0]\slaveRegDo_tcConfig[5147]_37 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__38 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__38 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__38 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__38 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__38 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__38 (.I0(\current_state[3]_i_4__38_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__38_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__38_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__38 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__38_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__38 (.I0(current_state[1]), .I1(\current_state[3]_i_2__38_n_0 ), .I2(\current_state[3]_i_4__38_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__38 (.I0(\current_state[3]_i_2__38_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__38_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__38_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__38 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__38_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) \current_state[3]_i_3__38 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__38_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__38 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__38_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__38 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__38_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__38_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [1]), .Q(\slaveRegDo_tcConfig[5147]_37 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [11]), .Q(\slaveRegDo_tcConfig[5147]_37 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [12]), .Q(\slaveRegDo_tcConfig[5147]_37 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [13]), .Q(\slaveRegDo_tcConfig[5147]_37 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [14]), .Q(\slaveRegDo_tcConfig[5147]_37 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [15]), .Q(\slaveRegDo_tcConfig[5147]_37 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5147]_37 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [2]), .Q(\slaveRegDo_tcConfig[5147]_37 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [3]), .Q(\slaveRegDo_tcConfig[5147]_37 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [4]), .Q(\slaveRegDo_tcConfig[5147]_37 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [5]), .Q(\slaveRegDo_tcConfig[5147]_37 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [6]), .Q(\slaveRegDo_tcConfig[5147]_37 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [7]), .Q(\slaveRegDo_tcConfig[5147]_37 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [8]), .Q(\slaveRegDo_tcConfig[5147]_37 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [9]), .Q(\slaveRegDo_tcConfig[5147]_37 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5147]_37 [10]), .Q(\slaveRegDo_tcConfig[5147]_37 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__38 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__38 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__38 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__38 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__38 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__38 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__38_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__38 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__38 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__38 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__38 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__38 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__38 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__38 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__38 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__38 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__38_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__38 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__38_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__38_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__38 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__38_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__38_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_1 (.I0(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_44 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_45 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_46 ), .O(D[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [0]), .O(\slaveRegDo_mux_5[0]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_1 (.I0(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_15 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_16 ), .O(D[10])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [10]), .O(\slaveRegDo_mux_5[10]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_1 (.I0(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ), .O(D[11])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [11]), .O(\slaveRegDo_mux_5[11]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_1 (.I0(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ), .O(D[12])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [12]), .O(\slaveRegDo_mux_5[12]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_1 (.I0(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ), .O(D[13])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [13]), .O(\slaveRegDo_mux_5[13]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_1 (.I0(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ), .O(D[14])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [14]), .O(\slaveRegDo_mux_5[14]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_1 (.I0(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ), .O(D[15])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [15]), .O(\slaveRegDo_mux_5[15]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_1 (.I0(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_41 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_42 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_43 ), .O(D[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [1]), .O(\slaveRegDo_mux_5[1]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_1 (.I0(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_38 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_39 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_40 ), .O(D[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [2]), .O(\slaveRegDo_mux_5[2]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_1 (.I0(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_35 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_36 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_37 ), .O(D[3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [3]), .O(\slaveRegDo_mux_5[3]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_1 (.I0(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_32 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_33 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_34 ), .O(D[4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [4]), .O(\slaveRegDo_mux_5[4]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_1 (.I0(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_29 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_30 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_31 ), .O(D[5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [5]), .O(\slaveRegDo_mux_5[5]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_1 (.I0(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_26 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_27 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_28 ), .O(D[6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [6]), .O(\slaveRegDo_mux_5[6]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_1 (.I0(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_23 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_24 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_25 ), .O(D[7])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [7]), .O(\slaveRegDo_mux_5[7]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_1 (.I0(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_20 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_21 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_22 ), .O(D[8])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [8]), .O(\slaveRegDo_mux_5[8]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_1 (.I0(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_17 ), .I2(s_daddr_o[4]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_18 ), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[2]_19 ), .O(D[9])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_6 (.I0(\slaveRegDo_tcConfig[5147]_37 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_1 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_2 [9]), .O(\slaveRegDo_mux_5[9]_i_6_n_0 )); MUXF7 \slaveRegDo_mux_5_reg[0]_i_2 (.I0(\slaveRegDo_mux_5[0]_i_6_n_0 ), .I1(\parallel_dout_reg[0]_0 ), .O(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[10]_i_2 (.I0(\slaveRegDo_mux_5[10]_i_6_n_0 ), .I1(\parallel_dout_reg[10]_0 ), .O(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[11]_i_2 (.I0(\slaveRegDo_mux_5[11]_i_6_n_0 ), .I1(\parallel_dout_reg[11]_0 ), .O(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[12]_i_2 (.I0(\slaveRegDo_mux_5[12]_i_6_n_0 ), .I1(\parallel_dout_reg[12]_0 ), .O(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[13]_i_2 (.I0(\slaveRegDo_mux_5[13]_i_6_n_0 ), .I1(\parallel_dout_reg[13]_0 ), .O(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[14]_i_2 (.I0(\slaveRegDo_mux_5[14]_i_6_n_0 ), .I1(\parallel_dout_reg[14]_0 ), .O(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[15]_i_2 (.I0(\slaveRegDo_mux_5[15]_i_6_n_0 ), .I1(\parallel_dout_reg[15]_0 ), .O(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[1]_i_2 (.I0(\slaveRegDo_mux_5[1]_i_6_n_0 ), .I1(\parallel_dout_reg[1]_0 ), .O(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[2]_i_2 (.I0(\slaveRegDo_mux_5[2]_i_6_n_0 ), .I1(\parallel_dout_reg[2]_0 ), .O(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[3]_i_2 (.I0(\slaveRegDo_mux_5[3]_i_6_n_0 ), .I1(\parallel_dout_reg[3]_0 ), .O(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[4]_i_2 (.I0(\slaveRegDo_mux_5[4]_i_6_n_0 ), .I1(\parallel_dout_reg[4]_0 ), .O(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[5]_i_2 (.I0(\slaveRegDo_mux_5[5]_i_6_n_0 ), .I1(\parallel_dout_reg[5]_0 ), .O(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[6]_i_2 (.I0(\slaveRegDo_mux_5[6]_i_6_n_0 ), .I1(\parallel_dout_reg[6]_0 ), .O(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[7]_i_2 (.I0(\slaveRegDo_mux_5[7]_i_6_n_0 ), .I1(\parallel_dout_reg[7]_0 ), .O(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[8]_i_2 (.I0(\slaveRegDo_mux_5[8]_i_6_n_0 ), .I1(\parallel_dout_reg[8]_0 ), .O(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ), .S(s_daddr_o[2])); MUXF7 \slaveRegDo_mux_5_reg[9]_i_2 (.I0(\slaveRegDo_mux_5[9]_i_6_n_0 ), .I1(\parallel_dout_reg[9]_0 ), .O(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ), .S(s_daddr_o[2])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__37 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,460
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__39_n_0 ; wire \current_state[3]_i_3__39_n_0 ; wire \current_state[3]_i_4__39_n_0 ; wire data_out_sel; wire data_out_sel_i_1__39_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__39_n_0 ; wire \shadow[10]_i_1__39_n_0 ; wire \shadow[11]_i_1__39_n_0 ; wire \shadow[12]_i_1__39_n_0 ; wire \shadow[13]_i_1__39_n_0 ; wire \shadow[14]_i_1__39_n_0 ; wire \shadow[15]_i_1__39_n_0 ; wire \shadow[1]_i_1__39_n_0 ; wire \shadow[2]_i_1__39_n_0 ; wire \shadow[3]_i_1__39_n_0 ; wire \shadow[4]_i_1__39_n_0 ; wire \shadow[5]_i_1__39_n_0 ; wire \shadow[6]_i_1__39_n_0 ; wire \shadow[7]_i_1__39_n_0 ; wire \shadow[8]_i_1__39_n_0 ; wire \shadow[9]_i_1__39_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__39_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__39 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__39 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__39 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__39 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__39 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__39 (.I0(\current_state[3]_i_4__39_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__39_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__39_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__39 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__39_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__39 (.I0(current_state[1]), .I1(\current_state[3]_i_2__39_n_0 ), .I2(\current_state[3]_i_4__39_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__39 (.I0(\current_state[3]_i_2__39_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__39_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__39_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__39 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__39_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__39 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__39_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__39 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__39_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__39 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__39_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__39_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__39 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__39 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__39 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__39 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__39 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__39 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__39_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__39 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__39 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__39 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__39 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__39 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__39 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__39 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__39 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__39 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__39 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__39_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__39 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__39_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__39_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__38 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__39_n_0 ; wire \current_state[3]_i_3__39_n_0 ; wire \current_state[3]_i_4__39_n_0 ; wire data_out_sel; wire data_out_sel_i_1__39_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__39_n_0 ; wire \shadow[10]_i_1__39_n_0 ; wire \shadow[11]_i_1__39_n_0 ; wire \shadow[12]_i_1__39_n_0 ; wire \shadow[13]_i_1__39_n_0 ; wire \shadow[14]_i_1__39_n_0 ; wire \shadow[15]_i_1__39_n_0 ; wire \shadow[1]_i_1__39_n_0 ; wire \shadow[2]_i_1__39_n_0 ; wire \shadow[3]_i_1__39_n_0 ; wire \shadow[4]_i_1__39_n_0 ; wire \shadow[5]_i_1__39_n_0 ; wire \shadow[6]_i_1__39_n_0 ; wire \shadow[7]_i_1__39_n_0 ; wire \shadow[8]_i_1__39_n_0 ; wire \shadow[9]_i_1__39_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__39_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__39 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__39 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__39 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__39 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__39 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__39 (.I0(\current_state[3]_i_4__39_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__39_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__39_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__39 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__39_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__39 (.I0(current_state[1]), .I1(\current_state[3]_i_2__39_n_0 ), .I2(\current_state[3]_i_4__39_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__39 (.I0(\current_state[3]_i_2__39_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__39_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__39_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__39 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__39_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__39 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__39_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__39 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__39_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__39 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__39_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__39_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__39 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__39 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__39 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__39 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__39 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__39 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__39_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__39 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__39 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__39 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__39 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__39 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__39 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__39 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__39 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__39 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__39_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__39 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__39_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__39_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__39 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__39_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__39_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__38 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,461
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__40_n_0 ; wire \current_state[3]_i_3__40_n_0 ; wire \current_state[3]_i_4__40_n_0 ; wire data_out_sel; wire data_out_sel_i_1__40_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__40_n_0 ; wire \shadow[10]_i_1__40_n_0 ; wire \shadow[11]_i_1__40_n_0 ; wire \shadow[12]_i_1__40_n_0 ; wire \shadow[13]_i_1__40_n_0 ; wire \shadow[14]_i_1__40_n_0 ; wire \shadow[15]_i_1__40_n_0 ; wire \shadow[1]_i_1__40_n_0 ; wire \shadow[2]_i_1__40_n_0 ; wire \shadow[3]_i_1__40_n_0 ; wire \shadow[4]_i_1__40_n_0 ; wire \shadow[5]_i_1__40_n_0 ; wire \shadow[6]_i_1__40_n_0 ; wire \shadow[7]_i_1__40_n_0 ; wire \shadow[8]_i_1__40_n_0 ; wire \shadow[9]_i_1__40_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__40_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__40 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__40 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__40 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__40 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__40 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__40 (.I0(\current_state[3]_i_4__40_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__40_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__40_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__40 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__40_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__40 (.I0(current_state[1]), .I1(\current_state[3]_i_2__40_n_0 ), .I2(\current_state[3]_i_4__40_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__40 (.I0(\current_state[3]_i_2__40_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__40_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__40_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__40 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__40 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__40_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__40 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__40_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__40 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__40_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__40_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__40 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__40 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__40 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__40 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__40 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__40 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__40_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__40 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__40 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__40 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__40 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__40 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__40 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__40 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__40 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__40 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__40 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__40_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__40 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__40_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__40_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__39 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__40_n_0 ; wire \current_state[3]_i_3__40_n_0 ; wire \current_state[3]_i_4__40_n_0 ; wire data_out_sel; wire data_out_sel_i_1__40_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__40_n_0 ; wire \shadow[10]_i_1__40_n_0 ; wire \shadow[11]_i_1__40_n_0 ; wire \shadow[12]_i_1__40_n_0 ; wire \shadow[13]_i_1__40_n_0 ; wire \shadow[14]_i_1__40_n_0 ; wire \shadow[15]_i_1__40_n_0 ; wire \shadow[1]_i_1__40_n_0 ; wire \shadow[2]_i_1__40_n_0 ; wire \shadow[3]_i_1__40_n_0 ; wire \shadow[4]_i_1__40_n_0 ; wire \shadow[5]_i_1__40_n_0 ; wire \shadow[6]_i_1__40_n_0 ; wire \shadow[7]_i_1__40_n_0 ; wire \shadow[8]_i_1__40_n_0 ; wire \shadow[9]_i_1__40_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__40_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__40 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__40 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__40 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__40 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__40 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__40 (.I0(\current_state[3]_i_4__40_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__40_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__40_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__40 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__40_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__40 (.I0(current_state[1]), .I1(\current_state[3]_i_2__40_n_0 ), .I2(\current_state[3]_i_4__40_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__40 (.I0(\current_state[3]_i_2__40_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__40_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__40_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__40 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__40_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__40 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__40_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__40 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__40_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__40 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__40_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__40_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__40 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__40 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__40 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__40 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__40 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__40 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__40_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__40 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__40 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__40 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__40 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__40 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__40 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__40 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__40 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__40 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__40_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__40 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__40_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__40_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__40 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__40_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__40_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__39 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,462
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__41_n_0 ; wire \current_state[3]_i_3__41_n_0 ; wire \current_state[3]_i_4__41_n_0 ; wire data_out_sel; wire data_out_sel_i_1__41_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__41_n_0 ; wire \shadow[10]_i_1__41_n_0 ; wire \shadow[11]_i_1__41_n_0 ; wire \shadow[12]_i_1__41_n_0 ; wire \shadow[13]_i_1__41_n_0 ; wire \shadow[14]_i_1__41_n_0 ; wire \shadow[15]_i_1__41_n_0 ; wire \shadow[1]_i_1__41_n_0 ; wire \shadow[2]_i_1__41_n_0 ; wire \shadow[3]_i_1__41_n_0 ; wire \shadow[4]_i_1__41_n_0 ; wire \shadow[5]_i_1__41_n_0 ; wire \shadow[6]_i_1__41_n_0 ; wire \shadow[7]_i_1__41_n_0 ; wire \shadow[8]_i_1__41_n_0 ; wire \shadow[9]_i_1__41_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__41_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__41 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__41 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__41 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__41 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__41 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__41 (.I0(\current_state[3]_i_4__41_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__41_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__41_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__41 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__41_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__41 (.I0(current_state[1]), .I1(\current_state[3]_i_2__41_n_0 ), .I2(\current_state[3]_i_4__41_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__41 (.I0(\current_state[3]_i_2__41_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__41_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__41_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__41 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__41_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__41 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__41_n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__41 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__41_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__41 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__41_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__41_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__41 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__41 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__41 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__41 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__41 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__41 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__41_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__41 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__41 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__41 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__41 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__41 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__41 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__41 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__41 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__41 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__41 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__41_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__41 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__41_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__41_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__40 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_daddr_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]s_daddr_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__41_n_0 ; wire \current_state[3]_i_3__41_n_0 ; wire \current_state[3]_i_4__41_n_0 ; wire data_out_sel; wire data_out_sel_i_1__41_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [3:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__41_n_0 ; wire \shadow[10]_i_1__41_n_0 ; wire \shadow[11]_i_1__41_n_0 ; wire \shadow[12]_i_1__41_n_0 ; wire \shadow[13]_i_1__41_n_0 ; wire \shadow[14]_i_1__41_n_0 ; wire \shadow[15]_i_1__41_n_0 ; wire \shadow[1]_i_1__41_n_0 ; wire \shadow[2]_i_1__41_n_0 ; wire \shadow[3]_i_1__41_n_0 ; wire \shadow[4]_i_1__41_n_0 ; wire \shadow[5]_i_1__41_n_0 ; wire \shadow[6]_i_1__41_n_0 ; wire \shadow[7]_i_1__41_n_0 ; wire \shadow[8]_i_1__41_n_0 ; wire \shadow[9]_i_1__41_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__41_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__41 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__41 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__41 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__41 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__41 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__41 (.I0(\current_state[3]_i_4__41_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__41_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__41_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__41 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__41_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__41 (.I0(current_state[1]), .I1(\current_state[3]_i_2__41_n_0 ), .I2(\current_state[3]_i_4__41_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__41 (.I0(\current_state[3]_i_2__41_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__41_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__41_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__41 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__41_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__41 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__41_n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__41 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__41_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__41 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__41_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__41_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__41 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__41 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__41 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__41 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__41 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__41 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__41_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__41 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__41 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__41 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__41 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__41 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__41 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__41 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__41 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__41 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__41_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__41 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__41_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__41_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__41 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__41_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__41_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__40 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,463
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__6_n_0 ; wire \current_state[3]_i_3__6_n_0 ; wire \current_state[3]_i_4__6_n_0 ; wire data_out_sel; wire data_out_sel_i_1__6_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__6_n_0 ; wire \shadow[10]_i_1__6_n_0 ; wire \shadow[11]_i_1__6_n_0 ; wire \shadow[12]_i_1__6_n_0 ; wire \shadow[13]_i_1__6_n_0 ; wire \shadow[14]_i_1__6_n_0 ; wire \shadow[15]_i_1__6_n_0 ; wire \shadow[1]_i_1__6_n_0 ; wire \shadow[2]_i_1__6_n_0 ; wire \shadow[3]_i_1__6_n_0 ; wire \shadow[4]_i_1__6_n_0 ; wire \shadow[5]_i_1__6_n_0 ; wire \shadow[6]_i_1__6_n_0 ; wire \shadow[7]_i_1__6_n_0 ; wire \shadow[8]_i_1__6_n_0 ; wire \shadow[9]_i_1__6_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__6_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__6 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__6 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__6 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__6 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__6 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__6 (.I0(\current_state[3]_i_4__6_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__6_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__6_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__6 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__6_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__6_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__6 (.I0(current_state[1]), .I1(\current_state[3]_i_2__6_n_0 ), .I2(\current_state[3]_i_4__6_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__6 (.I0(\current_state[3]_i_2__6_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__6_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__6_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__6 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__6_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__6 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__6_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__6 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__6_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__6_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__6 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__6 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__6 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__6 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__6 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__6 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__6_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__6 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__6 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__6 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__6 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__6 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__6 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__6 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__6 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__6 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__6 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__6_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__6 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__6_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__6_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__5 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__6_n_0 ; wire \current_state[3]_i_3__6_n_0 ; wire \current_state[3]_i_4__6_n_0 ; wire data_out_sel; wire data_out_sel_i_1__6_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__6_n_0 ; wire \shadow[10]_i_1__6_n_0 ; wire \shadow[11]_i_1__6_n_0 ; wire \shadow[12]_i_1__6_n_0 ; wire \shadow[13]_i_1__6_n_0 ; wire \shadow[14]_i_1__6_n_0 ; wire \shadow[15]_i_1__6_n_0 ; wire \shadow[1]_i_1__6_n_0 ; wire \shadow[2]_i_1__6_n_0 ; wire \shadow[3]_i_1__6_n_0 ; wire \shadow[4]_i_1__6_n_0 ; wire \shadow[5]_i_1__6_n_0 ; wire \shadow[6]_i_1__6_n_0 ; wire \shadow[7]_i_1__6_n_0 ; wire \shadow[8]_i_1__6_n_0 ; wire \shadow[9]_i_1__6_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__6_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__6 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__6 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__6 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__6 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__6 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__6 (.I0(\current_state[3]_i_4__6_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__6_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__6_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__6 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__6_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__6_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__6 (.I0(current_state[1]), .I1(\current_state[3]_i_2__6_n_0 ), .I2(\current_state[3]_i_4__6_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__6 (.I0(\current_state[3]_i_2__6_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__6_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__6_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__6 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__6_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__6 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__6_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__6 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__6_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__6_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__6 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__6 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__6 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__6 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__6 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__6 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__6_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__6 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__6 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__6 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__6 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__6 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__6 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__6 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__6 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__6 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__6_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__6 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__6_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__6_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__6 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__6_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__6_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__5 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,464
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o); output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [5:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__42_n_0 ; wire \current_state[3]_i_3__42_n_0 ; wire \current_state[3]_i_4__42_n_0 ; wire data_out_sel; wire data_out_sel_i_1__42_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__42_n_0 ; wire \shadow[10]_i_1__42_n_0 ; wire \shadow[11]_i_1__42_n_0 ; wire \shadow[12]_i_1__42_n_0 ; wire \shadow[13]_i_1__42_n_0 ; wire \shadow[14]_i_1__42_n_0 ; wire \shadow[15]_i_1__42_n_0 ; wire \shadow[1]_i_1__42_n_0 ; wire \shadow[2]_i_1__42_n_0 ; wire \shadow[3]_i_1__42_n_0 ; wire \shadow[4]_i_1__42_n_0 ; wire \shadow[5]_i_1__42_n_0 ; wire \shadow[6]_i_1__42_n_0 ; wire \shadow[7]_i_1__42_n_0 ; wire \shadow[8]_i_1__42_n_0 ; wire \shadow[9]_i_1__42_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__42_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5151]_41 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__42 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__42 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__42 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__42 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__42 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__42 (.I0(\current_state[3]_i_4__42_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__42_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__42_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__42 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__42_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__42 (.I0(current_state[1]), .I1(\current_state[3]_i_2__42_n_0 ), .I2(\current_state[3]_i_4__42_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__42 (.I0(\current_state[3]_i_2__42_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__42_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__42_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__42 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__42_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__42 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__42_n_0 )); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__42 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__42_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__42 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__42_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__42_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [1]), .Q(\slaveRegDo_tcConfig[5151]_41 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [11]), .Q(\slaveRegDo_tcConfig[5151]_41 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [12]), .Q(\slaveRegDo_tcConfig[5151]_41 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [13]), .Q(\slaveRegDo_tcConfig[5151]_41 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [14]), .Q(\slaveRegDo_tcConfig[5151]_41 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [15]), .Q(\slaveRegDo_tcConfig[5151]_41 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5151]_41 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [2]), .Q(\slaveRegDo_tcConfig[5151]_41 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [3]), .Q(\slaveRegDo_tcConfig[5151]_41 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [4]), .Q(\slaveRegDo_tcConfig[5151]_41 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [5]), .Q(\slaveRegDo_tcConfig[5151]_41 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [6]), .Q(\slaveRegDo_tcConfig[5151]_41 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [7]), .Q(\slaveRegDo_tcConfig[5151]_41 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [8]), .Q(\slaveRegDo_tcConfig[5151]_41 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [9]), .Q(\slaveRegDo_tcConfig[5151]_41 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [10]), .Q(\slaveRegDo_tcConfig[5151]_41 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__42 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__42 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__42 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__42 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__42 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__42 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__42_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__42 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__42 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__42 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__42 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__42 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__42 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__42 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__42 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__42 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__42 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__42_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__42 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__42_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__42_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__41 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40 (\slaveRegDo_mux_5_reg[15] , \slaveRegDo_mux_5_reg[14] , \slaveRegDo_mux_5_reg[13] , \slaveRegDo_mux_5_reg[12] , \slaveRegDo_mux_5_reg[11] , \slaveRegDo_mux_5_reg[10] , \slaveRegDo_mux_5_reg[9] , \slaveRegDo_mux_5_reg[8] , \slaveRegDo_mux_5_reg[7] , \slaveRegDo_mux_5_reg[6] , \slaveRegDo_mux_5_reg[5] , \slaveRegDo_mux_5_reg[4] , \slaveRegDo_mux_5_reg[3] , \slaveRegDo_mux_5_reg[2] , \slaveRegDo_mux_5_reg[1] , \slaveRegDo_mux_5_reg[0] , E, tc_config_cs_serial_output, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[7] , s_di_o);
output \slaveRegDo_mux_5_reg[15] ; output \slaveRegDo_mux_5_reg[14] ; output \slaveRegDo_mux_5_reg[13] ; output \slaveRegDo_mux_5_reg[12] ; output \slaveRegDo_mux_5_reg[11] ; output \slaveRegDo_mux_5_reg[10] ; output \slaveRegDo_mux_5_reg[9] ; output \slaveRegDo_mux_5_reg[8] ; output \slaveRegDo_mux_5_reg[7] ; output \slaveRegDo_mux_5_reg[6] ; output \slaveRegDo_mux_5_reg[5] ; output \slaveRegDo_mux_5_reg[4] ; output \slaveRegDo_mux_5_reg[3] ; output \slaveRegDo_mux_5_reg[2] ; output \slaveRegDo_mux_5_reg[1] ; output \slaveRegDo_mux_5_reg[0] ; output [0:0]E; output [0:0]tc_config_cs_serial_output; input [15:0]s_do_o; input [5:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__42_n_0 ; wire \current_state[3]_i_3__42_n_0 ; wire \current_state[3]_i_4__42_n_0 ; wire data_out_sel; wire data_out_sel_i_1__42_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [5:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__42_n_0 ; wire \shadow[10]_i_1__42_n_0 ; wire \shadow[11]_i_1__42_n_0 ; wire \shadow[12]_i_1__42_n_0 ; wire \shadow[13]_i_1__42_n_0 ; wire \shadow[14]_i_1__42_n_0 ; wire \shadow[15]_i_1__42_n_0 ; wire \shadow[1]_i_1__42_n_0 ; wire \shadow[2]_i_1__42_n_0 ; wire \shadow[3]_i_1__42_n_0 ; wire \shadow[4]_i_1__42_n_0 ; wire \shadow[5]_i_1__42_n_0 ; wire \shadow[6]_i_1__42_n_0 ; wire \shadow[7]_i_1__42_n_0 ; wire \shadow[8]_i_1__42_n_0 ; wire \shadow[9]_i_1__42_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__42_n_0; wire \slaveRegDo_mux_5_reg[0] ; wire \slaveRegDo_mux_5_reg[10] ; wire \slaveRegDo_mux_5_reg[11] ; wire \slaveRegDo_mux_5_reg[12] ; wire \slaveRegDo_mux_5_reg[13] ; wire \slaveRegDo_mux_5_reg[14] ; wire \slaveRegDo_mux_5_reg[15] ; wire \slaveRegDo_mux_5_reg[1] ; wire \slaveRegDo_mux_5_reg[2] ; wire \slaveRegDo_mux_5_reg[3] ; wire \slaveRegDo_mux_5_reg[4] ; wire \slaveRegDo_mux_5_reg[5] ; wire \slaveRegDo_mux_5_reg[6] ; wire \slaveRegDo_mux_5_reg[7] ; wire \slaveRegDo_mux_5_reg[8] ; wire \slaveRegDo_mux_5_reg[9] ; wire [15:0]\slaveRegDo_tcConfig[5151]_41 ; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__42 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__42 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__42 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__42 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__42 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__42 (.I0(\current_state[3]_i_4__42_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__42_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__42_n_0 ), .O(next_state[0])); LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__42 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__42_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__42 (.I0(current_state[1]), .I1(\current_state[3]_i_2__42_n_0 ), .I2(\current_state[3]_i_4__42_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__42 (.I0(\current_state[3]_i_2__42_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__42_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__42_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__42 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__42_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \current_state[3]_i_3__42 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[4]), .I4(s_daddr_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__42_n_0 )); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__42 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__42_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__42 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__42_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__42_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [1]), .Q(\slaveRegDo_tcConfig[5151]_41 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [11]), .Q(\slaveRegDo_tcConfig[5151]_41 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [12]), .Q(\slaveRegDo_tcConfig[5151]_41 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [13]), .Q(\slaveRegDo_tcConfig[5151]_41 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [14]), .Q(\slaveRegDo_tcConfig[5151]_41 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [15]), .Q(\slaveRegDo_tcConfig[5151]_41 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(\slaveRegDo_tcConfig[5151]_41 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [2]), .Q(\slaveRegDo_tcConfig[5151]_41 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [3]), .Q(\slaveRegDo_tcConfig[5151]_41 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [4]), .Q(\slaveRegDo_tcConfig[5151]_41 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [5]), .Q(\slaveRegDo_tcConfig[5151]_41 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [6]), .Q(\slaveRegDo_tcConfig[5151]_41 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [7]), .Q(\slaveRegDo_tcConfig[5151]_41 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [8]), .Q(\slaveRegDo_tcConfig[5151]_41 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [9]), .Q(\slaveRegDo_tcConfig[5151]_41 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_tcConfig[5151]_41 [10]), .Q(\slaveRegDo_tcConfig[5151]_41 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__42 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__42 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__42 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__42 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__42 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__42 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__42_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__42 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__42 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__42 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__42 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__42 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__42 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__42 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__42 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__42 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__42_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__42 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__42_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__42_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__42 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__42_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__42_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[0]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_5_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[10]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_5_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[11]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_5_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[12]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_5_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[13]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_5_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[14]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_5_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[15]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_5_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[1]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_5_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[2]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_5_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[3]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_5_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[4]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_5_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[5]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_5_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[6]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_5_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[7]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_5_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[8]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_5_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_5[9]_i_7 (.I0(\slaveRegDo_tcConfig[5151]_41 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_5_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__41 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,465
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41 (s_do_o, E, CFG_CNT_DIN, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__43_n_0 ; wire \current_state[3]_i_3__43_n_0 ; wire \current_state[3]_i_4__43_n_0 ; wire data_out_sel; wire data_out_sel_i_1__43_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__43_n_0 ; wire \shadow[10]_i_1__43_n_0 ; wire \shadow[11]_i_1__43_n_0 ; wire \shadow[12]_i_1__43_n_0 ; wire \shadow[13]_i_1__43_n_0 ; wire \shadow[14]_i_1__43_n_0 ; wire \shadow[15]_i_1__43_n_0 ; wire \shadow[1]_i_1__43_n_0 ; wire \shadow[2]_i_1__43_n_0 ; wire \shadow[3]_i_1__43_n_0 ; wire \shadow[4]_i_1__43_n_0 ; wire \shadow[5]_i_1__43_n_0 ; wire \shadow[6]_i_1__43_n_0 ; wire \shadow[7]_i_1__43_n_0 ; wire \shadow[8]_i_1__43_n_0 ; wire \shadow[9]_i_1__43_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__43_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[0].U_COUNTER_i_4 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__43 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__43 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__43 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__43 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__43 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__43 (.I0(\current_state[3]_i_4__43_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__43_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__43_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__43 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__43_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__43_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__43 (.I0(current_state[1]), .I1(\current_state[3]_i_2__43_n_0 ), .I2(\current_state[3]_i_4__43_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__43 (.I0(\current_state[3]_i_2__43_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__43_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__43_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__43 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__43_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3__43 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3__43_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__43 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__43_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__43 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__43_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__43_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__43 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__43 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__43 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__43 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__43 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__43 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__43_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__43 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__43 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__43 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__43 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__43 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__43 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__43 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__43 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__43 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__43 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__43_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__43 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__43_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__43_n_0), .Q(E), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41 (s_do_o, E, CFG_CNT_DIN, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__43_n_0 ; wire \current_state[3]_i_3__43_n_0 ; wire \current_state[3]_i_4__43_n_0 ; wire data_out_sel; wire data_out_sel_i_1__43_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__43_n_0 ; wire \shadow[10]_i_1__43_n_0 ; wire \shadow[11]_i_1__43_n_0 ; wire \shadow[12]_i_1__43_n_0 ; wire \shadow[13]_i_1__43_n_0 ; wire \shadow[14]_i_1__43_n_0 ; wire \shadow[15]_i_1__43_n_0 ; wire \shadow[1]_i_1__43_n_0 ; wire \shadow[2]_i_1__43_n_0 ; wire \shadow[3]_i_1__43_n_0 ; wire \shadow[4]_i_1__43_n_0 ; wire \shadow[5]_i_1__43_n_0 ; wire \shadow[6]_i_1__43_n_0 ; wire \shadow[7]_i_1__43_n_0 ; wire \shadow[8]_i_1__43_n_0 ; wire \shadow[9]_i_1__43_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__43_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[0].U_COUNTER_i_4 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__43 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__43 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__43 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__43 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__43 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__43 (.I0(\current_state[3]_i_4__43_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__43_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__43_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__43 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__43_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__43_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__43 (.I0(current_state[1]), .I1(\current_state[3]_i_2__43_n_0 ), .I2(\current_state[3]_i_4__43_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__43 (.I0(\current_state[3]_i_2__43_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__43_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__43_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__43 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__43_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3__43 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3__43_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__43 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__43_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__43 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__43_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__43_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__43 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__43 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__43 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__43 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__43 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__43 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__43_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__43 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__43 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__43 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__43 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__43 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__43 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__43 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__43 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__43 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__43_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__43 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__43_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__43_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__43 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__43_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__43_n_0), .Q(E), .R(1'b0)); endmodule
8
2,466
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42 (\count0_reg[6] , s_do_o, E, CFG_CNT_DIN, s_daddr_o, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_den_r_reg , s_di_o); output \count0_reg[6] ; output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input [4:0]s_daddr_o; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [0:0]\G_1PIPE_IFACE.s_den_r_reg ; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire [0:0]\G_1PIPE_IFACE.s_den_r_reg ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire \count0_reg[6] ; wire [3:0]current_state; wire \current_state[3]_i_2__44_n_0 ; wire \current_state[3]_i_3__44_n_0 ; wire \current_state[3]_i_4__44_n_0 ; wire data_out_sel; wire data_out_sel_i_1__44_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [4:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__44_n_0 ; wire \shadow[10]_i_1__44_n_0 ; wire \shadow[11]_i_1__44_n_0 ; wire \shadow[12]_i_1__44_n_0 ; wire \shadow[13]_i_1__44_n_0 ; wire \shadow[14]_i_1__44_n_0 ; wire \shadow[15]_i_1__44_n_0 ; wire \shadow[1]_i_1__44_n_0 ; wire \shadow[2]_i_1__44_n_0 ; wire \shadow[3]_i_1__44_n_0 ; wire \shadow[4]_i_1__44_n_0 ; wire \shadow[5]_i_1__44_n_0 ; wire \shadow[6]_i_1__44_n_0 ; wire \shadow[7]_i_1__44_n_0 ; wire \shadow[8]_i_1__44_n_0 ; wire \shadow[9]_i_1__44_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__44_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[1].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__44 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__44 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__44 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__44 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__44 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__44 (.I0(\current_state[3]_i_4__44_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__44_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__44_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__44 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__44_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__44_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__44 (.I0(current_state[1]), .I1(\current_state[3]_i_2__44_n_0 ), .I2(\current_state[3]_i_4__44_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__44 (.I0(\current_state[3]_i_2__44_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__44_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__44_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__44 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__44_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__44 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\count0_reg[6] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[2]), .I4(\G_1PIPE_IFACE.s_den_r_reg ), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__44_n_0 )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__44 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__44_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__44 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__44_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__44_n_0), .Q(data_out_sel), .R(1'b0)); LUT2 #( .INIT(4'h2)) drdy_ff9_i_4 (.I0(s_daddr_o[0]), .I1(s_daddr_o[1]), .O(\count0_reg[6] )); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__44 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__44 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__44 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__44 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__44 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__44 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__44_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__44 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__44 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__44 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__44 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__44 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__44 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__44 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__44 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__44 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__44 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__44_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__44 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__44_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__44_n_0), .Q(E), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42 (\count0_reg[6] , s_do_o, E, CFG_CNT_DIN, s_daddr_o, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_den_r_reg , s_di_o);
output \count0_reg[6] ; output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input [4:0]s_daddr_o; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [0:0]\G_1PIPE_IFACE.s_den_r_reg ; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire [0:0]\G_1PIPE_IFACE.s_den_r_reg ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire \count0_reg[6] ; wire [3:0]current_state; wire \current_state[3]_i_2__44_n_0 ; wire \current_state[3]_i_3__44_n_0 ; wire \current_state[3]_i_4__44_n_0 ; wire data_out_sel; wire data_out_sel_i_1__44_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [4:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__44_n_0 ; wire \shadow[10]_i_1__44_n_0 ; wire \shadow[11]_i_1__44_n_0 ; wire \shadow[12]_i_1__44_n_0 ; wire \shadow[13]_i_1__44_n_0 ; wire \shadow[14]_i_1__44_n_0 ; wire \shadow[15]_i_1__44_n_0 ; wire \shadow[1]_i_1__44_n_0 ; wire \shadow[2]_i_1__44_n_0 ; wire \shadow[3]_i_1__44_n_0 ; wire \shadow[4]_i_1__44_n_0 ; wire \shadow[5]_i_1__44_n_0 ; wire \shadow[6]_i_1__44_n_0 ; wire \shadow[7]_i_1__44_n_0 ; wire \shadow[8]_i_1__44_n_0 ; wire \shadow[9]_i_1__44_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__44_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[1].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__44 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__44 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__44 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__44 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__44 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__44 (.I0(\current_state[3]_i_4__44_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__44_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__44_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__44 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__44_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__44_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__44 (.I0(current_state[1]), .I1(\current_state[3]_i_2__44_n_0 ), .I2(\current_state[3]_i_4__44_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__44 (.I0(\current_state[3]_i_2__44_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__44_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__44_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__44 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__44_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__44 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\count0_reg[6] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[2]), .I4(\G_1PIPE_IFACE.s_den_r_reg ), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__44_n_0 )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__44 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__44_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__44 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__44_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__44_n_0), .Q(data_out_sel), .R(1'b0)); LUT2 #( .INIT(4'h2)) drdy_ff9_i_4 (.I0(s_daddr_o[0]), .I1(s_daddr_o[1]), .O(\count0_reg[6] )); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__44 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__44 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__44 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__44 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__44 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__44 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__44_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__44 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__44 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__44 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__44 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__44 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__44 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__44 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__44 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__44 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__44_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__44 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__44_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__44_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__44 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__44_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__44_n_0), .Q(E), .R(1'b0)); endmodule
8
2,467
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
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['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43 (s_do_o, E, CFG_CNT_DIN, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , D, s_den_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]D; input s_den_o; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [2:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__45_n_0 ; wire \current_state[3]_i_3__45_n_0 ; wire \current_state[3]_i_4__45_n_0 ; wire data_out_sel; wire data_out_sel_i_1__45_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__45_n_0 ; wire \shadow[10]_i_1__45_n_0 ; wire \shadow[11]_i_1__45_n_0 ; wire \shadow[12]_i_1__45_n_0 ; wire \shadow[13]_i_1__45_n_0 ; wire \shadow[14]_i_1__45_n_0 ; wire \shadow[15]_i_1__45_n_0 ; wire \shadow[1]_i_1__45_n_0 ; wire \shadow[2]_i_1__45_n_0 ; wire \shadow[3]_i_1__45_n_0 ; wire \shadow[4]_i_1__45_n_0 ; wire \shadow[5]_i_1__45_n_0 ; wire \shadow[6]_i_1__45_n_0 ; wire \shadow[7]_i_1__45_n_0 ; wire \shadow[8]_i_1__45_n_0 ; wire \shadow[9]_i_1__45_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__45_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[2].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__45 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__45 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__45 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__45 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__45 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__45 (.I0(\current_state[3]_i_4__45_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__45_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__45_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__45 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__45_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__45_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__45 (.I0(current_state[1]), .I1(\current_state[3]_i_2__45_n_0 ), .I2(\current_state[3]_i_4__45_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__45 (.I0(\current_state[3]_i_2__45_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__45_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__45_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__45 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__45_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \current_state[3]_i_3__45 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(D[1]), .I3(D[0]), .I4(s_den_o), .I5(D[2]), .O(\current_state[3]_i_3__45_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__45 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__45_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__45 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__45_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__45_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__45 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__45 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__45 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__45 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__45 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__45 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__45_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__45 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__45 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__45 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__45 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__45 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__45 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__45 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__45 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__45 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__45 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__45_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__45 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__45_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__45_n_0), .Q(E), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43 (s_do_o, E, CFG_CNT_DIN, s_dclk_o, CFG_CNT_DOUT, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , D, s_den_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]CFG_CNT_DIN; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]D; input s_den_o; input [14:0]s_di_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [2:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__45_n_0 ; wire \current_state[3]_i_3__45_n_0 ; wire \current_state[3]_i_4__45_n_0 ; wire data_out_sel; wire data_out_sel_i_1__45_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__45_n_0 ; wire \shadow[10]_i_1__45_n_0 ; wire \shadow[11]_i_1__45_n_0 ; wire \shadow[12]_i_1__45_n_0 ; wire \shadow[13]_i_1__45_n_0 ; wire \shadow[14]_i_1__45_n_0 ; wire \shadow[15]_i_1__45_n_0 ; wire \shadow[1]_i_1__45_n_0 ; wire \shadow[2]_i_1__45_n_0 ; wire \shadow[3]_i_1__45_n_0 ; wire \shadow[4]_i_1__45_n_0 ; wire \shadow[5]_i_1__45_n_0 ; wire \shadow[6]_i_1__45_n_0 ; wire \shadow[7]_i_1__45_n_0 ; wire \shadow[8]_i_1__45_n_0 ; wire \shadow[9]_i_1__45_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__45_n_0; LUT3 #( .INIT(8'hB8)) \G_COUNTER[2].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__45 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__45 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__45 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__45 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__45 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__45 (.I0(\current_state[3]_i_4__45_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__45_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__45_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__45 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__45_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__45_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__45 (.I0(current_state[1]), .I1(\current_state[3]_i_2__45_n_0 ), .I2(\current_state[3]_i_4__45_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__45 (.I0(\current_state[3]_i_2__45_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__45_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__45_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__45 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__45_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \current_state[3]_i_3__45 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(D[1]), .I3(D[0]), .I4(s_den_o), .I5(D[2]), .O(\current_state[3]_i_3__45_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__45 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__45_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__45 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__45_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__45_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__45 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__45 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__45 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__45 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__45 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__45 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__45_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__45 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__45 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__45 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__45 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__45 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__45 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__45 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__45 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__45 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__45_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__45 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__45_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__45_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__45 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__45_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__45_n_0), .Q(E), .R(1'b0)); endmodule
8
2,468
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44 (D, \slaveRegDo_mux_6_reg[14] , \slaveRegDo_mux_6_reg[13] , \slaveRegDo_mux_6_reg[12] , \slaveRegDo_mux_6_reg[11] , \slaveRegDo_mux_6_reg[10] , \slaveRegDo_mux_6_reg[9] , \slaveRegDo_mux_6_reg[8] , \slaveRegDo_mux_6_reg[7] , \slaveRegDo_mux_6_reg[6] , \slaveRegDo_mux_6_reg[5] , \slaveRegDo_mux_6_reg[4] , \slaveRegDo_mux_6_reg[3] , \slaveRegDo_mux_6_reg[2] , \slaveRegDo_mux_6_reg[1] , \slaveRegDo_mux_6_reg[0] , \shadow_reg[15]_0 , E, CFG_CNT_DIN, \G_1PIPE_IFACE.s_daddr_r_reg[4] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , Q, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_di_o, s_dclk_o, CFG_CNT_DOUT, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o); output [0:0]D; output \slaveRegDo_mux_6_reg[14] ; output \slaveRegDo_mux_6_reg[13] ; output \slaveRegDo_mux_6_reg[12] ; output \slaveRegDo_mux_6_reg[11] ; output \slaveRegDo_mux_6_reg[10] ; output \slaveRegDo_mux_6_reg[9] ; output \slaveRegDo_mux_6_reg[8] ; output \slaveRegDo_mux_6_reg[7] ; output \slaveRegDo_mux_6_reg[6] ; output \slaveRegDo_mux_6_reg[5] ; output \slaveRegDo_mux_6_reg[4] ; output \slaveRegDo_mux_6_reg[3] ; output \slaveRegDo_mux_6_reg[2] ; output \slaveRegDo_mux_6_reg[1] ; output \slaveRegDo_mux_6_reg[0] ; output \shadow_reg[15]_0 ; output [0:0]E; output [0:0]CFG_CNT_DIN; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [0:0]Q; input [15:0]s_do_o; input [4:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]s_di_o; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire [0:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__46_n_0 ; wire \current_state[3]_i_3__46_n_0 ; wire \current_state[3]_i_4__46_n_0 ; wire data_out_sel; wire data_out_sel_i_1__46_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [15:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__46_n_0 ; wire \shadow[10]_i_1__46_n_0 ; wire \shadow[11]_i_1__46_n_0 ; wire \shadow[12]_i_1__46_n_0 ; wire \shadow[13]_i_1__46_n_0 ; wire \shadow[14]_i_1__46_n_0 ; wire \shadow[15]_i_1__46_n_0 ; wire \shadow[1]_i_1__46_n_0 ; wire \shadow[2]_i_1__46_n_0 ; wire \shadow[3]_i_1__46_n_0 ; wire \shadow[4]_i_1__46_n_0 ; wire \shadow[5]_i_1__46_n_0 ; wire \shadow[6]_i_1__46_n_0 ; wire \shadow[7]_i_1__46_n_0 ; wire \shadow[8]_i_1__46_n_0 ; wire \shadow[9]_i_1__46_n_0 ; wire \shadow_reg[15]_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__46_n_0; wire [15:0]\slaveRegDo_cntConfig[6147]_45 ; wire \slaveRegDo_mux_6[15]_i_3_n_0 ; wire \slaveRegDo_mux_6_reg[0] ; wire \slaveRegDo_mux_6_reg[10] ; wire \slaveRegDo_mux_6_reg[11] ; wire \slaveRegDo_mux_6_reg[12] ; wire \slaveRegDo_mux_6_reg[13] ; wire \slaveRegDo_mux_6_reg[14] ; wire \slaveRegDo_mux_6_reg[1] ; wire \slaveRegDo_mux_6_reg[2] ; wire \slaveRegDo_mux_6_reg[3] ; wire \slaveRegDo_mux_6_reg[4] ; wire \slaveRegDo_mux_6_reg[5] ; wire \slaveRegDo_mux_6_reg[6] ; wire \slaveRegDo_mux_6_reg[7] ; wire \slaveRegDo_mux_6_reg[8] ; wire \slaveRegDo_mux_6_reg[9] ; LUT3 #( .INIT(8'hB8)) \G_COUNTER[3].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__46 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__46 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__46 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__46 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__46 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__46 (.I0(\current_state[3]_i_4__46_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__46_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__46_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__46 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__46_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__46_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__46 (.I0(current_state[1]), .I1(\current_state[3]_i_2__46_n_0 ), .I2(\current_state[3]_i_4__46_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__46 (.I0(\current_state[3]_i_2__46_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__46_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__46_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__46 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__46_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__46 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[2]), .I4(s_den_o), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__46_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__46 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__46_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__46 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__46_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__46_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [1]), .Q(\slaveRegDo_cntConfig[6147]_45 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [11]), .Q(\slaveRegDo_cntConfig[6147]_45 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [12]), .Q(\slaveRegDo_cntConfig[6147]_45 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [13]), .Q(\slaveRegDo_cntConfig[6147]_45 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [14]), .Q(\slaveRegDo_cntConfig[6147]_45 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [15]), .Q(\slaveRegDo_cntConfig[6147]_45 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(\slaveRegDo_cntConfig[6147]_45 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [2]), .Q(\slaveRegDo_cntConfig[6147]_45 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [3]), .Q(\slaveRegDo_cntConfig[6147]_45 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [4]), .Q(\slaveRegDo_cntConfig[6147]_45 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [5]), .Q(\slaveRegDo_cntConfig[6147]_45 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [6]), .Q(\slaveRegDo_cntConfig[6147]_45 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [7]), .Q(\slaveRegDo_cntConfig[6147]_45 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [8]), .Q(\slaveRegDo_cntConfig[6147]_45 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [9]), .Q(\slaveRegDo_cntConfig[6147]_45 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [10]), .Q(\slaveRegDo_cntConfig[6147]_45 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__46 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__46 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__46 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__46 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__46 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__46 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__46_n_0 )); LUT1 #( .INIT(2'h1)) \shadow[15]_i_1 (.I0(s_di_o[15]), .O(\shadow_reg[15]_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__46 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__46 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__46 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__46 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__46 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__46 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__46 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__46 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__46 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__46 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__46_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\shadow_reg[15]_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__46 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__46_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__46_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[0]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_6_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[10]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_6_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[11]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_6_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[12]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_6_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[13]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_6_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[14]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_6_reg[14] )); LUT4 #( .INIT(16'h4F44)) \slaveRegDo_mux_6[15]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I1(\slaveRegDo_mux_6[15]_i_3_n_0 ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I3(Q), .O(D)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[15]_i_3 (.I0(\slaveRegDo_cntConfig[6147]_45 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_6[15]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[1]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_6_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[2]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_6_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[3]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_6_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[4]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_6_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[5]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_6_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[6]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_6_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[7]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_6_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[8]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_6_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[9]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_6_reg[9] )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44 (D, \slaveRegDo_mux_6_reg[14] , \slaveRegDo_mux_6_reg[13] , \slaveRegDo_mux_6_reg[12] , \slaveRegDo_mux_6_reg[11] , \slaveRegDo_mux_6_reg[10] , \slaveRegDo_mux_6_reg[9] , \slaveRegDo_mux_6_reg[8] , \slaveRegDo_mux_6_reg[7] , \slaveRegDo_mux_6_reg[6] , \slaveRegDo_mux_6_reg[5] , \slaveRegDo_mux_6_reg[4] , \slaveRegDo_mux_6_reg[3] , \slaveRegDo_mux_6_reg[2] , \slaveRegDo_mux_6_reg[1] , \slaveRegDo_mux_6_reg[0] , \shadow_reg[15]_0 , E, CFG_CNT_DIN, \G_1PIPE_IFACE.s_daddr_r_reg[4] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , Q, s_do_o, s_daddr_o, \parallel_dout_reg[15]_0 , \parallel_dout_reg[15]_1 , s_di_o, s_dclk_o, CFG_CNT_DOUT, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o);
output [0:0]D; output \slaveRegDo_mux_6_reg[14] ; output \slaveRegDo_mux_6_reg[13] ; output \slaveRegDo_mux_6_reg[12] ; output \slaveRegDo_mux_6_reg[11] ; output \slaveRegDo_mux_6_reg[10] ; output \slaveRegDo_mux_6_reg[9] ; output \slaveRegDo_mux_6_reg[8] ; output \slaveRegDo_mux_6_reg[7] ; output \slaveRegDo_mux_6_reg[6] ; output \slaveRegDo_mux_6_reg[5] ; output \slaveRegDo_mux_6_reg[4] ; output \slaveRegDo_mux_6_reg[3] ; output \slaveRegDo_mux_6_reg[2] ; output \slaveRegDo_mux_6_reg[1] ; output \slaveRegDo_mux_6_reg[0] ; output \shadow_reg[15]_0 ; output [0:0]E; output [0:0]CFG_CNT_DIN; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [0:0]Q; input [15:0]s_do_o; input [4:0]s_daddr_o; input [15:0]\parallel_dout_reg[15]_0 ; input [15:0]\parallel_dout_reg[15]_1 ; input [15:0]s_di_o; input s_dclk_o; input [0:0]CFG_CNT_DOUT; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; wire [0:0]CFG_CNT_DIN; wire [0:0]CFG_CNT_DOUT; wire [0:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire [0:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__46_n_0 ; wire \current_state[3]_i_3__46_n_0 ; wire \current_state[3]_i_4__46_n_0 ; wire data_out_sel; wire data_out_sel_i_1__46_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire [15:0]\parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [15:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__46_n_0 ; wire \shadow[10]_i_1__46_n_0 ; wire \shadow[11]_i_1__46_n_0 ; wire \shadow[12]_i_1__46_n_0 ; wire \shadow[13]_i_1__46_n_0 ; wire \shadow[14]_i_1__46_n_0 ; wire \shadow[15]_i_1__46_n_0 ; wire \shadow[1]_i_1__46_n_0 ; wire \shadow[2]_i_1__46_n_0 ; wire \shadow[3]_i_1__46_n_0 ; wire \shadow[4]_i_1__46_n_0 ; wire \shadow[5]_i_1__46_n_0 ; wire \shadow[6]_i_1__46_n_0 ; wire \shadow[7]_i_1__46_n_0 ; wire \shadow[8]_i_1__46_n_0 ; wire \shadow[9]_i_1__46_n_0 ; wire \shadow_reg[15]_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__46_n_0; wire [15:0]\slaveRegDo_cntConfig[6147]_45 ; wire \slaveRegDo_mux_6[15]_i_3_n_0 ; wire \slaveRegDo_mux_6_reg[0] ; wire \slaveRegDo_mux_6_reg[10] ; wire \slaveRegDo_mux_6_reg[11] ; wire \slaveRegDo_mux_6_reg[12] ; wire \slaveRegDo_mux_6_reg[13] ; wire \slaveRegDo_mux_6_reg[14] ; wire \slaveRegDo_mux_6_reg[1] ; wire \slaveRegDo_mux_6_reg[2] ; wire \slaveRegDo_mux_6_reg[3] ; wire \slaveRegDo_mux_6_reg[4] ; wire \slaveRegDo_mux_6_reg[5] ; wire \slaveRegDo_mux_6_reg[6] ; wire \slaveRegDo_mux_6_reg[7] ; wire \slaveRegDo_mux_6_reg[8] ; wire \slaveRegDo_mux_6_reg[9] ; LUT3 #( .INIT(8'hB8)) \G_COUNTER[3].U_COUNTER_i_3 (.I0(serial_dout), .I1(data_out_sel), .I2(CFG_CNT_DOUT), .O(CFG_CNT_DIN)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__46 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__46 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__46 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__46 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__46 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__46 (.I0(\current_state[3]_i_4__46_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__46_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__46_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__46 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__46_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__46_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__46 (.I0(current_state[1]), .I1(\current_state[3]_i_2__46_n_0 ), .I2(\current_state[3]_i_4__46_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__46 (.I0(\current_state[3]_i_2__46_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__46_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__46_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__46 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__46_n_0 )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \current_state[3]_i_3__46 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[3]), .I3(s_daddr_o[2]), .I4(s_den_o), .I5(s_daddr_o[4]), .O(\current_state[3]_i_3__46_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__46 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__46_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__46 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__46_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__46_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [1]), .Q(\slaveRegDo_cntConfig[6147]_45 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [11]), .Q(\slaveRegDo_cntConfig[6147]_45 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [12]), .Q(\slaveRegDo_cntConfig[6147]_45 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [13]), .Q(\slaveRegDo_cntConfig[6147]_45 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [14]), .Q(\slaveRegDo_cntConfig[6147]_45 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [15]), .Q(\slaveRegDo_cntConfig[6147]_45 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(CFG_CNT_DOUT), .Q(\slaveRegDo_cntConfig[6147]_45 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [2]), .Q(\slaveRegDo_cntConfig[6147]_45 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [3]), .Q(\slaveRegDo_cntConfig[6147]_45 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [4]), .Q(\slaveRegDo_cntConfig[6147]_45 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [5]), .Q(\slaveRegDo_cntConfig[6147]_45 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [6]), .Q(\slaveRegDo_cntConfig[6147]_45 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [7]), .Q(\slaveRegDo_cntConfig[6147]_45 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [8]), .Q(\slaveRegDo_cntConfig[6147]_45 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [9]), .Q(\slaveRegDo_cntConfig[6147]_45 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_cntConfig[6147]_45 [10]), .Q(\slaveRegDo_cntConfig[6147]_45 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__46 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__46 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__46 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__46 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__46 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__46 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__46_n_0 )); LUT1 #( .INIT(2'h1)) \shadow[15]_i_1 (.I0(s_di_o[15]), .O(\shadow_reg[15]_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__46 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__46 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__46 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__46 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__46 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__46 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__46 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__46 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__46 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__46_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__46 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__46_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\shadow_reg[15]_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__46_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__46 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__46_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__46_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[0]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [0]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_6_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[10]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [10]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_6_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[11]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [11]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_6_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[12]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [12]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_6_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[13]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [13]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_6_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[14]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [14]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_6_reg[14] )); LUT4 #( .INIT(16'h4F44)) \slaveRegDo_mux_6[15]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I1(\slaveRegDo_mux_6[15]_i_3_n_0 ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I3(Q), .O(D)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[15]_i_3 (.I0(\slaveRegDo_cntConfig[6147]_45 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [15]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_6[15]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[1]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [1]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_6_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[2]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [2]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_6_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[3]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [3]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_6_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[4]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [4]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_6_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[5]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [5]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_6_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[6]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [6]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_6_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[7]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [7]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_6_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[8]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [8]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_6_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_6[9]_i_2 (.I0(\slaveRegDo_cntConfig[6147]_45 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[0]), .I3(\parallel_dout_reg[15]_0 [9]), .I4(s_daddr_o[1]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_6_reg[9] )); endmodule
8
2,469
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45 (E, D, Q, qual_strg_config_cs_serial_output, s_dclk_o, \G_1PIPE_IFACE.s_di_r_reg[15] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[4] , \parallel_dout_reg[0]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[14]_0 , shift_en_reg_0, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o); output [0:0]E; output [14:0]D; output [0:0]Q; output qual_strg_config_cs_serial_output; input s_dclk_o; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input \parallel_dout_reg[0]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[14]_0 ; input [0:0]shift_en_reg_0; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [14:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [0:0]Q; wire clear; wire [3:0]cnt_reg__0; wire [3:0]current_state; wire \current_state[3]_i_2_n_0 ; wire \current_state[3]_i_3_n_0 ; wire \current_state[3]_i_4_n_0 ; wire data_out_sel; wire data_out_sel_i_1_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire qual_strg_config_cs_serial_output; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1_n_0 ; wire \shadow[10]_i_1_n_0 ; wire \shadow[11]_i_1_n_0 ; wire \shadow[12]_i_1_n_0 ; wire \shadow[13]_i_1_n_0 ; wire \shadow[14]_i_1_n_0 ; wire \shadow[15]_i_2_n_0 ; wire \shadow[1]_i_1_n_0 ; wire \shadow[2]_i_1_n_0 ; wire \shadow[3]_i_1_n_0 ; wire \shadow[4]_i_1_n_0 ; wire \shadow[5]_i_1_n_0 ; wire \shadow[6]_i_1_n_0 ; wire \shadow[7]_i_1_n_0 ; wire \shadow[8]_i_1_n_0 ; wire \shadow[9]_i_1_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1_n_0; wire [0:0]shift_en_reg_0; wire [14:0]slaveRegDo_qualStrgConfig; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1 (.I0(cnt_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1 (.I0(cnt_reg__0[0]), .I1(cnt_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1 (.I0(cnt_reg__0[1]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2 (.I0(cnt_reg__0[2]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[1]), .I3(cnt_reg__0[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg__0[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg__0[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg__0[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg__0[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1 (.I0(\current_state[3]_i_4_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1 (.I0(s_dwe_o), .I1(\current_state[3]_i_4_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1 (.I0(current_state[1]), .I1(\current_state[3]_i_2_n_0 ), .I2(\current_state[3]_i_4_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1 (.I0(\current_state[3]_i_2_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2 (.I0(cnt_reg__0[2]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[1]), .I3(cnt_reg__0[3]), .O(\current_state[3]_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); LUT4 #( .INIT(16'h0004)) data_out_sel_i_1 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[1]), .Q(slaveRegDo_qualStrgConfig[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[11]), .Q(slaveRegDo_qualStrgConfig[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[12]), .Q(slaveRegDo_qualStrgConfig[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[13]), .Q(slaveRegDo_qualStrgConfig[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[14]), .Q(slaveRegDo_qualStrgConfig[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(Q), .Q(slaveRegDo_qualStrgConfig[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(shift_en_reg_0), .Q(Q), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[2]), .Q(slaveRegDo_qualStrgConfig[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[3]), .Q(slaveRegDo_qualStrgConfig[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[4]), .Q(slaveRegDo_qualStrgConfig[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[5]), .Q(slaveRegDo_qualStrgConfig[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[6]), .Q(slaveRegDo_qualStrgConfig[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[7]), .Q(slaveRegDo_qualStrgConfig[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[8]), .Q(slaveRegDo_qualStrgConfig[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[9]), .Q(slaveRegDo_qualStrgConfig[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[10]), .Q(slaveRegDo_qualStrgConfig[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_2 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_2_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h0104)) shift_en_i_1 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1_n_0), .Q(E), .R(1'b0)); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[0]_i_1 (.I0(slaveRegDo_qualStrgConfig[0]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[0]_0 ), .O(D[0])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[10]_i_1 (.I0(slaveRegDo_qualStrgConfig[10]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[10]_0 ), .O(D[10])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[11]_i_1 (.I0(slaveRegDo_qualStrgConfig[11]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[11]_0 ), .O(D[11])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[12]_i_1 (.I0(slaveRegDo_qualStrgConfig[12]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[12]_0 ), .O(D[12])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[13]_i_1 (.I0(slaveRegDo_qualStrgConfig[13]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[13]_0 ), .O(D[13])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[14]_i_1 (.I0(slaveRegDo_qualStrgConfig[14]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[14]_0 ), .O(D[14])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[1]_i_1 (.I0(slaveRegDo_qualStrgConfig[1]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[1]_0 ), .O(D[1])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[2]_i_1 (.I0(slaveRegDo_qualStrgConfig[2]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[2]_0 ), .O(D[2])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[3]_i_1 (.I0(slaveRegDo_qualStrgConfig[3]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[3]_0 ), .O(D[3])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[4]_i_1 (.I0(slaveRegDo_qualStrgConfig[4]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[4]_0 ), .O(D[4])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[5]_i_1 (.I0(slaveRegDo_qualStrgConfig[5]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[5]_0 ), .O(D[5])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[6]_i_1 (.I0(slaveRegDo_qualStrgConfig[6]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[6]_0 ), .O(D[6])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[7]_i_1 (.I0(slaveRegDo_qualStrgConfig[7]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[7]_0 ), .O(D[7])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[8]_i_1 (.I0(slaveRegDo_qualStrgConfig[8]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[8]_0 ), .O(D[8])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[9]_i_1 (.I0(slaveRegDo_qualStrgConfig[9]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[9]_0 ), .O(D[9])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1 (.I0(serial_dout), .I1(data_out_sel), .I2(shift_en_reg_0), .O(qual_strg_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45 (E, D, Q, qual_strg_config_cs_serial_output, s_dclk_o, \G_1PIPE_IFACE.s_di_r_reg[15] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[4] , \parallel_dout_reg[0]_0 , \parallel_dout_reg[1]_0 , \parallel_dout_reg[2]_0 , \parallel_dout_reg[3]_0 , \parallel_dout_reg[4]_0 , \parallel_dout_reg[5]_0 , \parallel_dout_reg[6]_0 , \parallel_dout_reg[7]_0 , \parallel_dout_reg[8]_0 , \parallel_dout_reg[9]_0 , \parallel_dout_reg[10]_0 , \parallel_dout_reg[11]_0 , \parallel_dout_reg[12]_0 , \parallel_dout_reg[13]_0 , \parallel_dout_reg[14]_0 , shift_en_reg_0, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[11] , s_di_o);
output [0:0]E; output [14:0]D; output [0:0]Q; output qual_strg_config_cs_serial_output; input s_dclk_o; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input \parallel_dout_reg[0]_0 ; input \parallel_dout_reg[1]_0 ; input \parallel_dout_reg[2]_0 ; input \parallel_dout_reg[3]_0 ; input \parallel_dout_reg[4]_0 ; input \parallel_dout_reg[5]_0 ; input \parallel_dout_reg[6]_0 ; input \parallel_dout_reg[7]_0 ; input \parallel_dout_reg[8]_0 ; input \parallel_dout_reg[9]_0 ; input \parallel_dout_reg[10]_0 ; input \parallel_dout_reg[11]_0 ; input \parallel_dout_reg[12]_0 ; input \parallel_dout_reg[13]_0 ; input \parallel_dout_reg[14]_0 ; input [0:0]shift_en_reg_0; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[11] ; input [14:0]s_di_o; wire [14:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [0:0]Q; wire clear; wire [3:0]cnt_reg__0; wire [3:0]current_state; wire \current_state[3]_i_2_n_0 ; wire \current_state[3]_i_3_n_0 ; wire \current_state[3]_i_4_n_0 ; wire data_out_sel; wire data_out_sel_i_1_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire qual_strg_config_cs_serial_output; wire [1:0]s_daddr_o; wire s_dclk_o; wire [14:0]s_di_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1_n_0 ; wire \shadow[10]_i_1_n_0 ; wire \shadow[11]_i_1_n_0 ; wire \shadow[12]_i_1_n_0 ; wire \shadow[13]_i_1_n_0 ; wire \shadow[14]_i_1_n_0 ; wire \shadow[15]_i_2_n_0 ; wire \shadow[1]_i_1_n_0 ; wire \shadow[2]_i_1_n_0 ; wire \shadow[3]_i_1_n_0 ; wire \shadow[4]_i_1_n_0 ; wire \shadow[5]_i_1_n_0 ; wire \shadow[6]_i_1_n_0 ; wire \shadow[7]_i_1_n_0 ; wire \shadow[8]_i_1_n_0 ; wire \shadow[9]_i_1_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1_n_0; wire [0:0]shift_en_reg_0; wire [14:0]slaveRegDo_qualStrgConfig; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1 (.I0(cnt_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1 (.I0(cnt_reg__0[0]), .I1(cnt_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1 (.I0(cnt_reg__0[1]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2 (.I0(cnt_reg__0[2]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[1]), .I3(cnt_reg__0[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg__0[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg__0[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg__0[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg__0[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1 (.I0(\current_state[3]_i_4_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1 (.I0(s_dwe_o), .I1(\current_state[3]_i_4_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1 (.I0(current_state[1]), .I1(\current_state[3]_i_2_n_0 ), .I2(\current_state[3]_i_4_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1 (.I0(\current_state[3]_i_2_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2 (.I0(cnt_reg__0[2]), .I1(cnt_reg__0[0]), .I2(cnt_reg__0[1]), .I3(cnt_reg__0[3]), .O(\current_state[3]_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \current_state[3]_i_3 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(s_daddr_o[0]), .I2(s_daddr_o[1]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ), .O(\current_state[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); LUT4 #( .INIT(16'h0004)) data_out_sel_i_1 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[1]), .Q(slaveRegDo_qualStrgConfig[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[11]), .Q(slaveRegDo_qualStrgConfig[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[12]), .Q(slaveRegDo_qualStrgConfig[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[13]), .Q(slaveRegDo_qualStrgConfig[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[14]), .Q(slaveRegDo_qualStrgConfig[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(Q), .Q(slaveRegDo_qualStrgConfig[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(shift_en_reg_0), .Q(Q), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[2]), .Q(slaveRegDo_qualStrgConfig[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[3]), .Q(slaveRegDo_qualStrgConfig[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[4]), .Q(slaveRegDo_qualStrgConfig[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[5]), .Q(slaveRegDo_qualStrgConfig[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[6]), .Q(slaveRegDo_qualStrgConfig[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[7]), .Q(slaveRegDo_qualStrgConfig[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[8]), .Q(slaveRegDo_qualStrgConfig[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[9]), .Q(slaveRegDo_qualStrgConfig[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_qualStrgConfig[10]), .Q(slaveRegDo_qualStrgConfig[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_2 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_2_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h0104)) shift_en_i_1 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1_n_0), .Q(E), .R(1'b0)); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[0]_i_1 (.I0(slaveRegDo_qualStrgConfig[0]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[0]_0 ), .O(D[0])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[10]_i_1 (.I0(slaveRegDo_qualStrgConfig[10]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[10]_0 ), .O(D[10])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[11]_i_1 (.I0(slaveRegDo_qualStrgConfig[11]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[11]_0 ), .O(D[11])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[12]_i_1 (.I0(slaveRegDo_qualStrgConfig[12]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[12]_0 ), .O(D[12])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[13]_i_1 (.I0(slaveRegDo_qualStrgConfig[13]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[13]_0 ), .O(D[13])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[14]_i_1 (.I0(slaveRegDo_qualStrgConfig[14]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[14]_0 ), .O(D[14])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[1]_i_1 (.I0(slaveRegDo_qualStrgConfig[1]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[1]_0 ), .O(D[1])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[2]_i_1 (.I0(slaveRegDo_qualStrgConfig[2]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[2]_0 ), .O(D[2])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[3]_i_1 (.I0(slaveRegDo_qualStrgConfig[3]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[3]_0 ), .O(D[3])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[4]_i_1 (.I0(slaveRegDo_qualStrgConfig[4]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[4]_0 ), .O(D[4])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[5]_i_1 (.I0(slaveRegDo_qualStrgConfig[5]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[5]_0 ), .O(D[5])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[6]_i_1 (.I0(slaveRegDo_qualStrgConfig[6]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[6]_0 ), .O(D[6])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[7]_i_1 (.I0(slaveRegDo_qualStrgConfig[7]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[7]_0 ), .O(D[7])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[8]_i_1 (.I0(slaveRegDo_qualStrgConfig[8]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[8]_0 ), .O(D[8])); LUT4 #( .INIT(16'h2F20)) \slaveRegDo_mux_6[9]_i_1 (.I0(slaveRegDo_qualStrgConfig[9]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I3(\parallel_dout_reg[9]_0 ), .O(D[9])); LUT3 #( .INIT(8'hB8)) u_srlD_i_1 (.I0(serial_dout), .I1(data_out_sel), .I2(shift_en_reg_0), .O(qual_strg_config_cs_serial_output)); endmodule
8
2,470
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46 (\slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[11] , \slaveRegDo_mux_3_reg[9] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[7] , \slaveRegDo_mux_3_reg[5] , \slaveRegDo_mux_3_reg[4] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[13] , \slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[6] , E, capture_ctrl_config_serial_output, \slaveRegDo_ff8_reg[7] , s_daddr_o, \slaveRegDo_ff8_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , Q, \xsdb_reg_reg[8] , \slaveRegDo_ff9_reg[8] , \slaveRegDo_ffa_reg[15] , \slaveRegDo_ff8_reg[7]_0 , \slaveRegDo_ff8_reg[7]_1 , \xsdb_reg_reg[15] , \xsdb_reg_reg[15]_0 , D, \xsdb_reg_reg[14] , \xsdb_reg_reg[13] , \xsdb_reg_reg[12] , \xsdb_reg_reg[11] , \xsdb_reg_reg[10] , \xsdb_reg_reg[9] , \xsdb_reg_reg[8]_0 , \xsdb_reg_reg[7] , \xsdb_reg_reg[6] , \xsdb_reg_reg[5] , \xsdb_reg_reg[4] , \xsdb_reg_reg[3] , \xsdb_reg_reg[2] , debug_data_in, s_dclk_o, shift_en_reg_0, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, s_den_o, s_di_o); output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[11] ; output \slaveRegDo_mux_3_reg[9] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[7] ; output \slaveRegDo_mux_3_reg[5] ; output \slaveRegDo_mux_3_reg[4] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[13] ; output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[6] ; output [0:0]E; output capture_ctrl_config_serial_output; input \slaveRegDo_ff8_reg[7] ; input [12:0]s_daddr_o; input \slaveRegDo_ff8_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input [4:0]Q; input \xsdb_reg_reg[8] ; input \slaveRegDo_ff9_reg[8] ; input \slaveRegDo_ffa_reg[15] ; input \slaveRegDo_ff8_reg[7]_0 ; input \slaveRegDo_ff8_reg[7]_1 ; input [15:0]\xsdb_reg_reg[15] ; input \xsdb_reg_reg[15]_0 ; input [15:0]D; input \xsdb_reg_reg[14] ; input \xsdb_reg_reg[13] ; input \xsdb_reg_reg[12] ; input \xsdb_reg_reg[11] ; input \xsdb_reg_reg[10] ; input \xsdb_reg_reg[9] ; input \xsdb_reg_reg[8]_0 ; input \xsdb_reg_reg[7] ; input \xsdb_reg_reg[6] ; input \xsdb_reg_reg[5] ; input \xsdb_reg_reg[4] ; input \xsdb_reg_reg[3] ; input \xsdb_reg_reg[2] ; input [1:0]debug_data_in; input s_dclk_o; input [0:0]shift_en_reg_0; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input s_den_o; input [14:0]s_di_o; wire [15:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [4:0]Q; wire capture_ctrl_config_serial_output; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__0_n_0 ; wire \current_state[3]_i_3__0_n_0 ; wire \current_state[3]_i_4__0_n_0 ; wire \current_state[3]_i_5_n_0 ; wire \current_state[3]_i_6_n_0 ; wire data_out_sel; wire data_out_sel_i_1__0_n_0; wire [1:0]debug_data_in; wire [3:0]next_state; wire [3:0]p_0_in; wire [12:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__0_n_0 ; wire \shadow[10]_i_1__0_n_0 ; wire \shadow[11]_i_1__0_n_0 ; wire \shadow[12]_i_1__0_n_0 ; wire \shadow[13]_i_1__0_n_0 ; wire \shadow[14]_i_1__0_n_0 ; wire \shadow[15]_i_1__0_n_0 ; wire \shadow[1]_i_1__0_n_0 ; wire \shadow[2]_i_1__0_n_0 ; wire \shadow[3]_i_1__0_n_0 ; wire \shadow[4]_i_1__0_n_0 ; wire \shadow[5]_i_1__0_n_0 ; wire \shadow[6]_i_1__0_n_0 ; wire \shadow[7]_i_1__0_n_0 ; wire \shadow[8]_i_1__0_n_0 ; wire \shadow[9]_i_1__0_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__0_n_0; wire [0:0]shift_en_reg_0; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[7] ; wire \slaveRegDo_ff8_reg[7]_0 ; wire \slaveRegDo_ff8_reg[7]_1 ; wire \slaveRegDo_ff9_reg[8] ; wire \slaveRegDo_ffa_reg[15] ; wire [15:0]slaveRegDo_fff; wire \slaveRegDo_mux_3[0]_i_2_n_0 ; wire \slaveRegDo_mux_3[11]_i_2_n_0 ; wire \slaveRegDo_mux_3[1]_i_2_n_0 ; wire \slaveRegDo_mux_3[2]_i_2_n_0 ; wire \slaveRegDo_mux_3[3]_i_2_n_0 ; wire \slaveRegDo_mux_3[4]_i_2_n_0 ; wire \slaveRegDo_mux_3[5]_i_2_n_0 ; wire \slaveRegDo_mux_3[7]_i_2_n_0 ; wire \slaveRegDo_mux_3[8]_i_2_n_0 ; wire \slaveRegDo_mux_3[9]_i_2_n_0 ; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[11] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[4] ; wire \slaveRegDo_mux_3_reg[5] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[7] ; wire \slaveRegDo_mux_3_reg[8] ; wire \slaveRegDo_mux_3_reg[9] ; wire \xsdb_reg_reg[10] ; wire \xsdb_reg_reg[11] ; wire \xsdb_reg_reg[12] ; wire \xsdb_reg_reg[13] ; wire \xsdb_reg_reg[14] ; wire [15:0]\xsdb_reg_reg[15] ; wire \xsdb_reg_reg[15]_0 ; wire \xsdb_reg_reg[2] ; wire \xsdb_reg_reg[3] ; wire \xsdb_reg_reg[4] ; wire \xsdb_reg_reg[5] ; wire \xsdb_reg_reg[6] ; wire \xsdb_reg_reg[7] ; wire \xsdb_reg_reg[8] ; wire \xsdb_reg_reg[8]_0 ; wire \xsdb_reg_reg[9] ; LUT3 #( .INIT(8'hB8)) \I_YESLUT6.U_SRL32_D_i_1 (.I0(serial_dout), .I1(data_out_sel), .I2(shift_en_reg_0), .O(capture_ctrl_config_serial_output)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__0 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__0 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__0 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__0 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__0 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__0 (.I0(\current_state[3]_i_4__0_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__0_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__0_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__0 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__0_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__0_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__0 (.I0(current_state[1]), .I1(\current_state[3]_i_2__0_n_0 ), .I2(\current_state[3]_i_4__0_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__0 (.I0(\current_state[3]_i_2__0_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__0_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__0_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__0 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFBFFFFFFF)) \current_state[3]_i_3__0 (.I0(\current_state[3]_i_5_n_0 ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[5]), .I4(s_daddr_o[4]), .I5(\current_state[3]_i_6_n_0 ), .O(\current_state[3]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__0 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__0_n_0 )); LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_5 (.I0(s_daddr_o[7]), .I1(s_daddr_o[6]), .I2(s_daddr_o[9]), .I3(s_daddr_o[8]), .O(\current_state[3]_i_5_n_0 )); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) \current_state[3]_i_6 (.I0(s_daddr_o[12]), .I1(s_den_o), .I2(s_daddr_o[10]), .I3(s_daddr_o[11]), .I4(s_daddr_o[1]), .I5(s_daddr_o[0]), .O(\current_state[3]_i_6_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__0 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__0_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__0_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[1]), .Q(slaveRegDo_fff[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[11]), .Q(slaveRegDo_fff[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[12]), .Q(slaveRegDo_fff[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[13]), .Q(slaveRegDo_fff[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[14]), .Q(slaveRegDo_fff[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[15]), .Q(slaveRegDo_fff[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(shift_en_reg_0), .Q(slaveRegDo_fff[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[2]), .Q(slaveRegDo_fff[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[3]), .Q(slaveRegDo_fff[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[4]), .Q(slaveRegDo_fff[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[5]), .Q(slaveRegDo_fff[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[6]), .Q(slaveRegDo_fff[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[7]), .Q(slaveRegDo_fff[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[8]), .Q(slaveRegDo_fff[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[9]), .Q(slaveRegDo_fff[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[10]), .Q(slaveRegDo_fff[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__0 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__0 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__0 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__0 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__0 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__0 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__0_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__0 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__0 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__0 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__0 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__0 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__0 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__0 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__0 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__0 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__0 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__0 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__0_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__0_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hACF0AC00AC00AC00)) \slaveRegDo_mux_3[0]_i_1 (.I0(\slaveRegDo_mux_3[0]_i_2_n_0 ), .I1(\slaveRegDo_ff8_reg[7] ), .I2(s_daddr_o[2]), .I3(s_daddr_o[3]), .I4(s_daddr_o[1]), .I5(s_daddr_o[0]), .O(\slaveRegDo_mux_3_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[0]_i_2 (.I0(slaveRegDo_fff[0]), .I1(\xsdb_reg_reg[15] [0]), .I2(s_daddr_o[1]), .I3(debug_data_in[0]), .I4(s_daddr_o[0]), .I5(D[0]), .O(\slaveRegDo_mux_3[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[10]_i_2 (.I0(slaveRegDo_fff[10]), .I1(\xsdb_reg_reg[15] [10]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[10] ), .I4(s_daddr_o[0]), .I5(D[10]), .O(\slaveRegDo_mux_3_reg[10] )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[11]_i_1 (.I0(\slaveRegDo_mux_3[11]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[4]), .O(\slaveRegDo_mux_3_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[11]_i_2 (.I0(slaveRegDo_fff[11]), .I1(\xsdb_reg_reg[15] [11]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[11] ), .I4(s_daddr_o[0]), .I5(D[11]), .O(\slaveRegDo_mux_3[11]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[12]_i_3 (.I0(slaveRegDo_fff[12]), .I1(\xsdb_reg_reg[15] [12]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[12] ), .I4(s_daddr_o[0]), .I5(D[12]), .O(\slaveRegDo_mux_3_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[13]_i_2 (.I0(slaveRegDo_fff[13]), .I1(\xsdb_reg_reg[15] [13]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[13] ), .I4(s_daddr_o[0]), .I5(D[13]), .O(\slaveRegDo_mux_3_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[14]_i_2 (.I0(slaveRegDo_fff[14]), .I1(\xsdb_reg_reg[15] [14]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[14] ), .I4(s_daddr_o[0]), .I5(D[14]), .O(\slaveRegDo_mux_3_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[15]_i_5 (.I0(slaveRegDo_fff[15]), .I1(\xsdb_reg_reg[15] [15]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[15]_0 ), .I4(s_daddr_o[0]), .I5(D[15]), .O(\slaveRegDo_mux_3_reg[15] )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[1]_i_1 (.I0(\slaveRegDo_mux_3[1]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[7]_1 ), .O(\slaveRegDo_mux_3_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[1]_i_2 (.I0(slaveRegDo_fff[1]), .I1(\xsdb_reg_reg[15] [1]), .I2(s_daddr_o[1]), .I3(debug_data_in[1]), .I4(s_daddr_o[0]), .I5(D[1]), .O(\slaveRegDo_mux_3[1]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[2]_i_1 (.I0(\slaveRegDo_mux_3[2]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[7]_0 ), .O(\slaveRegDo_mux_3_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[2]_i_2 (.I0(slaveRegDo_fff[2]), .I1(\xsdb_reg_reg[15] [2]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[2] ), .I4(s_daddr_o[0]), .I5(D[2]), .O(\slaveRegDo_mux_3[2]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[3]_i_1 (.I0(\slaveRegDo_mux_3[3]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ffa_reg[15] ), .O(\slaveRegDo_mux_3_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[3]_i_2 (.I0(slaveRegDo_fff[3]), .I1(\xsdb_reg_reg[15] [3]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[3] ), .I4(s_daddr_o[0]), .I5(D[3]), .O(\slaveRegDo_mux_3[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[4]_i_1 (.I0(\slaveRegDo_mux_3[4]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[0]), .O(\slaveRegDo_mux_3_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[4]_i_2 (.I0(slaveRegDo_fff[4]), .I1(\xsdb_reg_reg[15] [4]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[4] ), .I4(s_daddr_o[0]), .I5(D[4]), .O(\slaveRegDo_mux_3[4]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[5]_i_1 (.I0(\slaveRegDo_mux_3[5]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[1]), .O(\slaveRegDo_mux_3_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[5]_i_2 (.I0(slaveRegDo_fff[5]), .I1(\xsdb_reg_reg[15] [5]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[5] ), .I4(s_daddr_o[0]), .I5(D[5]), .O(\slaveRegDo_mux_3[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[6]_i_3 (.I0(slaveRegDo_fff[6]), .I1(\xsdb_reg_reg[15] [6]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[6] ), .I4(s_daddr_o[0]), .I5(D[6]), .O(\slaveRegDo_mux_3_reg[6] )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[7]_i_1 (.I0(\slaveRegDo_mux_3[7]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[2]), .O(\slaveRegDo_mux_3_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[7]_i_2 (.I0(slaveRegDo_fff[7]), .I1(\xsdb_reg_reg[15] [7]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[7] ), .I4(s_daddr_o[0]), .I5(D[7]), .O(\slaveRegDo_mux_3[7]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[8]_i_1 (.I0(\slaveRegDo_mux_3[8]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\xsdb_reg_reg[8] ), .O(\slaveRegDo_mux_3_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[8]_i_2 (.I0(slaveRegDo_fff[8]), .I1(\xsdb_reg_reg[15] [8]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[8]_0 ), .I4(s_daddr_o[0]), .I5(D[8]), .O(\slaveRegDo_mux_3[8]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[9]_i_1 (.I0(\slaveRegDo_mux_3[9]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[3]), .O(\slaveRegDo_mux_3_reg[9] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[9]_i_2 (.I0(slaveRegDo_fff[9]), .I1(\xsdb_reg_reg[15] [9]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[9] ), .I4(s_daddr_o[0]), .I5(D[9]), .O(\slaveRegDo_mux_3[9]_i_2_n_0 )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46 (\slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[11] , \slaveRegDo_mux_3_reg[9] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[7] , \slaveRegDo_mux_3_reg[5] , \slaveRegDo_mux_3_reg[4] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[13] , \slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[6] , E, capture_ctrl_config_serial_output, \slaveRegDo_ff8_reg[7] , s_daddr_o, \slaveRegDo_ff8_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , Q, \xsdb_reg_reg[8] , \slaveRegDo_ff9_reg[8] , \slaveRegDo_ffa_reg[15] , \slaveRegDo_ff8_reg[7]_0 , \slaveRegDo_ff8_reg[7]_1 , \xsdb_reg_reg[15] , \xsdb_reg_reg[15]_0 , D, \xsdb_reg_reg[14] , \xsdb_reg_reg[13] , \xsdb_reg_reg[12] , \xsdb_reg_reg[11] , \xsdb_reg_reg[10] , \xsdb_reg_reg[9] , \xsdb_reg_reg[8]_0 , \xsdb_reg_reg[7] , \xsdb_reg_reg[6] , \xsdb_reg_reg[5] , \xsdb_reg_reg[4] , \xsdb_reg_reg[3] , \xsdb_reg_reg[2] , debug_data_in, s_dclk_o, shift_en_reg_0, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, s_den_o, s_di_o);
output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[11] ; output \slaveRegDo_mux_3_reg[9] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[7] ; output \slaveRegDo_mux_3_reg[5] ; output \slaveRegDo_mux_3_reg[4] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[13] ; output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[6] ; output [0:0]E; output capture_ctrl_config_serial_output; input \slaveRegDo_ff8_reg[7] ; input [12:0]s_daddr_o; input \slaveRegDo_ff8_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input [4:0]Q; input \xsdb_reg_reg[8] ; input \slaveRegDo_ff9_reg[8] ; input \slaveRegDo_ffa_reg[15] ; input \slaveRegDo_ff8_reg[7]_0 ; input \slaveRegDo_ff8_reg[7]_1 ; input [15:0]\xsdb_reg_reg[15] ; input \xsdb_reg_reg[15]_0 ; input [15:0]D; input \xsdb_reg_reg[14] ; input \xsdb_reg_reg[13] ; input \xsdb_reg_reg[12] ; input \xsdb_reg_reg[11] ; input \xsdb_reg_reg[10] ; input \xsdb_reg_reg[9] ; input \xsdb_reg_reg[8]_0 ; input \xsdb_reg_reg[7] ; input \xsdb_reg_reg[6] ; input \xsdb_reg_reg[5] ; input \xsdb_reg_reg[4] ; input \xsdb_reg_reg[3] ; input \xsdb_reg_reg[2] ; input [1:0]debug_data_in; input s_dclk_o; input [0:0]shift_en_reg_0; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input s_den_o; input [14:0]s_di_o; wire [15:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [4:0]Q; wire capture_ctrl_config_serial_output; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__0_n_0 ; wire \current_state[3]_i_3__0_n_0 ; wire \current_state[3]_i_4__0_n_0 ; wire \current_state[3]_i_5_n_0 ; wire \current_state[3]_i_6_n_0 ; wire data_out_sel; wire data_out_sel_i_1__0_n_0; wire [1:0]debug_data_in; wire [3:0]next_state; wire [3:0]p_0_in; wire [12:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__0_n_0 ; wire \shadow[10]_i_1__0_n_0 ; wire \shadow[11]_i_1__0_n_0 ; wire \shadow[12]_i_1__0_n_0 ; wire \shadow[13]_i_1__0_n_0 ; wire \shadow[14]_i_1__0_n_0 ; wire \shadow[15]_i_1__0_n_0 ; wire \shadow[1]_i_1__0_n_0 ; wire \shadow[2]_i_1__0_n_0 ; wire \shadow[3]_i_1__0_n_0 ; wire \shadow[4]_i_1__0_n_0 ; wire \shadow[5]_i_1__0_n_0 ; wire \shadow[6]_i_1__0_n_0 ; wire \shadow[7]_i_1__0_n_0 ; wire \shadow[8]_i_1__0_n_0 ; wire \shadow[9]_i_1__0_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__0_n_0; wire [0:0]shift_en_reg_0; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[7] ; wire \slaveRegDo_ff8_reg[7]_0 ; wire \slaveRegDo_ff8_reg[7]_1 ; wire \slaveRegDo_ff9_reg[8] ; wire \slaveRegDo_ffa_reg[15] ; wire [15:0]slaveRegDo_fff; wire \slaveRegDo_mux_3[0]_i_2_n_0 ; wire \slaveRegDo_mux_3[11]_i_2_n_0 ; wire \slaveRegDo_mux_3[1]_i_2_n_0 ; wire \slaveRegDo_mux_3[2]_i_2_n_0 ; wire \slaveRegDo_mux_3[3]_i_2_n_0 ; wire \slaveRegDo_mux_3[4]_i_2_n_0 ; wire \slaveRegDo_mux_3[5]_i_2_n_0 ; wire \slaveRegDo_mux_3[7]_i_2_n_0 ; wire \slaveRegDo_mux_3[8]_i_2_n_0 ; wire \slaveRegDo_mux_3[9]_i_2_n_0 ; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[11] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[4] ; wire \slaveRegDo_mux_3_reg[5] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[7] ; wire \slaveRegDo_mux_3_reg[8] ; wire \slaveRegDo_mux_3_reg[9] ; wire \xsdb_reg_reg[10] ; wire \xsdb_reg_reg[11] ; wire \xsdb_reg_reg[12] ; wire \xsdb_reg_reg[13] ; wire \xsdb_reg_reg[14] ; wire [15:0]\xsdb_reg_reg[15] ; wire \xsdb_reg_reg[15]_0 ; wire \xsdb_reg_reg[2] ; wire \xsdb_reg_reg[3] ; wire \xsdb_reg_reg[4] ; wire \xsdb_reg_reg[5] ; wire \xsdb_reg_reg[6] ; wire \xsdb_reg_reg[7] ; wire \xsdb_reg_reg[8] ; wire \xsdb_reg_reg[8]_0 ; wire \xsdb_reg_reg[9] ; LUT3 #( .INIT(8'hB8)) \I_YESLUT6.U_SRL32_D_i_1 (.I0(serial_dout), .I1(data_out_sel), .I2(shift_en_reg_0), .O(capture_ctrl_config_serial_output)); LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__0 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__0 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__0 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__0 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__0 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__0 (.I0(\current_state[3]_i_4__0_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__0_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__0_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__0 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__0_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__0_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__0 (.I0(current_state[1]), .I1(\current_state[3]_i_2__0_n_0 ), .I2(\current_state[3]_i_4__0_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__0 (.I0(\current_state[3]_i_2__0_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__0_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__0_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__0 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFBFFFFFFF)) \current_state[3]_i_3__0 (.I0(\current_state[3]_i_5_n_0 ), .I1(s_daddr_o[2]), .I2(s_daddr_o[3]), .I3(s_daddr_o[5]), .I4(s_daddr_o[4]), .I5(\current_state[3]_i_6_n_0 ), .O(\current_state[3]_i_3__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__0 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__0_n_0 )); LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_5 (.I0(s_daddr_o[7]), .I1(s_daddr_o[6]), .I2(s_daddr_o[9]), .I3(s_daddr_o[8]), .O(\current_state[3]_i_5_n_0 )); LUT6 #( .INIT(64'hBFFFFFFFFFFFFFFF)) \current_state[3]_i_6 (.I0(s_daddr_o[12]), .I1(s_den_o), .I2(s_daddr_o[10]), .I3(s_daddr_o[11]), .I4(s_daddr_o[1]), .I5(s_daddr_o[0]), .O(\current_state[3]_i_6_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__0 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__0_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__0_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[1]), .Q(slaveRegDo_fff[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[11]), .Q(slaveRegDo_fff[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[12]), .Q(slaveRegDo_fff[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[13]), .Q(slaveRegDo_fff[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[14]), .Q(slaveRegDo_fff[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[15]), .Q(slaveRegDo_fff[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(shift_en_reg_0), .Q(slaveRegDo_fff[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[2]), .Q(slaveRegDo_fff[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[3]), .Q(slaveRegDo_fff[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[4]), .Q(slaveRegDo_fff[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[5]), .Q(slaveRegDo_fff[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[6]), .Q(slaveRegDo_fff[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[7]), .Q(slaveRegDo_fff[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[8]), .Q(slaveRegDo_fff[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[9]), .Q(slaveRegDo_fff[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(slaveRegDo_fff[10]), .Q(slaveRegDo_fff[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__0 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__0 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__0 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__0 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__0 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__0 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__0_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__0 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__0 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__0 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__0 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__0 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__0 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__0 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__0 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__0 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__0 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__0_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__0_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__0 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__0_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__0_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'hACF0AC00AC00AC00)) \slaveRegDo_mux_3[0]_i_1 (.I0(\slaveRegDo_mux_3[0]_i_2_n_0 ), .I1(\slaveRegDo_ff8_reg[7] ), .I2(s_daddr_o[2]), .I3(s_daddr_o[3]), .I4(s_daddr_o[1]), .I5(s_daddr_o[0]), .O(\slaveRegDo_mux_3_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[0]_i_2 (.I0(slaveRegDo_fff[0]), .I1(\xsdb_reg_reg[15] [0]), .I2(s_daddr_o[1]), .I3(debug_data_in[0]), .I4(s_daddr_o[0]), .I5(D[0]), .O(\slaveRegDo_mux_3[0]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[10]_i_2 (.I0(slaveRegDo_fff[10]), .I1(\xsdb_reg_reg[15] [10]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[10] ), .I4(s_daddr_o[0]), .I5(D[10]), .O(\slaveRegDo_mux_3_reg[10] )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[11]_i_1 (.I0(\slaveRegDo_mux_3[11]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[4]), .O(\slaveRegDo_mux_3_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[11]_i_2 (.I0(slaveRegDo_fff[11]), .I1(\xsdb_reg_reg[15] [11]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[11] ), .I4(s_daddr_o[0]), .I5(D[11]), .O(\slaveRegDo_mux_3[11]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[12]_i_3 (.I0(slaveRegDo_fff[12]), .I1(\xsdb_reg_reg[15] [12]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[12] ), .I4(s_daddr_o[0]), .I5(D[12]), .O(\slaveRegDo_mux_3_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[13]_i_2 (.I0(slaveRegDo_fff[13]), .I1(\xsdb_reg_reg[15] [13]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[13] ), .I4(s_daddr_o[0]), .I5(D[13]), .O(\slaveRegDo_mux_3_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[14]_i_2 (.I0(slaveRegDo_fff[14]), .I1(\xsdb_reg_reg[15] [14]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[14] ), .I4(s_daddr_o[0]), .I5(D[14]), .O(\slaveRegDo_mux_3_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[15]_i_5 (.I0(slaveRegDo_fff[15]), .I1(\xsdb_reg_reg[15] [15]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[15]_0 ), .I4(s_daddr_o[0]), .I5(D[15]), .O(\slaveRegDo_mux_3_reg[15] )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[1]_i_1 (.I0(\slaveRegDo_mux_3[1]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[7]_1 ), .O(\slaveRegDo_mux_3_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[1]_i_2 (.I0(slaveRegDo_fff[1]), .I1(\xsdb_reg_reg[15] [1]), .I2(s_daddr_o[1]), .I3(debug_data_in[1]), .I4(s_daddr_o[0]), .I5(D[1]), .O(\slaveRegDo_mux_3[1]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[2]_i_1 (.I0(\slaveRegDo_mux_3[2]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[7]_0 ), .O(\slaveRegDo_mux_3_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[2]_i_2 (.I0(slaveRegDo_fff[2]), .I1(\xsdb_reg_reg[15] [2]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[2] ), .I4(s_daddr_o[0]), .I5(D[2]), .O(\slaveRegDo_mux_3[2]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[3]_i_1 (.I0(\slaveRegDo_mux_3[3]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ffa_reg[15] ), .O(\slaveRegDo_mux_3_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[3]_i_2 (.I0(slaveRegDo_fff[3]), .I1(\xsdb_reg_reg[15] [3]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[3] ), .I4(s_daddr_o[0]), .I5(D[3]), .O(\slaveRegDo_mux_3[3]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[4]_i_1 (.I0(\slaveRegDo_mux_3[4]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[0]), .O(\slaveRegDo_mux_3_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[4]_i_2 (.I0(slaveRegDo_fff[4]), .I1(\xsdb_reg_reg[15] [4]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[4] ), .I4(s_daddr_o[0]), .I5(D[4]), .O(\slaveRegDo_mux_3[4]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[5]_i_1 (.I0(\slaveRegDo_mux_3[5]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[1]), .O(\slaveRegDo_mux_3_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[5]_i_2 (.I0(slaveRegDo_fff[5]), .I1(\xsdb_reg_reg[15] [5]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[5] ), .I4(s_daddr_o[0]), .I5(D[5]), .O(\slaveRegDo_mux_3[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[6]_i_3 (.I0(slaveRegDo_fff[6]), .I1(\xsdb_reg_reg[15] [6]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[6] ), .I4(s_daddr_o[0]), .I5(D[6]), .O(\slaveRegDo_mux_3_reg[6] )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[7]_i_1 (.I0(\slaveRegDo_mux_3[7]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff9_reg[8] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[2]), .O(\slaveRegDo_mux_3_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[7]_i_2 (.I0(slaveRegDo_fff[7]), .I1(\xsdb_reg_reg[15] [7]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[7] ), .I4(s_daddr_o[0]), .I5(D[7]), .O(\slaveRegDo_mux_3[7]_i_2_n_0 )); LUT4 #( .INIT(16'h8C80)) \slaveRegDo_mux_3[8]_i_1 (.I0(\slaveRegDo_mux_3[8]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\xsdb_reg_reg[8] ), .O(\slaveRegDo_mux_3_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[8]_i_2 (.I0(slaveRegDo_fff[8]), .I1(\xsdb_reg_reg[15] [8]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[8]_0 ), .I4(s_daddr_o[0]), .I5(D[8]), .O(\slaveRegDo_mux_3[8]_i_2_n_0 )); LUT6 #( .INIT(64'h8C8C8C808C808C80)) \slaveRegDo_mux_3[9]_i_1 (.I0(\slaveRegDo_mux_3[9]_i_2_n_0 ), .I1(s_daddr_o[3]), .I2(s_daddr_o[2]), .I3(\slaveRegDo_ff8_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I5(Q[3]), .O(\slaveRegDo_mux_3_reg[9] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_3[9]_i_2 (.I0(slaveRegDo_fff[9]), .I1(\xsdb_reg_reg[15] [9]), .I2(s_daddr_o[1]), .I3(\xsdb_reg_reg[9] ), .I4(s_daddr_o[0]), .I5(D[9]), .O(\slaveRegDo_mux_3[9]_i_2_n_0 )); endmodule
8
2,471
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
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module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__7_n_0 ; wire \current_state[3]_i_3__7_n_0 ; wire \current_state[3]_i_4__7_n_0 ; wire data_out_sel; wire data_out_sel_i_1__7_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__7_n_0 ; wire \shadow[10]_i_1__7_n_0 ; wire \shadow[11]_i_1__7_n_0 ; wire \shadow[12]_i_1__7_n_0 ; wire \shadow[13]_i_1__7_n_0 ; wire \shadow[14]_i_1__7_n_0 ; wire \shadow[15]_i_1__7_n_0 ; wire \shadow[1]_i_1__7_n_0 ; wire \shadow[2]_i_1__7_n_0 ; wire \shadow[3]_i_1__7_n_0 ; wire \shadow[4]_i_1__7_n_0 ; wire \shadow[5]_i_1__7_n_0 ; wire \shadow[6]_i_1__7_n_0 ; wire \shadow[7]_i_1__7_n_0 ; wire \shadow[8]_i_1__7_n_0 ; wire \shadow[9]_i_1__7_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__7_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__7 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__7 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__7 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__7 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__7 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__7 (.I0(\current_state[3]_i_4__7_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__7_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__7_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__7 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__7_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__7_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__7 (.I0(current_state[1]), .I1(\current_state[3]_i_2__7_n_0 ), .I2(\current_state[3]_i_4__7_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__7 (.I0(\current_state[3]_i_2__7_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__7_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__7_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__7 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__7_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \current_state[3]_i_3__7 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__7 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__7_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__7 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__7_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__7_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__7 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__7 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__7 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__7 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__7 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__7 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__7_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__7 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__7 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__7 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__7 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__7 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__7 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__7 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__7 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__7 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__7 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__7_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__7 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__7_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__7_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__6 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__7_n_0 ; wire \current_state[3]_i_3__7_n_0 ; wire \current_state[3]_i_4__7_n_0 ; wire data_out_sel; wire data_out_sel_i_1__7_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__7_n_0 ; wire \shadow[10]_i_1__7_n_0 ; wire \shadow[11]_i_1__7_n_0 ; wire \shadow[12]_i_1__7_n_0 ; wire \shadow[13]_i_1__7_n_0 ; wire \shadow[14]_i_1__7_n_0 ; wire \shadow[15]_i_1__7_n_0 ; wire \shadow[1]_i_1__7_n_0 ; wire \shadow[2]_i_1__7_n_0 ; wire \shadow[3]_i_1__7_n_0 ; wire \shadow[4]_i_1__7_n_0 ; wire \shadow[5]_i_1__7_n_0 ; wire \shadow[6]_i_1__7_n_0 ; wire \shadow[7]_i_1__7_n_0 ; wire \shadow[8]_i_1__7_n_0 ; wire \shadow[9]_i_1__7_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__7_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__7 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__7 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__7 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__7 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__7 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__7 (.I0(\current_state[3]_i_4__7_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__7_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__7_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__7 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__7_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__7_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__7 (.I0(current_state[1]), .I1(\current_state[3]_i_2__7_n_0 ), .I2(\current_state[3]_i_4__7_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__7 (.I0(\current_state[3]_i_2__7_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__7_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__7_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__7 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__7_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \current_state[3]_i_3__7 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__7 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__7_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__7 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__7_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__7_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__7 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__7 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__7 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__7 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__7 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__7 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__7_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__7 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__7 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__7 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__7 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__7 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__7 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__7 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__7 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__7 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__7_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__7 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__7_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__7_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__7 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__7_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__7_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__6 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,472
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6 (\slaveRegDo_mux_4_reg[15] , \slaveRegDo_mux_4_reg[14] , \slaveRegDo_mux_4_reg[13] , \slaveRegDo_mux_4_reg[12] , \slaveRegDo_mux_4_reg[11] , \slaveRegDo_mux_4_reg[10] , \slaveRegDo_mux_4_reg[9] , \slaveRegDo_mux_4_reg[8] , \slaveRegDo_mux_4_reg[7] , \slaveRegDo_mux_4_reg[6] , \slaveRegDo_mux_4_reg[5] , \slaveRegDo_mux_4_reg[4] , \slaveRegDo_mux_4_reg[3] , \slaveRegDo_mux_4_reg[2] , \slaveRegDo_mux_4_reg[1] , \slaveRegDo_mux_4_reg[0] , E, mu_config_cs_serial_output, \G_1PIPE_IFACE.s_daddr_r_reg[3] , \parallel_dout_reg[15]_0 , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 , \parallel_dout_reg[14]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 , \parallel_dout_reg[13]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 , \parallel_dout_reg[12]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 , \parallel_dout_reg[11]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 , \parallel_dout_reg[10]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 , \parallel_dout_reg[9]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 , \parallel_dout_reg[8]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 , \parallel_dout_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 , \parallel_dout_reg[6]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 , \parallel_dout_reg[5]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 , \parallel_dout_reg[4]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 , \parallel_dout_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 , \parallel_dout_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 , \parallel_dout_reg[1]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 , \parallel_dout_reg[0]_0 , s_do_o, Q, \parallel_dout_reg[15]_1 , s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o); output \slaveRegDo_mux_4_reg[15] ; output \slaveRegDo_mux_4_reg[14] ; output \slaveRegDo_mux_4_reg[13] ; output \slaveRegDo_mux_4_reg[12] ; output \slaveRegDo_mux_4_reg[11] ; output \slaveRegDo_mux_4_reg[10] ; output \slaveRegDo_mux_4_reg[9] ; output \slaveRegDo_mux_4_reg[8] ; output \slaveRegDo_mux_4_reg[7] ; output \slaveRegDo_mux_4_reg[6] ; output \slaveRegDo_mux_4_reg[5] ; output \slaveRegDo_mux_4_reg[4] ; output \slaveRegDo_mux_4_reg[3] ; output \slaveRegDo_mux_4_reg[2] ; output \slaveRegDo_mux_4_reg[1] ; output \slaveRegDo_mux_4_reg[0] ; output [0:0]E; output [0:0]mu_config_cs_serial_output; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \parallel_dout_reg[15]_0 ; input [6:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; input \parallel_dout_reg[14]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; input \parallel_dout_reg[13]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ; input \parallel_dout_reg[12]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ; input \parallel_dout_reg[11]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ; input \parallel_dout_reg[10]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ; input \parallel_dout_reg[9]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ; input \parallel_dout_reg[8]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ; input \parallel_dout_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ; input \parallel_dout_reg[6]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ; input \parallel_dout_reg[5]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ; input \parallel_dout_reg[4]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ; input \parallel_dout_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ; input \parallel_dout_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ; input \parallel_dout_reg[1]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ; input \parallel_dout_reg[0]_0 ; input [15:0]s_do_o; input [15:0]Q; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [15:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__8_n_0 ; wire \current_state[3]_i_3__8_n_0 ; wire \current_state[3]_i_4__8_n_0 ; wire data_out_sel; wire data_out_sel_i_1__8_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [6:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__8_n_0 ; wire \shadow[10]_i_1__8_n_0 ; wire \shadow[11]_i_1__8_n_0 ; wire \shadow[12]_i_1__8_n_0 ; wire \shadow[13]_i_1__8_n_0 ; wire \shadow[14]_i_1__8_n_0 ; wire \shadow[15]_i_1__8_n_0 ; wire \shadow[1]_i_1__8_n_0 ; wire \shadow[2]_i_1__8_n_0 ; wire \shadow[3]_i_1__8_n_0 ; wire \shadow[4]_i_1__8_n_0 ; wire \shadow[5]_i_1__8_n_0 ; wire \shadow[6]_i_1__8_n_0 ; wire \shadow[7]_i_1__8_n_0 ; wire \shadow[8]_i_1__8_n_0 ; wire \shadow[9]_i_1__8_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__8_n_0; wire [15:0]\slaveRegDo_muConfig[4107]_7 ; wire \slaveRegDo_mux_4[0]_i_2_n_0 ; wire \slaveRegDo_mux_4[10]_i_2_n_0 ; wire \slaveRegDo_mux_4[11]_i_2_n_0 ; wire \slaveRegDo_mux_4[12]_i_2_n_0 ; wire \slaveRegDo_mux_4[13]_i_2_n_0 ; wire \slaveRegDo_mux_4[14]_i_2_n_0 ; wire \slaveRegDo_mux_4[15]_i_2_n_0 ; wire \slaveRegDo_mux_4[1]_i_2_n_0 ; wire \slaveRegDo_mux_4[2]_i_2_n_0 ; wire \slaveRegDo_mux_4[3]_i_2_n_0 ; wire \slaveRegDo_mux_4[4]_i_2_n_0 ; wire \slaveRegDo_mux_4[5]_i_2_n_0 ; wire \slaveRegDo_mux_4[6]_i_2_n_0 ; wire \slaveRegDo_mux_4[7]_i_2_n_0 ; wire \slaveRegDo_mux_4[8]_i_2_n_0 ; wire \slaveRegDo_mux_4[9]_i_2_n_0 ; wire \slaveRegDo_mux_4_reg[0] ; wire \slaveRegDo_mux_4_reg[10] ; wire \slaveRegDo_mux_4_reg[11] ; wire \slaveRegDo_mux_4_reg[12] ; wire \slaveRegDo_mux_4_reg[13] ; wire \slaveRegDo_mux_4_reg[14] ; wire \slaveRegDo_mux_4_reg[15] ; wire \slaveRegDo_mux_4_reg[1] ; wire \slaveRegDo_mux_4_reg[2] ; wire \slaveRegDo_mux_4_reg[3] ; wire \slaveRegDo_mux_4_reg[4] ; wire \slaveRegDo_mux_4_reg[5] ; wire \slaveRegDo_mux_4_reg[6] ; wire \slaveRegDo_mux_4_reg[7] ; wire \slaveRegDo_mux_4_reg[8] ; wire \slaveRegDo_mux_4_reg[9] ; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__8 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__8 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__8 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__8 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__8 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__8 (.I0(\current_state[3]_i_4__8_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__8_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__8_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__8 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__8_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__8_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__8 (.I0(current_state[1]), .I1(\current_state[3]_i_2__8_n_0 ), .I2(\current_state[3]_i_4__8_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__8 (.I0(\current_state[3]_i_2__8_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__8_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__8_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__8 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__8_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__8 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[5]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[6]), .O(\current_state[3]_i_3__8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__8 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__8_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__8 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__8_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__8_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [1]), .Q(\slaveRegDo_muConfig[4107]_7 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [11]), .Q(\slaveRegDo_muConfig[4107]_7 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [12]), .Q(\slaveRegDo_muConfig[4107]_7 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [13]), .Q(\slaveRegDo_muConfig[4107]_7 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [14]), .Q(\slaveRegDo_muConfig[4107]_7 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [15]), .Q(\slaveRegDo_muConfig[4107]_7 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(\slaveRegDo_muConfig[4107]_7 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [2]), .Q(\slaveRegDo_muConfig[4107]_7 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [3]), .Q(\slaveRegDo_muConfig[4107]_7 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [4]), .Q(\slaveRegDo_muConfig[4107]_7 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [5]), .Q(\slaveRegDo_muConfig[4107]_7 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [6]), .Q(\slaveRegDo_muConfig[4107]_7 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [7]), .Q(\slaveRegDo_muConfig[4107]_7 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [8]), .Q(\slaveRegDo_muConfig[4107]_7 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [9]), .Q(\slaveRegDo_muConfig[4107]_7 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [10]), .Q(\slaveRegDo_muConfig[4107]_7 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__8 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__8 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__8 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__8 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__8 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__8 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__8_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__8 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__8 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__8 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__8 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__8 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__8 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__8 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__8 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__8 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__8 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__8_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h0104)) shift_en_i_1__8 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__8_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__8_n_0), .Q(E), .R(1'b0)); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[0]_i_1 (.I0(\slaveRegDo_mux_4[0]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ), .I2(\parallel_dout_reg[0]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[0]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(Q[0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_4[0]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[10]_i_1 (.I0(\slaveRegDo_mux_4[10]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ), .I2(\parallel_dout_reg[10]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[10]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(Q[10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_4[10]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[11]_i_1 (.I0(\slaveRegDo_mux_4[11]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ), .I2(\parallel_dout_reg[11]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[11]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(Q[11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_4[11]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[12]_i_1 (.I0(\slaveRegDo_mux_4[12]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ), .I2(\parallel_dout_reg[12]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[12]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(Q[12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_4[12]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[13]_i_1 (.I0(\slaveRegDo_mux_4[13]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ), .I2(\parallel_dout_reg[13]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[13]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(Q[13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_4[13]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[14]_i_1 (.I0(\slaveRegDo_mux_4[14]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ), .I2(\parallel_dout_reg[14]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[14]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(Q[14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_4[14]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[15]_i_1 (.I0(\slaveRegDo_mux_4[15]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I2(\parallel_dout_reg[15]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[15]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(Q[15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_4[15]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[1]_i_1 (.I0(\slaveRegDo_mux_4[1]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ), .I2(\parallel_dout_reg[1]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[1]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(Q[1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_4[1]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[2]_i_1 (.I0(\slaveRegDo_mux_4[2]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ), .I2(\parallel_dout_reg[2]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[2]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(Q[2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_4[2]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[3]_i_1 (.I0(\slaveRegDo_mux_4[3]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ), .I2(\parallel_dout_reg[3]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[3]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(Q[3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_4[3]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[4]_i_1 (.I0(\slaveRegDo_mux_4[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ), .I2(\parallel_dout_reg[4]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[4]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(Q[4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_4[4]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[5]_i_1 (.I0(\slaveRegDo_mux_4[5]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ), .I2(\parallel_dout_reg[5]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[5]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(Q[5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_4[5]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[6]_i_1 (.I0(\slaveRegDo_mux_4[6]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ), .I2(\parallel_dout_reg[6]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[6]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(Q[6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_4[6]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[7]_i_1 (.I0(\slaveRegDo_mux_4[7]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ), .I2(\parallel_dout_reg[7]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[7]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(Q[7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_4[7]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[8]_i_1 (.I0(\slaveRegDo_mux_4[8]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ), .I2(\parallel_dout_reg[8]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[8]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(Q[8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_4[8]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[9]_i_1 (.I0(\slaveRegDo_mux_4[9]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ), .I2(\parallel_dout_reg[9]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[9] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[9]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(Q[9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_4[9]_i_2_n_0 )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__7 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6 (\slaveRegDo_mux_4_reg[15] , \slaveRegDo_mux_4_reg[14] , \slaveRegDo_mux_4_reg[13] , \slaveRegDo_mux_4_reg[12] , \slaveRegDo_mux_4_reg[11] , \slaveRegDo_mux_4_reg[10] , \slaveRegDo_mux_4_reg[9] , \slaveRegDo_mux_4_reg[8] , \slaveRegDo_mux_4_reg[7] , \slaveRegDo_mux_4_reg[6] , \slaveRegDo_mux_4_reg[5] , \slaveRegDo_mux_4_reg[4] , \slaveRegDo_mux_4_reg[3] , \slaveRegDo_mux_4_reg[2] , \slaveRegDo_mux_4_reg[1] , \slaveRegDo_mux_4_reg[0] , E, mu_config_cs_serial_output, \G_1PIPE_IFACE.s_daddr_r_reg[3] , \parallel_dout_reg[15]_0 , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 , \parallel_dout_reg[14]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 , \parallel_dout_reg[13]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 , \parallel_dout_reg[12]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 , \parallel_dout_reg[11]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 , \parallel_dout_reg[10]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 , \parallel_dout_reg[9]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 , \parallel_dout_reg[8]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 , \parallel_dout_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 , \parallel_dout_reg[6]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 , \parallel_dout_reg[5]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 , \parallel_dout_reg[4]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 , \parallel_dout_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 , \parallel_dout_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 , \parallel_dout_reg[1]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 , \parallel_dout_reg[0]_0 , s_do_o, Q, \parallel_dout_reg[15]_1 , s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o);
output \slaveRegDo_mux_4_reg[15] ; output \slaveRegDo_mux_4_reg[14] ; output \slaveRegDo_mux_4_reg[13] ; output \slaveRegDo_mux_4_reg[12] ; output \slaveRegDo_mux_4_reg[11] ; output \slaveRegDo_mux_4_reg[10] ; output \slaveRegDo_mux_4_reg[9] ; output \slaveRegDo_mux_4_reg[8] ; output \slaveRegDo_mux_4_reg[7] ; output \slaveRegDo_mux_4_reg[6] ; output \slaveRegDo_mux_4_reg[5] ; output \slaveRegDo_mux_4_reg[4] ; output \slaveRegDo_mux_4_reg[3] ; output \slaveRegDo_mux_4_reg[2] ; output \slaveRegDo_mux_4_reg[1] ; output \slaveRegDo_mux_4_reg[0] ; output [0:0]E; output [0:0]mu_config_cs_serial_output; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \parallel_dout_reg[15]_0 ; input [6:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; input \parallel_dout_reg[14]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; input \parallel_dout_reg[13]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ; input \parallel_dout_reg[12]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ; input \parallel_dout_reg[11]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ; input \parallel_dout_reg[10]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ; input \parallel_dout_reg[9]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ; input \parallel_dout_reg[8]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ; input \parallel_dout_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ; input \parallel_dout_reg[6]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ; input \parallel_dout_reg[5]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ; input \parallel_dout_reg[4]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ; input \parallel_dout_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ; input \parallel_dout_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ; input \parallel_dout_reg[1]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ; input \parallel_dout_reg[0]_0 ; input [15:0]s_do_o; input [15:0]Q; input [15:0]\parallel_dout_reg[15]_1 ; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire [15:0]Q; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__8_n_0 ; wire \current_state[3]_i_3__8_n_0 ; wire \current_state[3]_i_4__8_n_0 ; wire data_out_sel; wire data_out_sel_i_1__8_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire \parallel_dout_reg[0]_0 ; wire \parallel_dout_reg[10]_0 ; wire \parallel_dout_reg[11]_0 ; wire \parallel_dout_reg[12]_0 ; wire \parallel_dout_reg[13]_0 ; wire \parallel_dout_reg[14]_0 ; wire \parallel_dout_reg[15]_0 ; wire [15:0]\parallel_dout_reg[15]_1 ; wire \parallel_dout_reg[1]_0 ; wire \parallel_dout_reg[2]_0 ; wire \parallel_dout_reg[3]_0 ; wire \parallel_dout_reg[4]_0 ; wire \parallel_dout_reg[5]_0 ; wire \parallel_dout_reg[6]_0 ; wire \parallel_dout_reg[7]_0 ; wire \parallel_dout_reg[8]_0 ; wire \parallel_dout_reg[9]_0 ; wire [6:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__8_n_0 ; wire \shadow[10]_i_1__8_n_0 ; wire \shadow[11]_i_1__8_n_0 ; wire \shadow[12]_i_1__8_n_0 ; wire \shadow[13]_i_1__8_n_0 ; wire \shadow[14]_i_1__8_n_0 ; wire \shadow[15]_i_1__8_n_0 ; wire \shadow[1]_i_1__8_n_0 ; wire \shadow[2]_i_1__8_n_0 ; wire \shadow[3]_i_1__8_n_0 ; wire \shadow[4]_i_1__8_n_0 ; wire \shadow[5]_i_1__8_n_0 ; wire \shadow[6]_i_1__8_n_0 ; wire \shadow[7]_i_1__8_n_0 ; wire \shadow[8]_i_1__8_n_0 ; wire \shadow[9]_i_1__8_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__8_n_0; wire [15:0]\slaveRegDo_muConfig[4107]_7 ; wire \slaveRegDo_mux_4[0]_i_2_n_0 ; wire \slaveRegDo_mux_4[10]_i_2_n_0 ; wire \slaveRegDo_mux_4[11]_i_2_n_0 ; wire \slaveRegDo_mux_4[12]_i_2_n_0 ; wire \slaveRegDo_mux_4[13]_i_2_n_0 ; wire \slaveRegDo_mux_4[14]_i_2_n_0 ; wire \slaveRegDo_mux_4[15]_i_2_n_0 ; wire \slaveRegDo_mux_4[1]_i_2_n_0 ; wire \slaveRegDo_mux_4[2]_i_2_n_0 ; wire \slaveRegDo_mux_4[3]_i_2_n_0 ; wire \slaveRegDo_mux_4[4]_i_2_n_0 ; wire \slaveRegDo_mux_4[5]_i_2_n_0 ; wire \slaveRegDo_mux_4[6]_i_2_n_0 ; wire \slaveRegDo_mux_4[7]_i_2_n_0 ; wire \slaveRegDo_mux_4[8]_i_2_n_0 ; wire \slaveRegDo_mux_4[9]_i_2_n_0 ; wire \slaveRegDo_mux_4_reg[0] ; wire \slaveRegDo_mux_4_reg[10] ; wire \slaveRegDo_mux_4_reg[11] ; wire \slaveRegDo_mux_4_reg[12] ; wire \slaveRegDo_mux_4_reg[13] ; wire \slaveRegDo_mux_4_reg[14] ; wire \slaveRegDo_mux_4_reg[15] ; wire \slaveRegDo_mux_4_reg[1] ; wire \slaveRegDo_mux_4_reg[2] ; wire \slaveRegDo_mux_4_reg[3] ; wire \slaveRegDo_mux_4_reg[4] ; wire \slaveRegDo_mux_4_reg[5] ; wire \slaveRegDo_mux_4_reg[6] ; wire \slaveRegDo_mux_4_reg[7] ; wire \slaveRegDo_mux_4_reg[8] ; wire \slaveRegDo_mux_4_reg[9] ; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__8 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__8 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__8 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__8 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__8 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__8 (.I0(\current_state[3]_i_4__8_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__8_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__8_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__8 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__8_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__8_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__8 (.I0(current_state[1]), .I1(\current_state[3]_i_2__8_n_0 ), .I2(\current_state[3]_i_4__8_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__8 (.I0(\current_state[3]_i_2__8_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__8_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__8_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__8 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__8_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__8 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[5]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[6]), .O(\current_state[3]_i_3__8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__8 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__8_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__8 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__8_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__8_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [1]), .Q(\slaveRegDo_muConfig[4107]_7 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [11]), .Q(\slaveRegDo_muConfig[4107]_7 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [12]), .Q(\slaveRegDo_muConfig[4107]_7 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [13]), .Q(\slaveRegDo_muConfig[4107]_7 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [14]), .Q(\slaveRegDo_muConfig[4107]_7 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [15]), .Q(\slaveRegDo_muConfig[4107]_7 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(\slaveRegDo_muConfig[4107]_7 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [2]), .Q(\slaveRegDo_muConfig[4107]_7 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [3]), .Q(\slaveRegDo_muConfig[4107]_7 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [4]), .Q(\slaveRegDo_muConfig[4107]_7 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [5]), .Q(\slaveRegDo_muConfig[4107]_7 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [6]), .Q(\slaveRegDo_muConfig[4107]_7 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [7]), .Q(\slaveRegDo_muConfig[4107]_7 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [8]), .Q(\slaveRegDo_muConfig[4107]_7 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [9]), .Q(\slaveRegDo_muConfig[4107]_7 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4107]_7 [10]), .Q(\slaveRegDo_muConfig[4107]_7 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__8 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__8 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__8 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__8 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__8 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__8 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__8_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__8 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__8 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__8 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__8 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__8 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__8 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__8 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__8 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__8 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__8_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__8 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__8_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__8_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h0104)) shift_en_i_1__8 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__8_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__8_n_0), .Q(E), .R(1'b0)); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[0]_i_1 (.I0(\slaveRegDo_mux_4[0]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_14 ), .I2(\parallel_dout_reg[0]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[0]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [0]), .I1(s_do_o[0]), .I2(s_daddr_o[1]), .I3(Q[0]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [0]), .O(\slaveRegDo_mux_4[0]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[10]_i_1 (.I0(\slaveRegDo_mux_4[10]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ), .I2(\parallel_dout_reg[10]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[10] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[10]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [10]), .I1(s_do_o[10]), .I2(s_daddr_o[1]), .I3(Q[10]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [10]), .O(\slaveRegDo_mux_4[10]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[11]_i_1 (.I0(\slaveRegDo_mux_4[11]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ), .I2(\parallel_dout_reg[11]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[11] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[11]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [11]), .I1(s_do_o[11]), .I2(s_daddr_o[1]), .I3(Q[11]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [11]), .O(\slaveRegDo_mux_4[11]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[12]_i_1 (.I0(\slaveRegDo_mux_4[12]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ), .I2(\parallel_dout_reg[12]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[12] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[12]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [12]), .I1(s_do_o[12]), .I2(s_daddr_o[1]), .I3(Q[12]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [12]), .O(\slaveRegDo_mux_4[12]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[13]_i_1 (.I0(\slaveRegDo_mux_4[13]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ), .I2(\parallel_dout_reg[13]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[13] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[13]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [13]), .I1(s_do_o[13]), .I2(s_daddr_o[1]), .I3(Q[13]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [13]), .O(\slaveRegDo_mux_4[13]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[14]_i_1 (.I0(\slaveRegDo_mux_4[14]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ), .I2(\parallel_dout_reg[14]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[14] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[14]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [14]), .I1(s_do_o[14]), .I2(s_daddr_o[1]), .I3(Q[14]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [14]), .O(\slaveRegDo_mux_4[14]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[15]_i_1 (.I0(\slaveRegDo_mux_4[15]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I2(\parallel_dout_reg[15]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[15] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[15]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [15]), .I1(s_do_o[15]), .I2(s_daddr_o[1]), .I3(Q[15]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [15]), .O(\slaveRegDo_mux_4[15]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[1]_i_1 (.I0(\slaveRegDo_mux_4[1]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_13 ), .I2(\parallel_dout_reg[1]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[1] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[1]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [1]), .I1(s_do_o[1]), .I2(s_daddr_o[1]), .I3(Q[1]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [1]), .O(\slaveRegDo_mux_4[1]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[2]_i_1 (.I0(\slaveRegDo_mux_4[2]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_12 ), .I2(\parallel_dout_reg[2]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[2] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[2]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [2]), .I1(s_do_o[2]), .I2(s_daddr_o[1]), .I3(Q[2]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [2]), .O(\slaveRegDo_mux_4[2]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[3]_i_1 (.I0(\slaveRegDo_mux_4[3]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_11 ), .I2(\parallel_dout_reg[3]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[3] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[3]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [3]), .I1(s_do_o[3]), .I2(s_daddr_o[1]), .I3(Q[3]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [3]), .O(\slaveRegDo_mux_4[3]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[4]_i_1 (.I0(\slaveRegDo_mux_4[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_10 ), .I2(\parallel_dout_reg[4]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[4]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [4]), .I1(s_do_o[4]), .I2(s_daddr_o[1]), .I3(Q[4]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [4]), .O(\slaveRegDo_mux_4[4]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[5]_i_1 (.I0(\slaveRegDo_mux_4[5]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ), .I2(\parallel_dout_reg[5]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[5] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[5]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [5]), .I1(s_do_o[5]), .I2(s_daddr_o[1]), .I3(Q[5]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [5]), .O(\slaveRegDo_mux_4[5]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[6]_i_1 (.I0(\slaveRegDo_mux_4[6]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ), .I2(\parallel_dout_reg[6]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[6]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [6]), .I1(s_do_o[6]), .I2(s_daddr_o[1]), .I3(Q[6]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [6]), .O(\slaveRegDo_mux_4[6]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[7]_i_1 (.I0(\slaveRegDo_mux_4[7]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ), .I2(\parallel_dout_reg[7]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[7] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[7]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [7]), .I1(s_do_o[7]), .I2(s_daddr_o[1]), .I3(Q[7]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [7]), .O(\slaveRegDo_mux_4[7]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[8]_i_1 (.I0(\slaveRegDo_mux_4[8]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ), .I2(\parallel_dout_reg[8]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[8] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[8]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [8]), .I1(s_do_o[8]), .I2(s_daddr_o[1]), .I3(Q[8]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [8]), .O(\slaveRegDo_mux_4[8]_i_2_n_0 )); LUT5 #( .INIT(32'hCCEECCFC)) \slaveRegDo_mux_4[9]_i_1 (.I0(\slaveRegDo_mux_4[9]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ), .I2(\parallel_dout_reg[9]_0 ), .I3(s_daddr_o[2]), .I4(s_daddr_o[3]), .O(\slaveRegDo_mux_4_reg[9] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \slaveRegDo_mux_4[9]_i_2 (.I0(\slaveRegDo_muConfig[4107]_7 [9]), .I1(s_do_o[9]), .I2(s_daddr_o[1]), .I3(Q[9]), .I4(s_daddr_o[0]), .I5(\parallel_dout_reg[15]_1 [9]), .O(\slaveRegDo_mux_4[9]_i_2_n_0 )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__7 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,473
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__9_n_0 ; wire \current_state[3]_i_3__9_n_0 ; wire \current_state[3]_i_4__9_n_0 ; wire data_out_sel; wire data_out_sel_i_1__9_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__9_n_0 ; wire \shadow[10]_i_1__9_n_0 ; wire \shadow[11]_i_1__9_n_0 ; wire \shadow[12]_i_1__9_n_0 ; wire \shadow[13]_i_1__9_n_0 ; wire \shadow[14]_i_1__9_n_0 ; wire \shadow[15]_i_1__9_n_0 ; wire \shadow[1]_i_1__9_n_0 ; wire \shadow[2]_i_1__9_n_0 ; wire \shadow[3]_i_1__9_n_0 ; wire \shadow[4]_i_1__9_n_0 ; wire \shadow[5]_i_1__9_n_0 ; wire \shadow[6]_i_1__9_n_0 ; wire \shadow[7]_i_1__9_n_0 ; wire \shadow[8]_i_1__9_n_0 ; wire \shadow[9]_i_1__9_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__9_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__9 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__9 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__9 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__9 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__9 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__9 (.I0(\current_state[3]_i_4__9_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__9_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__9_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__9 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__9_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__9_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__9 (.I0(current_state[1]), .I1(\current_state[3]_i_2__9_n_0 ), .I2(\current_state[3]_i_4__9_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__9 (.I0(\current_state[3]_i_2__9_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__9_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__9_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__9 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \current_state[3]_i_3__9 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__9 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__9_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__9 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__9_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__9_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__9 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__9 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__9 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__9 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__9 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__9 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__9_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__9 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__9 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__9 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__9 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__9 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__9 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__9 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__9 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__9 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__9 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__9_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__9 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__9_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__9_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__8 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7 (s_do_o, E, mu_config_cs_serial_output, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_daddr_o, s_den_o, s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]mu_config_cs_serial_output; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [2:0]s_daddr_o; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__9_n_0 ; wire \current_state[3]_i_3__9_n_0 ; wire \current_state[3]_i_4__9_n_0 ; wire data_out_sel; wire data_out_sel_i_1__9_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [2:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__9_n_0 ; wire \shadow[10]_i_1__9_n_0 ; wire \shadow[11]_i_1__9_n_0 ; wire \shadow[12]_i_1__9_n_0 ; wire \shadow[13]_i_1__9_n_0 ; wire \shadow[14]_i_1__9_n_0 ; wire \shadow[15]_i_1__9_n_0 ; wire \shadow[1]_i_1__9_n_0 ; wire \shadow[2]_i_1__9_n_0 ; wire \shadow[3]_i_1__9_n_0 ; wire \shadow[4]_i_1__9_n_0 ; wire \shadow[5]_i_1__9_n_0 ; wire \shadow[6]_i_1__9_n_0 ; wire \shadow[7]_i_1__9_n_0 ; wire \shadow[8]_i_1__9_n_0 ; wire \shadow[9]_i_1__9_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__9_n_0; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__9 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__9 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__9 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__9 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__9 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__9 (.I0(\current_state[3]_i_4__9_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__9_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__9_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__9 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__9_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__9_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__9 (.I0(current_state[1]), .I1(\current_state[3]_i_2__9_n_0 ), .I2(\current_state[3]_i_4__9_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__9 (.I0(\current_state[3]_i_2__9_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__9_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__9_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__9 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__9_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) \current_state[3]_i_3__9 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(s_den_o), .I5(s_daddr_o[2]), .O(\current_state[3]_i_3__9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__9 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__9_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__9 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__9_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__9_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__9 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__9 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__9 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__9 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__9 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__9 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__9_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__9 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__9 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__9 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__9 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__9 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__9 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__9 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__9 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__9 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__9_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__9 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__9_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__9_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__9 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__9_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__9_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__8 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,474
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8 (\slaveRegDo_mux_4_reg[0] , \slaveRegDo_mux_4_reg[1] , \slaveRegDo_mux_4_reg[2] , \slaveRegDo_mux_4_reg[3] , \slaveRegDo_mux_4_reg[4] , \slaveRegDo_mux_4_reg[5] , \slaveRegDo_mux_4_reg[6] , \slaveRegDo_mux_4_reg[7] , \slaveRegDo_mux_4_reg[8] , \slaveRegDo_mux_4_reg[9] , \slaveRegDo_mux_4_reg[10] , \slaveRegDo_mux_4_reg[11] , \slaveRegDo_mux_4_reg[12] , \slaveRegDo_mux_4_reg[13] , \slaveRegDo_mux_4_reg[14] , \slaveRegDo_mux_4_reg[15] , E, mu_config_cs_serial_output, s_daddr_o, s_do_o, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o); output \slaveRegDo_mux_4_reg[0] ; output \slaveRegDo_mux_4_reg[1] ; output \slaveRegDo_mux_4_reg[2] ; output \slaveRegDo_mux_4_reg[3] ; output \slaveRegDo_mux_4_reg[4] ; output \slaveRegDo_mux_4_reg[5] ; output \slaveRegDo_mux_4_reg[6] ; output \slaveRegDo_mux_4_reg[7] ; output \slaveRegDo_mux_4_reg[8] ; output \slaveRegDo_mux_4_reg[9] ; output \slaveRegDo_mux_4_reg[10] ; output \slaveRegDo_mux_4_reg[11] ; output \slaveRegDo_mux_4_reg[12] ; output \slaveRegDo_mux_4_reg[13] ; output \slaveRegDo_mux_4_reg[14] ; output \slaveRegDo_mux_4_reg[15] ; output [0:0]E; output [0:0]mu_config_cs_serial_output; input [6:0]s_daddr_o; input [15:0]s_do_o; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__10_n_0 ; wire \current_state[3]_i_3__10_n_0 ; wire \current_state[3]_i_4__10_n_0 ; wire data_out_sel; wire data_out_sel_i_1__10_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [6:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__10_n_0 ; wire \shadow[10]_i_1__10_n_0 ; wire \shadow[11]_i_1__10_n_0 ; wire \shadow[12]_i_1__10_n_0 ; wire \shadow[13]_i_1__10_n_0 ; wire \shadow[14]_i_1__10_n_0 ; wire \shadow[15]_i_1__10_n_0 ; wire \shadow[1]_i_1__10_n_0 ; wire \shadow[2]_i_1__10_n_0 ; wire \shadow[3]_i_1__10_n_0 ; wire \shadow[4]_i_1__10_n_0 ; wire \shadow[5]_i_1__10_n_0 ; wire \shadow[6]_i_1__10_n_0 ; wire \shadow[7]_i_1__10_n_0 ; wire \shadow[8]_i_1__10_n_0 ; wire \shadow[9]_i_1__10_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__10_n_0; wire [15:0]\slaveRegDo_muConfig[4111]_9 ; wire \slaveRegDo_mux_4_reg[0] ; wire \slaveRegDo_mux_4_reg[10] ; wire \slaveRegDo_mux_4_reg[11] ; wire \slaveRegDo_mux_4_reg[12] ; wire \slaveRegDo_mux_4_reg[13] ; wire \slaveRegDo_mux_4_reg[14] ; wire \slaveRegDo_mux_4_reg[15] ; wire \slaveRegDo_mux_4_reg[1] ; wire \slaveRegDo_mux_4_reg[2] ; wire \slaveRegDo_mux_4_reg[3] ; wire \slaveRegDo_mux_4_reg[4] ; wire \slaveRegDo_mux_4_reg[5] ; wire \slaveRegDo_mux_4_reg[6] ; wire \slaveRegDo_mux_4_reg[7] ; wire \slaveRegDo_mux_4_reg[8] ; wire \slaveRegDo_mux_4_reg[9] ; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__10 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__10 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__10 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__10 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__10 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__10 (.I0(\current_state[3]_i_4__10_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__10_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__10_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__10 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__10_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__10_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__10 (.I0(current_state[1]), .I1(\current_state[3]_i_2__10_n_0 ), .I2(\current_state[3]_i_4__10_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__10 (.I0(\current_state[3]_i_2__10_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__10_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__10_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__10 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__10_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__10 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[5]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[6]), .O(\current_state[3]_i_3__10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__10 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__10_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__10 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__10_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__10_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [1]), .Q(\slaveRegDo_muConfig[4111]_9 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [11]), .Q(\slaveRegDo_muConfig[4111]_9 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [12]), .Q(\slaveRegDo_muConfig[4111]_9 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [13]), .Q(\slaveRegDo_muConfig[4111]_9 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [14]), .Q(\slaveRegDo_muConfig[4111]_9 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [15]), .Q(\slaveRegDo_muConfig[4111]_9 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(\slaveRegDo_muConfig[4111]_9 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [2]), .Q(\slaveRegDo_muConfig[4111]_9 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [3]), .Q(\slaveRegDo_muConfig[4111]_9 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [4]), .Q(\slaveRegDo_muConfig[4111]_9 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [5]), .Q(\slaveRegDo_muConfig[4111]_9 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [6]), .Q(\slaveRegDo_muConfig[4111]_9 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [7]), .Q(\slaveRegDo_muConfig[4111]_9 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [8]), .Q(\slaveRegDo_muConfig[4111]_9 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [9]), .Q(\slaveRegDo_muConfig[4111]_9 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [10]), .Q(\slaveRegDo_muConfig[4111]_9 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__10 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__10 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__10 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__10 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__10 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__10 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__10_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__10 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__10 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__10 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__10 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__10 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__10 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__10 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__10 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__10 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__10 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__10_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__10 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__10_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__10_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[0]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [0]), .I3(s_daddr_o[0]), .I4(s_do_o[0]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[0] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[10]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [10]), .I3(s_daddr_o[0]), .I4(s_do_o[10]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[10] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[11]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [11]), .I3(s_daddr_o[0]), .I4(s_do_o[11]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[11] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[12]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [12]), .I3(s_daddr_o[0]), .I4(s_do_o[12]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[12] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[13]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [13]), .I3(s_daddr_o[0]), .I4(s_do_o[13]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[13] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[14]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [14]), .I3(s_daddr_o[0]), .I4(s_do_o[14]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[14] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[15]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [15]), .I3(s_daddr_o[0]), .I4(s_do_o[15]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[15] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[1]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [1]), .I3(s_daddr_o[0]), .I4(s_do_o[1]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[1] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[2]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [2]), .I3(s_daddr_o[0]), .I4(s_do_o[2]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[2] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[3]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [3]), .I3(s_daddr_o[0]), .I4(s_do_o[3]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[3] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[4]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [4]), .I3(s_daddr_o[0]), .I4(s_do_o[4]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[4] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[5]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [5]), .I3(s_daddr_o[0]), .I4(s_do_o[5]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[5] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[6]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [6]), .I3(s_daddr_o[0]), .I4(s_do_o[6]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[6] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[7]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [7]), .I3(s_daddr_o[0]), .I4(s_do_o[7]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[7] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[8]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [8]), .I3(s_daddr_o[0]), .I4(s_do_o[8]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[8] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[9]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [9]), .I3(s_daddr_o[0]), .I4(s_do_o[9]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__9 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8 (\slaveRegDo_mux_4_reg[0] , \slaveRegDo_mux_4_reg[1] , \slaveRegDo_mux_4_reg[2] , \slaveRegDo_mux_4_reg[3] , \slaveRegDo_mux_4_reg[4] , \slaveRegDo_mux_4_reg[5] , \slaveRegDo_mux_4_reg[6] , \slaveRegDo_mux_4_reg[7] , \slaveRegDo_mux_4_reg[8] , \slaveRegDo_mux_4_reg[9] , \slaveRegDo_mux_4_reg[10] , \slaveRegDo_mux_4_reg[11] , \slaveRegDo_mux_4_reg[12] , \slaveRegDo_mux_4_reg[13] , \slaveRegDo_mux_4_reg[14] , \slaveRegDo_mux_4_reg[15] , E, mu_config_cs_serial_output, s_daddr_o, s_do_o, s_dclk_o, mu_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[1] , s_den_o, s_di_o);
output \slaveRegDo_mux_4_reg[0] ; output \slaveRegDo_mux_4_reg[1] ; output \slaveRegDo_mux_4_reg[2] ; output \slaveRegDo_mux_4_reg[3] ; output \slaveRegDo_mux_4_reg[4] ; output \slaveRegDo_mux_4_reg[5] ; output \slaveRegDo_mux_4_reg[6] ; output \slaveRegDo_mux_4_reg[7] ; output \slaveRegDo_mux_4_reg[8] ; output \slaveRegDo_mux_4_reg[9] ; output \slaveRegDo_mux_4_reg[10] ; output \slaveRegDo_mux_4_reg[11] ; output \slaveRegDo_mux_4_reg[12] ; output \slaveRegDo_mux_4_reg[13] ; output \slaveRegDo_mux_4_reg[14] ; output \slaveRegDo_mux_4_reg[15] ; output [0:0]E; output [0:0]mu_config_cs_serial_output; input [6:0]s_daddr_o; input [15:0]s_do_o; input s_dclk_o; input [0:0]mu_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input s_den_o; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__10_n_0 ; wire \current_state[3]_i_3__10_n_0 ; wire \current_state[3]_i_4__10_n_0 ; wire data_out_sel; wire data_out_sel_i_1__10_n_0; wire [0:0]mu_config_cs_serial_input; wire [0:0]mu_config_cs_serial_output; wire [3:0]next_state; wire [3:0]p_0_in; wire [6:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__10_n_0 ; wire \shadow[10]_i_1__10_n_0 ; wire \shadow[11]_i_1__10_n_0 ; wire \shadow[12]_i_1__10_n_0 ; wire \shadow[13]_i_1__10_n_0 ; wire \shadow[14]_i_1__10_n_0 ; wire \shadow[15]_i_1__10_n_0 ; wire \shadow[1]_i_1__10_n_0 ; wire \shadow[2]_i_1__10_n_0 ; wire \shadow[3]_i_1__10_n_0 ; wire \shadow[4]_i_1__10_n_0 ; wire \shadow[5]_i_1__10_n_0 ; wire \shadow[6]_i_1__10_n_0 ; wire \shadow[7]_i_1__10_n_0 ; wire \shadow[8]_i_1__10_n_0 ; wire \shadow[9]_i_1__10_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__10_n_0; wire [15:0]\slaveRegDo_muConfig[4111]_9 ; wire \slaveRegDo_mux_4_reg[0] ; wire \slaveRegDo_mux_4_reg[10] ; wire \slaveRegDo_mux_4_reg[11] ; wire \slaveRegDo_mux_4_reg[12] ; wire \slaveRegDo_mux_4_reg[13] ; wire \slaveRegDo_mux_4_reg[14] ; wire \slaveRegDo_mux_4_reg[15] ; wire \slaveRegDo_mux_4_reg[1] ; wire \slaveRegDo_mux_4_reg[2] ; wire \slaveRegDo_mux_4_reg[3] ; wire \slaveRegDo_mux_4_reg[4] ; wire \slaveRegDo_mux_4_reg[5] ; wire \slaveRegDo_mux_4_reg[6] ; wire \slaveRegDo_mux_4_reg[7] ; wire \slaveRegDo_mux_4_reg[8] ; wire \slaveRegDo_mux_4_reg[9] ; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__10 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__10 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__10 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__10 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__10 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__10 (.I0(\current_state[3]_i_4__10_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__10_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__10_n_0 ), .O(next_state[0])); LUT4 #( .INIT(16'h0080)) \current_state[1]_i_1__10 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__10_n_0 ), .I2(current_state[0]), .I3(\current_state[3]_i_3__10_n_0 ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__10 (.I0(current_state[1]), .I1(\current_state[3]_i_2__10_n_0 ), .I2(\current_state[3]_i_4__10_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__10 (.I0(\current_state[3]_i_2__10_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__10_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__10_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__10 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__10_n_0 )); LUT6 #( .INIT(64'hFFFBFFFFFFFFFFFF)) \current_state[3]_i_3__10 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I2(s_daddr_o[5]), .I3(s_daddr_o[4]), .I4(s_den_o), .I5(s_daddr_o[6]), .O(\current_state[3]_i_3__10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__10 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__10_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__10 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__10_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__10_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [1]), .Q(\slaveRegDo_muConfig[4111]_9 [0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [11]), .Q(\slaveRegDo_muConfig[4111]_9 [10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [12]), .Q(\slaveRegDo_muConfig[4111]_9 [11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [13]), .Q(\slaveRegDo_muConfig[4111]_9 [12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [14]), .Q(\slaveRegDo_muConfig[4111]_9 [13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [15]), .Q(\slaveRegDo_muConfig[4111]_9 [14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(mu_config_cs_serial_input), .Q(\slaveRegDo_muConfig[4111]_9 [15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [2]), .Q(\slaveRegDo_muConfig[4111]_9 [1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [3]), .Q(\slaveRegDo_muConfig[4111]_9 [2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [4]), .Q(\slaveRegDo_muConfig[4111]_9 [3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [5]), .Q(\slaveRegDo_muConfig[4111]_9 [4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [6]), .Q(\slaveRegDo_muConfig[4111]_9 [5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [7]), .Q(\slaveRegDo_muConfig[4111]_9 [6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [8]), .Q(\slaveRegDo_muConfig[4111]_9 [7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [9]), .Q(\slaveRegDo_muConfig[4111]_9 [8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(\slaveRegDo_muConfig[4111]_9 [10]), .Q(\slaveRegDo_muConfig[4111]_9 [9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__10 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__10 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__10 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__10 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__10 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__10 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__10_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__10 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__10 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__10 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__10 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__10 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__10 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__10 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__10 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__10 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__10_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__10 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__10_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__10_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__10 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__10_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__10_n_0), .Q(E), .R(1'b0)); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[0]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [0]), .I3(s_daddr_o[0]), .I4(s_do_o[0]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[0] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[10]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [10]), .I3(s_daddr_o[0]), .I4(s_do_o[10]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[10] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[11]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [11]), .I3(s_daddr_o[0]), .I4(s_do_o[11]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[11] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[12]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [12]), .I3(s_daddr_o[0]), .I4(s_do_o[12]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[12] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[13]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [13]), .I3(s_daddr_o[0]), .I4(s_do_o[13]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[13] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[14]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [14]), .I3(s_daddr_o[0]), .I4(s_do_o[14]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[14] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[15]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [15]), .I3(s_daddr_o[0]), .I4(s_do_o[15]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[15] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[1]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [1]), .I3(s_daddr_o[0]), .I4(s_do_o[1]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[1] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[2]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [2]), .I3(s_daddr_o[0]), .I4(s_do_o[2]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[2] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[3]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [3]), .I3(s_daddr_o[0]), .I4(s_do_o[3]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[3] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[4]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [4]), .I3(s_daddr_o[0]), .I4(s_do_o[4]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[4] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[5]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [5]), .I3(s_daddr_o[0]), .I4(s_do_o[5]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[5] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[6]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [6]), .I3(s_daddr_o[0]), .I4(s_do_o[6]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[6] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[7]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [7]), .I3(s_daddr_o[0]), .I4(s_do_o[7]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[7] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[8]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [8]), .I3(s_daddr_o[0]), .I4(s_do_o[8]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[8] )); LUT6 #( .INIT(64'h8088800000000000)) \slaveRegDo_mux_4[9]_i_3 (.I0(s_daddr_o[3]), .I1(s_daddr_o[2]), .I2(\slaveRegDo_muConfig[4111]_9 [9]), .I3(s_daddr_o[0]), .I4(s_do_o[9]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_4_reg[9] )); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__9 (.I0(serial_dout), .I1(data_out_sel), .I2(mu_config_cs_serial_input), .O(mu_config_cs_serial_output)); endmodule
8
2,475
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
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module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_di_o); output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__11_n_0 ; wire \current_state[3]_i_3__11_n_0 ; wire \current_state[3]_i_4__11_n_0 ; wire data_out_sel; wire data_out_sel_i_1__11_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__11_n_0 ; wire \shadow[10]_i_1__11_n_0 ; wire \shadow[11]_i_1__11_n_0 ; wire \shadow[12]_i_1__11_n_0 ; wire \shadow[13]_i_1__11_n_0 ; wire \shadow[14]_i_1__11_n_0 ; wire \shadow[15]_i_1__11_n_0 ; wire \shadow[1]_i_1__11_n_0 ; wire \shadow[2]_i_1__11_n_0 ; wire \shadow[3]_i_1__11_n_0 ; wire \shadow[4]_i_1__11_n_0 ; wire \shadow[5]_i_1__11_n_0 ; wire \shadow[6]_i_1__11_n_0 ; wire \shadow[7]_i_1__11_n_0 ; wire \shadow[8]_i_1__11_n_0 ; wire \shadow[9]_i_1__11_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__11_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__11 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__11 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__11 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__11 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__11 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__11 (.I0(\current_state[3]_i_4__11_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__11_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__11_n_0 ), .O(next_state[0])); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__11 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__11_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__11 (.I0(current_state[1]), .I1(\current_state[3]_i_2__11_n_0 ), .I2(\current_state[3]_i_4__11_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__11 (.I0(\current_state[3]_i_2__11_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__11_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__11_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__11 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'hE)) \current_state[3]_i_3__11 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__11 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__11_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__11 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__11_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__11_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__11 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__11 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__11 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__11 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__11 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__11 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__11_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__11 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__11 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__11 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__11 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__11 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__11 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__11 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__11 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__11 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__11 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__11_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__11 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__11_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__11_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__10 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9 (s_do_o, E, tc_config_cs_serial_output, s_dclk_o, tc_config_cs_serial_input, \G_1PIPE_IFACE.s_di_r_reg[15] , s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[12] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , s_di_o);
output [15:0]s_do_o; output [0:0]E; output [0:0]tc_config_cs_serial_output; input s_dclk_o; input [0:0]tc_config_cs_serial_input; input \G_1PIPE_IFACE.s_di_r_reg[15] ; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[12] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input [14:0]s_di_o; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_di_r_reg[15] ; wire clear; wire [3:0]cnt_reg; wire [3:0]current_state; wire \current_state[3]_i_2__11_n_0 ; wire \current_state[3]_i_3__11_n_0 ; wire \current_state[3]_i_4__11_n_0 ; wire data_out_sel; wire data_out_sel_i_1__11_n_0; wire [3:0]next_state; wire [3:0]p_0_in; wire s_dclk_o; wire [14:0]s_di_o; wire [15:0]s_do_o; wire s_dwe_o; wire serial_dout; wire \shadow[0]_i_1__11_n_0 ; wire \shadow[10]_i_1__11_n_0 ; wire \shadow[11]_i_1__11_n_0 ; wire \shadow[12]_i_1__11_n_0 ; wire \shadow[13]_i_1__11_n_0 ; wire \shadow[14]_i_1__11_n_0 ; wire \shadow[15]_i_1__11_n_0 ; wire \shadow[1]_i_1__11_n_0 ; wire \shadow[2]_i_1__11_n_0 ; wire \shadow[3]_i_1__11_n_0 ; wire \shadow[4]_i_1__11_n_0 ; wire \shadow[5]_i_1__11_n_0 ; wire \shadow[6]_i_1__11_n_0 ; wire \shadow[7]_i_1__11_n_0 ; wire \shadow[8]_i_1__11_n_0 ; wire \shadow[9]_i_1__11_n_0 ; wire \shadow_reg_n_0_[0] ; wire \shadow_reg_n_0_[10] ; wire \shadow_reg_n_0_[11] ; wire \shadow_reg_n_0_[12] ; wire \shadow_reg_n_0_[13] ; wire \shadow_reg_n_0_[14] ; wire \shadow_reg_n_0_[15] ; wire \shadow_reg_n_0_[1] ; wire \shadow_reg_n_0_[2] ; wire \shadow_reg_n_0_[3] ; wire \shadow_reg_n_0_[4] ; wire \shadow_reg_n_0_[5] ; wire \shadow_reg_n_0_[6] ; wire \shadow_reg_n_0_[7] ; wire \shadow_reg_n_0_[8] ; wire \shadow_reg_n_0_[9] ; wire shift_en_i_1__11_n_0; wire [0:0]tc_config_cs_serial_input; wire [0:0]tc_config_cs_serial_output; LUT1 #( .INIT(2'h1)) \cnt[0]_i_1__11 (.I0(cnt_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h6)) \cnt[1]_i_1__11 (.I0(cnt_reg[0]), .I1(cnt_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'h78)) \cnt[2]_i_1__11 (.I0(cnt_reg[1]), .I1(cnt_reg[0]), .I2(cnt_reg[2]), .O(p_0_in[2])); LUT4 #( .INIT(16'hFFEB)) \cnt[3]_i_1__11 (.I0(current_state[0]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[1]), .O(clear)); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT4 #( .INIT(16'h7F80)) \cnt[3]_i_2__11 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(p_0_in[3])); FDRE \cnt_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[0]), .Q(cnt_reg[0]), .R(clear)); FDRE \cnt_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[1]), .Q(cnt_reg[1]), .R(clear)); FDRE \cnt_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[2]), .Q(cnt_reg[2]), .R(clear)); FDRE \cnt_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(p_0_in[3]), .Q(cnt_reg[3]), .R(clear)); LUT6 #( .INIT(64'hFFFF55FD55FD55FD)) \current_state[0]_i_1__11 (.I0(\current_state[3]_i_4__11_n_0 ), .I1(current_state[3]), .I2(current_state[2]), .I3(\current_state[3]_i_2__11_n_0 ), .I4(current_state[0]), .I5(\current_state[3]_i_3__11_n_0 ), .O(next_state[0])); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h00000080)) \current_state[1]_i_1__11 (.I0(s_dwe_o), .I1(\current_state[3]_i_4__11_n_0 ), .I2(current_state[0]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .O(next_state[1])); LUT4 #( .INIT(16'hE0A0)) \current_state[2]_i_1__11 (.I0(current_state[1]), .I1(\current_state[3]_i_2__11_n_0 ), .I2(\current_state[3]_i_4__11_n_0 ), .I3(current_state[2]), .O(next_state[2])); LUT6 #( .INIT(64'h888F888800000000)) \current_state[3]_i_1__11 (.I0(\current_state[3]_i_2__11_n_0 ), .I1(current_state[3]), .I2(\current_state[3]_i_3__11_n_0 ), .I3(s_dwe_o), .I4(current_state[0]), .I5(\current_state[3]_i_4__11_n_0 ), .O(next_state[3])); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT4 #( .INIT(16'h7FFF)) \current_state[3]_i_2__11 (.I0(cnt_reg[2]), .I1(cnt_reg[0]), .I2(cnt_reg[1]), .I3(cnt_reg[3]), .O(\current_state[3]_i_2__11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'hE)) \current_state[3]_i_3__11 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ), .O(\current_state[3]_i_3__11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h0116)) \current_state[3]_i_4__11 (.I0(current_state[0]), .I1(current_state[1]), .I2(current_state[2]), .I3(current_state[3]), .O(\current_state[3]_i_4__11_n_0 )); FDRE \current_state_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(next_state[0]), .Q(current_state[0]), .R(1'b0)); FDRE \current_state_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(next_state[1]), .Q(current_state[1]), .R(1'b0)); FDRE \current_state_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(next_state[2]), .Q(current_state[2]), .R(1'b0)); FDRE \current_state_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(next_state[3]), .Q(current_state[3]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h0004)) data_out_sel_i_1__11 (.I0(current_state[1]), .I1(current_state[2]), .I2(current_state[3]), .I3(current_state[0]), .O(data_out_sel_i_1__11_n_0)); FDRE data_out_sel_reg (.C(s_dclk_o), .CE(1'b1), .D(data_out_sel_i_1__11_n_0), .Q(data_out_sel), .R(1'b0)); FDRE \parallel_dout_reg[0] (.C(s_dclk_o), .CE(E), .D(s_do_o[1]), .Q(s_do_o[0]), .R(1'b0)); FDRE \parallel_dout_reg[10] (.C(s_dclk_o), .CE(E), .D(s_do_o[11]), .Q(s_do_o[10]), .R(1'b0)); FDRE \parallel_dout_reg[11] (.C(s_dclk_o), .CE(E), .D(s_do_o[12]), .Q(s_do_o[11]), .R(1'b0)); FDRE \parallel_dout_reg[12] (.C(s_dclk_o), .CE(E), .D(s_do_o[13]), .Q(s_do_o[12]), .R(1'b0)); FDRE \parallel_dout_reg[13] (.C(s_dclk_o), .CE(E), .D(s_do_o[14]), .Q(s_do_o[13]), .R(1'b0)); FDRE \parallel_dout_reg[14] (.C(s_dclk_o), .CE(E), .D(s_do_o[15]), .Q(s_do_o[14]), .R(1'b0)); FDRE \parallel_dout_reg[15] (.C(s_dclk_o), .CE(E), .D(tc_config_cs_serial_input), .Q(s_do_o[15]), .R(1'b0)); FDRE \parallel_dout_reg[1] (.C(s_dclk_o), .CE(E), .D(s_do_o[2]), .Q(s_do_o[1]), .R(1'b0)); FDRE \parallel_dout_reg[2] (.C(s_dclk_o), .CE(E), .D(s_do_o[3]), .Q(s_do_o[2]), .R(1'b0)); FDRE \parallel_dout_reg[3] (.C(s_dclk_o), .CE(E), .D(s_do_o[4]), .Q(s_do_o[3]), .R(1'b0)); FDRE \parallel_dout_reg[4] (.C(s_dclk_o), .CE(E), .D(s_do_o[5]), .Q(s_do_o[4]), .R(1'b0)); FDRE \parallel_dout_reg[5] (.C(s_dclk_o), .CE(E), .D(s_do_o[6]), .Q(s_do_o[5]), .R(1'b0)); FDRE \parallel_dout_reg[6] (.C(s_dclk_o), .CE(E), .D(s_do_o[7]), .Q(s_do_o[6]), .R(1'b0)); FDRE \parallel_dout_reg[7] (.C(s_dclk_o), .CE(E), .D(s_do_o[8]), .Q(s_do_o[7]), .R(1'b0)); FDRE \parallel_dout_reg[8] (.C(s_dclk_o), .CE(E), .D(s_do_o[9]), .Q(s_do_o[8]), .R(1'b0)); FDRE \parallel_dout_reg[9] (.C(s_dclk_o), .CE(E), .D(s_do_o[10]), .Q(s_do_o[9]), .R(1'b0)); FDRE serial_dout_reg (.C(s_dclk_o), .CE(1'b1), .D(\shadow_reg_n_0_[0] ), .Q(serial_dout), .R(1'b0)); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[0]_i_1__11 (.I0(\shadow_reg_n_0_[1] ), .I1(s_di_o[0]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[0]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[10]_i_1__11 (.I0(\shadow_reg_n_0_[11] ), .I1(s_di_o[10]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[10]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[11]_i_1__11 (.I0(\shadow_reg_n_0_[12] ), .I1(s_di_o[11]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[11]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[12]_i_1__11 (.I0(\shadow_reg_n_0_[13] ), .I1(s_di_o[12]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[12]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[13]_i_1__11 (.I0(\shadow_reg_n_0_[14] ), .I1(s_di_o[13]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[13]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[14]_i_1__11 (.I0(\shadow_reg_n_0_[15] ), .I1(s_di_o[14]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[14]_i_1__11_n_0 )); LUT4 #( .INIT(16'h0004)) \shadow[15]_i_1__11 (.I0(current_state[2]), .I1(current_state[1]), .I2(current_state[3]), .I3(current_state[0]), .O(\shadow[15]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[1]_i_1__11 (.I0(\shadow_reg_n_0_[2] ), .I1(s_di_o[1]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[1]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[2]_i_1__11 (.I0(\shadow_reg_n_0_[3] ), .I1(s_di_o[2]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[2]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[3]_i_1__11 (.I0(\shadow_reg_n_0_[4] ), .I1(s_di_o[3]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[3]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[4]_i_1__11 (.I0(\shadow_reg_n_0_[5] ), .I1(s_di_o[4]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[4]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[5]_i_1__11 (.I0(\shadow_reg_n_0_[6] ), .I1(s_di_o[5]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[5]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[6]_i_1__11 (.I0(\shadow_reg_n_0_[7] ), .I1(s_di_o[6]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[6]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[7]_i_1__11 (.I0(\shadow_reg_n_0_[8] ), .I1(s_di_o[7]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[7]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[8]_i_1__11 (.I0(\shadow_reg_n_0_[9] ), .I1(s_di_o[8]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[8]_i_1__11_n_0 )); LUT6 #( .INIT(64'h0000000000000CA0)) \shadow[9]_i_1__11 (.I0(\shadow_reg_n_0_[10] ), .I1(s_di_o[9]), .I2(current_state[2]), .I3(current_state[1]), .I4(current_state[3]), .I5(current_state[0]), .O(\shadow[9]_i_1__11_n_0 )); FDRE #( .INIT(1'b0)) \shadow_reg[0] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[0]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[10] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[10]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[11] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[11]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[11] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[12] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[12]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[13] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[13]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[14] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[14]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[15] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[15]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[15] ), .R(\G_1PIPE_IFACE.s_di_r_reg[15] )); FDRE #( .INIT(1'b0)) \shadow_reg[1] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[1]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[2] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[2]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[3] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[3]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[4] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[4]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[5] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[5]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[6] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[6]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[7] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[7]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[8] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[8]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \shadow_reg[9] (.C(s_dclk_o), .CE(1'b1), .D(\shadow[9]_i_1__11_n_0 ), .Q(\shadow_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'h0104)) shift_en_i_1__11 (.I0(current_state[0]), .I1(current_state[3]), .I2(current_state[1]), .I3(current_state[2]), .O(shift_en_i_1__11_n_0)); FDRE shift_en_reg (.C(s_dclk_o), .CE(1'b1), .D(shift_en_i_1__11_n_0), .Q(E), .R(1'b0)); LUT3 #( .INIT(8'hB8)) u_srlD_i_1__10 (.I0(serial_dout), .I1(data_out_sel), .I2(tc_config_cs_serial_input), .O(tc_config_cs_serial_output)); endmodule
8
2,476
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat (Q, E, \input_data_reg[31] , s_dclk_o); output [15:0]Q; input [0:0]E; input [15:0]\input_data_reg[31] ; input s_dclk_o; wire [0:0]E; wire [15:0]Q; wire [15:0]\input_data_reg[31] ; wire s_dclk_o; FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [0]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [10]), .Q(Q[10]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [11]), .Q(Q[11]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [12]), .Q(Q[12]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [13]), .Q(Q[13]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [14]), .Q(Q[14]), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [15]), .Q(Q[15]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [1]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [2]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [3]), .Q(Q[3]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [4]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [5]), .Q(Q[5]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [6]), .Q(Q[6]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [7]), .Q(Q[7]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [8]), .Q(Q[8]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [9]), .Q(Q[9]), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat (Q, E, \input_data_reg[31] , s_dclk_o);
output [15:0]Q; input [0:0]E; input [15:0]\input_data_reg[31] ; input s_dclk_o; wire [0:0]E; wire [15:0]Q; wire [15:0]\input_data_reg[31] ; wire s_dclk_o; FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [0]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [10]), .Q(Q[10]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [11]), .Q(Q[11]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [12]), .Q(Q[12]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [13]), .Q(Q[13]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [14]), .Q(Q[14]), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [15]), .Q(Q[15]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [1]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [2]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [3]), .Q(Q[3]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [4]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [5]), .Q(Q[5]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [6]), .Q(Q[6]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [7]), .Q(Q[7]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [8]), .Q(Q[8]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(E), .D(\input_data_reg[31] [9]), .Q(Q[9]), .R(1'b0)); endmodule
8
2,477
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164 (\slaveRegDo_mux_0_reg[2] , \slaveRegDo_mux_0_reg[4] , \slaveRegDo_mux_0_reg[1] , Q, s_daddr_o, \xsdb_reg_reg[2]_0 , \xsdb_reg_reg[4]_0 , s_den_o, \captured_samples_reg[14] , s_dclk_o); output \slaveRegDo_mux_0_reg[2] ; output \slaveRegDo_mux_0_reg[4] ; output \slaveRegDo_mux_0_reg[1] ; output [11:0]Q; input [3:0]s_daddr_o; input [1:0]\xsdb_reg_reg[2]_0 ; input \xsdb_reg_reg[4]_0 ; input s_den_o; input [14:0]\captured_samples_reg[14] ; input s_dclk_o; wire [11:0]Q; wire [14:0]\captured_samples_reg[14] ; wire [3:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_0_reg[1] ; wire \slaveRegDo_mux_0_reg[2] ; wire \slaveRegDo_mux_0_reg[4] ; wire [1:0]\xsdb_reg_reg[2]_0 ; wire \xsdb_reg_reg[4]_0 ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[4] ; LUT5 #( .INIT(32'hFFFFBABF)) \slaveRegDo_mux_0[1]_i_6 (.I0(s_daddr_o[2]), .I1(\xsdb_reg_reg_n_0_[1] ), .I2(s_daddr_o[0]), .I3(\xsdb_reg_reg[2]_0 [0]), .I4(s_daddr_o[1]), .O(\slaveRegDo_mux_0_reg[1] )); LUT6 #( .INIT(64'h0000000040444000)) \slaveRegDo_mux_0[2]_i_6 (.I0(s_daddr_o[2]), .I1(s_daddr_o[3]), .I2(\xsdb_reg_reg_n_0_[2] ), .I3(s_daddr_o[0]), .I4(\xsdb_reg_reg[2]_0 [1]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_0_reg[2] )); LUT6 #( .INIT(64'hFFBFFFFFFFBF0000)) \slaveRegDo_mux_0[4]_i_9 (.I0(s_daddr_o[2]), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg_n_0_[4] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\xsdb_reg_reg[4]_0 ), .O(\slaveRegDo_mux_0_reg[4] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [0]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [10]), .Q(Q[7]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [11]), .Q(Q[8]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [12]), .Q(Q[9]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [13]), .Q(Q[10]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [14]), .Q(Q[11]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [3]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [4]), .Q(\xsdb_reg_reg_n_0_[4] ), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [5]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [6]), .Q(Q[3]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [7]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [8]), .Q(Q[5]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [9]), .Q(Q[6]), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164 (\slaveRegDo_mux_0_reg[2] , \slaveRegDo_mux_0_reg[4] , \slaveRegDo_mux_0_reg[1] , Q, s_daddr_o, \xsdb_reg_reg[2]_0 , \xsdb_reg_reg[4]_0 , s_den_o, \captured_samples_reg[14] , s_dclk_o);
output \slaveRegDo_mux_0_reg[2] ; output \slaveRegDo_mux_0_reg[4] ; output \slaveRegDo_mux_0_reg[1] ; output [11:0]Q; input [3:0]s_daddr_o; input [1:0]\xsdb_reg_reg[2]_0 ; input \xsdb_reg_reg[4]_0 ; input s_den_o; input [14:0]\captured_samples_reg[14] ; input s_dclk_o; wire [11:0]Q; wire [14:0]\captured_samples_reg[14] ; wire [3:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_0_reg[1] ; wire \slaveRegDo_mux_0_reg[2] ; wire \slaveRegDo_mux_0_reg[4] ; wire [1:0]\xsdb_reg_reg[2]_0 ; wire \xsdb_reg_reg[4]_0 ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[4] ; LUT5 #( .INIT(32'hFFFFBABF)) \slaveRegDo_mux_0[1]_i_6 (.I0(s_daddr_o[2]), .I1(\xsdb_reg_reg_n_0_[1] ), .I2(s_daddr_o[0]), .I3(\xsdb_reg_reg[2]_0 [0]), .I4(s_daddr_o[1]), .O(\slaveRegDo_mux_0_reg[1] )); LUT6 #( .INIT(64'h0000000040444000)) \slaveRegDo_mux_0[2]_i_6 (.I0(s_daddr_o[2]), .I1(s_daddr_o[3]), .I2(\xsdb_reg_reg_n_0_[2] ), .I3(s_daddr_o[0]), .I4(\xsdb_reg_reg[2]_0 [1]), .I5(s_daddr_o[1]), .O(\slaveRegDo_mux_0_reg[2] )); LUT6 #( .INIT(64'hFFBFFFFFFFBF0000)) \slaveRegDo_mux_0[4]_i_9 (.I0(s_daddr_o[2]), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg_n_0_[4] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\xsdb_reg_reg[4]_0 ), .O(\slaveRegDo_mux_0_reg[4] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [0]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [10]), .Q(Q[7]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [11]), .Q(Q[8]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [12]), .Q(Q[9]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [13]), .Q(Q[10]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [14]), .Q(Q[11]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [3]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [4]), .Q(\xsdb_reg_reg_n_0_[4] ), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [5]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [6]), .Q(Q[3]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [7]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [8]), .Q(Q[5]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(s_den_o), .D(\captured_samples_reg[14] [9]), .Q(Q[6]), .R(1'b0)); endmodule
8
2,478
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
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module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_165 (\slaveRegDo_mux_2_reg[3] , \slaveRegDo_mux_2_reg[2] , \slaveRegDo_mux_2_reg[1] , \slaveRegDo_mux_2_reg[0] , \G_1PIPE_IFACE.s_den_r_reg , s_den_o, flag3_temp, s_dclk_o, flag2_temp, flag1_temp, flag0_temp); output \slaveRegDo_mux_2_reg[3] ; output \slaveRegDo_mux_2_reg[2] ; output \slaveRegDo_mux_2_reg[1] ; output \slaveRegDo_mux_2_reg[0] ; input \G_1PIPE_IFACE.s_den_r_reg ; input s_den_o; input flag3_temp; input s_dclk_o; input flag2_temp; input flag1_temp; input flag0_temp; wire \G_1PIPE_IFACE.s_den_r_reg ; wire flag0_temp; wire flag1_temp; wire flag2_temp; wire flag3_temp; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_2_reg[0] ; wire \slaveRegDo_mux_2_reg[1] ; wire \slaveRegDo_mux_2_reg[2] ; wire \slaveRegDo_mux_2_reg[3] ; FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(flag0_temp), .Q(\slaveRegDo_mux_2_reg[0] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(flag1_temp), .Q(\slaveRegDo_mux_2_reg[1] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(flag2_temp), .Q(\slaveRegDo_mux_2_reg[2] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(flag3_temp), .Q(\slaveRegDo_mux_2_reg[3] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_165 (\slaveRegDo_mux_2_reg[3] , \slaveRegDo_mux_2_reg[2] , \slaveRegDo_mux_2_reg[1] , \slaveRegDo_mux_2_reg[0] , \G_1PIPE_IFACE.s_den_r_reg , s_den_o, flag3_temp, s_dclk_o, flag2_temp, flag1_temp, flag0_temp);
output \slaveRegDo_mux_2_reg[3] ; output \slaveRegDo_mux_2_reg[2] ; output \slaveRegDo_mux_2_reg[1] ; output \slaveRegDo_mux_2_reg[0] ; input \G_1PIPE_IFACE.s_den_r_reg ; input s_den_o; input flag3_temp; input s_dclk_o; input flag2_temp; input flag1_temp; input flag0_temp; wire \G_1PIPE_IFACE.s_den_r_reg ; wire flag0_temp; wire flag1_temp; wire flag2_temp; wire flag3_temp; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_2_reg[0] ; wire \slaveRegDo_mux_2_reg[1] ; wire \slaveRegDo_mux_2_reg[2] ; wire \slaveRegDo_mux_2_reg[3] ; FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(flag0_temp), .Q(\slaveRegDo_mux_2_reg[0] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(flag1_temp), .Q(\slaveRegDo_mux_2_reg[1] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(flag2_temp), .Q(\slaveRegDo_mux_2_reg[2] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(flag3_temp), .Q(\slaveRegDo_mux_2_reg[3] ), .R(\G_1PIPE_IFACE.s_den_r_reg )); endmodule
8
2,479
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_166 (\slaveRegDo_mux_2_reg[5] , \slaveRegDo_mux_2_reg[6] , \slaveRegDo_mux_2_reg[7] , \slaveRegDo_mux_2_reg[8] , \slaveRegDo_mux_2_reg[9] , \slaveRegDo_mux_2_reg[10] , \slaveRegDo_mux_2_reg[11] , \slaveRegDo_mux_2_reg[12] , \slaveRegDo_mux_2_reg[13] , \slaveRegDo_mux_2_reg[14] , \slaveRegDo_mux_2_reg[15] , \xsdb_reg_reg[15]_0 , D, \slaveRegDo_mux_2_reg[0] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_do_o, \G_1PIPE_IFACE.s_daddr_r_reg[3] , \xsdb_reg_reg[3]_0 , s_den_o, en_adv_trigger, \G_1PIPE_IFACE.s_daddr_r_reg[7] , \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 , \xsdb_reg_reg[3]_1 , \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 , \xsdb_reg_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[1] , \xsdb_reg_reg[1]_0 , Q, SEQUENCER_STATE_O, s_dclk_o); output \slaveRegDo_mux_2_reg[5] ; output \slaveRegDo_mux_2_reg[6] ; output \slaveRegDo_mux_2_reg[7] ; output \slaveRegDo_mux_2_reg[8] ; output \slaveRegDo_mux_2_reg[9] ; output \slaveRegDo_mux_2_reg[10] ; output \slaveRegDo_mux_2_reg[11] ; output \slaveRegDo_mux_2_reg[12] ; output \slaveRegDo_mux_2_reg[13] ; output \slaveRegDo_mux_2_reg[14] ; output \slaveRegDo_mux_2_reg[15] ; output \xsdb_reg_reg[15]_0 ; output [3:0]D; output \slaveRegDo_mux_2_reg[0] ; input [4:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [12:0]s_do_o; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \xsdb_reg_reg[3]_0 ; input s_den_o; input en_adv_trigger; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; input \xsdb_reg_reg[3]_1 ; input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; input \xsdb_reg_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \xsdb_reg_reg[1]_0 ; input [0:0]Q; input [15:0]SEQUENCER_STATE_O; input s_dclk_o; wire [3:0]D; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; wire [0:0]Q; wire [15:0]SEQUENCER_STATE_O; wire en_adv_trigger; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [12:0]s_do_o; wire \slaveRegDo_mux_2[1]_i_2_n_0 ; wire \slaveRegDo_mux_2[1]_i_3_n_0 ; wire \slaveRegDo_mux_2[2]_i_2_n_0 ; wire \slaveRegDo_mux_2[3]_i_2_n_0 ; wire \slaveRegDo_mux_2[4]_i_2_n_0 ; wire \slaveRegDo_mux_2_reg[0] ; wire \slaveRegDo_mux_2_reg[10] ; wire \slaveRegDo_mux_2_reg[11] ; wire \slaveRegDo_mux_2_reg[12] ; wire \slaveRegDo_mux_2_reg[13] ; wire \slaveRegDo_mux_2_reg[14] ; wire \slaveRegDo_mux_2_reg[15] ; wire \slaveRegDo_mux_2_reg[5] ; wire \slaveRegDo_mux_2_reg[6] ; wire \slaveRegDo_mux_2_reg[7] ; wire \slaveRegDo_mux_2_reg[8] ; wire \slaveRegDo_mux_2_reg[9] ; wire \xsdb_reg_reg[15]_0 ; wire \xsdb_reg_reg[1]_0 ; wire \xsdb_reg_reg[2]_0 ; wire \xsdb_reg_reg[3]_0 ; wire \xsdb_reg_reg[3]_1 ; wire \xsdb_reg_reg_n_0_[10] ; wire \xsdb_reg_reg_n_0_[11] ; wire \xsdb_reg_reg_n_0_[12] ; wire \xsdb_reg_reg_n_0_[13] ; wire \xsdb_reg_reg_n_0_[14] ; wire \xsdb_reg_reg_n_0_[15] ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[3] ; wire \xsdb_reg_reg_n_0_[4] ; wire \xsdb_reg_reg_n_0_[5] ; wire \xsdb_reg_reg_n_0_[6] ; wire \xsdb_reg_reg_n_0_[7] ; wire \xsdb_reg_reg_n_0_[8] ; wire \xsdb_reg_reg_n_0_[9] ; LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[10]_i_1 (.I0(\xsdb_reg_reg_n_0_[10] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[7]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[10] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[11]_i_1 (.I0(\xsdb_reg_reg_n_0_[11] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[8]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[11] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[12]_i_1 (.I0(\xsdb_reg_reg_n_0_[12] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[9]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[12] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[13]_i_1 (.I0(\xsdb_reg_reg_n_0_[13] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[10]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[13] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[14]_i_1 (.I0(\xsdb_reg_reg_n_0_[14] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[11]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[14] )); LUT6 #( .INIT(64'hF4F444F444444444)) \slaveRegDo_mux_2[15]_i_2 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_do_o[12]), .I2(\xsdb_reg_reg_n_0_[15] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .O(\slaveRegDo_mux_2_reg[15] )); LUT4 #( .INIT(16'h4F44)) \slaveRegDo_mux_2[1]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [0]), .I2(\slaveRegDo_mux_2[1]_i_2_n_0 ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[0])); LUT6 #( .INIT(64'hDFDFFFFFDFDFF3FF)) \slaveRegDo_mux_2[1]_i_2 (.I0(\slaveRegDo_mux_2[1]_i_3_n_0 ), .I1(s_daddr_o[4]), .I2(s_daddr_o[2]), .I3(s_do_o[0]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .O(\slaveRegDo_mux_2[1]_i_2_n_0 )); LUT5 #( .INIT(32'hAFC0A0C0)) \slaveRegDo_mux_2[1]_i_3 (.I0(\xsdb_reg_reg_n_0_[1] ), .I1(\xsdb_reg_reg[1]_0 ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(Q), .O(\slaveRegDo_mux_2[1]_i_3_n_0 )); LUT5 #( .INIT(32'hFF4F4444)) \slaveRegDo_mux_2[2]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [1]), .I2(\slaveRegDo_mux_2[2]_i_2_n_0 ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[1])); LUT6 #( .INIT(64'hDFCFCFFFDFFFCFFF)) \slaveRegDo_mux_2[2]_i_2 (.I0(\xsdb_reg_reg_n_0_[2] ), .I1(s_daddr_o[4]), .I2(s_daddr_o[3]), .I3(s_daddr_o[0]), .I4(s_daddr_o[1]), .I5(\xsdb_reg_reg[2]_0 ), .O(\slaveRegDo_mux_2[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFF4F4444)) \slaveRegDo_mux_2[3]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [2]), .I2(\slaveRegDo_mux_2[3]_i_2_n_0 ), .I3(\xsdb_reg_reg[3]_1 ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[2])); LUT6 #( .INIT(64'hFFFF47FFFFFFFFFF)) \slaveRegDo_mux_2[3]_i_2 (.I0(\xsdb_reg_reg_n_0_[3] ), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg[3]_0 ), .I3(s_daddr_o[1]), .I4(s_daddr_o[4]), .I5(s_daddr_o[3]), .O(\slaveRegDo_mux_2[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF44F4)) \slaveRegDo_mux_2[4]_i_1 (.I0(\slaveRegDo_mux_2[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ), .O(D[3])); LUT6 #( .INIT(64'h0D0DDD0DDDDDDDDD)) \slaveRegDo_mux_2[4]_i_2 (.I0(s_do_o[1]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I2(\xsdb_reg_reg_n_0_[4] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .O(\slaveRegDo_mux_2[4]_i_2_n_0 )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[5]_i_1 (.I0(\xsdb_reg_reg_n_0_[5] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[2]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[5] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[6]_i_1 (.I0(\xsdb_reg_reg_n_0_[6] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[6] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[7]_i_1 (.I0(\xsdb_reg_reg_n_0_[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[4]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[7] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[8]_i_1 (.I0(\xsdb_reg_reg_n_0_[8] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[8] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[9]_i_1 (.I0(\xsdb_reg_reg_n_0_[9] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[6]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[9] )); LUT2 #( .INIT(4'h2)) \xsdb_reg[3]_i_1__0 (.I0(s_den_o), .I1(en_adv_trigger), .O(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[0]), .Q(\slaveRegDo_mux_2_reg[0] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[10]), .Q(\xsdb_reg_reg_n_0_[10] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[11]), .Q(\xsdb_reg_reg_n_0_[11] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[12]), .Q(\xsdb_reg_reg_n_0_[12] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[13]), .Q(\xsdb_reg_reg_n_0_[13] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[14]), .Q(\xsdb_reg_reg_n_0_[14] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[15]), .Q(\xsdb_reg_reg_n_0_[15] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[4]), .Q(\xsdb_reg_reg_n_0_[4] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[5]), .Q(\xsdb_reg_reg_n_0_[5] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[6]), .Q(\xsdb_reg_reg_n_0_[6] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[7]), .Q(\xsdb_reg_reg_n_0_[7] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[8]), .Q(\xsdb_reg_reg_n_0_[8] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[9]), .Q(\xsdb_reg_reg_n_0_[9] ), .R(\xsdb_reg_reg[15]_0 )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_166 (\slaveRegDo_mux_2_reg[5] , \slaveRegDo_mux_2_reg[6] , \slaveRegDo_mux_2_reg[7] , \slaveRegDo_mux_2_reg[8] , \slaveRegDo_mux_2_reg[9] , \slaveRegDo_mux_2_reg[10] , \slaveRegDo_mux_2_reg[11] , \slaveRegDo_mux_2_reg[12] , \slaveRegDo_mux_2_reg[13] , \slaveRegDo_mux_2_reg[14] , \slaveRegDo_mux_2_reg[15] , \xsdb_reg_reg[15]_0 , D, \slaveRegDo_mux_2_reg[0] , s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[0] , s_do_o, \G_1PIPE_IFACE.s_daddr_r_reg[3] , \xsdb_reg_reg[3]_0 , s_den_o, en_adv_trigger, \G_1PIPE_IFACE.s_daddr_r_reg[7] , \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 , \xsdb_reg_reg[3]_1 , \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 , \xsdb_reg_reg[2]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[1] , \xsdb_reg_reg[1]_0 , Q, SEQUENCER_STATE_O, s_dclk_o);
output \slaveRegDo_mux_2_reg[5] ; output \slaveRegDo_mux_2_reg[6] ; output \slaveRegDo_mux_2_reg[7] ; output \slaveRegDo_mux_2_reg[8] ; output \slaveRegDo_mux_2_reg[9] ; output \slaveRegDo_mux_2_reg[10] ; output \slaveRegDo_mux_2_reg[11] ; output \slaveRegDo_mux_2_reg[12] ; output \slaveRegDo_mux_2_reg[13] ; output \slaveRegDo_mux_2_reg[14] ; output \slaveRegDo_mux_2_reg[15] ; output \xsdb_reg_reg[15]_0 ; output [3:0]D; output \slaveRegDo_mux_2_reg[0] ; input [4:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[0] ; input [12:0]s_do_o; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \xsdb_reg_reg[3]_0 ; input s_den_o; input en_adv_trigger; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; input \xsdb_reg_reg[3]_1 ; input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; input \xsdb_reg_reg[2]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \xsdb_reg_reg[1]_0 ; input [0:0]Q; input [15:0]SEQUENCER_STATE_O; input s_dclk_o; wire [3:0]D; wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ; wire [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; wire [0:0]Q; wire [15:0]SEQUENCER_STATE_O; wire en_adv_trigger; wire [4:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [12:0]s_do_o; wire \slaveRegDo_mux_2[1]_i_2_n_0 ; wire \slaveRegDo_mux_2[1]_i_3_n_0 ; wire \slaveRegDo_mux_2[2]_i_2_n_0 ; wire \slaveRegDo_mux_2[3]_i_2_n_0 ; wire \slaveRegDo_mux_2[4]_i_2_n_0 ; wire \slaveRegDo_mux_2_reg[0] ; wire \slaveRegDo_mux_2_reg[10] ; wire \slaveRegDo_mux_2_reg[11] ; wire \slaveRegDo_mux_2_reg[12] ; wire \slaveRegDo_mux_2_reg[13] ; wire \slaveRegDo_mux_2_reg[14] ; wire \slaveRegDo_mux_2_reg[15] ; wire \slaveRegDo_mux_2_reg[5] ; wire \slaveRegDo_mux_2_reg[6] ; wire \slaveRegDo_mux_2_reg[7] ; wire \slaveRegDo_mux_2_reg[8] ; wire \slaveRegDo_mux_2_reg[9] ; wire \xsdb_reg_reg[15]_0 ; wire \xsdb_reg_reg[1]_0 ; wire \xsdb_reg_reg[2]_0 ; wire \xsdb_reg_reg[3]_0 ; wire \xsdb_reg_reg[3]_1 ; wire \xsdb_reg_reg_n_0_[10] ; wire \xsdb_reg_reg_n_0_[11] ; wire \xsdb_reg_reg_n_0_[12] ; wire \xsdb_reg_reg_n_0_[13] ; wire \xsdb_reg_reg_n_0_[14] ; wire \xsdb_reg_reg_n_0_[15] ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[3] ; wire \xsdb_reg_reg_n_0_[4] ; wire \xsdb_reg_reg_n_0_[5] ; wire \xsdb_reg_reg_n_0_[6] ; wire \xsdb_reg_reg_n_0_[7] ; wire \xsdb_reg_reg_n_0_[8] ; wire \xsdb_reg_reg_n_0_[9] ; LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[10]_i_1 (.I0(\xsdb_reg_reg_n_0_[10] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[7]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[10] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[11]_i_1 (.I0(\xsdb_reg_reg_n_0_[11] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[8]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[11] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[12]_i_1 (.I0(\xsdb_reg_reg_n_0_[12] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[9]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[12] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[13]_i_1 (.I0(\xsdb_reg_reg_n_0_[13] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[10]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[13] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[14]_i_1 (.I0(\xsdb_reg_reg_n_0_[14] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[11]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[14] )); LUT6 #( .INIT(64'hF4F444F444444444)) \slaveRegDo_mux_2[15]_i_2 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_do_o[12]), .I2(\xsdb_reg_reg_n_0_[15] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .O(\slaveRegDo_mux_2_reg[15] )); LUT4 #( .INIT(16'h4F44)) \slaveRegDo_mux_2[1]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [0]), .I2(\slaveRegDo_mux_2[1]_i_2_n_0 ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[0])); LUT6 #( .INIT(64'hDFDFFFFFDFDFF3FF)) \slaveRegDo_mux_2[1]_i_2 (.I0(\slaveRegDo_mux_2[1]_i_3_n_0 ), .I1(s_daddr_o[4]), .I2(s_daddr_o[2]), .I3(s_do_o[0]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .O(\slaveRegDo_mux_2[1]_i_2_n_0 )); LUT5 #( .INIT(32'hAFC0A0C0)) \slaveRegDo_mux_2[1]_i_3 (.I0(\xsdb_reg_reg_n_0_[1] ), .I1(\xsdb_reg_reg[1]_0 ), .I2(s_daddr_o[1]), .I3(s_daddr_o[0]), .I4(Q), .O(\slaveRegDo_mux_2[1]_i_3_n_0 )); LUT5 #( .INIT(32'hFF4F4444)) \slaveRegDo_mux_2[2]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [1]), .I2(\slaveRegDo_mux_2[2]_i_2_n_0 ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[1])); LUT6 #( .INIT(64'hDFCFCFFFDFFFCFFF)) \slaveRegDo_mux_2[2]_i_2 (.I0(\xsdb_reg_reg_n_0_[2] ), .I1(s_daddr_o[4]), .I2(s_daddr_o[3]), .I3(s_daddr_o[0]), .I4(s_daddr_o[1]), .I5(\xsdb_reg_reg[2]_0 ), .O(\slaveRegDo_mux_2[2]_i_2_n_0 )); LUT5 #( .INIT(32'hFF4F4444)) \slaveRegDo_mux_2[3]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [2]), .I2(\slaveRegDo_mux_2[3]_i_2_n_0 ), .I3(\xsdb_reg_reg[3]_1 ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .O(D[2])); LUT6 #( .INIT(64'hFFFF47FFFFFFFFFF)) \slaveRegDo_mux_2[3]_i_2 (.I0(\xsdb_reg_reg_n_0_[3] ), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg[3]_0 ), .I3(s_daddr_o[1]), .I4(s_daddr_o[4]), .I5(s_daddr_o[3]), .O(\slaveRegDo_mux_2[3]_i_2_n_0 )); LUT5 #( .INIT(32'hFFFF44F4)) \slaveRegDo_mux_2[4]_i_1 (.I0(\slaveRegDo_mux_2[4]_i_2_n_0 ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 [3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ), .O(D[3])); LUT6 #( .INIT(64'h0D0DDD0DDDDDDDDD)) \slaveRegDo_mux_2[4]_i_2 (.I0(s_do_o[1]), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I2(\xsdb_reg_reg_n_0_[4] ), .I3(s_daddr_o[1]), .I4(s_daddr_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .O(\slaveRegDo_mux_2[4]_i_2_n_0 )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[5]_i_1 (.I0(\xsdb_reg_reg_n_0_[5] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[2]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[5] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[6]_i_1 (.I0(\xsdb_reg_reg_n_0_[6] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[3]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[6] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[7]_i_1 (.I0(\xsdb_reg_reg_n_0_[7] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[4]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[7] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[8]_i_1 (.I0(\xsdb_reg_reg_n_0_[8] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[5]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[8] )); LUT6 #( .INIT(64'hA200A200FFFFA200)) \slaveRegDo_mux_2[9]_i_1 (.I0(\xsdb_reg_reg_n_0_[9] ), .I1(s_daddr_o[1]), .I2(s_daddr_o[3]), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[0] ), .I4(s_do_o[6]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .O(\slaveRegDo_mux_2_reg[9] )); LUT2 #( .INIT(4'h2)) \xsdb_reg[3]_i_1__0 (.I0(s_den_o), .I1(en_adv_trigger), .O(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[0]), .Q(\slaveRegDo_mux_2_reg[0] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[10]), .Q(\xsdb_reg_reg_n_0_[10] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[11]), .Q(\xsdb_reg_reg_n_0_[11] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[12]), .Q(\xsdb_reg_reg_n_0_[12] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[13]), .Q(\xsdb_reg_reg_n_0_[13] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[14]), .Q(\xsdb_reg_reg_n_0_[14] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[15]), .Q(\xsdb_reg_reg_n_0_[15] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[4]), .Q(\xsdb_reg_reg_n_0_[4] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[5]), .Q(\xsdb_reg_reg_n_0_[5] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[6]), .Q(\xsdb_reg_reg_n_0_[6] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[7]), .Q(\xsdb_reg_reg_n_0_[7] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[8]), .Q(\xsdb_reg_reg_n_0_[8] ), .R(\xsdb_reg_reg[15]_0 )); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(s_den_o), .D(SEQUENCER_STATE_O[9]), .Q(\xsdb_reg_reg_n_0_[9] ), .R(\xsdb_reg_reg[15]_0 )); endmodule
8
2,480
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_167 (D, Q, \G_1PIPE_IFACE.s_daddr_r_reg[7] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[3] , \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[4] , s_daddr_o, \xsdb_reg_reg[0]_0 , \xsdb_reg_reg[0]_1 , s_den_o, \I_YESLUT6.I_YES_OREG.O_reg_reg , s_dclk_o); output [0:0]D; output [0:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input [1:0]s_daddr_o; input \xsdb_reg_reg[0]_0 ; input \xsdb_reg_reg[0]_1 ; input s_den_o; input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ; input s_dclk_o; wire [0:0]D; wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ; wire [0:0]Q; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_2[0]_i_4_n_0 ; wire \xsdb_reg_reg[0]_0 ; wire \xsdb_reg_reg[0]_1 ; wire \xsdb_reg_reg_n_0_[0] ; LUT6 #( .INIT(64'hFFFFFFFFF444F4F4)) \slaveRegDo_mux_2[0]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I4(\slaveRegDo_mux_2[0]_i_4_n_0 ), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ), .O(D)); LUT6 #( .INIT(64'h555D775DDD5DFF5D)) \slaveRegDo_mux_2[0]_i_4 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(s_daddr_o[1]), .I4(\xsdb_reg_reg[0]_0 ), .I5(\xsdb_reg_reg[0]_1 ), .O(\slaveRegDo_mux_2[0]_i_4_n_0 )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(\I_YESLUT6.I_YES_OREG.O_reg_reg [0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(\I_YESLUT6.I_YES_OREG.O_reg_reg [1]), .Q(Q), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_167 (D, Q, \G_1PIPE_IFACE.s_daddr_r_reg[7] , \G_1PIPE_IFACE.s_daddr_r_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[5] , \G_1PIPE_IFACE.s_daddr_r_reg[3] , \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[4] , s_daddr_o, \xsdb_reg_reg[0]_0 , \xsdb_reg_reg[0]_1 , s_den_o, \I_YESLUT6.I_YES_OREG.O_reg_reg , s_dclk_o);
output [0:0]D; output [0:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[7] ; input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[5] ; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; input [1:0]s_daddr_o; input \xsdb_reg_reg[0]_0 ; input \xsdb_reg_reg[0]_1 ; input s_den_o; input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ; input s_dclk_o; wire [0:0]D; wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ; wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ; wire [0:0]Q; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_2[0]_i_4_n_0 ; wire \xsdb_reg_reg[0]_0 ; wire \xsdb_reg_reg[0]_1 ; wire \xsdb_reg_reg_n_0_[0] ; LUT6 #( .INIT(64'hFFFFFFFFF444F4F4)) \slaveRegDo_mux_2[0]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ), .I1(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I2(\G_1PIPE_IFACE.s_daddr_r_reg[5] ), .I3(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I4(\slaveRegDo_mux_2[0]_i_4_n_0 ), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ), .O(D)); LUT6 #( .INIT(64'h555D775DDD5DFF5D)) \slaveRegDo_mux_2[0]_i_4 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I1(s_daddr_o[0]), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(s_daddr_o[1]), .I4(\xsdb_reg_reg[0]_0 ), .I5(\xsdb_reg_reg[0]_1 ), .O(\slaveRegDo_mux_2[0]_i_4_n_0 )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(\I_YESLUT6.I_YES_OREG.O_reg_reg [0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(\I_YESLUT6.I_YES_OREG.O_reg_reg [1]), .Q(Q), .R(1'b0)); endmodule
8
2,481
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_168 (\slaveRegDo_mux_2_reg[3] , s_den_o, out, s_dclk_o, \G_1PIPE_IFACE.s_daddr_r_reg[2] , s_do_o, s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[4] ); output \slaveRegDo_mux_2_reg[3] ; input s_den_o; input out; input s_dclk_o; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [0:0]s_do_o; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire out; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [0:0]s_do_o; wire \slaveRegDo_mux_2_reg[3] ; wire \xsdb_reg_reg_n_0_[3] ; LUT6 #( .INIT(64'hF004000400040004)) \slaveRegDo_mux_2[3]_i_3 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I1(s_do_o), .I2(s_daddr_o[0]), .I3(s_daddr_o[1]), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I5(\xsdb_reg_reg_n_0_[3] ), .O(\slaveRegDo_mux_2_reg[3] )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(out), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_168 (\slaveRegDo_mux_2_reg[3] , s_den_o, out, s_dclk_o, \G_1PIPE_IFACE.s_daddr_r_reg[2] , s_do_o, s_daddr_o, \G_1PIPE_IFACE.s_daddr_r_reg[4] );
output \slaveRegDo_mux_2_reg[3] ; input s_den_o; input out; input s_dclk_o; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input [0:0]s_do_o; input [1:0]s_daddr_o; input \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ; wire out; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [0:0]s_do_o; wire \slaveRegDo_mux_2_reg[3] ; wire \xsdb_reg_reg_n_0_[3] ; LUT6 #( .INIT(64'hF004000400040004)) \slaveRegDo_mux_2[3]_i_3 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I1(s_do_o), .I2(s_daddr_o[0]), .I3(s_daddr_o[1]), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[4] ), .I5(\xsdb_reg_reg_n_0_[3] ), .O(\slaveRegDo_mux_2_reg[3] )); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(out), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); endmodule
8
2,482
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_173 (\slaveRegDo_mux_0_reg[0] , \slaveRegDo_mux_0_reg[3] , \slaveRegDo_mux_0_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[3] , s_daddr_o, Q, \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 , s_den_o, CAP_DONE_O_reg, s_dclk_o); output \slaveRegDo_mux_0_reg[0] ; output \slaveRegDo_mux_0_reg[3] ; output [1:0]\slaveRegDo_mux_0_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input [1:0]s_daddr_o; input [1:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; input s_den_o; input [3:0]CAP_DONE_O_reg; input s_dclk_o; wire [3:0]CAP_DONE_O_reg; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; wire [1:0]Q; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_0_reg[0] ; wire [1:0]\slaveRegDo_mux_0_reg[2] ; wire \slaveRegDo_mux_0_reg[3] ; wire \xsdb_reg_reg_n_0_[0] ; wire \xsdb_reg_reg_n_0_[3] ; LUT6 #( .INIT(64'h00000000DDDFFFDF)) \slaveRegDo_mux_0[0]_i_6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_daddr_o[1]), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(s_daddr_o[0]), .I4(Q[0]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ), .O(\slaveRegDo_mux_0_reg[0] )); LUT6 #( .INIT(64'h00000000DDDFFFDF)) \slaveRegDo_mux_0[3]_i_6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_daddr_o[1]), .I2(\xsdb_reg_reg_n_0_[3] ), .I3(s_daddr_o[0]), .I4(Q[1]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ), .O(\slaveRegDo_mux_0_reg[3] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[1]), .Q(\slaveRegDo_mux_0_reg[2] [0]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[2]), .Q(\slaveRegDo_mux_0_reg[2] [1]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_173 (\slaveRegDo_mux_0_reg[0] , \slaveRegDo_mux_0_reg[3] , \slaveRegDo_mux_0_reg[2] , \G_1PIPE_IFACE.s_daddr_r_reg[3] , s_daddr_o, Q, \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 , \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 , s_den_o, CAP_DONE_O_reg, s_dclk_o);
output \slaveRegDo_mux_0_reg[0] ; output \slaveRegDo_mux_0_reg[3] ; output [1:0]\slaveRegDo_mux_0_reg[2] ; input \G_1PIPE_IFACE.s_daddr_r_reg[3] ; input [1:0]s_daddr_o; input [1:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; input s_den_o; input [3:0]CAP_DONE_O_reg; input s_dclk_o; wire [3:0]CAP_DONE_O_reg; wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ; wire [1:0]Q; wire [1:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire \slaveRegDo_mux_0_reg[0] ; wire [1:0]\slaveRegDo_mux_0_reg[2] ; wire \slaveRegDo_mux_0_reg[3] ; wire \xsdb_reg_reg_n_0_[0] ; wire \xsdb_reg_reg_n_0_[3] ; LUT6 #( .INIT(64'h00000000DDDFFFDF)) \slaveRegDo_mux_0[0]_i_6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_daddr_o[1]), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(s_daddr_o[0]), .I4(Q[0]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ), .O(\slaveRegDo_mux_0_reg[0] )); LUT6 #( .INIT(64'h00000000DDDFFFDF)) \slaveRegDo_mux_0[3]_i_6 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ), .I1(s_daddr_o[1]), .I2(\xsdb_reg_reg_n_0_[3] ), .I3(s_daddr_o[0]), .I4(Q[1]), .I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ), .O(\slaveRegDo_mux_0_reg[3] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[1]), .Q(\slaveRegDo_mux_0_reg[2] [0]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[2]), .Q(\slaveRegDo_mux_0_reg[2] [1]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(s_den_o), .D(CAP_DONE_O_reg[3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); endmodule
8
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data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
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module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_180 (\slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[13] , Q, \G_1PIPE_IFACE.s_daddr_r_reg[1] , \slaveRegDo_ff8_reg[12] , D, \parallel_dout_reg[12] , \slaveRegDo_ff9_reg[8] , \parallel_dout_reg[6] , \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 , slaveRegDo_ffa, \G_1PIPE_IFACE.s_daddr_r_reg[2] , \parallel_dout_reg[10] , \parallel_dout_reg[14] , \parallel_dout_reg[15] , slaveRegDo_ff9, \slaveRegDo_ff8_reg[7] , \slaveRegDo_ff8_reg[12]_0 , \parallel_dout_reg[13] , E, \CFG_DATA_O_reg[15] , s_dclk_o); output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[13] ; output [4:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \slaveRegDo_ff8_reg[12] ; input [3:0]D; input \parallel_dout_reg[12] ; input \slaveRegDo_ff9_reg[8] ; input \parallel_dout_reg[6] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; input [0:0]slaveRegDo_ffa; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \parallel_dout_reg[10] ; input \parallel_dout_reg[14] ; input \parallel_dout_reg[15] ; input [0:0]slaveRegDo_ff9; input \slaveRegDo_ff8_reg[7] ; input \slaveRegDo_ff8_reg[12]_0 ; input \parallel_dout_reg[13] ; input [0:0]E; input [15:0]\CFG_DATA_O_reg[15] ; input s_dclk_o; wire [15:0]\CFG_DATA_O_reg[15] ; wire [3:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire [4:0]Q; wire \parallel_dout_reg[10] ; wire \parallel_dout_reg[12] ; wire \parallel_dout_reg[13] ; wire \parallel_dout_reg[14] ; wire \parallel_dout_reg[15] ; wire \parallel_dout_reg[6] ; wire s_dclk_o; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[12]_0 ; wire \slaveRegDo_ff8_reg[7] ; wire [0:0]slaveRegDo_ff9; wire \slaveRegDo_ff9_reg[8] ; wire [0:0]slaveRegDo_ffa; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[8] ; wire \xsdb_reg_reg_n_0_[0] ; wire \xsdb_reg_reg_n_0_[10] ; wire \xsdb_reg_reg_n_0_[12] ; wire \xsdb_reg_reg_n_0_[13] ; wire \xsdb_reg_reg_n_0_[14] ; wire \xsdb_reg_reg_n_0_[15] ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[3] ; wire \xsdb_reg_reg_n_0_[6] ; wire \xsdb_reg_reg_n_0_[8] ; LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[0]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[0] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[10]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[10] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[10] ), .O(\slaveRegDo_mux_3_reg[10] )); LUT6 #( .INIT(64'hFFF8000000F80000)) \slaveRegDo_mux_3[12]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I1(\xsdb_reg_reg_n_0_[12] ), .I2(\slaveRegDo_ff8_reg[12] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[12] ), .O(\slaveRegDo_mux_3_reg[12] )); LUT6 #( .INIT(64'hFF80000000800000)) \slaveRegDo_mux_3[13]_i_1 (.I0(D[1]), .I1(D[0]), .I2(\xsdb_reg_reg_n_0_[13] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[13] ), .O(\slaveRegDo_mux_3_reg[13] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[14]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[14] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[14] ), .O(\slaveRegDo_mux_3_reg[14] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[15]_i_2 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[15] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[15] ), .O(\slaveRegDo_mux_3_reg[15] )); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[1]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[1] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[1] )); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[2]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[2] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[2] )); LUT5 #( .INIT(32'hCAF0CA00)) \slaveRegDo_mux_3[3]_i_3 (.I0(slaveRegDo_ffa), .I1(\xsdb_reg_reg_n_0_[3] ), .I2(D[0]), .I3(D[1]), .I4(slaveRegDo_ff9), .O(\slaveRegDo_mux_3_reg[3] )); LUT6 #( .INIT(64'hFFF8000000F80000)) \slaveRegDo_mux_3[6]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I1(\xsdb_reg_reg_n_0_[6] ), .I2(\slaveRegDo_ff9_reg[8] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[6] ), .O(\slaveRegDo_mux_3_reg[6] )); LUT6 #( .INIT(64'hACFFACF0AC0FAC00)) \slaveRegDo_mux_3[8]_i_3 (.I0(\xsdb_reg_reg_n_0_[8] ), .I1(slaveRegDo_ff9), .I2(D[1]), .I3(D[0]), .I4(\slaveRegDo_ff8_reg[12]_0 ), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[8] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [10]), .Q(\xsdb_reg_reg_n_0_[10] ), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [11]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [12]), .Q(\xsdb_reg_reg_n_0_[12] ), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [13]), .Q(\xsdb_reg_reg_n_0_[13] ), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [14]), .Q(\xsdb_reg_reg_n_0_[14] ), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [15]), .Q(\xsdb_reg_reg_n_0_[15] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [4]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [5]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [6]), .Q(\xsdb_reg_reg_n_0_[6] ), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [7]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [8]), .Q(\xsdb_reg_reg_n_0_[8] ), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [9]), .Q(Q[3]), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_180 (\slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[13] , Q, \G_1PIPE_IFACE.s_daddr_r_reg[1] , \slaveRegDo_ff8_reg[12] , D, \parallel_dout_reg[12] , \slaveRegDo_ff9_reg[8] , \parallel_dout_reg[6] , \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 , slaveRegDo_ffa, \G_1PIPE_IFACE.s_daddr_r_reg[2] , \parallel_dout_reg[10] , \parallel_dout_reg[14] , \parallel_dout_reg[15] , slaveRegDo_ff9, \slaveRegDo_ff8_reg[7] , \slaveRegDo_ff8_reg[12]_0 , \parallel_dout_reg[13] , E, \CFG_DATA_O_reg[15] , s_dclk_o);
output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[13] ; output [4:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \slaveRegDo_ff8_reg[12] ; input [3:0]D; input \parallel_dout_reg[12] ; input \slaveRegDo_ff9_reg[8] ; input \parallel_dout_reg[6] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; input [0:0]slaveRegDo_ffa; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \parallel_dout_reg[10] ; input \parallel_dout_reg[14] ; input \parallel_dout_reg[15] ; input [0:0]slaveRegDo_ff9; input \slaveRegDo_ff8_reg[7] ; input \slaveRegDo_ff8_reg[12]_0 ; input \parallel_dout_reg[13] ; input [0:0]E; input [15:0]\CFG_DATA_O_reg[15] ; input s_dclk_o; wire [15:0]\CFG_DATA_O_reg[15] ; wire [3:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire [4:0]Q; wire \parallel_dout_reg[10] ; wire \parallel_dout_reg[12] ; wire \parallel_dout_reg[13] ; wire \parallel_dout_reg[14] ; wire \parallel_dout_reg[15] ; wire \parallel_dout_reg[6] ; wire s_dclk_o; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[12]_0 ; wire \slaveRegDo_ff8_reg[7] ; wire [0:0]slaveRegDo_ff9; wire \slaveRegDo_ff9_reg[8] ; wire [0:0]slaveRegDo_ffa; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[8] ; wire \xsdb_reg_reg_n_0_[0] ; wire \xsdb_reg_reg_n_0_[10] ; wire \xsdb_reg_reg_n_0_[12] ; wire \xsdb_reg_reg_n_0_[13] ; wire \xsdb_reg_reg_n_0_[14] ; wire \xsdb_reg_reg_n_0_[15] ; wire \xsdb_reg_reg_n_0_[1] ; wire \xsdb_reg_reg_n_0_[2] ; wire \xsdb_reg_reg_n_0_[3] ; wire \xsdb_reg_reg_n_0_[6] ; wire \xsdb_reg_reg_n_0_[8] ; LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[0]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[0] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[0] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[10]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[10] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[10] ), .O(\slaveRegDo_mux_3_reg[10] )); LUT6 #( .INIT(64'hFFF8000000F80000)) \slaveRegDo_mux_3[12]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I1(\xsdb_reg_reg_n_0_[12] ), .I2(\slaveRegDo_ff8_reg[12] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[12] ), .O(\slaveRegDo_mux_3_reg[12] )); LUT6 #( .INIT(64'hFF80000000800000)) \slaveRegDo_mux_3[13]_i_1 (.I0(D[1]), .I1(D[0]), .I2(\xsdb_reg_reg_n_0_[13] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[13] ), .O(\slaveRegDo_mux_3_reg[13] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[14]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[14] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[14] ), .O(\slaveRegDo_mux_3_reg[14] )); LUT6 #( .INIT(64'hFFFF454045404540)) \slaveRegDo_mux_3[15]_i_2 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .I1(\xsdb_reg_reg_n_0_[15] ), .I2(D[0]), .I3(slaveRegDo_ffa), .I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .I5(\parallel_dout_reg[15] ), .O(\slaveRegDo_mux_3_reg[15] )); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[1]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[1] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[1] )); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \slaveRegDo_mux_3[2]_i_3 (.I0(\slaveRegDo_ff8_reg[7] ), .I1(slaveRegDo_ff9), .I2(\xsdb_reg_reg_n_0_[2] ), .I3(D[0]), .I4(D[1]), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[2] )); LUT5 #( .INIT(32'hCAF0CA00)) \slaveRegDo_mux_3[3]_i_3 (.I0(slaveRegDo_ffa), .I1(\xsdb_reg_reg_n_0_[3] ), .I2(D[0]), .I3(D[1]), .I4(slaveRegDo_ff9), .O(\slaveRegDo_mux_3_reg[3] )); LUT6 #( .INIT(64'hFFF8000000F80000)) \slaveRegDo_mux_3[6]_i_1 (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .I1(\xsdb_reg_reg_n_0_[6] ), .I2(\slaveRegDo_ff9_reg[8] ), .I3(D[2]), .I4(D[3]), .I5(\parallel_dout_reg[6] ), .O(\slaveRegDo_mux_3_reg[6] )); LUT6 #( .INIT(64'hACFFACF0AC0FAC00)) \slaveRegDo_mux_3[8]_i_3 (.I0(\xsdb_reg_reg_n_0_[8] ), .I1(slaveRegDo_ff9), .I2(D[1]), .I3(D[0]), .I4(\slaveRegDo_ff8_reg[12]_0 ), .I5(slaveRegDo_ffa), .O(\slaveRegDo_mux_3_reg[8] )); FDRE \xsdb_reg_reg[0] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [0]), .Q(\xsdb_reg_reg_n_0_[0] ), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [10]), .Q(\xsdb_reg_reg_n_0_[10] ), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [11]), .Q(Q[4]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [12]), .Q(\xsdb_reg_reg_n_0_[12] ), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [13]), .Q(\xsdb_reg_reg_n_0_[13] ), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [14]), .Q(\xsdb_reg_reg_n_0_[14] ), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [15]), .Q(\xsdb_reg_reg_n_0_[15] ), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [1]), .Q(\xsdb_reg_reg_n_0_[1] ), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [2]), .Q(\xsdb_reg_reg_n_0_[2] ), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [3]), .Q(\xsdb_reg_reg_n_0_[3] ), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [4]), .Q(Q[0]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [5]), .Q(Q[1]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [6]), .Q(\xsdb_reg_reg_n_0_[6] ), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [7]), .Q(Q[2]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [8]), .Q(\xsdb_reg_reg_n_0_[8] ), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_o), .CE(E), .D(\CFG_DATA_O_reg[15] [9]), .Q(Q[3]), .R(1'b0)); endmodule
8
2,484
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_182 (s_do_o, s_den_i, din_i, s_dclk_i); output [15:0]s_do_o; input s_den_i; input [15:0]din_i; input s_dclk_i; wire [15:0]din_i; wire s_dclk_i; wire s_den_i; wire [15:0]s_do_o; FDRE \xsdb_reg_reg[0] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[0]), .Q(s_do_o[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[10]), .Q(s_do_o[10]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[11]), .Q(s_do_o[11]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[12]), .Q(s_do_o[12]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[13]), .Q(s_do_o[13]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[14]), .Q(s_do_o[14]), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[15]), .Q(s_do_o[15]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[1]), .Q(s_do_o[1]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[2]), .Q(s_do_o[2]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[3]), .Q(s_do_o[3]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[4]), .Q(s_do_o[4]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[5]), .Q(s_do_o[5]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[6]), .Q(s_do_o[6]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[7]), .Q(s_do_o[7]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[8]), .Q(s_do_o[8]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[9]), .Q(s_do_o[9]), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_182 (s_do_o, s_den_i, din_i, s_dclk_i);
output [15:0]s_do_o; input s_den_i; input [15:0]din_i; input s_dclk_i; wire [15:0]din_i; wire s_dclk_i; wire s_den_i; wire [15:0]s_do_o; FDRE \xsdb_reg_reg[0] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[0]), .Q(s_do_o[0]), .R(1'b0)); FDRE \xsdb_reg_reg[10] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[10]), .Q(s_do_o[10]), .R(1'b0)); FDRE \xsdb_reg_reg[11] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[11]), .Q(s_do_o[11]), .R(1'b0)); FDRE \xsdb_reg_reg[12] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[12]), .Q(s_do_o[12]), .R(1'b0)); FDRE \xsdb_reg_reg[13] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[13]), .Q(s_do_o[13]), .R(1'b0)); FDRE \xsdb_reg_reg[14] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[14]), .Q(s_do_o[14]), .R(1'b0)); FDRE \xsdb_reg_reg[15] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[15]), .Q(s_do_o[15]), .R(1'b0)); FDRE \xsdb_reg_reg[1] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[1]), .Q(s_do_o[1]), .R(1'b0)); FDRE \xsdb_reg_reg[2] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[2]), .Q(s_do_o[2]), .R(1'b0)); FDRE \xsdb_reg_reg[3] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[3]), .Q(s_do_o[3]), .R(1'b0)); FDRE \xsdb_reg_reg[4] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[4]), .Q(s_do_o[4]), .R(1'b0)); FDRE \xsdb_reg_reg[5] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[5]), .Q(s_do_o[5]), .R(1'b0)); FDRE \xsdb_reg_reg[6] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[6]), .Q(s_do_o[6]), .R(1'b0)); FDRE \xsdb_reg_reg[7] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[7]), .Q(s_do_o[7]), .R(1'b0)); FDRE \xsdb_reg_reg[8] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[8]), .Q(s_do_o[8]), .R(1'b0)); FDRE \xsdb_reg_reg[9] (.C(s_dclk_i), .CE(s_den_i), .D(din_i[9]), .Q(s_do_o[9]), .R(1'b0)); endmodule
8
2,485
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream (\slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[13] , Q, \G_1PIPE_IFACE.s_daddr_r_reg[1] , \slaveRegDo_ff8_reg[12] , D, \parallel_dout_reg[12] , \slaveRegDo_ff9_reg[8] , \parallel_dout_reg[6] , \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 , slaveRegDo_ffa, \G_1PIPE_IFACE.s_daddr_r_reg[2] , \parallel_dout_reg[10] , \parallel_dout_reg[14] , \parallel_dout_reg[15] , slaveRegDo_ff9, \slaveRegDo_ff8_reg[7] , \slaveRegDo_ff8_reg[12]_0 , \parallel_dout_reg[13] , E, \CFG_DATA_O_reg[15] , s_dclk_o); output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[13] ; output [4:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \slaveRegDo_ff8_reg[12] ; input [3:0]D; input \parallel_dout_reg[12] ; input \slaveRegDo_ff9_reg[8] ; input \parallel_dout_reg[6] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; input [0:0]slaveRegDo_ffa; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \parallel_dout_reg[10] ; input \parallel_dout_reg[14] ; input \parallel_dout_reg[15] ; input [0:0]slaveRegDo_ff9; input \slaveRegDo_ff8_reg[7] ; input \slaveRegDo_ff8_reg[12]_0 ; input \parallel_dout_reg[13] ; input [0:0]E; input [15:0]\CFG_DATA_O_reg[15] ; input s_dclk_o; wire [15:0]\CFG_DATA_O_reg[15] ; wire [3:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire [4:0]Q; wire \parallel_dout_reg[10] ; wire \parallel_dout_reg[12] ; wire \parallel_dout_reg[13] ; wire \parallel_dout_reg[14] ; wire \parallel_dout_reg[15] ; wire \parallel_dout_reg[6] ; wire s_dclk_o; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[12]_0 ; wire \slaveRegDo_ff8_reg[7] ; wire [0:0]slaveRegDo_ff9; wire \slaveRegDo_ff9_reg[8] ; wire [0:0]slaveRegDo_ffa; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[8] ; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_180 \I_EN_STAT_EQ1.U_STAT (.\CFG_DATA_O_reg[15] (\CFG_DATA_O_reg[15] ), .D(D), .E(E), .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .Q(Q), .\parallel_dout_reg[10] (\parallel_dout_reg[10] ), .\parallel_dout_reg[12] (\parallel_dout_reg[12] ), .\parallel_dout_reg[13] (\parallel_dout_reg[13] ), .\parallel_dout_reg[14] (\parallel_dout_reg[14] ), .\parallel_dout_reg[15] (\parallel_dout_reg[15] ), .\parallel_dout_reg[6] (\parallel_dout_reg[6] ), .s_dclk_o(s_dclk_o), .\slaveRegDo_ff8_reg[12] (\slaveRegDo_ff8_reg[12] ), .\slaveRegDo_ff8_reg[12]_0 (\slaveRegDo_ff8_reg[12]_0 ), .\slaveRegDo_ff8_reg[7] (\slaveRegDo_ff8_reg[7] ), .slaveRegDo_ff9(slaveRegDo_ff9), .\slaveRegDo_ff9_reg[8] (\slaveRegDo_ff9_reg[8] ), .slaveRegDo_ffa(slaveRegDo_ffa), .\slaveRegDo_mux_3_reg[0] (\slaveRegDo_mux_3_reg[0] ), .\slaveRegDo_mux_3_reg[10] (\slaveRegDo_mux_3_reg[10] ), .\slaveRegDo_mux_3_reg[12] (\slaveRegDo_mux_3_reg[12] ), .\slaveRegDo_mux_3_reg[13] (\slaveRegDo_mux_3_reg[13] ), .\slaveRegDo_mux_3_reg[14] (\slaveRegDo_mux_3_reg[14] ), .\slaveRegDo_mux_3_reg[15] (\slaveRegDo_mux_3_reg[15] ), .\slaveRegDo_mux_3_reg[1] (\slaveRegDo_mux_3_reg[1] ), .\slaveRegDo_mux_3_reg[2] (\slaveRegDo_mux_3_reg[2] ), .\slaveRegDo_mux_3_reg[3] (\slaveRegDo_mux_3_reg[3] ), .\slaveRegDo_mux_3_reg[6] (\slaveRegDo_mux_3_reg[6] ), .\slaveRegDo_mux_3_reg[8] (\slaveRegDo_mux_3_reg[8] )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream (\slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[0] , \slaveRegDo_mux_3_reg[1] , \slaveRegDo_mux_3_reg[2] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[13] , Q, \G_1PIPE_IFACE.s_daddr_r_reg[1] , \slaveRegDo_ff8_reg[12] , D, \parallel_dout_reg[12] , \slaveRegDo_ff9_reg[8] , \parallel_dout_reg[6] , \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 , slaveRegDo_ffa, \G_1PIPE_IFACE.s_daddr_r_reg[2] , \parallel_dout_reg[10] , \parallel_dout_reg[14] , \parallel_dout_reg[15] , slaveRegDo_ff9, \slaveRegDo_ff8_reg[7] , \slaveRegDo_ff8_reg[12]_0 , \parallel_dout_reg[13] , E, \CFG_DATA_O_reg[15] , s_dclk_o);
output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[0] ; output \slaveRegDo_mux_3_reg[1] ; output \slaveRegDo_mux_3_reg[2] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[13] ; output [4:0]Q; input \G_1PIPE_IFACE.s_daddr_r_reg[1] ; input \slaveRegDo_ff8_reg[12] ; input [3:0]D; input \parallel_dout_reg[12] ; input \slaveRegDo_ff9_reg[8] ; input \parallel_dout_reg[6] ; input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; input [0:0]slaveRegDo_ffa; input \G_1PIPE_IFACE.s_daddr_r_reg[2] ; input \parallel_dout_reg[10] ; input \parallel_dout_reg[14] ; input \parallel_dout_reg[15] ; input [0:0]slaveRegDo_ff9; input \slaveRegDo_ff8_reg[7] ; input \slaveRegDo_ff8_reg[12]_0 ; input \parallel_dout_reg[13] ; input [0:0]E; input [15:0]\CFG_DATA_O_reg[15] ; input s_dclk_o; wire [15:0]\CFG_DATA_O_reg[15] ; wire [3:0]D; wire [0:0]E; wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ; wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ; wire [4:0]Q; wire \parallel_dout_reg[10] ; wire \parallel_dout_reg[12] ; wire \parallel_dout_reg[13] ; wire \parallel_dout_reg[14] ; wire \parallel_dout_reg[15] ; wire \parallel_dout_reg[6] ; wire s_dclk_o; wire \slaveRegDo_ff8_reg[12] ; wire \slaveRegDo_ff8_reg[12]_0 ; wire \slaveRegDo_ff8_reg[7] ; wire [0:0]slaveRegDo_ff9; wire \slaveRegDo_ff9_reg[8] ; wire [0:0]slaveRegDo_ffa; wire \slaveRegDo_mux_3_reg[0] ; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[1] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[8] ; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_180 \I_EN_STAT_EQ1.U_STAT (.\CFG_DATA_O_reg[15] (\CFG_DATA_O_reg[15] ), .D(D), .E(E), .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ), .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ), .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ), .Q(Q), .\parallel_dout_reg[10] (\parallel_dout_reg[10] ), .\parallel_dout_reg[12] (\parallel_dout_reg[12] ), .\parallel_dout_reg[13] (\parallel_dout_reg[13] ), .\parallel_dout_reg[14] (\parallel_dout_reg[14] ), .\parallel_dout_reg[15] (\parallel_dout_reg[15] ), .\parallel_dout_reg[6] (\parallel_dout_reg[6] ), .s_dclk_o(s_dclk_o), .\slaveRegDo_ff8_reg[12] (\slaveRegDo_ff8_reg[12] ), .\slaveRegDo_ff8_reg[12]_0 (\slaveRegDo_ff8_reg[12]_0 ), .\slaveRegDo_ff8_reg[7] (\slaveRegDo_ff8_reg[7] ), .slaveRegDo_ff9(slaveRegDo_ff9), .\slaveRegDo_ff9_reg[8] (\slaveRegDo_ff9_reg[8] ), .slaveRegDo_ffa(slaveRegDo_ffa), .\slaveRegDo_mux_3_reg[0] (\slaveRegDo_mux_3_reg[0] ), .\slaveRegDo_mux_3_reg[10] (\slaveRegDo_mux_3_reg[10] ), .\slaveRegDo_mux_3_reg[12] (\slaveRegDo_mux_3_reg[12] ), .\slaveRegDo_mux_3_reg[13] (\slaveRegDo_mux_3_reg[13] ), .\slaveRegDo_mux_3_reg[14] (\slaveRegDo_mux_3_reg[14] ), .\slaveRegDo_mux_3_reg[15] (\slaveRegDo_mux_3_reg[15] ), .\slaveRegDo_mux_3_reg[1] (\slaveRegDo_mux_3_reg[1] ), .\slaveRegDo_mux_3_reg[2] (\slaveRegDo_mux_3_reg[2] ), .\slaveRegDo_mux_3_reg[3] (\slaveRegDo_mux_3_reg[3] ), .\slaveRegDo_mux_3_reg[6] (\slaveRegDo_mux_3_reg[6] ), .\slaveRegDo_mux_3_reg[8] (\slaveRegDo_mux_3_reg[8] )); endmodule
8
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data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0 (\I_EN_CTL_EQ1.temp_en_reg_0 , toggle_reg, bram_en, \slaveRegDo_mux_3_reg[0] , \BRAM_DATA_reg[15] , s_dclk_o, D, \FSM_BRAM_ADDR_O_reg[9] , \FSM_BRAM_ADDR_O_reg[3] , Q, toggle_reg_0, config_fsm_we, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[10] , E, s_di_o); output \I_EN_CTL_EQ1.temp_en_reg_0 ; output toggle_reg; output bram_en; output \slaveRegDo_mux_3_reg[0] ; output [15:0]\BRAM_DATA_reg[15] ; input s_dclk_o; input [10:0]D; input \FSM_BRAM_ADDR_O_reg[9] ; input \FSM_BRAM_ADDR_O_reg[3] ; input [4:0]Q; input [0:0]toggle_reg_0; input config_fsm_we; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[10] ; input [0:0]E; input [15:0]s_di_o; wire [15:0]\BRAM_DATA_reg[15] ; wire [10:0]D; wire [0:0]E; wire \FSM_BRAM_ADDR_O_reg[3] ; wire \FSM_BRAM_ADDR_O_reg[9] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ; wire \I_EN_CTL_EQ1.temp_en_reg_0 ; wire [4:0]Q; wire bram_en; wire bram_en_i_4_n_0; wire config_fsm_en; wire config_fsm_we; wire reg_ce; wire s_dclk_o; wire [15:0]s_di_o; wire s_dwe_o; wire \slaveRegDo_mux_3_reg[0] ; wire toggle_reg; wire [0:0]toggle_reg_0; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_181 \I_EN_CTL_EQ1.U_CTL (.\BRAM_DATA_reg[15] (\BRAM_DATA_reg[15] ), .D(D), .E(E), .\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ), .\I_EN_CTL_EQ1.temp_en_reg (\I_EN_CTL_EQ1.temp_en_reg_0 ), .reg_ce(reg_ce), .s_dclk_o(s_dclk_o), .s_di_o(s_di_o), .s_dwe_o(s_dwe_o), .\slaveRegDo_mux_3_reg[0] (\slaveRegDo_mux_3_reg[0] )); FDRE \I_EN_CTL_EQ1.temp_en_reg (.C(s_dclk_o), .CE(1'b1), .D(reg_ce), .Q(config_fsm_en), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h0800)) bram_en_i_1 (.I0(\FSM_BRAM_ADDR_O_reg[9] ), .I1(\FSM_BRAM_ADDR_O_reg[3] ), .I2(Q[0]), .I3(bram_en_i_4_n_0), .O(bram_en)); LUT6 #( .INIT(64'h0001000000000000)) bram_en_i_4 (.I0(Q[3]), .I1(Q[4]), .I2(Q[1]), .I3(Q[2]), .I4(config_fsm_we), .I5(config_fsm_en), .O(bram_en_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hF7FF0800)) toggle_i_1 (.I0(\FSM_BRAM_ADDR_O_reg[9] ), .I1(\FSM_BRAM_ADDR_O_reg[3] ), .I2(Q[0]), .I3(bram_en_i_4_n_0), .I4(toggle_reg_0), .O(toggle_reg)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0 (\I_EN_CTL_EQ1.temp_en_reg_0 , toggle_reg, bram_en, \slaveRegDo_mux_3_reg[0] , \BRAM_DATA_reg[15] , s_dclk_o, D, \FSM_BRAM_ADDR_O_reg[9] , \FSM_BRAM_ADDR_O_reg[3] , Q, toggle_reg_0, config_fsm_we, s_dwe_o, \G_1PIPE_IFACE.s_daddr_r_reg[10] , E, s_di_o);
output \I_EN_CTL_EQ1.temp_en_reg_0 ; output toggle_reg; output bram_en; output \slaveRegDo_mux_3_reg[0] ; output [15:0]\BRAM_DATA_reg[15] ; input s_dclk_o; input [10:0]D; input \FSM_BRAM_ADDR_O_reg[9] ; input \FSM_BRAM_ADDR_O_reg[3] ; input [4:0]Q; input [0:0]toggle_reg_0; input config_fsm_we; input s_dwe_o; input \G_1PIPE_IFACE.s_daddr_r_reg[10] ; input [0:0]E; input [15:0]s_di_o; wire [15:0]\BRAM_DATA_reg[15] ; wire [10:0]D; wire [0:0]E; wire \FSM_BRAM_ADDR_O_reg[3] ; wire \FSM_BRAM_ADDR_O_reg[9] ; wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ; wire \I_EN_CTL_EQ1.temp_en_reg_0 ; wire [4:0]Q; wire bram_en; wire bram_en_i_4_n_0; wire config_fsm_en; wire config_fsm_we; wire reg_ce; wire s_dclk_o; wire [15:0]s_di_o; wire s_dwe_o; wire \slaveRegDo_mux_3_reg[0] ; wire toggle_reg; wire [0:0]toggle_reg_0; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_181 \I_EN_CTL_EQ1.U_CTL (.\BRAM_DATA_reg[15] (\BRAM_DATA_reg[15] ), .D(D), .E(E), .\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ), .\I_EN_CTL_EQ1.temp_en_reg (\I_EN_CTL_EQ1.temp_en_reg_0 ), .reg_ce(reg_ce), .s_dclk_o(s_dclk_o), .s_di_o(s_di_o), .s_dwe_o(s_dwe_o), .\slaveRegDo_mux_3_reg[0] (\slaveRegDo_mux_3_reg[0] )); FDRE \I_EN_CTL_EQ1.temp_en_reg (.C(s_dclk_o), .CE(1'b1), .D(reg_ce), .Q(config_fsm_en), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h0800)) bram_en_i_1 (.I0(\FSM_BRAM_ADDR_O_reg[9] ), .I1(\FSM_BRAM_ADDR_O_reg[3] ), .I2(Q[0]), .I3(bram_en_i_4_n_0), .O(bram_en)); LUT6 #( .INIT(64'h0001000000000000)) bram_en_i_4 (.I0(Q[3]), .I1(Q[4]), .I2(Q[1]), .I3(Q[2]), .I4(config_fsm_we), .I5(config_fsm_en), .O(bram_en_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'hF7FF0800)) toggle_i_1 (.I0(\FSM_BRAM_ADDR_O_reg[9] ), .I1(\FSM_BRAM_ADDR_O_reg[3] ), .I2(Q[0]), .I3(bram_en_i_4_n_0), .I4(toggle_reg_0), .O(toggle_reg)); endmodule
8
2,487
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1 (\xsdb_reg_reg[0] , \xsdb_reg_reg[0]_0 , \xsdb_reg_reg[0]_1 , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[13] , \slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[11] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[9] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[7] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[5] , \slaveRegDo_mux_3_reg[4] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[2] , debug_data_in, s_daddr_o, s_dwe_o, s_den_o, s_di_o, s_dclk_o); output \xsdb_reg_reg[0] ; output \xsdb_reg_reg[0]_0 ; output \xsdb_reg_reg[0]_1 ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[13] ; output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[11] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[9] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[7] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[5] ; output \slaveRegDo_mux_3_reg[4] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[2] ; output [1:0]debug_data_in; input [12:0]s_daddr_o; input s_dwe_o; input s_den_o; input [15:0]s_di_o; input s_dclk_o; wire [1:0]debug_data_in; wire [12:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [15:0]s_di_o; wire s_dwe_o; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[11] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[4] ; wire \slaveRegDo_mux_3_reg[5] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[7] ; wire \slaveRegDo_mux_3_reg[8] ; wire \slaveRegDo_mux_3_reg[9] ; wire \xsdb_reg_reg[0] ; wire \xsdb_reg_reg[0]_0 ; wire \xsdb_reg_reg[0]_1 ; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl \I_EN_CTL_EQ1.U_CTL (.debug_data_in(debug_data_in), .s_daddr_o(s_daddr_o), .s_dclk_o(s_dclk_o), .s_den_o(s_den_o), .s_di_o(s_di_o), .s_dwe_o(s_dwe_o), .\slaveRegDo_mux_3_reg[10] (\slaveRegDo_mux_3_reg[10] ), .\slaveRegDo_mux_3_reg[11] (\slaveRegDo_mux_3_reg[11] ), .\slaveRegDo_mux_3_reg[12] (\slaveRegDo_mux_3_reg[12] ), .\slaveRegDo_mux_3_reg[13] (\slaveRegDo_mux_3_reg[13] ), .\slaveRegDo_mux_3_reg[14] (\slaveRegDo_mux_3_reg[14] ), .\slaveRegDo_mux_3_reg[15] (\slaveRegDo_mux_3_reg[15] ), .\slaveRegDo_mux_3_reg[2] (\slaveRegDo_mux_3_reg[2] ), .\slaveRegDo_mux_3_reg[3] (\slaveRegDo_mux_3_reg[3] ), .\slaveRegDo_mux_3_reg[4] (\slaveRegDo_mux_3_reg[4] ), .\slaveRegDo_mux_3_reg[5] (\slaveRegDo_mux_3_reg[5] ), .\slaveRegDo_mux_3_reg[6] (\slaveRegDo_mux_3_reg[6] ), .\slaveRegDo_mux_3_reg[7] (\slaveRegDo_mux_3_reg[7] ), .\slaveRegDo_mux_3_reg[8] (\slaveRegDo_mux_3_reg[8] ), .\slaveRegDo_mux_3_reg[9] (\slaveRegDo_mux_3_reg[9] ), .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ), .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ), .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 )); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1 (\xsdb_reg_reg[0] , \xsdb_reg_reg[0]_0 , \xsdb_reg_reg[0]_1 , \slaveRegDo_mux_3_reg[15] , \slaveRegDo_mux_3_reg[14] , \slaveRegDo_mux_3_reg[13] , \slaveRegDo_mux_3_reg[12] , \slaveRegDo_mux_3_reg[11] , \slaveRegDo_mux_3_reg[10] , \slaveRegDo_mux_3_reg[9] , \slaveRegDo_mux_3_reg[8] , \slaveRegDo_mux_3_reg[7] , \slaveRegDo_mux_3_reg[6] , \slaveRegDo_mux_3_reg[5] , \slaveRegDo_mux_3_reg[4] , \slaveRegDo_mux_3_reg[3] , \slaveRegDo_mux_3_reg[2] , debug_data_in, s_daddr_o, s_dwe_o, s_den_o, s_di_o, s_dclk_o);
output \xsdb_reg_reg[0] ; output \xsdb_reg_reg[0]_0 ; output \xsdb_reg_reg[0]_1 ; output \slaveRegDo_mux_3_reg[15] ; output \slaveRegDo_mux_3_reg[14] ; output \slaveRegDo_mux_3_reg[13] ; output \slaveRegDo_mux_3_reg[12] ; output \slaveRegDo_mux_3_reg[11] ; output \slaveRegDo_mux_3_reg[10] ; output \slaveRegDo_mux_3_reg[9] ; output \slaveRegDo_mux_3_reg[8] ; output \slaveRegDo_mux_3_reg[7] ; output \slaveRegDo_mux_3_reg[6] ; output \slaveRegDo_mux_3_reg[5] ; output \slaveRegDo_mux_3_reg[4] ; output \slaveRegDo_mux_3_reg[3] ; output \slaveRegDo_mux_3_reg[2] ; output [1:0]debug_data_in; input [12:0]s_daddr_o; input s_dwe_o; input s_den_o; input [15:0]s_di_o; input s_dclk_o; wire [1:0]debug_data_in; wire [12:0]s_daddr_o; wire s_dclk_o; wire s_den_o; wire [15:0]s_di_o; wire s_dwe_o; wire \slaveRegDo_mux_3_reg[10] ; wire \slaveRegDo_mux_3_reg[11] ; wire \slaveRegDo_mux_3_reg[12] ; wire \slaveRegDo_mux_3_reg[13] ; wire \slaveRegDo_mux_3_reg[14] ; wire \slaveRegDo_mux_3_reg[15] ; wire \slaveRegDo_mux_3_reg[2] ; wire \slaveRegDo_mux_3_reg[3] ; wire \slaveRegDo_mux_3_reg[4] ; wire \slaveRegDo_mux_3_reg[5] ; wire \slaveRegDo_mux_3_reg[6] ; wire \slaveRegDo_mux_3_reg[7] ; wire \slaveRegDo_mux_3_reg[8] ; wire \slaveRegDo_mux_3_reg[9] ; wire \xsdb_reg_reg[0] ; wire \xsdb_reg_reg[0]_0 ; wire \xsdb_reg_reg[0]_1 ; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl \I_EN_CTL_EQ1.U_CTL (.debug_data_in(debug_data_in), .s_daddr_o(s_daddr_o), .s_dclk_o(s_dclk_o), .s_den_o(s_den_o), .s_di_o(s_di_o), .s_dwe_o(s_dwe_o), .\slaveRegDo_mux_3_reg[10] (\slaveRegDo_mux_3_reg[10] ), .\slaveRegDo_mux_3_reg[11] (\slaveRegDo_mux_3_reg[11] ), .\slaveRegDo_mux_3_reg[12] (\slaveRegDo_mux_3_reg[12] ), .\slaveRegDo_mux_3_reg[13] (\slaveRegDo_mux_3_reg[13] ), .\slaveRegDo_mux_3_reg[14] (\slaveRegDo_mux_3_reg[14] ), .\slaveRegDo_mux_3_reg[15] (\slaveRegDo_mux_3_reg[15] ), .\slaveRegDo_mux_3_reg[2] (\slaveRegDo_mux_3_reg[2] ), .\slaveRegDo_mux_3_reg[3] (\slaveRegDo_mux_3_reg[3] ), .\slaveRegDo_mux_3_reg[4] (\slaveRegDo_mux_3_reg[4] ), .\slaveRegDo_mux_3_reg[5] (\slaveRegDo_mux_3_reg[5] ), .\slaveRegDo_mux_3_reg[6] (\slaveRegDo_mux_3_reg[6] ), .\slaveRegDo_mux_3_reg[7] (\slaveRegDo_mux_3_reg[7] ), .\slaveRegDo_mux_3_reg[8] (\slaveRegDo_mux_3_reg[8] ), .\slaveRegDo_mux_3_reg[9] (\slaveRegDo_mux_3_reg[9] ), .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ), .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ), .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 )); endmodule
8
2,488
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2 (Q, E, \input_data_reg[31] , s_dclk_o); output [15:0]Q; input [0:0]E; input [15:0]\input_data_reg[31] ; input s_dclk_o; wire [0:0]E; wire [15:0]Q; wire [15:0]\input_data_reg[31] ; wire s_dclk_o; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat \I_EN_STAT_EQ1.U_STAT (.E(E), .Q(Q), .\input_data_reg[31] (\input_data_reg[31] ), .s_dclk_o(s_dclk_o)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2 (Q, E, \input_data_reg[31] , s_dclk_o);
output [15:0]Q; input [0:0]E; input [15:0]\input_data_reg[31] ; input s_dclk_o; wire [0:0]E; wire [15:0]Q; wire [15:0]\input_data_reg[31] ; wire s_dclk_o; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat \I_EN_STAT_EQ1.U_STAT (.E(E), .Q(Q), .\input_data_reg[31] (\input_data_reg[31] ), .s_dclk_o(s_dclk_o)); endmodule
8
2,489
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs (s_rst_o, s_dclk_o, s_den_o, s_dwe_o, s_daddr_o, s_di_o, sl_oport_o, s_do_i, sl_iport_i, s_drdy_i); output s_rst_o; output s_dclk_o; output s_den_o; output s_dwe_o; output [16:0]s_daddr_o; output [15:0]s_di_o; output [16:0]sl_oport_o; input [15:0]s_do_i; input [36:0]sl_iport_i; input s_drdy_i; wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ; wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ; wire [15:0]p_0_in; wire [10:0]reg_do; wire \reg_do[10]_i_2_n_0 ; wire \reg_do[15]_i_1_n_0 ; wire \reg_do[4]_i_2_n_0 ; wire \reg_do_reg_n_0_[0] ; wire \reg_do_reg_n_0_[10] ; wire \reg_do_reg_n_0_[11] ; wire \reg_do_reg_n_0_[12] ; wire \reg_do_reg_n_0_[13] ; wire \reg_do_reg_n_0_[14] ; wire \reg_do_reg_n_0_[15] ; wire \reg_do_reg_n_0_[1] ; wire \reg_do_reg_n_0_[2] ; wire \reg_do_reg_n_0_[3] ; wire \reg_do_reg_n_0_[4] ; wire \reg_do_reg_n_0_[5] ; wire \reg_do_reg_n_0_[6] ; wire \reg_do_reg_n_0_[7] ; wire \reg_do_reg_n_0_[8] ; wire \reg_do_reg_n_0_[9] ; wire reg_drdy; wire reg_drdy0; wire [15:0]reg_test; wire reg_test0; wire [16:0]s_daddr_o; wire s_den_o; wire s_den_r0; wire [15:0]s_di_o; wire [15:0]s_do_i; wire s_drdy_i; wire s_dwe_o; wire [36:0]sl_iport_i; wire [16:0]sl_oport_o; assign s_dclk_o = sl_iport_i[1]; assign s_rst_o = sl_iport_i[0]; FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[4]), .Q(s_daddr_o[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[14]), .Q(s_daddr_o[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[15]), .Q(s_daddr_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[16]), .Q(s_daddr_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[17]), .Q(s_daddr_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[18]), .Q(s_daddr_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[19]), .Q(s_daddr_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[16] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[20]), .Q(s_daddr_o[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[5]), .Q(s_daddr_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[6]), .Q(s_daddr_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[7]), .Q(s_daddr_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[8]), .Q(s_daddr_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[9]), .Q(s_daddr_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[10]), .Q(s_daddr_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[11]), .Q(s_daddr_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[12]), .Q(s_daddr_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[13]), .Q(s_daddr_o[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h2AAAAAAA)) \G_1PIPE_IFACE.s_den_r_i_1 (.I0(sl_iport_i[2]), .I1(sl_iport_i[14]), .I2(sl_iport_i[13]), .I3(sl_iport_i[12]), .I4(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .O(s_den_r0)); LUT6 #( .INIT(64'h8000000000000000)) \G_1PIPE_IFACE.s_den_r_i_2 (.I0(sl_iport_i[15]), .I1(sl_iport_i[16]), .I2(sl_iport_i[17]), .I3(sl_iport_i[18]), .I4(sl_iport_i[20]), .I5(sl_iport_i[19]), .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_den_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(s_den_r0), .Q(s_den_o), .R(sl_iport_i[0])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[21]), .Q(s_di_o[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[31]), .Q(s_di_o[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[32]), .Q(s_di_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[33]), .Q(s_di_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[34]), .Q(s_di_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[35]), .Q(s_di_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[36]), .Q(s_di_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[22]), .Q(s_di_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[23]), .Q(s_di_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[24]), .Q(s_di_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[25]), .Q(s_di_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[26]), .Q(s_di_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[27]), .Q(s_di_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[28]), .Q(s_di_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[29]), .Q(s_di_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[30]), .Q(s_di_o[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[0]_i_1 (.I0(\reg_do_reg_n_0_[0] ), .I1(s_do_i[0]), .I2(reg_drdy), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[10]_i_1 (.I0(\reg_do_reg_n_0_[10] ), .I1(s_do_i[10]), .I2(reg_drdy), .O(p_0_in[10])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[11]_i_1 (.I0(\reg_do_reg_n_0_[11] ), .I1(s_do_i[11]), .I2(reg_drdy), .O(p_0_in[11])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[12]_i_1 (.I0(\reg_do_reg_n_0_[12] ), .I1(s_do_i[12]), .I2(reg_drdy), .O(p_0_in[12])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[13]_i_1 (.I0(\reg_do_reg_n_0_[13] ), .I1(s_do_i[13]), .I2(reg_drdy), .O(p_0_in[13])); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[14]_i_1 (.I0(\reg_do_reg_n_0_[14] ), .I1(s_do_i[14]), .I2(reg_drdy), .O(p_0_in[14])); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[15]_i_1 (.I0(\reg_do_reg_n_0_[15] ), .I1(s_do_i[15]), .I2(reg_drdy), .O(p_0_in[15])); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[1]_i_1 (.I0(\reg_do_reg_n_0_[1] ), .I1(s_do_i[1]), .I2(reg_drdy), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[2]_i_1 (.I0(\reg_do_reg_n_0_[2] ), .I1(s_do_i[2]), .I2(reg_drdy), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[3]_i_1 (.I0(\reg_do_reg_n_0_[3] ), .I1(s_do_i[3]), .I2(reg_drdy), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[4]_i_1 (.I0(\reg_do_reg_n_0_[4] ), .I1(s_do_i[4]), .I2(reg_drdy), .O(p_0_in[4])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[5]_i_1 (.I0(\reg_do_reg_n_0_[5] ), .I1(s_do_i[5]), .I2(reg_drdy), .O(p_0_in[5])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[6]_i_1 (.I0(\reg_do_reg_n_0_[6] ), .I1(s_do_i[6]), .I2(reg_drdy), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[7]_i_1 (.I0(\reg_do_reg_n_0_[7] ), .I1(s_do_i[7]), .I2(reg_drdy), .O(p_0_in[7])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[8]_i_1 (.I0(\reg_do_reg_n_0_[8] ), .I1(s_do_i[8]), .I2(reg_drdy), .O(p_0_in[8])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[9]_i_1 (.I0(\reg_do_reg_n_0_[9] ), .I1(s_do_i[9]), .I2(reg_drdy), .O(p_0_in[9])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[0]), .Q(sl_oport_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[10]), .Q(sl_oport_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[11]), .Q(sl_oport_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[12]), .Q(sl_oport_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[13]), .Q(sl_oport_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[14]), .Q(sl_oport_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[15]), .Q(sl_oport_o[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[1]), .Q(sl_oport_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[2]), .Q(sl_oport_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[3]), .Q(sl_oport_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[4]), .Q(sl_oport_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[5]), .Q(sl_oport_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[6]), .Q(sl_oport_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[7]), .Q(sl_oport_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[8]), .Q(sl_oport_o[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[9]), .Q(sl_oport_o[10]), .R(1'b0)); LUT2 #( .INIT(4'hE)) \G_1PIPE_IFACE.s_drdy_r_i_1 (.I0(s_drdy_i), .I1(reg_drdy), .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_drdy_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ), .Q(sl_oport_o[0]), .R(sl_iport_i[0])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_dwe_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[3]), .Q(s_dwe_o), .R(sl_iport_i[0])); LUT6 #( .INIT(64'hAAAAAAAAEAFFAAAA)) \reg_do[0]_i_1 (.I0(\reg_do[4]_i_2_n_0 ), .I1(reg_test[0]), .I2(sl_iport_i[5]), .I3(sl_iport_i[6]), .I4(sl_iport_i[8]), .I5(sl_iport_i[4]), .O(reg_do[0])); LUT5 #( .INIT(32'h20C0C000)) \reg_do[10]_i_1 (.I0(reg_test[10]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[10])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h00800000)) \reg_do[10]_i_2 (.I0(sl_iport_i[8]), .I1(sl_iport_i[10]), .I2(sl_iport_i[11]), .I3(sl_iport_i[7]), .I4(sl_iport_i[9]), .O(\reg_do[10]_i_2_n_0 )); LUT4 #( .INIT(16'hFF7F)) \reg_do[15]_i_1 (.I0(sl_iport_i[5]), .I1(sl_iport_i[6]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[4]), .O(\reg_do[15]_i_1_n_0 )); LUT5 #( .INIT(32'h20C000C0)) \reg_do[1]_i_1 (.I0(reg_test[1]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[1])); LUT5 #( .INIT(32'h0000D000)) \reg_do[2]_i_1 (.I0(sl_iport_i[5]), .I1(reg_test[2]), .I2(sl_iport_i[6]), .I3(\reg_do[10]_i_2_n_0 ), .I4(sl_iport_i[4]), .O(reg_do[2])); LUT6 #( .INIT(64'hAAEAAAAAAAAAAAFA)) \reg_do[4]_i_1 (.I0(\reg_do[4]_i_2_n_0 ), .I1(reg_test[4]), .I2(sl_iport_i[8]), .I3(sl_iport_i[4]), .I4(sl_iport_i[5]), .I5(sl_iport_i[6]), .O(reg_do[4])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'hBFFFFFFC)) \reg_do[4]_i_2 (.I0(sl_iport_i[7]), .I1(sl_iport_i[8]), .I2(sl_iport_i[11]), .I3(sl_iport_i[10]), .I4(sl_iport_i[9]), .O(\reg_do[4]_i_2_n_0 )); LUT5 #( .INIT(32'h2000C000)) \reg_do[5]_i_1 (.I0(reg_test[5]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[5])); LUT5 #( .INIT(32'h2000C000)) \reg_do[6]_i_1 (.I0(reg_test[6]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[6])); LUT5 #( .INIT(32'h2000C000)) \reg_do[7]_i_1 (.I0(reg_test[7]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[7])); LUT5 #( .INIT(32'h2F000000)) \reg_do[8]_i_1 (.I0(reg_test[8]), .I1(sl_iport_i[4]), .I2(sl_iport_i[5]), .I3(\reg_do[10]_i_2_n_0 ), .I4(sl_iport_i[6]), .O(reg_do[8])); LUT5 #( .INIT(32'h20C0C000)) \reg_do[9]_i_1 (.I0(reg_test[9]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[9])); FDRE #( .INIT(1'b0)) \reg_do_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[0]), .Q(\reg_do_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[10]), .Q(\reg_do_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[11]), .Q(\reg_do_reg_n_0_[11] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[12]), .Q(\reg_do_reg_n_0_[12] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[13]), .Q(\reg_do_reg_n_0_[13] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[14]), .Q(\reg_do_reg_n_0_[14] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[15]), .Q(\reg_do_reg_n_0_[15] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[1]), .Q(\reg_do_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[2]), .Q(\reg_do_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[3]), .Q(\reg_do_reg_n_0_[3] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[4]), .Q(\reg_do_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[5]), .Q(\reg_do_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[6]), .Q(\reg_do_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[7]), .Q(\reg_do_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[8]), .Q(\reg_do_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[9]), .Q(\reg_do_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h80000000)) reg_drdy_i_1 (.I0(sl_iport_i[14]), .I1(sl_iport_i[13]), .I2(sl_iport_i[12]), .I3(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .I4(sl_iport_i[2]), .O(reg_drdy0)); FDRE #( .INIT(1'b0)) reg_drdy_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_drdy0), .Q(reg_drdy), .R(sl_iport_i[0])); LUT6 #( .INIT(64'h8000000000000000)) \reg_test[15]_i_1 (.I0(sl_iport_i[3]), .I1(sl_iport_i[2]), .I2(sl_iport_i[14]), .I3(sl_iport_i[13]), .I4(sl_iport_i[12]), .I5(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .O(reg_test0)); FDRE #( .INIT(1'b0)) \reg_test_reg[0] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[21]), .Q(reg_test[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[10] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[31]), .Q(reg_test[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[11] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[32]), .Q(reg_test[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[12] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[33]), .Q(reg_test[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[13] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[34]), .Q(reg_test[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[14] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[35]), .Q(reg_test[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[15] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[36]), .Q(reg_test[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[1] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[22]), .Q(reg_test[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[2] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[23]), .Q(reg_test[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[3] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[24]), .Q(reg_test[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[4] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[25]), .Q(reg_test[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[5] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[26]), .Q(reg_test[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[6] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[27]), .Q(reg_test[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[7] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[28]), .Q(reg_test[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[8] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[29]), .Q(reg_test[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[9] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[30]), .Q(reg_test[9]), .R(1'b0)); endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs (s_rst_o, s_dclk_o, s_den_o, s_dwe_o, s_daddr_o, s_di_o, sl_oport_o, s_do_i, sl_iport_i, s_drdy_i);
output s_rst_o; output s_dclk_o; output s_den_o; output s_dwe_o; output [16:0]s_daddr_o; output [15:0]s_di_o; output [16:0]sl_oport_o; input [15:0]s_do_i; input [36:0]sl_iport_i; input s_drdy_i; wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ; wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ; wire [15:0]p_0_in; wire [10:0]reg_do; wire \reg_do[10]_i_2_n_0 ; wire \reg_do[15]_i_1_n_0 ; wire \reg_do[4]_i_2_n_0 ; wire \reg_do_reg_n_0_[0] ; wire \reg_do_reg_n_0_[10] ; wire \reg_do_reg_n_0_[11] ; wire \reg_do_reg_n_0_[12] ; wire \reg_do_reg_n_0_[13] ; wire \reg_do_reg_n_0_[14] ; wire \reg_do_reg_n_0_[15] ; wire \reg_do_reg_n_0_[1] ; wire \reg_do_reg_n_0_[2] ; wire \reg_do_reg_n_0_[3] ; wire \reg_do_reg_n_0_[4] ; wire \reg_do_reg_n_0_[5] ; wire \reg_do_reg_n_0_[6] ; wire \reg_do_reg_n_0_[7] ; wire \reg_do_reg_n_0_[8] ; wire \reg_do_reg_n_0_[9] ; wire reg_drdy; wire reg_drdy0; wire [15:0]reg_test; wire reg_test0; wire [16:0]s_daddr_o; wire s_den_o; wire s_den_r0; wire [15:0]s_di_o; wire [15:0]s_do_i; wire s_drdy_i; wire s_dwe_o; wire [36:0]sl_iport_i; wire [16:0]sl_oport_o; assign s_dclk_o = sl_iport_i[1]; assign s_rst_o = sl_iport_i[0]; FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[4]), .Q(s_daddr_o[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[14]), .Q(s_daddr_o[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[15]), .Q(s_daddr_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[16]), .Q(s_daddr_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[17]), .Q(s_daddr_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[18]), .Q(s_daddr_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[19]), .Q(s_daddr_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[16] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[20]), .Q(s_daddr_o[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[5]), .Q(s_daddr_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[6]), .Q(s_daddr_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[7]), .Q(s_daddr_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[8]), .Q(s_daddr_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[9]), .Q(s_daddr_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[10]), .Q(s_daddr_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[11]), .Q(s_daddr_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[12]), .Q(s_daddr_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_daddr_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[13]), .Q(s_daddr_o[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h2AAAAAAA)) \G_1PIPE_IFACE.s_den_r_i_1 (.I0(sl_iport_i[2]), .I1(sl_iport_i[14]), .I2(sl_iport_i[13]), .I3(sl_iport_i[12]), .I4(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .O(s_den_r0)); LUT6 #( .INIT(64'h8000000000000000)) \G_1PIPE_IFACE.s_den_r_i_2 (.I0(sl_iport_i[15]), .I1(sl_iport_i[16]), .I2(sl_iport_i[17]), .I3(sl_iport_i[18]), .I4(sl_iport_i[20]), .I5(sl_iport_i[19]), .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 )); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_den_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(s_den_r0), .Q(s_den_o), .R(sl_iport_i[0])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[21]), .Q(s_di_o[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[31]), .Q(s_di_o[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[32]), .Q(s_di_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[33]), .Q(s_di_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[34]), .Q(s_di_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[35]), .Q(s_di_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[36]), .Q(s_di_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[22]), .Q(s_di_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[23]), .Q(s_di_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[24]), .Q(s_di_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[25]), .Q(s_di_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[26]), .Q(s_di_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[27]), .Q(s_di_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[28]), .Q(s_di_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[29]), .Q(s_di_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_di_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[30]), .Q(s_di_o[9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[0]_i_1 (.I0(\reg_do_reg_n_0_[0] ), .I1(s_do_i[0]), .I2(reg_drdy), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[10]_i_1 (.I0(\reg_do_reg_n_0_[10] ), .I1(s_do_i[10]), .I2(reg_drdy), .O(p_0_in[10])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[11]_i_1 (.I0(\reg_do_reg_n_0_[11] ), .I1(s_do_i[11]), .I2(reg_drdy), .O(p_0_in[11])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[12]_i_1 (.I0(\reg_do_reg_n_0_[12] ), .I1(s_do_i[12]), .I2(reg_drdy), .O(p_0_in[12])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[13]_i_1 (.I0(\reg_do_reg_n_0_[13] ), .I1(s_do_i[13]), .I2(reg_drdy), .O(p_0_in[13])); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[14]_i_1 (.I0(\reg_do_reg_n_0_[14] ), .I1(s_do_i[14]), .I2(reg_drdy), .O(p_0_in[14])); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[15]_i_1 (.I0(\reg_do_reg_n_0_[15] ), .I1(s_do_i[15]), .I2(reg_drdy), .O(p_0_in[15])); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[1]_i_1 (.I0(\reg_do_reg_n_0_[1] ), .I1(s_do_i[1]), .I2(reg_drdy), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[2]_i_1 (.I0(\reg_do_reg_n_0_[2] ), .I1(s_do_i[2]), .I2(reg_drdy), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[3]_i_1 (.I0(\reg_do_reg_n_0_[3] ), .I1(s_do_i[3]), .I2(reg_drdy), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[4]_i_1 (.I0(\reg_do_reg_n_0_[4] ), .I1(s_do_i[4]), .I2(reg_drdy), .O(p_0_in[4])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[5]_i_1 (.I0(\reg_do_reg_n_0_[5] ), .I1(s_do_i[5]), .I2(reg_drdy), .O(p_0_in[5])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[6]_i_1 (.I0(\reg_do_reg_n_0_[6] ), .I1(s_do_i[6]), .I2(reg_drdy), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[7]_i_1 (.I0(\reg_do_reg_n_0_[7] ), .I1(s_do_i[7]), .I2(reg_drdy), .O(p_0_in[7])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[8]_i_1 (.I0(\reg_do_reg_n_0_[8] ), .I1(s_do_i[8]), .I2(reg_drdy), .O(p_0_in[8])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hAC)) \G_1PIPE_IFACE.s_do_r[9]_i_1 (.I0(\reg_do_reg_n_0_[9] ), .I1(s_do_i[9]), .I2(reg_drdy), .O(p_0_in[9])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[0]), .Q(sl_oport_o[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[10]), .Q(sl_oport_o[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[11]), .Q(sl_oport_o[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[12]), .Q(sl_oport_o[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[13]), .Q(sl_oport_o[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[14]), .Q(sl_oport_o[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[15]), .Q(sl_oport_o[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[1]), .Q(sl_oport_o[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[2]), .Q(sl_oport_o[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[3]), .Q(sl_oport_o[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[4]), .Q(sl_oport_o[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[5]), .Q(sl_oport_o[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[6]), .Q(sl_oport_o[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[7]), .Q(sl_oport_o[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[8]), .Q(sl_oport_o[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_do_r_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(p_0_in[9]), .Q(sl_oport_o[10]), .R(1'b0)); LUT2 #( .INIT(4'hE)) \G_1PIPE_IFACE.s_drdy_r_i_1 (.I0(s_drdy_i), .I1(reg_drdy), .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 )); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_drdy_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ), .Q(sl_oport_o[0]), .R(sl_iport_i[0])); FDRE #( .INIT(1'b0)) \G_1PIPE_IFACE.s_dwe_r_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(sl_iport_i[3]), .Q(s_dwe_o), .R(sl_iport_i[0])); LUT6 #( .INIT(64'hAAAAAAAAEAFFAAAA)) \reg_do[0]_i_1 (.I0(\reg_do[4]_i_2_n_0 ), .I1(reg_test[0]), .I2(sl_iport_i[5]), .I3(sl_iport_i[6]), .I4(sl_iport_i[8]), .I5(sl_iport_i[4]), .O(reg_do[0])); LUT5 #( .INIT(32'h20C0C000)) \reg_do[10]_i_1 (.I0(reg_test[10]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[10])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h00800000)) \reg_do[10]_i_2 (.I0(sl_iport_i[8]), .I1(sl_iport_i[10]), .I2(sl_iport_i[11]), .I3(sl_iport_i[7]), .I4(sl_iport_i[9]), .O(\reg_do[10]_i_2_n_0 )); LUT4 #( .INIT(16'hFF7F)) \reg_do[15]_i_1 (.I0(sl_iport_i[5]), .I1(sl_iport_i[6]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[4]), .O(\reg_do[15]_i_1_n_0 )); LUT5 #( .INIT(32'h20C000C0)) \reg_do[1]_i_1 (.I0(reg_test[1]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[1])); LUT5 #( .INIT(32'h0000D000)) \reg_do[2]_i_1 (.I0(sl_iport_i[5]), .I1(reg_test[2]), .I2(sl_iport_i[6]), .I3(\reg_do[10]_i_2_n_0 ), .I4(sl_iport_i[4]), .O(reg_do[2])); LUT6 #( .INIT(64'hAAEAAAAAAAAAAAFA)) \reg_do[4]_i_1 (.I0(\reg_do[4]_i_2_n_0 ), .I1(reg_test[4]), .I2(sl_iport_i[8]), .I3(sl_iport_i[4]), .I4(sl_iport_i[5]), .I5(sl_iport_i[6]), .O(reg_do[4])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'hBFFFFFFC)) \reg_do[4]_i_2 (.I0(sl_iport_i[7]), .I1(sl_iport_i[8]), .I2(sl_iport_i[11]), .I3(sl_iport_i[10]), .I4(sl_iport_i[9]), .O(\reg_do[4]_i_2_n_0 )); LUT5 #( .INIT(32'h2000C000)) \reg_do[5]_i_1 (.I0(reg_test[5]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[5])); LUT5 #( .INIT(32'h2000C000)) \reg_do[6]_i_1 (.I0(reg_test[6]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[6])); LUT5 #( .INIT(32'h2000C000)) \reg_do[7]_i_1 (.I0(reg_test[7]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[7])); LUT5 #( .INIT(32'h2F000000)) \reg_do[8]_i_1 (.I0(reg_test[8]), .I1(sl_iport_i[4]), .I2(sl_iport_i[5]), .I3(\reg_do[10]_i_2_n_0 ), .I4(sl_iport_i[6]), .O(reg_do[8])); LUT5 #( .INIT(32'h20C0C000)) \reg_do[9]_i_1 (.I0(reg_test[9]), .I1(sl_iport_i[4]), .I2(\reg_do[10]_i_2_n_0 ), .I3(sl_iport_i[6]), .I4(sl_iport_i[5]), .O(reg_do[9])); FDRE #( .INIT(1'b0)) \reg_do_reg[0] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[0]), .Q(\reg_do_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[10] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[10]), .Q(\reg_do_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[11] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[11]), .Q(\reg_do_reg_n_0_[11] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[12] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[12]), .Q(\reg_do_reg_n_0_[12] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[13] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[13]), .Q(\reg_do_reg_n_0_[13] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[14] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[14]), .Q(\reg_do_reg_n_0_[14] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[15] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[15]), .Q(\reg_do_reg_n_0_[15] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[1] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[1]), .Q(\reg_do_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[2] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[2]), .Q(\reg_do_reg_n_0_[2] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[3] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_test[3]), .Q(\reg_do_reg_n_0_[3] ), .R(\reg_do[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \reg_do_reg[4] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[4]), .Q(\reg_do_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[5] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[5]), .Q(\reg_do_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[6] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[6]), .Q(\reg_do_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[7] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[7]), .Q(\reg_do_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[8] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[8]), .Q(\reg_do_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_do_reg[9] (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_do[9]), .Q(\reg_do_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h80000000)) reg_drdy_i_1 (.I0(sl_iport_i[14]), .I1(sl_iport_i[13]), .I2(sl_iport_i[12]), .I3(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .I4(sl_iport_i[2]), .O(reg_drdy0)); FDRE #( .INIT(1'b0)) reg_drdy_reg (.C(sl_iport_i[1]), .CE(1'b1), .D(reg_drdy0), .Q(reg_drdy), .R(sl_iport_i[0])); LUT6 #( .INIT(64'h8000000000000000)) \reg_test[15]_i_1 (.I0(sl_iport_i[3]), .I1(sl_iport_i[2]), .I2(sl_iport_i[14]), .I3(sl_iport_i[13]), .I4(sl_iport_i[12]), .I5(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ), .O(reg_test0)); FDRE #( .INIT(1'b0)) \reg_test_reg[0] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[21]), .Q(reg_test[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[10] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[31]), .Q(reg_test[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[11] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[32]), .Q(reg_test[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[12] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[33]), .Q(reg_test[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[13] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[34]), .Q(reg_test[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[14] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[35]), .Q(reg_test[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[15] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[36]), .Q(reg_test[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[1] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[22]), .Q(reg_test[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[2] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[23]), .Q(reg_test[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[3] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[24]), .Q(reg_test[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[4] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[25]), .Q(reg_test[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[5] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[26]), .Q(reg_test[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[6] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[27]), .Q(reg_test[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[7] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[28]), .Q(reg_test[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[8] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[29]), .Q(reg_test[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \reg_test_reg[9] (.C(sl_iport_i[1]), .CE(reg_test0), .D(sl_iport_i[30]), .Q(reg_test[9]), .R(1'b0)); endmodule
8
2,490
data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
107,660,616
DemoSDRAM_system_ila_0_0_sim_netlist.v
v
113,308
21,627
[]
[]
['all rights reserved']
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1,831
module
module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule
module glbl ();
parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule
8
2,493
data/full_repos/permissive/401869901/src/main/scala/resources/verilog/VTAMemDPI.v
401,869,901
VTAMemDPI.v
v
112
64
[]
[]
[]
null
line:41: before: ""DPI-C""
data/verilator_xmls/e1910f6e-3d65-426a-851f-637771283f47.xml
null
191,655
module
module VTAMemDPI # ( parameter LEN_BITS = 8, parameter ADDR_BITS = 64, parameter DATA_BITS = `DATA_LEN_MEM ) ( input clock, input reset, input dpi_req_valid, input dpi_req_opcode, input [LEN_BITS-1:0] dpi_req_len, input [ADDR_BITS-1:0] dpi_req_addr, input dpi_wr_valid, input [DATA_BITS-1:0] dpi_wr_bits, output logic dpi_rd_valid, output logic [DATA_BITS-1:0] dpi_rd_bits, input dpi_rd_ready ); import "DPI-C" function void VTAMemDPI ( input byte unsigned req_valid, input byte unsigned req_opcode, input byte unsigned req_len, input longint unsigned req_addr, input byte unsigned wr_valid, input logic [DATA_BITS - 1 : 0] wr_value, output byte unsigned rd_valid, output logic [DATA_BITS - 1 : 0] rd_value, input byte unsigned rd_ready ); typedef logic dpi1_t; typedef logic [7:0] dpi8_t; typedef logic [31:0] dpi32_t; typedef logic [63:0] dpi64_t; typedef logic [ADDR_BITS - 1:0] dpiAddr_t; typedef logic [DATA_BITS - 1:0] dpiMem_t; dpi1_t __reset; dpi8_t __req_valid; dpi8_t __req_opcode; dpi8_t __req_len; dpiAddr_t __req_addr; dpi8_t __wr_valid; dpiMem_t __wr_value; dpi8_t __rd_valid; dpiMem_t __rd_value; dpi8_t __rd_ready; always_ff @(posedge clock) begin __reset <= reset; end always_ff @(posedge clock) begin dpi_rd_valid <= dpi1_t ' (__rd_valid); dpi_rd_bits <= __rd_value; end assign __req_valid = dpi8_t ' (dpi_req_valid); assign __req_opcode = dpi8_t ' (dpi_req_opcode); assign __req_len = dpi_req_len; assign __req_addr = dpi_req_addr; assign __wr_valid = dpi8_t ' (dpi_wr_valid); assign __wr_value = dpi_wr_bits; assign __rd_ready = dpi8_t ' (dpi_rd_ready); always_ff @(posedge clock) begin if (reset | __reset) begin __rd_valid = 0; __rd_value = 0; end else begin VTAMemDPI( __req_valid, __req_opcode, __req_len, __req_addr, __wr_valid, __wr_value, __rd_valid, __rd_value, __rd_ready); end end endmodule
module VTAMemDPI # ( parameter LEN_BITS = 8, parameter ADDR_BITS = 64, parameter DATA_BITS = `DATA_LEN_MEM ) ( input clock, input reset, input dpi_req_valid, input dpi_req_opcode, input [LEN_BITS-1:0] dpi_req_len, input [ADDR_BITS-1:0] dpi_req_addr, input dpi_wr_valid, input [DATA_BITS-1:0] dpi_wr_bits, output logic dpi_rd_valid, output logic [DATA_BITS-1:0] dpi_rd_bits, input dpi_rd_ready );
import "DPI-C" function void VTAMemDPI ( input byte unsigned req_valid, input byte unsigned req_opcode, input byte unsigned req_len, input longint unsigned req_addr, input byte unsigned wr_valid, input logic [DATA_BITS - 1 : 0] wr_value, output byte unsigned rd_valid, output logic [DATA_BITS - 1 : 0] rd_value, input byte unsigned rd_ready ); typedef logic dpi1_t; typedef logic [7:0] dpi8_t; typedef logic [31:0] dpi32_t; typedef logic [63:0] dpi64_t; typedef logic [ADDR_BITS - 1:0] dpiAddr_t; typedef logic [DATA_BITS - 1:0] dpiMem_t; dpi1_t __reset; dpi8_t __req_valid; dpi8_t __req_opcode; dpi8_t __req_len; dpiAddr_t __req_addr; dpi8_t __wr_valid; dpiMem_t __wr_value; dpi8_t __rd_valid; dpiMem_t __rd_value; dpi8_t __rd_ready; always_ff @(posedge clock) begin __reset <= reset; end always_ff @(posedge clock) begin dpi_rd_valid <= dpi1_t ' (__rd_valid); dpi_rd_bits <= __rd_value; end assign __req_valid = dpi8_t ' (dpi_req_valid); assign __req_opcode = dpi8_t ' (dpi_req_opcode); assign __req_len = dpi_req_len; assign __req_addr = dpi_req_addr; assign __wr_valid = dpi8_t ' (dpi_wr_valid); assign __wr_value = dpi_wr_bits; assign __rd_ready = dpi8_t ' (dpi_rd_ready); always_ff @(posedge clock) begin if (reset | __reset) begin __rd_valid = 0; __rd_value = 0; end else begin VTAMemDPI( __req_valid, __req_opcode, __req_len, __req_addr, __wr_valid, __wr_value, __rd_valid, __rd_value, __rd_ready); end end endmodule
1
2,494
data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v
23,713,597
vc-TestRandDelayMem_1port.t.v
v
365
130
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[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:5: Cannot find include file: vc-TestRandDelaySource.v\n`include "vc-TestRandDelaySource.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.v\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.sv\n vc-TestRandDelaySource.v\n vc-TestRandDelaySource.v.v\n vc-TestRandDelaySource.v.sv\n obj_dir/vc-TestRandDelaySource.v\n obj_dir/vc-TestRandDelaySource.v.v\n obj_dir/vc-TestRandDelaySource.v.sv\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:6: Cannot find include file: vc-TestRandDelaySink.v\n`include "vc-TestRandDelaySink.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:7: Cannot find include file: vc-TestRandDelayMem_1port.v\n`include "vc-TestRandDelayMem_1port.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:8: Cannot find include file: vc-test.v\n`include "vc-test.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:9: Cannot find include file: vc-trace.v\n`include "vc-trace.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: syntax error, unexpected \',\'\n localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: syntax error, unexpected \',\'\n localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:107: Define or directive not defined: \'`VC_TRACE_BEGIN\'\n `VC_TRACE_BEGIN\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:108: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:111: syntax error, unexpected \'(\', expecting IDENTIFIER\n vc_trace.append_str( trace_str, " > " );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:113: syntax error, unexpected \'(\', expecting IDENTIFIER\n mem.trace( trace_str );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:115: syntax error, unexpected \'(\', expecting IDENTIFIER\n vc_trace.append_str( trace_str, " > " );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:116: syntax error, unexpected \'(\', expecting IDENTIFIER\n sink.trace( trace_str );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:119: Define or directive not defined: \'`VC_TRACE_END\'\n `VC_TRACE_END\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:128: Define or directive not defined: \'`VC_TEST_SUITE_BEGIN\'\n `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: syntax error, unexpected \',\'\n reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: syntax error, unexpected \',\'\n reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_NBITS\'\n input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: syntax error, unexpected \',\'\n input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type,\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:177: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_NBITS\'\n input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:178: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_NBITS\'\n input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0] memreq_addr,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:179: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_NBITS\'\n input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0] memreq_len,\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:180: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_NBITS\'\n input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0] memreq_data,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:182: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_NBITS\'\n input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0] memresp_type,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:183: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_NBITS\'\n input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0] memresp_opaque,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:184: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_NBITS\'\n input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0] memresp_len,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:185: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_NBITS\'\n input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0] memresp_data\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:188: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)] = memreq_type;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:189: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:190: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)] = memreq_addr;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:191: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)] = memreq_len;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:192: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)] = memreq_data;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:194: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)] = memresp_type;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:195: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)] = memresp_opaque;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:196: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)] = memresp_len;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:197: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)] = memresp_data;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:199: syntax error, unexpected \'.\', expecting IDENTIFIER\n th.src.src.m[index] = th_port_memreq;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:200: syntax error, unexpected \'.\', expecting IDENTIFIER\n th.sink.sink.m[index] = th_port_memresp;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:206: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_READ\'\n localparam c_req_rd = `VC_MEM_REQ_MSG_TYPE_READ;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE\'\n localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE_INIT\'\n localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_ADD\'\n localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:210: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_AND\'\n localparam c_req_an = `VC_MEM_REQ_MSG_TYPE_AMO_AND;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
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module
module TestHarness ( input clk, input reset, input mem_clear, input [31:0] src_max_delay, input [31:0] mem_max_delay, input [31:0] sink_max_delay, output done ); localparam c_mem_nbytes = 1024; localparam c_opaque_nbits = 8; localparam c_addr_nbits = 16; localparam c_data_nbits = 32; localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits); localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits); wire src_val; wire src_rdy; wire [c_req_nbits-1:0] src_msg; wire src_done; vc_TestRandDelaySource#(c_req_nbits) src ( .clk (clk), .reset (reset), .max_delay (src_max_delay), .val (src_val), .rdy (src_rdy), .msg (src_msg), .done (src_done) ); wire sink_val; wire sink_rdy; wire [c_resp_nbits-1:0] sink_msg; vc_TestRandDelayMem_1port #( .p_mem_nbytes (c_mem_nbytes), .p_opaque_nbits (c_opaque_nbits), .p_addr_nbits (c_addr_nbits), .p_data_nbits (c_data_nbits) ) mem ( .clk (clk), .reset (reset), .mem_clear (mem_clear), .max_delay (mem_max_delay), .memreq_val (src_val), .memreq_rdy (src_rdy), .memreq_msg (src_msg), .memresp_val (sink_val), .memresp_rdy (sink_rdy), .memresp_msg (sink_msg) ); wire sink_done; vc_TestRandDelaySink#(c_resp_nbits) sink ( .clk (clk), .reset (reset), .max_delay (sink_max_delay), .val (sink_val), .rdy (sink_rdy), .msg (sink_msg), .done (sink_done) ); assign done = src_done & sink_done; `VC_TRACE_BEGIN begin src.trace( trace_str ); vc_trace.append_str( trace_str, " > " ); mem.trace( trace_str ); vc_trace.append_str( trace_str, " > " ); sink.trace( trace_str ); end `VC_TRACE_END endmodule
module TestHarness ( input clk, input reset, input mem_clear, input [31:0] src_max_delay, input [31:0] mem_max_delay, input [31:0] sink_max_delay, output done );
localparam c_mem_nbytes = 1024; localparam c_opaque_nbits = 8; localparam c_addr_nbits = 16; localparam c_data_nbits = 32; localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits); localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits); wire src_val; wire src_rdy; wire [c_req_nbits-1:0] src_msg; wire src_done; vc_TestRandDelaySource#(c_req_nbits) src ( .clk (clk), .reset (reset), .max_delay (src_max_delay), .val (src_val), .rdy (src_rdy), .msg (src_msg), .done (src_done) ); wire sink_val; wire sink_rdy; wire [c_resp_nbits-1:0] sink_msg; vc_TestRandDelayMem_1port #( .p_mem_nbytes (c_mem_nbytes), .p_opaque_nbits (c_opaque_nbits), .p_addr_nbits (c_addr_nbits), .p_data_nbits (c_data_nbits) ) mem ( .clk (clk), .reset (reset), .mem_clear (mem_clear), .max_delay (mem_max_delay), .memreq_val (src_val), .memreq_rdy (src_rdy), .memreq_msg (src_msg), .memresp_val (sink_val), .memresp_rdy (sink_rdy), .memresp_msg (sink_msg) ); wire sink_done; vc_TestRandDelaySink#(c_resp_nbits) sink ( .clk (clk), .reset (reset), .max_delay (sink_max_delay), .val (sink_val), .rdy (sink_rdy), .msg (sink_msg), .done (sink_done) ); assign done = src_done & sink_done; `VC_TRACE_BEGIN begin src.trace( trace_str ); vc_trace.append_str( trace_str, " > " ); mem.trace( trace_str ); vc_trace.append_str( trace_str, " > " ); sink.trace( trace_str ); end `VC_TRACE_END endmodule
2
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data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v
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[Errno 2] No such file or directory: 'preprocess.output'
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1: b'%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:5: Cannot find include file: vc-TestRandDelaySource.v\n`include "vc-TestRandDelaySource.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.v\n data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.sv\n vc-TestRandDelaySource.v\n vc-TestRandDelaySource.v.v\n vc-TestRandDelaySource.v.sv\n obj_dir/vc-TestRandDelaySource.v\n obj_dir/vc-TestRandDelaySource.v.v\n obj_dir/vc-TestRandDelaySource.v.sv\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:6: Cannot find include file: vc-TestRandDelaySink.v\n`include "vc-TestRandDelaySink.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:7: Cannot find include file: vc-TestRandDelayMem_1port.v\n`include "vc-TestRandDelayMem_1port.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:8: Cannot find include file: vc-test.v\n`include "vc-test.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:9: Cannot find include file: vc-trace.v\n`include "vc-trace.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: syntax error, unexpected \',\'\n localparam c_req_nbits = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: syntax error, unexpected \',\'\n localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:107: Define or directive not defined: \'`VC_TRACE_BEGIN\'\n `VC_TRACE_BEGIN\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:108: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:111: syntax error, unexpected \'(\', expecting IDENTIFIER\n vc_trace.append_str( trace_str, " > " );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:113: syntax error, unexpected \'(\', expecting IDENTIFIER\n mem.trace( trace_str );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:115: syntax error, unexpected \'(\', expecting IDENTIFIER\n vc_trace.append_str( trace_str, " > " );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:116: syntax error, unexpected \'(\', expecting IDENTIFIER\n sink.trace( trace_str );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:119: Define or directive not defined: \'`VC_TRACE_END\'\n `VC_TRACE_END\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:128: Define or directive not defined: \'`VC_TEST_SUITE_BEGIN\'\n `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: syntax error, unexpected \',\'\n reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: syntax error, unexpected \',\'\n reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_NBITS\'\n input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: syntax error, unexpected \',\'\n input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type,\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:177: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_NBITS\'\n input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:178: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_NBITS\'\n input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0] memreq_addr,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:179: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_NBITS\'\n input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0] memreq_len,\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:180: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_NBITS\'\n input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0] memreq_data,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:182: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_NBITS\'\n input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0] memresp_type,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:183: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_NBITS\'\n input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0] memresp_opaque,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:184: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_NBITS\'\n input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0] memresp_len,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:185: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_NBITS\'\n input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0] memresp_data\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:188: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)] = memreq_type;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:189: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:190: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)] = memreq_addr;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:191: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)] = memreq_len;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:192: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_FIELD\'\n th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)] = memreq_data;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:194: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)] = memresp_type;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:195: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)] = memresp_opaque;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:196: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)] = memresp_len;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:197: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_FIELD\'\n th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)] = memresp_data;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:199: syntax error, unexpected \'.\', expecting IDENTIFIER\n th.src.src.m[index] = th_port_memreq;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:200: syntax error, unexpected \'.\', expecting IDENTIFIER\n th.sink.sink.m[index] = th_port_memresp;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:206: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_READ\'\n localparam c_req_rd = `VC_MEM_REQ_MSG_TYPE_READ;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE\'\n localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE_INIT\'\n localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_ADD\'\n localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:210: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_AND\'\n localparam c_req_an = `VC_MEM_REQ_MSG_TYPE_AMO_AND;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
89,250
module
module top; `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" ) reg th_reset = 1; reg th_mem_clear; reg [31:0] th_src_max_delay; reg [31:0] th_mem_max_delay; reg [31:0] th_sink_max_delay; wire th_done; TestHarness th ( .clk (clk), .reset (th_reset), .mem_clear (th_mem_clear), .src_max_delay (th_src_max_delay), .mem_max_delay (th_mem_max_delay), .sink_max_delay (th_sink_max_delay), .done (th_done) ); task init_rand_delays ( input [31:0] src_max_delay, input [31:0] mem_max_delay, input [31:0] sink_max_delay ); begin th_src_max_delay = src_max_delay; th_mem_max_delay = mem_max_delay; th_sink_max_delay = sink_max_delay; end endtask reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq; reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp; task init_port ( input [1023:0] index, input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type, input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque, input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0] memreq_addr, input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0] memreq_len, input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0] memreq_data, input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0] memresp_type, input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0] memresp_opaque, input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0] memresp_len, input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0] memresp_data ); begin th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)] = memreq_type; th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque; th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)] = memreq_addr; th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)] = memreq_len; th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)] = memreq_data; th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)] = memresp_type; th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)] = memresp_opaque; th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)] = memresp_len; th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)] = memresp_data; th.src.src.m[index] = th_port_memreq; th.sink.sink.m[index] = th_port_memresp; end endtask localparam c_req_rd = `VC_MEM_REQ_MSG_TYPE_READ; localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE; localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT; localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD; localparam c_req_an = `VC_MEM_REQ_MSG_TYPE_AMO_AND; localparam c_req_ao = `VC_MEM_REQ_MSG_TYPE_AMO_OR; localparam c_resp_rd = `VC_MEM_RESP_MSG_TYPE_READ; localparam c_resp_wr = `VC_MEM_RESP_MSG_TYPE_WRITE; localparam c_resp_wn = `VC_MEM_RESP_MSG_TYPE_WRITE_INIT; localparam c_resp_ad = `VC_MEM_RESP_MSG_TYPE_AMO_ADD; localparam c_resp_an = `VC_MEM_RESP_MSG_TYPE_AMO_AND; localparam c_resp_ao = `VC_MEM_RESP_MSG_TYPE_AMO_OR; task init_common; begin #5; th_mem_clear = 1'b1; #20; th_mem_clear = 1'b0; init_port( 0, c_req_wr, 8'h00, 16'h0000, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h00, 2'd0, 32'h???????? ); init_port( 1, c_req_wn, 8'h01, 16'h0004, 2'd0, 32'h0e0f0102, c_resp_wn, 8'h01, 2'd0, 32'h???????? ); init_port( 2, c_req_rd, 8'h02, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h02, 2'd0, 32'h0a0b0c0d ); init_port( 3, c_req_rd, 8'h03, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'h0e0f0102 ); init_port( 4, c_req_wr, 8'h04, 16'h0008, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h04, 2'd0, 32'h???????? ); init_port( 5, c_req_wr, 8'h05, 16'h0008, 2'd1, 32'hdeadbeef, c_resp_wr, 8'h05, 2'd1, 32'h???????? ); init_port( 6, c_req_rd, 8'h06, 16'h0008, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h06, 2'd1, 32'h??????ef ); init_port( 7, c_req_rd, 8'h07, 16'h0009, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd1, 32'h??????0c ); init_port( 8, c_req_rd, 8'h08, 16'h000a, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h08, 2'd1, 32'h??????0b ); init_port( 9, c_req_rd, 8'h09, 16'h000b, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h09, 2'd1, 32'h??????0a ); init_port(10, c_req_wr, 8'h0a, 16'h000c, 2'd0, 32'h01020304, c_resp_wr, 8'h0a, 2'd0, 32'h???????? ); init_port(11, c_req_wr, 8'h0b, 16'h000c, 2'd2, 32'hdeadbeef, c_resp_wr, 8'h0b, 2'd2, 32'h???????? ); init_port(12, c_req_rd, 8'h0c, 16'h000c, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0c, 2'd2, 32'h????beef ); init_port(13, c_req_rd, 8'h0d, 16'h000e, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0d, 2'd2, 32'h????0102 ); init_port(14, c_req_wr, 8'h0e, 16'h0014, 2'd0, 32'ha0b0c0d0, c_resp_wr, 8'h0e, 2'd0, 32'h???????? ); init_port(15, c_req_wr, 8'h0f, 16'h1014, 2'd0, 32'he0102030, c_resp_wr, 8'h0f, 2'd0, 32'h???????? ); init_port(16, c_req_rd, 8'h00, 16'h0014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h00, 2'd0, 32'he0102030 ); init_port(17, c_req_rd, 8'h01, 16'h1014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h01, 2'd0, 32'he0102030 ); init_port(18, c_req_ao, 8'h02, 16'h0000, 2'd0, 32'hf0f0f0f0, c_resp_ao, 8'h02, 2'd0, 32'h0a0b0c0d ); init_port(19, c_req_rd, 8'h03, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'hfafbfcfd ); init_port(20, c_req_ad, 8'h04, 16'h0004, 2'd0, 32'h00000fff, c_resp_ad, 8'h04, 2'd0, 32'h0e0f0102 ); init_port(21, c_req_rd, 8'h05, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h05, 2'd0, 32'h0e0f1101 ); init_port(22, c_req_an, 8'h06, 16'h0000, 2'd0, 32'h33333333, c_resp_an, 8'h06, 2'd0, 32'hfafbfcfd ); init_port(23, c_req_rd, 8'h07, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd0, 32'h32333031 ); end endtask task run_test; begin #5; th_reset = 1'b1; #20; th_reset = 1'b0; while ( !th_done && (th.vc_trace.cycles < 500) ) begin th.display_trace(); #10; end `VC_TEST_NET( th_done, 1'b1 ); end endtask `VC_TEST_CASE_BEGIN( 1, "src delay = 0, mem delay = 0, sink delay = 0" ) begin init_rand_delays( 0, 0, 0 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 2, "src delay = 3, mem delay = 0, sink delay = 10" ) begin init_rand_delays( 3, 0, 10 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 3, "src delay = 10, mem delay = 0, sink delay = 3" ) begin init_rand_delays( 10, 0, 3 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 4, "src delay = 0, mem delay = 5, sink delay = 0" ) begin init_rand_delays( 0, 5, 0 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 5, "src delay = 3, mem delay = 5, sink delay = 10" ) begin init_rand_delays( 3, 5, 10 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 6, "src delay = 10, mem delay = 5, sink delay = 3" ) begin init_rand_delays( 10, 5, 3 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_SUITE_END endmodule
module top;
`VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" ) reg th_reset = 1; reg th_mem_clear; reg [31:0] th_src_max_delay; reg [31:0] th_mem_max_delay; reg [31:0] th_sink_max_delay; wire th_done; TestHarness th ( .clk (clk), .reset (th_reset), .mem_clear (th_mem_clear), .src_max_delay (th_src_max_delay), .mem_max_delay (th_mem_max_delay), .sink_max_delay (th_sink_max_delay), .done (th_done) ); task init_rand_delays ( input [31:0] src_max_delay, input [31:0] mem_max_delay, input [31:0] sink_max_delay ); begin th_src_max_delay = src_max_delay; th_mem_max_delay = mem_max_delay; th_sink_max_delay = sink_max_delay; end endtask reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq; reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0] th_port_memresp; task init_port ( input [1023:0] index, input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0] memreq_type, input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque, input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0] memreq_addr, input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0] memreq_len, input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0] memreq_data, input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0] memresp_type, input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0] memresp_opaque, input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0] memresp_len, input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0] memresp_data ); begin th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)] = memreq_type; th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque; th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)] = memreq_addr; th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)] = memreq_len; th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)] = memreq_data; th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)] = memresp_type; th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)] = memresp_opaque; th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)] = memresp_len; th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)] = memresp_data; th.src.src.m[index] = th_port_memreq; th.sink.sink.m[index] = th_port_memresp; end endtask localparam c_req_rd = `VC_MEM_REQ_MSG_TYPE_READ; localparam c_req_wr = `VC_MEM_REQ_MSG_TYPE_WRITE; localparam c_req_wn = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT; localparam c_req_ad = `VC_MEM_REQ_MSG_TYPE_AMO_ADD; localparam c_req_an = `VC_MEM_REQ_MSG_TYPE_AMO_AND; localparam c_req_ao = `VC_MEM_REQ_MSG_TYPE_AMO_OR; localparam c_resp_rd = `VC_MEM_RESP_MSG_TYPE_READ; localparam c_resp_wr = `VC_MEM_RESP_MSG_TYPE_WRITE; localparam c_resp_wn = `VC_MEM_RESP_MSG_TYPE_WRITE_INIT; localparam c_resp_ad = `VC_MEM_RESP_MSG_TYPE_AMO_ADD; localparam c_resp_an = `VC_MEM_RESP_MSG_TYPE_AMO_AND; localparam c_resp_ao = `VC_MEM_RESP_MSG_TYPE_AMO_OR; task init_common; begin #5; th_mem_clear = 1'b1; #20; th_mem_clear = 1'b0; init_port( 0, c_req_wr, 8'h00, 16'h0000, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h00, 2'd0, 32'h???????? ); init_port( 1, c_req_wn, 8'h01, 16'h0004, 2'd0, 32'h0e0f0102, c_resp_wn, 8'h01, 2'd0, 32'h???????? ); init_port( 2, c_req_rd, 8'h02, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h02, 2'd0, 32'h0a0b0c0d ); init_port( 3, c_req_rd, 8'h03, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'h0e0f0102 ); init_port( 4, c_req_wr, 8'h04, 16'h0008, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h04, 2'd0, 32'h???????? ); init_port( 5, c_req_wr, 8'h05, 16'h0008, 2'd1, 32'hdeadbeef, c_resp_wr, 8'h05, 2'd1, 32'h???????? ); init_port( 6, c_req_rd, 8'h06, 16'h0008, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h06, 2'd1, 32'h??????ef ); init_port( 7, c_req_rd, 8'h07, 16'h0009, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd1, 32'h??????0c ); init_port( 8, c_req_rd, 8'h08, 16'h000a, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h08, 2'd1, 32'h??????0b ); init_port( 9, c_req_rd, 8'h09, 16'h000b, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h09, 2'd1, 32'h??????0a ); init_port(10, c_req_wr, 8'h0a, 16'h000c, 2'd0, 32'h01020304, c_resp_wr, 8'h0a, 2'd0, 32'h???????? ); init_port(11, c_req_wr, 8'h0b, 16'h000c, 2'd2, 32'hdeadbeef, c_resp_wr, 8'h0b, 2'd2, 32'h???????? ); init_port(12, c_req_rd, 8'h0c, 16'h000c, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0c, 2'd2, 32'h????beef ); init_port(13, c_req_rd, 8'h0d, 16'h000e, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0d, 2'd2, 32'h????0102 ); init_port(14, c_req_wr, 8'h0e, 16'h0014, 2'd0, 32'ha0b0c0d0, c_resp_wr, 8'h0e, 2'd0, 32'h???????? ); init_port(15, c_req_wr, 8'h0f, 16'h1014, 2'd0, 32'he0102030, c_resp_wr, 8'h0f, 2'd0, 32'h???????? ); init_port(16, c_req_rd, 8'h00, 16'h0014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h00, 2'd0, 32'he0102030 ); init_port(17, c_req_rd, 8'h01, 16'h1014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h01, 2'd0, 32'he0102030 ); init_port(18, c_req_ao, 8'h02, 16'h0000, 2'd0, 32'hf0f0f0f0, c_resp_ao, 8'h02, 2'd0, 32'h0a0b0c0d ); init_port(19, c_req_rd, 8'h03, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'hfafbfcfd ); init_port(20, c_req_ad, 8'h04, 16'h0004, 2'd0, 32'h00000fff, c_resp_ad, 8'h04, 2'd0, 32'h0e0f0102 ); init_port(21, c_req_rd, 8'h05, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h05, 2'd0, 32'h0e0f1101 ); init_port(22, c_req_an, 8'h06, 16'h0000, 2'd0, 32'h33333333, c_resp_an, 8'h06, 2'd0, 32'hfafbfcfd ); init_port(23, c_req_rd, 8'h07, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd0, 32'h32333031 ); end endtask task run_test; begin #5; th_reset = 1'b1; #20; th_reset = 1'b0; while ( !th_done && (th.vc_trace.cycles < 500) ) begin th.display_trace(); #10; end `VC_TEST_NET( th_done, 1'b1 ); end endtask `VC_TEST_CASE_BEGIN( 1, "src delay = 0, mem delay = 0, sink delay = 0" ) begin init_rand_delays( 0, 0, 0 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 2, "src delay = 3, mem delay = 0, sink delay = 10" ) begin init_rand_delays( 3, 0, 10 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 3, "src delay = 10, mem delay = 0, sink delay = 3" ) begin init_rand_delays( 10, 0, 3 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 4, "src delay = 0, mem delay = 5, sink delay = 0" ) begin init_rand_delays( 0, 5, 0 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 5, "src delay = 3, mem delay = 5, sink delay = 10" ) begin init_rand_delays( 3, 5, 10 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_CASE_BEGIN( 6, "src delay = 10, mem delay = 5, sink delay = 3" ) begin init_rand_delays( 10, 5, 3 ); init_common; run_test; end `VC_TEST_CASE_END `VC_TEST_SUITE_END endmodule
2
2,496
data/full_repos/permissive/466009483/HDL/PROJECT_FILES/decoder.v
466,009,483
decoder.v
v
40
83
[]
[]
[]
[(23, 39)]
null
data/verilator_xmls/8754289b-ed7a-4fc0-a34a-bc36ebb7c81a.xml
null
233,691
module
module decoder#(parameter DEC_WIDTH = 2) (x_in , out_dec); input [DEC_WIDTH-1:0] x_in ; output reg [2:0] out_dec ; always @(*) begin case(x_in) 0: out_dec = 3'b110; 1: out_dec = 3'b101; 2: out_dec = 3'b011; 3: out_dec = 3'b111; default : out_dec = 3'bzzz ; endcase end endmodule
module decoder#(parameter DEC_WIDTH = 2) (x_in , out_dec);
input [DEC_WIDTH-1:0] x_in ; output reg [2:0] out_dec ; always @(*) begin case(x_in) 0: out_dec = 3'b110; 1: out_dec = 3'b101; 2: out_dec = 3'b011; 3: out_dec = 3'b111; default : out_dec = 3'bzzz ; endcase end endmodule
1
2,498
data/full_repos/permissive/298765980/benchmarks/Disjunctive_Decomposition/verilog/bobsm5378d2_all_bit_differing_from_cycle.v
298,765,980
bobsm5378d2_all_bit_differing_from_cycle.v
v
4,377
3,778
[]
[]
[]
[(3, 4375)]
null
data/verilator_xmls/e9ce2ed5-c3b6-4ac7-a51d-59b6d4d802c0.xml
null
117,145
module
module bobsm5378d2_all_bit_differing_from_cycle ( i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9, i_10, i_11, i_12, i_13, i_14, i_15, i_16, i_17, i_18, i_19, i_20, i_21, i_22, i_23, i_24, i_25, i_26, i_27, i_28, i_29, i_30, i_31, i_32, i_33, i_34, i_35, x_36, x_37, x_38, x_39, x_40, x_41, x_42, x_43, x_44, x_45, x_46, x_47, x_48, x_49, x_50, x_51, x_52, x_53, x_54, x_55, x_56, x_57, x_58, x_59, x_60, x_61, x_62, x_63, x_64, x_65, x_66, x_67, x_68, x_69, x_70, x_71, x_72, x_73, x_74, x_75, x_76, x_77, x_78, x_79, x_80, x_81, x_82, x_83, x_84, x_85, x_86, x_87, x_88, x_89, x_90, x_91, x_92, x_93, x_94, x_95, x_96, x_97, x_98, x_99, x_100, x_101, x_102, x_103, x_104, x_105, x_106, x_107, x_108, x_109, x_110, x_111, x_112, x_113, x_114, x_115, x_116, x_117, x_118, x_119, x_120, x_121, x_122, x_123, x_124, x_125, x_126, x_127, x_128, x_129, x_130, x_131, x_132, x_133, x_134, x_135, x_136, x_137, x_138, x_139, x_140, x_141, x_142, x_143, x_144, x_145, x_146, x_147, x_148, x_149, x_150, x_151, x_152, x_153, x_154, x_155, x_156, x_157, x_158, x_159, x_160, x_161, x_162, x_163, x_164, x_165, x_166, x_167, x_168, x_169, x_170, x_171, x_172, x_173, x_174, x_175, x_176, x_177, x_178, x_179, x_180, x_181, x_182, x_183, x_184, x_185, x_186, x_187, x_188, x_189, x_190, x_191, x_192, x_193, x_194, x_195, x_196, x_197, x_198, x_199, x_200, x_201, x_202, x_203, x_204, x_205, x_206, x_207, x_208, x_209, x_210, x_211, x_212, x_213, x_214, x_215, x_216, x_217, x_218, x_219, x_220, x_221, x_222, x_223, x_224, x_225, x_226, x_227, x_228, x_229, x_230, x_231, x_232, x_233, x_234, x_235, x_236, x_237, x_238, x_239, x_240, x_241, x_242, x_243, x_244, x_245, x_246, x_247, x_248, x_249, x_250, x_251, x_252, x_253, x_254, x_255, x_256, x_257, x_258, x_259, x_260, x_261, x_262, x_263, x_264, x_265, x_266, x_267, x_268, x_269, x_270, x_271, x_272, x_273, x_274, x_275, x_276, x_277, x_278, x_279, x_280, x_281, x_282, x_283, x_284, x_285, x_286, x_287, x_288, x_289, x_290, x_291, x_292, x_293, x_294, x_295, x_296, x_297, x_298, x_299, x_300, x_301, x_302, x_303, x_304, x_305, x_306, x_307, x_308, x_309, x_310, x_311, x_312, x_313, x_314, x_315, x_316, x_317, x_318, x_319, x_320, x_321, x_322, x_323, x_324, x_325, x_326, x_327, x_328, x_329, x_330, x_331, x_332, x_333, x_334, x_335, x_336, x_337, x_338, x_339, x_340, x_341, x_342, x_343, x_344, x_345, x_346, x_347, x_348, x_349, x_350, x_351, x_352, x_353, x_354, x_355, x_356, x_357, x_358, x_359, x_360, x_361, x_362, x_363, x_364, x_365, x_366, x_367, x_368, x_369, x_370, x_371, x_372, x_373, x_374, x_375, x_376, x_377, x_378, x_379, x_380, x_381, x_382, x_383, x_384, x_385, x_386, x_387, x_388, x_389, x_390, x_391, x_392, x_393, x_394, x_395, x_396, x_397, x_398, x_399, x_400, x_401, x_402, x_403, x_404, x_405, x_406, x_407, x_408, x_409, x_410, x_411, x_412, x_413, x_414, x_415, x_416, x_417, x_418, x_419, x_420, x_421, x_422, x_423, x_424, x_425, x_426, x_427, x_428, x_429, x_430, x_431, x_432, x_433, x_434, x_435, x_436, x_437, x_438, x_439, x_440, x_441, x_442, x_443, x_444, x_445, x_446, x_447, x_448, x_449, x_450, x_451, x_452, x_453, x_454, x_455, x_456, x_457, x_458, x_459, x_460, x_461, x_462, x_463, x_464, x_465, x_466, x_467, x_468, x_469, x_470, x_471, x_472, x_473, x_474, x_475, x_476, x_477, x_478, x_479, x_480, x_481, x_482, x_483, x_484, x_485, x_486, x_487, x_488, x_489, x_490, x_491, x_492, x_493, x_494, x_495, x_496, x_497, x_498, x_499, x_500, x_501, x_502, x_503, x_504, x_505, x_506, x_507, x_508, x_509, x_510, x_511, x_512, x_513, x_514, x_515, x_516, x_517, x_518, x_519, x_520, x_521, x_522, x_523, x_524, x_525, x_526, x_527, x_528, x_529, x_530, x_531, x_532, x_533, x_534, x_535, x_536, x_537, x_538, x_539, x_540, x_541, x_542, x_543, x_544, x_545, x_546, x_547, o_1 ); input i_1; input i_2; input i_3; input i_4; input i_5; input i_6; input i_7; input i_8; input i_9; input i_10; input i_11; input i_12; input i_13; input i_14; input i_15; input i_16; input i_17; input i_18; input i_19; input i_20; input i_21; input i_22; input i_23; input i_24; input i_25; input i_26; input i_27; input i_28; input i_29; input i_30; input i_31; input i_32; input i_33; input i_34; input i_35; input x_36; input x_37; input x_38; input x_39; input x_40; input x_41; input x_42; input x_43; input x_44; input x_45; input x_46; input x_47; input x_48; input x_49; input x_50; input x_51; input x_52; input x_53; input x_54; input x_55; input x_56; input x_57; input x_58; input x_59; input x_60; input x_61; input x_62; input x_63; input x_64; input x_65; input x_66; input x_67; input x_68; input x_69; input x_70; input x_71; input x_72; input x_73; input x_74; input x_75; input x_76; input x_77; input x_78; input x_79; input x_80; input x_81; input x_82; input x_83; input x_84; input x_85; input x_86; input x_87; input x_88; input x_89; input x_90; input x_91; input x_92; input x_93; input x_94; input x_95; input x_96; input x_97; input x_98; input x_99; input x_100; input x_101; input x_102; input x_103; input x_104; input x_105; input x_106; input x_107; input x_108; input x_109; input x_110; input x_111; input x_112; input x_113; input x_114; input x_115; input x_116; input x_117; input x_118; input x_119; input x_120; input x_121; input x_122; input x_123; input x_124; input x_125; input x_126; input x_127; input x_128; input x_129; input x_130; input x_131; input x_132; input x_133; input x_134; input x_135; input x_136; input x_137; input x_138; input x_139; input x_140; input x_141; input x_142; input x_143; input x_144; input x_145; input x_146; input x_147; input x_148; input x_149; input x_150; input x_151; input x_152; input x_153; input x_154; input x_155; input x_156; input x_157; input x_158; input x_159; input x_160; input x_161; input x_162; input x_163; input x_164; input x_165; input x_166; input x_167; input x_168; input x_169; input x_170; input x_171; input x_172; input x_173; input x_174; input x_175; input x_176; input x_177; input x_178; input x_179; input x_180; input x_181; input x_182; input x_183; input x_184; input x_185; input x_186; input x_187; input x_188; input x_189; input x_190; input x_191; input x_192; input x_193; input x_194; input x_195; input x_196; input x_197; input x_198; input x_199; input x_200; input x_201; input x_202; input x_203; input x_204; input x_205; input x_206; input x_207; input x_208; input x_209; input x_210; input x_211; input x_212; input x_213; input x_214; input x_215; input x_216; input x_217; input x_218; input x_219; input x_220; input x_221; input x_222; input x_223; input x_224; input x_225; input x_226; input x_227; input x_228; input x_229; input x_230; input x_231; input x_232; input x_233; input x_234; input x_235; input x_236; input x_237; input x_238; input x_239; input x_240; input x_241; input x_242; input x_243; input x_244; input x_245; input x_246; input x_247; input x_248; input x_249; input x_250; input x_251; input x_252; input x_253; input x_254; input x_255; input x_256; input x_257; input x_258; input x_259; input x_260; input x_261; input x_262; input x_263; input x_264; input x_265; input x_266; input x_267; input x_268; input x_269; input x_270; input x_271; input x_272; input x_273; input x_274; input x_275; input x_276; input x_277; input x_278; input x_279; input x_280; input x_281; input x_282; input x_283; input x_284; input x_285; input x_286; input x_287; input x_288; input x_289; input x_290; input x_291; input x_292; input x_293; input x_294; input x_295; input x_296; input x_297; input x_298; input x_299; input x_300; input x_301; input x_302; input x_303; input x_304; input x_305; input x_306; input x_307; input x_308; input x_309; input x_310; input x_311; input x_312; input x_313; input x_314; input x_315; input x_316; input x_317; input x_318; input x_319; input x_320; input x_321; input x_322; input x_323; input x_324; input x_325; input x_326; input x_327; input x_328; input x_329; input x_330; input x_331; input x_332; input x_333; input x_334; input x_335; input x_336; input x_337; input x_338; input x_339; input x_340; input x_341; input x_342; input x_343; input x_344; input x_345; input x_346; input x_347; input x_348; input x_349; input x_350; input x_351; input x_352; input x_353; input x_354; input x_355; input x_356; input x_357; input x_358; input x_359; input x_360; input x_361; input x_362; input x_363; input x_364; input x_365; input x_366; input x_367; input x_368; input x_369; input x_370; input x_371; input x_372; input x_373; input x_374; input x_375; input x_376; input x_377; input x_378; input x_379; input x_380; input x_381; input x_382; input x_383; input x_384; input x_385; input x_386; input x_387; input x_388; input x_389; input x_390; input x_391; input x_392; input x_393; input x_394; input x_395; input x_396; input x_397; input x_398; input x_399; input x_400; input x_401; input x_402; input x_403; input x_404; input x_405; input x_406; input x_407; input x_408; input x_409; input x_410; input x_411; input x_412; input x_413; input x_414; input x_415; input x_416; input x_417; input x_418; input x_419; input x_420; input x_421; input x_422; input x_423; input x_424; input x_425; input x_426; input x_427; input x_428; input x_429; input x_430; input x_431; input x_432; input x_433; input x_434; input x_435; input x_436; input x_437; input x_438; input x_439; input x_440; input x_441; input x_442; input x_443; input x_444; input x_445; input x_446; input x_447; input x_448; input x_449; input x_450; input x_451; input x_452; input x_453; input x_454; input x_455; input x_456; input x_457; input x_458; input x_459; input x_460; input x_461; input x_462; input x_463; input x_464; input x_465; input x_466; input x_467; input x_468; input x_469; input x_470; input x_471; input x_472; input x_473; input x_474; input x_475; input x_476; input x_477; input x_478; input x_479; input x_480; input x_481; input x_482; input x_483; input x_484; input x_485; input x_486; input x_487; input x_488; input x_489; input x_490; input x_491; input x_492; input x_493; input x_494; input x_495; input x_496; input x_497; input x_498; input x_499; input x_500; input x_501; input x_502; input x_503; input x_504; input x_505; input x_506; input x_507; input x_508; input x_509; input x_510; input x_511; input x_512; input x_513; input x_514; input x_515; input x_516; input x_517; input x_518; input x_519; input x_520; input x_521; input x_522; input x_523; input x_524; input x_525; input x_526; input x_527; input x_528; input x_529; input x_530; input x_531; input x_532; input x_533; input x_534; input x_535; input x_536; input x_537; input x_538; input x_539; input x_540; input x_541; input x_542; input x_543; input x_544; input x_545; input x_546; input x_547; output o_1; wire n_1; wire n_2; wire n_3; wire n_4; wire n_5; wire n_6; wire n_7; wire n_8; wire n_9; wire n_10; wire n_11; wire n_12; wire n_13; wire n_14; wire n_15; wire n_16; wire n_17; wire n_18; wire n_19; wire n_20; wire n_21; wire n_22; wire n_23; wire n_24; wire n_25; wire n_26; wire n_27; wire n_28; wire n_29; wire n_30; wire n_31; wire n_32; wire n_33; wire n_34; wire n_35; wire n_36; wire n_37; wire n_38; wire n_39; wire n_40; wire n_41; wire n_42; wire n_43; wire n_44; wire n_45; wire n_46; wire n_47; wire n_48; wire n_49; wire n_50; wire n_51; wire n_52; wire n_53; wire n_54; wire n_55; wire n_56; wire n_57; wire n_58; wire n_59; wire n_60; wire n_61; wire n_62; wire n_63; wire n_64; wire n_65; wire n_66; wire n_67; wire n_68; wire n_69; wire n_70; wire n_71; wire n_72; wire n_73; wire n_74; wire n_75; wire n_76; wire n_77; wire n_78; wire n_79; wire n_80; wire n_81; wire n_82; wire n_83; wire n_84; wire n_85; wire n_86; wire n_87; wire n_88; wire n_89; wire n_90; wire n_91; wire n_92; wire n_93; wire n_94; wire n_95; wire n_96; wire n_97; wire n_98; wire n_99; wire n_100; wire n_101; wire n_102; wire n_103; wire n_104; wire n_105; wire n_106; wire n_107; wire n_108; wire n_109; wire n_110; wire n_111; wire n_112; wire n_113; wire n_114; wire n_115; wire n_116; wire n_117; wire n_118; wire n_119; wire n_120; wire n_121; wire n_122; wire n_123; wire n_124; wire n_125; wire n_126; wire n_127; wire n_128; wire n_129; wire n_130; wire n_131; wire n_132; wire n_133; wire n_134; wire n_135; wire n_136; wire n_137; wire n_138; wire n_139; wire n_140; wire n_141; wire n_142; wire n_143; wire n_144; wire n_145; wire n_146; wire n_147; wire n_148; wire n_149; wire n_150; wire n_151; wire n_152; wire n_153; wire n_154; wire n_155; wire n_156; wire n_157; wire n_158; wire n_159; wire n_160; wire n_161; wire n_162; wire n_163; wire n_164; wire n_165; wire n_166; wire n_167; wire n_168; wire n_169; wire n_170; wire n_171; wire n_172; wire n_173; wire n_174; wire n_175; wire n_176; wire n_177; wire n_178; wire n_179; wire n_180; wire n_181; wire n_182; wire n_183; wire n_184; wire n_185; wire n_186; wire n_187; wire n_188; wire n_189; wire n_190; wire n_191; wire n_192; wire n_193; wire n_194; wire n_195; wire n_196; wire n_197; wire n_198; wire n_199; wire n_200; wire n_201; wire n_202; wire n_203; wire n_204; wire n_205; wire n_206; wire n_207; wire n_208; wire n_209; wire n_210; wire n_211; wire n_212; wire n_213; wire n_214; wire n_215; wire n_216; wire n_217; wire n_218; wire n_219; wire n_220; wire n_221; wire n_222; wire n_223; wire n_224; wire n_225; wire n_226; wire n_227; wire n_228; wire n_229; wire n_230; wire n_231; wire n_232; wire n_233; wire n_234; wire n_235; wire n_236; wire n_237; wire n_238; wire n_239; wire n_240; wire n_241; wire n_242; wire n_243; wire n_244; wire n_245; wire n_246; wire n_247; wire n_248; wire n_249; wire n_250; wire n_251; wire n_252; wire n_253; wire n_254; wire n_255; wire n_256; wire n_257; wire n_258; wire n_259; wire n_260; wire n_261; wire n_262; wire n_263; wire n_264; wire n_265; wire n_266; wire n_267; wire n_268; wire n_269; wire n_270; wire n_271; wire n_272; wire n_273; wire n_274; wire n_275; wire n_276; wire n_277; wire n_278; wire n_279; wire n_280; wire n_281; wire n_282; wire n_283; wire n_284; wire n_285; wire n_286; wire n_287; wire n_288; wire n_289; wire n_290; wire n_291; wire n_292; wire n_293; wire n_294; wire n_295; wire n_296; wire n_297; wire n_298; wire n_299; wire n_300; wire n_301; wire n_302; wire n_303; wire n_304; wire n_305; wire n_306; wire n_307; wire n_308; wire n_309; wire n_310; wire n_311; wire n_312; wire n_313; wire n_314; wire n_315; wire n_316; wire n_317; wire n_318; wire n_319; wire n_320; wire n_321; wire n_322; wire n_323; wire n_324; wire n_325; wire n_326; wire n_327; wire n_328; wire n_329; wire n_330; wire n_331; wire n_332; wire n_333; wire n_334; wire n_335; wire n_336; wire n_337; wire n_338; wire n_339; wire n_340; wire n_341; wire n_342; wire n_343; wire n_344; wire n_345; wire n_346; wire n_347; wire n_348; wire n_349; wire n_350; wire n_351; wire n_352; wire n_353; wire n_354; wire n_355; wire n_356; wire n_357; wire n_358; wire n_359; wire n_360; wire n_361; wire n_362; wire n_363; wire n_364; wire n_365; wire n_366; wire n_367; wire n_368; wire n_369; wire n_370; wire n_371; wire n_372; wire n_373; wire n_374; wire n_375; wire n_376; wire n_377; wire n_378; wire n_379; wire n_380; wire n_381; wire n_382; wire n_383; wire n_384; wire n_385; wire n_386; wire n_387; wire n_388; wire n_389; wire n_390; wire n_391; wire n_392; wire n_393; wire n_394; wire n_395; wire n_396; wire n_397; wire n_398; wire n_399; wire n_400; wire n_401; wire n_402; wire n_403; wire n_404; wire n_405; wire n_406; wire n_407; wire n_408; wire n_409; wire n_410; wire n_411; wire n_412; wire n_413; wire n_414; wire n_415; wire n_416; wire n_417; wire n_418; wire n_419; wire n_420; wire n_421; wire n_422; wire n_423; wire n_424; wire n_425; wire n_426; wire n_427; wire n_428; wire n_429; wire n_430; wire n_431; wire n_432; wire n_433; wire n_434; wire n_435; wire n_436; wire n_437; wire n_438; wire n_439; wire n_440; wire n_441; wire n_442; wire n_443; wire n_444; wire n_445; wire n_446; wire n_447; wire n_448; wire n_449; wire n_450; wire n_451; wire n_452; wire n_453; wire n_454; wire n_455; wire n_456; wire n_457; wire n_458; wire n_459; wire n_460; wire n_461; wire n_462; wire n_463; wire n_464; wire n_465; wire n_466; wire n_467; wire n_468; wire n_469; wire n_470; wire n_471; wire n_472; wire n_473; wire n_474; wire n_475; wire n_476; wire n_477; wire n_478; wire n_479; wire n_480; wire n_481; wire n_482; wire n_483; wire n_484; wire n_485; wire n_486; wire n_487; wire n_488; wire n_489; wire n_490; wire n_491; wire n_492; wire n_493; wire n_494; wire n_495; wire n_496; wire n_497; wire n_498; wire n_499; wire n_500; wire n_501; wire n_502; wire n_503; wire n_504; wire n_505; wire n_506; wire n_507; wire n_508; wire n_509; wire n_510; wire n_511; wire n_512; wire n_513; wire n_514; wire n_515; wire n_516; wire n_517; wire n_518; wire n_519; wire n_520; wire n_521; wire n_522; wire n_523; wire n_524; wire n_525; wire n_526; wire n_527; wire n_528; wire n_529; wire n_530; wire n_531; wire n_532; wire n_533; wire n_534; wire n_535; wire n_536; wire n_537; wire n_538; wire n_539; wire n_540; wire n_541; wire n_542; wire n_543; wire n_544; wire n_545; wire n_546; wire n_547; wire n_548; wire n_549; wire n_550; wire n_551; wire n_552; wire n_553; wire n_554; wire n_555; wire n_556; wire n_557; wire n_558; wire n_559; wire n_560; wire n_561; wire n_562; wire n_563; wire n_564; wire n_565; wire n_566; wire n_567; wire n_568; wire n_569; wire n_570; wire n_571; wire n_572; wire n_573; wire n_574; wire n_575; wire n_576; wire n_577; wire n_578; wire n_579; wire n_580; wire n_581; wire n_582; wire n_583; wire n_584; wire n_585; wire n_586; wire n_587; wire n_588; wire n_589; wire n_590; wire n_591; wire n_592; wire n_593; wire n_594; wire n_595; wire n_596; wire n_597; wire n_598; wire n_599; wire n_600; wire n_601; wire n_602; wire n_603; wire n_604; wire n_605; wire n_606; wire n_607; wire n_608; wire n_609; wire n_610; wire n_611; wire n_612; wire n_613; wire n_614; wire n_615; wire n_616; wire n_617; wire n_618; wire n_619; wire n_620; wire n_621; wire n_622; wire n_623; wire n_624; wire n_625; wire n_626; wire n_627; wire n_628; wire n_629; wire n_630; wire n_631; wire n_632; wire n_633; wire n_634; wire n_635; wire n_636; wire n_637; wire n_638; wire n_639; wire n_640; wire n_641; wire n_642; wire n_643; wire n_644; wire n_645; wire n_646; wire n_647; wire n_648; wire n_649; wire n_650; wire n_651; wire n_652; wire n_653; wire n_654; wire n_655; wire n_656; wire n_657; wire n_658; wire n_659; wire n_660; wire n_661; wire n_662; wire n_663; wire n_664; wire n_665; wire n_666; wire n_667; wire n_668; wire n_669; wire n_670; wire n_671; wire n_672; wire n_673; wire n_674; wire n_675; wire n_676; wire n_677; wire n_678; wire n_679; wire n_680; wire n_681; wire n_682; wire n_683; wire n_684; wire n_685; wire n_686; wire n_687; wire n_688; wire n_689; wire n_690; wire n_691; wire n_692; wire n_693; wire n_694; wire n_695; wire n_696; wire n_697; wire n_698; wire n_699; wire n_700; wire n_701; wire n_702; wire n_703; wire n_704; wire n_705; wire n_706; wire n_707; wire n_708; wire n_709; wire n_710; wire n_711; wire n_712; wire n_713; wire n_714; wire n_715; wire n_716; wire n_717; wire n_718; wire n_719; wire n_720; wire n_721; wire n_722; wire n_723; wire n_724; wire n_725; wire n_726; wire n_727; wire n_728; wire n_729; wire n_730; wire n_731; wire n_732; wire n_733; wire n_734; wire n_735; wire n_736; wire n_737; wire n_738; wire n_739; wire n_740; wire n_741; wire n_742; wire n_743; wire n_744; wire n_745; wire n_746; wire n_747; wire n_748; wire n_749; wire n_750; wire n_751; wire n_752; wire n_753; wire n_754; wire n_755; wire n_756; wire n_757; wire n_758; wire n_759; wire n_760; wire n_761; wire n_762; wire n_763; wire n_764; wire n_765; wire n_766; wire n_767; wire n_768; wire n_769; wire n_770; wire n_771; wire n_772; wire n_773; wire n_774; wire n_775; wire n_776; wire n_777; wire n_778; wire n_779; wire n_780; wire n_781; wire n_782; wire n_783; wire n_784; wire n_785; wire n_786; wire n_787; wire n_788; wire n_789; wire n_790; wire n_791; wire n_792; wire n_793; wire n_794; wire n_795; wire n_796; wire n_797; wire n_798; wire n_799; wire n_800; wire n_801; wire n_802; wire n_803; wire n_804; wire n_805; wire n_806; wire n_807; wire n_808; wire n_809; wire n_810; wire n_811; wire n_812; wire n_813; wire n_814; wire n_815; wire n_816; wire n_817; wire n_818; wire n_819; wire n_820; wire n_821; wire n_822; wire n_823; wire n_824; wire n_825; wire n_826; wire n_827; wire n_828; wire n_829; wire n_830; wire n_831; wire n_832; wire n_833; wire n_834; wire n_835; wire n_836; wire n_837; wire n_838; wire n_839; wire n_840; wire n_841; wire n_842; wire n_843; wire n_844; wire n_845; wire n_846; wire n_847; wire n_848; wire n_849; wire n_850; wire n_851; wire n_852; wire n_853; wire n_854; wire n_855; wire n_856; wire n_857; wire n_858; wire n_859; wire n_860; wire n_861; wire n_862; wire n_863; wire n_864; wire n_865; wire n_866; wire n_867; wire n_868; wire n_869; wire n_870; wire n_871; wire n_872; wire n_873; wire n_874; wire n_875; wire n_876; wire n_877; wire n_878; wire n_879; wire n_880; wire n_881; wire n_882; wire n_883; wire n_884; wire n_885; wire n_886; wire n_887; wire n_888; wire n_889; wire n_890; wire n_891; wire n_892; wire n_893; wire n_894; wire n_895; wire n_896; wire n_897; wire n_898; wire n_899; wire n_900; wire n_901; wire n_902; wire n_903; wire n_904; wire n_905; wire n_906; wire n_907; wire n_908; wire n_909; wire n_910; wire n_911; wire n_912; wire n_913; wire n_914; wire n_915; wire n_916; wire n_917; wire n_918; wire n_919; wire n_920; wire n_921; wire n_922; wire n_923; wire n_924; wire n_925; wire n_926; wire n_927; wire n_928; wire n_929; wire n_930; wire n_931; wire n_932; wire n_933; wire n_934; wire n_935; wire n_936; wire n_937; wire n_938; wire n_939; wire n_940; wire n_941; wire n_942; wire n_943; wire n_944; wire n_945; wire n_946; wire n_947; wire n_948; wire n_949; wire n_950; wire n_951; wire n_952; wire n_953; wire n_954; wire n_955; wire n_956; wire n_957; wire n_958; wire n_959; wire n_960; wire n_961; wire n_962; wire n_963; wire n_964; wire n_965; wire n_966; wire n_967; wire n_968; wire n_969; wire n_970; wire n_971; wire n_972; wire n_973; wire n_974; wire n_975; wire n_976; wire n_977; wire n_978; wire n_979; wire n_980; wire n_981; wire n_982; wire n_983; wire n_984; wire n_985; wire n_986; wire n_987; wire n_988; wire n_989; wire n_990; wire n_991; wire n_992; wire n_993; wire n_994; wire n_995; wire n_996; wire n_997; wire n_998; wire n_999; wire n_1000; wire n_1001; wire n_1002; wire n_1003; wire n_1004; wire n_1005; wire n_1006; wire n_1007; wire n_1008; wire n_1009; wire n_1010; wire n_1011; wire n_1012; wire n_1013; wire n_1014; wire n_1015; wire n_1016; wire n_1017; wire n_1018; wire n_1019; wire n_1020; wire n_1021; wire n_1022; wire n_1023; wire n_1024; wire n_1025; wire n_1026; wire n_1027; wire n_1028; wire n_1029; wire n_1030; wire n_1031; wire n_1032; wire n_1033; wire n_1034; wire n_1035; wire n_1036; wire n_1037; wire n_1038; wire n_1039; wire n_1040; wire n_1041; wire n_1042; wire n_1043; wire n_1044; wire n_1045; wire n_1046; wire n_1047; wire n_1048; wire n_1049; wire n_1050; wire n_1051; wire n_1052; wire n_1053; wire n_1054; wire n_1055; wire n_1056; wire n_1057; wire n_1058; wire n_1059; wire n_1060; wire n_1061; wire n_1062; wire n_1063; wire n_1064; wire n_1065; wire n_1066; wire n_1067; wire n_1068; wire n_1069; wire n_1070; wire n_1071; wire n_1072; wire n_1073; wire n_1074; wire n_1075; wire n_1076; wire n_1077; wire n_1078; wire n_1079; wire n_1080; wire n_1081; wire n_1082; wire n_1083; wire n_1084; wire n_1085; wire n_1086; wire n_1087; wire n_1088; wire n_1089; wire n_1090; wire n_1091; wire n_1092; wire n_1093; wire n_1094; wire n_1095; wire n_1096; wire n_1097; wire n_1098; wire n_1099; wire n_1100; wire n_1101; wire n_1102; wire n_1103; wire n_1104; wire n_1105; wire n_1106; wire n_1107; wire n_1108; wire n_1109; wire n_1110; wire n_1111; wire n_1112; wire n_1113; wire n_1114; wire n_1115; wire n_1116; wire n_1117; wire n_1118; wire n_1119; wire n_1120; wire n_1121; wire n_1122; wire n_1123; wire n_1124; wire n_1125; wire n_1126; wire n_1127; wire n_1128; wire n_1129; wire n_1130; wire n_1131; wire n_1132; wire n_1133; wire n_1134; wire n_1135; wire n_1136; wire n_1137; wire n_1138; wire n_1139; wire n_1140; wire n_1141; wire n_1142; wire n_1143; wire n_1144; wire n_1145; wire n_1146; wire n_1147; wire n_1148; wire n_1149; wire n_1150; wire n_1151; wire n_1152; wire n_1153; wire n_1154; wire n_1155; wire n_1156; wire n_1157; wire n_1158; wire n_1159; wire n_1160; wire n_1161; wire n_1162; wire n_1163; wire n_1164; wire n_1165; wire n_1166; wire n_1167; wire n_1168; wire n_1169; wire n_1170; wire n_1171; wire n_1172; wire n_1173; wire n_1174; wire n_1175; wire n_1176; wire n_1177; wire n_1178; wire n_1179; wire n_1180; wire n_1181; wire n_1182; wire n_1183; wire n_1184; wire n_1185; wire n_1186; wire n_1187; wire n_1188; wire n_1189; wire n_1190; wire n_1191; wire n_1192; wire n_1193; wire n_1194; wire n_1195; wire n_1196; wire n_1197; wire n_1198; wire n_1199; wire n_1200; wire n_1201; wire n_1202; wire n_1203; wire n_1204; wire n_1205; wire n_1206; wire n_1207; wire n_1208; wire n_1209; wire n_1210; wire n_1211; wire n_1212; wire n_1213; wire n_1214; wire n_1215; wire n_1216; wire n_1217; wire n_1218; wire n_1219; wire n_1220; wire n_1221; wire n_1222; wire n_1223; wire n_1224; wire n_1225; wire n_1226; wire n_1227; wire n_1228; wire n_1229; wire n_1230; wire n_1231; wire n_1232; wire n_1233; wire n_1234; wire n_1235; wire n_1236; wire n_1237; wire n_1238; wire n_1239; wire n_1240; wire n_1241; wire n_1242; wire n_1243; wire n_1244; wire n_1245; wire n_1246; wire n_1247; wire n_1248; wire n_1249; wire n_1250; wire n_1251; wire n_1252; wire n_1253; wire n_1254; wire n_1255; wire n_1256; wire n_1257; wire n_1258; wire n_1259; wire n_1260; wire n_1261; wire n_1262; wire n_1263; wire n_1264; wire n_1265; wire n_1266; wire n_1267; wire n_1268; wire n_1269; wire n_1270; wire n_1271; wire n_1272; wire n_1273; wire n_1274; wire n_1275; wire n_1276; wire n_1277; wire n_1278; wire n_1279; wire n_1280; wire n_1281; wire n_1282; wire n_1283; wire n_1284; wire n_1285; wire n_1286; wire n_1287; wire n_1288; wire n_1289; wire n_1290; wire n_1291; wire n_1292; wire n_1293; wire n_1294; wire n_1295; wire n_1296; wire n_1297; wire n_1298; wire n_1299; wire n_1300; wire n_1301; wire n_1302; wire n_1303; wire n_1304; wire n_1305; wire n_1306; wire n_1307; wire n_1308; wire n_1309; wire n_1310; wire n_1311; wire n_1312; wire n_1313; wire n_1314; wire n_1315; wire n_1316; wire n_1317; wire n_1318; wire n_1319; wire n_1320; wire n_1321; wire n_1322; wire n_1323; wire n_1324; wire n_1325; wire n_1326; wire n_1327; wire n_1328; wire n_1329; wire n_1330; wire n_1331; wire n_1332; wire n_1333; wire n_1334; wire n_1335; wire n_1336; wire n_1337; wire n_1338; wire n_1339; wire n_1340; wire n_1341; wire n_1342; wire n_1343; wire n_1344; wire n_1345; wire n_1346; wire n_1347; wire n_1348; wire n_1349; wire n_1350; wire n_1351; wire n_1352; wire n_1353; wire n_1354; wire n_1355; wire n_1356; wire n_1357; wire n_1358; wire n_1359; wire n_1360; wire n_1361; wire n_1362; wire n_1363; wire n_1364; wire n_1365; wire n_1366; wire n_1367; wire n_1368; wire n_1369; wire n_1370; wire n_1371; wire n_1372; wire n_1373; wire n_1374; wire n_1375; wire n_1376; wire n_1377; wire n_1378; wire n_1379; wire n_1380; wire n_1381; wire n_1382; wire n_1383; wire n_1384; wire n_1385; wire n_1386; wire n_1387; wire n_1388; wire n_1389; wire n_1390; wire n_1391; wire n_1392; wire n_1393; wire n_1394; wire n_1395; wire n_1396; wire n_1397; wire n_1398; wire n_1399; wire n_1400; wire n_1401; wire n_1402; wire n_1403; wire n_1404; wire n_1405; wire n_1406; wire n_1407; wire n_1408; wire n_1409; wire n_1410; wire n_1411; wire n_1412; wire n_1413; wire n_1414; wire n_1415; wire n_1416; wire n_1417; wire n_1418; wire n_1419; wire n_1420; wire n_1421; wire n_1422; wire n_1423; wire n_1424; wire n_1425; wire n_1426; wire n_1427; wire n_1428; wire n_1429; wire n_1430; wire n_1431; wire n_1432; wire n_1433; wire n_1434; wire n_1435; wire n_1436; wire n_1437; wire n_1438; wire n_1439; wire n_1440; wire n_1441; wire n_1442; wire n_1443; wire n_1444; wire n_1445; wire n_1446; wire n_1447; wire n_1448; wire n_1449; wire n_1450; wire n_1451; wire n_1452; wire n_1453; wire n_1454; wire n_1455; wire n_1456; wire n_1457; wire n_1458; wire n_1459; wire n_1460; wire n_1461; wire n_1462; wire n_1463; wire n_1464; wire n_1465; wire n_1466; wire n_1467; wire n_1468; wire n_1469; wire n_1470; wire n_1471; wire n_1472; wire n_1473; wire n_1474; wire n_1475; wire n_1476; wire n_1477; wire n_1478; wire n_1479; wire n_1480; wire n_1481; wire n_1482; wire n_1483; wire n_1484; wire n_1485; wire n_1486; wire n_1487; wire n_1488; wire n_1489; wire n_1490; wire n_1491; wire n_1492; wire n_1493; wire n_1494; wire n_1495; wire n_1496; wire n_1497; wire n_1498; wire n_1499; wire n_1500; wire n_1501; wire n_1502; wire n_1503; wire n_1504; wire n_1505; wire n_1506; wire n_1507; wire n_1508; wire n_1509; wire n_1510; wire n_1511; wire n_1512; wire n_1513; wire n_1514; wire n_1515; wire n_1516; wire n_1517; wire n_1518; wire n_1519; wire n_1520; wire n_1521; wire n_1522; wire n_1523; wire n_1524; wire n_1525; wire n_1526; wire n_1527; wire n_1528; wire n_1529; wire n_1530; wire n_1531; wire n_1532; wire n_1533; wire n_1534; wire n_1535; wire n_1536; wire n_1537; wire n_1538; wire n_1539; wire n_1540; wire n_1541; wire n_1542; wire n_1543; wire n_1544; wire n_1545; wire n_1546; wire n_1547; wire n_1548; wire n_1549; wire n_1550; wire n_1551; wire n_1552; wire n_1553; wire n_1554; wire n_1555; wire n_1556; wire n_1557; wire n_1558; wire n_1559; wire n_1560; wire n_1561; wire n_1562; wire n_1563; wire n_1564; wire n_1565; wire n_1566; wire n_1567; wire n_1568; wire n_1569; wire n_1570; wire n_1571; wire n_1572; wire n_1573; wire n_1574; wire n_1575; wire n_1576; wire n_1577; wire n_1578; wire n_1579; wire n_1580; wire n_1581; wire n_1582; wire n_1583; wire n_1584; wire n_1585; wire n_1586; wire n_1587; wire n_1588; wire n_1589; wire n_1590; wire n_1591; wire n_1592; wire n_1593; wire n_1594; wire n_1595; wire n_1596; wire n_1597; wire n_1598; wire n_1599; wire n_1600; wire n_1601; wire n_1602; wire n_1603; wire n_1604; wire n_1605; wire n_1606; wire n_1607; wire n_1608; wire n_1609; wire n_1610; wire n_1611; wire n_1612; wire n_1613; wire n_1614; wire n_1615; wire n_1616; wire n_1617; wire n_1618; wire n_1619; wire n_1620; wire n_1621; wire n_1622; wire n_1623; wire n_1624; wire n_1625; wire n_1626; wire n_1627; wire n_1628; wire n_1629; wire n_1630; wire n_1631; wire n_1632; wire n_1633; wire n_1634; wire n_1635; wire n_1636; wire n_1637; wire n_1638; wire n_1639; wire n_1640; wire n_1641; wire n_1642; wire n_1643; wire n_1644; wire n_1645; wire n_1646; wire n_1647; wire n_1648; wire n_1649; wire n_1650; wire n_1651; wire n_1652; wire n_1653; wire n_1654; wire n_1655; wire n_1656; wire n_1657; wire n_1658; wire n_1659; wire n_1660; wire n_1661; wire n_1662; wire n_1663; wire n_1664; wire n_1665; wire n_1666; wire n_1667; wire n_1668; wire n_1669; wire n_1670; wire n_1671; wire n_1672; wire n_1673; wire n_1674; wire n_1675; wire n_1676; wire n_1677; wire n_1678; wire n_1679; wire n_1680; wire n_1681; wire n_1682; wire n_1683; wire n_1684; wire n_1685; wire n_1686; wire n_1687; wire n_1688; wire n_1689; wire n_1690; wire n_1691; wire n_1692; wire n_1693; wire n_1694; wire n_1695; wire n_1696; wire n_1697; wire n_1698; wire n_1699; wire n_1700; wire n_1701; wire n_1702; wire n_1703; wire n_1704; wire n_1705; wire n_1706; wire n_1707; wire n_1708; wire n_1709; wire n_1710; wire n_1711; wire n_1712; wire n_1713; wire n_1714; wire n_1715; wire n_1716; wire n_1717; wire n_1718; wire n_1719; wire n_1720; wire n_1721; wire n_1722; wire n_1723; wire n_1724; wire n_1725; wire n_1726; wire n_1727; wire n_1728; wire n_1729; wire n_1730; wire n_1731; wire n_1732; wire n_1733; wire n_1734; wire n_1735; wire n_1736; wire n_1737; wire n_1738; wire n_1739; wire n_1740; wire n_1741; wire n_1742; wire n_1743; wire n_1744; wire n_1745; wire n_1746; wire n_1747; wire n_1748; wire n_1749; wire n_1750; wire n_1751; wire n_1752; wire n_1753; wire n_1754; wire n_1755; wire n_1756; wire n_1757; wire n_1758; wire n_1759; wire n_1760; wire n_1761; wire n_1762; wire n_1763; wire n_1764; wire n_1765; wire n_1766; wire n_1767; wire n_1768; wire n_1769; wire n_1770; wire n_1771; wire n_1772; wire n_1773; wire n_1774; wire n_1775; wire n_1776; wire n_1777; wire n_1778; wire n_1779; wire n_1780; wire n_1781; wire n_1782; wire n_1783; wire n_1784; wire n_1785; wire n_1786; wire n_1787; wire n_1788; wire n_1789; wire n_1790; wire n_1791; wire n_1792; wire n_1793; wire n_1794; wire n_1795; wire n_1796; wire n_1797; wire n_1798; wire n_1799; wire n_1800; wire n_1801; wire n_1802; wire n_1803; wire n_1804; wire n_1805; wire n_1806; wire n_1807; wire n_1808; wire n_1809; wire n_1810; wire n_1811; wire n_1812; wire n_1813; wire n_1814; wire n_1815; wire n_1816; wire n_1817; wire n_1818; wire n_1819; wire n_1820; wire n_1821; wire n_1822; wire n_1823; wire n_1824; wire n_1825; wire n_1826; wire n_1827; wire n_1828; wire n_1829; wire n_1830; wire n_1831; wire n_1832; wire n_1833; wire n_1834; wire n_1835; wire n_1836; wire n_1837; wire n_1838; wire n_1839; wire n_1840; wire n_1841; wire n_1842; wire n_1843; wire n_1844; wire n_1845; wire n_1846; wire n_1847; wire n_1848; wire n_1849; wire n_1850; wire n_1851; wire n_1852; wire n_1853; wire n_1854; wire n_1855; wire n_1856; wire n_1857; wire n_1858; wire n_1859; wire n_1860; wire n_1861; wire n_1862; wire n_1863; wire n_1864; wire n_1865; wire n_1866; wire n_1867; wire n_1868; wire n_1869; wire n_1870; wire n_1871; wire n_1872; wire n_1873; wire n_1874; wire n_1875; wire n_1876; wire n_1877; wire n_1878; wire n_1879; wire n_1880; wire n_1881; wire n_1882; wire n_1883; wire n_1884; wire n_1885; wire n_1886; wire n_1887; wire n_1888; wire n_1889; wire n_1890; wire n_1891; wire n_1892; wire n_1893; wire n_1894; wire n_1895; wire n_1896; wire n_1897; wire n_1898; wire n_1899; wire n_1900; wire n_1901; wire n_1902; wire n_1903; wire n_1904; wire n_1905; wire n_1906; wire n_1907; wire n_1908; wire n_1909; wire n_1910; wire n_1911; assign n_1 = i_5 & i_29; assign n_2 = i_14 & i_31; assign n_3 = ~n_1 & ~n_2; assign n_4 = x_153 & n_3; assign n_5 = ~x_153 & ~n_3; assign n_6 = ~n_4 & ~n_5; assign n_7 = i_6 & i_29; assign n_8 = i_15 & i_31; assign n_9 = ~n_7 & ~n_8; assign n_10 = x_152 & n_9; assign n_11 = ~x_152 & ~n_9; assign n_12 = ~n_10 & ~n_11; assign n_13 = i_4 & i_29; assign n_14 = i_13 & i_31; assign n_15 = ~n_13 & ~n_14; assign n_16 = x_151 & n_15; assign n_17 = ~x_151 & ~n_15; assign n_18 = ~n_16 & ~n_17; assign n_19 = i_9 & i_29; assign n_20 = i_18 & i_31; assign n_21 = ~n_19 & ~n_20; assign n_22 = x_150 & n_21; assign n_23 = ~x_150 & ~n_21; assign n_24 = ~n_22 & ~n_23; assign n_25 = i_7 & i_29; assign n_26 = i_16 & i_31; assign n_27 = ~n_25 & ~n_26; assign n_28 = x_149 & n_27; assign n_29 = ~x_149 & ~n_27; assign n_30 = ~n_28 & ~n_29; assign n_31 = i_2 & i_29; assign n_32 = i_11 & i_31; assign n_33 = ~n_31 & ~n_32; assign n_34 = x_148 & n_33; assign n_35 = ~x_148 & ~n_33; assign n_36 = ~n_34 & ~n_35; assign n_37 = i_3 & i_29; assign n_38 = i_12 & i_31; assign n_39 = ~n_37 & ~n_38; assign n_40 = x_147 & n_39; assign n_41 = ~x_147 & ~n_39; assign n_42 = ~n_40 & ~n_41; assign n_43 = i_1 & i_29; assign n_44 = i_10 & i_31; assign n_45 = ~n_43 & ~n_44; assign n_46 = x_146 & n_45; assign n_47 = ~x_146 & ~n_45; assign n_48 = ~n_46 & ~n_47; assign n_49 = x_129 & ~x_130; assign n_50 = ~x_129 & x_130; assign n_51 = ~n_49 & ~n_50; assign n_52 = x_138 & ~n_51; assign n_53 = ~x_138 & n_51; assign n_54 = ~n_52 & ~n_53; assign n_55 = ~x_134 & ~x_135; assign n_56 = x_134 & x_135; assign n_57 = ~n_55 & ~n_56; assign n_58 = x_136 & n_57; assign n_59 = ~x_136 & ~n_57; assign n_60 = ~n_58 & ~n_59; assign n_61 = x_131 & ~x_132; assign n_62 = ~x_131 & x_132; assign n_63 = ~n_61 & ~n_62; assign n_64 = x_137 & ~n_63; assign n_65 = ~x_137 & n_63; assign n_66 = ~n_64 & ~n_65; assign n_67 = n_60 & ~n_66; assign n_68 = ~n_60 & n_66; assign n_69 = ~n_67 & ~n_68; assign n_70 = n_54 & n_69; assign n_71 = ~n_54 & ~n_69; assign n_72 = ~n_70 & ~n_71; assign n_73 = x_145 & ~n_72; assign n_74 = ~x_145 & n_72; assign n_75 = ~n_73 & ~n_74; assign n_76 = ~x_143 & x_144; assign n_77 = x_143 & ~x_144; assign n_78 = ~n_76 & ~n_77; assign n_79 = ~x_142 & x_143; assign n_80 = x_142 & ~x_143; assign n_81 = ~n_79 & ~n_80; assign n_82 = ~i_34 & ~x_141; assign n_83 = x_142 & ~n_82; assign n_84 = ~x_142 & n_82; assign n_85 = ~n_83 & ~n_84; assign n_86 = ~x_140 & x_141; assign n_87 = x_140 & ~x_141; assign n_88 = ~n_86 & ~n_87; assign n_89 = ~x_131 & ~x_132; assign n_90 = ~x_129 & ~x_130; assign n_91 = n_89 & n_90; assign n_92 = x_140 & ~n_91; assign n_93 = ~x_140 & n_91; assign n_94 = ~n_92 & ~n_93; assign n_95 = x_139 & ~n_72; assign n_96 = ~x_139 & n_72; assign n_97 = ~n_95 & ~n_96; assign n_98 = ~i_4 & x_138; assign n_99 = i_4 & ~x_138; assign n_100 = ~n_98 & ~n_99; assign n_101 = ~i_9 & x_137; assign n_102 = i_9 & ~x_137; assign n_103 = ~n_101 & ~n_102; assign n_104 = ~i_2 & x_136; assign n_105 = i_2 & ~x_136; assign n_106 = ~n_104 & ~n_105; assign n_107 = ~i_3 & x_135; assign n_108 = i_3 & ~x_135; assign n_109 = ~n_107 & ~n_108; assign n_110 = ~i_1 & x_134; assign n_111 = i_1 & ~x_134; assign n_112 = ~n_110 & ~n_111; assign n_113 = i_24 & ~i_25; assign n_114 = ~i_24 & i_25; assign n_115 = ~n_113 & ~n_114; assign n_116 = i_22 & ~i_23; assign n_117 = ~i_22 & i_23; assign n_118 = ~n_116 & ~n_117; assign n_119 = ~i_19 & ~i_20; assign n_120 = i_19 & i_20; assign n_121 = ~n_119 & ~n_120; assign n_122 = i_21 & ~n_121; assign n_123 = ~i_21 & n_121; assign n_124 = ~n_122 & ~n_123; assign n_125 = n_118 & ~n_124; assign n_126 = ~n_118 & n_124; assign n_127 = ~n_125 & ~n_126; assign n_128 = n_115 & n_127; assign n_129 = ~n_115 & ~n_127; assign n_130 = ~n_128 & ~n_129; assign n_131 = x_133 & n_130; assign n_132 = ~x_133 & ~n_130; assign n_133 = ~n_131 & ~n_132; assign n_134 = ~i_7 & x_132; assign n_135 = i_7 & ~x_132; assign n_136 = ~n_134 & ~n_135; assign n_137 = ~i_8 & x_131; assign n_138 = i_8 & ~x_131; assign n_139 = ~n_137 & ~n_138; assign n_140 = ~i_6 & x_130; assign n_141 = i_6 & ~x_130; assign n_142 = ~n_140 & ~n_141; assign n_143 = ~i_5 & x_129; assign n_144 = i_5 & ~x_129; assign n_145 = ~n_143 & ~n_144; assign n_146 = i_8 & i_29; assign n_147 = i_17 & i_31; assign n_148 = ~n_146 & ~n_147; assign n_149 = x_128 & n_148; assign n_150 = ~x_128 & ~n_148; assign n_151 = ~n_149 & ~n_150; assign n_152 = ~x_42 & x_43; assign n_153 = x_42 & ~x_43; assign n_154 = ~n_152 & ~n_153; assign n_155 = ~x_40 & x_41; assign n_156 = x_40 & ~x_41; assign n_157 = ~n_155 & ~n_156; assign n_158 = n_154 & ~n_157; assign n_159 = ~n_154 & n_157; assign n_160 = ~n_158 & ~n_159; assign n_161 = x_39 & n_160; assign n_162 = ~x_39 & ~n_160; assign n_163 = ~n_161 & ~n_162; assign n_164 = ~x_36 & ~x_37; assign n_165 = x_36 & x_37; assign n_166 = ~n_164 & ~n_165; assign n_167 = x_38 & ~n_166; assign n_168 = ~x_38 & n_166; assign n_169 = ~n_167 & ~n_168; assign n_170 = x_44 & ~n_169; assign n_171 = ~x_44 & n_169; assign n_172 = ~n_170 & ~n_171; assign n_173 = n_163 & n_172; assign n_174 = ~n_163 & ~n_172; assign n_175 = ~n_173 & ~n_174; assign n_176 = ~x_114 & n_175; assign n_177 = ~x_95 & ~x_97; assign n_178 = x_95 & x_97; assign n_179 = ~n_177 & ~n_178; assign n_180 = x_98 & n_179; assign n_181 = ~x_98 & ~n_179; assign n_182 = ~n_180 & ~n_181; assign n_183 = x_96 & ~x_101; assign n_184 = ~x_96 & x_101; assign n_185 = ~n_183 & ~n_184; assign n_186 = n_182 & ~n_185; assign n_187 = ~n_182 & n_185; assign n_188 = ~n_186 & ~n_187; assign n_189 = ~x_99 & ~x_100; assign n_190 = x_99 & x_100; assign n_191 = ~n_189 & ~n_190; assign n_192 = x_102 & ~x_103; assign n_193 = ~x_102 & x_103; assign n_194 = ~n_192 & ~n_193; assign n_195 = n_191 & ~n_194; assign n_196 = ~n_191 & n_194; assign n_197 = ~n_195 & ~n_196; assign n_198 = n_188 & n_197; assign n_199 = ~n_188 & ~n_197; assign n_200 = ~n_198 & ~n_199; assign n_201 = ~x_91 & ~x_93; assign n_202 = x_91 & x_93; assign n_203 = ~n_201 & ~n_202; assign n_204 = x_94 & ~n_203; assign n_205 = ~x_94 & n_203; assign n_206 = ~n_204 & ~n_205; assign n_207 = ~x_90 & ~x_92; assign n_208 = x_90 & x_92; assign n_209 = ~n_207 & ~n_208; assign n_210 = ~n_160 & n_209; assign n_211 = n_160 & ~n_209; assign n_212 = ~n_210 & ~n_211; assign n_213 = n_206 & n_212; assign n_214 = ~n_206 & ~n_212; assign n_215 = ~n_213 & ~n_214; assign n_216 = ~x_82 & ~x_83; assign n_217 = x_82 & x_83; assign n_218 = ~n_216 & ~n_217; assign n_219 = x_84 & n_218; assign n_220 = ~x_84 & ~n_218; assign n_221 = ~n_219 & ~n_220; assign n_222 = ~x_87 & ~x_88; assign n_223 = x_87 & x_88; assign n_224 = ~n_222 & ~n_223; assign n_225 = x_79 & ~x_85; assign n_226 = ~x_79 & x_85; assign n_227 = ~n_225 & ~n_226; assign n_228 = n_224 & ~n_227; assign n_229 = ~n_224 & n_227; assign n_230 = ~n_228 & ~n_229; assign n_231 = n_221 & n_230; assign n_232 = ~n_221 & ~n_230; assign n_233 = ~n_231 & ~n_232; assign n_234 = x_86 & ~x_89; assign n_235 = ~x_86 & x_89; assign n_236 = ~n_234 & ~n_235; assign n_237 = n_233 & n_236; assign n_238 = ~n_233 & ~n_236; assign n_239 = ~n_237 & ~n_238; assign n_240 = n_215 & n_239; assign n_241 = ~n_200 & n_240; assign n_242 = n_176 & n_241; assign n_243 = x_127 & ~n_242; assign n_244 = ~x_127 & n_242; assign n_245 = ~n_243 & ~n_244; assign n_246 = ~x_104 & x_106; assign n_247 = ~x_115 & ~n_246; assign n_248 = x_115 & n_246; assign n_249 = ~n_247 & ~n_248; assign n_250 = x_126 & ~n_249; assign n_251 = ~x_126 & n_249; assign n_252 = ~n_250 & ~n_251; assign n_253 = x_112 & ~x_113; assign n_254 = ~x_112 & x_113; assign n_255 = ~n_253 & ~n_254; assign n_256 = ~x_116 & n_255; assign n_257 = ~x_110 & x_111; assign n_258 = x_116 & ~n_255; assign n_259 = ~n_257 & ~n_258; assign n_260 = ~n_256 & n_259; assign n_261 = x_105 & ~x_106; assign n_262 = ~x_104 & ~x_115; assign n_263 = ~n_261 & ~n_262; assign n_264 = ~i_26 & ~x_127; assign n_265 = ~x_109 & ~n_264; assign n_266 = ~n_263 & n_265; assign n_267 = ~n_260 & n_266; assign n_268 = ~n_130 & n_267; assign n_269 = x_125 & ~n_268; assign n_270 = ~x_125 & n_268; assign n_271 = ~n_269 & ~n_270; assign n_272 = i_35 & x_76; assign n_273 = ~x_78 & n_272; assign n_274 = ~x_42 & ~x_43; assign n_275 = ~x_41 & n_274; assign n_276 = ~x_40 & n_275; assign n_277 = x_40 & ~n_275; assign n_278 = x_120 & ~n_277; assign n_279 = ~n_276 & n_278; assign n_280 = n_273 & n_279; assign n_281 = x_124 & ~n_280; assign n_282 = ~x_124 & n_280; assign n_283 = ~n_281 & ~n_282; assign n_284 = x_47 & ~x_81; assign n_285 = i_35 & ~x_80; assign n_286 = ~n_284 & n_285; assign n_287 = ~n_286 & ~n_273; assign n_288 = x_36 & x_120; assign n_289 = ~n_287 & n_288; assign n_290 = x_123 & ~n_289; assign n_291 = ~x_123 & n_289; assign n_292 = ~n_290 & ~n_291; assign n_293 = ~i_6 & x_41; assign n_294 = i_6 & ~x_41; assign n_295 = ~n_293 & ~n_294; assign n_296 = ~i_5 & x_40; assign n_297 = i_5 & ~x_40; assign n_298 = ~n_296 & ~n_297; assign n_299 = ~i_4 & x_39; assign n_300 = i_4 & ~x_39; assign n_301 = ~n_299 & ~n_300; assign n_302 = ~i_3 & x_38; assign n_303 = i_3 & ~x_38; assign n_304 = ~n_302 & ~n_303; assign n_305 = ~i_2 & x_37; assign n_306 = i_2 & ~x_37; assign n_307 = ~n_305 & ~n_306; assign n_308 = ~i_1 & x_36; assign n_309 = i_1 & ~x_36; assign n_310 = ~n_308 & ~n_309; assign n_311 = ~x_220 & x_221; assign n_312 = ~x_218 & ~x_219; assign n_313 = ~x_222 & n_312; assign n_314 = n_311 & n_313; assign n_315 = ~x_243 & n_314; assign n_316 = x_291 & ~n_315; assign n_317 = ~x_291 & n_315; assign n_318 = ~n_316 & ~n_317; assign n_319 = ~x_218 & x_219; assign n_320 = x_220 & x_221; assign n_321 = ~x_222 & n_320; assign n_322 = n_319 & n_321; assign n_323 = ~x_224 & x_225; assign n_324 = x_223 & x_227; assign n_325 = ~x_226 & n_324; assign n_326 = n_323 & n_325; assign n_327 = n_322 & n_326; assign n_328 = x_290 & ~n_327; assign n_329 = ~x_290 & n_327; assign n_330 = ~n_328 & ~n_329; assign n_331 = x_219 & n_320; assign n_332 = x_218 & n_331; assign n_333 = ~x_222 & n_332; assign n_334 = n_333 & n_326; assign n_335 = x_289 & ~n_334; assign n_336 = ~x_289 & n_334; assign n_337 = ~n_335 & ~n_336; assign n_338 = x_220 & ~x_221; assign n_339 = n_313 & n_338; assign n_340 = x_288 & ~n_339; assign n_341 = ~x_288 & n_339; assign n_342 = ~n_340 & ~n_341; assign n_343 = ~x_224 & ~x_225; assign n_344 = n_89 & n_343; assign n_345 = x_224 & x_225; assign n_346 = x_131 & x_132; assign n_347 = n_345 & n_346; assign n_348 = ~n_344 & ~n_347; assign n_349 = x_224 & ~x_225; assign n_350 = n_62 & n_349; assign n_351 = n_61 & n_323; assign n_352 = ~n_350 & ~n_351; assign n_353 = n_348 & n_352; assign n_354 = ~x_223 & x_226; assign n_355 = ~x_227 & n_354; assign n_356 = n_90 & n_355; assign n_357 = x_223 & ~x_227; assign n_358 = x_226 & n_50; assign n_359 = n_357 & n_358; assign n_360 = ~n_356 & ~n_359; assign n_361 = ~n_353 & ~n_360; assign n_362 = ~x_223 & x_227; assign n_363 = x_226 & n_362; assign n_364 = n_363 & n_343; assign n_365 = ~n_361 & ~n_364; assign n_366 = ~x_182 & ~x_215; assign n_367 = ~x_216 & n_366; assign n_368 = x_182 & x_183; assign n_369 = ~x_181 & ~n_368; assign n_370 = n_369 & n_322; assign n_371 = x_222 & n_311; assign n_372 = n_312 & n_371; assign n_373 = ~n_369 & n_372; assign n_374 = ~n_370 & ~n_373; assign n_375 = ~n_367 & ~n_374; assign n_376 = ~n_365 & n_375; assign n_377 = n_349 & n_363; assign n_378 = n_373 & ~n_377; assign n_379 = ~n_376 & n_378; assign n_380 = x_287 & ~n_379; assign n_381 = ~x_287 & n_379; assign n_382 = ~n_380 & ~n_381; assign n_383 = n_349 & n_325; assign n_384 = ~x_222 & n_319; assign n_385 = ~x_220 & ~x_221; assign n_386 = n_384 & n_385; assign n_387 = n_383 & n_386; assign n_388 = x_286 & ~n_387; assign n_389 = ~x_286 & n_387; assign n_390 = ~n_388 & ~n_389; assign n_391 = x_285 & ~n_333; assign n_392 = ~x_285 & n_333; assign n_393 = ~n_391 & ~n_392; assign n_394 = n_311 & n_384; assign n_395 = x_284 & ~n_394; assign n_396 = ~x_284 & n_394; assign n_397 = ~n_395 & ~n_396; assign n_398 = n_322 & ~n_376; assign n_399 = x_283 & ~n_398; assign n_400 = ~x_283 & n_398; assign n_401 = ~n_399 & ~n_400; assign n_402 = x_176 & ~x_177; assign n_403 = ~x_179 & ~x_180; assign n_404 = ~x_178 & n_403; assign n_405 = n_402 & n_404; assign n_406 = ~x_173 & x_175; assign n_407 = ~x_171 & ~x_172; assign n_408 = ~x_174 & n_407; assign n_409 = n_406 & n_408; assign n_410 = n_405 & n_409; assign n_411 = x_282 & ~n_410; assign n_412 = ~x_282 & n_410; assign n_413 = ~n_411 & ~n_412; assign n_414 = ~x_250 & ~x_251; assign n_415 = ~i_35 & ~n_414; assign n_416 = ~x_142 & x_144; assign n_417 = ~x_140 & ~n_416; assign n_418 = ~n_415 & n_417; assign n_419 = x_255 & n_50; assign n_420 = n_419 & n_346; assign n_421 = n_418 & n_420; assign n_422 = x_281 & ~n_421; assign n_423 = ~x_281 & n_421; assign n_424 = ~n_422 & ~n_423; assign n_425 = ~x_279 & x_280; assign n_426 = x_279 & ~x_280; assign n_427 = ~n_425 & ~n_426; assign n_428 = ~x_246 & x_279; assign n_429 = x_246 & ~x_279; assign n_430 = ~n_428 & ~n_429; assign n_431 = ~x_155 & x_278; assign n_432 = x_155 & ~x_278; assign n_433 = ~n_431 & ~n_432; assign n_434 = ~x_158 & x_277; assign n_435 = x_158 & ~x_277; assign n_436 = ~n_434 & ~n_435; assign n_437 = ~x_157 & x_276; assign n_438 = x_157 & ~x_276; assign n_439 = ~n_437 & ~n_438; assign n_440 = ~x_169 & x_275; assign n_441 = x_169 & ~x_275; assign n_442 = ~n_440 & ~n_441; assign n_443 = ~x_168 & x_274; assign n_444 = x_168 & ~x_274; assign n_445 = ~n_443 & ~n_444; assign n_446 = ~x_165 & x_273; assign n_447 = x_165 & ~x_273; assign n_448 = ~n_446 & ~n_447; assign n_449 = ~x_166 & x_272; assign n_450 = x_166 & ~x_272; assign n_451 = ~n_449 & ~n_450; assign n_452 = ~x_164 & x_271; assign n_453 = x_164 & ~x_271; assign n_454 = ~n_452 & ~n_453; assign n_455 = ~x_156 & x_270; assign n_456 = x_156 & ~x_270; assign n_457 = ~n_455 & ~n_456; assign n_458 = ~x_159 & x_269; assign n_459 = x_159 & ~x_269; assign n_460 = ~n_458 & ~n_459; assign n_461 = ~x_206 & x_268; assign n_462 = x_206 & ~x_268; assign n_463 = ~n_461 & ~n_462; assign n_464 = ~x_213 & x_267; assign n_465 = x_213 & ~x_267; assign n_466 = ~n_464 & ~n_465; assign n_467 = ~x_265 & x_266; assign n_468 = x_265 & ~x_266; assign n_469 = ~n_467 & ~n_468; assign n_470 = ~x_264 & x_265; assign n_471 = x_264 & ~x_265; assign n_472 = ~n_470 & ~n_471; assign n_473 = ~x_263 & x_264; assign n_474 = x_263 & ~x_264; assign n_475 = ~n_473 & ~n_474; assign n_476 = ~x_262 & x_263; assign n_477 = x_262 & ~x_263; assign n_478 = ~n_476 & ~n_477; assign n_479 = ~x_258 & x_262; assign n_480 = x_258 & ~x_262; assign n_481 = ~n_479 & ~n_480; assign n_482 = ~x_208 & x_261; assign n_483 = x_208 & ~x_261; assign n_484 = ~n_482 & ~n_483; assign n_485 = ~x_259 & x_260; assign n_486 = x_259 & ~x_260; assign n_487 = ~n_485 & ~n_486; assign n_488 = ~x_182 & ~x_229; assign n_489 = ~n_488 & ~n_376; assign n_490 = x_259 & ~n_489; assign n_491 = ~x_259 & n_489; assign n_492 = ~n_490 & ~n_491; assign n_493 = ~x_257 & x_258; assign n_494 = x_257 & ~x_258; assign n_495 = ~n_493 & ~n_494; assign n_496 = x_241 & x_244; assign n_497 = x_256 & n_496; assign n_498 = x_257 & ~n_497; assign n_499 = ~x_257 & n_497; assign n_500 = ~n_498 & ~n_499; assign n_501 = x_255 & n_61; assign n_502 = n_90 & n_501; assign n_503 = x_255 & n_49; assign n_504 = n_89 & n_503; assign n_505 = ~x_132 & n_419; assign n_506 = ~n_504 & ~n_505; assign n_507 = ~n_502 & n_506; assign n_508 = ~x_129 & x_132; assign n_509 = x_255 & n_508; assign n_510 = ~x_130 & n_509; assign n_511 = n_507 & ~n_510; assign n_512 = x_256 & n_511; assign n_513 = ~x_256 & ~n_511; assign n_514 = ~n_512 & ~n_513; assign n_515 = ~x_133 & ~x_205; assign n_516 = ~x_207 & ~x_212; assign n_517 = ~x_214 & n_516; assign n_518 = n_515 & n_517; assign n_519 = ~x_249 & n_518; assign n_520 = ~i_35 & ~n_519; assign n_521 = ~x_243 & x_254; assign n_522 = ~n_520 & n_521; assign n_523 = ~n_376 & n_522; assign n_524 = x_255 & ~n_523; assign n_525 = ~x_255 & n_523; assign n_526 = ~n_524 & ~n_525; assign n_527 = ~x_253 & x_254; assign n_528 = x_253 & ~x_254; assign n_529 = ~n_527 & ~n_528; assign n_530 = ~x_252 & x_253; assign n_531 = x_252 & ~x_253; assign n_532 = ~n_530 & ~n_531; assign n_533 = i_23 & i_24; assign n_534 = ~i_21 & n_119; assign n_535 = i_31 & ~x_245; assign n_536 = n_534 & n_535; assign n_537 = i_22 & i_30; assign n_538 = n_536 & n_537; assign n_539 = n_533 & n_538; assign n_540 = ~i_27 & ~i_28; assign n_541 = i_21 & ~n_540; assign n_542 = i_29 & n_119; assign n_543 = ~x_245 & n_542; assign n_544 = n_541 & n_543; assign n_545 = i_23 & ~i_24; assign n_546 = i_22 & n_545; assign n_547 = n_544 & n_546; assign n_548 = ~n_539 & ~n_547; assign n_549 = x_252 & n_548; assign n_550 = ~x_252 & ~n_548; assign n_551 = ~n_549 & ~n_550; assign n_552 = x_251 & n_518; assign n_553 = ~x_251 & ~n_518; assign n_554 = ~n_552 & ~n_553; assign n_555 = ~x_249 & x_250; assign n_556 = x_249 & ~x_250; assign n_557 = ~n_555 & ~n_556; assign n_558 = x_248 & ~n_386; assign n_559 = ~x_248 & n_386; assign n_560 = ~n_558 & ~n_559; assign n_561 = x_218 & ~x_219; assign n_562 = ~x_222 & n_561; assign n_563 = n_311 & n_562; assign n_564 = ~n_369 & n_563; assign n_565 = x_247 & ~n_564; assign n_566 = ~x_247 & n_564; assign n_567 = ~n_565 & ~n_566; assign n_568 = ~x_244 & x_246; assign n_569 = x_244 & ~x_246; assign n_570 = ~n_568 & ~n_569; assign n_571 = x_243 & ~x_244; assign n_572 = ~n_520 & ~n_571; assign n_573 = n_489 & n_572; assign n_574 = x_245 & ~n_573; assign n_575 = ~x_245 & n_573; assign n_576 = ~n_574 & ~n_575; assign n_577 = n_62 & n_419; assign n_578 = n_418 & n_577; assign n_579 = x_244 & ~n_578; assign n_580 = ~x_244 & n_578; assign n_581 = ~n_579 & ~n_580; assign n_582 = ~x_242 & x_243; assign n_583 = x_242 & ~x_243; assign n_584 = ~n_582 & ~n_583; assign n_585 = ~x_241 & x_242; assign n_586 = x_241 & ~x_242; assign n_587 = ~n_585 & ~n_586; assign n_588 = ~x_240 & x_241; assign n_589 = x_240 & ~x_241; assign n_590 = ~n_588 & ~n_589; assign n_591 = x_231 & x_232; assign n_592 = n_369 & n_591; assign n_593 = n_394 & n_592; assign n_594 = ~n_591 & n_370; assign n_595 = ~n_593 & ~n_594; assign n_596 = x_234 & n_373; assign n_597 = ~x_234 & ~n_369; assign n_598 = n_333 & n_597; assign n_599 = ~n_596 & ~n_598; assign n_600 = n_595 & n_599; assign n_601 = n_369 & ~n_323; assign n_602 = ~n_369 & ~n_349; assign n_603 = ~n_602 & n_363; assign n_604 = ~n_601 & n_603; assign n_605 = x_236 & x_238; assign n_606 = x_237 & n_605; assign n_607 = x_235 & n_606; assign n_608 = ~x_239 & ~n_607; assign n_609 = n_604 & ~n_608; assign n_610 = ~n_600 & n_609; assign n_611 = x_240 & ~n_610; assign n_612 = ~x_240 & n_610; assign n_613 = ~n_611 & ~n_612; assign n_614 = ~n_504 & ~n_510; assign n_615 = ~n_502 & n_614; assign n_616 = x_239 & n_615; assign n_617 = ~x_239 & ~n_615; assign n_618 = ~n_616 & ~n_617; assign n_619 = ~x_209 & x_238; assign n_620 = x_209 & ~x_238; assign n_621 = ~n_619 & ~n_620; assign n_622 = ~x_211 & x_237; assign n_623 = x_211 & ~x_237; assign n_624 = ~n_622 & ~n_623; assign n_625 = ~x_210 & x_236; assign n_626 = x_210 & ~x_236; assign n_627 = ~n_625 & ~n_626; assign n_628 = x_235 & ~n_505; assign n_629 = ~x_235 & n_505; assign n_630 = ~n_628 & ~n_629; assign n_631 = ~x_233 & x_234; assign n_632 = x_233 & ~x_234; assign n_633 = ~n_631 & ~n_632; assign n_634 = n_321 & n_312; assign n_635 = n_383 & n_634; assign n_636 = x_233 & ~n_635; assign n_637 = ~x_233 & n_635; assign n_638 = ~n_636 & ~n_637; assign n_639 = x_232 & n_507; assign n_640 = ~x_232 & ~n_507; assign n_641 = ~n_639 & ~n_640; assign n_642 = ~x_230 & x_231; assign n_643 = x_230 & ~x_231; assign n_644 = ~n_642 & ~n_643; assign n_645 = n_343 & n_355; assign n_646 = n_314 & n_645; assign n_647 = x_230 & ~n_646; assign n_648 = ~x_230 & n_646; assign n_649 = ~n_647 & ~n_648; assign n_650 = n_507 & ~n_509; assign n_651 = x_229 & n_650; assign n_652 = ~x_229 & ~n_650; assign n_653 = ~n_651 & ~n_652; assign n_654 = ~n_374 & n_383; assign n_655 = x_228 & ~n_654; assign n_656 = ~x_228 & n_654; assign n_657 = ~n_655 & ~n_656; assign n_658 = ~x_173 & x_227; assign n_659 = x_173 & ~x_227; assign n_660 = ~n_658 & ~n_659; assign n_661 = ~x_175 & x_226; assign n_662 = x_175 & ~x_226; assign n_663 = ~n_661 & ~n_662; assign n_664 = ~x_174 & x_225; assign n_665 = x_174 & ~x_225; assign n_666 = ~n_664 & ~n_665; assign n_667 = ~x_172 & x_224; assign n_668 = x_172 & ~x_224; assign n_669 = ~n_667 & ~n_668; assign n_670 = ~x_171 & x_223; assign n_671 = x_171 & ~x_223; assign n_672 = ~n_670 & ~n_671; assign n_673 = ~x_179 & x_222; assign n_674 = x_179 & ~x_222; assign n_675 = ~n_673 & ~n_674; assign n_676 = ~x_176 & x_221; assign n_677 = x_176 & ~x_221; assign n_678 = ~n_676 & ~n_677; assign n_679 = ~x_177 & x_220; assign n_680 = x_177 & ~x_220; assign n_681 = ~n_679 & ~n_680; assign n_682 = ~x_178 & x_219; assign n_683 = x_178 & ~x_219; assign n_684 = ~n_682 & ~n_683; assign n_685 = ~x_180 & x_218; assign n_686 = x_180 & ~x_218; assign n_687 = ~n_685 & ~n_686; assign n_688 = x_217 & n_367; assign n_689 = ~x_217 & ~n_367; assign n_690 = ~n_688 & ~n_689; assign n_691 = x_216 & ~n_577; assign n_692 = ~x_216 & n_577; assign n_693 = ~n_691 & ~n_692; assign n_694 = x_215 & ~n_420; assign n_695 = ~x_215 & n_420; assign n_696 = ~n_694 & ~n_695; assign n_697 = x_179 & x_180; assign n_698 = ~n_403 & ~n_697; assign n_699 = ~x_176 & x_177; assign n_700 = ~n_699 & ~n_402; assign n_701 = ~x_178 & ~x_213; assign n_702 = x_178 & x_213; assign n_703 = ~n_701 & ~n_702; assign n_704 = n_700 & ~n_703; assign n_705 = ~n_700 & n_703; assign n_706 = ~n_704 & ~n_705; assign n_707 = n_698 & n_706; assign n_708 = ~n_698 & ~n_706; assign n_709 = ~n_707 & ~n_708; assign n_710 = x_214 & n_709; assign n_711 = ~x_214 & ~n_709; assign n_712 = ~n_710 & ~n_711; assign n_713 = ~x_260 & ~n_488; assign n_714 = ~x_252 & ~x_258; assign n_715 = ~n_713 & n_714; assign n_716 = ~n_520 & n_715; assign n_717 = n_716 & n_600; assign n_718 = x_221 & n_319; assign n_719 = ~n_311 & ~n_718; assign n_720 = ~x_267 & n_719; assign n_721 = x_267 & ~n_719; assign n_722 = ~n_720 & ~n_721; assign n_723 = n_717 & n_722; assign n_724 = x_213 & n_723; assign n_725 = ~x_213 & ~n_723; assign n_726 = ~n_724 & ~n_725; assign n_727 = x_208 & ~x_209; assign n_728 = ~x_208 & x_209; assign n_729 = ~n_727 & ~n_728; assign n_730 = x_210 & ~x_211; assign n_731 = ~x_210 & x_211; assign n_732 = ~n_730 & ~n_731; assign n_733 = n_729 & n_732; assign n_734 = ~n_729 & ~n_732; assign n_735 = ~n_733 & ~n_734; assign n_736 = x_212 & n_735; assign n_737 = ~x_212 & ~n_735; assign n_738 = ~n_736 & ~n_737; assign n_739 = ~x_237 & ~n_605; assign n_740 = ~n_739 & ~n_606; assign n_741 = n_716 & n_740; assign n_742 = x_211 & ~n_741; assign n_743 = ~x_211 & n_741; assign n_744 = ~n_742 & ~n_743; assign n_745 = ~x_236 & ~x_238; assign n_746 = n_716 & ~n_745; assign n_747 = x_210 & ~n_746; assign n_748 = ~x_210 & n_746; assign n_749 = ~n_747 & ~n_748; assign n_750 = x_209 & ~n_716; assign n_751 = ~x_209 & n_716; assign n_752 = ~n_750 & ~n_751; assign n_753 = ~x_236 & x_238; assign n_754 = ~x_261 & ~n_753; assign n_755 = x_261 & n_753; assign n_756 = ~n_754 & ~n_755; assign n_757 = n_716 & n_756; assign n_758 = x_208 & n_757; assign n_759 = ~x_208 & ~n_757; assign n_760 = ~n_758 & ~n_759; assign n_761 = x_174 & ~x_206; assign n_762 = ~x_174 & x_206; assign n_763 = ~n_761 & ~n_762; assign n_764 = ~x_171 & x_172; assign n_765 = x_171 & ~x_172; assign n_766 = ~n_764 & ~n_765; assign n_767 = x_173 & x_175; assign n_768 = ~x_173 & ~x_175; assign n_769 = ~n_767 & ~n_768; assign n_770 = n_766 & ~n_769; assign n_771 = ~n_766 & n_769; assign n_772 = ~n_770 & ~n_771; assign n_773 = n_763 & n_772; assign n_774 = ~n_763 & ~n_772; assign n_775 = ~n_773 & ~n_774; assign n_776 = x_207 & ~n_775; assign n_777 = ~x_207 & n_775; assign n_778 = ~n_776 & ~n_777; assign n_779 = n_716 & ~n_604; assign n_780 = x_225 & n_357; assign n_781 = ~n_323 & ~n_780; assign n_782 = ~x_268 & n_781; assign n_783 = x_268 & ~n_781; assign n_784 = ~n_782 & ~n_783; assign n_785 = n_779 & n_784; assign n_786 = x_206 & n_785; assign n_787 = ~x_206 & ~n_785; assign n_788 = ~n_786 & ~n_787; assign n_789 = ~x_160 & ~x_170; assign n_790 = ~x_194 & ~x_204; assign n_791 = n_789 & n_790; assign n_792 = ~i_26 & ~x_139; assign n_793 = ~x_145 & ~x_154; assign n_794 = n_792 & n_793; assign n_795 = n_791 & n_794; assign n_796 = x_205 & n_795; assign n_797 = ~x_205 & ~n_795; assign n_798 = ~n_796 & ~n_797; assign n_799 = ~x_196 & ~x_197; assign n_800 = x_196 & x_197; assign n_801 = ~n_799 & ~n_800; assign n_802 = x_198 & ~n_801; assign n_803 = ~x_198 & n_801; assign n_804 = ~n_802 & ~n_803; assign n_805 = ~x_202 & ~x_203; assign n_806 = x_202 & x_203; assign n_807 = ~n_805 & ~n_806; assign n_808 = x_201 & ~n_807; assign n_809 = ~x_201 & n_807; assign n_810 = ~n_808 & ~n_809; assign n_811 = ~x_199 & ~x_200; assign n_812 = x_199 & x_200; assign n_813 = ~n_811 & ~n_812; assign n_814 = n_810 & ~n_813; assign n_815 = ~n_810 & n_813; assign n_816 = ~n_814 & ~n_815; assign n_817 = n_804 & n_816; assign n_818 = ~n_804 & ~n_816; assign n_819 = ~n_817 & ~n_818; assign n_820 = x_195 & n_819; assign n_821 = ~x_195 & ~n_819; assign n_822 = ~n_820 & ~n_821; assign n_823 = x_204 & ~n_822; assign n_824 = ~x_204 & n_822; assign n_825 = ~n_823 & ~n_824; assign n_826 = x_174 & n_407; assign n_827 = n_826 & n_767; assign n_828 = x_175 & x_178; assign n_829 = ~x_179 & n_828; assign n_830 = ~n_827 & n_829; assign n_831 = ~x_174 & n_764; assign n_832 = n_767 & n_831; assign n_833 = x_180 & x_184; assign n_834 = n_699 & n_833; assign n_835 = ~x_180 & ~x_184; assign n_836 = n_402 & n_835; assign n_837 = ~n_834 & ~n_836; assign n_838 = ~n_832 & ~n_837; assign n_839 = n_830 & n_838; assign n_840 = ~n_507 & n_839; assign n_841 = n_3 & ~n_840; assign n_842 = x_203 & n_841; assign n_843 = ~x_203 & ~n_841; assign n_844 = ~n_842 & ~n_843; assign n_845 = n_9 & ~n_840; assign n_846 = x_202 & n_845; assign n_847 = ~x_202 & ~n_845; assign n_848 = ~n_846 & ~n_847; assign n_849 = n_15 & ~n_840; assign n_850 = x_201 & n_849; assign n_851 = ~x_201 & ~n_849; assign n_852 = ~n_850 & ~n_851; assign n_853 = n_148 & ~n_840; assign n_854 = x_200 & n_853; assign n_855 = ~x_200 & ~n_853; assign n_856 = ~n_854 & ~n_855; assign n_857 = n_27 & ~n_840; assign n_858 = x_199 & n_857; assign n_859 = ~x_199 & ~n_857; assign n_860 = ~n_858 & ~n_859; assign n_861 = n_33 & ~n_840; assign n_862 = x_198 & n_861; assign n_863 = ~x_198 & ~n_861; assign n_864 = ~n_862 & ~n_863; assign n_865 = n_39 & ~n_840; assign n_866 = x_197 & n_865; assign n_867 = ~x_197 & ~n_865; assign n_868 = ~n_866 & ~n_867; assign n_869 = n_45 & ~n_840; assign n_870 = x_196 & n_869; assign n_871 = ~x_196 & ~n_869; assign n_872 = ~n_870 & ~n_871; assign n_873 = n_21 & ~n_840; assign n_874 = x_195 & n_873; assign n_875 = ~x_195 & ~n_873; assign n_876 = ~n_874 & ~n_875; assign n_877 = ~x_185 & ~x_186; assign n_878 = x_185 & x_186; assign n_879 = ~n_877 & ~n_878; assign n_880 = x_187 & ~n_879; assign n_881 = ~x_187 & n_879; assign n_882 = ~n_880 & ~n_881; assign n_883 = ~x_191 & ~x_192; assign n_884 = x_191 & x_192; assign n_885 = ~n_883 & ~n_884; assign n_886 = x_190 & ~n_885; assign n_887 = ~x_190 & n_885; assign n_888 = ~n_886 & ~n_887; assign n_889 = ~x_188 & ~x_189; assign n_890 = x_188 & x_189; assign n_891 = ~n_889 & ~n_890; assign n_892 = n_888 & ~n_891; assign n_893 = ~n_888 & n_891; assign n_894 = ~n_892 & ~n_893; assign n_895 = n_882 & n_894; assign n_896 = ~n_882 & ~n_894; assign n_897 = ~n_895 & ~n_896; assign n_898 = x_193 & n_897; assign n_899 = ~x_193 & ~n_897; assign n_900 = ~n_898 & ~n_899; assign n_901 = x_194 & ~n_900; assign n_902 = ~x_194 & n_900; assign n_903 = ~n_901 & ~n_902; assign n_904 = n_545 & n_538; assign n_905 = ~i_23 & i_24; assign n_906 = i_22 & n_905; assign n_907 = n_544 & n_906; assign n_908 = ~n_904 & ~n_907; assign n_909 = i_9 & ~n_908; assign n_910 = ~n_840 & ~n_909; assign n_911 = x_193 & n_910; assign n_912 = ~x_193 & ~n_910; assign n_913 = ~n_911 & ~n_912; assign n_914 = i_5 & ~n_908; assign n_915 = ~n_840 & ~n_914; assign n_916 = x_192 & n_915; assign n_917 = ~x_192 & ~n_915; assign n_918 = ~n_916 & ~n_917; assign n_919 = i_6 & ~n_908; assign n_920 = ~n_840 & ~n_919; assign n_921 = x_191 & n_920; assign n_922 = ~x_191 & ~n_920; assign n_923 = ~n_921 & ~n_922; assign n_924 = i_4 & ~n_908; assign n_925 = ~n_840 & ~n_924; assign n_926 = x_190 & n_925; assign n_927 = ~x_190 & ~n_925; assign n_928 = ~n_926 & ~n_927; assign n_929 = i_8 & ~n_908; assign n_930 = ~n_840 & ~n_929; assign n_931 = x_189 & n_930; assign n_932 = ~x_189 & ~n_930; assign n_933 = ~n_931 & ~n_932; assign n_934 = i_7 & ~n_908; assign n_935 = ~n_840 & ~n_934; assign n_936 = x_188 & n_935; assign n_937 = ~x_188 & ~n_935; assign n_938 = ~n_936 & ~n_937; assign n_939 = i_2 & ~n_908; assign n_940 = ~n_840 & ~n_939; assign n_941 = x_187 & n_940; assign n_942 = ~x_187 & ~n_940; assign n_943 = ~n_941 & ~n_942; assign n_944 = i_3 & ~n_908; assign n_945 = ~n_840 & ~n_944; assign n_946 = x_186 & n_945; assign n_947 = ~x_186 & ~n_945; assign n_948 = ~n_946 & ~n_947; assign n_949 = i_1 & ~n_908; assign n_950 = ~n_949 & ~n_840; assign n_951 = x_185 & n_950; assign n_952 = ~x_185 & ~n_950; assign n_953 = ~n_951 & ~n_952; assign n_954 = x_184 & n_369; assign n_955 = ~x_184 & ~n_369; assign n_956 = ~n_954 & ~n_955; assign n_957 = x_134 & x_255; assign n_958 = n_957 & n_418; assign n_959 = x_183 & ~n_958; assign n_960 = ~x_183 & n_958; assign n_961 = ~n_959 & ~n_960; assign n_962 = x_264 & ~x_266; assign n_963 = ~n_415 & n_962; assign n_964 = x_182 & ~n_963; assign n_965 = ~x_182 & n_963; assign n_966 = ~n_964 & ~n_965; assign n_967 = x_181 & ~n_957; assign n_968 = ~x_181 & n_957; assign n_969 = ~n_967 & ~n_968; assign n_970 = x_218 & ~n_331; assign n_971 = n_319 & n_320; assign n_972 = ~n_970 & ~n_971; assign n_973 = n_717 & ~n_972; assign n_974 = x_180 & ~n_973; assign n_975 = ~x_180 & n_973; assign n_976 = ~n_974 & ~n_975; assign n_977 = x_222 & ~n_332; assign n_978 = ~n_333 & ~n_977; assign n_979 = n_717 & ~n_978; assign n_980 = x_179 & ~n_979; assign n_981 = ~x_179 & n_979; assign n_982 = ~n_980 & ~n_981; assign n_983 = ~x_219 & ~n_320; assign n_984 = ~n_331 & ~n_983; assign n_985 = n_717 & n_984; assign n_986 = x_178 & ~n_985; assign n_987 = ~x_178 & n_985; assign n_988 = ~n_986 & ~n_987; assign n_989 = n_717 & ~n_385; assign n_990 = x_177 & ~n_989; assign n_991 = ~x_177 & n_989; assign n_992 = ~n_990 & ~n_991; assign n_993 = x_176 & ~n_717; assign n_994 = ~x_176 & n_717; assign n_995 = ~n_993 & ~n_994; assign n_996 = n_345 & n_324; assign n_997 = x_226 & ~n_996; assign n_998 = n_345 & n_325; assign n_999 = ~n_997 & ~n_998; assign n_1000 = n_779 & ~n_999; assign n_1001 = x_175 & ~n_1000; assign n_1002 = ~x_175 & n_1000; assign n_1003 = ~n_1001 & ~n_1002; assign n_1004 = x_174 & ~n_779; assign n_1005 = ~x_174 & n_779; assign n_1006 = ~n_1004 & ~n_1005; assign n_1007 = x_223 & ~n_345; assign n_1008 = ~n_362 & ~n_357; assign n_1009 = ~n_1007 & n_1008; assign n_1010 = ~n_345 & n_357; assign n_1011 = ~n_1009 & ~n_1010; assign n_1012 = n_779 & n_1011; assign n_1013 = x_173 & ~n_1012; assign n_1014 = ~x_173 & n_1012; assign n_1015 = ~n_1013 & ~n_1014; assign n_1016 = n_779 & ~n_343; assign n_1017 = x_172 & ~n_1016; assign n_1018 = ~x_172 & n_1016; assign n_1019 = ~n_1017 & ~n_1018; assign n_1020 = ~x_223 & n_345; assign n_1021 = ~n_1007 & ~n_1020; assign n_1022 = ~n_1021 & n_779; assign n_1023 = x_171 & ~n_1022; assign n_1024 = ~x_171 & n_1022; assign n_1025 = ~n_1023 & ~n_1024; assign n_1026 = x_163 & ~x_167; assign n_1027 = ~x_163 & x_167; assign n_1028 = ~n_1026 & ~n_1027; assign n_1029 = ~x_164 & ~x_165; assign n_1030 = x_164 & x_165; assign n_1031 = ~n_1029 & ~n_1030; assign n_1032 = x_166 & n_1031; assign n_1033 = ~x_166 & ~n_1031; assign n_1034 = ~n_1032 & ~n_1033; assign n_1035 = ~x_161 & ~x_162; assign n_1036 = x_161 & x_162; assign n_1037 = ~n_1035 & ~n_1036; assign n_1038 = x_168 & ~x_169; assign n_1039 = ~x_168 & x_169; assign n_1040 = ~n_1038 & ~n_1039; assign n_1041 = n_1037 & n_1040; assign n_1042 = ~n_1037 & ~n_1040; assign n_1043 = ~n_1041 & ~n_1042; assign n_1044 = n_1034 & ~n_1043; assign n_1045 = ~n_1034 & n_1043; assign n_1046 = ~n_1044 & ~n_1045; assign n_1047 = n_1028 & n_1046; assign n_1048 = ~n_1028 & ~n_1046; assign n_1049 = ~n_1047 & ~n_1048; assign n_1050 = x_170 & ~n_1049; assign n_1051 = ~x_170 & n_1049; assign n_1052 = ~n_1050 & ~n_1051; assign n_1053 = n_89 & n_419; assign n_1054 = x_272 & n_1053; assign n_1055 = x_271 & n_1054; assign n_1056 = x_274 & n_1055; assign n_1057 = x_275 & n_1056; assign n_1058 = n_905 & n_538; assign n_1059 = ~i_22 & n_545; assign n_1060 = n_1059 & n_544; assign n_1061 = ~n_1058 & ~n_1060; assign n_1062 = ~x_275 & ~n_1056; assign n_1063 = n_1061 & ~n_1062; assign n_1064 = ~n_1057 & n_1063; assign n_1065 = i_14 & n_1058; assign n_1066 = i_5 & n_1060; assign n_1067 = ~n_1065 & ~n_1066; assign n_1068 = ~n_1064 & n_1067; assign n_1069 = x_169 & n_1068; assign n_1070 = ~x_169 & ~n_1068; assign n_1071 = ~n_1069 & ~n_1070; assign n_1072 = ~x_274 & ~n_1055; assign n_1073 = n_1061 & ~n_1056; assign n_1074 = ~n_1072 & n_1073; assign n_1075 = i_15 & n_1058; assign n_1076 = i_6 & n_1060; assign n_1077 = ~n_1075 & ~n_1076; assign n_1078 = ~n_1074 & n_1077; assign n_1079 = x_168 & n_1078; assign n_1080 = ~x_168 & ~n_1078; assign n_1081 = ~n_1079 & ~n_1080; assign n_1082 = i_13 & n_1058; assign n_1083 = i_4 & n_1060; assign n_1084 = ~n_1082 & ~n_1083; assign n_1085 = x_167 & n_1084; assign n_1086 = ~x_167 & ~n_1084; assign n_1087 = ~n_1085 & ~n_1086; assign n_1088 = ~x_272 & ~n_1053; assign n_1089 = ~n_1054 & ~n_1088; assign n_1090 = n_1061 & n_1089; assign n_1091 = i_8 & n_1060; assign n_1092 = i_17 & n_1058; assign n_1093 = ~n_1091 & ~n_1092; assign n_1094 = ~n_1090 & n_1093; assign n_1095 = x_166 & n_1094; assign n_1096 = ~x_166 & ~n_1094; assign n_1097 = ~n_1095 & ~n_1096; assign n_1098 = x_271 & ~x_274; assign n_1099 = x_272 & ~n_1098; assign n_1100 = n_1053 & ~n_1099; assign n_1101 = x_273 & n_1100; assign n_1102 = ~x_273 & ~n_1100; assign n_1103 = ~n_1101 & ~n_1102; assign n_1104 = n_1061 & n_1103; assign n_1105 = i_9 & n_1060; assign n_1106 = i_18 & n_1058; assign n_1107 = ~n_1105 & ~n_1106; assign n_1108 = ~n_1104 & n_1107; assign n_1109 = x_165 & n_1108; assign n_1110 = ~x_165 & ~n_1108; assign n_1111 = ~n_1109 & ~n_1110; assign n_1112 = ~x_271 & ~n_1054; assign n_1113 = ~n_1112 & ~n_1055; assign n_1114 = n_1061 & n_1113; assign n_1115 = i_16 & n_1058; assign n_1116 = i_7 & n_1060; assign n_1117 = ~n_1115 & ~n_1116; assign n_1118 = ~n_1114 & n_1117; assign n_1119 = x_164 & n_1118; assign n_1120 = ~x_164 & ~n_1118; assign n_1121 = ~n_1119 & ~n_1120; assign n_1122 = i_11 & n_1058; assign n_1123 = i_2 & n_1060; assign n_1124 = ~n_1122 & ~n_1123; assign n_1125 = x_163 & n_1124; assign n_1126 = ~x_163 & ~n_1124; assign n_1127 = ~n_1125 & ~n_1126; assign n_1128 = i_3 & n_1060; assign n_1129 = i_12 & n_1058; assign n_1130 = ~n_1128 & ~n_1129; assign n_1131 = x_162 & n_1130; assign n_1132 = ~x_162 & ~n_1130; assign n_1133 = ~n_1131 & ~n_1132; assign n_1134 = i_1 & n_1060; assign n_1135 = i_10 & n_1058; assign n_1136 = ~n_1134 & ~n_1135; assign n_1137 = x_161 & n_1136; assign n_1138 = ~x_161 & ~n_1136; assign n_1139 = ~n_1137 & ~n_1138; assign n_1140 = x_159 & ~n_51; assign n_1141 = ~x_159 & n_51; assign n_1142 = ~n_1140 & ~n_1141; assign n_1143 = ~x_155 & ~x_156; assign n_1144 = x_155 & x_156; assign n_1145 = ~n_1143 & ~n_1144; assign n_1146 = x_157 & n_1145; assign n_1147 = ~x_157 & ~n_1145; assign n_1148 = ~n_1146 & ~n_1147; assign n_1149 = x_158 & ~n_63; assign n_1150 = ~x_158 & n_63; assign n_1151 = ~n_1149 & ~n_1150; assign n_1152 = n_1148 & ~n_1151; assign n_1153 = ~n_1148 & n_1151; assign n_1154 = ~n_1152 & ~n_1153; assign n_1155 = n_1142 & n_1154; assign n_1156 = ~n_1142 & ~n_1154; assign n_1157 = ~n_1155 & ~n_1156; assign n_1158 = x_160 & ~n_1157; assign n_1159 = ~x_160 & n_1157; assign n_1160 = ~n_1158 & ~n_1159; assign n_1161 = ~i_22 & n_541; assign n_1162 = n_1161 & n_543; assign n_1163 = n_533 & n_1162; assign n_1164 = ~n_1058 & ~n_1163; assign n_1165 = n_61 & n_419; assign n_1166 = x_269 & n_1165; assign n_1167 = ~x_269 & ~n_1165; assign n_1168 = ~n_1166 & ~n_1167; assign n_1169 = n_1164 & n_1168; assign n_1170 = i_4 & ~n_1164; assign n_1171 = ~n_1169 & ~n_1170; assign n_1172 = x_159 & n_1171; assign n_1173 = ~x_159 & ~n_1171; assign n_1174 = ~n_1172 & ~n_1173; assign n_1175 = x_270 & ~x_276; assign n_1176 = x_269 & ~n_1175; assign n_1177 = n_1165 & ~n_1176; assign n_1178 = x_277 & ~n_1177; assign n_1179 = ~x_277 & n_1177; assign n_1180 = ~n_1178 & ~n_1179; assign n_1181 = n_1164 & ~n_1180; assign n_1182 = i_9 & ~n_1164; assign n_1183 = ~n_1181 & ~n_1182; assign n_1184 = x_158 & n_1183; assign n_1185 = ~x_158 & ~n_1183; assign n_1186 = ~n_1184 & ~n_1185; assign n_1187 = x_270 & n_1166; assign n_1188 = ~x_276 & ~n_1187; assign n_1189 = x_276 & n_1187; assign n_1190 = n_1164 & ~n_1189; assign n_1191 = ~n_1188 & n_1190; assign n_1192 = i_2 & ~n_1164; assign n_1193 = ~n_1191 & ~n_1192; assign n_1194 = x_157 & n_1193; assign n_1195 = ~x_157 & ~n_1193; assign n_1196 = ~n_1194 & ~n_1195; assign n_1197 = ~x_270 & ~n_1166; assign n_1198 = ~n_1187 & ~n_1197; assign n_1199 = n_1164 & n_1198; assign n_1200 = i_3 & ~n_1164; assign n_1201 = ~n_1199 & ~n_1200; assign n_1202 = x_156 & n_1201; assign n_1203 = ~x_156 & ~n_1201; assign n_1204 = ~n_1202 & ~n_1203; assign n_1205 = x_278 & ~n_1189; assign n_1206 = ~x_278 & n_1189; assign n_1207 = ~n_1205 & ~n_1206; assign n_1208 = n_1164 & ~n_1207; assign n_1209 = i_1 & ~n_1164; assign n_1210 = ~n_1208 & ~n_1209; assign n_1211 = x_155 & n_1210; assign n_1212 = ~x_155 & ~n_1210; assign n_1213 = ~n_1211 & ~n_1212; assign n_1214 = ~x_146 & ~x_147; assign n_1215 = x_146 & x_147; assign n_1216 = ~n_1214 & ~n_1215; assign n_1217 = x_148 & ~n_1216; assign n_1218 = ~x_148 & n_1216; assign n_1219 = ~n_1217 & ~n_1218; assign n_1220 = ~x_151 & ~x_152; assign n_1221 = x_151 & x_152; assign n_1222 = ~n_1220 & ~n_1221; assign n_1223 = x_153 & n_1222; assign n_1224 = ~x_153 & ~n_1222; assign n_1225 = ~n_1223 & ~n_1224; assign n_1226 = ~x_128 & ~x_149; assign n_1227 = x_128 & x_149; assign n_1228 = ~n_1226 & ~n_1227; assign n_1229 = x_150 & n_1228; assign n_1230 = ~x_150 & ~n_1228; assign n_1231 = ~n_1229 & ~n_1230; assign n_1232 = n_1225 & ~n_1231; assign n_1233 = ~n_1225 & n_1231; assign n_1234 = ~n_1232 & ~n_1233; assign n_1235 = n_1219 & n_1234; assign n_1236 = ~n_1219 & ~n_1234; assign n_1237 = ~n_1235 & ~n_1236; assign n_1238 = x_154 & n_1237; assign n_1239 = ~x_154 & ~n_1237; assign n_1240 = ~n_1238 & ~n_1239; assign n_1241 = x_122 & n_261; assign n_1242 = ~x_122 & ~n_261; assign n_1243 = ~n_1241 & ~n_1242; assign n_1244 = x_64 & ~x_66; assign n_1245 = ~x_65 & n_1244; assign n_1246 = ~x_40 & x_42; assign n_1247 = x_43 & ~x_59; assign n_1248 = x_61 & ~x_123; assign n_1249 = n_1247 & n_1248; assign n_1250 = n_1246 & n_1249; assign n_1251 = x_41 & x_58; assign n_1252 = ~x_41 & ~x_58; assign n_1253 = ~n_1251 & ~n_1252; assign n_1254 = ~n_1253 & n_1245; assign n_1255 = n_1250 & n_1254; assign n_1256 = n_1245 & ~n_1255; assign n_1257 = x_121 & ~n_1256; assign n_1258 = ~x_121 & n_1256; assign n_1259 = ~n_1257 & ~n_1258; assign n_1260 = ~i_35 & x_125; assign n_1261 = ~x_70 & ~n_1260; assign n_1262 = x_73 & n_1261; assign n_1263 = x_120 & ~n_1262; assign n_1264 = ~x_120 & n_1262; assign n_1265 = ~n_1263 & ~n_1264; assign n_1266 = i_22 & i_31; assign n_1267 = n_534 & n_1266; assign n_1268 = i_30 & n_1267; assign n_1269 = ~x_118 & n_533; assign n_1270 = n_1268 & n_1269; assign n_1271 = ~i_24 & ~x_118; assign n_1272 = n_119 & n_1271; assign n_1273 = i_23 & i_29; assign n_1274 = i_22 & n_1273; assign n_1275 = n_541 & n_1274; assign n_1276 = n_1272 & n_1275; assign n_1277 = ~n_1270 & ~n_1276; assign n_1278 = x_119 & n_1277; assign n_1279 = ~x_119 & ~n_1277; assign n_1280 = ~n_1278 & ~n_1279; assign n_1281 = x_70 & ~x_117; assign n_1282 = x_124 & ~n_1260; assign n_1283 = ~n_1281 & n_1282; assign n_1284 = ~n_1255 & n_1283; assign n_1285 = x_118 & ~n_1284; assign n_1286 = ~x_118 & n_1284; assign n_1287 = ~n_1285 & ~n_1286; assign n_1288 = x_120 & n_155; assign n_1289 = n_1288 & n_153; assign n_1290 = n_286 & n_1289; assign n_1291 = x_117 & ~n_1290; assign n_1292 = ~x_117 & n_1290; assign n_1293 = ~n_1291 & ~n_1292; assign n_1294 = ~x_119 & n_1261; assign n_1295 = x_66 & x_123; assign n_1296 = ~x_66 & ~x_123; assign n_1297 = ~n_1295 & ~n_1296; assign n_1298 = x_64 & ~x_65; assign n_1299 = ~n_1297 & n_1298; assign n_1300 = n_1294 & ~n_1299; assign n_1301 = x_62 & ~x_63; assign n_1302 = ~n_1244 & ~n_1301; assign n_1303 = ~x_67 & ~n_1302; assign n_1304 = x_67 & n_1302; assign n_1305 = ~n_1303 & ~n_1304; assign n_1306 = n_1300 & ~n_1305; assign n_1307 = x_116 & n_1306; assign n_1308 = ~x_116 & ~n_1306; assign n_1309 = ~n_1307 & ~n_1308; assign n_1310 = x_126 & n_1294; assign n_1311 = x_115 & n_1310; assign n_1312 = ~x_115 & ~n_1310; assign n_1313 = ~n_1311 & ~n_1312; assign n_1314 = n_1268 & n_1271; assign n_1315 = i_23 & n_1314; assign n_1316 = ~x_118 & n_905; assign n_1317 = i_22 & i_29; assign n_1318 = n_1316 & n_1317; assign n_1319 = n_119 & n_541; assign n_1320 = n_1318 & n_1319; assign n_1321 = ~n_1315 & ~n_1320; assign n_1322 = x_114 & n_1321; assign n_1323 = ~x_114 & ~n_1321; assign n_1324 = ~n_1322 & ~n_1323; assign n_1325 = ~x_64 & x_66; assign n_1326 = ~n_1244 & ~n_1325; assign n_1327 = n_1300 & ~n_1326; assign n_1328 = x_113 & ~n_1327; assign n_1329 = ~x_113 & n_1327; assign n_1330 = ~n_1328 & ~n_1329; assign n_1331 = x_64 & x_66; assign n_1332 = ~x_65 & ~n_1331; assign n_1333 = x_65 & n_1331; assign n_1334 = ~n_1332 & ~n_1333; assign n_1335 = n_1300 & n_1334; assign n_1336 = x_112 & ~n_1335; assign n_1337 = ~x_112 & n_1335; assign n_1338 = ~n_1336 & ~n_1337; assign n_1339 = x_63 & ~x_64; assign n_1340 = n_1294 & n_1339; assign n_1341 = x_111 & ~n_1340; assign n_1342 = ~x_111 & n_1340; assign n_1343 = ~n_1341 & ~n_1342; assign n_1344 = x_62 & n_1300; assign n_1345 = x_110 & ~n_1344; assign n_1346 = ~x_110 & n_1344; assign n_1347 = ~n_1345 & ~n_1346; assign n_1348 = x_109 & ~n_1300; assign n_1349 = ~x_109 & n_1300; assign n_1350 = ~n_1348 & ~n_1349; assign n_1351 = x_58 & x_59; assign n_1352 = x_61 & ~n_1351; assign n_1353 = ~x_61 & n_1351; assign n_1354 = ~n_1352 & ~n_1353; assign n_1355 = n_1294 & ~n_1354; assign n_1356 = x_108 & ~n_1355; assign n_1357 = ~x_108 & n_1355; assign n_1358 = ~n_1356 & ~n_1357; assign n_1359 = ~x_58 & ~x_59; assign n_1360 = ~n_1351 & ~n_1359; assign n_1361 = n_1294 & n_1360; assign n_1362 = x_107 & ~n_1361; assign n_1363 = ~x_107 & n_1361; assign n_1364 = ~n_1362 & ~n_1363; assign n_1365 = x_60 & n_1294; assign n_1366 = x_106 & ~n_1365; assign n_1367 = ~x_106 & n_1365; assign n_1368 = ~n_1366 & ~n_1367; assign n_1369 = x_122 & n_1294; assign n_1370 = x_105 & ~n_1369; assign n_1371 = ~x_105 & n_1369; assign n_1372 = ~n_1370 & ~n_1371; assign n_1373 = x_104 & ~n_1294; assign n_1374 = ~x_104 & n_1294; assign n_1375 = ~n_1373 & ~n_1374; assign n_1376 = n_274 & n_1288; assign n_1377 = x_55 & n_1376; assign n_1378 = x_53 & n_1377; assign n_1379 = x_56 & n_1378; assign n_1380 = x_57 & n_1379; assign n_1381 = n_1268 & n_1316; assign n_1382 = n_542 & n_1161; assign n_1383 = ~x_118 & n_1382; assign n_1384 = n_1383 & n_545; assign n_1385 = ~n_1381 & ~n_1384; assign n_1386 = ~x_57 & ~n_1379; assign n_1387 = n_1385 & ~n_1386; assign n_1388 = ~n_1380 & n_1387; assign n_1389 = i_14 & n_1381; assign n_1390 = i_5 & n_1384; assign n_1391 = ~n_1389 & ~n_1390; assign n_1392 = ~n_1388 & n_1391; assign n_1393 = x_103 & n_1392; assign n_1394 = ~x_103 & ~n_1392; assign n_1395 = ~n_1393 & ~n_1394; assign n_1396 = ~x_56 & ~n_1378; assign n_1397 = ~n_1396 & ~n_1379; assign n_1398 = n_1385 & n_1397; assign n_1399 = i_15 & n_1381; assign n_1400 = i_6 & n_1384; assign n_1401 = ~n_1399 & ~n_1400; assign n_1402 = ~n_1398 & n_1401; assign n_1403 = x_102 & n_1402; assign n_1404 = ~x_102 & ~n_1402; assign n_1405 = ~n_1403 & ~n_1404; assign n_1406 = i_4 & n_1384; assign n_1407 = i_13 & n_1381; assign n_1408 = ~n_1406 & ~n_1407; assign n_1409 = x_101 & n_1408; assign n_1410 = ~x_101 & ~n_1408; assign n_1411 = ~n_1409 & ~n_1410; assign n_1412 = ~x_55 & ~n_1376; assign n_1413 = ~n_1377 & ~n_1412; assign n_1414 = n_1385 & n_1413; assign n_1415 = i_8 & n_1384; assign n_1416 = i_17 & n_1381; assign n_1417 = ~n_1415 & ~n_1416; assign n_1418 = ~n_1414 & n_1417; assign n_1419 = x_100 & n_1418; assign n_1420 = ~x_100 & ~n_1418; assign n_1421 = ~n_1419 & ~n_1420; assign n_1422 = x_53 & ~x_56; assign n_1423 = x_55 & ~n_1422; assign n_1424 = n_1376 & ~n_1423; assign n_1425 = ~x_54 & ~n_1424; assign n_1426 = x_54 & n_1424; assign n_1427 = ~n_1425 & ~n_1426; assign n_1428 = n_1385 & n_1427; assign n_1429 = i_18 & n_1381; assign n_1430 = i_9 & n_1384; assign n_1431 = ~n_1429 & ~n_1430; assign n_1432 = ~n_1428 & n_1431; assign n_1433 = x_99 & n_1432; assign n_1434 = ~x_99 & ~n_1432; assign n_1435 = ~n_1433 & ~n_1434; assign n_1436 = ~x_53 & ~n_1377; assign n_1437 = ~n_1378 & ~n_1436; assign n_1438 = n_1385 & n_1437; assign n_1439 = i_16 & n_1381; assign n_1440 = i_7 & n_1384; assign n_1441 = ~n_1439 & ~n_1440; assign n_1442 = ~n_1438 & n_1441; assign n_1443 = x_98 & n_1442; assign n_1444 = ~x_98 & ~n_1442; assign n_1445 = ~n_1443 & ~n_1444; assign n_1446 = i_2 & n_1384; assign n_1447 = i_11 & n_1381; assign n_1448 = ~n_1446 & ~n_1447; assign n_1449 = x_97 & n_1448; assign n_1450 = ~x_97 & ~n_1448; assign n_1451 = ~n_1449 & ~n_1450; assign n_1452 = i_3 & n_1384; assign n_1453 = i_12 & n_1381; assign n_1454 = ~n_1452 & ~n_1453; assign n_1455 = x_96 & n_1454; assign n_1456 = ~x_96 & ~n_1454; assign n_1457 = ~n_1455 & ~n_1456; assign n_1458 = i_1 & n_1384; assign n_1459 = i_10 & n_1381; assign n_1460 = ~n_1458 & ~n_1459; assign n_1461 = x_95 & n_1460; assign n_1462 = ~x_95 & ~n_1460; assign n_1463 = ~n_1461 & ~n_1462; assign n_1464 = n_1382 & n_1269; assign n_1465 = ~n_1381 & ~n_1464; assign n_1466 = i_4 & ~n_1465; assign n_1467 = n_152 & n_1288; assign n_1468 = x_52 & n_1467; assign n_1469 = ~x_52 & ~n_1467; assign n_1470 = ~n_1468 & ~n_1469; assign n_1471 = n_1465 & n_1470; assign n_1472 = ~n_1466 & ~n_1471; assign n_1473 = x_94 & n_1472; assign n_1474 = ~x_94 & ~n_1472; assign n_1475 = ~n_1473 & ~n_1474; assign n_1476 = ~i_9 & ~n_1465; assign n_1477 = x_49 & ~x_50; assign n_1478 = x_52 & ~n_1477; assign n_1479 = n_1467 & ~n_1478; assign n_1480 = x_51 & ~n_1479; assign n_1481 = ~x_51 & n_1479; assign n_1482 = ~n_1480 & ~n_1481; assign n_1483 = n_1465 & n_1482; assign n_1484 = ~n_1476 & ~n_1483; assign n_1485 = x_93 & ~n_1484; assign n_1486 = ~x_93 & n_1484; assign n_1487 = ~n_1485 & ~n_1486; assign n_1488 = i_2 & ~n_1465; assign n_1489 = x_49 & n_1468; assign n_1490 = ~x_50 & ~n_1489; assign n_1491 = x_50 & n_1489; assign n_1492 = n_1465 & ~n_1491; assign n_1493 = ~n_1490 & n_1492; assign n_1494 = ~n_1488 & ~n_1493; assign n_1495 = x_92 & n_1494; assign n_1496 = ~x_92 & ~n_1494; assign n_1497 = ~n_1495 & ~n_1496; assign n_1498 = i_3 & ~n_1465; assign n_1499 = ~x_49 & ~n_1468; assign n_1500 = ~n_1489 & ~n_1499; assign n_1501 = n_1465 & n_1500; assign n_1502 = ~n_1498 & ~n_1501; assign n_1503 = x_91 & n_1502; assign n_1504 = ~x_91 & ~n_1502; assign n_1505 = ~n_1503 & ~n_1504; assign n_1506 = x_48 & ~n_1491; assign n_1507 = ~x_48 & n_1491; assign n_1508 = ~n_1506 & ~n_1507; assign n_1509 = n_1465 & ~n_1508; assign n_1510 = i_1 & ~n_1465; assign n_1511 = ~n_1509 & ~n_1510; assign n_1512 = x_90 & n_1511; assign n_1513 = ~x_90 & ~n_1511; assign n_1514 = ~n_1512 & ~n_1513; assign n_1515 = x_89 & n_3; assign n_1516 = ~x_89 & ~n_3; assign n_1517 = ~n_1515 & ~n_1516; assign n_1518 = x_88 & n_9; assign n_1519 = ~x_88 & ~n_9; assign n_1520 = ~n_1518 & ~n_1519; assign n_1521 = x_87 & n_15; assign n_1522 = ~x_87 & ~n_15; assign n_1523 = ~n_1521 & ~n_1522; assign n_1524 = x_86 & n_21; assign n_1525 = ~x_86 & ~n_21; assign n_1526 = ~n_1524 & ~n_1525; assign n_1527 = x_85 & n_27; assign n_1528 = ~x_85 & ~n_27; assign n_1529 = ~n_1527 & ~n_1528; assign n_1530 = x_84 & n_33; assign n_1531 = ~x_84 & ~n_33; assign n_1532 = ~n_1530 & ~n_1531; assign n_1533 = x_83 & n_39; assign n_1534 = ~x_83 & ~n_39; assign n_1535 = ~n_1533 & ~n_1534; assign n_1536 = x_82 & n_45; assign n_1537 = ~x_82 & ~n_45; assign n_1538 = ~n_1536 & ~n_1537; assign n_1539 = ~i_34 & ~x_45; assign n_1540 = x_81 & ~n_1539; assign n_1541 = ~x_81 & n_1539; assign n_1542 = ~n_1540 & ~n_1541; assign n_1543 = x_80 & ~n_276; assign n_1544 = ~x_80 & n_276; assign n_1545 = ~n_1543 & ~n_1544; assign n_1546 = x_79 & n_148; assign n_1547 = ~x_79 & ~n_148; assign n_1548 = ~n_1546 & ~n_1547; assign n_1549 = ~x_77 & x_78; assign n_1550 = x_77 & ~x_78; assign n_1551 = ~n_1549 & ~n_1550; assign n_1552 = ~x_76 & x_77; assign n_1553 = x_76 & ~x_77; assign n_1554 = ~n_1552 & ~n_1553; assign n_1555 = ~x_75 & x_76; assign n_1556 = x_75 & ~x_76; assign n_1557 = ~n_1555 & ~n_1556; assign n_1558 = ~x_74 & x_75; assign n_1559 = x_74 & ~x_75; assign n_1560 = ~n_1558 & ~n_1559; assign n_1561 = ~x_70 & x_74; assign n_1562 = x_70 & ~x_74; assign n_1563 = ~n_1561 & ~n_1562; assign n_1564 = ~x_72 & x_73; assign n_1565 = x_72 & ~x_73; assign n_1566 = ~n_1564 & ~n_1565; assign n_1567 = x_72 & ~x_119; assign n_1568 = ~x_72 & x_119; assign n_1569 = ~n_1567 & ~n_1568; assign n_1570 = ~x_69 & x_70; assign n_1571 = x_69 & ~x_70; assign n_1572 = ~n_1570 & ~n_1571; assign n_1573 = ~x_68 & x_69; assign n_1574 = x_68 & ~x_69; assign n_1575 = ~n_1573 & ~n_1574; assign n_1576 = x_68 & ~x_71; assign n_1577 = ~x_68 & x_71; assign n_1578 = ~n_1576 & ~n_1577; assign n_1579 = x_67 & ~x_116; assign n_1580 = ~x_67 & x_116; assign n_1581 = ~n_1579 & ~n_1580; assign n_1582 = x_66 & ~x_113; assign n_1583 = ~x_66 & x_113; assign n_1584 = ~n_1582 & ~n_1583; assign n_1585 = x_65 & ~x_112; assign n_1586 = ~x_65 & x_112; assign n_1587 = ~n_1585 & ~n_1586; assign n_1588 = x_64 & ~x_111; assign n_1589 = ~x_64 & x_111; assign n_1590 = ~n_1588 & ~n_1589; assign n_1591 = x_63 & ~x_110; assign n_1592 = ~x_63 & x_110; assign n_1593 = ~n_1591 & ~n_1592; assign n_1594 = x_62 & ~x_109; assign n_1595 = ~x_62 & x_109; assign n_1596 = ~n_1594 & ~n_1595; assign n_1597 = x_61 & ~x_108; assign n_1598 = ~x_61 & x_108; assign n_1599 = ~n_1597 & ~n_1598; assign n_1600 = x_60 & ~x_104; assign n_1601 = ~x_60 & x_104; assign n_1602 = ~n_1600 & ~n_1601; assign n_1603 = x_59 & ~x_107; assign n_1604 = ~x_59 & x_107; assign n_1605 = ~n_1603 & ~n_1604; assign n_1606 = x_58 & ~x_105; assign n_1607 = ~x_58 & x_105; assign n_1608 = ~n_1606 & ~n_1607; assign n_1609 = x_57 & ~x_103; assign n_1610 = ~x_57 & x_103; assign n_1611 = ~n_1609 & ~n_1610; assign n_1612 = x_56 & ~x_102; assign n_1613 = ~x_56 & x_102; assign n_1614 = ~n_1612 & ~n_1613; assign n_1615 = x_55 & ~x_100; assign n_1616 = ~x_55 & x_100; assign n_1617 = ~n_1615 & ~n_1616; assign n_1618 = x_54 & ~x_99; assign n_1619 = ~x_54 & x_99; assign n_1620 = ~n_1618 & ~n_1619; assign n_1621 = x_53 & ~x_98; assign n_1622 = ~x_53 & x_98; assign n_1623 = ~n_1621 & ~n_1622; assign n_1624 = x_52 & ~x_94; assign n_1625 = ~x_52 & x_94; assign n_1626 = ~n_1624 & ~n_1625; assign n_1627 = x_51 & ~x_93; assign n_1628 = ~x_51 & x_93; assign n_1629 = ~n_1627 & ~n_1628; assign n_1630 = x_50 & ~x_92; assign n_1631 = ~x_50 & x_92; assign n_1632 = ~n_1630 & ~n_1631; assign n_1633 = x_49 & ~x_91; assign n_1634 = ~x_49 & x_91; assign n_1635 = ~n_1633 & ~n_1634; assign n_1636 = x_48 & ~x_90; assign n_1637 = ~x_48 & x_90; assign n_1638 = ~n_1636 & ~n_1637; assign n_1639 = ~x_46 & x_47; assign n_1640 = x_46 & ~x_47; assign n_1641 = ~n_1639 & ~n_1640; assign n_1642 = x_46 & ~x_81; assign n_1643 = ~x_46 & x_81; assign n_1644 = ~n_1642 & ~n_1643; assign n_1645 = x_45 & ~x_80; assign n_1646 = ~x_45 & x_80; assign n_1647 = ~n_1645 & ~n_1646; assign n_1648 = ~i_9 & x_44; assign n_1649 = i_9 & ~x_44; assign n_1650 = ~n_1648 & ~n_1649; assign n_1651 = ~i_7 & x_42; assign n_1652 = i_7 & ~x_42; assign n_1653 = ~n_1651 & ~n_1652; assign n_1654 = ~i_8 & x_43; assign n_1655 = i_8 & ~x_43; assign n_1656 = ~n_1654 & ~n_1655; assign n_1657 = ~n_1653 & ~n_1656; assign n_1658 = ~n_1650 & n_1657; assign n_1659 = ~n_1647 & n_1658; assign n_1660 = ~n_1644 & n_1659; assign n_1661 = ~n_1641 & n_1660; assign n_1662 = ~n_1638 & n_1661; assign n_1663 = ~n_1635 & n_1662; assign n_1664 = ~n_1632 & n_1663; assign n_1665 = ~n_1629 & n_1664; assign n_1666 = ~n_1626 & n_1665; assign n_1667 = ~n_1623 & n_1666; assign n_1668 = ~n_1620 & n_1667; assign n_1669 = ~n_1617 & n_1668; assign n_1670 = ~n_1614 & n_1669; assign n_1671 = ~n_1611 & n_1670; assign n_1672 = ~n_1608 & n_1671; assign n_1673 = ~n_1605 & n_1672; assign n_1674 = ~n_1602 & n_1673; assign n_1675 = ~n_1599 & n_1674; assign n_1676 = ~n_1596 & n_1675; assign n_1677 = ~n_1593 & n_1676; assign n_1678 = ~n_1590 & n_1677; assign n_1679 = ~n_1587 & n_1678; assign n_1680 = ~n_1584 & n_1679; assign n_1681 = ~n_1581 & n_1680; assign n_1682 = ~n_1578 & n_1681; assign n_1683 = ~n_1575 & n_1682; assign n_1684 = ~n_1572 & n_1683; assign n_1685 = ~n_1569 & n_1684; assign n_1686 = ~n_1566 & n_1685; assign n_1687 = ~n_1563 & n_1686; assign n_1688 = ~n_1560 & n_1687; assign n_1689 = ~n_1557 & n_1688; assign n_1690 = ~n_1554 & n_1689; assign n_1691 = ~n_1551 & n_1690; assign n_1692 = ~n_1548 & n_1691; assign n_1693 = ~n_1545 & n_1692; assign n_1694 = ~n_1542 & n_1693; assign n_1695 = ~n_1538 & n_1694; assign n_1696 = ~n_1535 & n_1695; assign n_1697 = ~n_1532 & n_1696; assign n_1698 = ~n_1529 & n_1697; assign n_1699 = ~n_1526 & n_1698; assign n_1700 = ~n_1523 & n_1699; assign n_1701 = ~n_1520 & n_1700; assign n_1702 = ~n_1517 & n_1701; assign n_1703 = ~n_1514 & n_1702; assign n_1704 = ~n_1505 & n_1703; assign n_1705 = ~n_1497 & n_1704; assign n_1706 = ~n_1487 & n_1705; assign n_1707 = ~n_1475 & n_1706; assign n_1708 = ~n_1463 & n_1707; assign n_1709 = ~n_1457 & n_1708; assign n_1710 = ~n_1451 & n_1709; assign n_1711 = ~n_1445 & n_1710; assign n_1712 = ~n_1435 & n_1711; assign n_1713 = ~n_1421 & n_1712; assign n_1714 = ~n_1411 & n_1713; assign n_1715 = ~n_1405 & n_1714; assign n_1716 = ~n_1395 & n_1715; assign n_1717 = ~n_1375 & n_1716; assign n_1718 = ~n_1372 & n_1717; assign n_1719 = ~n_1368 & n_1718; assign n_1720 = ~n_1364 & n_1719; assign n_1721 = ~n_1358 & n_1720; assign n_1722 = ~n_1350 & n_1721; assign n_1723 = ~n_1347 & n_1722; assign n_1724 = ~n_1343 & n_1723; assign n_1725 = ~n_1338 & n_1724; assign n_1726 = ~n_1330 & n_1725; assign n_1727 = ~n_1324 & n_1726; assign n_1728 = ~n_1313 & n_1727; assign n_1729 = ~n_1309 & n_1728; assign n_1730 = ~n_1293 & n_1729; assign n_1731 = ~n_1287 & n_1730; assign n_1732 = ~n_1280 & n_1731; assign n_1733 = ~n_1265 & n_1732; assign n_1734 = ~n_1259 & n_1733; assign n_1735 = ~n_1243 & n_1734; assign n_1736 = ~n_1240 & n_1735; assign n_1737 = ~n_1213 & n_1736; assign n_1738 = ~n_1204 & n_1737; assign n_1739 = ~n_1196 & n_1738; assign n_1740 = ~n_1186 & n_1739; assign n_1741 = ~n_1174 & n_1740; assign n_1742 = ~n_1160 & n_1741; assign n_1743 = ~n_1139 & n_1742; assign n_1744 = ~n_1133 & n_1743; assign n_1745 = ~n_1127 & n_1744; assign n_1746 = ~n_1121 & n_1745; assign n_1747 = ~n_1111 & n_1746; assign n_1748 = ~n_1097 & n_1747; assign n_1749 = ~n_1087 & n_1748; assign n_1750 = ~n_1081 & n_1749; assign n_1751 = ~n_1071 & n_1750; assign n_1752 = ~n_1052 & n_1751; assign n_1753 = ~n_1025 & n_1752; assign n_1754 = ~n_1019 & n_1753; assign n_1755 = ~n_1015 & n_1754; assign n_1756 = ~n_1006 & n_1755; assign n_1757 = ~n_1003 & n_1756; assign n_1758 = ~n_995 & n_1757; assign n_1759 = ~n_992 & n_1758; assign n_1760 = ~n_988 & n_1759; assign n_1761 = ~n_982 & n_1760; assign n_1762 = ~n_976 & n_1761; assign n_1763 = ~n_969 & n_1762; assign n_1764 = ~n_966 & n_1763; assign n_1765 = ~n_961 & n_1764; assign n_1766 = ~n_956 & n_1765; assign n_1767 = ~n_953 & n_1766; assign n_1768 = ~n_948 & n_1767; assign n_1769 = ~n_943 & n_1768; assign n_1770 = ~n_938 & n_1769; assign n_1771 = ~n_933 & n_1770; assign n_1772 = ~n_928 & n_1771; assign n_1773 = ~n_923 & n_1772; assign n_1774 = ~n_918 & n_1773; assign n_1775 = ~n_913 & n_1774; assign n_1776 = ~n_903 & n_1775; assign n_1777 = ~n_876 & n_1776; assign n_1778 = ~n_872 & n_1777; assign n_1779 = ~n_868 & n_1778; assign n_1780 = ~n_864 & n_1779; assign n_1781 = ~n_860 & n_1780; assign n_1782 = ~n_856 & n_1781; assign n_1783 = ~n_852 & n_1782; assign n_1784 = ~n_848 & n_1783; assign n_1785 = ~n_844 & n_1784; assign n_1786 = ~n_825 & n_1785; assign n_1787 = ~n_798 & n_1786; assign n_1788 = ~n_788 & n_1787; assign n_1789 = ~n_778 & n_1788; assign n_1790 = ~n_760 & n_1789; assign n_1791 = ~n_752 & n_1790; assign n_1792 = ~n_749 & n_1791; assign n_1793 = ~n_744 & n_1792; assign n_1794 = ~n_738 & n_1793; assign n_1795 = ~n_726 & n_1794; assign n_1796 = ~n_712 & n_1795; assign n_1797 = ~n_696 & n_1796; assign n_1798 = ~n_693 & n_1797; assign n_1799 = ~n_690 & n_1798; assign n_1800 = ~n_687 & n_1799; assign n_1801 = ~n_684 & n_1800; assign n_1802 = ~n_681 & n_1801; assign n_1803 = ~n_678 & n_1802; assign n_1804 = ~n_675 & n_1803; assign n_1805 = ~n_672 & n_1804; assign n_1806 = ~n_669 & n_1805; assign n_1807 = ~n_666 & n_1806; assign n_1808 = ~n_663 & n_1807; assign n_1809 = ~n_660 & n_1808; assign n_1810 = ~n_657 & n_1809; assign n_1811 = ~n_653 & n_1810; assign n_1812 = ~n_649 & n_1811; assign n_1813 = ~n_644 & n_1812; assign n_1814 = ~n_641 & n_1813; assign n_1815 = ~n_638 & n_1814; assign n_1816 = ~n_633 & n_1815; assign n_1817 = ~n_630 & n_1816; assign n_1818 = ~n_627 & n_1817; assign n_1819 = ~n_624 & n_1818; assign n_1820 = ~n_621 & n_1819; assign n_1821 = ~n_618 & n_1820; assign n_1822 = ~n_613 & n_1821; assign n_1823 = ~n_590 & n_1822; assign n_1824 = ~n_587 & n_1823; assign n_1825 = ~n_584 & n_1824; assign n_1826 = ~n_581 & n_1825; assign n_1827 = ~n_576 & n_1826; assign n_1828 = ~n_570 & n_1827; assign n_1829 = ~n_567 & n_1828; assign n_1830 = ~n_560 & n_1829; assign n_1831 = ~n_557 & n_1830; assign n_1832 = ~n_554 & n_1831; assign n_1833 = ~n_551 & n_1832; assign n_1834 = ~n_532 & n_1833; assign n_1835 = ~n_529 & n_1834; assign n_1836 = ~n_526 & n_1835; assign n_1837 = ~n_514 & n_1836; assign n_1838 = ~n_500 & n_1837; assign n_1839 = ~n_495 & n_1838; assign n_1840 = ~n_492 & n_1839; assign n_1841 = ~n_487 & n_1840; assign n_1842 = ~n_484 & n_1841; assign n_1843 = ~n_481 & n_1842; assign n_1844 = ~n_478 & n_1843; assign n_1845 = ~n_475 & n_1844; assign n_1846 = ~n_472 & n_1845; assign n_1847 = ~n_469 & n_1846; assign n_1848 = ~n_466 & n_1847; assign n_1849 = ~n_463 & n_1848; assign n_1850 = ~n_460 & n_1849; assign n_1851 = ~n_457 & n_1850; assign n_1852 = ~n_454 & n_1851; assign n_1853 = ~n_451 & n_1852; assign n_1854 = ~n_448 & n_1853; assign n_1855 = ~n_445 & n_1854; assign n_1856 = ~n_442 & n_1855; assign n_1857 = ~n_439 & n_1856; assign n_1858 = ~n_436 & n_1857; assign n_1859 = ~n_433 & n_1858; assign n_1860 = ~n_430 & n_1859; assign n_1861 = ~n_427 & n_1860; assign n_1862 = ~n_424 & n_1861; assign n_1863 = ~n_413 & n_1862; assign n_1864 = ~n_401 & n_1863; assign n_1865 = ~n_397 & n_1864; assign n_1866 = ~n_393 & n_1865; assign n_1867 = ~n_390 & n_1866; assign n_1868 = ~n_382 & n_1867; assign n_1869 = ~n_342 & n_1868; assign n_1870 = ~n_337 & n_1869; assign n_1871 = ~n_330 & n_1870; assign n_1872 = ~n_318 & n_1871; assign n_1873 = ~n_310 & n_1872; assign n_1874 = ~n_307 & n_1873; assign n_1875 = ~n_304 & n_1874; assign n_1876 = ~n_301 & n_1875; assign n_1877 = ~n_298 & n_1876; assign n_1878 = ~n_295 & n_1877; assign n_1879 = x_71 & n_1878; assign n_1880 = ~n_292 & n_1879; assign n_1881 = ~n_283 & n_1880; assign n_1882 = ~n_271 & n_1881; assign n_1883 = ~n_252 & n_1882; assign n_1884 = ~n_245 & n_1883; assign n_1885 = ~n_151 & n_1884; assign n_1886 = ~n_145 & n_1885; assign n_1887 = ~n_142 & n_1886; assign n_1888 = ~n_139 & n_1887; assign n_1889 = ~n_136 & n_1888; assign n_1890 = ~n_133 & n_1889; assign n_1891 = ~n_112 & n_1890; assign n_1892 = ~n_109 & n_1891; assign n_1893 = ~n_106 & n_1892; assign n_1894 = ~n_103 & n_1893; assign n_1895 = ~n_100 & n_1894; assign n_1896 = ~n_97 & n_1895; assign n_1897 = ~n_94 & n_1896; assign n_1898 = ~n_88 & n_1897; assign n_1899 = ~n_85 & n_1898; assign n_1900 = ~n_81 & n_1899; assign n_1901 = ~n_78 & n_1900; assign n_1902 = ~n_75 & n_1901; assign n_1903 = ~n_48 & n_1902; assign n_1904 = ~n_42 & n_1903; assign n_1905 = ~n_36 & n_1904; assign n_1906 = ~n_30 & n_1905; assign n_1907 = ~n_24 & n_1906; assign n_1908 = ~n_18 & n_1907; assign n_1909 = ~n_12 & n_1908; assign n_1910 = ~n_6 & n_1909; assign n_1911 = ~x_249 & n_1910; assign o_1 = ~n_1911; endmodule
module bobsm5378d2_all_bit_differing_from_cycle ( i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9, i_10, i_11, i_12, i_13, i_14, i_15, i_16, i_17, i_18, i_19, i_20, i_21, i_22, i_23, i_24, i_25, i_26, i_27, i_28, i_29, i_30, i_31, i_32, i_33, i_34, i_35, x_36, x_37, x_38, x_39, x_40, x_41, x_42, x_43, x_44, x_45, x_46, x_47, x_48, x_49, x_50, x_51, x_52, x_53, x_54, x_55, x_56, x_57, x_58, x_59, x_60, x_61, x_62, x_63, x_64, x_65, x_66, x_67, x_68, x_69, x_70, x_71, x_72, x_73, x_74, x_75, x_76, x_77, x_78, x_79, x_80, x_81, x_82, x_83, x_84, x_85, x_86, x_87, x_88, x_89, x_90, x_91, x_92, x_93, x_94, x_95, x_96, x_97, x_98, x_99, x_100, x_101, x_102, x_103, x_104, x_105, x_106, x_107, x_108, x_109, x_110, x_111, x_112, x_113, x_114, x_115, x_116, x_117, x_118, x_119, x_120, x_121, x_122, x_123, x_124, x_125, x_126, x_127, x_128, x_129, x_130, x_131, x_132, x_133, x_134, x_135, x_136, x_137, x_138, x_139, x_140, x_141, x_142, x_143, x_144, x_145, x_146, x_147, x_148, x_149, x_150, x_151, x_152, x_153, x_154, x_155, x_156, x_157, x_158, x_159, x_160, x_161, x_162, x_163, x_164, x_165, x_166, x_167, x_168, x_169, x_170, x_171, x_172, x_173, x_174, x_175, x_176, x_177, x_178, x_179, x_180, x_181, x_182, x_183, x_184, x_185, x_186, x_187, x_188, x_189, x_190, x_191, x_192, x_193, x_194, x_195, x_196, x_197, x_198, x_199, x_200, x_201, x_202, x_203, x_204, x_205, x_206, x_207, x_208, x_209, x_210, x_211, x_212, x_213, x_214, x_215, x_216, x_217, x_218, x_219, x_220, x_221, x_222, x_223, x_224, x_225, x_226, x_227, x_228, x_229, x_230, x_231, x_232, x_233, x_234, x_235, x_236, x_237, x_238, x_239, x_240, x_241, x_242, x_243, x_244, x_245, x_246, x_247, x_248, x_249, x_250, x_251, x_252, x_253, x_254, x_255, x_256, x_257, x_258, x_259, x_260, x_261, x_262, x_263, x_264, x_265, x_266, x_267, x_268, x_269, x_270, x_271, x_272, x_273, x_274, x_275, x_276, x_277, x_278, x_279, x_280, x_281, x_282, x_283, x_284, x_285, x_286, x_287, x_288, x_289, x_290, x_291, x_292, x_293, x_294, x_295, x_296, x_297, x_298, x_299, x_300, x_301, x_302, x_303, x_304, x_305, x_306, x_307, x_308, x_309, x_310, x_311, x_312, x_313, x_314, x_315, x_316, x_317, x_318, x_319, x_320, x_321, x_322, x_323, x_324, x_325, x_326, x_327, x_328, x_329, x_330, x_331, x_332, x_333, x_334, x_335, x_336, x_337, x_338, x_339, x_340, x_341, x_342, x_343, x_344, x_345, x_346, x_347, x_348, x_349, x_350, x_351, x_352, x_353, x_354, x_355, x_356, x_357, x_358, x_359, x_360, x_361, x_362, x_363, x_364, x_365, x_366, x_367, x_368, x_369, x_370, x_371, x_372, x_373, x_374, x_375, x_376, x_377, x_378, x_379, x_380, x_381, x_382, x_383, x_384, x_385, x_386, x_387, x_388, x_389, x_390, x_391, x_392, x_393, x_394, x_395, x_396, x_397, x_398, x_399, x_400, x_401, x_402, x_403, x_404, x_405, x_406, x_407, x_408, x_409, x_410, x_411, x_412, x_413, x_414, x_415, x_416, x_417, x_418, x_419, x_420, x_421, x_422, x_423, x_424, x_425, x_426, x_427, x_428, x_429, x_430, x_431, x_432, x_433, x_434, x_435, x_436, x_437, x_438, x_439, x_440, x_441, x_442, x_443, x_444, x_445, x_446, x_447, x_448, x_449, x_450, x_451, x_452, x_453, x_454, x_455, x_456, x_457, x_458, x_459, x_460, x_461, x_462, x_463, x_464, x_465, x_466, x_467, x_468, x_469, x_470, x_471, x_472, x_473, x_474, x_475, x_476, x_477, x_478, x_479, x_480, x_481, x_482, x_483, x_484, x_485, x_486, x_487, x_488, x_489, x_490, x_491, x_492, x_493, x_494, x_495, x_496, x_497, x_498, x_499, x_500, x_501, x_502, x_503, x_504, x_505, x_506, x_507, x_508, x_509, x_510, x_511, x_512, x_513, x_514, x_515, x_516, x_517, x_518, x_519, x_520, x_521, x_522, x_523, x_524, x_525, x_526, x_527, x_528, x_529, x_530, x_531, x_532, x_533, x_534, x_535, x_536, x_537, x_538, x_539, x_540, x_541, x_542, x_543, x_544, x_545, x_546, x_547, o_1 );
input i_1; input i_2; input i_3; input i_4; input i_5; input i_6; input i_7; input i_8; input i_9; input i_10; input i_11; input i_12; input i_13; input i_14; input i_15; input i_16; input i_17; input i_18; input i_19; input i_20; input i_21; input i_22; input i_23; input i_24; input i_25; input i_26; input i_27; input i_28; input i_29; input i_30; input i_31; input i_32; input i_33; input i_34; input i_35; input x_36; input x_37; input x_38; input x_39; input x_40; input x_41; input x_42; input x_43; input x_44; input x_45; input x_46; input x_47; input x_48; input x_49; input x_50; input x_51; input x_52; input x_53; input x_54; input x_55; input x_56; input x_57; input x_58; input x_59; input x_60; input x_61; input x_62; input x_63; input x_64; input x_65; input x_66; input x_67; input x_68; input x_69; input x_70; input x_71; input x_72; input x_73; input x_74; input x_75; input x_76; input x_77; input x_78; input x_79; input x_80; input x_81; input x_82; input x_83; input x_84; input x_85; input x_86; input x_87; input x_88; input x_89; input x_90; input x_91; input x_92; input x_93; input x_94; input x_95; input x_96; input x_97; input x_98; input x_99; input x_100; input x_101; input x_102; input x_103; input x_104; input x_105; input x_106; input x_107; input x_108; input x_109; input x_110; input x_111; input x_112; input x_113; input x_114; input x_115; input x_116; input x_117; input x_118; input x_119; input x_120; input x_121; input x_122; input x_123; input x_124; input x_125; input x_126; input x_127; input x_128; input x_129; input x_130; input x_131; input x_132; input x_133; input x_134; input x_135; input x_136; input x_137; input x_138; input x_139; input x_140; input x_141; input x_142; input x_143; input x_144; input x_145; input x_146; input x_147; input x_148; input x_149; input x_150; input x_151; input x_152; input x_153; input x_154; input x_155; input x_156; input x_157; input x_158; input x_159; input x_160; input x_161; input x_162; input x_163; input x_164; input x_165; input x_166; input x_167; input x_168; input x_169; input x_170; input x_171; input x_172; input x_173; input x_174; input x_175; input x_176; input x_177; input x_178; input x_179; input x_180; input x_181; input x_182; input x_183; input x_184; input x_185; input x_186; input x_187; input x_188; input x_189; input x_190; input x_191; input x_192; input x_193; input x_194; input x_195; input x_196; input x_197; input x_198; input x_199; input x_200; input x_201; input x_202; input x_203; input x_204; input x_205; input x_206; input x_207; input x_208; input x_209; input x_210; input x_211; input x_212; input x_213; input x_214; input x_215; input x_216; input x_217; input x_218; input x_219; input x_220; input x_221; input x_222; input x_223; input x_224; input x_225; input x_226; input x_227; input x_228; input x_229; input x_230; input x_231; input x_232; input x_233; input x_234; input x_235; input x_236; input x_237; input x_238; input x_239; input x_240; input x_241; input x_242; input x_243; input x_244; input x_245; input x_246; input x_247; input x_248; input x_249; input x_250; input x_251; input x_252; input x_253; input x_254; input x_255; input x_256; input x_257; input x_258; input x_259; input x_260; input x_261; input x_262; input x_263; input x_264; input x_265; input x_266; input x_267; input x_268; input x_269; input x_270; input x_271; input x_272; input x_273; input x_274; input x_275; input x_276; input x_277; input x_278; input x_279; input x_280; input x_281; input x_282; input x_283; input x_284; input x_285; input x_286; input x_287; input x_288; input x_289; input x_290; input x_291; input x_292; input x_293; input x_294; input x_295; input x_296; input x_297; input x_298; input x_299; input x_300; input x_301; input x_302; input x_303; input x_304; input x_305; input x_306; input x_307; input x_308; input x_309; input x_310; input x_311; input x_312; input x_313; input x_314; input x_315; input x_316; input x_317; input x_318; input x_319; input x_320; input x_321; input x_322; input x_323; input x_324; input x_325; input x_326; input x_327; input x_328; input x_329; input x_330; input x_331; input x_332; input x_333; input x_334; input x_335; input x_336; input x_337; input x_338; input x_339; input x_340; input x_341; input x_342; input x_343; input x_344; input x_345; input x_346; input x_347; input x_348; input x_349; input x_350; input x_351; input x_352; input x_353; input x_354; input x_355; input x_356; input x_357; input x_358; input x_359; input x_360; input x_361; input x_362; input x_363; input x_364; input x_365; input x_366; input x_367; input x_368; input x_369; input x_370; input x_371; input x_372; input x_373; input x_374; input x_375; input x_376; input x_377; input x_378; input x_379; input x_380; input x_381; input x_382; input x_383; input x_384; input x_385; input x_386; input x_387; input x_388; input x_389; input x_390; input x_391; input x_392; input x_393; input x_394; input x_395; input x_396; input x_397; input x_398; input x_399; input x_400; input x_401; input x_402; input x_403; input x_404; input x_405; input x_406; input x_407; input x_408; input x_409; input x_410; input x_411; input x_412; input x_413; input x_414; input x_415; input x_416; input x_417; input x_418; input x_419; input x_420; input x_421; input x_422; input x_423; input x_424; input x_425; input x_426; input x_427; input x_428; input x_429; input x_430; input x_431; input x_432; input x_433; input x_434; input x_435; input x_436; input x_437; input x_438; input x_439; input x_440; input x_441; input x_442; input x_443; input x_444; input x_445; input x_446; input x_447; input x_448; input x_449; input x_450; input x_451; input x_452; input x_453; input x_454; input x_455; input x_456; input x_457; input x_458; input x_459; input x_460; input x_461; input x_462; input x_463; input x_464; input x_465; input x_466; input x_467; input x_468; input x_469; input x_470; input x_471; input x_472; input x_473; input x_474; input x_475; input x_476; input x_477; input x_478; input x_479; input x_480; input x_481; input x_482; input x_483; input x_484; input x_485; input x_486; input x_487; input x_488; input x_489; input x_490; input x_491; input x_492; input x_493; input x_494; input x_495; input x_496; input x_497; input x_498; input x_499; input x_500; input x_501; input x_502; input x_503; input x_504; input x_505; input x_506; input x_507; input x_508; input x_509; input x_510; input x_511; input x_512; input x_513; input x_514; input x_515; input x_516; input x_517; input x_518; input x_519; input x_520; input x_521; input x_522; input x_523; input x_524; input x_525; input x_526; input x_527; input x_528; input x_529; input x_530; input x_531; input x_532; input x_533; input x_534; input x_535; input x_536; input x_537; input x_538; input x_539; input x_540; input x_541; input x_542; input x_543; input x_544; input x_545; input x_546; input x_547; output o_1; wire n_1; wire n_2; wire n_3; wire n_4; wire n_5; wire n_6; wire n_7; wire n_8; wire n_9; wire n_10; wire n_11; wire n_12; wire n_13; wire n_14; wire n_15; wire n_16; wire n_17; wire n_18; wire n_19; wire n_20; wire n_21; wire n_22; wire n_23; wire n_24; wire n_25; wire n_26; wire n_27; wire n_28; wire n_29; wire n_30; wire n_31; wire n_32; wire n_33; wire n_34; wire n_35; wire n_36; wire n_37; wire n_38; wire n_39; wire n_40; wire n_41; wire n_42; wire n_43; wire n_44; wire n_45; wire n_46; wire n_47; wire n_48; wire n_49; wire n_50; wire n_51; wire n_52; wire n_53; wire n_54; wire n_55; wire n_56; wire n_57; wire n_58; wire n_59; wire n_60; wire n_61; wire n_62; wire n_63; wire n_64; wire n_65; wire n_66; wire n_67; wire n_68; wire n_69; wire n_70; wire n_71; wire n_72; wire n_73; wire n_74; wire n_75; wire n_76; wire n_77; wire n_78; wire n_79; wire n_80; wire n_81; wire n_82; wire n_83; wire n_84; wire n_85; wire n_86; wire n_87; wire n_88; wire n_89; wire n_90; wire n_91; wire n_92; wire n_93; wire n_94; wire n_95; wire n_96; wire n_97; wire n_98; wire n_99; wire n_100; wire n_101; wire n_102; wire n_103; wire n_104; wire n_105; wire n_106; wire n_107; wire n_108; wire n_109; wire n_110; wire n_111; wire n_112; wire n_113; wire n_114; wire n_115; wire n_116; wire n_117; wire n_118; wire n_119; wire n_120; wire n_121; wire n_122; wire n_123; wire n_124; wire n_125; wire n_126; wire n_127; wire n_128; wire n_129; wire n_130; wire n_131; wire n_132; wire n_133; wire n_134; wire n_135; wire n_136; wire n_137; wire n_138; wire n_139; wire n_140; wire n_141; wire n_142; wire n_143; wire n_144; wire n_145; wire n_146; wire n_147; wire n_148; wire n_149; wire n_150; wire n_151; wire n_152; wire n_153; wire n_154; wire n_155; wire n_156; wire n_157; wire n_158; wire n_159; wire n_160; wire n_161; wire n_162; wire n_163; wire n_164; wire n_165; wire n_166; wire n_167; wire n_168; wire n_169; wire n_170; wire n_171; wire n_172; wire n_173; wire n_174; wire n_175; wire n_176; wire n_177; wire n_178; wire n_179; wire n_180; wire n_181; wire n_182; wire n_183; wire n_184; wire n_185; wire n_186; wire n_187; wire n_188; wire n_189; wire n_190; wire n_191; wire n_192; wire n_193; wire n_194; wire n_195; wire n_196; wire n_197; wire n_198; wire n_199; wire n_200; wire n_201; wire n_202; wire n_203; wire n_204; wire n_205; wire n_206; wire n_207; wire n_208; wire n_209; wire n_210; wire n_211; wire n_212; wire n_213; wire n_214; wire n_215; wire n_216; wire n_217; wire n_218; wire n_219; wire n_220; wire n_221; wire n_222; wire n_223; wire n_224; wire n_225; wire n_226; wire n_227; wire n_228; wire n_229; wire n_230; wire n_231; wire n_232; wire n_233; wire n_234; wire n_235; wire n_236; wire n_237; wire n_238; wire n_239; wire n_240; wire n_241; wire n_242; wire n_243; wire n_244; wire n_245; wire n_246; wire n_247; wire n_248; wire n_249; wire n_250; wire n_251; wire n_252; wire n_253; wire n_254; wire n_255; wire n_256; wire n_257; wire n_258; wire n_259; wire n_260; wire n_261; wire n_262; wire n_263; wire n_264; wire n_265; wire n_266; wire n_267; wire n_268; wire n_269; wire n_270; wire n_271; wire n_272; wire n_273; wire n_274; wire n_275; wire n_276; wire n_277; wire n_278; wire n_279; wire n_280; wire n_281; wire n_282; wire n_283; wire n_284; wire n_285; wire n_286; wire n_287; wire n_288; wire n_289; wire n_290; wire n_291; wire n_292; wire n_293; wire n_294; wire n_295; wire n_296; wire n_297; wire n_298; wire n_299; wire n_300; wire n_301; wire n_302; wire n_303; wire n_304; wire n_305; wire n_306; wire n_307; wire n_308; wire n_309; wire n_310; wire n_311; wire n_312; wire n_313; wire n_314; wire n_315; wire n_316; wire n_317; wire n_318; wire n_319; wire n_320; wire n_321; wire n_322; wire n_323; wire n_324; wire n_325; wire n_326; wire n_327; wire n_328; wire n_329; wire n_330; wire n_331; wire n_332; wire n_333; wire n_334; wire n_335; wire n_336; wire n_337; wire n_338; wire n_339; wire n_340; wire n_341; wire n_342; wire n_343; wire n_344; wire n_345; wire n_346; wire n_347; wire n_348; wire n_349; wire n_350; wire n_351; wire n_352; wire n_353; wire n_354; wire n_355; wire n_356; wire n_357; wire n_358; wire n_359; wire n_360; wire n_361; wire n_362; wire n_363; wire n_364; wire n_365; wire n_366; wire n_367; wire n_368; wire n_369; wire n_370; wire n_371; wire n_372; wire n_373; wire n_374; wire n_375; wire n_376; wire n_377; wire n_378; wire n_379; wire n_380; wire n_381; wire n_382; wire n_383; wire n_384; wire n_385; wire n_386; wire n_387; wire n_388; wire n_389; wire n_390; wire n_391; wire n_392; wire n_393; wire n_394; wire n_395; wire n_396; wire n_397; wire n_398; wire n_399; wire n_400; wire n_401; wire n_402; wire n_403; wire n_404; wire n_405; wire n_406; wire n_407; wire n_408; wire n_409; wire n_410; wire n_411; wire n_412; wire n_413; wire n_414; wire n_415; wire n_416; wire n_417; wire n_418; wire n_419; wire n_420; wire n_421; wire n_422; wire n_423; wire n_424; wire n_425; wire n_426; wire n_427; wire n_428; wire n_429; wire n_430; wire n_431; wire n_432; wire n_433; wire n_434; wire n_435; wire n_436; wire n_437; wire n_438; wire n_439; wire n_440; wire n_441; wire n_442; wire n_443; wire n_444; wire n_445; wire n_446; wire n_447; wire n_448; wire n_449; wire n_450; wire n_451; wire n_452; wire n_453; wire n_454; wire n_455; wire n_456; wire n_457; wire n_458; wire n_459; wire n_460; wire n_461; wire n_462; wire n_463; wire n_464; wire n_465; wire n_466; wire n_467; wire n_468; wire n_469; wire n_470; wire n_471; wire n_472; wire n_473; wire n_474; wire n_475; wire n_476; wire n_477; wire n_478; wire n_479; wire n_480; wire n_481; wire n_482; wire n_483; wire n_484; wire n_485; wire n_486; wire n_487; wire n_488; wire n_489; wire n_490; wire n_491; wire n_492; wire n_493; wire n_494; wire n_495; wire n_496; wire n_497; wire n_498; wire n_499; wire n_500; wire n_501; wire n_502; wire n_503; wire n_504; wire n_505; wire n_506; wire n_507; wire n_508; wire n_509; wire n_510; wire n_511; wire n_512; wire n_513; wire n_514; wire n_515; wire n_516; wire n_517; wire n_518; wire n_519; wire n_520; wire n_521; wire n_522; wire n_523; wire n_524; wire n_525; wire n_526; wire n_527; wire n_528; wire n_529; wire n_530; wire n_531; wire n_532; wire n_533; wire n_534; wire n_535; wire n_536; wire n_537; wire n_538; wire n_539; wire n_540; wire n_541; wire n_542; wire n_543; wire n_544; wire n_545; wire n_546; wire n_547; wire n_548; wire n_549; wire n_550; wire n_551; wire n_552; wire n_553; wire n_554; wire n_555; wire n_556; wire n_557; wire n_558; wire n_559; wire n_560; wire n_561; wire n_562; wire n_563; wire n_564; wire n_565; wire n_566; wire n_567; wire n_568; wire n_569; wire n_570; wire n_571; wire n_572; wire n_573; wire n_574; wire n_575; wire n_576; wire n_577; wire n_578; wire n_579; wire n_580; wire n_581; wire n_582; wire n_583; wire n_584; wire n_585; wire n_586; wire n_587; wire n_588; wire n_589; wire n_590; wire n_591; wire n_592; wire n_593; wire n_594; wire n_595; wire n_596; wire n_597; wire n_598; wire n_599; wire n_600; wire n_601; wire n_602; wire n_603; wire n_604; wire n_605; wire n_606; wire n_607; wire n_608; wire n_609; wire n_610; wire n_611; wire n_612; wire n_613; wire n_614; wire n_615; wire n_616; wire n_617; wire n_618; wire n_619; wire n_620; wire n_621; wire n_622; wire n_623; wire n_624; wire n_625; wire n_626; wire n_627; wire n_628; wire n_629; wire n_630; wire n_631; wire n_632; wire n_633; wire n_634; wire n_635; wire n_636; wire n_637; wire n_638; wire n_639; wire n_640; wire n_641; wire n_642; wire n_643; wire n_644; wire n_645; wire n_646; wire n_647; wire n_648; wire n_649; wire n_650; wire n_651; wire n_652; wire n_653; wire n_654; wire n_655; wire n_656; wire n_657; wire n_658; wire n_659; wire n_660; wire n_661; wire n_662; wire n_663; wire n_664; wire n_665; wire n_666; wire n_667; wire n_668; wire n_669; wire n_670; wire n_671; wire n_672; wire n_673; wire n_674; wire n_675; wire n_676; wire n_677; wire n_678; wire n_679; wire n_680; wire n_681; wire n_682; wire n_683; wire n_684; wire n_685; wire n_686; wire n_687; wire n_688; wire n_689; wire n_690; wire n_691; wire n_692; wire n_693; wire n_694; wire n_695; wire n_696; wire n_697; wire n_698; wire n_699; wire n_700; wire n_701; wire n_702; wire n_703; wire n_704; wire n_705; wire n_706; wire n_707; wire n_708; wire n_709; wire n_710; wire n_711; wire n_712; wire n_713; wire n_714; wire n_715; wire n_716; wire n_717; wire n_718; wire n_719; wire n_720; wire n_721; wire n_722; wire n_723; wire n_724; wire n_725; wire n_726; wire n_727; wire n_728; wire n_729; wire n_730; wire n_731; wire n_732; wire n_733; wire n_734; wire n_735; wire n_736; wire n_737; wire n_738; wire n_739; wire n_740; wire n_741; wire n_742; wire n_743; wire n_744; wire n_745; wire n_746; wire n_747; wire n_748; wire n_749; wire n_750; wire n_751; wire n_752; wire n_753; wire n_754; wire n_755; wire n_756; wire n_757; wire n_758; wire n_759; wire n_760; wire n_761; wire n_762; wire n_763; wire n_764; wire n_765; wire n_766; wire n_767; wire n_768; wire n_769; wire n_770; wire n_771; wire n_772; wire n_773; wire n_774; wire n_775; wire n_776; wire n_777; wire n_778; wire n_779; wire n_780; wire n_781; wire n_782; wire n_783; wire n_784; wire n_785; wire n_786; wire n_787; wire n_788; wire n_789; wire n_790; wire n_791; wire n_792; wire n_793; wire n_794; wire n_795; wire n_796; wire n_797; wire n_798; wire n_799; wire n_800; wire n_801; wire n_802; wire n_803; wire n_804; wire n_805; wire n_806; wire n_807; wire n_808; wire n_809; wire n_810; wire n_811; wire n_812; wire n_813; wire n_814; wire n_815; wire n_816; wire n_817; wire n_818; wire n_819; wire n_820; wire n_821; wire n_822; wire n_823; wire n_824; wire n_825; wire n_826; wire n_827; wire n_828; wire n_829; wire n_830; wire n_831; wire n_832; wire n_833; wire n_834; wire n_835; wire n_836; wire n_837; wire n_838; wire n_839; wire n_840; wire n_841; wire n_842; wire n_843; wire n_844; wire n_845; wire n_846; wire n_847; wire n_848; wire n_849; wire n_850; wire n_851; wire n_852; wire n_853; wire n_854; wire n_855; wire n_856; wire n_857; wire n_858; wire n_859; wire n_860; wire n_861; wire n_862; wire n_863; wire n_864; wire n_865; wire n_866; wire n_867; wire n_868; wire n_869; wire n_870; wire n_871; wire n_872; wire n_873; wire n_874; wire n_875; wire n_876; wire n_877; wire n_878; wire n_879; wire n_880; wire n_881; wire n_882; wire n_883; wire n_884; wire n_885; wire n_886; wire n_887; wire n_888; wire n_889; wire n_890; wire n_891; wire n_892; wire n_893; wire n_894; wire n_895; wire n_896; wire n_897; wire n_898; wire n_899; wire n_900; wire n_901; wire n_902; wire n_903; wire n_904; wire n_905; wire n_906; wire n_907; wire n_908; wire n_909; wire n_910; wire n_911; wire n_912; wire n_913; wire n_914; wire n_915; wire n_916; wire n_917; wire n_918; wire n_919; wire n_920; wire n_921; wire n_922; wire n_923; wire n_924; wire n_925; wire n_926; wire n_927; wire n_928; wire n_929; wire n_930; wire n_931; wire n_932; wire n_933; wire n_934; wire n_935; wire n_936; wire n_937; wire n_938; wire n_939; wire n_940; wire n_941; wire n_942; wire n_943; wire n_944; wire n_945; wire n_946; wire n_947; wire n_948; wire n_949; wire n_950; wire n_951; wire n_952; wire n_953; wire n_954; wire n_955; wire n_956; wire n_957; wire n_958; wire n_959; wire n_960; wire n_961; wire n_962; wire n_963; wire n_964; wire n_965; wire n_966; wire n_967; wire n_968; wire n_969; wire n_970; wire n_971; wire n_972; wire n_973; wire n_974; wire n_975; wire n_976; wire n_977; wire n_978; wire n_979; wire n_980; wire n_981; wire n_982; wire n_983; wire n_984; wire n_985; wire n_986; wire n_987; wire n_988; wire n_989; wire n_990; wire n_991; wire n_992; wire n_993; wire n_994; wire n_995; wire n_996; wire n_997; wire n_998; wire n_999; wire n_1000; wire n_1001; wire n_1002; wire n_1003; wire n_1004; wire n_1005; wire n_1006; wire n_1007; wire n_1008; wire n_1009; wire n_1010; wire n_1011; wire n_1012; wire n_1013; wire n_1014; wire n_1015; wire n_1016; wire n_1017; wire n_1018; wire n_1019; wire n_1020; wire n_1021; wire n_1022; wire n_1023; wire n_1024; wire n_1025; wire n_1026; wire n_1027; wire n_1028; wire n_1029; wire n_1030; wire n_1031; wire n_1032; wire n_1033; wire n_1034; wire n_1035; wire n_1036; wire n_1037; wire n_1038; wire n_1039; wire n_1040; wire n_1041; wire n_1042; wire n_1043; wire n_1044; wire n_1045; wire n_1046; wire n_1047; wire n_1048; wire n_1049; wire n_1050; wire n_1051; wire n_1052; wire n_1053; wire n_1054; wire n_1055; wire n_1056; wire n_1057; wire n_1058; wire n_1059; wire n_1060; wire n_1061; wire n_1062; wire n_1063; wire n_1064; wire n_1065; wire n_1066; wire n_1067; wire n_1068; wire n_1069; wire n_1070; wire n_1071; wire n_1072; wire n_1073; wire n_1074; wire n_1075; wire n_1076; wire n_1077; wire n_1078; wire n_1079; wire n_1080; wire n_1081; wire n_1082; wire n_1083; wire n_1084; wire n_1085; wire n_1086; wire n_1087; wire n_1088; wire n_1089; wire n_1090; wire n_1091; wire n_1092; wire n_1093; wire n_1094; wire n_1095; wire n_1096; wire n_1097; wire n_1098; wire n_1099; wire n_1100; wire n_1101; wire n_1102; wire n_1103; wire n_1104; wire n_1105; wire n_1106; wire n_1107; wire n_1108; wire n_1109; wire n_1110; wire n_1111; wire n_1112; wire n_1113; wire n_1114; wire n_1115; wire n_1116; wire n_1117; wire n_1118; wire n_1119; wire n_1120; wire n_1121; wire n_1122; wire n_1123; wire n_1124; wire n_1125; wire n_1126; wire n_1127; wire n_1128; wire n_1129; wire n_1130; wire n_1131; wire n_1132; wire n_1133; wire n_1134; wire n_1135; wire n_1136; wire n_1137; wire n_1138; wire n_1139; wire n_1140; wire n_1141; wire n_1142; wire n_1143; wire n_1144; wire n_1145; wire n_1146; wire n_1147; wire n_1148; wire n_1149; wire n_1150; wire n_1151; wire n_1152; wire n_1153; wire n_1154; wire n_1155; wire n_1156; wire n_1157; wire n_1158; wire n_1159; wire n_1160; wire n_1161; wire n_1162; wire n_1163; wire n_1164; wire n_1165; wire n_1166; wire n_1167; wire n_1168; wire n_1169; wire n_1170; wire n_1171; wire n_1172; wire n_1173; wire n_1174; wire n_1175; wire n_1176; wire n_1177; wire n_1178; wire n_1179; wire n_1180; wire n_1181; wire n_1182; wire n_1183; wire n_1184; wire n_1185; wire n_1186; wire n_1187; wire n_1188; wire n_1189; wire n_1190; wire n_1191; wire n_1192; wire n_1193; wire n_1194; wire n_1195; wire n_1196; wire n_1197; wire n_1198; wire n_1199; wire n_1200; wire n_1201; wire n_1202; wire n_1203; wire n_1204; wire n_1205; wire n_1206; wire n_1207; wire n_1208; wire n_1209; wire n_1210; wire n_1211; wire n_1212; wire n_1213; wire n_1214; wire n_1215; wire n_1216; wire n_1217; wire n_1218; wire n_1219; wire n_1220; wire n_1221; wire n_1222; wire n_1223; wire n_1224; wire n_1225; wire n_1226; wire n_1227; wire n_1228; wire n_1229; wire n_1230; wire n_1231; wire n_1232; wire n_1233; wire n_1234; wire n_1235; wire n_1236; wire n_1237; wire n_1238; wire n_1239; wire n_1240; wire n_1241; wire n_1242; wire n_1243; wire n_1244; wire n_1245; wire n_1246; wire n_1247; wire n_1248; wire n_1249; wire n_1250; wire n_1251; wire n_1252; wire n_1253; wire n_1254; wire n_1255; wire n_1256; wire n_1257; wire n_1258; wire n_1259; wire n_1260; wire n_1261; wire n_1262; wire n_1263; wire n_1264; wire n_1265; wire n_1266; wire n_1267; wire n_1268; wire n_1269; wire n_1270; wire n_1271; wire n_1272; wire n_1273; wire n_1274; wire n_1275; wire n_1276; wire n_1277; wire n_1278; wire n_1279; wire n_1280; wire n_1281; wire n_1282; wire n_1283; wire n_1284; wire n_1285; wire n_1286; wire n_1287; wire n_1288; wire n_1289; wire n_1290; wire n_1291; wire n_1292; wire n_1293; wire n_1294; wire n_1295; wire n_1296; wire n_1297; wire n_1298; wire n_1299; wire n_1300; wire n_1301; wire n_1302; wire n_1303; wire n_1304; wire n_1305; wire n_1306; wire n_1307; wire n_1308; wire n_1309; wire n_1310; wire n_1311; wire n_1312; wire n_1313; wire n_1314; wire n_1315; wire n_1316; wire n_1317; wire n_1318; wire n_1319; wire n_1320; wire n_1321; wire n_1322; wire n_1323; wire n_1324; wire n_1325; wire n_1326; wire n_1327; wire n_1328; wire n_1329; wire n_1330; wire n_1331; wire n_1332; wire n_1333; wire n_1334; wire n_1335; wire n_1336; wire n_1337; wire n_1338; wire n_1339; wire n_1340; wire n_1341; wire n_1342; wire n_1343; wire n_1344; wire n_1345; wire n_1346; wire n_1347; wire n_1348; wire n_1349; wire n_1350; wire n_1351; wire n_1352; wire n_1353; wire n_1354; wire n_1355; wire n_1356; wire n_1357; wire n_1358; wire n_1359; wire n_1360; wire n_1361; wire n_1362; wire n_1363; wire n_1364; wire n_1365; wire n_1366; wire n_1367; wire n_1368; wire n_1369; wire n_1370; wire n_1371; wire n_1372; wire n_1373; wire n_1374; wire n_1375; wire n_1376; wire n_1377; wire n_1378; wire n_1379; wire n_1380; wire n_1381; wire n_1382; wire n_1383; wire n_1384; wire n_1385; wire n_1386; wire n_1387; wire n_1388; wire n_1389; wire n_1390; wire n_1391; wire n_1392; wire n_1393; wire n_1394; wire n_1395; wire n_1396; wire n_1397; wire n_1398; wire n_1399; wire n_1400; wire n_1401; wire n_1402; wire n_1403; wire n_1404; wire n_1405; wire n_1406; wire n_1407; wire n_1408; wire n_1409; wire n_1410; wire n_1411; wire n_1412; wire n_1413; wire n_1414; wire n_1415; wire n_1416; wire n_1417; wire n_1418; wire n_1419; wire n_1420; wire n_1421; wire n_1422; wire n_1423; wire n_1424; wire n_1425; wire n_1426; wire n_1427; wire n_1428; wire n_1429; wire n_1430; wire n_1431; wire n_1432; wire n_1433; wire n_1434; wire n_1435; wire n_1436; wire n_1437; wire n_1438; wire n_1439; wire n_1440; wire n_1441; wire n_1442; wire n_1443; wire n_1444; wire n_1445; wire n_1446; wire n_1447; wire n_1448; wire n_1449; wire n_1450; wire n_1451; wire n_1452; wire n_1453; wire n_1454; wire n_1455; wire n_1456; wire n_1457; wire n_1458; wire n_1459; wire n_1460; wire n_1461; wire n_1462; wire n_1463; wire n_1464; wire n_1465; wire n_1466; wire n_1467; wire n_1468; wire n_1469; wire n_1470; wire n_1471; wire n_1472; wire n_1473; wire n_1474; wire n_1475; wire n_1476; wire n_1477; wire n_1478; wire n_1479; wire n_1480; wire n_1481; wire n_1482; wire n_1483; wire n_1484; wire n_1485; wire n_1486; wire n_1487; wire n_1488; wire n_1489; wire n_1490; wire n_1491; wire n_1492; wire n_1493; wire n_1494; wire n_1495; wire n_1496; wire n_1497; wire n_1498; wire n_1499; wire n_1500; wire n_1501; wire n_1502; wire n_1503; wire n_1504; wire n_1505; wire n_1506; wire n_1507; wire n_1508; wire n_1509; wire n_1510; wire n_1511; wire n_1512; wire n_1513; wire n_1514; wire n_1515; wire n_1516; wire n_1517; wire n_1518; wire n_1519; wire n_1520; wire n_1521; wire n_1522; wire n_1523; wire n_1524; wire n_1525; wire n_1526; wire n_1527; wire n_1528; wire n_1529; wire n_1530; wire n_1531; wire n_1532; wire n_1533; wire n_1534; wire n_1535; wire n_1536; wire n_1537; wire n_1538; wire n_1539; wire n_1540; wire n_1541; wire n_1542; wire n_1543; wire n_1544; wire n_1545; wire n_1546; wire n_1547; wire n_1548; wire n_1549; wire n_1550; wire n_1551; wire n_1552; wire n_1553; wire n_1554; wire n_1555; wire n_1556; wire n_1557; wire n_1558; wire n_1559; wire n_1560; wire n_1561; wire n_1562; wire n_1563; wire n_1564; wire n_1565; wire n_1566; wire n_1567; wire n_1568; wire n_1569; wire n_1570; wire n_1571; wire n_1572; wire n_1573; wire n_1574; wire n_1575; wire n_1576; wire n_1577; wire n_1578; wire n_1579; wire n_1580; wire n_1581; wire n_1582; wire n_1583; wire n_1584; wire n_1585; wire n_1586; wire n_1587; wire n_1588; wire n_1589; wire n_1590; wire n_1591; wire n_1592; wire n_1593; wire n_1594; wire n_1595; wire n_1596; wire n_1597; wire n_1598; wire n_1599; wire n_1600; wire n_1601; wire n_1602; wire n_1603; wire n_1604; wire n_1605; wire n_1606; wire n_1607; wire n_1608; wire n_1609; wire n_1610; wire n_1611; wire n_1612; wire n_1613; wire n_1614; wire n_1615; wire n_1616; wire n_1617; wire n_1618; wire n_1619; wire n_1620; wire n_1621; wire n_1622; wire n_1623; wire n_1624; wire n_1625; wire n_1626; wire n_1627; wire n_1628; wire n_1629; wire n_1630; wire n_1631; wire n_1632; wire n_1633; wire n_1634; wire n_1635; wire n_1636; wire n_1637; wire n_1638; wire n_1639; wire n_1640; wire n_1641; wire n_1642; wire n_1643; wire n_1644; wire n_1645; wire n_1646; wire n_1647; wire n_1648; wire n_1649; wire n_1650; wire n_1651; wire n_1652; wire n_1653; wire n_1654; wire n_1655; wire n_1656; wire n_1657; wire n_1658; wire n_1659; wire n_1660; wire n_1661; wire n_1662; wire n_1663; wire n_1664; wire n_1665; wire n_1666; wire n_1667; wire n_1668; wire n_1669; wire n_1670; wire n_1671; wire n_1672; wire n_1673; wire n_1674; wire n_1675; wire n_1676; wire n_1677; wire n_1678; wire n_1679; wire n_1680; wire n_1681; wire n_1682; wire n_1683; wire n_1684; wire n_1685; wire n_1686; wire n_1687; wire n_1688; wire n_1689; wire n_1690; wire n_1691; wire n_1692; wire n_1693; wire n_1694; wire n_1695; wire n_1696; wire n_1697; wire n_1698; wire n_1699; wire n_1700; wire n_1701; wire n_1702; wire n_1703; wire n_1704; wire n_1705; wire n_1706; wire n_1707; wire n_1708; wire n_1709; wire n_1710; wire n_1711; wire n_1712; wire n_1713; wire n_1714; wire n_1715; wire n_1716; wire n_1717; wire n_1718; wire n_1719; wire n_1720; wire n_1721; wire n_1722; wire n_1723; wire n_1724; wire n_1725; wire n_1726; wire n_1727; wire n_1728; wire n_1729; wire n_1730; wire n_1731; wire n_1732; wire n_1733; wire n_1734; wire n_1735; wire n_1736; wire n_1737; wire n_1738; wire n_1739; wire n_1740; wire n_1741; wire n_1742; wire n_1743; wire n_1744; wire n_1745; wire n_1746; wire n_1747; wire n_1748; wire n_1749; wire n_1750; wire n_1751; wire n_1752; wire n_1753; wire n_1754; wire n_1755; wire n_1756; wire n_1757; wire n_1758; wire n_1759; wire n_1760; wire n_1761; wire n_1762; wire n_1763; wire n_1764; wire n_1765; wire n_1766; wire n_1767; wire n_1768; wire n_1769; wire n_1770; wire n_1771; wire n_1772; wire n_1773; wire n_1774; wire n_1775; wire n_1776; wire n_1777; wire n_1778; wire n_1779; wire n_1780; wire n_1781; wire n_1782; wire n_1783; wire n_1784; wire n_1785; wire n_1786; wire n_1787; wire n_1788; wire n_1789; wire n_1790; wire n_1791; wire n_1792; wire n_1793; wire n_1794; wire n_1795; wire n_1796; wire n_1797; wire n_1798; wire n_1799; wire n_1800; wire n_1801; wire n_1802; wire n_1803; wire n_1804; wire n_1805; wire n_1806; wire n_1807; wire n_1808; wire n_1809; wire n_1810; wire n_1811; wire n_1812; wire n_1813; wire n_1814; wire n_1815; wire n_1816; wire n_1817; wire n_1818; wire n_1819; wire n_1820; wire n_1821; wire n_1822; wire n_1823; wire n_1824; wire n_1825; wire n_1826; wire n_1827; wire n_1828; wire n_1829; wire n_1830; wire n_1831; wire n_1832; wire n_1833; wire n_1834; wire n_1835; wire n_1836; wire n_1837; wire n_1838; wire n_1839; wire n_1840; wire n_1841; wire n_1842; wire n_1843; wire n_1844; wire n_1845; wire n_1846; wire n_1847; wire n_1848; wire n_1849; wire n_1850; wire n_1851; wire n_1852; wire n_1853; wire n_1854; wire n_1855; wire n_1856; wire n_1857; wire n_1858; wire n_1859; wire n_1860; wire n_1861; wire n_1862; wire n_1863; wire n_1864; wire n_1865; wire n_1866; wire n_1867; wire n_1868; wire n_1869; wire n_1870; wire n_1871; wire n_1872; wire n_1873; wire n_1874; wire n_1875; wire n_1876; wire n_1877; wire n_1878; wire n_1879; wire n_1880; wire n_1881; wire n_1882; wire n_1883; wire n_1884; wire n_1885; wire n_1886; wire n_1887; wire n_1888; wire n_1889; wire n_1890; wire n_1891; wire n_1892; wire n_1893; wire n_1894; wire n_1895; wire n_1896; wire n_1897; wire n_1898; wire n_1899; wire n_1900; wire n_1901; wire n_1902; wire n_1903; wire n_1904; wire n_1905; wire n_1906; wire n_1907; wire n_1908; wire n_1909; wire n_1910; wire n_1911; assign n_1 = i_5 & i_29; assign n_2 = i_14 & i_31; assign n_3 = ~n_1 & ~n_2; assign n_4 = x_153 & n_3; assign n_5 = ~x_153 & ~n_3; assign n_6 = ~n_4 & ~n_5; assign n_7 = i_6 & i_29; assign n_8 = i_15 & i_31; assign n_9 = ~n_7 & ~n_8; assign n_10 = x_152 & n_9; assign n_11 = ~x_152 & ~n_9; assign n_12 = ~n_10 & ~n_11; assign n_13 = i_4 & i_29; assign n_14 = i_13 & i_31; assign n_15 = ~n_13 & ~n_14; assign n_16 = x_151 & n_15; assign n_17 = ~x_151 & ~n_15; assign n_18 = ~n_16 & ~n_17; assign n_19 = i_9 & i_29; assign n_20 = i_18 & i_31; assign n_21 = ~n_19 & ~n_20; assign n_22 = x_150 & n_21; assign n_23 = ~x_150 & ~n_21; assign n_24 = ~n_22 & ~n_23; assign n_25 = i_7 & i_29; assign n_26 = i_16 & i_31; assign n_27 = ~n_25 & ~n_26; assign n_28 = x_149 & n_27; assign n_29 = ~x_149 & ~n_27; assign n_30 = ~n_28 & ~n_29; assign n_31 = i_2 & i_29; assign n_32 = i_11 & i_31; assign n_33 = ~n_31 & ~n_32; assign n_34 = x_148 & n_33; assign n_35 = ~x_148 & ~n_33; assign n_36 = ~n_34 & ~n_35; assign n_37 = i_3 & i_29; assign n_38 = i_12 & i_31; assign n_39 = ~n_37 & ~n_38; assign n_40 = x_147 & n_39; assign n_41 = ~x_147 & ~n_39; assign n_42 = ~n_40 & ~n_41; assign n_43 = i_1 & i_29; assign n_44 = i_10 & i_31; assign n_45 = ~n_43 & ~n_44; assign n_46 = x_146 & n_45; assign n_47 = ~x_146 & ~n_45; assign n_48 = ~n_46 & ~n_47; assign n_49 = x_129 & ~x_130; assign n_50 = ~x_129 & x_130; assign n_51 = ~n_49 & ~n_50; assign n_52 = x_138 & ~n_51; assign n_53 = ~x_138 & n_51; assign n_54 = ~n_52 & ~n_53; assign n_55 = ~x_134 & ~x_135; assign n_56 = x_134 & x_135; assign n_57 = ~n_55 & ~n_56; assign n_58 = x_136 & n_57; assign n_59 = ~x_136 & ~n_57; assign n_60 = ~n_58 & ~n_59; assign n_61 = x_131 & ~x_132; assign n_62 = ~x_131 & x_132; assign n_63 = ~n_61 & ~n_62; assign n_64 = x_137 & ~n_63; assign n_65 = ~x_137 & n_63; assign n_66 = ~n_64 & ~n_65; assign n_67 = n_60 & ~n_66; assign n_68 = ~n_60 & n_66; assign n_69 = ~n_67 & ~n_68; assign n_70 = n_54 & n_69; assign n_71 = ~n_54 & ~n_69; assign n_72 = ~n_70 & ~n_71; assign n_73 = x_145 & ~n_72; assign n_74 = ~x_145 & n_72; assign n_75 = ~n_73 & ~n_74; assign n_76 = ~x_143 & x_144; assign n_77 = x_143 & ~x_144; assign n_78 = ~n_76 & ~n_77; assign n_79 = ~x_142 & x_143; assign n_80 = x_142 & ~x_143; assign n_81 = ~n_79 & ~n_80; assign n_82 = ~i_34 & ~x_141; assign n_83 = x_142 & ~n_82; assign n_84 = ~x_142 & n_82; assign n_85 = ~n_83 & ~n_84; assign n_86 = ~x_140 & x_141; assign n_87 = x_140 & ~x_141; assign n_88 = ~n_86 & ~n_87; assign n_89 = ~x_131 & ~x_132; assign n_90 = ~x_129 & ~x_130; assign n_91 = n_89 & n_90; assign n_92 = x_140 & ~n_91; assign n_93 = ~x_140 & n_91; assign n_94 = ~n_92 & ~n_93; assign n_95 = x_139 & ~n_72; assign n_96 = ~x_139 & n_72; assign n_97 = ~n_95 & ~n_96; assign n_98 = ~i_4 & x_138; assign n_99 = i_4 & ~x_138; assign n_100 = ~n_98 & ~n_99; assign n_101 = ~i_9 & x_137; assign n_102 = i_9 & ~x_137; assign n_103 = ~n_101 & ~n_102; assign n_104 = ~i_2 & x_136; assign n_105 = i_2 & ~x_136; assign n_106 = ~n_104 & ~n_105; assign n_107 = ~i_3 & x_135; assign n_108 = i_3 & ~x_135; assign n_109 = ~n_107 & ~n_108; assign n_110 = ~i_1 & x_134; assign n_111 = i_1 & ~x_134; assign n_112 = ~n_110 & ~n_111; assign n_113 = i_24 & ~i_25; assign n_114 = ~i_24 & i_25; assign n_115 = ~n_113 & ~n_114; assign n_116 = i_22 & ~i_23; assign n_117 = ~i_22 & i_23; assign n_118 = ~n_116 & ~n_117; assign n_119 = ~i_19 & ~i_20; assign n_120 = i_19 & i_20; assign n_121 = ~n_119 & ~n_120; assign n_122 = i_21 & ~n_121; assign n_123 = ~i_21 & n_121; assign n_124 = ~n_122 & ~n_123; assign n_125 = n_118 & ~n_124; assign n_126 = ~n_118 & n_124; assign n_127 = ~n_125 & ~n_126; assign n_128 = n_115 & n_127; assign n_129 = ~n_115 & ~n_127; assign n_130 = ~n_128 & ~n_129; assign n_131 = x_133 & n_130; assign n_132 = ~x_133 & ~n_130; assign n_133 = ~n_131 & ~n_132; assign n_134 = ~i_7 & x_132; assign n_135 = i_7 & ~x_132; assign n_136 = ~n_134 & ~n_135; assign n_137 = ~i_8 & x_131; assign n_138 = i_8 & ~x_131; assign n_139 = ~n_137 & ~n_138; assign n_140 = ~i_6 & x_130; assign n_141 = i_6 & ~x_130; assign n_142 = ~n_140 & ~n_141; assign n_143 = ~i_5 & x_129; assign n_144 = i_5 & ~x_129; assign n_145 = ~n_143 & ~n_144; assign n_146 = i_8 & i_29; assign n_147 = i_17 & i_31; assign n_148 = ~n_146 & ~n_147; assign n_149 = x_128 & n_148; assign n_150 = ~x_128 & ~n_148; assign n_151 = ~n_149 & ~n_150; assign n_152 = ~x_42 & x_43; assign n_153 = x_42 & ~x_43; assign n_154 = ~n_152 & ~n_153; assign n_155 = ~x_40 & x_41; assign n_156 = x_40 & ~x_41; assign n_157 = ~n_155 & ~n_156; assign n_158 = n_154 & ~n_157; assign n_159 = ~n_154 & n_157; assign n_160 = ~n_158 & ~n_159; assign n_161 = x_39 & n_160; assign n_162 = ~x_39 & ~n_160; assign n_163 = ~n_161 & ~n_162; assign n_164 = ~x_36 & ~x_37; assign n_165 = x_36 & x_37; assign n_166 = ~n_164 & ~n_165; assign n_167 = x_38 & ~n_166; assign n_168 = ~x_38 & n_166; assign n_169 = ~n_167 & ~n_168; assign n_170 = x_44 & ~n_169; assign n_171 = ~x_44 & n_169; assign n_172 = ~n_170 & ~n_171; assign n_173 = n_163 & n_172; assign n_174 = ~n_163 & ~n_172; assign n_175 = ~n_173 & ~n_174; assign n_176 = ~x_114 & n_175; assign n_177 = ~x_95 & ~x_97; assign n_178 = x_95 & x_97; assign n_179 = ~n_177 & ~n_178; assign n_180 = x_98 & n_179; assign n_181 = ~x_98 & ~n_179; assign n_182 = ~n_180 & ~n_181; assign n_183 = x_96 & ~x_101; assign n_184 = ~x_96 & x_101; assign n_185 = ~n_183 & ~n_184; assign n_186 = n_182 & ~n_185; assign n_187 = ~n_182 & n_185; assign n_188 = ~n_186 & ~n_187; assign n_189 = ~x_99 & ~x_100; assign n_190 = x_99 & x_100; assign n_191 = ~n_189 & ~n_190; assign n_192 = x_102 & ~x_103; assign n_193 = ~x_102 & x_103; assign n_194 = ~n_192 & ~n_193; assign n_195 = n_191 & ~n_194; assign n_196 = ~n_191 & n_194; assign n_197 = ~n_195 & ~n_196; assign n_198 = n_188 & n_197; assign n_199 = ~n_188 & ~n_197; assign n_200 = ~n_198 & ~n_199; assign n_201 = ~x_91 & ~x_93; assign n_202 = x_91 & x_93; assign n_203 = ~n_201 & ~n_202; assign n_204 = x_94 & ~n_203; assign n_205 = ~x_94 & n_203; assign n_206 = ~n_204 & ~n_205; assign n_207 = ~x_90 & ~x_92; assign n_208 = x_90 & x_92; assign n_209 = ~n_207 & ~n_208; assign n_210 = ~n_160 & n_209; assign n_211 = n_160 & ~n_209; assign n_212 = ~n_210 & ~n_211; assign n_213 = n_206 & n_212; assign n_214 = ~n_206 & ~n_212; assign n_215 = ~n_213 & ~n_214; assign n_216 = ~x_82 & ~x_83; assign n_217 = x_82 & x_83; assign n_218 = ~n_216 & ~n_217; assign n_219 = x_84 & n_218; assign n_220 = ~x_84 & ~n_218; assign n_221 = ~n_219 & ~n_220; assign n_222 = ~x_87 & ~x_88; assign n_223 = x_87 & x_88; assign n_224 = ~n_222 & ~n_223; assign n_225 = x_79 & ~x_85; assign n_226 = ~x_79 & x_85; assign n_227 = ~n_225 & ~n_226; assign n_228 = n_224 & ~n_227; assign n_229 = ~n_224 & n_227; assign n_230 = ~n_228 & ~n_229; assign n_231 = n_221 & n_230; assign n_232 = ~n_221 & ~n_230; assign n_233 = ~n_231 & ~n_232; assign n_234 = x_86 & ~x_89; assign n_235 = ~x_86 & x_89; assign n_236 = ~n_234 & ~n_235; assign n_237 = n_233 & n_236; assign n_238 = ~n_233 & ~n_236; assign n_239 = ~n_237 & ~n_238; assign n_240 = n_215 & n_239; assign n_241 = ~n_200 & n_240; assign n_242 = n_176 & n_241; assign n_243 = x_127 & ~n_242; assign n_244 = ~x_127 & n_242; assign n_245 = ~n_243 & ~n_244; assign n_246 = ~x_104 & x_106; assign n_247 = ~x_115 & ~n_246; assign n_248 = x_115 & n_246; assign n_249 = ~n_247 & ~n_248; assign n_250 = x_126 & ~n_249; assign n_251 = ~x_126 & n_249; assign n_252 = ~n_250 & ~n_251; assign n_253 = x_112 & ~x_113; assign n_254 = ~x_112 & x_113; assign n_255 = ~n_253 & ~n_254; assign n_256 = ~x_116 & n_255; assign n_257 = ~x_110 & x_111; assign n_258 = x_116 & ~n_255; assign n_259 = ~n_257 & ~n_258; assign n_260 = ~n_256 & n_259; assign n_261 = x_105 & ~x_106; assign n_262 = ~x_104 & ~x_115; assign n_263 = ~n_261 & ~n_262; assign n_264 = ~i_26 & ~x_127; assign n_265 = ~x_109 & ~n_264; assign n_266 = ~n_263 & n_265; assign n_267 = ~n_260 & n_266; assign n_268 = ~n_130 & n_267; assign n_269 = x_125 & ~n_268; assign n_270 = ~x_125 & n_268; assign n_271 = ~n_269 & ~n_270; assign n_272 = i_35 & x_76; assign n_273 = ~x_78 & n_272; assign n_274 = ~x_42 & ~x_43; assign n_275 = ~x_41 & n_274; assign n_276 = ~x_40 & n_275; assign n_277 = x_40 & ~n_275; assign n_278 = x_120 & ~n_277; assign n_279 = ~n_276 & n_278; assign n_280 = n_273 & n_279; assign n_281 = x_124 & ~n_280; assign n_282 = ~x_124 & n_280; assign n_283 = ~n_281 & ~n_282; assign n_284 = x_47 & ~x_81; assign n_285 = i_35 & ~x_80; assign n_286 = ~n_284 & n_285; assign n_287 = ~n_286 & ~n_273; assign n_288 = x_36 & x_120; assign n_289 = ~n_287 & n_288; assign n_290 = x_123 & ~n_289; assign n_291 = ~x_123 & n_289; assign n_292 = ~n_290 & ~n_291; assign n_293 = ~i_6 & x_41; assign n_294 = i_6 & ~x_41; assign n_295 = ~n_293 & ~n_294; assign n_296 = ~i_5 & x_40; assign n_297 = i_5 & ~x_40; assign n_298 = ~n_296 & ~n_297; assign n_299 = ~i_4 & x_39; assign n_300 = i_4 & ~x_39; assign n_301 = ~n_299 & ~n_300; assign n_302 = ~i_3 & x_38; assign n_303 = i_3 & ~x_38; assign n_304 = ~n_302 & ~n_303; assign n_305 = ~i_2 & x_37; assign n_306 = i_2 & ~x_37; assign n_307 = ~n_305 & ~n_306; assign n_308 = ~i_1 & x_36; assign n_309 = i_1 & ~x_36; assign n_310 = ~n_308 & ~n_309; assign n_311 = ~x_220 & x_221; assign n_312 = ~x_218 & ~x_219; assign n_313 = ~x_222 & n_312; assign n_314 = n_311 & n_313; assign n_315 = ~x_243 & n_314; assign n_316 = x_291 & ~n_315; assign n_317 = ~x_291 & n_315; assign n_318 = ~n_316 & ~n_317; assign n_319 = ~x_218 & x_219; assign n_320 = x_220 & x_221; assign n_321 = ~x_222 & n_320; assign n_322 = n_319 & n_321; assign n_323 = ~x_224 & x_225; assign n_324 = x_223 & x_227; assign n_325 = ~x_226 & n_324; assign n_326 = n_323 & n_325; assign n_327 = n_322 & n_326; assign n_328 = x_290 & ~n_327; assign n_329 = ~x_290 & n_327; assign n_330 = ~n_328 & ~n_329; assign n_331 = x_219 & n_320; assign n_332 = x_218 & n_331; assign n_333 = ~x_222 & n_332; assign n_334 = n_333 & n_326; assign n_335 = x_289 & ~n_334; assign n_336 = ~x_289 & n_334; assign n_337 = ~n_335 & ~n_336; assign n_338 = x_220 & ~x_221; assign n_339 = n_313 & n_338; assign n_340 = x_288 & ~n_339; assign n_341 = ~x_288 & n_339; assign n_342 = ~n_340 & ~n_341; assign n_343 = ~x_224 & ~x_225; assign n_344 = n_89 & n_343; assign n_345 = x_224 & x_225; assign n_346 = x_131 & x_132; assign n_347 = n_345 & n_346; assign n_348 = ~n_344 & ~n_347; assign n_349 = x_224 & ~x_225; assign n_350 = n_62 & n_349; assign n_351 = n_61 & n_323; assign n_352 = ~n_350 & ~n_351; assign n_353 = n_348 & n_352; assign n_354 = ~x_223 & x_226; assign n_355 = ~x_227 & n_354; assign n_356 = n_90 & n_355; assign n_357 = x_223 & ~x_227; assign n_358 = x_226 & n_50; assign n_359 = n_357 & n_358; assign n_360 = ~n_356 & ~n_359; assign n_361 = ~n_353 & ~n_360; assign n_362 = ~x_223 & x_227; assign n_363 = x_226 & n_362; assign n_364 = n_363 & n_343; assign n_365 = ~n_361 & ~n_364; assign n_366 = ~x_182 & ~x_215; assign n_367 = ~x_216 & n_366; assign n_368 = x_182 & x_183; assign n_369 = ~x_181 & ~n_368; assign n_370 = n_369 & n_322; assign n_371 = x_222 & n_311; assign n_372 = n_312 & n_371; assign n_373 = ~n_369 & n_372; assign n_374 = ~n_370 & ~n_373; assign n_375 = ~n_367 & ~n_374; assign n_376 = ~n_365 & n_375; assign n_377 = n_349 & n_363; assign n_378 = n_373 & ~n_377; assign n_379 = ~n_376 & n_378; assign n_380 = x_287 & ~n_379; assign n_381 = ~x_287 & n_379; assign n_382 = ~n_380 & ~n_381; assign n_383 = n_349 & n_325; assign n_384 = ~x_222 & n_319; assign n_385 = ~x_220 & ~x_221; assign n_386 = n_384 & n_385; assign n_387 = n_383 & n_386; assign n_388 = x_286 & ~n_387; assign n_389 = ~x_286 & n_387; assign n_390 = ~n_388 & ~n_389; assign n_391 = x_285 & ~n_333; assign n_392 = ~x_285 & n_333; assign n_393 = ~n_391 & ~n_392; assign n_394 = n_311 & n_384; assign n_395 = x_284 & ~n_394; assign n_396 = ~x_284 & n_394; assign n_397 = ~n_395 & ~n_396; assign n_398 = n_322 & ~n_376; assign n_399 = x_283 & ~n_398; assign n_400 = ~x_283 & n_398; assign n_401 = ~n_399 & ~n_400; assign n_402 = x_176 & ~x_177; assign n_403 = ~x_179 & ~x_180; assign n_404 = ~x_178 & n_403; assign n_405 = n_402 & n_404; assign n_406 = ~x_173 & x_175; assign n_407 = ~x_171 & ~x_172; assign n_408 = ~x_174 & n_407; assign n_409 = n_406 & n_408; assign n_410 = n_405 & n_409; assign n_411 = x_282 & ~n_410; assign n_412 = ~x_282 & n_410; assign n_413 = ~n_411 & ~n_412; assign n_414 = ~x_250 & ~x_251; assign n_415 = ~i_35 & ~n_414; assign n_416 = ~x_142 & x_144; assign n_417 = ~x_140 & ~n_416; assign n_418 = ~n_415 & n_417; assign n_419 = x_255 & n_50; assign n_420 = n_419 & n_346; assign n_421 = n_418 & n_420; assign n_422 = x_281 & ~n_421; assign n_423 = ~x_281 & n_421; assign n_424 = ~n_422 & ~n_423; assign n_425 = ~x_279 & x_280; assign n_426 = x_279 & ~x_280; assign n_427 = ~n_425 & ~n_426; assign n_428 = ~x_246 & x_279; assign n_429 = x_246 & ~x_279; assign n_430 = ~n_428 & ~n_429; assign n_431 = ~x_155 & x_278; assign n_432 = x_155 & ~x_278; assign n_433 = ~n_431 & ~n_432; assign n_434 = ~x_158 & x_277; assign n_435 = x_158 & ~x_277; assign n_436 = ~n_434 & ~n_435; assign n_437 = ~x_157 & x_276; assign n_438 = x_157 & ~x_276; assign n_439 = ~n_437 & ~n_438; assign n_440 = ~x_169 & x_275; assign n_441 = x_169 & ~x_275; assign n_442 = ~n_440 & ~n_441; assign n_443 = ~x_168 & x_274; assign n_444 = x_168 & ~x_274; assign n_445 = ~n_443 & ~n_444; assign n_446 = ~x_165 & x_273; assign n_447 = x_165 & ~x_273; assign n_448 = ~n_446 & ~n_447; assign n_449 = ~x_166 & x_272; assign n_450 = x_166 & ~x_272; assign n_451 = ~n_449 & ~n_450; assign n_452 = ~x_164 & x_271; assign n_453 = x_164 & ~x_271; assign n_454 = ~n_452 & ~n_453; assign n_455 = ~x_156 & x_270; assign n_456 = x_156 & ~x_270; assign n_457 = ~n_455 & ~n_456; assign n_458 = ~x_159 & x_269; assign n_459 = x_159 & ~x_269; assign n_460 = ~n_458 & ~n_459; assign n_461 = ~x_206 & x_268; assign n_462 = x_206 & ~x_268; assign n_463 = ~n_461 & ~n_462; assign n_464 = ~x_213 & x_267; assign n_465 = x_213 & ~x_267; assign n_466 = ~n_464 & ~n_465; assign n_467 = ~x_265 & x_266; assign n_468 = x_265 & ~x_266; assign n_469 = ~n_467 & ~n_468; assign n_470 = ~x_264 & x_265; assign n_471 = x_264 & ~x_265; assign n_472 = ~n_470 & ~n_471; assign n_473 = ~x_263 & x_264; assign n_474 = x_263 & ~x_264; assign n_475 = ~n_473 & ~n_474; assign n_476 = ~x_262 & x_263; assign n_477 = x_262 & ~x_263; assign n_478 = ~n_476 & ~n_477; assign n_479 = ~x_258 & x_262; assign n_480 = x_258 & ~x_262; assign n_481 = ~n_479 & ~n_480; assign n_482 = ~x_208 & x_261; assign n_483 = x_208 & ~x_261; assign n_484 = ~n_482 & ~n_483; assign n_485 = ~x_259 & x_260; assign n_486 = x_259 & ~x_260; assign n_487 = ~n_485 & ~n_486; assign n_488 = ~x_182 & ~x_229; assign n_489 = ~n_488 & ~n_376; assign n_490 = x_259 & ~n_489; assign n_491 = ~x_259 & n_489; assign n_492 = ~n_490 & ~n_491; assign n_493 = ~x_257 & x_258; assign n_494 = x_257 & ~x_258; assign n_495 = ~n_493 & ~n_494; assign n_496 = x_241 & x_244; assign n_497 = x_256 & n_496; assign n_498 = x_257 & ~n_497; assign n_499 = ~x_257 & n_497; assign n_500 = ~n_498 & ~n_499; assign n_501 = x_255 & n_61; assign n_502 = n_90 & n_501; assign n_503 = x_255 & n_49; assign n_504 = n_89 & n_503; assign n_505 = ~x_132 & n_419; assign n_506 = ~n_504 & ~n_505; assign n_507 = ~n_502 & n_506; assign n_508 = ~x_129 & x_132; assign n_509 = x_255 & n_508; assign n_510 = ~x_130 & n_509; assign n_511 = n_507 & ~n_510; assign n_512 = x_256 & n_511; assign n_513 = ~x_256 & ~n_511; assign n_514 = ~n_512 & ~n_513; assign n_515 = ~x_133 & ~x_205; assign n_516 = ~x_207 & ~x_212; assign n_517 = ~x_214 & n_516; assign n_518 = n_515 & n_517; assign n_519 = ~x_249 & n_518; assign n_520 = ~i_35 & ~n_519; assign n_521 = ~x_243 & x_254; assign n_522 = ~n_520 & n_521; assign n_523 = ~n_376 & n_522; assign n_524 = x_255 & ~n_523; assign n_525 = ~x_255 & n_523; assign n_526 = ~n_524 & ~n_525; assign n_527 = ~x_253 & x_254; assign n_528 = x_253 & ~x_254; assign n_529 = ~n_527 & ~n_528; assign n_530 = ~x_252 & x_253; assign n_531 = x_252 & ~x_253; assign n_532 = ~n_530 & ~n_531; assign n_533 = i_23 & i_24; assign n_534 = ~i_21 & n_119; assign n_535 = i_31 & ~x_245; assign n_536 = n_534 & n_535; assign n_537 = i_22 & i_30; assign n_538 = n_536 & n_537; assign n_539 = n_533 & n_538; assign n_540 = ~i_27 & ~i_28; assign n_541 = i_21 & ~n_540; assign n_542 = i_29 & n_119; assign n_543 = ~x_245 & n_542; assign n_544 = n_541 & n_543; assign n_545 = i_23 & ~i_24; assign n_546 = i_22 & n_545; assign n_547 = n_544 & n_546; assign n_548 = ~n_539 & ~n_547; assign n_549 = x_252 & n_548; assign n_550 = ~x_252 & ~n_548; assign n_551 = ~n_549 & ~n_550; assign n_552 = x_251 & n_518; assign n_553 = ~x_251 & ~n_518; assign n_554 = ~n_552 & ~n_553; assign n_555 = ~x_249 & x_250; assign n_556 = x_249 & ~x_250; assign n_557 = ~n_555 & ~n_556; assign n_558 = x_248 & ~n_386; assign n_559 = ~x_248 & n_386; assign n_560 = ~n_558 & ~n_559; assign n_561 = x_218 & ~x_219; assign n_562 = ~x_222 & n_561; assign n_563 = n_311 & n_562; assign n_564 = ~n_369 & n_563; assign n_565 = x_247 & ~n_564; assign n_566 = ~x_247 & n_564; assign n_567 = ~n_565 & ~n_566; assign n_568 = ~x_244 & x_246; assign n_569 = x_244 & ~x_246; assign n_570 = ~n_568 & ~n_569; assign n_571 = x_243 & ~x_244; assign n_572 = ~n_520 & ~n_571; assign n_573 = n_489 & n_572; assign n_574 = x_245 & ~n_573; assign n_575 = ~x_245 & n_573; assign n_576 = ~n_574 & ~n_575; assign n_577 = n_62 & n_419; assign n_578 = n_418 & n_577; assign n_579 = x_244 & ~n_578; assign n_580 = ~x_244 & n_578; assign n_581 = ~n_579 & ~n_580; assign n_582 = ~x_242 & x_243; assign n_583 = x_242 & ~x_243; assign n_584 = ~n_582 & ~n_583; assign n_585 = ~x_241 & x_242; assign n_586 = x_241 & ~x_242; assign n_587 = ~n_585 & ~n_586; assign n_588 = ~x_240 & x_241; assign n_589 = x_240 & ~x_241; assign n_590 = ~n_588 & ~n_589; assign n_591 = x_231 & x_232; assign n_592 = n_369 & n_591; assign n_593 = n_394 & n_592; assign n_594 = ~n_591 & n_370; assign n_595 = ~n_593 & ~n_594; assign n_596 = x_234 & n_373; assign n_597 = ~x_234 & ~n_369; assign n_598 = n_333 & n_597; assign n_599 = ~n_596 & ~n_598; assign n_600 = n_595 & n_599; assign n_601 = n_369 & ~n_323; assign n_602 = ~n_369 & ~n_349; assign n_603 = ~n_602 & n_363; assign n_604 = ~n_601 & n_603; assign n_605 = x_236 & x_238; assign n_606 = x_237 & n_605; assign n_607 = x_235 & n_606; assign n_608 = ~x_239 & ~n_607; assign n_609 = n_604 & ~n_608; assign n_610 = ~n_600 & n_609; assign n_611 = x_240 & ~n_610; assign n_612 = ~x_240 & n_610; assign n_613 = ~n_611 & ~n_612; assign n_614 = ~n_504 & ~n_510; assign n_615 = ~n_502 & n_614; assign n_616 = x_239 & n_615; assign n_617 = ~x_239 & ~n_615; assign n_618 = ~n_616 & ~n_617; assign n_619 = ~x_209 & x_238; assign n_620 = x_209 & ~x_238; assign n_621 = ~n_619 & ~n_620; assign n_622 = ~x_211 & x_237; assign n_623 = x_211 & ~x_237; assign n_624 = ~n_622 & ~n_623; assign n_625 = ~x_210 & x_236; assign n_626 = x_210 & ~x_236; assign n_627 = ~n_625 & ~n_626; assign n_628 = x_235 & ~n_505; assign n_629 = ~x_235 & n_505; assign n_630 = ~n_628 & ~n_629; assign n_631 = ~x_233 & x_234; assign n_632 = x_233 & ~x_234; assign n_633 = ~n_631 & ~n_632; assign n_634 = n_321 & n_312; assign n_635 = n_383 & n_634; assign n_636 = x_233 & ~n_635; assign n_637 = ~x_233 & n_635; assign n_638 = ~n_636 & ~n_637; assign n_639 = x_232 & n_507; assign n_640 = ~x_232 & ~n_507; assign n_641 = ~n_639 & ~n_640; assign n_642 = ~x_230 & x_231; assign n_643 = x_230 & ~x_231; assign n_644 = ~n_642 & ~n_643; assign n_645 = n_343 & n_355; assign n_646 = n_314 & n_645; assign n_647 = x_230 & ~n_646; assign n_648 = ~x_230 & n_646; assign n_649 = ~n_647 & ~n_648; assign n_650 = n_507 & ~n_509; assign n_651 = x_229 & n_650; assign n_652 = ~x_229 & ~n_650; assign n_653 = ~n_651 & ~n_652; assign n_654 = ~n_374 & n_383; assign n_655 = x_228 & ~n_654; assign n_656 = ~x_228 & n_654; assign n_657 = ~n_655 & ~n_656; assign n_658 = ~x_173 & x_227; assign n_659 = x_173 & ~x_227; assign n_660 = ~n_658 & ~n_659; assign n_661 = ~x_175 & x_226; assign n_662 = x_175 & ~x_226; assign n_663 = ~n_661 & ~n_662; assign n_664 = ~x_174 & x_225; assign n_665 = x_174 & ~x_225; assign n_666 = ~n_664 & ~n_665; assign n_667 = ~x_172 & x_224; assign n_668 = x_172 & ~x_224; assign n_669 = ~n_667 & ~n_668; assign n_670 = ~x_171 & x_223; assign n_671 = x_171 & ~x_223; assign n_672 = ~n_670 & ~n_671; assign n_673 = ~x_179 & x_222; assign n_674 = x_179 & ~x_222; assign n_675 = ~n_673 & ~n_674; assign n_676 = ~x_176 & x_221; assign n_677 = x_176 & ~x_221; assign n_678 = ~n_676 & ~n_677; assign n_679 = ~x_177 & x_220; assign n_680 = x_177 & ~x_220; assign n_681 = ~n_679 & ~n_680; assign n_682 = ~x_178 & x_219; assign n_683 = x_178 & ~x_219; assign n_684 = ~n_682 & ~n_683; assign n_685 = ~x_180 & x_218; assign n_686 = x_180 & ~x_218; assign n_687 = ~n_685 & ~n_686; assign n_688 = x_217 & n_367; assign n_689 = ~x_217 & ~n_367; assign n_690 = ~n_688 & ~n_689; assign n_691 = x_216 & ~n_577; assign n_692 = ~x_216 & n_577; assign n_693 = ~n_691 & ~n_692; assign n_694 = x_215 & ~n_420; assign n_695 = ~x_215 & n_420; assign n_696 = ~n_694 & ~n_695; assign n_697 = x_179 & x_180; assign n_698 = ~n_403 & ~n_697; assign n_699 = ~x_176 & x_177; assign n_700 = ~n_699 & ~n_402; assign n_701 = ~x_178 & ~x_213; assign n_702 = x_178 & x_213; assign n_703 = ~n_701 & ~n_702; assign n_704 = n_700 & ~n_703; assign n_705 = ~n_700 & n_703; assign n_706 = ~n_704 & ~n_705; assign n_707 = n_698 & n_706; assign n_708 = ~n_698 & ~n_706; assign n_709 = ~n_707 & ~n_708; assign n_710 = x_214 & n_709; assign n_711 = ~x_214 & ~n_709; assign n_712 = ~n_710 & ~n_711; assign n_713 = ~x_260 & ~n_488; assign n_714 = ~x_252 & ~x_258; assign n_715 = ~n_713 & n_714; assign n_716 = ~n_520 & n_715; assign n_717 = n_716 & n_600; assign n_718 = x_221 & n_319; assign n_719 = ~n_311 & ~n_718; assign n_720 = ~x_267 & n_719; assign n_721 = x_267 & ~n_719; assign n_722 = ~n_720 & ~n_721; assign n_723 = n_717 & n_722; assign n_724 = x_213 & n_723; assign n_725 = ~x_213 & ~n_723; assign n_726 = ~n_724 & ~n_725; assign n_727 = x_208 & ~x_209; assign n_728 = ~x_208 & x_209; assign n_729 = ~n_727 & ~n_728; assign n_730 = x_210 & ~x_211; assign n_731 = ~x_210 & x_211; assign n_732 = ~n_730 & ~n_731; assign n_733 = n_729 & n_732; assign n_734 = ~n_729 & ~n_732; assign n_735 = ~n_733 & ~n_734; assign n_736 = x_212 & n_735; assign n_737 = ~x_212 & ~n_735; assign n_738 = ~n_736 & ~n_737; assign n_739 = ~x_237 & ~n_605; assign n_740 = ~n_739 & ~n_606; assign n_741 = n_716 & n_740; assign n_742 = x_211 & ~n_741; assign n_743 = ~x_211 & n_741; assign n_744 = ~n_742 & ~n_743; assign n_745 = ~x_236 & ~x_238; assign n_746 = n_716 & ~n_745; assign n_747 = x_210 & ~n_746; assign n_748 = ~x_210 & n_746; assign n_749 = ~n_747 & ~n_748; assign n_750 = x_209 & ~n_716; assign n_751 = ~x_209 & n_716; assign n_752 = ~n_750 & ~n_751; assign n_753 = ~x_236 & x_238; assign n_754 = ~x_261 & ~n_753; assign n_755 = x_261 & n_753; assign n_756 = ~n_754 & ~n_755; assign n_757 = n_716 & n_756; assign n_758 = x_208 & n_757; assign n_759 = ~x_208 & ~n_757; assign n_760 = ~n_758 & ~n_759; assign n_761 = x_174 & ~x_206; assign n_762 = ~x_174 & x_206; assign n_763 = ~n_761 & ~n_762; assign n_764 = ~x_171 & x_172; assign n_765 = x_171 & ~x_172; assign n_766 = ~n_764 & ~n_765; assign n_767 = x_173 & x_175; assign n_768 = ~x_173 & ~x_175; assign n_769 = ~n_767 & ~n_768; assign n_770 = n_766 & ~n_769; assign n_771 = ~n_766 & n_769; assign n_772 = ~n_770 & ~n_771; assign n_773 = n_763 & n_772; assign n_774 = ~n_763 & ~n_772; assign n_775 = ~n_773 & ~n_774; assign n_776 = x_207 & ~n_775; assign n_777 = ~x_207 & n_775; assign n_778 = ~n_776 & ~n_777; assign n_779 = n_716 & ~n_604; assign n_780 = x_225 & n_357; assign n_781 = ~n_323 & ~n_780; assign n_782 = ~x_268 & n_781; assign n_783 = x_268 & ~n_781; assign n_784 = ~n_782 & ~n_783; assign n_785 = n_779 & n_784; assign n_786 = x_206 & n_785; assign n_787 = ~x_206 & ~n_785; assign n_788 = ~n_786 & ~n_787; assign n_789 = ~x_160 & ~x_170; assign n_790 = ~x_194 & ~x_204; assign n_791 = n_789 & n_790; assign n_792 = ~i_26 & ~x_139; assign n_793 = ~x_145 & ~x_154; assign n_794 = n_792 & n_793; assign n_795 = n_791 & n_794; assign n_796 = x_205 & n_795; assign n_797 = ~x_205 & ~n_795; assign n_798 = ~n_796 & ~n_797; assign n_799 = ~x_196 & ~x_197; assign n_800 = x_196 & x_197; assign n_801 = ~n_799 & ~n_800; assign n_802 = x_198 & ~n_801; assign n_803 = ~x_198 & n_801; assign n_804 = ~n_802 & ~n_803; assign n_805 = ~x_202 & ~x_203; assign n_806 = x_202 & x_203; assign n_807 = ~n_805 & ~n_806; assign n_808 = x_201 & ~n_807; assign n_809 = ~x_201 & n_807; assign n_810 = ~n_808 & ~n_809; assign n_811 = ~x_199 & ~x_200; assign n_812 = x_199 & x_200; assign n_813 = ~n_811 & ~n_812; assign n_814 = n_810 & ~n_813; assign n_815 = ~n_810 & n_813; assign n_816 = ~n_814 & ~n_815; assign n_817 = n_804 & n_816; assign n_818 = ~n_804 & ~n_816; assign n_819 = ~n_817 & ~n_818; assign n_820 = x_195 & n_819; assign n_821 = ~x_195 & ~n_819; assign n_822 = ~n_820 & ~n_821; assign n_823 = x_204 & ~n_822; assign n_824 = ~x_204 & n_822; assign n_825 = ~n_823 & ~n_824; assign n_826 = x_174 & n_407; assign n_827 = n_826 & n_767; assign n_828 = x_175 & x_178; assign n_829 = ~x_179 & n_828; assign n_830 = ~n_827 & n_829; assign n_831 = ~x_174 & n_764; assign n_832 = n_767 & n_831; assign n_833 = x_180 & x_184; assign n_834 = n_699 & n_833; assign n_835 = ~x_180 & ~x_184; assign n_836 = n_402 & n_835; assign n_837 = ~n_834 & ~n_836; assign n_838 = ~n_832 & ~n_837; assign n_839 = n_830 & n_838; assign n_840 = ~n_507 & n_839; assign n_841 = n_3 & ~n_840; assign n_842 = x_203 & n_841; assign n_843 = ~x_203 & ~n_841; assign n_844 = ~n_842 & ~n_843; assign n_845 = n_9 & ~n_840; assign n_846 = x_202 & n_845; assign n_847 = ~x_202 & ~n_845; assign n_848 = ~n_846 & ~n_847; assign n_849 = n_15 & ~n_840; assign n_850 = x_201 & n_849; assign n_851 = ~x_201 & ~n_849; assign n_852 = ~n_850 & ~n_851; assign n_853 = n_148 & ~n_840; assign n_854 = x_200 & n_853; assign n_855 = ~x_200 & ~n_853; assign n_856 = ~n_854 & ~n_855; assign n_857 = n_27 & ~n_840; assign n_858 = x_199 & n_857; assign n_859 = ~x_199 & ~n_857; assign n_860 = ~n_858 & ~n_859; assign n_861 = n_33 & ~n_840; assign n_862 = x_198 & n_861; assign n_863 = ~x_198 & ~n_861; assign n_864 = ~n_862 & ~n_863; assign n_865 = n_39 & ~n_840; assign n_866 = x_197 & n_865; assign n_867 = ~x_197 & ~n_865; assign n_868 = ~n_866 & ~n_867; assign n_869 = n_45 & ~n_840; assign n_870 = x_196 & n_869; assign n_871 = ~x_196 & ~n_869; assign n_872 = ~n_870 & ~n_871; assign n_873 = n_21 & ~n_840; assign n_874 = x_195 & n_873; assign n_875 = ~x_195 & ~n_873; assign n_876 = ~n_874 & ~n_875; assign n_877 = ~x_185 & ~x_186; assign n_878 = x_185 & x_186; assign n_879 = ~n_877 & ~n_878; assign n_880 = x_187 & ~n_879; assign n_881 = ~x_187 & n_879; assign n_882 = ~n_880 & ~n_881; assign n_883 = ~x_191 & ~x_192; assign n_884 = x_191 & x_192; assign n_885 = ~n_883 & ~n_884; assign n_886 = x_190 & ~n_885; assign n_887 = ~x_190 & n_885; assign n_888 = ~n_886 & ~n_887; assign n_889 = ~x_188 & ~x_189; assign n_890 = x_188 & x_189; assign n_891 = ~n_889 & ~n_890; assign n_892 = n_888 & ~n_891; assign n_893 = ~n_888 & n_891; assign n_894 = ~n_892 & ~n_893; assign n_895 = n_882 & n_894; assign n_896 = ~n_882 & ~n_894; assign n_897 = ~n_895 & ~n_896; assign n_898 = x_193 & n_897; assign n_899 = ~x_193 & ~n_897; assign n_900 = ~n_898 & ~n_899; assign n_901 = x_194 & ~n_900; assign n_902 = ~x_194 & n_900; assign n_903 = ~n_901 & ~n_902; assign n_904 = n_545 & n_538; assign n_905 = ~i_23 & i_24; assign n_906 = i_22 & n_905; assign n_907 = n_544 & n_906; assign n_908 = ~n_904 & ~n_907; assign n_909 = i_9 & ~n_908; assign n_910 = ~n_840 & ~n_909; assign n_911 = x_193 & n_910; assign n_912 = ~x_193 & ~n_910; assign n_913 = ~n_911 & ~n_912; assign n_914 = i_5 & ~n_908; assign n_915 = ~n_840 & ~n_914; assign n_916 = x_192 & n_915; assign n_917 = ~x_192 & ~n_915; assign n_918 = ~n_916 & ~n_917; assign n_919 = i_6 & ~n_908; assign n_920 = ~n_840 & ~n_919; assign n_921 = x_191 & n_920; assign n_922 = ~x_191 & ~n_920; assign n_923 = ~n_921 & ~n_922; assign n_924 = i_4 & ~n_908; assign n_925 = ~n_840 & ~n_924; assign n_926 = x_190 & n_925; assign n_927 = ~x_190 & ~n_925; assign n_928 = ~n_926 & ~n_927; assign n_929 = i_8 & ~n_908; assign n_930 = ~n_840 & ~n_929; assign n_931 = x_189 & n_930; assign n_932 = ~x_189 & ~n_930; assign n_933 = ~n_931 & ~n_932; assign n_934 = i_7 & ~n_908; assign n_935 = ~n_840 & ~n_934; assign n_936 = x_188 & n_935; assign n_937 = ~x_188 & ~n_935; assign n_938 = ~n_936 & ~n_937; assign n_939 = i_2 & ~n_908; assign n_940 = ~n_840 & ~n_939; assign n_941 = x_187 & n_940; assign n_942 = ~x_187 & ~n_940; assign n_943 = ~n_941 & ~n_942; assign n_944 = i_3 & ~n_908; assign n_945 = ~n_840 & ~n_944; assign n_946 = x_186 & n_945; assign n_947 = ~x_186 & ~n_945; assign n_948 = ~n_946 & ~n_947; assign n_949 = i_1 & ~n_908; assign n_950 = ~n_949 & ~n_840; assign n_951 = x_185 & n_950; assign n_952 = ~x_185 & ~n_950; assign n_953 = ~n_951 & ~n_952; assign n_954 = x_184 & n_369; assign n_955 = ~x_184 & ~n_369; assign n_956 = ~n_954 & ~n_955; assign n_957 = x_134 & x_255; assign n_958 = n_957 & n_418; assign n_959 = x_183 & ~n_958; assign n_960 = ~x_183 & n_958; assign n_961 = ~n_959 & ~n_960; assign n_962 = x_264 & ~x_266; assign n_963 = ~n_415 & n_962; assign n_964 = x_182 & ~n_963; assign n_965 = ~x_182 & n_963; assign n_966 = ~n_964 & ~n_965; assign n_967 = x_181 & ~n_957; assign n_968 = ~x_181 & n_957; assign n_969 = ~n_967 & ~n_968; assign n_970 = x_218 & ~n_331; assign n_971 = n_319 & n_320; assign n_972 = ~n_970 & ~n_971; assign n_973 = n_717 & ~n_972; assign n_974 = x_180 & ~n_973; assign n_975 = ~x_180 & n_973; assign n_976 = ~n_974 & ~n_975; assign n_977 = x_222 & ~n_332; assign n_978 = ~n_333 & ~n_977; assign n_979 = n_717 & ~n_978; assign n_980 = x_179 & ~n_979; assign n_981 = ~x_179 & n_979; assign n_982 = ~n_980 & ~n_981; assign n_983 = ~x_219 & ~n_320; assign n_984 = ~n_331 & ~n_983; assign n_985 = n_717 & n_984; assign n_986 = x_178 & ~n_985; assign n_987 = ~x_178 & n_985; assign n_988 = ~n_986 & ~n_987; assign n_989 = n_717 & ~n_385; assign n_990 = x_177 & ~n_989; assign n_991 = ~x_177 & n_989; assign n_992 = ~n_990 & ~n_991; assign n_993 = x_176 & ~n_717; assign n_994 = ~x_176 & n_717; assign n_995 = ~n_993 & ~n_994; assign n_996 = n_345 & n_324; assign n_997 = x_226 & ~n_996; assign n_998 = n_345 & n_325; assign n_999 = ~n_997 & ~n_998; assign n_1000 = n_779 & ~n_999; assign n_1001 = x_175 & ~n_1000; assign n_1002 = ~x_175 & n_1000; assign n_1003 = ~n_1001 & ~n_1002; assign n_1004 = x_174 & ~n_779; assign n_1005 = ~x_174 & n_779; assign n_1006 = ~n_1004 & ~n_1005; assign n_1007 = x_223 & ~n_345; assign n_1008 = ~n_362 & ~n_357; assign n_1009 = ~n_1007 & n_1008; assign n_1010 = ~n_345 & n_357; assign n_1011 = ~n_1009 & ~n_1010; assign n_1012 = n_779 & n_1011; assign n_1013 = x_173 & ~n_1012; assign n_1014 = ~x_173 & n_1012; assign n_1015 = ~n_1013 & ~n_1014; assign n_1016 = n_779 & ~n_343; assign n_1017 = x_172 & ~n_1016; assign n_1018 = ~x_172 & n_1016; assign n_1019 = ~n_1017 & ~n_1018; assign n_1020 = ~x_223 & n_345; assign n_1021 = ~n_1007 & ~n_1020; assign n_1022 = ~n_1021 & n_779; assign n_1023 = x_171 & ~n_1022; assign n_1024 = ~x_171 & n_1022; assign n_1025 = ~n_1023 & ~n_1024; assign n_1026 = x_163 & ~x_167; assign n_1027 = ~x_163 & x_167; assign n_1028 = ~n_1026 & ~n_1027; assign n_1029 = ~x_164 & ~x_165; assign n_1030 = x_164 & x_165; assign n_1031 = ~n_1029 & ~n_1030; assign n_1032 = x_166 & n_1031; assign n_1033 = ~x_166 & ~n_1031; assign n_1034 = ~n_1032 & ~n_1033; assign n_1035 = ~x_161 & ~x_162; assign n_1036 = x_161 & x_162; assign n_1037 = ~n_1035 & ~n_1036; assign n_1038 = x_168 & ~x_169; assign n_1039 = ~x_168 & x_169; assign n_1040 = ~n_1038 & ~n_1039; assign n_1041 = n_1037 & n_1040; assign n_1042 = ~n_1037 & ~n_1040; assign n_1043 = ~n_1041 & ~n_1042; assign n_1044 = n_1034 & ~n_1043; assign n_1045 = ~n_1034 & n_1043; assign n_1046 = ~n_1044 & ~n_1045; assign n_1047 = n_1028 & n_1046; assign n_1048 = ~n_1028 & ~n_1046; assign n_1049 = ~n_1047 & ~n_1048; assign n_1050 = x_170 & ~n_1049; assign n_1051 = ~x_170 & n_1049; assign n_1052 = ~n_1050 & ~n_1051; assign n_1053 = n_89 & n_419; assign n_1054 = x_272 & n_1053; assign n_1055 = x_271 & n_1054; assign n_1056 = x_274 & n_1055; assign n_1057 = x_275 & n_1056; assign n_1058 = n_905 & n_538; assign n_1059 = ~i_22 & n_545; assign n_1060 = n_1059 & n_544; assign n_1061 = ~n_1058 & ~n_1060; assign n_1062 = ~x_275 & ~n_1056; assign n_1063 = n_1061 & ~n_1062; assign n_1064 = ~n_1057 & n_1063; assign n_1065 = i_14 & n_1058; assign n_1066 = i_5 & n_1060; assign n_1067 = ~n_1065 & ~n_1066; assign n_1068 = ~n_1064 & n_1067; assign n_1069 = x_169 & n_1068; assign n_1070 = ~x_169 & ~n_1068; assign n_1071 = ~n_1069 & ~n_1070; assign n_1072 = ~x_274 & ~n_1055; assign n_1073 = n_1061 & ~n_1056; assign n_1074 = ~n_1072 & n_1073; assign n_1075 = i_15 & n_1058; assign n_1076 = i_6 & n_1060; assign n_1077 = ~n_1075 & ~n_1076; assign n_1078 = ~n_1074 & n_1077; assign n_1079 = x_168 & n_1078; assign n_1080 = ~x_168 & ~n_1078; assign n_1081 = ~n_1079 & ~n_1080; assign n_1082 = i_13 & n_1058; assign n_1083 = i_4 & n_1060; assign n_1084 = ~n_1082 & ~n_1083; assign n_1085 = x_167 & n_1084; assign n_1086 = ~x_167 & ~n_1084; assign n_1087 = ~n_1085 & ~n_1086; assign n_1088 = ~x_272 & ~n_1053; assign n_1089 = ~n_1054 & ~n_1088; assign n_1090 = n_1061 & n_1089; assign n_1091 = i_8 & n_1060; assign n_1092 = i_17 & n_1058; assign n_1093 = ~n_1091 & ~n_1092; assign n_1094 = ~n_1090 & n_1093; assign n_1095 = x_166 & n_1094; assign n_1096 = ~x_166 & ~n_1094; assign n_1097 = ~n_1095 & ~n_1096; assign n_1098 = x_271 & ~x_274; assign n_1099 = x_272 & ~n_1098; assign n_1100 = n_1053 & ~n_1099; assign n_1101 = x_273 & n_1100; assign n_1102 = ~x_273 & ~n_1100; assign n_1103 = ~n_1101 & ~n_1102; assign n_1104 = n_1061 & n_1103; assign n_1105 = i_9 & n_1060; assign n_1106 = i_18 & n_1058; assign n_1107 = ~n_1105 & ~n_1106; assign n_1108 = ~n_1104 & n_1107; assign n_1109 = x_165 & n_1108; assign n_1110 = ~x_165 & ~n_1108; assign n_1111 = ~n_1109 & ~n_1110; assign n_1112 = ~x_271 & ~n_1054; assign n_1113 = ~n_1112 & ~n_1055; assign n_1114 = n_1061 & n_1113; assign n_1115 = i_16 & n_1058; assign n_1116 = i_7 & n_1060; assign n_1117 = ~n_1115 & ~n_1116; assign n_1118 = ~n_1114 & n_1117; assign n_1119 = x_164 & n_1118; assign n_1120 = ~x_164 & ~n_1118; assign n_1121 = ~n_1119 & ~n_1120; assign n_1122 = i_11 & n_1058; assign n_1123 = i_2 & n_1060; assign n_1124 = ~n_1122 & ~n_1123; assign n_1125 = x_163 & n_1124; assign n_1126 = ~x_163 & ~n_1124; assign n_1127 = ~n_1125 & ~n_1126; assign n_1128 = i_3 & n_1060; assign n_1129 = i_12 & n_1058; assign n_1130 = ~n_1128 & ~n_1129; assign n_1131 = x_162 & n_1130; assign n_1132 = ~x_162 & ~n_1130; assign n_1133 = ~n_1131 & ~n_1132; assign n_1134 = i_1 & n_1060; assign n_1135 = i_10 & n_1058; assign n_1136 = ~n_1134 & ~n_1135; assign n_1137 = x_161 & n_1136; assign n_1138 = ~x_161 & ~n_1136; assign n_1139 = ~n_1137 & ~n_1138; assign n_1140 = x_159 & ~n_51; assign n_1141 = ~x_159 & n_51; assign n_1142 = ~n_1140 & ~n_1141; assign n_1143 = ~x_155 & ~x_156; assign n_1144 = x_155 & x_156; assign n_1145 = ~n_1143 & ~n_1144; assign n_1146 = x_157 & n_1145; assign n_1147 = ~x_157 & ~n_1145; assign n_1148 = ~n_1146 & ~n_1147; assign n_1149 = x_158 & ~n_63; assign n_1150 = ~x_158 & n_63; assign n_1151 = ~n_1149 & ~n_1150; assign n_1152 = n_1148 & ~n_1151; assign n_1153 = ~n_1148 & n_1151; assign n_1154 = ~n_1152 & ~n_1153; assign n_1155 = n_1142 & n_1154; assign n_1156 = ~n_1142 & ~n_1154; assign n_1157 = ~n_1155 & ~n_1156; assign n_1158 = x_160 & ~n_1157; assign n_1159 = ~x_160 & n_1157; assign n_1160 = ~n_1158 & ~n_1159; assign n_1161 = ~i_22 & n_541; assign n_1162 = n_1161 & n_543; assign n_1163 = n_533 & n_1162; assign n_1164 = ~n_1058 & ~n_1163; assign n_1165 = n_61 & n_419; assign n_1166 = x_269 & n_1165; assign n_1167 = ~x_269 & ~n_1165; assign n_1168 = ~n_1166 & ~n_1167; assign n_1169 = n_1164 & n_1168; assign n_1170 = i_4 & ~n_1164; assign n_1171 = ~n_1169 & ~n_1170; assign n_1172 = x_159 & n_1171; assign n_1173 = ~x_159 & ~n_1171; assign n_1174 = ~n_1172 & ~n_1173; assign n_1175 = x_270 & ~x_276; assign n_1176 = x_269 & ~n_1175; assign n_1177 = n_1165 & ~n_1176; assign n_1178 = x_277 & ~n_1177; assign n_1179 = ~x_277 & n_1177; assign n_1180 = ~n_1178 & ~n_1179; assign n_1181 = n_1164 & ~n_1180; assign n_1182 = i_9 & ~n_1164; assign n_1183 = ~n_1181 & ~n_1182; assign n_1184 = x_158 & n_1183; assign n_1185 = ~x_158 & ~n_1183; assign n_1186 = ~n_1184 & ~n_1185; assign n_1187 = x_270 & n_1166; assign n_1188 = ~x_276 & ~n_1187; assign n_1189 = x_276 & n_1187; assign n_1190 = n_1164 & ~n_1189; assign n_1191 = ~n_1188 & n_1190; assign n_1192 = i_2 & ~n_1164; assign n_1193 = ~n_1191 & ~n_1192; assign n_1194 = x_157 & n_1193; assign n_1195 = ~x_157 & ~n_1193; assign n_1196 = ~n_1194 & ~n_1195; assign n_1197 = ~x_270 & ~n_1166; assign n_1198 = ~n_1187 & ~n_1197; assign n_1199 = n_1164 & n_1198; assign n_1200 = i_3 & ~n_1164; assign n_1201 = ~n_1199 & ~n_1200; assign n_1202 = x_156 & n_1201; assign n_1203 = ~x_156 & ~n_1201; assign n_1204 = ~n_1202 & ~n_1203; assign n_1205 = x_278 & ~n_1189; assign n_1206 = ~x_278 & n_1189; assign n_1207 = ~n_1205 & ~n_1206; assign n_1208 = n_1164 & ~n_1207; assign n_1209 = i_1 & ~n_1164; assign n_1210 = ~n_1208 & ~n_1209; assign n_1211 = x_155 & n_1210; assign n_1212 = ~x_155 & ~n_1210; assign n_1213 = ~n_1211 & ~n_1212; assign n_1214 = ~x_146 & ~x_147; assign n_1215 = x_146 & x_147; assign n_1216 = ~n_1214 & ~n_1215; assign n_1217 = x_148 & ~n_1216; assign n_1218 = ~x_148 & n_1216; assign n_1219 = ~n_1217 & ~n_1218; assign n_1220 = ~x_151 & ~x_152; assign n_1221 = x_151 & x_152; assign n_1222 = ~n_1220 & ~n_1221; assign n_1223 = x_153 & n_1222; assign n_1224 = ~x_153 & ~n_1222; assign n_1225 = ~n_1223 & ~n_1224; assign n_1226 = ~x_128 & ~x_149; assign n_1227 = x_128 & x_149; assign n_1228 = ~n_1226 & ~n_1227; assign n_1229 = x_150 & n_1228; assign n_1230 = ~x_150 & ~n_1228; assign n_1231 = ~n_1229 & ~n_1230; assign n_1232 = n_1225 & ~n_1231; assign n_1233 = ~n_1225 & n_1231; assign n_1234 = ~n_1232 & ~n_1233; assign n_1235 = n_1219 & n_1234; assign n_1236 = ~n_1219 & ~n_1234; assign n_1237 = ~n_1235 & ~n_1236; assign n_1238 = x_154 & n_1237; assign n_1239 = ~x_154 & ~n_1237; assign n_1240 = ~n_1238 & ~n_1239; assign n_1241 = x_122 & n_261; assign n_1242 = ~x_122 & ~n_261; assign n_1243 = ~n_1241 & ~n_1242; assign n_1244 = x_64 & ~x_66; assign n_1245 = ~x_65 & n_1244; assign n_1246 = ~x_40 & x_42; assign n_1247 = x_43 & ~x_59; assign n_1248 = x_61 & ~x_123; assign n_1249 = n_1247 & n_1248; assign n_1250 = n_1246 & n_1249; assign n_1251 = x_41 & x_58; assign n_1252 = ~x_41 & ~x_58; assign n_1253 = ~n_1251 & ~n_1252; assign n_1254 = ~n_1253 & n_1245; assign n_1255 = n_1250 & n_1254; assign n_1256 = n_1245 & ~n_1255; assign n_1257 = x_121 & ~n_1256; assign n_1258 = ~x_121 & n_1256; assign n_1259 = ~n_1257 & ~n_1258; assign n_1260 = ~i_35 & x_125; assign n_1261 = ~x_70 & ~n_1260; assign n_1262 = x_73 & n_1261; assign n_1263 = x_120 & ~n_1262; assign n_1264 = ~x_120 & n_1262; assign n_1265 = ~n_1263 & ~n_1264; assign n_1266 = i_22 & i_31; assign n_1267 = n_534 & n_1266; assign n_1268 = i_30 & n_1267; assign n_1269 = ~x_118 & n_533; assign n_1270 = n_1268 & n_1269; assign n_1271 = ~i_24 & ~x_118; assign n_1272 = n_119 & n_1271; assign n_1273 = i_23 & i_29; assign n_1274 = i_22 & n_1273; assign n_1275 = n_541 & n_1274; assign n_1276 = n_1272 & n_1275; assign n_1277 = ~n_1270 & ~n_1276; assign n_1278 = x_119 & n_1277; assign n_1279 = ~x_119 & ~n_1277; assign n_1280 = ~n_1278 & ~n_1279; assign n_1281 = x_70 & ~x_117; assign n_1282 = x_124 & ~n_1260; assign n_1283 = ~n_1281 & n_1282; assign n_1284 = ~n_1255 & n_1283; assign n_1285 = x_118 & ~n_1284; assign n_1286 = ~x_118 & n_1284; assign n_1287 = ~n_1285 & ~n_1286; assign n_1288 = x_120 & n_155; assign n_1289 = n_1288 & n_153; assign n_1290 = n_286 & n_1289; assign n_1291 = x_117 & ~n_1290; assign n_1292 = ~x_117 & n_1290; assign n_1293 = ~n_1291 & ~n_1292; assign n_1294 = ~x_119 & n_1261; assign n_1295 = x_66 & x_123; assign n_1296 = ~x_66 & ~x_123; assign n_1297 = ~n_1295 & ~n_1296; assign n_1298 = x_64 & ~x_65; assign n_1299 = ~n_1297 & n_1298; assign n_1300 = n_1294 & ~n_1299; assign n_1301 = x_62 & ~x_63; assign n_1302 = ~n_1244 & ~n_1301; assign n_1303 = ~x_67 & ~n_1302; assign n_1304 = x_67 & n_1302; assign n_1305 = ~n_1303 & ~n_1304; assign n_1306 = n_1300 & ~n_1305; assign n_1307 = x_116 & n_1306; assign n_1308 = ~x_116 & ~n_1306; assign n_1309 = ~n_1307 & ~n_1308; assign n_1310 = x_126 & n_1294; assign n_1311 = x_115 & n_1310; assign n_1312 = ~x_115 & ~n_1310; assign n_1313 = ~n_1311 & ~n_1312; assign n_1314 = n_1268 & n_1271; assign n_1315 = i_23 & n_1314; assign n_1316 = ~x_118 & n_905; assign n_1317 = i_22 & i_29; assign n_1318 = n_1316 & n_1317; assign n_1319 = n_119 & n_541; assign n_1320 = n_1318 & n_1319; assign n_1321 = ~n_1315 & ~n_1320; assign n_1322 = x_114 & n_1321; assign n_1323 = ~x_114 & ~n_1321; assign n_1324 = ~n_1322 & ~n_1323; assign n_1325 = ~x_64 & x_66; assign n_1326 = ~n_1244 & ~n_1325; assign n_1327 = n_1300 & ~n_1326; assign n_1328 = x_113 & ~n_1327; assign n_1329 = ~x_113 & n_1327; assign n_1330 = ~n_1328 & ~n_1329; assign n_1331 = x_64 & x_66; assign n_1332 = ~x_65 & ~n_1331; assign n_1333 = x_65 & n_1331; assign n_1334 = ~n_1332 & ~n_1333; assign n_1335 = n_1300 & n_1334; assign n_1336 = x_112 & ~n_1335; assign n_1337 = ~x_112 & n_1335; assign n_1338 = ~n_1336 & ~n_1337; assign n_1339 = x_63 & ~x_64; assign n_1340 = n_1294 & n_1339; assign n_1341 = x_111 & ~n_1340; assign n_1342 = ~x_111 & n_1340; assign n_1343 = ~n_1341 & ~n_1342; assign n_1344 = x_62 & n_1300; assign n_1345 = x_110 & ~n_1344; assign n_1346 = ~x_110 & n_1344; assign n_1347 = ~n_1345 & ~n_1346; assign n_1348 = x_109 & ~n_1300; assign n_1349 = ~x_109 & n_1300; assign n_1350 = ~n_1348 & ~n_1349; assign n_1351 = x_58 & x_59; assign n_1352 = x_61 & ~n_1351; assign n_1353 = ~x_61 & n_1351; assign n_1354 = ~n_1352 & ~n_1353; assign n_1355 = n_1294 & ~n_1354; assign n_1356 = x_108 & ~n_1355; assign n_1357 = ~x_108 & n_1355; assign n_1358 = ~n_1356 & ~n_1357; assign n_1359 = ~x_58 & ~x_59; assign n_1360 = ~n_1351 & ~n_1359; assign n_1361 = n_1294 & n_1360; assign n_1362 = x_107 & ~n_1361; assign n_1363 = ~x_107 & n_1361; assign n_1364 = ~n_1362 & ~n_1363; assign n_1365 = x_60 & n_1294; assign n_1366 = x_106 & ~n_1365; assign n_1367 = ~x_106 & n_1365; assign n_1368 = ~n_1366 & ~n_1367; assign n_1369 = x_122 & n_1294; assign n_1370 = x_105 & ~n_1369; assign n_1371 = ~x_105 & n_1369; assign n_1372 = ~n_1370 & ~n_1371; assign n_1373 = x_104 & ~n_1294; assign n_1374 = ~x_104 & n_1294; assign n_1375 = ~n_1373 & ~n_1374; assign n_1376 = n_274 & n_1288; assign n_1377 = x_55 & n_1376; assign n_1378 = x_53 & n_1377; assign n_1379 = x_56 & n_1378; assign n_1380 = x_57 & n_1379; assign n_1381 = n_1268 & n_1316; assign n_1382 = n_542 & n_1161; assign n_1383 = ~x_118 & n_1382; assign n_1384 = n_1383 & n_545; assign n_1385 = ~n_1381 & ~n_1384; assign n_1386 = ~x_57 & ~n_1379; assign n_1387 = n_1385 & ~n_1386; assign n_1388 = ~n_1380 & n_1387; assign n_1389 = i_14 & n_1381; assign n_1390 = i_5 & n_1384; assign n_1391 = ~n_1389 & ~n_1390; assign n_1392 = ~n_1388 & n_1391; assign n_1393 = x_103 & n_1392; assign n_1394 = ~x_103 & ~n_1392; assign n_1395 = ~n_1393 & ~n_1394; assign n_1396 = ~x_56 & ~n_1378; assign n_1397 = ~n_1396 & ~n_1379; assign n_1398 = n_1385 & n_1397; assign n_1399 = i_15 & n_1381; assign n_1400 = i_6 & n_1384; assign n_1401 = ~n_1399 & ~n_1400; assign n_1402 = ~n_1398 & n_1401; assign n_1403 = x_102 & n_1402; assign n_1404 = ~x_102 & ~n_1402; assign n_1405 = ~n_1403 & ~n_1404; assign n_1406 = i_4 & n_1384; assign n_1407 = i_13 & n_1381; assign n_1408 = ~n_1406 & ~n_1407; assign n_1409 = x_101 & n_1408; assign n_1410 = ~x_101 & ~n_1408; assign n_1411 = ~n_1409 & ~n_1410; assign n_1412 = ~x_55 & ~n_1376; assign n_1413 = ~n_1377 & ~n_1412; assign n_1414 = n_1385 & n_1413; assign n_1415 = i_8 & n_1384; assign n_1416 = i_17 & n_1381; assign n_1417 = ~n_1415 & ~n_1416; assign n_1418 = ~n_1414 & n_1417; assign n_1419 = x_100 & n_1418; assign n_1420 = ~x_100 & ~n_1418; assign n_1421 = ~n_1419 & ~n_1420; assign n_1422 = x_53 & ~x_56; assign n_1423 = x_55 & ~n_1422; assign n_1424 = n_1376 & ~n_1423; assign n_1425 = ~x_54 & ~n_1424; assign n_1426 = x_54 & n_1424; assign n_1427 = ~n_1425 & ~n_1426; assign n_1428 = n_1385 & n_1427; assign n_1429 = i_18 & n_1381; assign n_1430 = i_9 & n_1384; assign n_1431 = ~n_1429 & ~n_1430; assign n_1432 = ~n_1428 & n_1431; assign n_1433 = x_99 & n_1432; assign n_1434 = ~x_99 & ~n_1432; assign n_1435 = ~n_1433 & ~n_1434; assign n_1436 = ~x_53 & ~n_1377; assign n_1437 = ~n_1378 & ~n_1436; assign n_1438 = n_1385 & n_1437; assign n_1439 = i_16 & n_1381; assign n_1440 = i_7 & n_1384; assign n_1441 = ~n_1439 & ~n_1440; assign n_1442 = ~n_1438 & n_1441; assign n_1443 = x_98 & n_1442; assign n_1444 = ~x_98 & ~n_1442; assign n_1445 = ~n_1443 & ~n_1444; assign n_1446 = i_2 & n_1384; assign n_1447 = i_11 & n_1381; assign n_1448 = ~n_1446 & ~n_1447; assign n_1449 = x_97 & n_1448; assign n_1450 = ~x_97 & ~n_1448; assign n_1451 = ~n_1449 & ~n_1450; assign n_1452 = i_3 & n_1384; assign n_1453 = i_12 & n_1381; assign n_1454 = ~n_1452 & ~n_1453; assign n_1455 = x_96 & n_1454; assign n_1456 = ~x_96 & ~n_1454; assign n_1457 = ~n_1455 & ~n_1456; assign n_1458 = i_1 & n_1384; assign n_1459 = i_10 & n_1381; assign n_1460 = ~n_1458 & ~n_1459; assign n_1461 = x_95 & n_1460; assign n_1462 = ~x_95 & ~n_1460; assign n_1463 = ~n_1461 & ~n_1462; assign n_1464 = n_1382 & n_1269; assign n_1465 = ~n_1381 & ~n_1464; assign n_1466 = i_4 & ~n_1465; assign n_1467 = n_152 & n_1288; assign n_1468 = x_52 & n_1467; assign n_1469 = ~x_52 & ~n_1467; assign n_1470 = ~n_1468 & ~n_1469; assign n_1471 = n_1465 & n_1470; assign n_1472 = ~n_1466 & ~n_1471; assign n_1473 = x_94 & n_1472; assign n_1474 = ~x_94 & ~n_1472; assign n_1475 = ~n_1473 & ~n_1474; assign n_1476 = ~i_9 & ~n_1465; assign n_1477 = x_49 & ~x_50; assign n_1478 = x_52 & ~n_1477; assign n_1479 = n_1467 & ~n_1478; assign n_1480 = x_51 & ~n_1479; assign n_1481 = ~x_51 & n_1479; assign n_1482 = ~n_1480 & ~n_1481; assign n_1483 = n_1465 & n_1482; assign n_1484 = ~n_1476 & ~n_1483; assign n_1485 = x_93 & ~n_1484; assign n_1486 = ~x_93 & n_1484; assign n_1487 = ~n_1485 & ~n_1486; assign n_1488 = i_2 & ~n_1465; assign n_1489 = x_49 & n_1468; assign n_1490 = ~x_50 & ~n_1489; assign n_1491 = x_50 & n_1489; assign n_1492 = n_1465 & ~n_1491; assign n_1493 = ~n_1490 & n_1492; assign n_1494 = ~n_1488 & ~n_1493; assign n_1495 = x_92 & n_1494; assign n_1496 = ~x_92 & ~n_1494; assign n_1497 = ~n_1495 & ~n_1496; assign n_1498 = i_3 & ~n_1465; assign n_1499 = ~x_49 & ~n_1468; assign n_1500 = ~n_1489 & ~n_1499; assign n_1501 = n_1465 & n_1500; assign n_1502 = ~n_1498 & ~n_1501; assign n_1503 = x_91 & n_1502; assign n_1504 = ~x_91 & ~n_1502; assign n_1505 = ~n_1503 & ~n_1504; assign n_1506 = x_48 & ~n_1491; assign n_1507 = ~x_48 & n_1491; assign n_1508 = ~n_1506 & ~n_1507; assign n_1509 = n_1465 & ~n_1508; assign n_1510 = i_1 & ~n_1465; assign n_1511 = ~n_1509 & ~n_1510; assign n_1512 = x_90 & n_1511; assign n_1513 = ~x_90 & ~n_1511; assign n_1514 = ~n_1512 & ~n_1513; assign n_1515 = x_89 & n_3; assign n_1516 = ~x_89 & ~n_3; assign n_1517 = ~n_1515 & ~n_1516; assign n_1518 = x_88 & n_9; assign n_1519 = ~x_88 & ~n_9; assign n_1520 = ~n_1518 & ~n_1519; assign n_1521 = x_87 & n_15; assign n_1522 = ~x_87 & ~n_15; assign n_1523 = ~n_1521 & ~n_1522; assign n_1524 = x_86 & n_21; assign n_1525 = ~x_86 & ~n_21; assign n_1526 = ~n_1524 & ~n_1525; assign n_1527 = x_85 & n_27; assign n_1528 = ~x_85 & ~n_27; assign n_1529 = ~n_1527 & ~n_1528; assign n_1530 = x_84 & n_33; assign n_1531 = ~x_84 & ~n_33; assign n_1532 = ~n_1530 & ~n_1531; assign n_1533 = x_83 & n_39; assign n_1534 = ~x_83 & ~n_39; assign n_1535 = ~n_1533 & ~n_1534; assign n_1536 = x_82 & n_45; assign n_1537 = ~x_82 & ~n_45; assign n_1538 = ~n_1536 & ~n_1537; assign n_1539 = ~i_34 & ~x_45; assign n_1540 = x_81 & ~n_1539; assign n_1541 = ~x_81 & n_1539; assign n_1542 = ~n_1540 & ~n_1541; assign n_1543 = x_80 & ~n_276; assign n_1544 = ~x_80 & n_276; assign n_1545 = ~n_1543 & ~n_1544; assign n_1546 = x_79 & n_148; assign n_1547 = ~x_79 & ~n_148; assign n_1548 = ~n_1546 & ~n_1547; assign n_1549 = ~x_77 & x_78; assign n_1550 = x_77 & ~x_78; assign n_1551 = ~n_1549 & ~n_1550; assign n_1552 = ~x_76 & x_77; assign n_1553 = x_76 & ~x_77; assign n_1554 = ~n_1552 & ~n_1553; assign n_1555 = ~x_75 & x_76; assign n_1556 = x_75 & ~x_76; assign n_1557 = ~n_1555 & ~n_1556; assign n_1558 = ~x_74 & x_75; assign n_1559 = x_74 & ~x_75; assign n_1560 = ~n_1558 & ~n_1559; assign n_1561 = ~x_70 & x_74; assign n_1562 = x_70 & ~x_74; assign n_1563 = ~n_1561 & ~n_1562; assign n_1564 = ~x_72 & x_73; assign n_1565 = x_72 & ~x_73; assign n_1566 = ~n_1564 & ~n_1565; assign n_1567 = x_72 & ~x_119; assign n_1568 = ~x_72 & x_119; assign n_1569 = ~n_1567 & ~n_1568; assign n_1570 = ~x_69 & x_70; assign n_1571 = x_69 & ~x_70; assign n_1572 = ~n_1570 & ~n_1571; assign n_1573 = ~x_68 & x_69; assign n_1574 = x_68 & ~x_69; assign n_1575 = ~n_1573 & ~n_1574; assign n_1576 = x_68 & ~x_71; assign n_1577 = ~x_68 & x_71; assign n_1578 = ~n_1576 & ~n_1577; assign n_1579 = x_67 & ~x_116; assign n_1580 = ~x_67 & x_116; assign n_1581 = ~n_1579 & ~n_1580; assign n_1582 = x_66 & ~x_113; assign n_1583 = ~x_66 & x_113; assign n_1584 = ~n_1582 & ~n_1583; assign n_1585 = x_65 & ~x_112; assign n_1586 = ~x_65 & x_112; assign n_1587 = ~n_1585 & ~n_1586; assign n_1588 = x_64 & ~x_111; assign n_1589 = ~x_64 & x_111; assign n_1590 = ~n_1588 & ~n_1589; assign n_1591 = x_63 & ~x_110; assign n_1592 = ~x_63 & x_110; assign n_1593 = ~n_1591 & ~n_1592; assign n_1594 = x_62 & ~x_109; assign n_1595 = ~x_62 & x_109; assign n_1596 = ~n_1594 & ~n_1595; assign n_1597 = x_61 & ~x_108; assign n_1598 = ~x_61 & x_108; assign n_1599 = ~n_1597 & ~n_1598; assign n_1600 = x_60 & ~x_104; assign n_1601 = ~x_60 & x_104; assign n_1602 = ~n_1600 & ~n_1601; assign n_1603 = x_59 & ~x_107; assign n_1604 = ~x_59 & x_107; assign n_1605 = ~n_1603 & ~n_1604; assign n_1606 = x_58 & ~x_105; assign n_1607 = ~x_58 & x_105; assign n_1608 = ~n_1606 & ~n_1607; assign n_1609 = x_57 & ~x_103; assign n_1610 = ~x_57 & x_103; assign n_1611 = ~n_1609 & ~n_1610; assign n_1612 = x_56 & ~x_102; assign n_1613 = ~x_56 & x_102; assign n_1614 = ~n_1612 & ~n_1613; assign n_1615 = x_55 & ~x_100; assign n_1616 = ~x_55 & x_100; assign n_1617 = ~n_1615 & ~n_1616; assign n_1618 = x_54 & ~x_99; assign n_1619 = ~x_54 & x_99; assign n_1620 = ~n_1618 & ~n_1619; assign n_1621 = x_53 & ~x_98; assign n_1622 = ~x_53 & x_98; assign n_1623 = ~n_1621 & ~n_1622; assign n_1624 = x_52 & ~x_94; assign n_1625 = ~x_52 & x_94; assign n_1626 = ~n_1624 & ~n_1625; assign n_1627 = x_51 & ~x_93; assign n_1628 = ~x_51 & x_93; assign n_1629 = ~n_1627 & ~n_1628; assign n_1630 = x_50 & ~x_92; assign n_1631 = ~x_50 & x_92; assign n_1632 = ~n_1630 & ~n_1631; assign n_1633 = x_49 & ~x_91; assign n_1634 = ~x_49 & x_91; assign n_1635 = ~n_1633 & ~n_1634; assign n_1636 = x_48 & ~x_90; assign n_1637 = ~x_48 & x_90; assign n_1638 = ~n_1636 & ~n_1637; assign n_1639 = ~x_46 & x_47; assign n_1640 = x_46 & ~x_47; assign n_1641 = ~n_1639 & ~n_1640; assign n_1642 = x_46 & ~x_81; assign n_1643 = ~x_46 & x_81; assign n_1644 = ~n_1642 & ~n_1643; assign n_1645 = x_45 & ~x_80; assign n_1646 = ~x_45 & x_80; assign n_1647 = ~n_1645 & ~n_1646; assign n_1648 = ~i_9 & x_44; assign n_1649 = i_9 & ~x_44; assign n_1650 = ~n_1648 & ~n_1649; assign n_1651 = ~i_7 & x_42; assign n_1652 = i_7 & ~x_42; assign n_1653 = ~n_1651 & ~n_1652; assign n_1654 = ~i_8 & x_43; assign n_1655 = i_8 & ~x_43; assign n_1656 = ~n_1654 & ~n_1655; assign n_1657 = ~n_1653 & ~n_1656; assign n_1658 = ~n_1650 & n_1657; assign n_1659 = ~n_1647 & n_1658; assign n_1660 = ~n_1644 & n_1659; assign n_1661 = ~n_1641 & n_1660; assign n_1662 = ~n_1638 & n_1661; assign n_1663 = ~n_1635 & n_1662; assign n_1664 = ~n_1632 & n_1663; assign n_1665 = ~n_1629 & n_1664; assign n_1666 = ~n_1626 & n_1665; assign n_1667 = ~n_1623 & n_1666; assign n_1668 = ~n_1620 & n_1667; assign n_1669 = ~n_1617 & n_1668; assign n_1670 = ~n_1614 & n_1669; assign n_1671 = ~n_1611 & n_1670; assign n_1672 = ~n_1608 & n_1671; assign n_1673 = ~n_1605 & n_1672; assign n_1674 = ~n_1602 & n_1673; assign n_1675 = ~n_1599 & n_1674; assign n_1676 = ~n_1596 & n_1675; assign n_1677 = ~n_1593 & n_1676; assign n_1678 = ~n_1590 & n_1677; assign n_1679 = ~n_1587 & n_1678; assign n_1680 = ~n_1584 & n_1679; assign n_1681 = ~n_1581 & n_1680; assign n_1682 = ~n_1578 & n_1681; assign n_1683 = ~n_1575 & n_1682; assign n_1684 = ~n_1572 & n_1683; assign n_1685 = ~n_1569 & n_1684; assign n_1686 = ~n_1566 & n_1685; assign n_1687 = ~n_1563 & n_1686; assign n_1688 = ~n_1560 & n_1687; assign n_1689 = ~n_1557 & n_1688; assign n_1690 = ~n_1554 & n_1689; assign n_1691 = ~n_1551 & n_1690; assign n_1692 = ~n_1548 & n_1691; assign n_1693 = ~n_1545 & n_1692; assign n_1694 = ~n_1542 & n_1693; assign n_1695 = ~n_1538 & n_1694; assign n_1696 = ~n_1535 & n_1695; assign n_1697 = ~n_1532 & n_1696; assign n_1698 = ~n_1529 & n_1697; assign n_1699 = ~n_1526 & n_1698; assign n_1700 = ~n_1523 & n_1699; assign n_1701 = ~n_1520 & n_1700; assign n_1702 = ~n_1517 & n_1701; assign n_1703 = ~n_1514 & n_1702; assign n_1704 = ~n_1505 & n_1703; assign n_1705 = ~n_1497 & n_1704; assign n_1706 = ~n_1487 & n_1705; assign n_1707 = ~n_1475 & n_1706; assign n_1708 = ~n_1463 & n_1707; assign n_1709 = ~n_1457 & n_1708; assign n_1710 = ~n_1451 & n_1709; assign n_1711 = ~n_1445 & n_1710; assign n_1712 = ~n_1435 & n_1711; assign n_1713 = ~n_1421 & n_1712; assign n_1714 = ~n_1411 & n_1713; assign n_1715 = ~n_1405 & n_1714; assign n_1716 = ~n_1395 & n_1715; assign n_1717 = ~n_1375 & n_1716; assign n_1718 = ~n_1372 & n_1717; assign n_1719 = ~n_1368 & n_1718; assign n_1720 = ~n_1364 & n_1719; assign n_1721 = ~n_1358 & n_1720; assign n_1722 = ~n_1350 & n_1721; assign n_1723 = ~n_1347 & n_1722; assign n_1724 = ~n_1343 & n_1723; assign n_1725 = ~n_1338 & n_1724; assign n_1726 = ~n_1330 & n_1725; assign n_1727 = ~n_1324 & n_1726; assign n_1728 = ~n_1313 & n_1727; assign n_1729 = ~n_1309 & n_1728; assign n_1730 = ~n_1293 & n_1729; assign n_1731 = ~n_1287 & n_1730; assign n_1732 = ~n_1280 & n_1731; assign n_1733 = ~n_1265 & n_1732; assign n_1734 = ~n_1259 & n_1733; assign n_1735 = ~n_1243 & n_1734; assign n_1736 = ~n_1240 & n_1735; assign n_1737 = ~n_1213 & n_1736; assign n_1738 = ~n_1204 & n_1737; assign n_1739 = ~n_1196 & n_1738; assign n_1740 = ~n_1186 & n_1739; assign n_1741 = ~n_1174 & n_1740; assign n_1742 = ~n_1160 & n_1741; assign n_1743 = ~n_1139 & n_1742; assign n_1744 = ~n_1133 & n_1743; assign n_1745 = ~n_1127 & n_1744; assign n_1746 = ~n_1121 & n_1745; assign n_1747 = ~n_1111 & n_1746; assign n_1748 = ~n_1097 & n_1747; assign n_1749 = ~n_1087 & n_1748; assign n_1750 = ~n_1081 & n_1749; assign n_1751 = ~n_1071 & n_1750; assign n_1752 = ~n_1052 & n_1751; assign n_1753 = ~n_1025 & n_1752; assign n_1754 = ~n_1019 & n_1753; assign n_1755 = ~n_1015 & n_1754; assign n_1756 = ~n_1006 & n_1755; assign n_1757 = ~n_1003 & n_1756; assign n_1758 = ~n_995 & n_1757; assign n_1759 = ~n_992 & n_1758; assign n_1760 = ~n_988 & n_1759; assign n_1761 = ~n_982 & n_1760; assign n_1762 = ~n_976 & n_1761; assign n_1763 = ~n_969 & n_1762; assign n_1764 = ~n_966 & n_1763; assign n_1765 = ~n_961 & n_1764; assign n_1766 = ~n_956 & n_1765; assign n_1767 = ~n_953 & n_1766; assign n_1768 = ~n_948 & n_1767; assign n_1769 = ~n_943 & n_1768; assign n_1770 = ~n_938 & n_1769; assign n_1771 = ~n_933 & n_1770; assign n_1772 = ~n_928 & n_1771; assign n_1773 = ~n_923 & n_1772; assign n_1774 = ~n_918 & n_1773; assign n_1775 = ~n_913 & n_1774; assign n_1776 = ~n_903 & n_1775; assign n_1777 = ~n_876 & n_1776; assign n_1778 = ~n_872 & n_1777; assign n_1779 = ~n_868 & n_1778; assign n_1780 = ~n_864 & n_1779; assign n_1781 = ~n_860 & n_1780; assign n_1782 = ~n_856 & n_1781; assign n_1783 = ~n_852 & n_1782; assign n_1784 = ~n_848 & n_1783; assign n_1785 = ~n_844 & n_1784; assign n_1786 = ~n_825 & n_1785; assign n_1787 = ~n_798 & n_1786; assign n_1788 = ~n_788 & n_1787; assign n_1789 = ~n_778 & n_1788; assign n_1790 = ~n_760 & n_1789; assign n_1791 = ~n_752 & n_1790; assign n_1792 = ~n_749 & n_1791; assign n_1793 = ~n_744 & n_1792; assign n_1794 = ~n_738 & n_1793; assign n_1795 = ~n_726 & n_1794; assign n_1796 = ~n_712 & n_1795; assign n_1797 = ~n_696 & n_1796; assign n_1798 = ~n_693 & n_1797; assign n_1799 = ~n_690 & n_1798; assign n_1800 = ~n_687 & n_1799; assign n_1801 = ~n_684 & n_1800; assign n_1802 = ~n_681 & n_1801; assign n_1803 = ~n_678 & n_1802; assign n_1804 = ~n_675 & n_1803; assign n_1805 = ~n_672 & n_1804; assign n_1806 = ~n_669 & n_1805; assign n_1807 = ~n_666 & n_1806; assign n_1808 = ~n_663 & n_1807; assign n_1809 = ~n_660 & n_1808; assign n_1810 = ~n_657 & n_1809; assign n_1811 = ~n_653 & n_1810; assign n_1812 = ~n_649 & n_1811; assign n_1813 = ~n_644 & n_1812; assign n_1814 = ~n_641 & n_1813; assign n_1815 = ~n_638 & n_1814; assign n_1816 = ~n_633 & n_1815; assign n_1817 = ~n_630 & n_1816; assign n_1818 = ~n_627 & n_1817; assign n_1819 = ~n_624 & n_1818; assign n_1820 = ~n_621 & n_1819; assign n_1821 = ~n_618 & n_1820; assign n_1822 = ~n_613 & n_1821; assign n_1823 = ~n_590 & n_1822; assign n_1824 = ~n_587 & n_1823; assign n_1825 = ~n_584 & n_1824; assign n_1826 = ~n_581 & n_1825; assign n_1827 = ~n_576 & n_1826; assign n_1828 = ~n_570 & n_1827; assign n_1829 = ~n_567 & n_1828; assign n_1830 = ~n_560 & n_1829; assign n_1831 = ~n_557 & n_1830; assign n_1832 = ~n_554 & n_1831; assign n_1833 = ~n_551 & n_1832; assign n_1834 = ~n_532 & n_1833; assign n_1835 = ~n_529 & n_1834; assign n_1836 = ~n_526 & n_1835; assign n_1837 = ~n_514 & n_1836; assign n_1838 = ~n_500 & n_1837; assign n_1839 = ~n_495 & n_1838; assign n_1840 = ~n_492 & n_1839; assign n_1841 = ~n_487 & n_1840; assign n_1842 = ~n_484 & n_1841; assign n_1843 = ~n_481 & n_1842; assign n_1844 = ~n_478 & n_1843; assign n_1845 = ~n_475 & n_1844; assign n_1846 = ~n_472 & n_1845; assign n_1847 = ~n_469 & n_1846; assign n_1848 = ~n_466 & n_1847; assign n_1849 = ~n_463 & n_1848; assign n_1850 = ~n_460 & n_1849; assign n_1851 = ~n_457 & n_1850; assign n_1852 = ~n_454 & n_1851; assign n_1853 = ~n_451 & n_1852; assign n_1854 = ~n_448 & n_1853; assign n_1855 = ~n_445 & n_1854; assign n_1856 = ~n_442 & n_1855; assign n_1857 = ~n_439 & n_1856; assign n_1858 = ~n_436 & n_1857; assign n_1859 = ~n_433 & n_1858; assign n_1860 = ~n_430 & n_1859; assign n_1861 = ~n_427 & n_1860; assign n_1862 = ~n_424 & n_1861; assign n_1863 = ~n_413 & n_1862; assign n_1864 = ~n_401 & n_1863; assign n_1865 = ~n_397 & n_1864; assign n_1866 = ~n_393 & n_1865; assign n_1867 = ~n_390 & n_1866; assign n_1868 = ~n_382 & n_1867; assign n_1869 = ~n_342 & n_1868; assign n_1870 = ~n_337 & n_1869; assign n_1871 = ~n_330 & n_1870; assign n_1872 = ~n_318 & n_1871; assign n_1873 = ~n_310 & n_1872; assign n_1874 = ~n_307 & n_1873; assign n_1875 = ~n_304 & n_1874; assign n_1876 = ~n_301 & n_1875; assign n_1877 = ~n_298 & n_1876; assign n_1878 = ~n_295 & n_1877; assign n_1879 = x_71 & n_1878; assign n_1880 = ~n_292 & n_1879; assign n_1881 = ~n_283 & n_1880; assign n_1882 = ~n_271 & n_1881; assign n_1883 = ~n_252 & n_1882; assign n_1884 = ~n_245 & n_1883; assign n_1885 = ~n_151 & n_1884; assign n_1886 = ~n_145 & n_1885; assign n_1887 = ~n_142 & n_1886; assign n_1888 = ~n_139 & n_1887; assign n_1889 = ~n_136 & n_1888; assign n_1890 = ~n_133 & n_1889; assign n_1891 = ~n_112 & n_1890; assign n_1892 = ~n_109 & n_1891; assign n_1893 = ~n_106 & n_1892; assign n_1894 = ~n_103 & n_1893; assign n_1895 = ~n_100 & n_1894; assign n_1896 = ~n_97 & n_1895; assign n_1897 = ~n_94 & n_1896; assign n_1898 = ~n_88 & n_1897; assign n_1899 = ~n_85 & n_1898; assign n_1900 = ~n_81 & n_1899; assign n_1901 = ~n_78 & n_1900; assign n_1902 = ~n_75 & n_1901; assign n_1903 = ~n_48 & n_1902; assign n_1904 = ~n_42 & n_1903; assign n_1905 = ~n_36 & n_1904; assign n_1906 = ~n_30 & n_1905; assign n_1907 = ~n_24 & n_1906; assign n_1908 = ~n_18 & n_1907; assign n_1909 = ~n_12 & n_1908; assign n_1910 = ~n_6 & n_1909; assign n_1911 = ~x_249 & n_1910; assign o_1 = ~n_1911; endmodule
2
2,499
data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/02_fsm1s.v
201,488,448
02_fsm1s.v
v
28
74
[]
[]
[]
[(2, 27)]
null
data/verilator_xmls/67f81053-7a98-4389-a020-915686778602.xml
null
61,522
module
module top_module(clk, reset, in, out); input clk; input reset; input in; output out; reg out; parameter A=0, B=1; reg state; reg next; always@(*) begin case (state) A: next = in ? A : B; B: next = in ? B : A; endcase end always @(posedge clk) begin if (reset) state <= B; else state <= next; end assign out = (state==B); endmodule
module top_module(clk, reset, in, out);
input clk; input reset; input in; output out; reg out; parameter A=0, B=1; reg state; reg next; always@(*) begin case (state) A: next = in ? A : B; B: next = in ? B : A; endcase end always @(posedge clk) begin if (reset) state <= B; else state <= next; end assign out = (state==B); endmodule
0
2,502
data/full_repos/permissive/98490156/complishment_coordi/check/Summarize16.v
98,490,156
Summarize16.v
v
28
141
[]
[]
[]
[(5, 27)]
null
data/verilator_xmls/92054b43-06d2-479b-8aef-0acca4726d41.xml
null
313,453
module
module Summarize16(check_ans, out); input [31:0] check_ans; output reg [1:0] out; always@(*) begin if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00) && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00) && (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00) && (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00) && (check_ans[25:24] == 2'b00) && (check_ans[27:26] == 2'b00) && (check_ans[29:28] == 2'b00) && (check_ans[31:30] == 2'b00)) out = 2'b00; else if((check_ans[1:0] == 2'b10) || (check_ans[3:2] == 2'b10) || (check_ans[5:4] == 2'b10) || (check_ans[7:6] == 2'b10) || (check_ans[9:8] == 2'b10) || (check_ans[11:10] == 2'b10) || (check_ans[13:12] == 2'b10) || (check_ans[15:14] == 2'b10) || (check_ans[17:16] == 2'b10) || (check_ans[19:18] == 2'b10) || (check_ans[21:20] == 2'b10) || (check_ans[23:22] == 2'b10) || (check_ans[25:24] == 2'b10) || (check_ans[27:26] == 2'b10) || (check_ans[29:28] == 2'b10) || (check_ans[31:30] == 2'b10)) out = 2'b10; else out = 2'b01; end endmodule
module Summarize16(check_ans, out);
input [31:0] check_ans; output reg [1:0] out; always@(*) begin if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00) && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00) && (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00) && (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00) && (check_ans[25:24] == 2'b00) && (check_ans[27:26] == 2'b00) && (check_ans[29:28] == 2'b00) && (check_ans[31:30] == 2'b00)) out = 2'b00; else if((check_ans[1:0] == 2'b10) || (check_ans[3:2] == 2'b10) || (check_ans[5:4] == 2'b10) || (check_ans[7:6] == 2'b10) || (check_ans[9:8] == 2'b10) || (check_ans[11:10] == 2'b10) || (check_ans[13:12] == 2'b10) || (check_ans[15:14] == 2'b10) || (check_ans[17:16] == 2'b10) || (check_ans[19:18] == 2'b10) || (check_ans[21:20] == 2'b10) || (check_ans[23:22] == 2'b10) || (check_ans[25:24] == 2'b10) || (check_ans[27:26] == 2'b10) || (check_ans[29:28] == 2'b10) || (check_ans[31:30] == 2'b10)) out = 2'b10; else out = 2'b01; end endmodule
0
2,503
data/full_repos/permissive/305996059/系统硬件综合设计/CPU_WH/RegW.v
305,996,059
RegW.v
v
70
66
[]
[]
[]
[(1, 70)]
null
data/verilator_xmls/03eb6f76-40ef-47de-9825-9b64ef3b1a4b.xml
null
121,161
module
module RegW( input clk, rst, input [31:0] PCPlus8M, input [31:0] ALUOutM, input [31:0] ReadDataM, input [4:0] WriteRegM, input RegWriteM, input MemToRegM, input IsJJalM, input IsJrJalrM, input IsUnsignedM, input [3:0] BEOutM, output reg [31:0] PCPlus8W, output reg [31:0] ALUOutW, output reg [31:0] ReadDataW, output reg [4:0] WriteRegW, output reg RegWriteW, output reg MemToRegW, output reg IsJJalW, output reg IsJrJalrW, output reg IsUnsignedW, output reg [3:0] BEOutW ); initial begin PCPlus8W <= 0; ALUOutW <= 0; ReadDataW <= 0; WriteRegW <= 0; RegWriteW <= 0; MemToRegW <= 0; IsJJalW <= 0; IsJrJalrW <= 0; IsUnsignedW <= 0; BEOutW <= 0; end always @(posedge clk) begin if (rst) begin PCPlus8W <= 0; ALUOutW <= 0; ReadDataW <= 0; WriteRegW <= 0; RegWriteW <= 0; MemToRegW <= 0; IsJJalW <= 0; IsJrJalrW <= 0; IsUnsignedW <= 0; BEOutW <= 0; end else begin PCPlus8W <= PCPlus8M; ALUOutW <= ALUOutM; ReadDataW <= ReadDataM; WriteRegW <= WriteRegM; RegWriteW <= RegWriteM; MemToRegW <= MemToRegM; IsJJalW <= IsJJalM; IsJrJalrW <= IsJrJalrM; IsUnsignedW <= IsUnsignedM; BEOutW <= BEOutM; end end endmodule
module RegW( input clk, rst, input [31:0] PCPlus8M, input [31:0] ALUOutM, input [31:0] ReadDataM, input [4:0] WriteRegM, input RegWriteM, input MemToRegM, input IsJJalM, input IsJrJalrM, input IsUnsignedM, input [3:0] BEOutM, output reg [31:0] PCPlus8W, output reg [31:0] ALUOutW, output reg [31:0] ReadDataW, output reg [4:0] WriteRegW, output reg RegWriteW, output reg MemToRegW, output reg IsJJalW, output reg IsJrJalrW, output reg IsUnsignedW, output reg [3:0] BEOutW );
initial begin PCPlus8W <= 0; ALUOutW <= 0; ReadDataW <= 0; WriteRegW <= 0; RegWriteW <= 0; MemToRegW <= 0; IsJJalW <= 0; IsJrJalrW <= 0; IsUnsignedW <= 0; BEOutW <= 0; end always @(posedge clk) begin if (rst) begin PCPlus8W <= 0; ALUOutW <= 0; ReadDataW <= 0; WriteRegW <= 0; RegWriteW <= 0; MemToRegW <= 0; IsJJalW <= 0; IsJrJalrW <= 0; IsUnsignedW <= 0; BEOutW <= 0; end else begin PCPlus8W <= PCPlus8M; ALUOutW <= ALUOutM; ReadDataW <= ReadDataM; WriteRegW <= WriteRegM; RegWriteW <= RegWriteM; MemToRegW <= MemToRegM; IsJJalW <= IsJJalM; IsJrJalrW <= IsJrJalrM; IsUnsignedW <= IsUnsignedM; BEOutW <= BEOutM; end end endmodule
1
2,549
data/full_repos/permissive/260351496/src/clk_prescaler.v
260,351,496
clk_prescaler.v
v
61
140
[]
[]
[]
null
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/899282cd-ab35-4f6a-ba44-89325acc6af0.xml
null
99,030
module
module clk_prescaler(i_clk, i_arst, i_on, i_divide_by, o_clk_enable); input i_clk; input i_arst; input i_on; input [6:0] i_divide_by; output o_clk_enable; reg [6:0] counter; reg [6:0] buffer; assign o_clk_enable = (i_on & (counter == buffer)); always @(posedge i_clk, posedge i_arst, negedge i_on) begin if(i_arst) begin buffer <= {7{1'b0}}; end else if(~i_on) begin buffer <= {7{1'b0}}; end else begin buffer <= i_divide_by; end end wire is_not_changed; assign is_not_changed = (buffer == i_divide_by); reg is_not_changed_state; always @(negedge is_not_changed) begin is_not_changed_state <= 1'b1; counter <= {7{1'b0}}; end always @(posedge i_clk, posedge i_arst, negedge i_on) begin if(i_arst) begin counter <= {7{1'b0}}; end else if(~i_on) begin counter <= {7{1'b0}}; end else if(is_not_changed_state) begin counter <= {7{1'b0}}; is_not_changed_state <= 1'b0; end else begin if(o_clk_enable) begin counter <= {7{1'b0}}; end else begin if(i_on) begin counter <= counter + 1'b1; end else begin counter <= {7{1'b0}}; end end end end endmodule
module clk_prescaler(i_clk, i_arst, i_on, i_divide_by, o_clk_enable);
input i_clk; input i_arst; input i_on; input [6:0] i_divide_by; output o_clk_enable; reg [6:0] counter; reg [6:0] buffer; assign o_clk_enable = (i_on & (counter == buffer)); always @(posedge i_clk, posedge i_arst, negedge i_on) begin if(i_arst) begin buffer <= {7{1'b0}}; end else if(~i_on) begin buffer <= {7{1'b0}}; end else begin buffer <= i_divide_by; end end wire is_not_changed; assign is_not_changed = (buffer == i_divide_by); reg is_not_changed_state; always @(negedge is_not_changed) begin is_not_changed_state <= 1'b1; counter <= {7{1'b0}}; end always @(posedge i_clk, posedge i_arst, negedge i_on) begin if(i_arst) begin counter <= {7{1'b0}}; end else if(~i_on) begin counter <= {7{1'b0}}; end else if(is_not_changed_state) begin counter <= {7{1'b0}}; is_not_changed_state <= 1'b0; end else begin if(o_clk_enable) begin counter <= {7{1'b0}}; end else begin if(i_on) begin counter <= counter + 1'b1; end else begin counter <= {7{1'b0}}; end end end end endmodule
2
2,550
data/full_repos/permissive/203526788/iVerilog/Template/top.v
203,526,788
top.v
v
33
83
[]
[]
[]
[(23, 32)]
null
data/verilator_xmls/651345ed-d6ab-4609-89ee-8389f01b24c8.xml
null
62,469
module
module top (input wire a, input wire clk, output reg b); always @(posedge clk) begin b <= a; end endmodule
module top (input wire a, input wire clk, output reg b);
always @(posedge clk) begin b <= a; end endmodule
0
2,563
data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v
354,584,424
ROM_ASIC.v
v
1,198
180
[]
[]
[]
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:41: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d0: rdata = 56\'b00000000000000000000000000000000000000000000000000000001;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:44: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d1: rdata = 56\'b00000000000000000000000000000000000100100100100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:50: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d2: rdata = 56\'b00000000000000000000000000000000000000000000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:53: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d3: rdata = 56\'b00000000000000000000100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:56: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d4: rdata = 56\'b00000000000000000000000000100100100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:62: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h3\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d5: rdata = 56\'b00000000000000000000000000000000000000000000000000000011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d6: rdata = 56\'b00000000100100100100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:68: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d7: rdata = 56\'b00000000100100100100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:74: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h3\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d8: rdata = 56\'b00000000000000000000000000000000000000000000000000000011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:77: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d9: rdata = 56\'b00000000000000000000000000000000000000001101100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:80: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d10: rdata = 56\'b00100100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:83: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d11: rdata = 56\'b00000000000000000000000000000000000000001101100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:86: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d12: rdata = 56\'b00100100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:92: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h7\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d13: rdata = 56\'b00000000000000000000000000000000000000000000000000000111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:95: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb6005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d14: rdata = 56\'b00000000000000000000000000001101101101100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:98: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d15: rdata = 56\'b00000000000000000000000000001101101101100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:101: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d16: rdata = 56\'b00000000000000000000000000001101101101100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:107: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h7\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d17: rdata = 56\'b00000000000000000000000000000000000000000000000000000111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:110: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d18: rdata = 56\'b00000000000001101101100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:113: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d19: rdata = 56\'b00000000000000000000000001100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:116: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d20: rdata = 56\'b00000000000001101101100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:119: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d21: rdata = 56\'b00000000000001101101100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:122: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d22: rdata = 56\'b00000000000000000000000001100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:125: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d23: rdata = 56\'b00000000000000000000000001100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:131: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d24: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:134: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d25: rdata = 56\'b01101101101100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:137: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d26: rdata = 56\'b01101101101100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:140: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d27: rdata = 56\'b01101101101100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d28: rdata = 56\'b01101101101100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:149: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d29: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:152: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d30: rdata = 56\'b00000000000000000000000000000000010110110110100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:155: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d31: rdata = 56\'b00000000000000000000000000000000010110110110100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:158: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d32: rdata = 56\'b00000000000000000000000000000000010110110110100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:161: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d33: rdata = 56\'b00000000000000000000000000000000010110110110100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:167: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d34: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:170: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d35: rdata = 56\'b00000000000000000010100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:173: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d36: rdata = 56\'b00000000000000000000000010110110100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:176: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d37: rdata = 56\'b00000000000000000010100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:179: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d38: rdata = 56\'b00000000000000000010100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:182: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d39: rdata = 56\'b00000000000000000010100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:185: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d40: rdata = 56\'b00000000000000000000000010110110100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:188: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d41: rdata = 56\'b00000000000000000000000010110110100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:191: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d42: rdata = 56\'b00000000000000000000000010110110100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:197: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d43: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:200: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d44: rdata = 56\'b00000010110110110100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:203: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d45: rdata = 56\'b00000010110110110100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:206: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d46: rdata = 56\'b00000010110110110100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:209: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d47: rdata = 56\'b00000010110110110100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:215: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d48: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:218: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d49: rdata = 56\'b00000000000000000000000000000000000000011111100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:221: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d50: rdata = 56\'b10110100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:224: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d51: rdata = 56\'b00000000000000000000000000000000000000011111100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:227: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d52: rdata = 56\'b10110100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:230: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d53: rdata = 56\'b00000000000000000000000000000000000000011111100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:233: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d54: rdata = 56\'b10110100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:236: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d55: rdata = 56\'b00000000000000000000000000000000000000011111100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:239: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d56: rdata = 56\'b10110100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:245: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d57: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:248: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d58: rdata = 56\'b00000000000000000000000000011111111111100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d59: rdata = 56\'b00000000000000000000000000011111111111100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:254: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d60: rdata = 56\'b00000000000000000000000000011111111111100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:257: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d61: rdata = 56\'b00000000000000000000000000011111111111100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:263: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d62: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:266: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d63: rdata = 56\'b00000000000011111111100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:269: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d64: rdata = 56\'b00000000000000000000000011100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:272: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d65: rdata = 56\'b00000000000011111111100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:275: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d66: rdata = 56\'b00000000000011111111100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:278: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d67: rdata = 56\'b00000000000011111111100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:281: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d68: rdata = 56\'b00000000000000000000000011100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:284: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d69: rdata = 56\'b00000000000000000000000011100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:287: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d70: rdata = 56\'b00000000000000000000000011100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:293: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d71: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:296: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d72: rdata = 56\'b11111111111100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:299: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d73: rdata = 56\'b11111111111100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:302: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d74: rdata = 56\'b11111111111100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:305: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d75: rdata = 56\'b11111111111100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:311: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d76: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:314: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d77: rdata = 56\'b00000000000000000000000000000000000100100100100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:317: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d78: rdata = 56\'b00000000000000000000000000000000000100100100100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:320: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d79: rdata = 56\'b00000000000000000000000000000000000100100100100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:323: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d80: rdata = 56\'b00000000000000000000000000000000000100100100100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:329: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d81: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:332: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d82: rdata = 56\'b00000000000000000000100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:335: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d83: rdata = 56\'b00000000000000000000000000100100100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:338: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d84: rdata = 56\'b00000000000000000000100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:341: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d85: rdata = 56\'b00000000000000000000100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:344: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d86: rdata = 56\'b00000000000000000000100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:347: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d87: rdata = 56\'b00000000000000000000000000100100100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:350: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d88: rdata = 56\'b00000000000000000000000000100100100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:353: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d89: rdata = 56\'b00000000000000000000000000100100100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:359: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d90: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:362: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92680000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d91: rdata = 56\'b00000000100100100110100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:365: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d92: rdata = 56\'b00000000000000000000000010110110100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:368: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d93: rdata = 56\'b00000000100100100100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:371: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d94: rdata = 56\'b00000000100100100100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:377: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d95: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:380: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d96: rdata = 56\'b00000000000000000000000000000000000000001101100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:383: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h26db4000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d97: rdata = 56\'b00100110110110110100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:386: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d98: rdata = 56\'b00000000000000000000000000000000000000001101100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:389: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d99: rdata = 56\'b00100100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:392: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d100: rdata = 56\'b00000000000000000000000000000000000000001101100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:395: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d101: rdata = 56\'b00100100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:401: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d102: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:404: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d103: rdata = 56\'b00000000000000000000000000000000000000011111100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:407: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d104: rdata = 56\'b10110100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:410: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb7f855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d105: rdata = 56\'b00000000000000000000000000001101101101111111100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:413: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d106: rdata = 56\'b10110100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:416: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d107: rdata = 56\'b00000000000000000000000000001101101101100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:422: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d108: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:425: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d109: rdata = 56\'b00000000000001101101100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:428: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d110: rdata = 56\'b00000000000001101101100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:431: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d111: rdata = 56\'b00000000000000000000000000011111111111100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:434: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h7ffe0051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d112: rdata = 56\'b00000000000000000000000001111111111111100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:437: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d113: rdata = 56\'b00000000000000000000000001100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:443: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d114: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:446: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d115: rdata = 56\'b00000000000011111111100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:449: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d116: rdata = 56\'b00000000000000000000000011100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:452: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d117: rdata = 56\'b00000000000011111111100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:455: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6dbff800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d118: rdata = 56\'b01101101101111111111100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:458: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d119: rdata = 56\'b00000000000000000000000011100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:461: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d120: rdata = 56\'b00000000000000000000000011100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:467: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d121: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:470: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d122: rdata = 56\'b00000000000000000000000000000000010110110110100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:473: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d123: rdata = 56\'b11111111111100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:476: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d124: rdata = 56\'b11111111111100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:479: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d125: rdata = 56\'b11111111111100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:485: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d126: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:488: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d127: rdata = 56\'b00000000000000000000000000000000000100100100100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:491: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d128: rdata = 56\'b00000000000000000000000000000000000100100100100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:494: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d129: rdata = 56\'b00000000000000000000000000000000000100100100100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:497: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d130: rdata = 56\'b00000000000000000000000000000000000100100100100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:503: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d131: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:506: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d132: rdata = 56\'b00000000000000000000100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:509: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d133: rdata = 56\'b00000000000000000000000000100100100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:512: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d134: rdata = 56\'b00000000000000000000100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:515: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d135: rdata = 56\'b00000000000000000000100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:518: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d136: rdata = 56\'b00000000000000000000100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:521: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d137: rdata = 56\'b00000000000000000000000000100100100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:524: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d138: rdata = 56\'b00000000000000000000000000100100100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:527: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d139: rdata = 56\'b00000000000000000000000000100100100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:533: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d140: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:536: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d141: rdata = 56\'b00000000100100100100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:539: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d142: rdata = 56\'b00000000100100100100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:542: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d143: rdata = 56\'b00000000100100100100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:545: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d144: rdata = 56\'b00000000100100100100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:551: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d145: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:554: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d146: rdata = 56\'b00000000000000000000000000000000000000001101100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:557: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d147: rdata = 56\'b00100100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:560: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d148: rdata = 56\'b00000000000000000000000000000000000000001101100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:563: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d149: rdata = 56\'b00100100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:566: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d150: rdata = 56\'b00000000000000000000000000000000000000001101100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:569: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d151: rdata = 56\'b00100100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:572: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d152: rdata = 56\'b00000000000000000000000000000000000000001101100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:575: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d153: rdata = 56\'b00100100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:581: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d154: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:584: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb6005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d155: rdata = 56\'b00000000000000000000000000001101101101100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:587: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d156: rdata = 56\'b00000000000000000000000000001101101101100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:590: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d157: rdata = 56\'b00000000000000000000000000001101101101100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:593: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d158: rdata = 56\'b00000000000000000000000000001101101101100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:599: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d159: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:602: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d160: rdata = 56\'b00000000000001101101100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:605: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d161: rdata = 56\'b00000000000000000000000001100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:608: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d162: rdata = 56\'b00000000000001101101100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:611: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d163: rdata = 56\'b00000000000001101101100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:614: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d164: rdata = 56\'b00000000000001101101100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:617: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d165: rdata = 56\'b00000000000000000000000001100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:620: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d166: rdata = 56\'b00000000000000000000000001100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:623: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d167: rdata = 56\'b00000000000000000000000001100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:629: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d168: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:632: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d169: rdata = 56\'b01101101101100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:635: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d170: rdata = 56\'b01101101101100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:638: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d171: rdata = 56\'b01101101101100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:641: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d172: rdata = 56\'b01101101101100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:647: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d173: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:650: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d174: rdata = 56\'b00000000000000000000000000000000010110110110100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:653: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d175: rdata = 56\'b00000000000000000000000000000000010110110110100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:656: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d176: rdata = 56\'b00000000000000000000000000000000010110110110100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:659: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d177: rdata = 56\'b00000000000000000000000000000000010110110110100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:665: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d178: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:668: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d179: rdata = 56\'b00000000000000000010100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:671: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d180: rdata = 56\'b00000000000000000000000010110110100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:674: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d181: rdata = 56\'b00000000000000000010100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:677: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d182: rdata = 56\'b00000000000000000010100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:680: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d183: rdata = 56\'b00000000000000000010100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:683: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d184: rdata = 56\'b00000000000000000000000010110110100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:686: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d185: rdata = 56\'b00000000000000000000000010110110100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:689: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d186: rdata = 56\'b00000000000000000000000010110110100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:695: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d187: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:698: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d188: rdata = 56\'b00000010110110110100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:701: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d189: rdata = 56\'b00000010110110110100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:704: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d190: rdata = 56\'b00000010110110110100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:707: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d191: rdata = 56\'b00000010110110110100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:713: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d192: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:716: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d193: rdata = 56\'b00000000000000000000000000000000000000011111100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:719: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4924000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d194: rdata = 56\'b10110100100100100100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:722: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d195: rdata = 56\'b00000000000000000000000000000000000000011111100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:725: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d196: rdata = 56\'b10110100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:728: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d197: rdata = 56\'b00000000000000000000000000000000000000011111100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:731: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d198: rdata = 56\'b10110100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:737: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d199: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:740: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffed851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d200: rdata = 56\'b00000000000000000000000000011111111111101101100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:743: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d201: rdata = 56\'b00100100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:746: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d202: rdata = 56\'b00000000000000000000000000011111111111100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:749: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d203: rdata = 56\'b00000000000000000000000000011111111111100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:755: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d204: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:758: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d205: rdata = 56\'b00000000000011111111100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:761: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d206: rdata = 56\'b00000000000011111111100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:764: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb6005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d207: rdata = 56\'b00000000000000000000000000001101101101100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:767: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hedb60051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d208: rdata = 56\'b00000000000000000000000011101101101101100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:770: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d209: rdata = 56\'b00000000000000000000000011100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:776: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d210: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:779: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d211: rdata = 56\'b00000000000001101101100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:782: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d212: rdata = 56\'b00000000000000000000000001100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:785: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff6d80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d213: rdata = 56\'b11111111111101101101100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:788: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d214: rdata = 56\'b11111111111100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:791: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d215: rdata = 56\'b00000000000000000000000001100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:797: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d216: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:800: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d217: rdata = 56\'b00000000000000000000000000000000000100100100100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:803: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d218: rdata = 56\'b01101101101100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:806: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d219: rdata = 56\'b01101101101100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:809: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d220: rdata = 56\'b01101101101100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:815: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d221: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:818: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d222: rdata = 56\'b00000000000000000000100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:821: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d223: rdata = 56\'b00000000000000000000000000000000010110110110100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:824: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d224: rdata = 56\'b00000000000000000000000000000000010110110110100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:827: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24db6857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d225: rdata = 56\'b00000000000000000000000000100100110110110110100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:833: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d226: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:836: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d227: rdata = 56\'b00000000000000000010100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:839: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d228: rdata = 56\'b00000000000000000000000010110110100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:842: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h280000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d229: rdata = 56\'b00000000000000000010100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:845: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d230: rdata = 56\'b00000000000000000010100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:848: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d231: rdata = 56\'b00000000000000000010100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:851: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb680005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d232: rdata = 56\'b00000000000000000000000010110110100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:854: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d233: rdata = 56\'b00000000000000000000000010110110100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:857: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d234: rdata = 56\'b00000000000000000000000010110110100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:863: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d235: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:866: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d236: rdata = 56\'b00000010110110110100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:869: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d237: rdata = 56\'b00000010110110110100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:872: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d238: rdata = 56\'b00000010110110110100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:875: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d239: rdata = 56\'b00000010110110110100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:881: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d240: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:884: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d241: rdata = 56\'b00000000000000000000000000000000000000011111100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:887: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d242: rdata = 56\'b10110100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:890: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d243: rdata = 56\'b00000000000000000000000000000000000000011111100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:893: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d244: rdata = 56\'b10110100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:896: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d245: rdata = 56\'b00000000000000000000000000000000000000011111100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:899: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d246: rdata = 56\'b10110100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:902: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1f85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d247: rdata = 56\'b00000000000000000000000000000000000000011111100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:905: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d248: rdata = 56\'b10110100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:911: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d249: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:914: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d250: rdata = 56\'b00000000000000000000000000011111111111100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:917: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d251: rdata = 56\'b00000000000000000000000000011111111111100000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:920: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d252: rdata = 56\'b00000000000000000000000000011111111111100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:923: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h1ffe0059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d253: rdata = 56\'b00000000000000000000000000011111111111100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:929: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d254: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:932: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d255: rdata = 56\'b00000000000011111111100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:935: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d256: rdata = 56\'b00000000000000000000000011100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:938: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d257: rdata = 56\'b00000000000011111111100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:941: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d258: rdata = 56\'b00000000000011111111100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:944: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d259: rdata = 56\'b00000000000011111111100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:947: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he000005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d260: rdata = 56\'b00000000000000000000000011100000000000000000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:950: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d261: rdata = 56\'b00000000000000000000000011100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:953: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d262: rdata = 56\'b00000000000000000000000011100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:959: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d263: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:962: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d264: rdata = 56\'b11111111111100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:965: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d265: rdata = 56\'b11111111111100000000000000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:968: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d266: rdata = 56\'b11111111111100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:971: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d267: rdata = 56\'b11111111111100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:977: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d268: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:980: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d269: rdata = 56\'b00000000000000000000000000000000000100100100100001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:983: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124853\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d270: rdata = 56\'b00000000000000000000000000000000000100100100100001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:986: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h124857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d271: rdata = 56\'b00000000000000000000000000000000000100100100100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:989: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h12485b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d272: rdata = 56\'b00000000000000000000000000000000000100100100100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:995: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d273: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:998: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d274: rdata = 56\'b00000000000000000000100000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1001: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d275: rdata = 56\'b00000000000000000000000000100100100000000000000001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1004: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h80000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d276: rdata = 56\'b00000000000000000000100000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1007: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d277: rdata = 56\'b00000000000000000000100000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1010: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d278: rdata = 56\'b00000000000000000000100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1013: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2480005f\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d279: rdata = 56\'b00000000000000000000000000100100100000000000000001011111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1016: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800053\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d280: rdata = 56\'b00000000000000000000000000100100100000000000000001010011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1019: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d281: rdata = 56\'b00000000000000000000000000100100100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1025: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d282: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1028: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d283: rdata = 56\'b00000000100100100100000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1031: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d284: rdata = 56\'b00000000100100100100000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1034: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h92400000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d285: rdata = 56\'b00000000100100100100000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1037: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h924000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d286: rdata = 56\'b00000000100100100100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1043: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d287: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1046: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d288: rdata = 56\'b00000000000000000000000000000000000000001101100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1049: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d289: rdata = 56\'b00100100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1052: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd855\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d290: rdata = 56\'b00000000000000000000000000000000000000001101100001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1055: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h24000000000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d291: rdata = 56\'b00100100000000000000000000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1058: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd859\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d292: rdata = 56\'b00000000000000000000000000000000000000001101100001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1061: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005a\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d293: rdata = 56\'b00100100000000000000000000000000000000000000000001011010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1064: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd85d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d294: rdata = 56\'b00000000000000000000000000000000000000001101100001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1067: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2400000000005e\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d295: rdata = 56\'b00100100000000000000000000000000000000000000000001011110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1073: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d296: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1076: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb7f851\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d297: rdata = 56\'b00000000000000000000000000001101101101111111100001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1079: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb4000000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d298: rdata = 56\'b10110100000000000000000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1082: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d299: rdata = 56\'b00000000000000000000000000001101101101100000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1085: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hdb60059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d300: rdata = 56\'b00000000000000000000000000001101101101100000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1091: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hf\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d301: rdata = 56\'b00000000000000000000000000000000000000000000000000001111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1094: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d80000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d302: rdata = 56\'b00000000000001101101100000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1097: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d303: rdata = 56\'b00000000000001101101100000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1100: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6d800000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d304: rdata = 56\'b00000000000001101101100000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1103: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h7ffe005d\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d305: rdata = 56\'b00000000000000000000000001111111111111100000000001011101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1106: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000051\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d306: rdata = 56\'b00000000000000000000000001100000000000000000000001010001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1109: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60000055\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d307: rdata = 56\'b00000000000000000000000001100000000000000000000001010101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1115: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d308: rdata = 56\'b00000000000000000000000000000000000000000000000000001101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1118: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hff800000058\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d309: rdata = 56\'b00000000000011111111100000000000000000000000000001011000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1121: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'he0000059\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d310: rdata = 56\'b00000000000000000000000011100000000000000000000001011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1124: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db0000000005c\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d311: rdata = 56\'b01101101101100000000000000000000000000000000000001011100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1127: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6db00000000050\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d312: rdata = 56\'b01101101101100000000000000000000000000000000000001010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1133: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hd\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d313: rdata = 56\'b00000000000000000000000000000000000000000000000000001101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1136: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hfff00000000054\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d314: rdata = 56\'b11111111111100000000000000000000000000000000000001010100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1139: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b6857\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d315: rdata = 56\'b00000000000000000000000000000000010110110110100001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1142: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h5b685b\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d316: rdata = 56\'b00000000000000000000000000000000010110110110100001011011;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1148: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h9\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d317: rdata = 56\'b00000000000000000000000000000000000000000000000000001001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1151: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h6800000056\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d318: rdata = 56\'b00000000000000000110100000000000000000000000000001010110;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1154: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'hb6800057\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d319: rdata = 56\'b00000000000000000000000010110110100000000000000001010111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1160: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h8\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d320: rdata = 56\'b00000000000000000000000000000000000000000000000000001000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1163: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h2db4000000052\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d321: rdata = 56\'b00000010110110110100000000000000000000000000000001010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1166: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h60\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d322: rdata = 56\'b00000000000000000000000000000000000000000000000001100000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1169: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h70\' generates 56 bits.\n : ... In instance ROM_ASIC\n9\'d323: rdata = 56\'b00000000000000000000000000000000000000000000000001110000; \n ^\n%Warning-WIDTH: data/full_repos/permissive/354584424/tabla/hardware/fpga/config/linear_784/ROM_ASIC.v:1170: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'56\'h70\' generates 56 bits.\n : ... In instance ROM_ASIC\ndefault: rdata = 56\'b00000000000000000000000000000000000000000000000001110000;\n ^\n%Error: Exiting due to 325 warning(s)\n'
166,483
module
module ROM_ASIC #( parameter DATA_WIDTH = 16, parameter ADDR_WIDTH = 9, parameter INIT = "weight.txt", parameter TYPE = "block", parameter ROM_DEPTH = 1<<ADDR_WIDTH ) ( input wire CLK, input wire RESET, input wire [ADDR_WIDTH-1:0] ADDRESS, input wire ENABLE, output reg [DATA_WIDTH-1:0] DATA_OUT, output reg DATA_OUT_VALID ); localparam DEPTH = ROM_DEPTH; reg [DATA_WIDTH-1:0] rdata; wire [ADDR_WIDTH-1:0] address; assign address = ADDRESS; always @(*) begin case(address) 9'd0: rdata = 56'b00000000000000000000000000000000000000000000000000000001; 9'd1: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd2: rdata = 56'b00000000000000000000000000000000000000000000000000000001; 9'd3: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd4: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd5: rdata = 56'b00000000000000000000000000000000000000000000000000000011; 9'd6: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd7: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd8: rdata = 56'b00000000000000000000000000000000000000000000000000000011; 9'd9: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd10: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd11: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd12: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd13: rdata = 56'b00000000000000000000000000000000000000000000000000000111; 9'd14: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd15: rdata = 56'b00000000000000000000000000001101101101100000000001010001; 9'd16: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd17: rdata = 56'b00000000000000000000000000000000000000000000000000000111; 9'd18: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd19: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd20: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd21: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd22: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd23: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd24: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd25: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd26: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd27: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd28: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd29: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd30: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd31: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd32: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd33: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd34: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd35: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd36: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd37: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd38: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd39: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd40: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd41: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd42: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd43: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd44: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd45: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd46: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd47: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd48: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd49: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd50: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd51: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd52: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd53: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd54: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd55: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd56: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd57: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd58: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd59: rdata = 56'b00000000000000000000000000011111111111100000000001010001; 9'd60: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd61: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd62: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd63: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd64: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd65: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd66: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd67: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd68: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd69: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd70: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd71: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd72: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd73: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd74: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd75: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd76: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd77: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd78: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd79: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd80: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd81: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd82: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd83: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd84: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd85: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd86: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd87: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd88: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd89: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd90: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd91: rdata = 56'b00000000100100100110100000000000000000000000000001011010; 9'd92: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd93: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd94: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd95: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd96: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd97: rdata = 56'b00100110110110110100000000000000000000000000000001010110; 9'd98: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd99: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd100: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd101: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd102: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd103: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd104: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd105: rdata = 56'b00000000000000000000000000001101101101111111100001010101; 9'd106: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd107: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd108: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd109: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd110: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd111: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd112: rdata = 56'b00000000000000000000000001111111111111100000000001010001; 9'd113: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd114: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd115: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd116: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd117: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd118: rdata = 56'b01101101101111111111100000000000000000000000000001010000; 9'd119: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd120: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd121: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd122: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd123: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd124: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd125: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd126: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd127: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd128: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd129: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd130: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd131: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd132: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd133: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd134: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd135: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd136: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd137: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd138: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd139: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd140: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd141: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd142: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd143: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd144: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd145: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd146: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd147: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd148: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd149: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd150: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd151: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd152: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd153: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd154: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd155: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd156: rdata = 56'b00000000000000000000000000001101101101100000000001010001; 9'd157: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd158: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd159: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd160: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd161: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd162: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd163: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd164: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd165: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd166: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd167: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd168: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd169: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd170: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd171: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd172: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd173: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd174: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd175: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd176: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd177: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd178: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd179: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd180: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd181: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd182: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd183: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd184: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd185: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd186: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd187: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd188: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd189: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd190: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd191: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd192: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd193: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd194: rdata = 56'b10110100100100100100000000000000000000000000000001010110; 9'd195: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd196: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd197: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd198: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd199: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd200: rdata = 56'b00000000000000000000000000011111111111101101100001010001; 9'd201: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd202: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd203: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd204: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd205: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd206: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd207: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd208: rdata = 56'b00000000000000000000000011101101101101100000000001010001; 9'd209: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd210: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd211: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd212: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd213: rdata = 56'b11111111111101101101100000000000000000000000000001011100; 9'd214: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd215: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd216: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd217: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd218: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd219: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd220: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd221: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd222: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd223: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd224: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd225: rdata = 56'b00000000000000000000000000100100110110110110100001010111; 9'd226: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd227: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd228: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd229: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd230: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd231: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd232: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd233: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd234: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd235: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd236: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd237: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd238: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd239: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd240: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd241: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd242: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd243: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd244: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd245: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd246: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd247: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd248: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd249: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd250: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd251: rdata = 56'b00000000000000000000000000011111111111100000000001010001; 9'd252: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd253: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd254: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd255: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd256: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd257: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd258: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd259: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd260: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd261: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd262: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd263: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd264: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd265: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd266: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd267: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd268: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd269: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd270: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd271: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd272: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd273: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd274: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd275: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd276: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd277: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd278: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd279: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd280: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd281: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd282: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd283: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd284: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd285: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd286: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd287: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd288: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd289: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd290: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd291: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd292: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd293: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd294: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd295: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd296: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd297: rdata = 56'b00000000000000000000000000001101101101111111100001010001; 9'd298: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd299: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd300: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd301: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd302: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd303: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd304: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd305: rdata = 56'b00000000000000000000000001111111111111100000000001011101; 9'd306: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd307: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd308: rdata = 56'b00000000000000000000000000000000000000000000000000001101; 9'd309: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd310: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd311: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd312: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd313: rdata = 56'b00000000000000000000000000000000000000000000000000001101; 9'd314: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd315: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd316: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd317: rdata = 56'b00000000000000000000000000000000000000000000000000001001; 9'd318: rdata = 56'b00000000000000000110100000000000000000000000000001010110; 9'd319: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd320: rdata = 56'b00000000000000000000000000000000000000000000000000001000; 9'd321: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd322: rdata = 56'b00000000000000000000000000000000000000000000000001100000; 9'd323: rdata = 56'b00000000000000000000000000000000000000000000000001110000; default: rdata = 56'b00000000000000000000000000000000000000000000000001110000; endcase end always @ (posedge CLK) begin : READ_VALID if (RESET) begin DATA_OUT_VALID <= 1'b0; end else if (ENABLE) begin DATA_OUT_VALID <= 1'b1; end end always @(posedge CLK) begin if (ENABLE) DATA_OUT <= rdata; end endmodule
module ROM_ASIC #( parameter DATA_WIDTH = 16, parameter ADDR_WIDTH = 9, parameter INIT = "weight.txt", parameter TYPE = "block", parameter ROM_DEPTH = 1<<ADDR_WIDTH ) ( input wire CLK, input wire RESET, input wire [ADDR_WIDTH-1:0] ADDRESS, input wire ENABLE, output reg [DATA_WIDTH-1:0] DATA_OUT, output reg DATA_OUT_VALID );
localparam DEPTH = ROM_DEPTH; reg [DATA_WIDTH-1:0] rdata; wire [ADDR_WIDTH-1:0] address; assign address = ADDRESS; always @(*) begin case(address) 9'd0: rdata = 56'b00000000000000000000000000000000000000000000000000000001; 9'd1: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd2: rdata = 56'b00000000000000000000000000000000000000000000000000000001; 9'd3: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd4: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd5: rdata = 56'b00000000000000000000000000000000000000000000000000000011; 9'd6: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd7: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd8: rdata = 56'b00000000000000000000000000000000000000000000000000000011; 9'd9: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd10: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd11: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd12: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd13: rdata = 56'b00000000000000000000000000000000000000000000000000000111; 9'd14: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd15: rdata = 56'b00000000000000000000000000001101101101100000000001010001; 9'd16: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd17: rdata = 56'b00000000000000000000000000000000000000000000000000000111; 9'd18: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd19: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd20: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd21: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd22: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd23: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd24: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd25: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd26: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd27: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd28: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd29: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd30: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd31: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd32: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd33: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd34: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd35: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd36: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd37: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd38: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd39: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd40: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd41: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd42: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd43: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd44: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd45: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd46: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd47: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd48: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd49: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd50: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd51: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd52: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd53: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd54: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd55: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd56: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd57: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd58: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd59: rdata = 56'b00000000000000000000000000011111111111100000000001010001; 9'd60: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd61: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd62: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd63: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd64: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd65: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd66: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd67: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd68: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd69: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd70: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd71: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd72: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd73: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd74: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd75: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd76: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd77: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd78: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd79: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd80: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd81: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd82: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd83: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd84: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd85: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd86: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd87: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd88: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd89: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd90: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd91: rdata = 56'b00000000100100100110100000000000000000000000000001011010; 9'd92: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd93: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd94: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd95: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd96: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd97: rdata = 56'b00100110110110110100000000000000000000000000000001010110; 9'd98: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd99: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd100: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd101: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd102: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd103: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd104: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd105: rdata = 56'b00000000000000000000000000001101101101111111100001010101; 9'd106: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd107: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd108: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd109: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd110: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd111: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd112: rdata = 56'b00000000000000000000000001111111111111100000000001010001; 9'd113: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd114: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd115: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd116: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd117: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd118: rdata = 56'b01101101101111111111100000000000000000000000000001010000; 9'd119: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd120: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd121: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd122: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd123: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd124: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd125: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd126: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd127: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd128: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd129: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd130: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd131: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd132: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd133: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd134: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd135: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd136: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd137: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd138: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd139: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd140: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd141: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd142: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd143: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd144: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd145: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd146: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd147: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd148: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd149: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd150: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd151: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd152: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd153: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd154: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd155: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd156: rdata = 56'b00000000000000000000000000001101101101100000000001010001; 9'd157: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd158: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd159: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd160: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd161: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd162: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd163: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd164: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd165: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd166: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd167: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd168: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd169: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd170: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd171: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd172: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd173: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd174: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd175: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd176: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd177: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd178: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd179: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd180: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd181: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd182: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd183: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd184: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd185: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd186: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd187: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd188: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd189: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd190: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd191: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd192: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd193: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd194: rdata = 56'b10110100100100100100000000000000000000000000000001010110; 9'd195: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd196: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd197: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd198: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd199: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd200: rdata = 56'b00000000000000000000000000011111111111101101100001010001; 9'd201: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd202: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd203: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd204: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd205: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd206: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd207: rdata = 56'b00000000000000000000000000001101101101100000000001011101; 9'd208: rdata = 56'b00000000000000000000000011101101101101100000000001010001; 9'd209: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd210: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd211: rdata = 56'b00000000000001101101100000000000000000000000000001011000; 9'd212: rdata = 56'b00000000000000000000000001100000000000000000000001011001; 9'd213: rdata = 56'b11111111111101101101100000000000000000000000000001011100; 9'd214: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd215: rdata = 56'b00000000000000000000000001100000000000000000000001011101; 9'd216: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd217: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd218: rdata = 56'b01101101101100000000000000000000000000000000000001010100; 9'd219: rdata = 56'b01101101101100000000000000000000000000000000000001011000; 9'd220: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd221: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd222: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd223: rdata = 56'b00000000000000000000000000000000010110110110100001011111; 9'd224: rdata = 56'b00000000000000000000000000000000010110110110100001010011; 9'd225: rdata = 56'b00000000000000000000000000100100110110110110100001010111; 9'd226: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd227: rdata = 56'b00000000000000000010100000000000000000000000000001011010; 9'd228: rdata = 56'b00000000000000000000000010110110100000000000000001011011; 9'd229: rdata = 56'b00000000000000000010100000000000000000000000000001011110; 9'd230: rdata = 56'b00000000000000000010100000000000000000000000000001010010; 9'd231: rdata = 56'b00000000000000000010100000000000000000000000000001010110; 9'd232: rdata = 56'b00000000000000000000000010110110100000000000000001011111; 9'd233: rdata = 56'b00000000000000000000000010110110100000000000000001010011; 9'd234: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd235: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd236: rdata = 56'b00000010110110110100000000000000000000000000000001010110; 9'd237: rdata = 56'b00000010110110110100000000000000000000000000000001011010; 9'd238: rdata = 56'b00000010110110110100000000000000000000000000000001011110; 9'd239: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd240: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd241: rdata = 56'b00000000000000000000000000000000000000011111100001010001; 9'd242: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd243: rdata = 56'b00000000000000000000000000000000000000011111100001010101; 9'd244: rdata = 56'b10110100000000000000000000000000000000000000000001010110; 9'd245: rdata = 56'b00000000000000000000000000000000000000011111100001011001; 9'd246: rdata = 56'b10110100000000000000000000000000000000000000000001011010; 9'd247: rdata = 56'b00000000000000000000000000000000000000011111100001011101; 9'd248: rdata = 56'b10110100000000000000000000000000000000000000000001011110; 9'd249: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd250: rdata = 56'b00000000000000000000000000011111111111100000000001011101; 9'd251: rdata = 56'b00000000000000000000000000011111111111100000000001010001; 9'd252: rdata = 56'b00000000000000000000000000011111111111100000000001010101; 9'd253: rdata = 56'b00000000000000000000000000011111111111100000000001011001; 9'd254: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd255: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd256: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd257: rdata = 56'b00000000000011111111100000000000000000000000000001011100; 9'd258: rdata = 56'b00000000000011111111100000000000000000000000000001010000; 9'd259: rdata = 56'b00000000000011111111100000000000000000000000000001010100; 9'd260: rdata = 56'b00000000000000000000000011100000000000000000000001011101; 9'd261: rdata = 56'b00000000000000000000000011100000000000000000000001010001; 9'd262: rdata = 56'b00000000000000000000000011100000000000000000000001010101; 9'd263: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd264: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd265: rdata = 56'b11111111111100000000000000000000000000000000000001011000; 9'd266: rdata = 56'b11111111111100000000000000000000000000000000000001011100; 9'd267: rdata = 56'b11111111111100000000000000000000000000000000000001010000; 9'd268: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd269: rdata = 56'b00000000000000000000000000000000000100100100100001011111; 9'd270: rdata = 56'b00000000000000000000000000000000000100100100100001010011; 9'd271: rdata = 56'b00000000000000000000000000000000000100100100100001010111; 9'd272: rdata = 56'b00000000000000000000000000000000000100100100100001011011; 9'd273: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd274: rdata = 56'b00000000000000000000100000000000000000000000000001011010; 9'd275: rdata = 56'b00000000000000000000000000100100100000000000000001011011; 9'd276: rdata = 56'b00000000000000000000100000000000000000000000000001011110; 9'd277: rdata = 56'b00000000000000000000100000000000000000000000000001010010; 9'd278: rdata = 56'b00000000000000000000100000000000000000000000000001010110; 9'd279: rdata = 56'b00000000000000000000000000100100100000000000000001011111; 9'd280: rdata = 56'b00000000000000000000000000100100100000000000000001010011; 9'd281: rdata = 56'b00000000000000000000000000100100100000000000000001010111; 9'd282: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd283: rdata = 56'b00000000100100100100000000000000000000000000000001010110; 9'd284: rdata = 56'b00000000100100100100000000000000000000000000000001011010; 9'd285: rdata = 56'b00000000100100100100000000000000000000000000000001011110; 9'd286: rdata = 56'b00000000100100100100000000000000000000000000000001010010; 9'd287: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd288: rdata = 56'b00000000000000000000000000000000000000001101100001010001; 9'd289: rdata = 56'b00100100000000000000000000000000000000000000000001010010; 9'd290: rdata = 56'b00000000000000000000000000000000000000001101100001010101; 9'd291: rdata = 56'b00100100000000000000000000000000000000000000000001010110; 9'd292: rdata = 56'b00000000000000000000000000000000000000001101100001011001; 9'd293: rdata = 56'b00100100000000000000000000000000000000000000000001011010; 9'd294: rdata = 56'b00000000000000000000000000000000000000001101100001011101; 9'd295: rdata = 56'b00100100000000000000000000000000000000000000000001011110; 9'd296: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd297: rdata = 56'b00000000000000000000000000001101101101111111100001010001; 9'd298: rdata = 56'b10110100000000000000000000000000000000000000000001010010; 9'd299: rdata = 56'b00000000000000000000000000001101101101100000000001010101; 9'd300: rdata = 56'b00000000000000000000000000001101101101100000000001011001; 9'd301: rdata = 56'b00000000000000000000000000000000000000000000000000001111; 9'd302: rdata = 56'b00000000000001101101100000000000000000000000000001011100; 9'd303: rdata = 56'b00000000000001101101100000000000000000000000000001010000; 9'd304: rdata = 56'b00000000000001101101100000000000000000000000000001010100; 9'd305: rdata = 56'b00000000000000000000000001111111111111100000000001011101; 9'd306: rdata = 56'b00000000000000000000000001100000000000000000000001010001; 9'd307: rdata = 56'b00000000000000000000000001100000000000000000000001010101; 9'd308: rdata = 56'b00000000000000000000000000000000000000000000000000001101; 9'd309: rdata = 56'b00000000000011111111100000000000000000000000000001011000; 9'd310: rdata = 56'b00000000000000000000000011100000000000000000000001011001; 9'd311: rdata = 56'b01101101101100000000000000000000000000000000000001011100; 9'd312: rdata = 56'b01101101101100000000000000000000000000000000000001010000; 9'd313: rdata = 56'b00000000000000000000000000000000000000000000000000001101; 9'd314: rdata = 56'b11111111111100000000000000000000000000000000000001010100; 9'd315: rdata = 56'b00000000000000000000000000000000010110110110100001010111; 9'd316: rdata = 56'b00000000000000000000000000000000010110110110100001011011; 9'd317: rdata = 56'b00000000000000000000000000000000000000000000000000001001; 9'd318: rdata = 56'b00000000000000000110100000000000000000000000000001010110; 9'd319: rdata = 56'b00000000000000000000000010110110100000000000000001010111; 9'd320: rdata = 56'b00000000000000000000000000000000000000000000000000001000; 9'd321: rdata = 56'b00000010110110110100000000000000000000000000000001010010; 9'd322: rdata = 56'b00000000000000000000000000000000000000000000000001100000; 9'd323: rdata = 56'b00000000000000000000000000000000000000000000000001110000; default: rdata = 56'b00000000000000000000000000000000000000000000000001110000; endcase end always @ (posedge CLK) begin : READ_VALID if (RESET) begin DATA_OUT_VALID <= 1'b0; end else if (ENABLE) begin DATA_OUT_VALID <= 1'b1; end end always @(posedge CLK) begin if (ENABLE) DATA_OUT <= rdata; end endmodule
24
2,567
data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v
403,930,142
mkCSR_RegFile.v
v
3,659
87
['generated by']
[]
[]
[(114, 3657)]
null
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v:2956: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v:1130: Cannot find file containing module: \'mkCSR_MIE\'\n mkCSR_MIE csr_mie(.CLK(CLK),\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL,data/full_repos/permissive/403930142/mkCSR_MIE\n data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL,data/full_repos/permissive/403930142/mkCSR_MIE.v\n data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL,data/full_repos/permissive/403930142/mkCSR_MIE.sv\n mkCSR_MIE\n mkCSR_MIE.v\n mkCSR_MIE.sv\n obj_dir/mkCSR_MIE\n obj_dir/mkCSR_MIE.v\n obj_dir/mkCSR_MIE.sv\n%Error: data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v:1145: Cannot find file containing module: \'mkCSR_MIP\'\n mkCSR_MIP csr_mip(.CLK(CLK),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v:1164: Cannot find file containing module: \'FIFO20\'\n FIFO20 #(.guarded(32\'d1)) f_reset_rsps(.RST(RST_N),\n ^~~~~~\n%Error: data/full_repos/permissive/403930142/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v:1173: Cannot find file containing module: \'mkSoC_Map\'\n mkSoC_Map soc_map(.CLK(CLK),\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
192,537
module
module mkCSR_RegFile(CLK, RST_N, EN_server_reset_request_put, RDY_server_reset_request_put, EN_server_reset_response_get, RDY_server_reset_response_get, read_csr_csr_addr, read_csr, read_csr_port2_csr_addr, read_csr_port2, mav_read_csr_csr_addr, EN_mav_read_csr, mav_read_csr, mav_csr_write_csr_addr, mav_csr_write_word, EN_mav_csr_write, mav_csr_write, read_frm, ma_update_fcsr_fflags_flags, EN_ma_update_fcsr_fflags, ma_update_mstatus_fs_fs, EN_ma_update_mstatus_fs, read_misa, read_mstatus, read_sstatus, read_ustatus, read_satp, csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_nmi, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval, EN_csr_trap_actions, csr_trap_actions, RDY_csr_trap_actions, csr_ret_actions_from_priv, EN_csr_ret_actions, csr_ret_actions, RDY_csr_ret_actions, read_csr_minstret, EN_csr_minstret_incr, read_csr_mcycle, read_csr_mtime, access_permitted_1_priv, access_permitted_1_csr_addr, access_permitted_1_read_not_write, access_permitted_1, access_permitted_2_priv, access_permitted_2_csr_addr, access_permitted_2_read_not_write, access_permitted_2, csr_counter_read_fault_priv, csr_counter_read_fault_csr_addr, csr_counter_read_fault, csr_mip_read, m_external_interrupt_req_set_not_clear, s_external_interrupt_req_set_not_clear, timer_interrupt_req_set_not_clear, software_interrupt_req_set_not_clear, interrupt_pending_cur_priv, interrupt_pending, wfi_resume, nmi_req_set_not_clear, nmi_pending, EN_debug, RDY_debug); input CLK; input RST_N; input EN_server_reset_request_put; output RDY_server_reset_request_put; input EN_server_reset_response_get; output RDY_server_reset_response_get; input [11 : 0] read_csr_csr_addr; output [64 : 0] read_csr; input [11 : 0] read_csr_port2_csr_addr; output [64 : 0] read_csr_port2; input [11 : 0] mav_read_csr_csr_addr; input EN_mav_read_csr; output [64 : 0] mav_read_csr; input [11 : 0] mav_csr_write_csr_addr; input [63 : 0] mav_csr_write_word; input EN_mav_csr_write; output [63 : 0] mav_csr_write; output [2 : 0] read_frm; input [4 : 0] ma_update_fcsr_fflags_flags; input EN_ma_update_fcsr_fflags; input [1 : 0] ma_update_mstatus_fs_fs; input EN_ma_update_mstatus_fs; output [27 : 0] read_misa; output [63 : 0] read_mstatus; output [63 : 0] read_sstatus; output [63 : 0] read_ustatus; output [63 : 0] read_satp; input [1 : 0] csr_trap_actions_from_priv; input [63 : 0] csr_trap_actions_pc; input csr_trap_actions_nmi; input csr_trap_actions_interrupt; input [3 : 0] csr_trap_actions_exc_code; input [63 : 0] csr_trap_actions_xtval; input EN_csr_trap_actions; output [193 : 0] csr_trap_actions; output RDY_csr_trap_actions; input [1 : 0] csr_ret_actions_from_priv; input EN_csr_ret_actions; output [129 : 0] csr_ret_actions; output RDY_csr_ret_actions; output [63 : 0] read_csr_minstret; input EN_csr_minstret_incr; output [63 : 0] read_csr_mcycle; output [63 : 0] read_csr_mtime; input [1 : 0] access_permitted_1_priv; input [11 : 0] access_permitted_1_csr_addr; input access_permitted_1_read_not_write; output access_permitted_1; input [1 : 0] access_permitted_2_priv; input [11 : 0] access_permitted_2_csr_addr; input access_permitted_2_read_not_write; output access_permitted_2; input [1 : 0] csr_counter_read_fault_priv; input [11 : 0] csr_counter_read_fault_csr_addr; output csr_counter_read_fault; output [63 : 0] csr_mip_read; input m_external_interrupt_req_set_not_clear; input s_external_interrupt_req_set_not_clear; input timer_interrupt_req_set_not_clear; input software_interrupt_req_set_not_clear; input [1 : 0] interrupt_pending_cur_priv; output [4 : 0] interrupt_pending; output wfi_resume; input nmi_req_set_not_clear; output nmi_pending; input EN_debug; output RDY_debug; wire [193 : 0] csr_trap_actions; wire [129 : 0] csr_ret_actions; wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; wire [63 : 0] csr_mip_read, mav_csr_write, read_csr_mcycle, read_csr_minstret, read_csr_mtime, read_mstatus, read_satp, read_sstatus, read_ustatus; wire [27 : 0] read_misa; wire [4 : 0] interrupt_pending; wire [2 : 0] read_frm; wire RDY_csr_ret_actions, RDY_csr_trap_actions, RDY_debug, RDY_server_reset_request_put, RDY_server_reset_response_get, access_permitted_1, access_permitted_2, csr_counter_read_fault, nmi_pending, wfi_resume; reg [3 : 0] cfg_verbosity; wire [3 : 0] cfg_verbosity$D_IN; wire cfg_verbosity$EN; reg [63 : 0] csr_mstatus_rg_mstatus; reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; wire csr_mstatus_rg_mstatus$EN; reg [31 : 0] rg_dcsr; wire [31 : 0] rg_dcsr$D_IN; wire rg_dcsr$EN; reg [63 : 0] rg_dpc; wire [63 : 0] rg_dpc$D_IN; wire rg_dpc$EN; reg [63 : 0] rg_dscratch0; wire [63 : 0] rg_dscratch0$D_IN; wire rg_dscratch0$EN; reg [63 : 0] rg_dscratch1; wire [63 : 0] rg_dscratch1$D_IN; wire rg_dscratch1$EN; reg [4 : 0] rg_fflags; reg [4 : 0] rg_fflags$D_IN; wire rg_fflags$EN; reg [2 : 0] rg_frm; wire [2 : 0] rg_frm$D_IN; wire rg_frm$EN; reg [4 : 0] rg_mcause; reg [4 : 0] rg_mcause$D_IN; wire rg_mcause$EN; reg [2 : 0] rg_mcounteren; wire [2 : 0] rg_mcounteren$D_IN; wire rg_mcounteren$EN; reg [63 : 0] rg_mcycle; wire [63 : 0] rg_mcycle$D_IN; wire rg_mcycle$EN; reg [15 : 0] rg_medeleg; wire [15 : 0] rg_medeleg$D_IN; wire rg_medeleg$EN; reg [63 : 0] rg_mepc; wire [63 : 0] rg_mepc$D_IN; wire rg_mepc$EN; reg [11 : 0] rg_mideleg; wire [11 : 0] rg_mideleg$D_IN; wire rg_mideleg$EN; reg [63 : 0] rg_minstret; wire [63 : 0] rg_minstret$D_IN; wire rg_minstret$EN; reg [63 : 0] rg_mscratch; wire [63 : 0] rg_mscratch$D_IN; wire rg_mscratch$EN; reg [63 : 0] rg_mtval; wire [63 : 0] rg_mtval$D_IN; wire rg_mtval$EN; reg [62 : 0] rg_mtvec; wire [62 : 0] rg_mtvec$D_IN; wire rg_mtvec$EN; reg rg_nmi; wire rg_nmi$D_IN, rg_nmi$EN; reg [63 : 0] rg_nmi_vector; wire [63 : 0] rg_nmi_vector$D_IN; wire rg_nmi_vector$EN; reg [63 : 0] rg_satp; wire [63 : 0] rg_satp$D_IN; wire rg_satp$EN; reg [4 : 0] rg_scause; reg [4 : 0] rg_scause$D_IN; wire rg_scause$EN; reg [63 : 0] rg_sepc; wire [63 : 0] rg_sepc$D_IN; wire rg_sepc$EN; reg [63 : 0] rg_sscratch; wire [63 : 0] rg_sscratch$D_IN; wire rg_sscratch$EN; reg rg_state; wire rg_state$D_IN, rg_state$EN; reg [63 : 0] rg_stval; wire [63 : 0] rg_stval$D_IN; wire rg_stval$EN; reg [62 : 0] rg_stvec; wire [62 : 0] rg_stvec$D_IN; wire rg_stvec$EN; reg [63 : 0] rg_tdata1; wire [63 : 0] rg_tdata1$D_IN; wire rg_tdata1$EN; reg [63 : 0] rg_tdata2; wire [63 : 0] rg_tdata2$D_IN; wire rg_tdata2$EN; reg [63 : 0] rg_tdata3; wire [63 : 0] rg_tdata3$D_IN; wire rg_tdata3$EN; reg [63 : 0] rg_tselect; wire [63 : 0] rg_tselect$D_IN; wire rg_tselect$EN; wire [63 : 0] csr_mie$fav_sie_write, csr_mie$fav_sie_write_wordxl, csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read, csr_mie$fv_sie_read; wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; wire [63 : 0] csr_mip$fav_sip_write, csr_mip$fav_sip_write_wordxl, csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read, csr_mip$fv_sip_read; wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; wire csr_mip$EN_fav_sip_write, csr_mip$EN_fav_write, csr_mip$EN_reset, csr_mip$m_external_interrupt_req_req, csr_mip$s_external_interrupt_req_req, csr_mip$software_interrupt_req_req, csr_mip$timer_interrupt_req_req; wire f_reset_rsps$CLR, f_reset_rsps$DEQ, f_reset_rsps$EMPTY_N, f_reset_rsps$ENQ, f_reset_rsps$FULL_N; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_mtvec_reset_value, soc_map$m_nmivec_reset_value; wire CAN_FIRE_RL_rl_mcycle_incr, CAN_FIRE_RL_rl_reset_start, CAN_FIRE_RL_rl_upd_minstret_csrrx, CAN_FIRE_RL_rl_upd_minstret_incr, CAN_FIRE_csr_minstret_incr, CAN_FIRE_csr_ret_actions, CAN_FIRE_csr_trap_actions, CAN_FIRE_debug, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_ma_update_fcsr_fflags, CAN_FIRE_ma_update_mstatus_fs, CAN_FIRE_mav_csr_write, CAN_FIRE_mav_read_csr, CAN_FIRE_nmi_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_server_reset_request_put, CAN_FIRE_server_reset_response_get, CAN_FIRE_software_interrupt_req, CAN_FIRE_timer_interrupt_req, WILL_FIRE_RL_rl_mcycle_incr, WILL_FIRE_RL_rl_reset_start, WILL_FIRE_RL_rl_upd_minstret_csrrx, WILL_FIRE_RL_rl_upd_minstret_incr, WILL_FIRE_csr_minstret_incr, WILL_FIRE_csr_ret_actions, WILL_FIRE_csr_trap_actions, WILL_FIRE_debug, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_ma_update_fcsr_fflags, WILL_FIRE_ma_update_mstatus_fs, WILL_FIRE_mav_csr_write, WILL_FIRE_mav_read_csr, WILL_FIRE_nmi_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_server_reset_request_put, WILL_FIRE_server_reset_response_get, WILL_FIRE_software_interrupt_req, WILL_FIRE_timer_interrupt_req; wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, MUX_csr_mstatus_rg_mstatus$write_1__VAL_5, MUX_rg_minstret$write_1__VAL_1, MUX_rg_minstret$write_1__VAL_2; wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; wire [2 : 0] MUX_rg_frm$write_1__VAL_1; wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, MUX_rg_fflags$write_1__SEL_2, MUX_rg_frm$write_1__SEL_1, MUX_rg_mcause$write_1__SEL_2, MUX_rg_mcause$write_1__SEL_3, MUX_rg_mcounteren$write_1__SEL_1, MUX_rg_medeleg$write_1__SEL_1, MUX_rg_mideleg$write_1__SEL_1, MUX_rg_mtvec$write_1__SEL_1, MUX_rg_satp$write_1__SEL_1, MUX_rg_scause$write_1__SEL_2, MUX_rg_scause$write_1__SEL_3, MUX_rg_sepc$write_1__SEL_1, MUX_rg_state$write_1__SEL_2, MUX_rg_stval$write_1__SEL_1, MUX_rg_stvec$write_1__SEL_1, MUX_rg_tdata1$write_1__SEL_1, MUX_rw_minstret$wset_1__SEL_1; reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731, IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291, IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511, y_avValue_fst__h9500; reg [61 : 0] CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1; reg CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742, IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845; wire [63 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477, _theResult___fst__h13593, _theResult___fst__h13794, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267, exc_pc___1__h12586, exc_pc__h12512, mask__h11532, mask__h11549, mask__h13614, mask__h13631, result__h9129, v__h11328, v__h5882, v__h6026, v__h6140, v__h7518, v__h7554, v__h8224, v__h8286, v__h8442, val__h11533, val__h11550, val__h13632, vector_offset__h12513, wordxl1__h7649, x__h10300, x__h11531, x__h11544, x__h11561, x__h13437, x__h13438, x__h13613, x__h13626, x__h13643, y__h11545, y__h11562, y__h13627, y__h13644, y_avValue_fst__h12469, y_avValue_fst__h12486, y_avValue_snd_snd__h12559; wire [22 : 0] fixed_up_val_23__h11372, fixed_up_val_23__h13500, fixed_up_val_23__h6191, fixed_up_val_23__h7690, fixed_up_val_23__h9712; wire [5 : 0] ie_from_x__h13577, ie_to_x__h11449, pie_from_x__h13578, pie_to_x__h11450; wire [3 : 0] IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928, exc_code__h13279; wire [1 : 0] IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, _theResult____h15189, _theResult____h15401, _theResult____h15613, _theResult____h15825, _theResult____h16037, _theResult____h16249, _theResult____h16461, _theResult____h16673, _theResult____h16885, _theResult___fst__h11461, new_priv__h11323, to_y__h13793; wire NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598, NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701, NOT_cfg_verbosity_read__42_ULE_1_43___d944, NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902, NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883, NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856, NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892, NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865, NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901, NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874, NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402, b__h11548, b__h13630, csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821, csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745, csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811, csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788, csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755, csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799, csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766, csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810, csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777, csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301, csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453, deleg_bit___1__h11470, deleg_bit___1__h11485, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817, mav_csr_write_csr_addr_ULE_0x33F___d739, mav_csr_write_csr_addr_ULE_0xB1F___d735, mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940, mav_csr_write_csr_addr_ULT_0x323___d738, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861, mav_csr_write_csr_addr_ULT_0xB03___d734, sd__h11371, sd__h13499, sd__h7689, sd__h9711; assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign CAN_FIRE_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; assign read_csr = { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || read_csr_csr_addr == 12'h001 || read_csr_csr_addr == 12'h002 || read_csr_csr_addr == 12'h003 || read_csr_csr_addr == 12'hC00 || read_csr_csr_addr == 12'hC02 || read_csr_csr_addr == 12'h100 || read_csr_csr_addr == 12'h102 || read_csr_csr_addr == 12'h103 || read_csr_csr_addr == 12'h104 || read_csr_csr_addr == 12'h105 || read_csr_csr_addr == 12'h106 || read_csr_csr_addr == 12'h140 || read_csr_csr_addr == 12'h141 || read_csr_csr_addr == 12'h142 || read_csr_csr_addr == 12'h143 || read_csr_csr_addr == 12'h144 || read_csr_csr_addr == 12'h180 || read_csr_csr_addr == 12'h302 || read_csr_csr_addr == 12'h303 || read_csr_csr_addr == 12'hF11 || read_csr_csr_addr == 12'hF12 || read_csr_csr_addr == 12'hF13 || read_csr_csr_addr == 12'hF14 || read_csr_csr_addr == 12'h300 || read_csr_csr_addr == 12'h301 || read_csr_csr_addr == 12'h304 || read_csr_csr_addr == 12'h305 || read_csr_csr_addr == 12'h306 || read_csr_csr_addr == 12'h340 || read_csr_csr_addr == 12'h341 || read_csr_csr_addr == 12'h342 || read_csr_csr_addr == 12'h343 || read_csr_csr_addr == 12'h344 || read_csr_csr_addr == 12'hB00 || read_csr_csr_addr == 12'hB02 || read_csr_csr_addr == 12'h7A0 || read_csr_csr_addr == 12'h7A1 || read_csr_csr_addr == 12'h7A2 || read_csr_csr_addr == 12'h7A3, (read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 } ; assign read_csr_port2 = { read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F || read_csr_port2_csr_addr == 12'h001 || read_csr_port2_csr_addr == 12'h002 || read_csr_port2_csr_addr == 12'h003 || read_csr_port2_csr_addr == 12'hC00 || read_csr_port2_csr_addr == 12'hC02 || read_csr_port2_csr_addr == 12'h100 || read_csr_port2_csr_addr == 12'h102 || read_csr_port2_csr_addr == 12'h103 || read_csr_port2_csr_addr == 12'h104 || read_csr_port2_csr_addr == 12'h105 || read_csr_port2_csr_addr == 12'h106 || read_csr_port2_csr_addr == 12'h140 || read_csr_port2_csr_addr == 12'h141 || read_csr_port2_csr_addr == 12'h142 || read_csr_port2_csr_addr == 12'h143 || read_csr_port2_csr_addr == 12'h144 || read_csr_port2_csr_addr == 12'h180 || read_csr_port2_csr_addr == 12'h302 || read_csr_port2_csr_addr == 12'h303 || read_csr_port2_csr_addr == 12'hF11 || read_csr_port2_csr_addr == 12'hF12 || read_csr_port2_csr_addr == 12'hF13 || read_csr_port2_csr_addr == 12'hF14 || read_csr_port2_csr_addr == 12'h300 || read_csr_port2_csr_addr == 12'h301 || read_csr_port2_csr_addr == 12'h304 || read_csr_port2_csr_addr == 12'h305 || read_csr_port2_csr_addr == 12'h306 || read_csr_port2_csr_addr == 12'h340 || read_csr_port2_csr_addr == 12'h341 || read_csr_port2_csr_addr == 12'h342 || read_csr_port2_csr_addr == 12'h343 || read_csr_port2_csr_addr == 12'h344 || read_csr_port2_csr_addr == 12'hB00 || read_csr_port2_csr_addr == 12'hB02 || read_csr_port2_csr_addr == 12'h7A0 || read_csr_port2_csr_addr == 12'h7A1 || read_csr_port2_csr_addr == 12'h7A2 || read_csr_port2_csr_addr == 12'h7A3, (read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 } ; assign mav_read_csr = { mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F || mav_read_csr_csr_addr == 12'h001 || mav_read_csr_csr_addr == 12'h002 || mav_read_csr_csr_addr == 12'h003 || mav_read_csr_csr_addr == 12'hC00 || mav_read_csr_csr_addr == 12'hC02 || mav_read_csr_csr_addr == 12'h100 || mav_read_csr_csr_addr == 12'h102 || mav_read_csr_csr_addr == 12'h103 || mav_read_csr_csr_addr == 12'h104 || mav_read_csr_csr_addr == 12'h105 || mav_read_csr_csr_addr == 12'h106 || mav_read_csr_csr_addr == 12'h140 || mav_read_csr_csr_addr == 12'h141 || mav_read_csr_csr_addr == 12'h142 || mav_read_csr_csr_addr == 12'h143 || mav_read_csr_csr_addr == 12'h144 || mav_read_csr_csr_addr == 12'h180 || mav_read_csr_csr_addr == 12'h302 || mav_read_csr_csr_addr == 12'h303 || mav_read_csr_csr_addr == 12'hF11 || mav_read_csr_csr_addr == 12'hF12 || mav_read_csr_csr_addr == 12'hF13 || mav_read_csr_csr_addr == 12'hF14 || mav_read_csr_csr_addr == 12'h300 || mav_read_csr_csr_addr == 12'h301 || mav_read_csr_csr_addr == 12'h304 || mav_read_csr_csr_addr == 12'h305 || mav_read_csr_csr_addr == 12'h306 || mav_read_csr_csr_addr == 12'h340 || mav_read_csr_csr_addr == 12'h341 || mav_read_csr_csr_addr == 12'h342 || mav_read_csr_csr_addr == 12'h343 || mav_read_csr_csr_addr == 12'h344 || mav_read_csr_csr_addr == 12'hB00 || mav_read_csr_csr_addr == 12'hB02 || mav_read_csr_csr_addr == 12'h7A0 || mav_read_csr_csr_addr == 12'h7A1 || mav_read_csr_csr_addr == 12'h7A2 || mav_read_csr_csr_addr == 12'h7A3, (mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 } ; assign CAN_FIRE_mav_read_csr = 1'd1 ; assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; assign mav_csr_write = (!mav_csr_write_csr_addr_ULT_0xB03___d734 && mav_csr_write_csr_addr_ULE_0xB1F___d735 || !mav_csr_write_csr_addr_ULT_0x323___d738 && mav_csr_write_csr_addr_ULE_0x33F___d739) ? 64'd0 : y_avValue_fst__h9500 ; assign CAN_FIRE_mav_csr_write = 1'd1 ; assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; assign read_frm = rg_frm ; assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; assign read_misa = 28'd135532845 ; assign read_mstatus = csr_mstatus_rg_mstatus ; assign read_sstatus = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] } ; assign read_ustatus = { 59'd0, csr_mstatus_rg_mstatus[4], 3'd0, csr_mstatus_rg_mstatus[0] } ; assign read_satp = rg_satp ; assign csr_trap_actions = { x__h10300, x__h13437, x__h13438, new_priv__h11323 } ; assign RDY_csr_trap_actions = 1'd1 ; assign CAN_FIRE_csr_trap_actions = 1'd1 ; assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; assign csr_ret_actions = (csr_ret_actions_from_priv == 2'b11) ? { rg_mepc, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[12:11], _theResult___fst__h13593 } : { rg_sepc, to_y__h13793, _theResult___fst__h13794 } ; assign RDY_csr_ret_actions = 1'd1 ; assign CAN_FIRE_csr_ret_actions = 1'd1 ; assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; assign read_csr_minstret = rg_minstret ; assign CAN_FIRE_csr_minstret_incr = 1'd1 ; assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; assign read_csr_mcycle = rg_mcycle ; assign read_csr_mtime = rg_mcycle ; assign access_permitted_1 = NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 && (access_permitted_1_read_not_write || access_permitted_1_csr_addr[11:10] != 2'b11) ; assign access_permitted_2 = NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 && (access_permitted_2_read_not_write || access_permitted_2_csr_addr[11:10] != 2'b11) ; assign csr_counter_read_fault = (csr_counter_read_fault_priv == 2'b01 || csr_counter_read_fault_priv == 2'b0) && (csr_counter_read_fault_csr_addr == 12'hC00 && !rg_mcounteren[0] || csr_counter_read_fault_csr_addr == 12'hC01 && !rg_mcounteren[1] || csr_counter_read_fault_csr_addr == 12'hC02 && !rg_mcounteren[2] || csr_counter_read_fault_csr_addr >= 12'hC03 && csr_counter_read_fault_csr_addr <= 12'hC1F) ; assign csr_mip_read = csr_mip$fv_read ; assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; assign CAN_FIRE_timer_interrupt_req = 1'd1 ; assign WILL_FIRE_timer_interrupt_req = 1'd1 ; assign CAN_FIRE_software_interrupt_req = 1'd1 ; assign WILL_FIRE_software_interrupt_req = 1'd1 ; assign interrupt_pending = { csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 || csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 || csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 } ; assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; assign CAN_FIRE_nmi_req = 1'd1 ; assign WILL_FIRE_nmi_req = 1'd1 ; assign nmi_pending = rg_nmi ; assign RDY_debug = 1'd1 ; assign CAN_FIRE_debug = 1'd1 ; assign WILL_FIRE_debug = EN_debug ; mkCSR_MIE csr_mie(.CLK(CLK), .RST_N(RST_N), .fav_sie_write_misa(csr_mie$fav_sie_write_misa), .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), .fav_write_misa(csr_mie$fav_write_misa), .fav_write_wordxl(csr_mie$fav_write_wordxl), .EN_reset(csr_mie$EN_reset), .EN_fav_write(csr_mie$EN_fav_write), .EN_fav_sie_write(csr_mie$EN_fav_sie_write), .fv_read(csr_mie$fv_read), .fav_write(csr_mie$fav_write), .fv_sie_read(csr_mie$fv_sie_read), .fav_sie_write(csr_mie$fav_sie_write)); mkCSR_MIP csr_mip(.CLK(CLK), .RST_N(RST_N), .fav_sip_write_misa(csr_mip$fav_sip_write_misa), .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), .fav_write_misa(csr_mip$fav_write_misa), .fav_write_wordxl(csr_mip$fav_write_wordxl), .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), .software_interrupt_req_req(csr_mip$software_interrupt_req_req), .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), .EN_reset(csr_mip$EN_reset), .EN_fav_write(csr_mip$EN_fav_write), .EN_fav_sip_write(csr_mip$EN_fav_sip_write), .fv_read(csr_mip$fv_read), .fav_write(csr_mip$fav_write), .fv_sip_read(csr_mip$fv_sip_read), .fav_sip_write(csr_mip$fav_sip_write)); FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), .CLK(CLK), .ENQ(f_reset_rsps$ENQ), .DEQ(f_reset_rsps$DEQ), .CLR(f_reset_rsps$CLR), .FULL_N(f_reset_rsps$FULL_N), .EMPTY_N(f_reset_rsps$EMPTY_N)); mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_near_mem_io_addr_base(), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(), .m_plic_addr_base(), .m_plic_addr_size(), .m_plic_addr_lim(), .m_uart0_addr_base(), .m_uart0_addr_size(), .m_uart0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_mem0_controller_addr_base(), .m_mem0_controller_addr_size(), .m_mem0_controller_addr_lim(), .m_tcm_addr_base(), .m_tcm_addr_size(), .m_tcm_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); assign CAN_FIRE_RL_rl_reset_start = !rg_state ; assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; assign CAN_FIRE_RL_rl_upd_minstret_csrrx = MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; assign WILL_FIRE_RL_rl_upd_minstret_csrrx = CAN_FIRE_RL_rl_upd_minstret_csrrx ; assign CAN_FIRE_RL_rl_upd_minstret_incr = !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; assign WILL_FIRE_RL_rl_upd_minstret_incr = CAN_FIRE_RL_rl_upd_minstret_incr ; assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 ; assign MUX_rg_fflags$write_1__SEL_2 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ; assign MUX_rg_frm$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 ; assign MUX_rg_mcause$write_1__SEL_2 = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ; assign MUX_rg_mcause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 ; assign MUX_rg_mcounteren$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 ; assign MUX_rg_medeleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 ; assign MUX_rg_mideleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ; assign MUX_rg_mtvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 ; assign MUX_rg_satp$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ; assign MUX_rg_scause$write_1__SEL_2 = EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign MUX_rg_scause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 ; assign MUX_rg_sepc$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ; assign MUX_rg_state$write_1__SEL_2 = CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; assign MUX_rg_stval$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ; assign MUX_rg_stvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ; assign MUX_rg_tdata1$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 ; assign MUX_rw_minstret$wset_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = { sd__h13499, 40'd5120, fixed_up_val_23__h13500 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = { sd__h9711, 40'd5120, fixed_up_val_23__h9712 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = { sd__h7689, 40'd5120, (mav_csr_write_csr_addr == 12'h100) ? fixed_up_val_23__h6191 : fixed_up_val_23__h7690 } ; assign MUX_rg_fflags$write_1__VAL_3 = rg_fflags | ma_update_fcsr_fflags_flags ; assign MUX_rg_frm$write_1__VAL_1 = (mav_csr_write_csr_addr == 12'h002) ? mav_csr_write_word[2:0] : mav_csr_write_word[7:5] ; assign MUX_rg_mcause$write_1__VAL_2 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, exc_code__h13279 } ; assign MUX_rg_mcause$write_1__VAL_3 = { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; assign MUX_rg_medeleg$write_1__VAL_1 = { mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign MUX_rg_minstret$write_1__VAL_1 = MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; assign MUX_rg_mtvec$write_1__VAL_1 = { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; assign MUX_rg_mtvec$write_1__VAL_2 = { soc_map$m_mtvec_reset_value[63:2], soc_map$m_mtvec_reset_value[0] } ; assign cfg_verbosity$D_IN = 4'h0 ; assign cfg_verbosity$EN = 1'b0 ; always@(WILL_FIRE_RL_rl_reset_start or EN_csr_ret_actions or MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or EN_csr_trap_actions or v__h11328 or EN_ma_update_mstatus_fs or MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) case (1'b1) WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000; EN_csr_ret_actions: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h11328; EN_ma_update_mstatus_fs: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; default: csr_mstatus_rg_mstatus$D_IN = 64'hAAAAAAAAAAAAAAAA; endcase assign csr_mstatus_rg_mstatus$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 || EN_csr_trap_actions || EN_ma_update_mstatus_fs || EN_csr_ret_actions || WILL_FIRE_RL_rl_reset_start ; assign rg_dcsr$D_IN = 32'h0 ; assign rg_dcsr$EN = 1'b0 ; assign rg_dpc$D_IN = 64'h0 ; assign rg_dpc$EN = 1'b0 ; assign rg_dscratch0$D_IN = 64'h0 ; assign rg_dscratch0$EN = 1'b0 ; assign rg_dscratch1$D_IN = 64'h0 ; assign rg_dscratch1$EN = 1'b0 ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_fflags$write_1__SEL_2 or mav_csr_write_word or EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; default: rg_fflags$D_IN = 5'b01010; endcase assign rg_fflags$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 || EN_ma_update_fcsr_fflags || WILL_FIRE_RL_rl_reset_start ; assign rg_frm$D_IN = MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; assign rg_frm$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 || WILL_FIRE_RL_rl_reset_start ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_mcause$write_1__SEL_2 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; MUX_rg_mcause$write_1__SEL_2: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_mcause$write_1__SEL_3: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_mcause$D_IN = 5'b01010; endcase assign rg_mcause$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 || WILL_FIRE_RL_rl_reset_start ; assign rg_mcounteren$D_IN = MUX_rg_mcounteren$write_1__SEL_1 ? mav_csr_write_word[2:0] : 3'd0 ; assign rg_mcounteren$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 || WILL_FIRE_RL_rl_reset_start ; assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; assign rg_mcycle$EN = 1'd1 ; assign rg_medeleg$D_IN = MUX_rg_medeleg$write_1__SEL_1 ? MUX_rg_medeleg$write_1__VAL_1 : 16'd0 ; assign rg_medeleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 || WILL_FIRE_RL_rl_reset_start ; assign rg_mepc$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_pc : mav_csr_write_word ; assign rg_mepc$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 ; assign rg_mideleg$D_IN = MUX_rg_mideleg$write_1__SEL_1 ? mav_csr_write_word[11:0] : 12'd0 ; assign rg_mideleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 || WILL_FIRE_RL_rl_reset_start ; assign rg_minstret$D_IN = WILL_FIRE_RL_rl_upd_minstret_csrrx ? MUX_rg_minstret$write_1__VAL_1 : MUX_rg_minstret$write_1__VAL_2 ; assign rg_minstret$EN = WILL_FIRE_RL_rl_upd_minstret_csrrx || WILL_FIRE_RL_rl_upd_minstret_incr ; assign rg_mscratch$D_IN = mav_csr_write_word ; assign rg_mscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ; assign rg_mtval$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_xtval : mav_csr_write_word ; assign rg_mtval$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 ; assign rg_mtvec$D_IN = MUX_rg_mtvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_mtvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 || WILL_FIRE_RL_rl_reset_start ; assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; assign rg_nmi$EN = 1'b1 ; assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; assign rg_satp$D_IN = MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign rg_satp$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 || WILL_FIRE_RL_rl_reset_start ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_scause$write_1__SEL_2 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; MUX_rg_scause$write_1__SEL_2: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_scause$write_1__SEL_3: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_scause$D_IN = 5'b01010; endcase assign rg_scause$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 || WILL_FIRE_RL_rl_reset_start ; assign rg_sepc$D_IN = MUX_rg_sepc$write_1__SEL_1 ? mav_csr_write_word : csr_trap_actions_pc ; assign rg_sepc$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign rg_sscratch$D_IN = mav_csr_write_word ; assign rg_sscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 ; assign rg_state$D_IN = !EN_server_reset_request_put ; assign rg_state$EN = EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; assign rg_stval$D_IN = MUX_rg_stval$write_1__SEL_1 ? mav_csr_write_word : csr_trap_actions_xtval ; assign rg_stval$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign rg_stvec$D_IN = MUX_rg_stvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_stvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 || WILL_FIRE_RL_rl_reset_start ; assign rg_tdata1$D_IN = MUX_rg_tdata1$write_1__SEL_1 ? result__h9129 : 64'd0 ; assign rg_tdata1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 || WILL_FIRE_RL_rl_reset_start ; assign rg_tdata2$D_IN = mav_csr_write_word ; assign rg_tdata2$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 ; assign rg_tdata3$D_IN = mav_csr_write_word ; assign rg_tdata3$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 ; assign rg_tselect$D_IN = 64'd0 ; assign rg_tselect$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 || WILL_FIRE_RL_rl_reset_start ; assign csr_mie$fav_sie_write_misa = 28'd135532845 ; assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; assign csr_mie$fav_write_misa = 28'd135532845 ; assign csr_mie$fav_write_wordxl = mav_csr_write_word ; assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mie$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 ; assign csr_mie$EN_fav_sie_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 ; assign csr_mip$fav_sip_write_misa = 28'd135532845 ; assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; assign csr_mip$fav_write_misa = 28'd135532845 ; assign csr_mip$fav_write_wordxl = mav_csr_write_word ; assign csr_mip$m_external_interrupt_req_req = m_external_interrupt_req_set_not_clear ; assign csr_mip$s_external_interrupt_req_req = s_external_interrupt_req_set_not_clear ; assign csr_mip$software_interrupt_req_req = software_interrupt_req_set_not_clear ; assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mip$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 ; assign csr_mip$EN_fav_sip_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 ; assign f_reset_rsps$ENQ = EN_server_reset_request_put ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275 = (new_priv__h11323 == 2'b11) ? { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:13], csr_trap_actions_from_priv, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[10:0] } : { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:9], csr_trap_actions_from_priv[0], csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[7:0] } ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865) ? 4'd9 : ((NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856) ? 4'd7 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 ? 4'd3 : 4'd11)) ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883) ? 4'd5 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 ? 4'd1 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923) ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892) ? 4'd8 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 && NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910) ? 4'd4 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 ? 4'd0 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926) ; assign IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774 = (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? 2'b01 : csr_mstatus_rg_mstatus[12:11] ; assign IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477 = (csr_ret_actions_from_priv == 2'b11) ? _theResult___fst__h13593 : _theResult___fst__h13794 ; assign NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 = (access_permitted_1_csr_addr >= 12'hC03 && access_permitted_1_csr_addr <= 12'hC1F || access_permitted_1_csr_addr >= 12'hB03 && access_permitted_1_csr_addr <= 12'hB1F || access_permitted_1_csr_addr >= 12'h323 && access_permitted_1_csr_addr <= 12'h33F || access_permitted_1_csr_addr == 12'h001 || access_permitted_1_csr_addr == 12'h002 || access_permitted_1_csr_addr == 12'h003 || access_permitted_1_csr_addr == 12'hC00 || access_permitted_1_csr_addr == 12'hC02 || access_permitted_1_csr_addr == 12'h100 || access_permitted_1_csr_addr == 12'h102 || access_permitted_1_csr_addr == 12'h103 || access_permitted_1_csr_addr == 12'h104 || access_permitted_1_csr_addr == 12'h105 || access_permitted_1_csr_addr == 12'h106 || access_permitted_1_csr_addr == 12'h140 || access_permitted_1_csr_addr == 12'h141 || access_permitted_1_csr_addr == 12'h142 || access_permitted_1_csr_addr == 12'h143 || access_permitted_1_csr_addr == 12'h144 || access_permitted_1_csr_addr == 12'h180 || access_permitted_1_csr_addr == 12'h302 || access_permitted_1_csr_addr == 12'h303 || access_permitted_1_csr_addr == 12'hF11 || access_permitted_1_csr_addr == 12'hF12 || access_permitted_1_csr_addr == 12'hF13 || access_permitted_1_csr_addr == 12'hF14 || access_permitted_1_csr_addr == 12'h300 || access_permitted_1_csr_addr == 12'h301 || access_permitted_1_csr_addr == 12'h304 || access_permitted_1_csr_addr == 12'h305 || access_permitted_1_csr_addr == 12'h306 || access_permitted_1_csr_addr == 12'h340 || access_permitted_1_csr_addr == 12'h341 || access_permitted_1_csr_addr == 12'h342 || access_permitted_1_csr_addr == 12'h343 || access_permitted_1_csr_addr == 12'h344 || access_permitted_1_csr_addr == 12'hB00 || access_permitted_1_csr_addr == 12'hB02 || access_permitted_1_csr_addr == 12'h7A0 || access_permitted_1_csr_addr == 12'h7A1 || access_permitted_1_csr_addr == 12'h7A2 || access_permitted_1_csr_addr == 12'h7A3) && access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && (access_permitted_1_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 = (access_permitted_2_csr_addr >= 12'hC03 && access_permitted_2_csr_addr <= 12'hC1F || access_permitted_2_csr_addr >= 12'hB03 && access_permitted_2_csr_addr <= 12'hB1F || access_permitted_2_csr_addr >= 12'h323 && access_permitted_2_csr_addr <= 12'h33F || access_permitted_2_csr_addr == 12'h001 || access_permitted_2_csr_addr == 12'h002 || access_permitted_2_csr_addr == 12'h003 || access_permitted_2_csr_addr == 12'hC00 || access_permitted_2_csr_addr == 12'hC02 || access_permitted_2_csr_addr == 12'h100 || access_permitted_2_csr_addr == 12'h102 || access_permitted_2_csr_addr == 12'h103 || access_permitted_2_csr_addr == 12'h104 || access_permitted_2_csr_addr == 12'h105 || access_permitted_2_csr_addr == 12'h106 || access_permitted_2_csr_addr == 12'h140 || access_permitted_2_csr_addr == 12'h141 || access_permitted_2_csr_addr == 12'h142 || access_permitted_2_csr_addr == 12'h143 || access_permitted_2_csr_addr == 12'h144 || access_permitted_2_csr_addr == 12'h180 || access_permitted_2_csr_addr == 12'h302 || access_permitted_2_csr_addr == 12'h303 || access_permitted_2_csr_addr == 12'hF11 || access_permitted_2_csr_addr == 12'hF12 || access_permitted_2_csr_addr == 12'hF13 || access_permitted_2_csr_addr == 12'hF14 || access_permitted_2_csr_addr == 12'h300 || access_permitted_2_csr_addr == 12'h301 || access_permitted_2_csr_addr == 12'h304 || access_permitted_2_csr_addr == 12'h305 || access_permitted_2_csr_addr == 12'h306 || access_permitted_2_csr_addr == 12'h340 || access_permitted_2_csr_addr == 12'h341 || access_permitted_2_csr_addr == 12'h342 || access_permitted_2_csr_addr == 12'h343 || access_permitted_2_csr_addr == 12'h344 || access_permitted_2_csr_addr == 12'hB00 || access_permitted_2_csr_addr == 12'hB02 || access_permitted_2_csr_addr == 12'h7A0 || access_permitted_2_csr_addr == 12'h7A1 || access_permitted_2_csr_addr == 12'h7A2 || access_permitted_2_csr_addr == 12'h7A3) && access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && (access_permitted_2_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_cfg_verbosity_read__42_ULE_1_43___d944 = cfg_verbosity > 4'd1 ; assign NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910 = !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 = !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 = NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 && NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 = NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 && NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 ; assign NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 = !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 = !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 = !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 = !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 = !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 = !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402 = !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 != 4'd0 && exc_code__h13279 != 4'd1 && exc_code__h13279 != 4'd2 && exc_code__h13279 != 4'd3 && exc_code__h13279 != 4'd4 && exc_code__h13279 != 4'd5 && exc_code__h13279 != 4'd6 && exc_code__h13279 != 4'd7 && exc_code__h13279 != 4'd8 && exc_code__h13279 != 4'd9 && exc_code__h13279 != 4'd10 && exc_code__h13279 != 4'd11 ; assign _theResult____h15189 = rg_mideleg[11] ? 2'b01 : 2'b11 ; assign _theResult____h15401 = rg_mideleg[3] ? 2'b01 : 2'b11 ; assign _theResult____h15613 = rg_mideleg[7] ? 2'b01 : 2'b11 ; assign _theResult____h15825 = rg_mideleg[9] ? 2'b01 : 2'b11 ; assign _theResult____h16037 = rg_mideleg[1] ? 2'b01 : 2'b11 ; assign _theResult____h16249 = rg_mideleg[5] ? 2'b01 : 2'b11 ; assign _theResult____h16461 = rg_mideleg[8] ? 2'b01 : 2'b11 ; assign _theResult____h16673 = rg_mideleg[0] ? 2'b01 : 2'b11 ; assign _theResult____h16885 = rg_mideleg[4] ? 2'b01 : 2'b11 ; assign _theResult___fst__h11461 = (csr_trap_actions_interrupt ? deleg_bit___1__h11470 : deleg_bit___1__h11485) ? 2'b01 : 2'b11 ; assign _theResult___fst__h13593 = { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:13], 2'd0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[10:0] } ; assign _theResult___fst__h13794 = { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:9], 1'd0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[7:0] } ; assign b__h11548 = csr_mstatus_rg_mstatus[ie_to_x__h11449] ; assign b__h13630 = csr_mstatus_rg_mstatus[pie_from_x__h13578] ; assign csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 = csr_mip$fv_read[0] && csr_mie$fv_read[0] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 = csr_mip$fv_read[11] && csr_mie$fv_read[11] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 = csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 || csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 || csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 || csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 || csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 || csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 || csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 ; assign csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 = csr_mip$fv_read[1] && csr_mie$fv_read[1] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 = csr_mip$fv_read[3] && csr_mie$fv_read[3] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832 = csr_mip$fv_read[4] && csr_mie$fv_read[4] && (interrupt_pending_cur_priv < _theResult____h16885 || interrupt_pending_cur_priv == _theResult____h16885 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 = csr_mip$fv_read[5] && csr_mie$fv_read[5] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 = csr_mip$fv_read[7] && csr_mie$fv_read[7] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 = csr_mip$fv_read[8] && csr_mie$fv_read[8] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 = csr_mip$fv_read[9] && csr_mie$fv_read[9] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470 = x__h13626 | mask__h13614 ; assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267 = x__h11544 | val__h11533 ; assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 = csr_trap_actions_interrupt && !csr_trap_actions_nmi && CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453 = (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 != 4'd0 && exc_code__h13279 != 4'd1 && exc_code__h13279 != 4'd2 && exc_code__h13279 != 4'd3 && exc_code__h13279 != 4'd4 && exc_code__h13279 != 4'd5 && exc_code__h13279 != 4'd6 && exc_code__h13279 != 4'd7 && exc_code__h13279 != 4'd8 && exc_code__h13279 != 4'd9 && exc_code__h13279 != 4'd11 && exc_code__h13279 != 4'd12 && exc_code__h13279 != 4'd13 && exc_code__h13279 != 4'd15 ; assign deleg_bit___1__h11470 = rg_mideleg[csr_trap_actions_exc_code] ; assign deleg_bit___1__h11485 = rg_medeleg[csr_trap_actions_exc_code] ; assign exc_code__h13279 = csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; assign exc_pc___1__h12586 = exc_pc__h12512 + vector_offset__h12513 ; assign exc_pc__h12512 = csr_trap_actions_nmi ? rg_nmi_vector : y_avValue_snd_snd__h12559 ; assign fixed_up_val_23__h11372 = { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[22:17], 2'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11] == 2'b10) ? 2'b01 : IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11], IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[10:5], 1'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[3:1], 1'd0 } ; assign fixed_up_val_23__h13500 = { IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[22:17], 2'd0, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13], (IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11] == 2'b10) ? 2'b01 : IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11], IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[10:5], 1'd0, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[3:1], 1'd0 } ; assign fixed_up_val_23__h6191 = { csr_mstatus_rg_mstatus[22:20], mav_csr_write_word[19:18], csr_mstatus_rg_mstatus[17], 2'd0, mav_csr_write_word[14:13], IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, csr_mstatus_rg_mstatus[10:9], mav_csr_write_word[8], csr_mstatus_rg_mstatus[7:6], mav_csr_write_word[5], 1'd0, csr_mstatus_rg_mstatus[3:2], mav_csr_write_word[1], 1'd0 } ; assign fixed_up_val_23__h7690 = { mav_csr_write_word[22:17], 2'd0, mav_csr_write_word[14:13], (mav_csr_write_word[12:11] == 2'b10) ? 2'b01 : mav_csr_write_word[12:11], mav_csr_write_word[10:5], 1'd0, mav_csr_write_word[3:1], 1'd0 } ; assign fixed_up_val_23__h9712 = { csr_mstatus_rg_mstatus[22:17], 2'd0, ma_update_mstatus_fs_fs, IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, csr_mstatus_rg_mstatus[10:5], 1'd0, csr_mstatus_rg_mstatus[3:1], 1'd0 } ; assign ie_from_x__h13577 = { 4'd0, csr_ret_actions_from_priv } ; assign ie_to_x__h11449 = { 4'd0, new_priv__h11323 } ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 = interrupt_pending_cur_priv == _theResult____h15189 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 = interrupt_pending_cur_priv == _theResult____h15401 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 = interrupt_pending_cur_priv == _theResult____h15613 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 = interrupt_pending_cur_priv == _theResult____h15825 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 = interrupt_pending_cur_priv == _theResult____h16037 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 = interrupt_pending_cur_priv == _theResult____h16249 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 = interrupt_pending_cur_priv == _theResult____h16461 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 = interrupt_pending_cur_priv == _theResult____h16673 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 = interrupt_pending_cur_priv < _theResult____h15189 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 = interrupt_pending_cur_priv < _theResult____h15401 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 = interrupt_pending_cur_priv < _theResult____h15613 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 = interrupt_pending_cur_priv < _theResult____h15825 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 = interrupt_pending_cur_priv < _theResult____h16037 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 = interrupt_pending_cur_priv < _theResult____h16249 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 = interrupt_pending_cur_priv < _theResult____h16461 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 = interrupt_pending_cur_priv < _theResult____h16673 ; assign mask__h11532 = 64'd1 << ie_to_x__h11449 ; assign mask__h11549 = 64'd1 << pie_to_x__h11450 ; assign mask__h13614 = 64'd1 << pie_from_x__h13578 ; assign mask__h13631 = 64'd1 << ie_from_x__h13577 ; assign mav_csr_write_csr_addr_ULE_0x33F___d739 = mav_csr_write_csr_addr <= 12'h33F ; assign mav_csr_write_csr_addr_ULE_0xB1F___d735 = mav_csr_write_csr_addr <= 12'hB1F ; assign mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 = (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr != 12'h001 && mav_csr_write_csr_addr != 12'h002 && mav_csr_write_csr_addr != 12'h003 && mav_csr_write_csr_addr != 12'h100 && mav_csr_write_csr_addr != 12'h102 && mav_csr_write_csr_addr != 12'h103 && mav_csr_write_csr_addr != 12'h104 && mav_csr_write_csr_addr != 12'h105 && mav_csr_write_csr_addr != 12'h106 && mav_csr_write_csr_addr != 12'h140 && mav_csr_write_csr_addr != 12'h141 && mav_csr_write_csr_addr != 12'h142 && mav_csr_write_csr_addr != 12'h143 && mav_csr_write_csr_addr != 12'h144 && mav_csr_write_csr_addr != 12'h180 && mav_csr_write_csr_addr != 12'h302 && mav_csr_write_csr_addr != 12'h303 && mav_csr_write_csr_addr != 12'hF11 && mav_csr_write_csr_addr != 12'hF12 && mav_csr_write_csr_addr != 12'hF13 && mav_csr_write_csr_addr != 12'hF14 && mav_csr_write_csr_addr != 12'h300 && mav_csr_write_csr_addr != 12'h301 && mav_csr_write_csr_addr != 12'h304 && mav_csr_write_csr_addr != 12'h305 && mav_csr_write_csr_addr != 12'h306 && mav_csr_write_csr_addr != 12'h340 && mav_csr_write_csr_addr != 12'h341 && mav_csr_write_csr_addr != 12'h342 && mav_csr_write_csr_addr != 12'h343 && mav_csr_write_csr_addr != 12'h344 && mav_csr_write_csr_addr != 12'hB00 && mav_csr_write_csr_addr != 12'hB02 && mav_csr_write_csr_addr != 12'h7A0 && mav_csr_write_csr_addr != 12'h7A1 && mav_csr_write_csr_addr != 12'h7A2 && mav_csr_write_csr_addr != 12'h7A3 ; assign mav_csr_write_csr_addr_ULT_0x323___d738 = mav_csr_write_csr_addr < 12'h323 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h001 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h002 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h100 || mav_csr_write_csr_addr == 12'h300) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h104 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h105 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h140 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h141 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h142 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h143 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h144 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h180 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h302 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h303 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h304 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h305 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h306 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h340 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h341 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h342 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h343 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h344 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'hB02 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A0 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A1 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A2 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A3 ; assign mav_csr_write_csr_addr_ULT_0xB03___d734 = mav_csr_write_csr_addr < 12'hB03 ; assign new_priv__h11323 = csr_trap_actions_nmi ? 2'b11 : ((csr_trap_actions_from_priv == 2'b11) ? csr_trap_actions_from_priv : _theResult___fst__h11461) ; assign pie_from_x__h13578 = { 4'd1, csr_ret_actions_from_priv } ; assign pie_to_x__h11450 = { 4'd1, new_priv__h11323 } ; assign result__h9129 = { 4'd0, mav_csr_write_word[59:0] } ; assign sd__h11371 = IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13] == 2'h3 ; assign sd__h13499 = IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13] == 2'h3 ; assign sd__h7689 = mav_csr_write_word[14:13] == 2'h3 ; assign sd__h9711 = ma_update_mstatus_fs_fs == 2'h3 ; assign to_y__h13793 = { 1'b0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[8] } ; assign v__h11328 = { sd__h11371, 40'd5120, fixed_up_val_23__h11372 } ; assign v__h5882 = { 59'd0, mav_csr_write_word[4:0] } ; assign v__h6026 = { 56'd0, mav_csr_write_word[7:0] } ; assign v__h6140 = { sd__h7689, 43'd8192, mav_csr_write_word[19:18], 3'd0, mav_csr_write_word[14:13], 4'd0, mav_csr_write_word[8], 2'd0, mav_csr_write_word[5], 3'd0, mav_csr_write_word[1], 1'd0 } ; assign v__h7518 = { 48'd0, mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign v__h7554 = { 52'd0, mav_csr_write_word[11:0] } ; assign v__h8224 = { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; assign v__h8286 = { 61'd0, mav_csr_write_word[2:0] } ; assign v__h8442 = { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; assign val__h11533 = 64'd0 << ie_to_x__h11449 ; assign val__h11550 = { 63'd0, b__h11548 } << pie_to_x__h11450 ; assign val__h13632 = { 63'd0, b__h13630 } << ie_from_x__h13577 ; assign vector_offset__h12513 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; assign wordxl1__h7649 = { sd__h7689, 40'd5120, fixed_up_val_23__h7690 } ; assign x__h10300 = csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 ? exc_pc___1__h12586 : exc_pc__h12512 ; assign x__h11531 = x__h11561 | val__h11550 ; assign x__h11544 = x__h11531 & y__h11545 ; assign x__h11561 = csr_mstatus_rg_mstatus & y__h11562 ; assign x__h13437 = (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ? v__h11328 : y_avValue_fst__h12486 ; assign x__h13438 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, 59'd0, exc_code__h13279 } ; assign x__h13613 = x__h13643 | val__h13632 ; assign x__h13626 = x__h13613 & y__h13627 ; assign x__h13643 = csr_mstatus_rg_mstatus & y__h13644 ; assign y__h11545 = ~mask__h11532 ; assign y__h11562 = ~mask__h11549 ; assign y__h13627 = ~mask__h13614 ; assign y__h13644 = ~mask__h13631 ; assign y_avValue_fst__h12469 = { sd__h11371, 43'd8192, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[19:18], 3'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], 4'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[8], 2'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[5], 3'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[1], 1'd0 } ; assign y_avValue_fst__h12486 = (new_priv__h11323 == 2'b01) ? y_avValue_fst__h12469 : v__h11328 ; assign y_avValue_snd_snd__h12559 = { CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1, 2'd0 } ; always@(mav_csr_write_csr_addr or v__h5882 or v__h8286 or v__h6026 or v__h6140 or csr_mie$fav_sie_write or v__h8224 or mav_csr_write_word or v__h8442 or csr_mip$fav_sip_write or wordxl1__h7649 or v__h7518 or v__h7554 or csr_mie$fav_write or csr_mip$fav_write or result__h9129) begin case (mav_csr_write_csr_addr) 12'h001: y_avValue_fst__h9500 = v__h5882; 12'h002, 12'h306: y_avValue_fst__h9500 = v__h8286; 12'h003: y_avValue_fst__h9500 = v__h6026; 12'h100: y_avValue_fst__h9500 = v__h6140; 12'h102, 12'h103, 12'h106, 12'h301, 12'h7A0, 12'hF11, 12'hF12, 12'hF13, 12'hF14: y_avValue_fst__h9500 = 64'd0; 12'h104: y_avValue_fst__h9500 = csr_mie$fav_sie_write; 12'h105, 12'h305: y_avValue_fst__h9500 = v__h8224; 12'h140, 12'h141, 12'h143, 12'h180, 12'h340, 12'h341, 12'h343, 12'h7A2, 12'h7A3, 12'hB00, 12'hB02: y_avValue_fst__h9500 = mav_csr_write_word; 12'h142, 12'h342: y_avValue_fst__h9500 = v__h8442; 12'h144: y_avValue_fst__h9500 = csr_mip$fav_sip_write; 12'h300: y_avValue_fst__h9500 = wordxl1__h7649; 12'h302: y_avValue_fst__h9500 = v__h7518; 12'h303: y_avValue_fst__h9500 = v__h7554; 12'h304: y_avValue_fst__h9500 = csr_mie$fav_write; 12'h344: y_avValue_fst__h9500 = csr_mip$fav_write; 12'h7A1: y_avValue_fst__h9500 = result__h9129; default: y_avValue_fst__h9500 = 64'd0; endcase end always@(new_priv__h11323 or rg_mtvec or rg_stvec) begin case (new_priv__h11323) 2'b01: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_stvec[62:1]; 2'b11: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; default: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; endcase end always@(new_priv__h11323 or rg_mtvec or rg_stvec) begin case (new_priv__h11323) 2'b01: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_stvec[0]; 2'b11: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; default: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = interrupt_pending_cur_priv == 2'b11 && csr_mstatus_rg_mstatus[3]; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = !csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = !csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = interrupt_pending_cur_priv != 2'b11 || !csr_mstatus_rg_mstatus[3]; endcase end always@(read_csr_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (read_csr_csr_addr) 12'h001: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'd0; 12'h104: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sscratch; 12'h141: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sepc; 12'h142: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_stval; 12'h144: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_satp; 12'h300: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'h800000000014112D; 12'h302: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mie$fv_read; 12'h305: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mscratch; 12'h341: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mepc; 12'h342: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mtval; 12'h344: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mip$fv_read; 12'h7A0: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tselect; 12'h7A1: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata1; 12'h7A2: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata2; 12'hB00, 12'hC00: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_minstret; default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata3; endcase end always@(mav_read_csr_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (mav_read_csr_csr_addr) 12'h001: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 59'd0, rg_fflags }; 12'h002: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 61'd0, rg_frm }; 12'h003: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'd0; 12'h104: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mie$fv_sie_read; 12'h105: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sscratch; 12'h141: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sepc; 12'h142: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_stval; 12'h144: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mip$fv_sip_read; 12'h180: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_satp; 12'h300: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mstatus_rg_mstatus; 12'h301: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'h800000000014112D; 12'h302: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 48'd0, rg_medeleg }; 12'h303: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 52'd0, rg_mideleg }; 12'h304: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mie$fv_read; 12'h305: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 61'd0, rg_mcounteren }; 12'h340: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mscratch; 12'h341: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mepc; 12'h342: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mtval; 12'h344: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mip$fv_read; 12'h7A0: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tselect; 12'h7A1: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata1; 12'h7A2: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata2; 12'hB00, 12'hC00: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mcycle; 12'hB02, 12'hC02: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_minstret; default: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata3; endcase end always@(read_csr_port2_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (read_csr_port2_csr_addr) 12'h001: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'd0; 12'h104: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sscratch; 12'h141: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sepc; 12'h142: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_stval; 12'h144: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_satp; 12'h300: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'h800000000014112D; 12'h302: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mie$fv_read; 12'h305: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mscratch; 12'h341: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mepc; 12'h342: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mtval; 12'h344: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mip$fv_read; 12'h7A0: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tselect; 12'h7A1: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata1; 12'h7A2: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata2; 12'hB00, 12'hC00: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_minstret; default: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata3; endcase end always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000; rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (cfg_verbosity$EN) cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; if (csr_mstatus_rg_mstatus$EN) csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY csr_mstatus_rg_mstatus$D_IN; if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; if (rg_minstret$EN) rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; end if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; if (rg_dscratch0$EN) rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; if (rg_dscratch1$EN) rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; if (rg_mcounteren$EN) rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; if (rg_nmi_vector$EN) rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; end `ifdef BSV_NO_INITIAL_BLOCKS `else initial begin cfg_verbosity = 4'hA; csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; rg_dcsr = 32'hAAAAAAAA; rg_dpc = 64'hAAAAAAAAAAAAAAAA; rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; rg_fflags = 5'h0A; rg_frm = 3'h2; rg_mcause = 5'h0A; rg_mcounteren = 3'h2; rg_mcycle = 64'hAAAAAAAAAAAAAAAA; rg_medeleg = 16'hAAAA; rg_mepc = 64'hAAAAAAAAAAAAAAAA; rg_mideleg = 12'hAAA; rg_minstret = 64'hAAAAAAAAAAAAAAAA; rg_mscratch = 64'hAAAAAAAAAAAAAAAA; rg_mtval = 64'hAAAAAAAAAAAAAAAA; rg_mtvec = 63'h2AAAAAAAAAAAAAAA; rg_nmi = 1'h0; rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; rg_satp = 64'hAAAAAAAAAAAAAAAA; rg_scause = 5'h0A; rg_sepc = 64'hAAAAAAAAAAAAAAAA; rg_sscratch = 64'hAAAAAAAAAAAAAAAA; rg_state = 1'h0; rg_stval = 64'hAAAAAAAAAAAAAAAA; rg_stvec = 63'h2AAAAAAAAAAAAAAA; rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; rg_tselect = 64'hAAAAAAAAAAAAAAAA; end `endif always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sstatus = 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); if (RST_N != `BSV_RESET_VALUE) if (EN_mav_csr_write && (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", rg_mcycle, mav_csr_write_csr_addr, mav_csr_write_word); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" priv %0d: ", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" edeleg: 0x%0h", 16'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ideleg: 0x%0h", 12'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd10 && rg_scause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd11 && rg_scause[3:0] != 4'd12 && rg_scause[3:0] != 4'd13 && rg_scause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" status: 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" epc: 0x%0h", rg_sepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tval: 0x%0h", rg_stval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" priv %0d: ", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" edeleg: 0x%0h", rg_medeleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ideleg: 0x%0h", rg_mideleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd10 && rg_mcause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd11 && rg_mcause[3:0] != 4'd12 && rg_mcause[3:0] != 4'd13 && rg_mcause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" status: 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" epc: 0x%0h", rg_mepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tval: 0x%0h", rg_mtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" Return: new pc 0x%0h ", x__h10300); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new mstatus:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write("MStatus{", "sd:%0d", x__h13437[14:13] == 2'h3 || x__h13437[16:15] == 2'h3); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" sxl:%0d uxl:%0d", x__h13437[35:34], x__h13437[33:32]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tsr:%0d", x__h13437[22]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tw:%0d", x__h13437[21]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvm:%0d", x__h13437[20]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mxr:%0d", x__h13437[19]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" sum:%0d", x__h13437[18]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mprv:%0d", x__h13437[17]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" xs:%0d", x__h13437[16:15]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" fs:%0d", x__h13437[14:13]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mpp:%0d", x__h13437[12:11]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" spp:%0d", x__h13437[8]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" pies:%0d_%0d%0d", x__h13437[7], x__h13437[5], x__h13437[4]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ies:%0d_%0d%0d", x__h13437[3], x__h13437[1], x__h13437[0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write("}"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new xcause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402) $write("unknown interrupt Exc_Code %d", exc_code__h13279); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453) $write("unknown trap Exc_Code %d", exc_code__h13279); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new priv %0d", new_priv__h11323); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", rg_mcycle, m_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", rg_mcycle, s_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: timer_interrupt_req: %x", rg_mcycle, timer_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: software_interrupt_req: %x", rg_mcycle, software_interrupt_req_set_not_clear); end endmodule
module mkCSR_RegFile(CLK, RST_N, EN_server_reset_request_put, RDY_server_reset_request_put, EN_server_reset_response_get, RDY_server_reset_response_get, read_csr_csr_addr, read_csr, read_csr_port2_csr_addr, read_csr_port2, mav_read_csr_csr_addr, EN_mav_read_csr, mav_read_csr, mav_csr_write_csr_addr, mav_csr_write_word, EN_mav_csr_write, mav_csr_write, read_frm, ma_update_fcsr_fflags_flags, EN_ma_update_fcsr_fflags, ma_update_mstatus_fs_fs, EN_ma_update_mstatus_fs, read_misa, read_mstatus, read_sstatus, read_ustatus, read_satp, csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_nmi, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval, EN_csr_trap_actions, csr_trap_actions, RDY_csr_trap_actions, csr_ret_actions_from_priv, EN_csr_ret_actions, csr_ret_actions, RDY_csr_ret_actions, read_csr_minstret, EN_csr_minstret_incr, read_csr_mcycle, read_csr_mtime, access_permitted_1_priv, access_permitted_1_csr_addr, access_permitted_1_read_not_write, access_permitted_1, access_permitted_2_priv, access_permitted_2_csr_addr, access_permitted_2_read_not_write, access_permitted_2, csr_counter_read_fault_priv, csr_counter_read_fault_csr_addr, csr_counter_read_fault, csr_mip_read, m_external_interrupt_req_set_not_clear, s_external_interrupt_req_set_not_clear, timer_interrupt_req_set_not_clear, software_interrupt_req_set_not_clear, interrupt_pending_cur_priv, interrupt_pending, wfi_resume, nmi_req_set_not_clear, nmi_pending, EN_debug, RDY_debug);
input CLK; input RST_N; input EN_server_reset_request_put; output RDY_server_reset_request_put; input EN_server_reset_response_get; output RDY_server_reset_response_get; input [11 : 0] read_csr_csr_addr; output [64 : 0] read_csr; input [11 : 0] read_csr_port2_csr_addr; output [64 : 0] read_csr_port2; input [11 : 0] mav_read_csr_csr_addr; input EN_mav_read_csr; output [64 : 0] mav_read_csr; input [11 : 0] mav_csr_write_csr_addr; input [63 : 0] mav_csr_write_word; input EN_mav_csr_write; output [63 : 0] mav_csr_write; output [2 : 0] read_frm; input [4 : 0] ma_update_fcsr_fflags_flags; input EN_ma_update_fcsr_fflags; input [1 : 0] ma_update_mstatus_fs_fs; input EN_ma_update_mstatus_fs; output [27 : 0] read_misa; output [63 : 0] read_mstatus; output [63 : 0] read_sstatus; output [63 : 0] read_ustatus; output [63 : 0] read_satp; input [1 : 0] csr_trap_actions_from_priv; input [63 : 0] csr_trap_actions_pc; input csr_trap_actions_nmi; input csr_trap_actions_interrupt; input [3 : 0] csr_trap_actions_exc_code; input [63 : 0] csr_trap_actions_xtval; input EN_csr_trap_actions; output [193 : 0] csr_trap_actions; output RDY_csr_trap_actions; input [1 : 0] csr_ret_actions_from_priv; input EN_csr_ret_actions; output [129 : 0] csr_ret_actions; output RDY_csr_ret_actions; output [63 : 0] read_csr_minstret; input EN_csr_minstret_incr; output [63 : 0] read_csr_mcycle; output [63 : 0] read_csr_mtime; input [1 : 0] access_permitted_1_priv; input [11 : 0] access_permitted_1_csr_addr; input access_permitted_1_read_not_write; output access_permitted_1; input [1 : 0] access_permitted_2_priv; input [11 : 0] access_permitted_2_csr_addr; input access_permitted_2_read_not_write; output access_permitted_2; input [1 : 0] csr_counter_read_fault_priv; input [11 : 0] csr_counter_read_fault_csr_addr; output csr_counter_read_fault; output [63 : 0] csr_mip_read; input m_external_interrupt_req_set_not_clear; input s_external_interrupt_req_set_not_clear; input timer_interrupt_req_set_not_clear; input software_interrupt_req_set_not_clear; input [1 : 0] interrupt_pending_cur_priv; output [4 : 0] interrupt_pending; output wfi_resume; input nmi_req_set_not_clear; output nmi_pending; input EN_debug; output RDY_debug; wire [193 : 0] csr_trap_actions; wire [129 : 0] csr_ret_actions; wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; wire [63 : 0] csr_mip_read, mav_csr_write, read_csr_mcycle, read_csr_minstret, read_csr_mtime, read_mstatus, read_satp, read_sstatus, read_ustatus; wire [27 : 0] read_misa; wire [4 : 0] interrupt_pending; wire [2 : 0] read_frm; wire RDY_csr_ret_actions, RDY_csr_trap_actions, RDY_debug, RDY_server_reset_request_put, RDY_server_reset_response_get, access_permitted_1, access_permitted_2, csr_counter_read_fault, nmi_pending, wfi_resume; reg [3 : 0] cfg_verbosity; wire [3 : 0] cfg_verbosity$D_IN; wire cfg_verbosity$EN; reg [63 : 0] csr_mstatus_rg_mstatus; reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; wire csr_mstatus_rg_mstatus$EN; reg [31 : 0] rg_dcsr; wire [31 : 0] rg_dcsr$D_IN; wire rg_dcsr$EN; reg [63 : 0] rg_dpc; wire [63 : 0] rg_dpc$D_IN; wire rg_dpc$EN; reg [63 : 0] rg_dscratch0; wire [63 : 0] rg_dscratch0$D_IN; wire rg_dscratch0$EN; reg [63 : 0] rg_dscratch1; wire [63 : 0] rg_dscratch1$D_IN; wire rg_dscratch1$EN; reg [4 : 0] rg_fflags; reg [4 : 0] rg_fflags$D_IN; wire rg_fflags$EN; reg [2 : 0] rg_frm; wire [2 : 0] rg_frm$D_IN; wire rg_frm$EN; reg [4 : 0] rg_mcause; reg [4 : 0] rg_mcause$D_IN; wire rg_mcause$EN; reg [2 : 0] rg_mcounteren; wire [2 : 0] rg_mcounteren$D_IN; wire rg_mcounteren$EN; reg [63 : 0] rg_mcycle; wire [63 : 0] rg_mcycle$D_IN; wire rg_mcycle$EN; reg [15 : 0] rg_medeleg; wire [15 : 0] rg_medeleg$D_IN; wire rg_medeleg$EN; reg [63 : 0] rg_mepc; wire [63 : 0] rg_mepc$D_IN; wire rg_mepc$EN; reg [11 : 0] rg_mideleg; wire [11 : 0] rg_mideleg$D_IN; wire rg_mideleg$EN; reg [63 : 0] rg_minstret; wire [63 : 0] rg_minstret$D_IN; wire rg_minstret$EN; reg [63 : 0] rg_mscratch; wire [63 : 0] rg_mscratch$D_IN; wire rg_mscratch$EN; reg [63 : 0] rg_mtval; wire [63 : 0] rg_mtval$D_IN; wire rg_mtval$EN; reg [62 : 0] rg_mtvec; wire [62 : 0] rg_mtvec$D_IN; wire rg_mtvec$EN; reg rg_nmi; wire rg_nmi$D_IN, rg_nmi$EN; reg [63 : 0] rg_nmi_vector; wire [63 : 0] rg_nmi_vector$D_IN; wire rg_nmi_vector$EN; reg [63 : 0] rg_satp; wire [63 : 0] rg_satp$D_IN; wire rg_satp$EN; reg [4 : 0] rg_scause; reg [4 : 0] rg_scause$D_IN; wire rg_scause$EN; reg [63 : 0] rg_sepc; wire [63 : 0] rg_sepc$D_IN; wire rg_sepc$EN; reg [63 : 0] rg_sscratch; wire [63 : 0] rg_sscratch$D_IN; wire rg_sscratch$EN; reg rg_state; wire rg_state$D_IN, rg_state$EN; reg [63 : 0] rg_stval; wire [63 : 0] rg_stval$D_IN; wire rg_stval$EN; reg [62 : 0] rg_stvec; wire [62 : 0] rg_stvec$D_IN; wire rg_stvec$EN; reg [63 : 0] rg_tdata1; wire [63 : 0] rg_tdata1$D_IN; wire rg_tdata1$EN; reg [63 : 0] rg_tdata2; wire [63 : 0] rg_tdata2$D_IN; wire rg_tdata2$EN; reg [63 : 0] rg_tdata3; wire [63 : 0] rg_tdata3$D_IN; wire rg_tdata3$EN; reg [63 : 0] rg_tselect; wire [63 : 0] rg_tselect$D_IN; wire rg_tselect$EN; wire [63 : 0] csr_mie$fav_sie_write, csr_mie$fav_sie_write_wordxl, csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read, csr_mie$fv_sie_read; wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; wire [63 : 0] csr_mip$fav_sip_write, csr_mip$fav_sip_write_wordxl, csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read, csr_mip$fv_sip_read; wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; wire csr_mip$EN_fav_sip_write, csr_mip$EN_fav_write, csr_mip$EN_reset, csr_mip$m_external_interrupt_req_req, csr_mip$s_external_interrupt_req_req, csr_mip$software_interrupt_req_req, csr_mip$timer_interrupt_req_req; wire f_reset_rsps$CLR, f_reset_rsps$DEQ, f_reset_rsps$EMPTY_N, f_reset_rsps$ENQ, f_reset_rsps$FULL_N; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_mtvec_reset_value, soc_map$m_nmivec_reset_value; wire CAN_FIRE_RL_rl_mcycle_incr, CAN_FIRE_RL_rl_reset_start, CAN_FIRE_RL_rl_upd_minstret_csrrx, CAN_FIRE_RL_rl_upd_minstret_incr, CAN_FIRE_csr_minstret_incr, CAN_FIRE_csr_ret_actions, CAN_FIRE_csr_trap_actions, CAN_FIRE_debug, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_ma_update_fcsr_fflags, CAN_FIRE_ma_update_mstatus_fs, CAN_FIRE_mav_csr_write, CAN_FIRE_mav_read_csr, CAN_FIRE_nmi_req, CAN_FIRE_s_external_interrupt_req, CAN_FIRE_server_reset_request_put, CAN_FIRE_server_reset_response_get, CAN_FIRE_software_interrupt_req, CAN_FIRE_timer_interrupt_req, WILL_FIRE_RL_rl_mcycle_incr, WILL_FIRE_RL_rl_reset_start, WILL_FIRE_RL_rl_upd_minstret_csrrx, WILL_FIRE_RL_rl_upd_minstret_incr, WILL_FIRE_csr_minstret_incr, WILL_FIRE_csr_ret_actions, WILL_FIRE_csr_trap_actions, WILL_FIRE_debug, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_ma_update_fcsr_fflags, WILL_FIRE_ma_update_mstatus_fs, WILL_FIRE_mav_csr_write, WILL_FIRE_mav_read_csr, WILL_FIRE_nmi_req, WILL_FIRE_s_external_interrupt_req, WILL_FIRE_server_reset_request_put, WILL_FIRE_server_reset_response_get, WILL_FIRE_software_interrupt_req, WILL_FIRE_timer_interrupt_req; wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, MUX_csr_mstatus_rg_mstatus$write_1__VAL_5, MUX_rg_minstret$write_1__VAL_1, MUX_rg_minstret$write_1__VAL_2; wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; wire [2 : 0] MUX_rg_frm$write_1__VAL_1; wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, MUX_rg_fflags$write_1__SEL_2, MUX_rg_frm$write_1__SEL_1, MUX_rg_mcause$write_1__SEL_2, MUX_rg_mcause$write_1__SEL_3, MUX_rg_mcounteren$write_1__SEL_1, MUX_rg_medeleg$write_1__SEL_1, MUX_rg_mideleg$write_1__SEL_1, MUX_rg_mtvec$write_1__SEL_1, MUX_rg_satp$write_1__SEL_1, MUX_rg_scause$write_1__SEL_2, MUX_rg_scause$write_1__SEL_3, MUX_rg_sepc$write_1__SEL_1, MUX_rg_state$write_1__SEL_2, MUX_rg_stval$write_1__SEL_1, MUX_rg_stvec$write_1__SEL_1, MUX_rg_tdata1$write_1__SEL_1, MUX_rw_minstret$wset_1__SEL_1; reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731, IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291, IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511, y_avValue_fst__h9500; reg [61 : 0] CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1; reg CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742, IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845; wire [63 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477, _theResult___fst__h13593, _theResult___fst__h13794, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267, exc_pc___1__h12586, exc_pc__h12512, mask__h11532, mask__h11549, mask__h13614, mask__h13631, result__h9129, v__h11328, v__h5882, v__h6026, v__h6140, v__h7518, v__h7554, v__h8224, v__h8286, v__h8442, val__h11533, val__h11550, val__h13632, vector_offset__h12513, wordxl1__h7649, x__h10300, x__h11531, x__h11544, x__h11561, x__h13437, x__h13438, x__h13613, x__h13626, x__h13643, y__h11545, y__h11562, y__h13627, y__h13644, y_avValue_fst__h12469, y_avValue_fst__h12486, y_avValue_snd_snd__h12559; wire [22 : 0] fixed_up_val_23__h11372, fixed_up_val_23__h13500, fixed_up_val_23__h6191, fixed_up_val_23__h7690, fixed_up_val_23__h9712; wire [5 : 0] ie_from_x__h13577, ie_to_x__h11449, pie_from_x__h13578, pie_to_x__h11450; wire [3 : 0] IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928, exc_code__h13279; wire [1 : 0] IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, _theResult____h15189, _theResult____h15401, _theResult____h15613, _theResult____h15825, _theResult____h16037, _theResult____h16249, _theResult____h16461, _theResult____h16673, _theResult____h16885, _theResult___fst__h11461, new_priv__h11323, to_y__h13793; wire NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598, NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701, NOT_cfg_verbosity_read__42_ULE_1_43___d944, NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875, NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902, NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883, NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856, NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892, NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865, NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901, NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874, NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402, b__h11548, b__h13630, csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821, csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745, csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811, csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788, csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755, csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799, csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766, csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810, csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777, csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301, csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453, deleg_bit___1__h11470, deleg_bit___1__h11485, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807, interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806, interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817, mav_csr_write_csr_addr_ULE_0x33F___d739, mav_csr_write_csr_addr_ULE_0xB1F___d735, mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940, mav_csr_write_csr_addr_ULT_0x323___d738, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859, mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861, mav_csr_write_csr_addr_ULT_0xB03___d734, sd__h11371, sd__h13499, sd__h7689, sd__h9711; assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign CAN_FIRE_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; assign read_csr = { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || read_csr_csr_addr == 12'h001 || read_csr_csr_addr == 12'h002 || read_csr_csr_addr == 12'h003 || read_csr_csr_addr == 12'hC00 || read_csr_csr_addr == 12'hC02 || read_csr_csr_addr == 12'h100 || read_csr_csr_addr == 12'h102 || read_csr_csr_addr == 12'h103 || read_csr_csr_addr == 12'h104 || read_csr_csr_addr == 12'h105 || read_csr_csr_addr == 12'h106 || read_csr_csr_addr == 12'h140 || read_csr_csr_addr == 12'h141 || read_csr_csr_addr == 12'h142 || read_csr_csr_addr == 12'h143 || read_csr_csr_addr == 12'h144 || read_csr_csr_addr == 12'h180 || read_csr_csr_addr == 12'h302 || read_csr_csr_addr == 12'h303 || read_csr_csr_addr == 12'hF11 || read_csr_csr_addr == 12'hF12 || read_csr_csr_addr == 12'hF13 || read_csr_csr_addr == 12'hF14 || read_csr_csr_addr == 12'h300 || read_csr_csr_addr == 12'h301 || read_csr_csr_addr == 12'h304 || read_csr_csr_addr == 12'h305 || read_csr_csr_addr == 12'h306 || read_csr_csr_addr == 12'h340 || read_csr_csr_addr == 12'h341 || read_csr_csr_addr == 12'h342 || read_csr_csr_addr == 12'h343 || read_csr_csr_addr == 12'h344 || read_csr_csr_addr == 12'hB00 || read_csr_csr_addr == 12'hB02 || read_csr_csr_addr == 12'h7A0 || read_csr_csr_addr == 12'h7A1 || read_csr_csr_addr == 12'h7A2 || read_csr_csr_addr == 12'h7A3, (read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 } ; assign read_csr_port2 = { read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F || read_csr_port2_csr_addr == 12'h001 || read_csr_port2_csr_addr == 12'h002 || read_csr_port2_csr_addr == 12'h003 || read_csr_port2_csr_addr == 12'hC00 || read_csr_port2_csr_addr == 12'hC02 || read_csr_port2_csr_addr == 12'h100 || read_csr_port2_csr_addr == 12'h102 || read_csr_port2_csr_addr == 12'h103 || read_csr_port2_csr_addr == 12'h104 || read_csr_port2_csr_addr == 12'h105 || read_csr_port2_csr_addr == 12'h106 || read_csr_port2_csr_addr == 12'h140 || read_csr_port2_csr_addr == 12'h141 || read_csr_port2_csr_addr == 12'h142 || read_csr_port2_csr_addr == 12'h143 || read_csr_port2_csr_addr == 12'h144 || read_csr_port2_csr_addr == 12'h180 || read_csr_port2_csr_addr == 12'h302 || read_csr_port2_csr_addr == 12'h303 || read_csr_port2_csr_addr == 12'hF11 || read_csr_port2_csr_addr == 12'hF12 || read_csr_port2_csr_addr == 12'hF13 || read_csr_port2_csr_addr == 12'hF14 || read_csr_port2_csr_addr == 12'h300 || read_csr_port2_csr_addr == 12'h301 || read_csr_port2_csr_addr == 12'h304 || read_csr_port2_csr_addr == 12'h305 || read_csr_port2_csr_addr == 12'h306 || read_csr_port2_csr_addr == 12'h340 || read_csr_port2_csr_addr == 12'h341 || read_csr_port2_csr_addr == 12'h342 || read_csr_port2_csr_addr == 12'h343 || read_csr_port2_csr_addr == 12'h344 || read_csr_port2_csr_addr == 12'hB00 || read_csr_port2_csr_addr == 12'hB02 || read_csr_port2_csr_addr == 12'h7A0 || read_csr_port2_csr_addr == 12'h7A1 || read_csr_port2_csr_addr == 12'h7A2 || read_csr_port2_csr_addr == 12'h7A3, (read_csr_port2_csr_addr >= 12'hC03 && read_csr_port2_csr_addr <= 12'hC1F || read_csr_port2_csr_addr >= 12'hB03 && read_csr_port2_csr_addr <= 12'hB1F || read_csr_port2_csr_addr >= 12'h323 && read_csr_port2_csr_addr <= 12'h33F) ? 64'd0 : IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 } ; assign mav_read_csr = { mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F || mav_read_csr_csr_addr == 12'h001 || mav_read_csr_csr_addr == 12'h002 || mav_read_csr_csr_addr == 12'h003 || mav_read_csr_csr_addr == 12'hC00 || mav_read_csr_csr_addr == 12'hC02 || mav_read_csr_csr_addr == 12'h100 || mav_read_csr_csr_addr == 12'h102 || mav_read_csr_csr_addr == 12'h103 || mav_read_csr_csr_addr == 12'h104 || mav_read_csr_csr_addr == 12'h105 || mav_read_csr_csr_addr == 12'h106 || mav_read_csr_csr_addr == 12'h140 || mav_read_csr_csr_addr == 12'h141 || mav_read_csr_csr_addr == 12'h142 || mav_read_csr_csr_addr == 12'h143 || mav_read_csr_csr_addr == 12'h144 || mav_read_csr_csr_addr == 12'h180 || mav_read_csr_csr_addr == 12'h302 || mav_read_csr_csr_addr == 12'h303 || mav_read_csr_csr_addr == 12'hF11 || mav_read_csr_csr_addr == 12'hF12 || mav_read_csr_csr_addr == 12'hF13 || mav_read_csr_csr_addr == 12'hF14 || mav_read_csr_csr_addr == 12'h300 || mav_read_csr_csr_addr == 12'h301 || mav_read_csr_csr_addr == 12'h304 || mav_read_csr_csr_addr == 12'h305 || mav_read_csr_csr_addr == 12'h306 || mav_read_csr_csr_addr == 12'h340 || mav_read_csr_csr_addr == 12'h341 || mav_read_csr_csr_addr == 12'h342 || mav_read_csr_csr_addr == 12'h343 || mav_read_csr_csr_addr == 12'h344 || mav_read_csr_csr_addr == 12'hB00 || mav_read_csr_csr_addr == 12'hB02 || mav_read_csr_csr_addr == 12'h7A0 || mav_read_csr_csr_addr == 12'h7A1 || mav_read_csr_csr_addr == 12'h7A2 || mav_read_csr_csr_addr == 12'h7A3, (mav_read_csr_csr_addr >= 12'hC03 && mav_read_csr_csr_addr <= 12'hC1F || mav_read_csr_csr_addr >= 12'hB03 && mav_read_csr_csr_addr <= 12'hB1F || mav_read_csr_csr_addr >= 12'h323 && mav_read_csr_csr_addr <= 12'h33F) ? 64'd0 : IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 } ; assign CAN_FIRE_mav_read_csr = 1'd1 ; assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; assign mav_csr_write = (!mav_csr_write_csr_addr_ULT_0xB03___d734 && mav_csr_write_csr_addr_ULE_0xB1F___d735 || !mav_csr_write_csr_addr_ULT_0x323___d738 && mav_csr_write_csr_addr_ULE_0x33F___d739) ? 64'd0 : y_avValue_fst__h9500 ; assign CAN_FIRE_mav_csr_write = 1'd1 ; assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; assign read_frm = rg_frm ; assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; assign read_misa = 28'd135532845 ; assign read_mstatus = csr_mstatus_rg_mstatus ; assign read_sstatus = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] } ; assign read_ustatus = { 59'd0, csr_mstatus_rg_mstatus[4], 3'd0, csr_mstatus_rg_mstatus[0] } ; assign read_satp = rg_satp ; assign csr_trap_actions = { x__h10300, x__h13437, x__h13438, new_priv__h11323 } ; assign RDY_csr_trap_actions = 1'd1 ; assign CAN_FIRE_csr_trap_actions = 1'd1 ; assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; assign csr_ret_actions = (csr_ret_actions_from_priv == 2'b11) ? { rg_mepc, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[12:11], _theResult___fst__h13593 } : { rg_sepc, to_y__h13793, _theResult___fst__h13794 } ; assign RDY_csr_ret_actions = 1'd1 ; assign CAN_FIRE_csr_ret_actions = 1'd1 ; assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; assign read_csr_minstret = rg_minstret ; assign CAN_FIRE_csr_minstret_incr = 1'd1 ; assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; assign read_csr_mcycle = rg_mcycle ; assign read_csr_mtime = rg_mcycle ; assign access_permitted_1 = NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 && (access_permitted_1_read_not_write || access_permitted_1_csr_addr[11:10] != 2'b11) ; assign access_permitted_2 = NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 && (access_permitted_2_read_not_write || access_permitted_2_csr_addr[11:10] != 2'b11) ; assign csr_counter_read_fault = (csr_counter_read_fault_priv == 2'b01 || csr_counter_read_fault_priv == 2'b0) && (csr_counter_read_fault_csr_addr == 12'hC00 && !rg_mcounteren[0] || csr_counter_read_fault_csr_addr == 12'hC01 && !rg_mcounteren[1] || csr_counter_read_fault_csr_addr == 12'hC02 && !rg_mcounteren[2] || csr_counter_read_fault_csr_addr >= 12'hC03 && csr_counter_read_fault_csr_addr <= 12'hC1F) ; assign csr_mip_read = csr_mip$fv_read ; assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; assign CAN_FIRE_timer_interrupt_req = 1'd1 ; assign WILL_FIRE_timer_interrupt_req = 1'd1 ; assign CAN_FIRE_software_interrupt_req = 1'd1 ; assign WILL_FIRE_software_interrupt_req = 1'd1 ; assign interrupt_pending = { csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 || csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 || csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 } ; assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; assign CAN_FIRE_nmi_req = 1'd1 ; assign WILL_FIRE_nmi_req = 1'd1 ; assign nmi_pending = rg_nmi ; assign RDY_debug = 1'd1 ; assign CAN_FIRE_debug = 1'd1 ; assign WILL_FIRE_debug = EN_debug ; mkCSR_MIE csr_mie(.CLK(CLK), .RST_N(RST_N), .fav_sie_write_misa(csr_mie$fav_sie_write_misa), .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), .fav_write_misa(csr_mie$fav_write_misa), .fav_write_wordxl(csr_mie$fav_write_wordxl), .EN_reset(csr_mie$EN_reset), .EN_fav_write(csr_mie$EN_fav_write), .EN_fav_sie_write(csr_mie$EN_fav_sie_write), .fv_read(csr_mie$fv_read), .fav_write(csr_mie$fav_write), .fv_sie_read(csr_mie$fv_sie_read), .fav_sie_write(csr_mie$fav_sie_write)); mkCSR_MIP csr_mip(.CLK(CLK), .RST_N(RST_N), .fav_sip_write_misa(csr_mip$fav_sip_write_misa), .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), .fav_write_misa(csr_mip$fav_write_misa), .fav_write_wordxl(csr_mip$fav_write_wordxl), .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), .software_interrupt_req_req(csr_mip$software_interrupt_req_req), .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), .EN_reset(csr_mip$EN_reset), .EN_fav_write(csr_mip$EN_fav_write), .EN_fav_sip_write(csr_mip$EN_fav_sip_write), .fv_read(csr_mip$fv_read), .fav_write(csr_mip$fav_write), .fv_sip_read(csr_mip$fv_sip_read), .fav_sip_write(csr_mip$fav_sip_write)); FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), .CLK(CLK), .ENQ(f_reset_rsps$ENQ), .DEQ(f_reset_rsps$DEQ), .CLR(f_reset_rsps$CLR), .FULL_N(f_reset_rsps$FULL_N), .EMPTY_N(f_reset_rsps$EMPTY_N)); mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_near_mem_io_addr_base(), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(), .m_plic_addr_base(), .m_plic_addr_size(), .m_plic_addr_lim(), .m_uart0_addr_base(), .m_uart0_addr_size(), .m_uart0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_mem0_controller_addr_base(), .m_mem0_controller_addr_size(), .m_mem0_controller_addr_lim(), .m_tcm_addr_base(), .m_tcm_addr_size(), .m_tcm_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); assign CAN_FIRE_RL_rl_reset_start = !rg_state ; assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; assign CAN_FIRE_RL_rl_upd_minstret_csrrx = MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; assign WILL_FIRE_RL_rl_upd_minstret_csrrx = CAN_FIRE_RL_rl_upd_minstret_csrrx ; assign CAN_FIRE_RL_rl_upd_minstret_incr = !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; assign WILL_FIRE_RL_rl_upd_minstret_incr = CAN_FIRE_RL_rl_upd_minstret_incr ; assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 ; assign MUX_rg_fflags$write_1__SEL_2 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ; assign MUX_rg_frm$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 ; assign MUX_rg_mcause$write_1__SEL_2 = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ; assign MUX_rg_mcause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 ; assign MUX_rg_mcounteren$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 ; assign MUX_rg_medeleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 ; assign MUX_rg_mideleg$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ; assign MUX_rg_mtvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 ; assign MUX_rg_satp$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ; assign MUX_rg_scause$write_1__SEL_2 = EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign MUX_rg_scause$write_1__SEL_3 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 ; assign MUX_rg_sepc$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ; assign MUX_rg_state$write_1__SEL_2 = CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; assign MUX_rg_stval$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ; assign MUX_rg_stvec$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ; assign MUX_rg_tdata1$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 ; assign MUX_rw_minstret$wset_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = { sd__h13499, 40'd5120, fixed_up_val_23__h13500 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = { sd__h9711, 40'd5120, fixed_up_val_23__h9712 } ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = { sd__h7689, 40'd5120, (mav_csr_write_csr_addr == 12'h100) ? fixed_up_val_23__h6191 : fixed_up_val_23__h7690 } ; assign MUX_rg_fflags$write_1__VAL_3 = rg_fflags | ma_update_fcsr_fflags_flags ; assign MUX_rg_frm$write_1__VAL_1 = (mav_csr_write_csr_addr == 12'h002) ? mav_csr_write_word[2:0] : mav_csr_write_word[7:5] ; assign MUX_rg_mcause$write_1__VAL_2 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, exc_code__h13279 } ; assign MUX_rg_mcause$write_1__VAL_3 = { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; assign MUX_rg_medeleg$write_1__VAL_1 = { mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign MUX_rg_minstret$write_1__VAL_1 = MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; assign MUX_rg_mtvec$write_1__VAL_1 = { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; assign MUX_rg_mtvec$write_1__VAL_2 = { soc_map$m_mtvec_reset_value[63:2], soc_map$m_mtvec_reset_value[0] } ; assign cfg_verbosity$D_IN = 4'h0 ; assign cfg_verbosity$EN = 1'b0 ; always@(WILL_FIRE_RL_rl_reset_start or EN_csr_ret_actions or MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or EN_csr_trap_actions or v__h11328 or EN_ma_update_mstatus_fs or MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) case (1'b1) WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000; EN_csr_ret_actions: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h11328; EN_ma_update_mstatus_fs: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; default: csr_mstatus_rg_mstatus$D_IN = 64'hAAAAAAAAAAAAAAAA; endcase assign csr_mstatus_rg_mstatus$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 || EN_csr_trap_actions || EN_ma_update_mstatus_fs || EN_csr_ret_actions || WILL_FIRE_RL_rl_reset_start ; assign rg_dcsr$D_IN = 32'h0 ; assign rg_dcsr$EN = 1'b0 ; assign rg_dpc$D_IN = 64'h0 ; assign rg_dpc$EN = 1'b0 ; assign rg_dscratch0$D_IN = 64'h0 ; assign rg_dscratch0$EN = 1'b0 ; assign rg_dscratch1$D_IN = 64'h0 ; assign rg_dscratch1$EN = 1'b0 ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_fflags$write_1__SEL_2 or mav_csr_write_word or EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; default: rg_fflags$D_IN = 5'b01010; endcase assign rg_fflags$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 || EN_ma_update_fcsr_fflags || WILL_FIRE_RL_rl_reset_start ; assign rg_frm$D_IN = MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; assign rg_frm$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 || WILL_FIRE_RL_rl_reset_start ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_mcause$write_1__SEL_2 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; MUX_rg_mcause$write_1__SEL_2: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_mcause$write_1__SEL_3: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_mcause$D_IN = 5'b01010; endcase assign rg_mcause$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 || WILL_FIRE_RL_rl_reset_start ; assign rg_mcounteren$D_IN = MUX_rg_mcounteren$write_1__SEL_1 ? mav_csr_write_word[2:0] : 3'd0 ; assign rg_mcounteren$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 || WILL_FIRE_RL_rl_reset_start ; assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; assign rg_mcycle$EN = 1'd1 ; assign rg_medeleg$D_IN = MUX_rg_medeleg$write_1__SEL_1 ? MUX_rg_medeleg$write_1__VAL_1 : 16'd0 ; assign rg_medeleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 || WILL_FIRE_RL_rl_reset_start ; assign rg_mepc$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_pc : mav_csr_write_word ; assign rg_mepc$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 ; assign rg_mideleg$D_IN = MUX_rg_mideleg$write_1__SEL_1 ? mav_csr_write_word[11:0] : 12'd0 ; assign rg_mideleg$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 || WILL_FIRE_RL_rl_reset_start ; assign rg_minstret$D_IN = WILL_FIRE_RL_rl_upd_minstret_csrrx ? MUX_rg_minstret$write_1__VAL_1 : MUX_rg_minstret$write_1__VAL_2 ; assign rg_minstret$EN = WILL_FIRE_RL_rl_upd_minstret_csrrx || WILL_FIRE_RL_rl_upd_minstret_incr ; assign rg_mscratch$D_IN = mav_csr_write_word ; assign rg_mscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ; assign rg_mtval$D_IN = MUX_rg_mcause$write_1__SEL_2 ? csr_trap_actions_xtval : mav_csr_write_word ; assign rg_mtval$EN = EN_csr_trap_actions && (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 ; assign rg_mtvec$D_IN = MUX_rg_mtvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_mtvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 || WILL_FIRE_RL_rl_reset_start ; assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; assign rg_nmi$EN = 1'b1 ; assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; assign rg_satp$D_IN = MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; assign rg_satp$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 || WILL_FIRE_RL_rl_reset_start ; always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_scause$write_1__SEL_2 or MUX_rg_mcause$write_1__VAL_2 or MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; MUX_rg_scause$write_1__SEL_2: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; MUX_rg_scause$write_1__SEL_3: rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; default: rg_scause$D_IN = 5'b01010; endcase assign rg_scause$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 || WILL_FIRE_RL_rl_reset_start ; assign rg_sepc$D_IN = MUX_rg_sepc$write_1__SEL_1 ? mav_csr_write_word : csr_trap_actions_pc ; assign rg_sepc$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign rg_sscratch$D_IN = mav_csr_write_word ; assign rg_sscratch$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 ; assign rg_state$D_IN = !EN_server_reset_request_put ; assign rg_state$EN = EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; assign rg_stval$D_IN = MUX_rg_stval$write_1__SEL_1 ? mav_csr_write_word : csr_trap_actions_xtval ; assign rg_stval$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 || EN_csr_trap_actions && !csr_trap_actions_nmi && new_priv__h11323 == 2'b01 ; assign rg_stvec$D_IN = MUX_rg_stvec$write_1__SEL_1 ? MUX_rg_mtvec$write_1__VAL_1 : MUX_rg_mtvec$write_1__VAL_2 ; assign rg_stvec$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 || WILL_FIRE_RL_rl_reset_start ; assign rg_tdata1$D_IN = MUX_rg_tdata1$write_1__SEL_1 ? result__h9129 : 64'd0 ; assign rg_tdata1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 || WILL_FIRE_RL_rl_reset_start ; assign rg_tdata2$D_IN = mav_csr_write_word ; assign rg_tdata2$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 ; assign rg_tdata3$D_IN = mav_csr_write_word ; assign rg_tdata3$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 ; assign rg_tselect$D_IN = 64'd0 ; assign rg_tselect$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 || WILL_FIRE_RL_rl_reset_start ; assign csr_mie$fav_sie_write_misa = 28'd135532845 ; assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; assign csr_mie$fav_write_misa = 28'd135532845 ; assign csr_mie$fav_write_wordxl = mav_csr_write_word ; assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mie$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 ; assign csr_mie$EN_fav_sie_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 ; assign csr_mip$fav_sip_write_misa = 28'd135532845 ; assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; assign csr_mip$fav_write_misa = 28'd135532845 ; assign csr_mip$fav_write_wordxl = mav_csr_write_word ; assign csr_mip$m_external_interrupt_req_req = m_external_interrupt_req_set_not_clear ; assign csr_mip$s_external_interrupt_req_req = s_external_interrupt_req_set_not_clear ; assign csr_mip$software_interrupt_req_req = software_interrupt_req_set_not_clear ; assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; assign csr_mip$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 ; assign csr_mip$EN_fav_sip_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 ; assign f_reset_rsps$ENQ = EN_server_reset_request_put ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275 = (new_priv__h11323 == 2'b11) ? { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:13], csr_trap_actions_from_priv, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[10:0] } : { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:9], csr_trap_actions_from_priv[0], csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[7:0] } ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865) ? 4'd9 : ((NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856) ? 4'd7 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 ? 4'd3 : 4'd11)) ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883) ? 4'd5 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 ? 4'd1 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923) ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892) ? 4'd8 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 ; assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 = (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 && NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910) ? 4'd4 : (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 ? 4'd0 : IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926) ; assign IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774 = (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? 2'b01 : csr_mstatus_rg_mstatus[12:11] ; assign IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477 = (csr_ret_actions_from_priv == 2'b11) ? _theResult___fst__h13593 : _theResult___fst__h13794 ; assign NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 = (access_permitted_1_csr_addr >= 12'hC03 && access_permitted_1_csr_addr <= 12'hC1F || access_permitted_1_csr_addr >= 12'hB03 && access_permitted_1_csr_addr <= 12'hB1F || access_permitted_1_csr_addr >= 12'h323 && access_permitted_1_csr_addr <= 12'h33F || access_permitted_1_csr_addr == 12'h001 || access_permitted_1_csr_addr == 12'h002 || access_permitted_1_csr_addr == 12'h003 || access_permitted_1_csr_addr == 12'hC00 || access_permitted_1_csr_addr == 12'hC02 || access_permitted_1_csr_addr == 12'h100 || access_permitted_1_csr_addr == 12'h102 || access_permitted_1_csr_addr == 12'h103 || access_permitted_1_csr_addr == 12'h104 || access_permitted_1_csr_addr == 12'h105 || access_permitted_1_csr_addr == 12'h106 || access_permitted_1_csr_addr == 12'h140 || access_permitted_1_csr_addr == 12'h141 || access_permitted_1_csr_addr == 12'h142 || access_permitted_1_csr_addr == 12'h143 || access_permitted_1_csr_addr == 12'h144 || access_permitted_1_csr_addr == 12'h180 || access_permitted_1_csr_addr == 12'h302 || access_permitted_1_csr_addr == 12'h303 || access_permitted_1_csr_addr == 12'hF11 || access_permitted_1_csr_addr == 12'hF12 || access_permitted_1_csr_addr == 12'hF13 || access_permitted_1_csr_addr == 12'hF14 || access_permitted_1_csr_addr == 12'h300 || access_permitted_1_csr_addr == 12'h301 || access_permitted_1_csr_addr == 12'h304 || access_permitted_1_csr_addr == 12'h305 || access_permitted_1_csr_addr == 12'h306 || access_permitted_1_csr_addr == 12'h340 || access_permitted_1_csr_addr == 12'h341 || access_permitted_1_csr_addr == 12'h342 || access_permitted_1_csr_addr == 12'h343 || access_permitted_1_csr_addr == 12'h344 || access_permitted_1_csr_addr == 12'hB00 || access_permitted_1_csr_addr == 12'hB02 || access_permitted_1_csr_addr == 12'h7A0 || access_permitted_1_csr_addr == 12'h7A1 || access_permitted_1_csr_addr == 12'h7A2 || access_permitted_1_csr_addr == 12'h7A3) && access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && (access_permitted_1_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 = (access_permitted_2_csr_addr >= 12'hC03 && access_permitted_2_csr_addr <= 12'hC1F || access_permitted_2_csr_addr >= 12'hB03 && access_permitted_2_csr_addr <= 12'hB1F || access_permitted_2_csr_addr >= 12'h323 && access_permitted_2_csr_addr <= 12'h33F || access_permitted_2_csr_addr == 12'h001 || access_permitted_2_csr_addr == 12'h002 || access_permitted_2_csr_addr == 12'h003 || access_permitted_2_csr_addr == 12'hC00 || access_permitted_2_csr_addr == 12'hC02 || access_permitted_2_csr_addr == 12'h100 || access_permitted_2_csr_addr == 12'h102 || access_permitted_2_csr_addr == 12'h103 || access_permitted_2_csr_addr == 12'h104 || access_permitted_2_csr_addr == 12'h105 || access_permitted_2_csr_addr == 12'h106 || access_permitted_2_csr_addr == 12'h140 || access_permitted_2_csr_addr == 12'h141 || access_permitted_2_csr_addr == 12'h142 || access_permitted_2_csr_addr == 12'h143 || access_permitted_2_csr_addr == 12'h144 || access_permitted_2_csr_addr == 12'h180 || access_permitted_2_csr_addr == 12'h302 || access_permitted_2_csr_addr == 12'h303 || access_permitted_2_csr_addr == 12'hF11 || access_permitted_2_csr_addr == 12'hF12 || access_permitted_2_csr_addr == 12'hF13 || access_permitted_2_csr_addr == 12'hF14 || access_permitted_2_csr_addr == 12'h300 || access_permitted_2_csr_addr == 12'h301 || access_permitted_2_csr_addr == 12'h304 || access_permitted_2_csr_addr == 12'h305 || access_permitted_2_csr_addr == 12'h306 || access_permitted_2_csr_addr == 12'h340 || access_permitted_2_csr_addr == 12'h341 || access_permitted_2_csr_addr == 12'h342 || access_permitted_2_csr_addr == 12'h343 || access_permitted_2_csr_addr == 12'h344 || access_permitted_2_csr_addr == 12'hB00 || access_permitted_2_csr_addr == 12'hB02 || access_permitted_2_csr_addr == 12'h7A0 || access_permitted_2_csr_addr == 12'h7A1 || access_permitted_2_csr_addr == 12'h7A2 || access_permitted_2_csr_addr == 12'h7A3) && access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && (access_permitted_2_csr_addr != 12'h180 || !csr_mstatus_rg_mstatus[20]) ; assign NOT_cfg_verbosity_read__42_ULE_1_43___d944 = cfg_verbosity > 4'd1 ; assign NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910 = !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 = !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 = NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 && NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 ; assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 = NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 && NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 ; assign NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 = !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 = !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 = !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 = !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 = !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 = !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 && (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 || IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; assign NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402 = !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 != 4'd0 && exc_code__h13279 != 4'd1 && exc_code__h13279 != 4'd2 && exc_code__h13279 != 4'd3 && exc_code__h13279 != 4'd4 && exc_code__h13279 != 4'd5 && exc_code__h13279 != 4'd6 && exc_code__h13279 != 4'd7 && exc_code__h13279 != 4'd8 && exc_code__h13279 != 4'd9 && exc_code__h13279 != 4'd10 && exc_code__h13279 != 4'd11 ; assign _theResult____h15189 = rg_mideleg[11] ? 2'b01 : 2'b11 ; assign _theResult____h15401 = rg_mideleg[3] ? 2'b01 : 2'b11 ; assign _theResult____h15613 = rg_mideleg[7] ? 2'b01 : 2'b11 ; assign _theResult____h15825 = rg_mideleg[9] ? 2'b01 : 2'b11 ; assign _theResult____h16037 = rg_mideleg[1] ? 2'b01 : 2'b11 ; assign _theResult____h16249 = rg_mideleg[5] ? 2'b01 : 2'b11 ; assign _theResult____h16461 = rg_mideleg[8] ? 2'b01 : 2'b11 ; assign _theResult____h16673 = rg_mideleg[0] ? 2'b01 : 2'b11 ; assign _theResult____h16885 = rg_mideleg[4] ? 2'b01 : 2'b11 ; assign _theResult___fst__h11461 = (csr_trap_actions_interrupt ? deleg_bit___1__h11470 : deleg_bit___1__h11485) ? 2'b01 : 2'b11 ; assign _theResult___fst__h13593 = { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:13], 2'd0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[10:0] } ; assign _theResult___fst__h13794 = { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:9], 1'd0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[7:0] } ; assign b__h11548 = csr_mstatus_rg_mstatus[ie_to_x__h11449] ; assign b__h13630 = csr_mstatus_rg_mstatus[pie_from_x__h13578] ; assign csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 = csr_mip$fv_read[0] && csr_mie$fv_read[0] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 = csr_mip$fv_read[11] && csr_mie$fv_read[11] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 = csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 || csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 || csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 || csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 || csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 || csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 || csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 ; assign csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 = csr_mip$fv_read[1] && csr_mie$fv_read[1] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 = csr_mip$fv_read[3] && csr_mie$fv_read[3] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832 = csr_mip$fv_read[4] && csr_mie$fv_read[4] && (interrupt_pending_cur_priv < _theResult____h16885 || interrupt_pending_cur_priv == _theResult____h16885 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 = csr_mip$fv_read[5] && csr_mie$fv_read[5] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 = csr_mip$fv_read[7] && csr_mie$fv_read[7] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 = csr_mip$fv_read[8] && csr_mie$fv_read[8] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 = csr_mip$fv_read[9] && csr_mie$fv_read[9] && (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 || interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 && IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470 = x__h13626 | mask__h13614 ; assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267 = x__h11544 | val__h11533 ; assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 = csr_trap_actions_interrupt && !csr_trap_actions_nmi && CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453 = (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 != 4'd0 && exc_code__h13279 != 4'd1 && exc_code__h13279 != 4'd2 && exc_code__h13279 != 4'd3 && exc_code__h13279 != 4'd4 && exc_code__h13279 != 4'd5 && exc_code__h13279 != 4'd6 && exc_code__h13279 != 4'd7 && exc_code__h13279 != 4'd8 && exc_code__h13279 != 4'd9 && exc_code__h13279 != 4'd11 && exc_code__h13279 != 4'd12 && exc_code__h13279 != 4'd13 && exc_code__h13279 != 4'd15 ; assign deleg_bit___1__h11470 = rg_mideleg[csr_trap_actions_exc_code] ; assign deleg_bit___1__h11485 = rg_medeleg[csr_trap_actions_exc_code] ; assign exc_code__h13279 = csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; assign exc_pc___1__h12586 = exc_pc__h12512 + vector_offset__h12513 ; assign exc_pc__h12512 = csr_trap_actions_nmi ? rg_nmi_vector : y_avValue_snd_snd__h12559 ; assign fixed_up_val_23__h11372 = { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[22:17], 2'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11] == 2'b10) ? 2'b01 : IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11], IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[10:5], 1'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[3:1], 1'd0 } ; assign fixed_up_val_23__h13500 = { IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[22:17], 2'd0, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13], (IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11] == 2'b10) ? 2'b01 : IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11], IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[10:5], 1'd0, IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[3:1], 1'd0 } ; assign fixed_up_val_23__h6191 = { csr_mstatus_rg_mstatus[22:20], mav_csr_write_word[19:18], csr_mstatus_rg_mstatus[17], 2'd0, mav_csr_write_word[14:13], IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, csr_mstatus_rg_mstatus[10:9], mav_csr_write_word[8], csr_mstatus_rg_mstatus[7:6], mav_csr_write_word[5], 1'd0, csr_mstatus_rg_mstatus[3:2], mav_csr_write_word[1], 1'd0 } ; assign fixed_up_val_23__h7690 = { mav_csr_write_word[22:17], 2'd0, mav_csr_write_word[14:13], (mav_csr_write_word[12:11] == 2'b10) ? 2'b01 : mav_csr_write_word[12:11], mav_csr_write_word[10:5], 1'd0, mav_csr_write_word[3:1], 1'd0 } ; assign fixed_up_val_23__h9712 = { csr_mstatus_rg_mstatus[22:17], 2'd0, ma_update_mstatus_fs_fs, IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, csr_mstatus_rg_mstatus[10:5], 1'd0, csr_mstatus_rg_mstatus[3:1], 1'd0 } ; assign ie_from_x__h13577 = { 4'd0, csr_ret_actions_from_priv } ; assign ie_to_x__h11449 = { 4'd0, new_priv__h11323 } ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 = interrupt_pending_cur_priv == _theResult____h15189 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 = interrupt_pending_cur_priv == _theResult____h15401 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 = interrupt_pending_cur_priv == _theResult____h15613 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 = interrupt_pending_cur_priv == _theResult____h15825 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 = interrupt_pending_cur_priv == _theResult____h16037 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 = interrupt_pending_cur_priv == _theResult____h16249 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 = interrupt_pending_cur_priv == _theResult____h16461 ; assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 = interrupt_pending_cur_priv == _theResult____h16673 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 = interrupt_pending_cur_priv < _theResult____h15189 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 = interrupt_pending_cur_priv < _theResult____h15401 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 = interrupt_pending_cur_priv < _theResult____h15613 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 = interrupt_pending_cur_priv < _theResult____h15825 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 = interrupt_pending_cur_priv < _theResult____h16037 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 = interrupt_pending_cur_priv < _theResult____h16249 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 = interrupt_pending_cur_priv < _theResult____h16461 ; assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 = interrupt_pending_cur_priv < _theResult____h16673 ; assign mask__h11532 = 64'd1 << ie_to_x__h11449 ; assign mask__h11549 = 64'd1 << pie_to_x__h11450 ; assign mask__h13614 = 64'd1 << pie_from_x__h13578 ; assign mask__h13631 = 64'd1 << ie_from_x__h13577 ; assign mav_csr_write_csr_addr_ULE_0x33F___d739 = mav_csr_write_csr_addr <= 12'h33F ; assign mav_csr_write_csr_addr_ULE_0xB1F___d735 = mav_csr_write_csr_addr <= 12'hB1F ; assign mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 = (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr != 12'h001 && mav_csr_write_csr_addr != 12'h002 && mav_csr_write_csr_addr != 12'h003 && mav_csr_write_csr_addr != 12'h100 && mav_csr_write_csr_addr != 12'h102 && mav_csr_write_csr_addr != 12'h103 && mav_csr_write_csr_addr != 12'h104 && mav_csr_write_csr_addr != 12'h105 && mav_csr_write_csr_addr != 12'h106 && mav_csr_write_csr_addr != 12'h140 && mav_csr_write_csr_addr != 12'h141 && mav_csr_write_csr_addr != 12'h142 && mav_csr_write_csr_addr != 12'h143 && mav_csr_write_csr_addr != 12'h144 && mav_csr_write_csr_addr != 12'h180 && mav_csr_write_csr_addr != 12'h302 && mav_csr_write_csr_addr != 12'h303 && mav_csr_write_csr_addr != 12'hF11 && mav_csr_write_csr_addr != 12'hF12 && mav_csr_write_csr_addr != 12'hF13 && mav_csr_write_csr_addr != 12'hF14 && mav_csr_write_csr_addr != 12'h300 && mav_csr_write_csr_addr != 12'h301 && mav_csr_write_csr_addr != 12'h304 && mav_csr_write_csr_addr != 12'h305 && mav_csr_write_csr_addr != 12'h306 && mav_csr_write_csr_addr != 12'h340 && mav_csr_write_csr_addr != 12'h341 && mav_csr_write_csr_addr != 12'h342 && mav_csr_write_csr_addr != 12'h343 && mav_csr_write_csr_addr != 12'h344 && mav_csr_write_csr_addr != 12'hB00 && mav_csr_write_csr_addr != 12'hB02 && mav_csr_write_csr_addr != 12'h7A0 && mav_csr_write_csr_addr != 12'h7A1 && mav_csr_write_csr_addr != 12'h7A2 && mav_csr_write_csr_addr != 12'h7A3 ; assign mav_csr_write_csr_addr_ULT_0x323___d738 = mav_csr_write_csr_addr < 12'h323 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h001 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h002 || mav_csr_write_csr_addr == 12'h003) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && (mav_csr_write_csr_addr == 12'h100 || mav_csr_write_csr_addr == 12'h300) ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h104 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h105 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h140 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h141 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h142 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h143 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h144 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h180 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h302 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h303 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h304 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h305 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h306 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h340 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h341 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h342 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h343 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h344 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'hB02 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A0 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A1 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A2 ; assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 = (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && (mav_csr_write_csr_addr_ULT_0x323___d738 || !mav_csr_write_csr_addr_ULE_0x33F___d739) && mav_csr_write_csr_addr == 12'h7A3 ; assign mav_csr_write_csr_addr_ULT_0xB03___d734 = mav_csr_write_csr_addr < 12'hB03 ; assign new_priv__h11323 = csr_trap_actions_nmi ? 2'b11 : ((csr_trap_actions_from_priv == 2'b11) ? csr_trap_actions_from_priv : _theResult___fst__h11461) ; assign pie_from_x__h13578 = { 4'd1, csr_ret_actions_from_priv } ; assign pie_to_x__h11450 = { 4'd1, new_priv__h11323 } ; assign result__h9129 = { 4'd0, mav_csr_write_word[59:0] } ; assign sd__h11371 = IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13] == 2'h3 ; assign sd__h13499 = IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13] == 2'h3 ; assign sd__h7689 = mav_csr_write_word[14:13] == 2'h3 ; assign sd__h9711 = ma_update_mstatus_fs_fs == 2'h3 ; assign to_y__h13793 = { 1'b0, csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[8] } ; assign v__h11328 = { sd__h11371, 40'd5120, fixed_up_val_23__h11372 } ; assign v__h5882 = { 59'd0, mav_csr_write_word[4:0] } ; assign v__h6026 = { 56'd0, mav_csr_write_word[7:0] } ; assign v__h6140 = { sd__h7689, 43'd8192, mav_csr_write_word[19:18], 3'd0, mav_csr_write_word[14:13], 4'd0, mav_csr_write_word[8], 2'd0, mav_csr_write_word[5], 3'd0, mav_csr_write_word[1], 1'd0 } ; assign v__h7518 = { 48'd0, mav_csr_write_word[15], 1'd0, mav_csr_write_word[13:12], 2'd0, mav_csr_write_word[9:0] } ; assign v__h7554 = { 52'd0, mav_csr_write_word[11:0] } ; assign v__h8224 = { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; assign v__h8286 = { 61'd0, mav_csr_write_word[2:0] } ; assign v__h8442 = { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; assign val__h11533 = 64'd0 << ie_to_x__h11449 ; assign val__h11550 = { 63'd0, b__h11548 } << pie_to_x__h11450 ; assign val__h13632 = { 63'd0, b__h13630 } << ie_from_x__h13577 ; assign vector_offset__h12513 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; assign wordxl1__h7649 = { sd__h7689, 40'd5120, fixed_up_val_23__h7690 } ; assign x__h10300 = csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 ? exc_pc___1__h12586 : exc_pc__h12512 ; assign x__h11531 = x__h11561 | val__h11550 ; assign x__h11544 = x__h11531 & y__h11545 ; assign x__h11561 = csr_mstatus_rg_mstatus & y__h11562 ; assign x__h13437 = (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ? v__h11328 : y_avValue_fst__h12486 ; assign x__h13438 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, 59'd0, exc_code__h13279 } ; assign x__h13613 = x__h13643 | val__h13632 ; assign x__h13626 = x__h13613 & y__h13627 ; assign x__h13643 = csr_mstatus_rg_mstatus & y__h13644 ; assign y__h11545 = ~mask__h11532 ; assign y__h11562 = ~mask__h11549 ; assign y__h13627 = ~mask__h13614 ; assign y__h13644 = ~mask__h13631 ; assign y_avValue_fst__h12469 = { sd__h11371, 43'd8192, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[19:18], 3'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], 4'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[8], 2'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[5], 3'd0, IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[1], 1'd0 } ; assign y_avValue_fst__h12486 = (new_priv__h11323 == 2'b01) ? y_avValue_fst__h12469 : v__h11328 ; assign y_avValue_snd_snd__h12559 = { CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1, 2'd0 } ; always@(mav_csr_write_csr_addr or v__h5882 or v__h8286 or v__h6026 or v__h6140 or csr_mie$fav_sie_write or v__h8224 or mav_csr_write_word or v__h8442 or csr_mip$fav_sip_write or wordxl1__h7649 or v__h7518 or v__h7554 or csr_mie$fav_write or csr_mip$fav_write or result__h9129) begin case (mav_csr_write_csr_addr) 12'h001: y_avValue_fst__h9500 = v__h5882; 12'h002, 12'h306: y_avValue_fst__h9500 = v__h8286; 12'h003: y_avValue_fst__h9500 = v__h6026; 12'h100: y_avValue_fst__h9500 = v__h6140; 12'h102, 12'h103, 12'h106, 12'h301, 12'h7A0, 12'hF11, 12'hF12, 12'hF13, 12'hF14: y_avValue_fst__h9500 = 64'd0; 12'h104: y_avValue_fst__h9500 = csr_mie$fav_sie_write; 12'h105, 12'h305: y_avValue_fst__h9500 = v__h8224; 12'h140, 12'h141, 12'h143, 12'h180, 12'h340, 12'h341, 12'h343, 12'h7A2, 12'h7A3, 12'hB00, 12'hB02: y_avValue_fst__h9500 = mav_csr_write_word; 12'h142, 12'h342: y_avValue_fst__h9500 = v__h8442; 12'h144: y_avValue_fst__h9500 = csr_mip$fav_sip_write; 12'h300: y_avValue_fst__h9500 = wordxl1__h7649; 12'h302: y_avValue_fst__h9500 = v__h7518; 12'h303: y_avValue_fst__h9500 = v__h7554; 12'h304: y_avValue_fst__h9500 = csr_mie$fav_write; 12'h344: y_avValue_fst__h9500 = csr_mip$fav_write; 12'h7A1: y_avValue_fst__h9500 = result__h9129; default: y_avValue_fst__h9500 = 64'd0; endcase end always@(new_priv__h11323 or rg_mtvec or rg_stvec) begin case (new_priv__h11323) 2'b01: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_stvec[62:1]; 2'b11: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; default: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = rg_mtvec[62:1]; endcase end always@(new_priv__h11323 or rg_mtvec or rg_stvec) begin case (new_priv__h11323) 2'b01: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_stvec[0]; 2'b11: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; default: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = rg_mtvec[0]; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = interrupt_pending_cur_priv == 2'b11 && csr_mstatus_rg_mstatus[3]; endcase end always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) begin case (interrupt_pending_cur_priv) 2'b0: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = !csr_mstatus_rg_mstatus[0]; 2'b01: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = !csr_mstatus_rg_mstatus[1]; default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = interrupt_pending_cur_priv != 2'b11 || !csr_mstatus_rg_mstatus[3]; endcase end always@(read_csr_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (read_csr_csr_addr) 12'h001: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'd0; 12'h104: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sscratch; 12'h141: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sepc; 12'h142: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_stval; 12'h144: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_satp; 12'h300: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'h800000000014112D; 12'h302: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mie$fv_read; 12'h305: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mscratch; 12'h341: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mepc; 12'h342: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mtval; 12'h344: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = csr_mip$fv_read; 12'h7A0: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tselect; 12'h7A1: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata1; 12'h7A2: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata2; 12'hB00, 12'hC00: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_minstret; default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_tdata3; endcase end always@(mav_read_csr_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (mav_read_csr_csr_addr) 12'h001: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 59'd0, rg_fflags }; 12'h002: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 61'd0, rg_frm }; 12'h003: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'd0; 12'h104: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mie$fv_sie_read; 12'h105: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sscratch; 12'h141: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sepc; 12'h142: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_stval; 12'h144: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mip$fv_sip_read; 12'h180: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_satp; 12'h300: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mstatus_rg_mstatus; 12'h301: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'h800000000014112D; 12'h302: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 48'd0, rg_medeleg }; 12'h303: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 52'd0, rg_mideleg }; 12'h304: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mie$fv_read; 12'h305: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { 61'd0, rg_mcounteren }; 12'h340: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mscratch; 12'h341: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mepc; 12'h342: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mtval; 12'h344: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = csr_mip$fv_read; 12'h7A0: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tselect; 12'h7A1: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata1; 12'h7A2: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata2; 12'hB00, 12'hC00: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mcycle; 12'hB02, 12'hC02: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_minstret; default: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_tdata3; endcase end always@(read_csr_port2_csr_addr or rg_tdata3 or rg_fflags or rg_frm or csr_mstatus_rg_mstatus or csr_mie$fv_sie_read or rg_stvec or rg_sscratch or rg_sepc or rg_scause or rg_stval or csr_mip$fv_sip_read or rg_satp or rg_medeleg or rg_mideleg or csr_mie$fv_read or rg_mtvec or rg_mcounteren or rg_mscratch or rg_mepc or rg_mcause or rg_mtval or csr_mip$fv_read or rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) begin case (read_csr_port2_csr_addr) 12'h001: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 59'd0, rg_fflags }; 12'h002: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 61'd0, rg_frm }; 12'h003: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 56'd0, rg_frm, rg_fflags }; 12'h100: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }; 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'd0; 12'h104: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mie$fv_sie_read; 12'h105: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_stvec[62:1], 1'b0, rg_stvec[0] }; 12'h140: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sscratch; 12'h141: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sepc; 12'h142: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_scause[4], 59'd0, rg_scause[3:0] }; 12'h143: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_stval; 12'h144: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mip$fv_sip_read; 12'h180: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_satp; 12'h300: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mstatus_rg_mstatus; 12'h301: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'h800000000014112D; 12'h302: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 48'd0, rg_medeleg }; 12'h303: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 52'd0, rg_mideleg }; 12'h304: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mie$fv_read; 12'h305: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; 12'h306: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { 61'd0, rg_mcounteren }; 12'h340: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mscratch; 12'h341: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mepc; 12'h342: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = { rg_mcause[4], 59'd0, rg_mcause[3:0] }; 12'h343: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mtval; 12'h344: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = csr_mip$fv_read; 12'h7A0: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tselect; 12'h7A1: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata1; 12'h7A2: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata2; 12'hB00, 12'hC00: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mcycle; 12'hB02, 12'hC02: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_minstret; default: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_tdata3; endcase end always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000; rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; end else begin if (cfg_verbosity$EN) cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; if (csr_mstatus_rg_mstatus$EN) csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY csr_mstatus_rg_mstatus$D_IN; if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; if (rg_minstret$EN) rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; end if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; if (rg_dscratch0$EN) rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; if (rg_dscratch1$EN) rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; if (rg_mcounteren$EN) rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; if (rg_nmi_vector$EN) rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; end `ifdef BSV_NO_INITIAL_BLOCKS `else initial begin cfg_verbosity = 4'hA; csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; rg_dcsr = 32'hAAAAAAAA; rg_dpc = 64'hAAAAAAAAAAAAAAAA; rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; rg_fflags = 5'h0A; rg_frm = 3'h2; rg_mcause = 5'h0A; rg_mcounteren = 3'h2; rg_mcycle = 64'hAAAAAAAAAAAAAAAA; rg_medeleg = 16'hAAAA; rg_mepc = 64'hAAAAAAAAAAAAAAAA; rg_mideleg = 12'hAAA; rg_minstret = 64'hAAAAAAAAAAAAAAAA; rg_mscratch = 64'hAAAAAAAAAAAAAAAA; rg_mtval = 64'hAAAAAAAAAAAAAAAA; rg_mtvec = 63'h2AAAAAAAAAAAAAAA; rg_nmi = 1'h0; rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; rg_satp = 64'hAAAAAAAAAAAAAAAA; rg_scause = 5'h0A; rg_sepc = 64'hAAAAAAAAAAAAAAAA; rg_sscratch = 64'hAAAAAAAAAAAAAAAA; rg_state = 1'h0; rg_stval = 64'hAAAAAAAAAAAAAAAA; rg_stvec = 63'h2AAAAAAAAAAAAAAA; rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; rg_tselect = 64'hAAAAAAAAAAAAAAAA; end `endif always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sstatus = 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); if (RST_N != `BSV_RESET_VALUE) if (EN_mav_csr_write && (mav_csr_write_csr_addr_ULT_0xB03___d734 || !mav_csr_write_csr_addr_ULE_0xB1F___d735) && mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", rg_mcycle, mav_csr_write_csr_addr, mav_csr_write_word); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", csr_trap_actions_from_priv, csr_trap_actions_pc, csr_trap_actions_interrupt, csr_trap_actions_exc_code, csr_trap_actions_xtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" priv %0d: ", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" edeleg: 0x%0h", 16'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ideleg: 0x%0h", 12'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd10 && rg_scause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_scause[4] && rg_scause[3:0] != 4'd0 && rg_scause[3:0] != 4'd1 && rg_scause[3:0] != 4'd2 && rg_scause[3:0] != 4'd3 && rg_scause[3:0] != 4'd4 && rg_scause[3:0] != 4'd5 && rg_scause[3:0] != 4'd6 && rg_scause[3:0] != 4'd7 && rg_scause[3:0] != 4'd8 && rg_scause[3:0] != 4'd9 && rg_scause[3:0] != 4'd11 && rg_scause[3:0] != 4'd12 && rg_scause[3:0] != 4'd13 && rg_scause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_scause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" status: 0x%0h", { csr_mstatus_rg_mstatus[63], 29'd0, csr_mstatus_rg_mstatus[33:32], 12'd0, csr_mstatus_rg_mstatus[19:18], 1'd0, csr_mstatus_rg_mstatus[16:13], 4'd0, csr_mstatus_rg_mstatus[8], 2'd0, csr_mstatus_rg_mstatus[5:4], 2'd0, csr_mstatus_rg_mstatus[1:0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" epc: 0x%0h", rg_sepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tval: 0x%0h", rg_stval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" priv %0d: ", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ip: 0x%0h", csr_mip$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ie: 0x%0h", csr_mie$fv_read); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" edeleg: 0x%0h", rg_medeleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ideleg: 0x%0h", rg_mideleg); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" cause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd10 && rg_mcause[3:0] != 4'd11) $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !rg_mcause[4] && rg_mcause[3:0] != 4'd0 && rg_mcause[3:0] != 4'd1 && rg_mcause[3:0] != 4'd2 && rg_mcause[3:0] != 4'd3 && rg_mcause[3:0] != 4'd4 && rg_mcause[3:0] != 4'd5 && rg_mcause[3:0] != 4'd6 && rg_mcause[3:0] != 4'd7 && rg_mcause[3:0] != 4'd8 && rg_mcause[3:0] != 4'd9 && rg_mcause[3:0] != 4'd11 && rg_mcause[3:0] != 4'd12 && rg_mcause[3:0] != 4'd13 && rg_mcause[3:0] != 4'd15) $write("unknown trap Exc_Code %d", rg_mcause[3:0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" status: 0x%0h", csr_mstatus_rg_mstatus); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" epc: 0x%0h", rg_mepc); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tval: 0x%0h", rg_mtval); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" Return: new pc 0x%0h ", x__h10300); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new mstatus:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write("MStatus{", "sd:%0d", x__h13437[14:13] == 2'h3 || x__h13437[16:15] == 2'h3); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" sxl:%0d uxl:%0d", x__h13437[35:34], x__h13437[33:32]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tsr:%0d", x__h13437[22]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tw:%0d", x__h13437[21]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" tvm:%0d", x__h13437[20]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mxr:%0d", x__h13437[19]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" sum:%0d", x__h13437[18]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mprv:%0d", x__h13437[17]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" xs:%0d", x__h13437[16:15]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" fs:%0d", x__h13437[14:13]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" mpp:%0d", x__h13437[12:11]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" spp:%0d", x__h13437[8]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" pies:%0d_%0d%0d", x__h13437[7], x__h13437[5], x__h13437[4]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" ies:%0d_%0d%0d", x__h13437[3], x__h13437[1], x__h13437[0]); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write("}"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new xcause:"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && exc_code__h13279 == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402) $write("unknown interrupt Exc_Code %d", exc_code__h13279); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && exc_code__h13279 == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453) $write("unknown trap Exc_Code %d", exc_code__h13279); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $write(" new priv %0d", new_priv__h11323); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display(""); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", rg_mcycle, m_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", rg_mcycle, s_external_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: timer_interrupt_req: %x", rg_mcycle, timer_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) $display("%0d: CSR_RegFile: software_interrupt_req: %x", rg_mcycle, software_interrupt_req_set_not_clear); end endmodule
0
2,568
data/full_repos/permissive/255270114/rtl/e203/perips/sirv_qspi_1cs_top.v
255,270,114
sirv_qspi_1cs_top.v
v
178
77
[]
[]
[]
[(28, 177)]
null
null
1: b"%Error: data/full_repos/permissive/255270114/rtl/e203/perips/sirv_qspi_1cs_top.v:114: Cannot find file containing module: 'sirv_qspi_1cs'\nsirv_qspi_1cs u_sirv_qspi_1cs(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/255270114/rtl/e203/perips,data/full_repos/permissive/255270114/sirv_qspi_1cs\n data/full_repos/permissive/255270114/rtl/e203/perips,data/full_repos/permissive/255270114/sirv_qspi_1cs.v\n data/full_repos/permissive/255270114/rtl/e203/perips,data/full_repos/permissive/255270114/sirv_qspi_1cs.sv\n sirv_qspi_1cs\n sirv_qspi_1cs.v\n sirv_qspi_1cs.sv\n obj_dir/sirv_qspi_1cs\n obj_dir/sirv_qspi_1cs.v\n obj_dir/sirv_qspi_1cs.sv\n%Error: Exiting due to 1 error(s)\n"
97,231
module
module sirv_qspi_1cs_top( input clk, input rst_n, input i_icb_cmd_valid, output i_icb_cmd_ready, input [32-1:0] i_icb_cmd_addr, input i_icb_cmd_read, input [32-1:0] i_icb_cmd_wdata, output i_icb_rsp_valid, input i_icb_rsp_ready, output [32-1:0] i_icb_rsp_rdata, output io_port_sck, input io_port_dq_0_i, output io_port_dq_0_o, output io_port_dq_0_oe, input io_port_dq_1_i, output io_port_dq_1_o, output io_port_dq_1_oe, input io_port_dq_2_i, output io_port_dq_2_o, output io_port_dq_2_oe, input io_port_dq_3_i, output io_port_dq_3_o, output io_port_dq_3_oe, output io_port_cs_0, output io_tl_i_0_0 ); wire io_tl_r_0_a_ready; assign i_icb_cmd_ready = io_tl_r_0_a_ready; wire io_tl_r_0_a_valid = i_icb_cmd_valid; wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0; wire [2:0] io_tl_r_0_a_bits_param = 3'b0; wire [2:0] io_tl_r_0_a_bits_size = 3'd2; wire [4:0] io_tl_r_0_a_bits_source = 5'b0; wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0]; wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111; wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata; wire io_tl_r_0_d_ready = i_icb_rsp_ready; wire [2:0] io_tl_r_0_d_bits_opcode; wire [1:0] io_tl_r_0_d_bits_param; wire [2:0] io_tl_r_0_d_bits_size; wire [4:0] io_tl_r_0_d_bits_source; wire io_tl_r_0_d_bits_sink; wire [1:0] io_tl_r_0_d_bits_addr_lo; wire [31:0] io_tl_r_0_d_bits_data; wire io_tl_r_0_d_bits_error; wire io_tl_r_0_d_valid; assign i_icb_rsp_valid = io_tl_r_0_d_valid; assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data; wire io_tl_r_0_b_ready = 1'b0; wire io_tl_r_0_b_valid; wire [2:0] io_tl_r_0_b_bits_opcode; wire [1:0] io_tl_r_0_b_bits_param; wire [2:0] io_tl_r_0_b_bits_size; wire [4:0] io_tl_r_0_b_bits_source; wire [28:0] io_tl_r_0_b_bits_address; wire [3:0] io_tl_r_0_b_bits_mask; wire [31:0] io_tl_r_0_b_bits_data; wire io_tl_r_0_c_ready; wire io_tl_r_0_c_valid = 1'b0; wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0; wire [2:0] io_tl_r_0_c_bits_param = 3'b0; wire [2:0] io_tl_r_0_c_bits_size = 3'd2; wire [4:0] io_tl_r_0_c_bits_source = 5'b0; wire [28:0] io_tl_r_0_c_bits_address = 29'b0; wire [31:0] io_tl_r_0_c_bits_data = 32'b0; wire io_tl_r_0_c_bits_error = 1'b0; wire io_tl_r_0_e_ready; wire io_tl_r_0_e_valid = 1'b0; wire io_tl_r_0_e_bits_sink = 1'b0; sirv_qspi_1cs u_sirv_qspi_1cs( .clock (clk ), .reset (~rst_n ), .io_tl_r_0_a_ready (io_tl_r_0_a_ready ), .io_tl_r_0_a_valid (io_tl_r_0_a_valid ), .io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ), .io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ), .io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ), .io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ), .io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ), .io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ), .io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ), .io_tl_r_0_b_ready (io_tl_r_0_b_ready ), .io_tl_r_0_b_valid (io_tl_r_0_b_valid ), .io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ), .io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ), .io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ), .io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ), .io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ), .io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ), .io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ), .io_tl_r_0_c_ready (io_tl_r_0_c_ready ), .io_tl_r_0_c_valid (io_tl_r_0_c_valid ), .io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ), .io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ), .io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ), .io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ), .io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ), .io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ), .io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ), .io_tl_r_0_d_ready (io_tl_r_0_d_ready ), .io_tl_r_0_d_valid (io_tl_r_0_d_valid ), .io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ), .io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ), .io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ), .io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ), .io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ), .io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ), .io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ), .io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ), .io_tl_r_0_e_ready (io_tl_r_0_e_ready ), .io_tl_r_0_e_valid (io_tl_r_0_e_valid ), .io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ), .io_port_sck (io_port_sck ), .io_port_dq_0_i (io_port_dq_0_i ), .io_port_dq_0_o (io_port_dq_0_o ), .io_port_dq_0_oe (io_port_dq_0_oe), .io_port_dq_1_i (io_port_dq_1_i ), .io_port_dq_1_o (io_port_dq_1_o ), .io_port_dq_1_oe (io_port_dq_1_oe), .io_port_dq_2_i (io_port_dq_2_i ), .io_port_dq_2_o (io_port_dq_2_o ), .io_port_dq_2_oe (io_port_dq_2_oe), .io_port_dq_3_i (io_port_dq_3_i ), .io_port_dq_3_o (io_port_dq_3_o ), .io_port_dq_3_oe (io_port_dq_3_oe), .io_port_cs_0 (io_port_cs_0 ), .io_tl_i_0_0 (io_tl_i_0_0 ) ); endmodule
module sirv_qspi_1cs_top( input clk, input rst_n, input i_icb_cmd_valid, output i_icb_cmd_ready, input [32-1:0] i_icb_cmd_addr, input i_icb_cmd_read, input [32-1:0] i_icb_cmd_wdata, output i_icb_rsp_valid, input i_icb_rsp_ready, output [32-1:0] i_icb_rsp_rdata, output io_port_sck, input io_port_dq_0_i, output io_port_dq_0_o, output io_port_dq_0_oe, input io_port_dq_1_i, output io_port_dq_1_o, output io_port_dq_1_oe, input io_port_dq_2_i, output io_port_dq_2_o, output io_port_dq_2_oe, input io_port_dq_3_i, output io_port_dq_3_o, output io_port_dq_3_oe, output io_port_cs_0, output io_tl_i_0_0 );
wire io_tl_r_0_a_ready; assign i_icb_cmd_ready = io_tl_r_0_a_ready; wire io_tl_r_0_a_valid = i_icb_cmd_valid; wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0; wire [2:0] io_tl_r_0_a_bits_param = 3'b0; wire [2:0] io_tl_r_0_a_bits_size = 3'd2; wire [4:0] io_tl_r_0_a_bits_source = 5'b0; wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0]; wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111; wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata; wire io_tl_r_0_d_ready = i_icb_rsp_ready; wire [2:0] io_tl_r_0_d_bits_opcode; wire [1:0] io_tl_r_0_d_bits_param; wire [2:0] io_tl_r_0_d_bits_size; wire [4:0] io_tl_r_0_d_bits_source; wire io_tl_r_0_d_bits_sink; wire [1:0] io_tl_r_0_d_bits_addr_lo; wire [31:0] io_tl_r_0_d_bits_data; wire io_tl_r_0_d_bits_error; wire io_tl_r_0_d_valid; assign i_icb_rsp_valid = io_tl_r_0_d_valid; assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data; wire io_tl_r_0_b_ready = 1'b0; wire io_tl_r_0_b_valid; wire [2:0] io_tl_r_0_b_bits_opcode; wire [1:0] io_tl_r_0_b_bits_param; wire [2:0] io_tl_r_0_b_bits_size; wire [4:0] io_tl_r_0_b_bits_source; wire [28:0] io_tl_r_0_b_bits_address; wire [3:0] io_tl_r_0_b_bits_mask; wire [31:0] io_tl_r_0_b_bits_data; wire io_tl_r_0_c_ready; wire io_tl_r_0_c_valid = 1'b0; wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0; wire [2:0] io_tl_r_0_c_bits_param = 3'b0; wire [2:0] io_tl_r_0_c_bits_size = 3'd2; wire [4:0] io_tl_r_0_c_bits_source = 5'b0; wire [28:0] io_tl_r_0_c_bits_address = 29'b0; wire [31:0] io_tl_r_0_c_bits_data = 32'b0; wire io_tl_r_0_c_bits_error = 1'b0; wire io_tl_r_0_e_ready; wire io_tl_r_0_e_valid = 1'b0; wire io_tl_r_0_e_bits_sink = 1'b0; sirv_qspi_1cs u_sirv_qspi_1cs( .clock (clk ), .reset (~rst_n ), .io_tl_r_0_a_ready (io_tl_r_0_a_ready ), .io_tl_r_0_a_valid (io_tl_r_0_a_valid ), .io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ), .io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ), .io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ), .io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ), .io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ), .io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ), .io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ), .io_tl_r_0_b_ready (io_tl_r_0_b_ready ), .io_tl_r_0_b_valid (io_tl_r_0_b_valid ), .io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ), .io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ), .io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ), .io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ), .io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ), .io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ), .io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ), .io_tl_r_0_c_ready (io_tl_r_0_c_ready ), .io_tl_r_0_c_valid (io_tl_r_0_c_valid ), .io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ), .io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ), .io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ), .io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ), .io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ), .io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ), .io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ), .io_tl_r_0_d_ready (io_tl_r_0_d_ready ), .io_tl_r_0_d_valid (io_tl_r_0_d_valid ), .io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ), .io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ), .io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ), .io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ), .io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ), .io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ), .io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ), .io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ), .io_tl_r_0_e_ready (io_tl_r_0_e_ready ), .io_tl_r_0_e_valid (io_tl_r_0_e_valid ), .io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ), .io_port_sck (io_port_sck ), .io_port_dq_0_i (io_port_dq_0_i ), .io_port_dq_0_o (io_port_dq_0_o ), .io_port_dq_0_oe (io_port_dq_0_oe), .io_port_dq_1_i (io_port_dq_1_i ), .io_port_dq_1_o (io_port_dq_1_o ), .io_port_dq_1_oe (io_port_dq_1_oe), .io_port_dq_2_i (io_port_dq_2_i ), .io_port_dq_2_o (io_port_dq_2_o ), .io_port_dq_2_oe (io_port_dq_2_oe), .io_port_dq_3_i (io_port_dq_3_i ), .io_port_dq_3_o (io_port_dq_3_o ), .io_port_dq_3_oe (io_port_dq_3_oe), .io_port_cs_0 (io_port_cs_0 ), .io_tl_i_0_0 (io_tl_i_0_0 ) ); endmodule
0
2,569
data/full_repos/permissive/268184328/stopwatch/stopwatch.v
268,184,328
stopwatch.v
v
88
118
[]
[]
[]
null
[Errno 2] No such file or directory: 'preprocess.output'
null
1: b'%Error: data/full_repos/permissive/268184328/stopwatch/stopwatch.v:9: Cannot find include file: ./counter.v\n`include "./counter.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v\n data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v.v\n data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v.sv\n ./counter.v\n ./counter.v.v\n ./counter.v.sv\n obj_dir/./counter.v\n obj_dir/./counter.v.v\n obj_dir/./counter.v.sv\n%Error: data/full_repos/permissive/268184328/stopwatch/stopwatch.v:10: Cannot find include file: ./divider_s.v\n`include "./divider_s.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
102,235
module
module stopwatch(clk, rst, sw_en, pause, clear, clk_out, time_sec_h, time_sec_l, time_msec_h, time_msec_l, time_out); input clk, rst, clear, sw_en, pause; output clk_out, time_out; output [2:0] time_sec_h; output [3:0] time_sec_l, time_msec_l, time_msec_h; reg [2:0] time_sec_h; reg [3:0] time_sec_l, time_msec_l, time_msec_h; wire clk_1, clk_2; wire [2:0] time_sec_h_in; wire [3:0] time_sec_l_in, time_msec_l_in, time_msec_h_in; reg time_out; parameter time_set = 16'h1000; divider_s divider_s (.clk(clk), .rst(rst), .clk_1(clk_1), .clk_2(clk_2)); assign clk_out = clk_2; counter counter(.clk_1(clk_1), .rst(rst), .clear(clear), .sw_en(sw_en), .time_sec_h(time_sec_h_in), .time_sec_l(time_sec_l_in), .time_msec_h(time_msec_h_in), .time_msec_l(time_msec_l_in)); always @(posedge clk or negedge rst) begin if (!rst) begin time_sec_h <=0; time_sec_l <=0; time_msec_h <=0; time_msec_l <=0; end else if (!pause) begin time_sec_h <=time_sec_h_in ; time_sec_l <=time_sec_l_in ; time_msec_h <=time_msec_h_in; time_msec_l <=time_msec_l_in; end else begin time_sec_h <=time_sec_h ; time_sec_l <=time_sec_l ; time_msec_h <=time_msec_h; time_msec_l <=time_msec_l; end end always @(posedge clk or negedge rst) begin if (!rst) time_out <= 0; else begin if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == time_set) time_out = 1; else if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == 16'h5999) time_out = 0; end end endmodule
module stopwatch(clk, rst, sw_en, pause, clear, clk_out, time_sec_h, time_sec_l, time_msec_h, time_msec_l, time_out);
input clk, rst, clear, sw_en, pause; output clk_out, time_out; output [2:0] time_sec_h; output [3:0] time_sec_l, time_msec_l, time_msec_h; reg [2:0] time_sec_h; reg [3:0] time_sec_l, time_msec_l, time_msec_h; wire clk_1, clk_2; wire [2:0] time_sec_h_in; wire [3:0] time_sec_l_in, time_msec_l_in, time_msec_h_in; reg time_out; parameter time_set = 16'h1000; divider_s divider_s (.clk(clk), .rst(rst), .clk_1(clk_1), .clk_2(clk_2)); assign clk_out = clk_2; counter counter(.clk_1(clk_1), .rst(rst), .clear(clear), .sw_en(sw_en), .time_sec_h(time_sec_h_in), .time_sec_l(time_sec_l_in), .time_msec_h(time_msec_h_in), .time_msec_l(time_msec_l_in)); always @(posedge clk or negedge rst) begin if (!rst) begin time_sec_h <=0; time_sec_l <=0; time_msec_h <=0; time_msec_l <=0; end else if (!pause) begin time_sec_h <=time_sec_h_in ; time_sec_l <=time_sec_l_in ; time_msec_h <=time_msec_h_in; time_msec_l <=time_msec_l_in; end else begin time_sec_h <=time_sec_h ; time_sec_l <=time_sec_l ; time_msec_h <=time_msec_h; time_msec_l <=time_msec_l; end end always @(posedge clk or negedge rst) begin if (!rst) time_out <= 0; else begin if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == time_set) time_out = 1; else if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == 16'h5999) time_out = 0; end end endmodule
0
2,570
data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v
200,650,987
mycpu.v
v
1,237
222
[]
[]
[]
null
line:8: before: "("
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1: b'%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:386: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n : ... In instance mycpu\nassign seq_pc = fs_pc + 3\'h4;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:523: Cannot find file containing module: \'decoder_6_64\'\ndecoder_6_64 u_dec0(.in(op ), .out(op_d ));\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU,data/full_repos/permissive/200650987/decoder_6_64\n data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU,data/full_repos/permissive/200650987/decoder_6_64.v\n data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU,data/full_repos/permissive/200650987/decoder_6_64.sv\n decoder_6_64\n decoder_6_64.v\n decoder_6_64.sv\n obj_dir/decoder_6_64\n obj_dir/decoder_6_64.v\n obj_dir/decoder_6_64.sv\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:524: Cannot find file containing module: \'decoder_6_64\'\ndecoder_6_64 u_dec1(.in(func), .out(func_d));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:525: Cannot find file containing module: \'decoder_5_32\'\ndecoder_5_32 u_dec2(.in(rs ), .out(rs_d ));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:526: Cannot find file containing module: \'decoder_5_32\'\ndecoder_5_32 u_dec3(.in(rt ), .out(rt_d ));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:527: Cannot find file containing module: \'decoder_5_32\'\ndecoder_5_32 u_dec4(.in(rd ), .out(rd_d ));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:528: Cannot find file containing module: \'decoder_5_32\'\ndecoder_5_32 u_dec5(.in(sa ), .out(sa_d ));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:672: Cannot find file containing module: \'regfile\'\nregfile u_regfile(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:726: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n : ... In instance mycpu\nassign excode = ex_INT ? 6\'h00 :\n ^\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:810: Cannot find file containing module: \'alu\'\nalu u_alu(\n^~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:817: Cannot find file containing module: \'mul\'\nmul u_mul(\n^~~\n%Error: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:826: Cannot find file containing module: \'div\'\ndiv u_div(\n^~~\n%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:844: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'es_excode\' generates 5 bits.\n : ... In instance mycpu\nassign exe_excode = (es_excode==6\'h00 & es_ex_occur) ? 6\'h00 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/mycpu.v:848: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'es_excode\' generates 5 bits.\n : ... In instance mycpu\n ex_data_ADES ? 6\'h05 :\n ^\n%Error: Exiting due to 10 error(s), 4 warning(s)\n'
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module
module mycpu( input [ 5:0] hw_int , input clk , input resetn , (*mark_debug = "true"*)output inst_req , (*mark_debug = "true"*)output inst_wr , (*mark_debug = "true"*)output [1 :0] inst_size , (*mark_debug = "true"*)output [31:0] inst_addr , (*mark_debug = "true"*)output [31:0] inst_wdata , (*mark_debug = "true"*)input [31:0] inst_rdata , (*mark_debug = "true"*)input inst_addr_ok , (*mark_debug = "true"*)input inst_data_ok , (*mark_debug = "true"*)output data_req , (*mark_debug = "true"*)output data_wr , (*mark_debug = "true"*)output [1 :0] data_size , (*mark_debug = "true"*)output [31:0] data_addr , (*mark_debug = "true"*)output [31:0] data_wdata , (*mark_debug = "true"*)input [31:0] data_rdata , (*mark_debug = "true"*)input data_addr_ok , (*mark_debug = "true"*)input data_data_ok , output [31:0] debug_wb_pc , output [ 3:0] debug_wb_rf_wen , output [ 4:0] debug_wb_rf_wnum , output [31:0] debug_wb_rf_wdata ); reg reset; always @(posedge clk) reset <= ~resetn; wire [31:0] seq_pc; wire [31:0] nextpc; wire to_fs_valid; wire ex_inst_ADEL; wire fs_allowin; wire fs_ready_go; wire fs_to_ds_valid; reg fs_valid; reg fs_inst_data_ok; reg [31:0] fs_inst; (*mark_debug = "true"*)reg [31:0] fs_pc; wire [31:0] inst; reg fs_inst_ADEL; wire ds_allowin; wire ds_ready_go; wire ds_to_es_valid; reg ds_valid; reg [31:0] ds_pc; reg [31:0] ds_inst; wire [ 5:0] op; wire [ 4:0] rs; wire [ 4:0] rt; wire [ 4:0] rd; wire [ 4:0] sa; wire [ 5:0] func; wire [15:0] imm; wire [25:0] jidx; wire [ 2:0] sel; wire [63:0] op_d; wire [31:0] rs_d; wire [31:0] rt_d; wire [31:0] rd_d; wire [31:0] sa_d; wire [63:0] func_d; wire inst_ADDU; wire inst_SUBU; wire inst_SLT; wire inst_SLTU; wire inst_AND; wire inst_OR; wire inst_XOR; wire inst_NOR; wire inst_SLL; wire inst_SRL; wire inst_SRA; wire inst_ADDIU; wire inst_LUI; wire inst_LW; wire inst_SW; wire inst_BEQ; wire inst_BNE; wire inst_JAL; wire inst_JR; wire inst_ADD; wire inst_ADDI; wire inst_SUB; wire inst_SLTI; wire inst_SLTIU; wire inst_ANDI; wire inst_ORI; wire inst_XORI; wire inst_SLLV; wire inst_SRAV; wire inst_SRLV; wire inst_DIV; wire inst_DIVU; wire inst_MULT; wire inst_MULTU; wire inst_MFHI; wire inst_MFLO; wire inst_MTHI; wire inst_MTLO; wire inst_J; wire inst_BGEZ; wire inst_BGTZ; wire inst_BLEZ; wire inst_BLTZ; wire inst_BLTZAL; wire inst_BGEZAL; wire inst_JALR; wire inst_LB; wire inst_LBU; wire inst_LH; wire inst_LHU; wire inst_LWL; wire inst_LWR; wire inst_SB; wire inst_SH; wire inst_SWL; wire inst_SWR; wire inst_MTC0; wire inst_MFC0; wire inst_ERET; wire inst_SYSCALL; wire inst_BREAK; wire [11:0] alu_op; wire src1_is_sa; wire src1_is_pc; wire src2_is_imm; wire src2_is_uimm; wire src2_is_8; wire res_from_mem; wire dst_is_r31; wire dst_is_rt; wire gr_we; wire not_read_rs; wire not_read_rt; wire inst_BRANCH; wire [ 4:0] dest; wire [ 6:0] load_mask; wire [ 4:0] save_mask; wire [ 4:0] rf_raddr1; wire [31:0] rf_rdata1; wire [ 4:0] rf_raddr2; wire [31:0] rf_rdata2; wire [31:0] rs_value; wire [31:0] rt_value; wire rs_eq_rt; wire rs_zero; wire rs_gez; wire rs_gtz; wire rs_lez; wire rs_ltz; wire br_taken; wire [31:0] br_target; wire [ 3:0] mul_div; wire rs_from_es; wire rs_from_ms; wire rs_from_ws; wire rt_from_es; wire rt_from_ms; wire rt_from_ws; wire rs_stall; wire rt_stall; wire stall; reg ds_ex_tag; reg ds_inst_ADEL; wire ds_exception; wire [ 4:0] excode; wire ex_INT; wire ex_RI; wire es_allowin; wire es_ready_go; wire es_to_ms_valid; reg es_valid; reg [31:0] es_pc; reg [31:0] es_rs_value; reg [31:0] es_rt_value; reg [15:0] es_imm; reg [11:0] es_alu_op; reg es_src1_is_sa; reg es_src1_is_pc; reg es_src2_is_imm; reg es_src2_is_uimm; reg es_src2_is_8; reg es_res_from_mem; reg es_gr_we; reg [ 3:0] es_mul_div; reg es_inst_MFHI; reg es_inst_MFLO; reg es_inst_MTHI; reg es_inst_MTLO; reg es_inst_MTC0; reg es_inst_MFC0; reg es_inst_ERET; reg es_inst_BRANCH; reg [ 4:0] es_dest; reg [ 6:0] es_load_mask; reg [ 4:0] es_save_mask; wire [ 4:0] mem_we; wire [31:0] mem_wdata; wire [63:0] mul_result; wire div_done; wire [63:0] div_result; wire [31:0] alu_src1; wire [31:0] alu_src2; wire [31:0] alu_result; wire es_exception; reg [ 7:0] es_cp0_addr; reg [ 4:0] es_excode; reg es_ex_tag; reg es_ex_occur; reg es_inst_ADEL; reg es_ov_add; reg es_ov_sub; wire ex_data_ADEL; (*mark_debug = "true"*)wire ex_data_ADES; wire ex_OV; wire cp0_ren; wire cp0_wen; wire [ 7:0] cp0_addr; wire [ 7:0] cp0_raddr; wire [ 7:0] cp0_waddr; wire [31:0] cp0_wr_value; wire [31:0] cp0_rd_value; wire ms_allowin; wire ms_ready_go; wire ms_to_ws_valid; reg ms_valid; reg [31:0] ms_pc; reg [ 4:0] ms_dest; reg [ 6:0] ms_load_mask; reg [ 4:0] ms_save_mask; reg ms_res_from_mem; reg ms_gr_we; reg [31:0] ms_final_result; reg [ 3:0] ms_mul_div; reg [63:0] ms_div_result; reg ms_inst_MTHI; reg ms_inst_MTLO; reg [31:0] ms_data_addr; reg ms_data_data_ok; reg [31:0] ms_data; reg [31:0] ms_rt_value; reg ms_inst_BRANCH; wire [31:0] mem_result; wire [31:0] mask_result; wire [31:0] final_result; reg ms_ex_tag; wire ws_allowin; wire ws_ready_go; reg ws_valid; reg [31:0] ws_pc; reg ws_gr_we; reg [ 4:0] ws_dest; reg [31:0] ws_final_result; wire rf_we; wire [ 4:0] rf_waddr; wire [31:0] rf_wdata; reg [31:0] HI; reg [31:0] LO; wire [31:0] next_HI; wire [31:0] next_LO; reg ws_ex_tag; wire exception_commit; wire set_ex_tag; wire [ 5:0] exe_excode; reg [31:0] cr_badvaddr; wire [31:0] badvaddr_value; assign badvaddr_value = cr_badvaddr; reg [31:0] cr_count; wire [31:0] count_value; assign count_value = cr_count; reg [31:0] cr_compare; wire [31:0] compare_value; assign compare_value = cr_compare; wire cr_status_BEV; reg cr_status_IM7; reg cr_status_IM6; reg cr_status_IM5; reg cr_status_IM4; reg cr_status_IM3; reg cr_status_IM2; reg cr_status_IM1; reg cr_status_IM0; reg cr_status_EXL; reg cr_status_IE; assign cr_status_BEV = 1'b1; wire [31:0] status_value; assign status_value = { 9'b0, cr_status_BEV, 6'b0, cr_status_IM7, cr_status_IM6, cr_status_IM5, cr_status_IM4, cr_status_IM3, cr_status_IM2, cr_status_IM1, cr_status_IM0, 6'b0, cr_status_EXL, cr_status_IE }; reg cr_cause_BD; reg cr_cause_TI; reg cr_cause_IP7; reg cr_cause_IP6; reg cr_cause_IP5; reg cr_cause_IP4; reg cr_cause_IP3; reg cr_cause_IP2; reg cr_cause_IP1; reg cr_cause_IP0; reg [4:0] cr_cause_ExcCode; wire [31:0] cause_value; assign cause_value = { cr_cause_BD, cr_cause_TI, 14'b0, cr_cause_IP7, cr_cause_IP6, cr_cause_IP5, cr_cause_IP4, cr_cause_IP3, cr_cause_IP2, cr_cause_IP1, cr_cause_IP0, 1'b0, cr_cause_ExcCode, 2'b00 }; reg [31:0] cr_epc; wire [31:0] epc_value; assign epc_value = cr_epc; assign to_fs_valid = ~reset; /; ds_pc <= fs_pc; ds_inst <= fs_inst; end else if(set_ex_tag & !es_inst_ERET) ds_ex_reg <= 1'b1; end assign op = ds_inst[31:26]; assign rs = ds_inst[25:21]; assign rt = ds_inst[20:16]; assign rd = ds_inst[15:11]; assign sa = ds_inst[10: 6]; assign func = ds_inst[ 5: 0]; assign imm = ds_inst[15: 0]; assign jidx = ds_inst[25: 0]; assign sel = ds_inst[ 2: 0]; decoder_6_64 u_dec0(.in(op ), .out(op_d )); decoder_6_64 u_dec1(.in(func), .out(func_d)); decoder_5_32 u_dec2(.in(rs ), .out(rs_d )); decoder_5_32 u_dec3(.in(rt ), .out(rt_d )); decoder_5_32 u_dec4(.in(rd ), .out(rd_d )); decoder_5_32 u_dec5(.in(sa ), .out(sa_d )); assign inst_ADDU = op_d[6'h00] & func_d[6'h21] & sa_d[5'h00]; assign inst_SUBU = op_d[6'h00] & func_d[6'h23] & sa_d[5'h00]; assign inst_SLT = op_d[6'h00] & func_d[6'h2a] & sa_d[5'h00]; assign inst_SLTU = op_d[6'h00] & func_d[6'h2b] & sa_d[5'h00]; assign inst_AND = op_d[6'h00] & func_d[6'h24] & sa_d[5'h00]; assign inst_OR = op_d[6'h00] & func_d[6'h25] & sa_d[5'h00]; assign inst_XOR = op_d[6'h00] & func_d[6'h26] & sa_d[5'h00]; assign inst_NOR = op_d[6'h00] & func_d[6'h27] & sa_d[5'h00]; assign inst_SLL = op_d[6'h00] & func_d[6'h00] & rs_d[5'h00]; assign inst_SRL = op_d[6'h00] & func_d[6'h02] & rs_d[5'h00]; assign inst_SRA = op_d[6'h00] & func_d[6'h03] & rs_d[5'h00]; assign inst_ADDIU = op_d[6'h09]; assign inst_LUI = op_d[6'h0f] & rs_d[5'h00]; assign inst_LW = op_d[6'h23]; assign inst_SW = op_d[6'h2b]; assign inst_BEQ = op_d[6'h04]; assign inst_BNE = op_d[6'h05]; assign inst_JAL = op_d[6'h03]; assign inst_JR = op_d[6'h00] & func_d[6'h08] & rt_d[5'h00] & rd_d[5'h00] & sa_d[5'h00]; assign inst_ADD = op_d[6'h00] & func_d[6'h20] & sa_d[5'h00]; assign inst_ADDI = op_d[6'h08]; assign inst_SUB = op_d[6'h00] & func_d[6'h22] & sa_d[5'h00]; assign inst_SLTI = op_d[6'h0a]; assign inst_SLTIU = op_d[6'h0b]; assign inst_ANDI = op_d[6'h0c]; assign inst_ORI = op_d[6'h0d]; assign inst_XORI = op_d[6'h0e]; assign inst_SLLV = op_d[6'h00] & func_d[6'h04] & sa_d[5'h00]; assign inst_SRAV = op_d[6'h00] & func_d[6'h07] & sa_d[5'h00]; assign inst_SRLV = op_d[6'h00] & func_d[6'h06] & sa_d[5'h00]; assign inst_DIV = op_d[6'h00] & func_d[6'h1a] & sa_d[5'h00] & rd_d[5'h00]; assign inst_DIVU = op_d[6'h00] & func_d[6'h1b] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MULT = op_d[6'h00] & func_d[6'h18] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MULTU = op_d[6'h00] & func_d[6'h19] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MFHI = op_d[6'h00] & func_d[6'h10] & sa_d[5'h00] & rs_d[5'h00] & rt_d[5'h00]; assign inst_MFLO = op_d[6'h00] & func_d[6'h12] & sa_d[5'h00] & rs_d[5'h00] & rt_d[5'h00]; assign inst_MTHI = op_d[6'h00] & func_d[6'h11] & sa_d[5'h00] & rt_d[5'h00] & rd_d[5'h00]; assign inst_MTLO = op_d[6'h00] & func_d[6'h13] & sa_d[5'h00] & rt_d[5'h00] & rd_d[5'h00]; assign inst_J = op_d[6'h02]; assign inst_BGEZ = op_d[6'h01] & rt_d[5'h01]; assign inst_BGTZ = op_d[6'h07] & rt_d[5'h00]; assign inst_BLEZ = op_d[6'h06] & rt_d[5'h00]; assign inst_BLTZ = op_d[6'h01] & rt_d[5'h00]; assign inst_BLTZAL = op_d[6'h01] & rt_d[5'h10]; assign inst_BGEZAL = op_d[6'h01] & rt_d[5'h11]; assign inst_JALR = op_d[6'h00] & func_d[6'h09] & sa_d[5'h00] & rt_d[5'h00]; assign inst_LB = op_d[6'h20]; assign inst_LBU = op_d[6'h24]; assign inst_LH = op_d[6'h21]; assign inst_LHU = op_d[6'h25]; assign inst_LWL = op_d[6'h22]; assign inst_LWR = op_d[6'h26]; assign inst_SB = op_d[6'h28]; assign inst_SH = op_d[6'h29]; assign inst_SWL = op_d[6'h2a]; assign inst_SWR = op_d[6'h2e]; assign inst_ERET = op_d[6'h10] & func_d[6'h18]&rs_d[5'h10]&rt_d[5'h00]&rd_d[5'h00]&sa_d[5'h00]; assign inst_MFC0 = op_d[6'h10] & (func[5:3]==3'b0) & rs_d[5'h00] & sa_d[5'h00]; assign inst_MTC0 = op_d[6'h10] & (func[5:3]==3'b0) & rs_d[5'h04] & sa_d[5'h00]; assign inst_BREAK = op_d[6'h00] & func_d[6'h0d]; assign inst_SYSCALL= op_d[6'h00] & func_d[6'h0c]; assign alu_op[ 0] = inst_ADD | inst_ADDU | inst_ADDI | inst_ADDIU | inst_LW | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SW | inst_SB | inst_SH | inst_SWL | inst_SWR | inst_JAL | inst_BLTZAL | inst_BGEZAL | inst_JALR; assign alu_op[ 1] = inst_SUB | inst_SUBU | inst_BEQ | inst_BNE ; assign alu_op[ 2] = inst_SLT | inst_SLTI; assign alu_op[ 3] = inst_SLTU | inst_SLTIU; assign alu_op[ 4] = inst_AND | inst_ANDI; assign alu_op[ 5] = inst_NOR; assign alu_op[ 6] = inst_OR | inst_ORI | inst_MTHI | inst_MTLO; assign alu_op[ 7] = inst_XOR | inst_XORI; assign alu_op[ 8] = inst_SLL | inst_SLLV; assign alu_op[ 9] = inst_SRL | inst_SRLV; assign alu_op[10] = inst_SRA | inst_SRAV; assign alu_op[11] = inst_LUI; assign src1_is_sa = inst_SLL | inst_SRL | inst_SRA; assign src1_is_pc = inst_JAL | inst_JALR | inst_BLTZAL | inst_BGEZAL; assign src2_is_imm = inst_LUI | inst_LW | inst_SW | inst_ADDI | inst_ADDIU | inst_SLTI | inst_SLTIU | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SB | inst_SH | inst_SW | inst_SWR | inst_SWL; assign src2_is_uimm = inst_ORI | inst_ANDI | inst_XORI; assign src2_is_8 = inst_JAL | inst_JALR | inst_BLTZAL | inst_BGEZAL; assign res_from_mem = inst_LW | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR; assign dst_is_r31 = inst_JAL | inst_BLTZAL | inst_BGEZAL; assign dst_is_rt = inst_LUI | inst_LW | inst_ADDIU | inst_ORI | inst_ANDI | inst_XORI | inst_ADDI | inst_SLTI | inst_SLTIU | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_MFC0; assign gr_we = ~inst_SW & ~inst_BEQ & ~inst_BNE & ~inst_JR & ~inst_DIV & ~inst_DIVU & ~inst_MULT & ~inst_MULTU & ~inst_MTHI & ~inst_MTLO & ~inst_J & ~inst_BGEZ & ~inst_BGTZ & ~inst_BLEZ & ~inst_BLTZ & ~inst_SB & ~inst_SH & ~inst_SWL & ~inst_SWR & ~inst_MTC0 & ~inst_ERET & ~inst_SYSCALL & ~inst_BREAK; assign not_read_rs = inst_JAL | inst_J | inst_MFC0 | inst_MTC0 | inst_ERET | inst_BREAK | inst_SYSCALL; assign not_read_rt = inst_LUI | inst_ADDIU | inst_LW | inst_JAL | inst_ADDI | inst_SLTI | inst_SLTIU | inst_ANDI | inst_ORI | inst_XORI | inst_J | inst_BGEZ | inst_BLTZAL | inst_BGEZAL | inst_LB | inst_LBU |inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_MFC0 | inst_ERET | inst_BREAK | inst_SYSCALL; assign mul_div = {inst_MULT, inst_MULTU, inst_DIV, inst_DIVU}; assign dest = dst_is_r31 ? 5'd31 : dst_is_rt ? rt : rd; assign load_mask = {inst_LW, inst_LH, inst_LHU, inst_LB, inst_LBU, inst_LWL, inst_LWR}; assign save_mask = {inst_SW, inst_SH, inst_SB, inst_SWL, inst_SWR}; assign inst_BRANCH = inst_BEQ | inst_BNE | inst_BGEZ | inst_BGEZAL | inst_BLTZ | inst_BLTZAL | inst_BGTZ | inst_BLEZ| inst_JAL | inst_JALR | inst_JR | inst_J; assign rs_from_es = (!not_read_rs) && (rs != 5'b0) && (rs == es_dest) && es_gr_we && (!inst_BRANCH) && (!es_res_from_mem) && (!es_inst_MFHI) && (!es_inst_MFLO) &&(!es_inst_MFC0) && (!es_ex_tag) && es_ready_go; assign rs_from_ms = (!not_read_rs) && (rs != 5'b0) && (rs == ms_dest) && ms_gr_we && (!inst_BRANCH) && (!ms_ex_tag) && ms_ready_go; assign rs_from_ws = (!not_read_rs) && (rs != 5'b0) && (rs == ws_dest) && ws_gr_we && (!inst_BRANCH) && (!ws_ex_tag) && ws_ready_go; assign rt_from_es = (!not_read_rt) && (rt != 5'b0) && (rt == es_dest) && es_gr_we && (!inst_BRANCH) && (!es_res_from_mem) && (!es_inst_MFHI) && (!es_inst_MFLO) &&(!es_inst_MFC0) && (!es_ex_tag) && es_ready_go; assign rt_from_ms = (!not_read_rt) && (rt != 5'b0) && (rt == ms_dest) && ms_gr_we && (!inst_BRANCH) && (!ms_ex_tag) && ms_ready_go; assign rt_from_ws = (!not_read_rt) && (rt != 5'b0) && (rt == ws_dest) && ws_gr_we && (!inst_BRANCH) && (!ws_ex_tag) && ws_ready_go; assign rs_stall = (not_read_rs || rs == 5'b0 || rs_from_es || rs_from_ms || rs_from_ws) ? 1'b0 : (rs == es_dest || rs == ms_dest || rs == ws_dest); assign rt_stall = (not_read_rt || rt == 5'b0 || rt_from_es || rt_from_ms || rt_from_ws) ? 1'b0 : (rt == es_dest || rt == ms_dest || rt == ws_dest); assign stall = (rs_stall || rt_stall) & !set_ex_tag; assign rf_raddr1 = rs; assign rf_raddr2 = rt; regfile u_regfile( .clk (clk ), .raddr1 (rf_raddr1), .rdata1 (rf_rdata1), .raddr2 (rf_raddr2), .rdata2 (rf_rdata2), .we (rf_we ), .waddr (rf_waddr ), .wdata (rf_wdata ) ); assign rs_value = rs_from_es ? alu_result : rs_from_ms ? final_result : rs_from_ws ? ws_final_result : rf_rdata1; assign rt_value = rt_from_es ? alu_result : rt_from_ms ? final_result : rt_from_ws ? ws_final_result : rf_rdata2; assign rs_eq_rt = (rf_rdata1 == rf_rdata2); assign rs_zero = ~(|rf_rdata1); assign rs_gez = rs_zero | !rf_rdata1[31]; assign rs_gtz = !rs_zero & !rf_rdata1[31]; assign rs_lez = rs_zero | rf_rdata1[31]; assign rs_ltz = !rs_zero & rf_rdata1[31]; assign br_taken = ( rs_eq_rt && inst_BEQ || !rs_eq_rt && inst_BNE || rs_gez && (inst_BGEZ | inst_BGEZAL) || rs_ltz && (inst_BLTZ | inst_BLTZAL) || rs_gtz && inst_BGTZ || rs_lez && inst_BLEZ || inst_JAL || inst_JALR || inst_JR || inst_J )&& !ds_ex_tag; assign br_target = (inst_JAL || inst_J) ? ({fs_pc[31:28], jidx[25:0], 2'b0}) : (inst_JR || inst_JALR) ? rf_rdata1 : fs_pc + {{14{imm[15]}}, imm[15:0], 2'b0}; assign ex_INT = |(cause_value[15:8] & status_value[15:8]); assign ex_RI = !(inst_ADDU | inst_SUBU | inst_SLT | inst_SLTU | inst_AND | inst_OR | inst_XOR | inst_NOR | inst_SLL | inst_SRL | inst_SRA | inst_ADDIU | inst_LUI | inst_LW | inst_SW | inst_BEQ | inst_BNE | inst_JAL | inst_JR | inst_ADD | inst_ADDI | inst_SUB | inst_SLTI | inst_SLTIU | inst_ANDI | inst_ORI | inst_XORI | inst_SLLV | inst_SRAV | inst_SRLV | inst_DIV | inst_DIVU | inst_MULT | inst_MULTU | inst_MFHI | inst_MFLO | inst_MTHI | inst_MTLO | inst_J | inst_BGEZ | inst_BGTZ | inst_BLEZ | inst_BLTZ | inst_BLTZAL| inst_BGEZAL| inst_JALR | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SB | inst_SH | inst_SWL | inst_SWR | inst_ERET | inst_MFC0 | inst_MTC0 | inst_BREAK | inst_SYSCALL); assign excode = ex_INT ? 6'h00 : ex_RI ? 6'h0a : inst_SYSCALL ? 6'h08 : inst_BREAK ? 6'h09 : 6'h00 ; assign ds_exception = inst_SYSCALL | inst_BREAK | ex_RI | ex_INT; reg es_ex_reg; assign es_ready_go = (es_mul_div[1:0] == 2'b0 | es_ex_tag) ? 1'b1 : div_done; assign es_allowin = !es_valid || es_ready_go && ms_allowin; assign es_to_ms_valid = es_valid && es_ready_go || stall; always @(posedge clk) begin if (reset) begin es_valid <= 1'b0; es_mul_div <= 4'b0; es_ex_tag <= 1'b0; es_ex_reg <= 1'b0; es_ex_occur <= 1'b0; es_inst_ADEL <= 1'b0; end else if (es_allowin) begin es_valid <= ds_to_es_valid; end if(set_ex_tag & !(ds_to_es_valid && es_allowin)) es_ex_reg <= 1'b1; if (stall & !es_valid) begin es_res_from_mem <= 1'b0; es_gr_we <= 1'b0; es_dest <= 5'b0; end else if (ds_to_es_valid && es_allowin) begin es_pc <= ds_pc; es_rs_value <= rs_value; es_rt_value <= rt_value; es_imm <= imm; es_alu_op <= alu_op; es_src1_is_sa <= src1_is_sa; es_src1_is_pc <= src1_is_pc; es_src2_is_imm <= src2_is_imm; es_src2_is_uimm <= src2_is_uimm; es_src2_is_8 <= src2_is_8; es_res_from_mem <= res_from_mem; es_gr_we <= gr_we; es_dest <= gr_we ? dest : 5'b0; es_load_mask <= load_mask; es_save_mask <= save_mask; es_mul_div <= mul_div; es_inst_MFHI <= inst_MFHI; es_inst_MFLO <= inst_MFLO; es_inst_MTHI <= inst_MTHI; es_inst_MTLO <= inst_MTLO; es_inst_MTC0 <= inst_MTC0; es_inst_MFC0 <= inst_MFC0; es_inst_ERET <= inst_ERET; es_inst_BRANCH <= inst_BRANCH; es_excode <= excode; es_ex_occur <= ds_exception; es_inst_ADEL <= ds_inst_ADEL; es_cp0_addr <= {rd, sel}; es_ov_add <= inst_ADD | inst_ADDI; es_ov_sub <= inst_SUB; if(es_ex_reg || set_ex_tag) begin es_ex_tag <= 1'b1; es_ex_reg <= 1'b0; end else begin es_ex_tag <= ds_ex_tag; end end end assign alu_src1 = es_src1_is_sa ? {27'b0, es_imm[10:6]} : es_src1_is_pc ? es_pc[31:0] : es_rs_value; assign alu_src2 = es_src2_is_imm ? {{16{es_imm[15]}}, es_imm[15:0]} : es_src2_is_uimm ? {16'b0, es_imm[15:0]} : es_src2_is_8 ? 32'd8 : es_rt_value; alu u_alu( .alu_control (es_alu_op ), .alu_src1 (alu_src1 ), .alu_src2 (alu_src2 ), .alu_result (alu_result) ); mul u_mul( .mul_clk (clk), .resetn (resetn), .mul_signed (es_mul_div[3]), .x (es_rs_value), .y (es_rt_value), .result (mul_result) ); div u_div( .div_clk (clk), .resetn (resetn), .div ((es_mul_div[1] | es_mul_div[0]) & !es_ex_tag), .div_signed (es_mul_div[1]), .x (es_rs_value), .y (es_rt_value), .s (div_result[63:32]), .r (div_result[31: 0]), .complete (div_done) ); assign ex_OV = (~alu_src1[31]&~alu_src2[31]& alu_result[31] | alu_src1[31]& alu_src2[31]&~alu_result[31] ) & es_ov_add | (~alu_src1[31]& alu_src2[31]& alu_result[31] | alu_src1[31]&~alu_src2[31]&~alu_result[31] ) & es_ov_sub ; assign ex_data_ADES = (es_save_mask[4] & (alu_result[1] | alu_result[0])) | (es_save_mask[3] & alu_result[0]); assign ex_data_ADEL = (es_load_mask[6] & (alu_result[1] | alu_result[0])) | ((es_load_mask[5] | es_load_mask[4]) & alu_result[0]); assign es_exception = ex_data_ADEL | ex_data_ADES | ex_OV | es_ex_occur | es_inst_ADEL; assign exe_excode = (es_excode==6'h00 & es_ex_occur) ? 6'h00 : es_inst_ADEL ? 6'h04 : ex_OV ? 6'h0c : ex_data_ADEL ? 6'h04 : ex_data_ADES ? 6'h05 : es_excode ; reg ms_ex_reg; (*mark_debug = "true"*)reg [2:0] ms_state; reg [2:0] ms_next_state; assign ms_ready_go = ms_state == 3'b000; assign ms_allowin = !ms_valid || ms_ready_go && ws_allowin; assign ms_to_ws_valid = ms_valid && ms_ready_go; always @(posedge clk) begin if (reset) begin ms_valid <= 1'b0; ms_ex_tag <= 1'b0; ms_ex_reg <= 1'b0; ms_data_data_ok <= 1'b1; end else if (ms_allowin) begin ms_valid <= es_to_ms_valid; end ms_data_data_ok <= data_data_ok; if(data_data_ok) ms_data <= data_rdata; if (es_to_ms_valid && ms_allowin) begin ms_pc <= es_pc; ms_gr_we <= es_gr_we; ms_dest <= es_dest; ms_load_mask <= es_load_mask; ms_save_mask <= es_save_mask; ms_final_result <= es_inst_MFHI ? next_HI : es_inst_MFLO ? next_LO : es_inst_MFC0 ? cp0_rd_value : alu_result; ms_res_from_mem <= es_res_from_mem; ms_mul_div <= es_mul_div; ms_div_result <= div_result; ms_inst_MTHI <= es_inst_MTHI; ms_inst_MTLO <= es_inst_MTLO; ms_rt_value <= es_rt_value; ms_inst_BRANCH <= es_inst_BRANCH; if(ms_ex_reg || set_ex_tag) begin ms_ex_tag <= 1'b1; ms_ex_reg <= 1'b0; end else begin ms_ex_tag <= es_ex_tag; end end else if(set_ex_tag) ms_ex_reg <= 1'b1; end wire write_twice; wire [1 :0] w1_size; wire [31:0] w1_addr; wire [1 :0] w2_size; wire [31:0] w2_addr; assign write_twice = (ms_save_mask[1] & (ms_final_result[1:0]==2'b10)) | (ms_save_mask[0] & (ms_final_result[1:0]==2'b01)); assign w1_size = ms_save_mask[4] ? 2'b10 : ms_save_mask[3] & (ms_final_result[1:0]==2'b00) ? 2'b01 : ms_save_mask[3] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[2] & (ms_final_result[1:0]==2'b00) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b01) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b10) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b11) ? 2'b00 : ms_save_mask[1] & (ms_final_result[1:0]==2'b00) ? 2'b00 : ms_save_mask[1] & (ms_final_result[1:0]==2'b01) ? 2'b01 : ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[1] & (ms_final_result[1:0]==2'b11) ? 2'b10 : ms_save_mask[0] & (ms_final_result[1:0]==2'b00) ? 2'b10 : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? 2'b00 : ms_save_mask[0] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[0] & (ms_final_result[1:0]==2'b11) ? 2'b00 : 2'b11; assign w1_addr = ms_save_mask[1] ? {ms_final_result[31:2], 2'b00} : ms_final_result; assign w2_size = ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? 2'b00 : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? 2'b01 : 2'b11; assign w2_addr = ms_save_mask[0] ? {ms_final_result[31:2], 2'b10} : ms_final_result; assign mem_wdata = ms_save_mask[4] ? ms_rt_value : ms_save_mask[3] & (ms_final_result[1:0]==2'b00) ? {16'b0, ms_rt_value[15: 0]} : ms_save_mask[3] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[15: 0], 16'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b00) ? {24'b0, ms_rt_value[ 7: 0]} : ms_save_mask[2] & (ms_final_result[1:0]==2'b01) ? {16'b0, ms_rt_value[ 7: 0], 8'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b10) ? { 8'b0, ms_rt_value[ 7: 0], 16'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[ 7: 0], 24'b0} : ms_save_mask[1] & (ms_final_result[1:0]==2'b00) ? {24'b0, ms_rt_value[31:24]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b01) ? {16'b0, ms_rt_value[31:16]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? { 8'b0, ms_rt_value[31: 8]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b11) ? ms_rt_value : ms_save_mask[0] & (ms_final_result[1:0]==2'b00) ? ms_rt_value : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? {ms_rt_value[23: 0], 8'b0} : ms_save_mask[0] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[15: 0], 16'b0} : ms_save_mask[0] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[ 7: 0], 24'b0} : 32'b0; assign mem_result = data_rdata; assign mask_result = ms_load_mask[6] ? mem_result[31:0] : ms_load_mask[5] & (ms_final_result[1:0]==2'b00) ? {{16{mem_result[15]}}, mem_result[15: 0]} : ms_load_mask[5] & (ms_final_result[1:0]==2'b10) ? {{16{mem_result[31]}}, mem_result[31:16]} : ms_load_mask[4] & (ms_final_result[1:0]==2'b00) ? {16'b0, mem_result[15:0]} : ms_load_mask[4] & (ms_final_result[1:0]==2'b10) ? {16'b0, mem_result[31:16]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b00) ? {{24{mem_result[ 7]}}, mem_result[ 7: 0]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b01) ? {{24{mem_result[15]}}, mem_result[15: 8]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b10) ? {{24{mem_result[23]}}, mem_result[23:16]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b11) ? {{24{mem_result[31]}}, mem_result[31:24]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b00) ? {24'b0, mem_result[ 7: 0]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b01) ? {24'b0, mem_result[15: 8]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b10) ? {24'b0, mem_result[23:16]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b11) ? {24'b0, mem_result[31:24]} : ms_load_mask[1] & (ms_final_result[1:0]==2'b00) ? {mem_result[ 7: 0], ms_rt_value[23: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b01) ? {mem_result[15: 0], ms_rt_value[15: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b10) ? {mem_result[23: 0], ms_rt_value[ 7: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b11) ? {mem_result[31: 0]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b00) ? {mem_result[31: 0]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b01) ? {ms_rt_value[31:24], mem_result[31: 8]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[31:16], mem_result[31:16]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[31: 8], mem_result[31:24]}: 32'b0; wire inst_LOAD = |es_load_mask; wire inst_STORE = |es_save_mask; assign data_req = ms_valid & (ms_state==3'b001 || ms_state==3'b011); assign data_wr = |ms_save_mask & data_req; assign data_size = |ms_load_mask ? 2'b10 : ms_state==3'b011 ? w2_size : w1_size; assign data_addr = |ms_load_mask ? ms_final_result : ms_state==3'b011 ? w2_addr : w1_addr; assign data_wdata = mem_wdata; assign final_result = ms_res_from_mem ? mask_result : ms_final_result; always @(posedge clk) begin if (reset) ms_state <= 3'b000; else ms_state <= ms_next_state; end always @(*) begin if(ms_state == 3'b000 & es_to_ms_valid & ms_allowin & (inst_LOAD|inst_STORE) & !es_ex_tag & !(ex_data_ADEL | ex_data_ADES | ex_OV)) ms_next_state <= 3'b001; else if(ms_state == 3'b001 & data_addr_ok) ms_next_state <= 3'b010; else if(ms_state == 3'b010 & data_data_ok & write_twice) ms_next_state <= 3'b011; else if(ms_state == 3'b010 & data_data_ok) ms_next_state <= 3'b000; else if(ms_state == 3'b011 & data_addr_ok) ms_next_state <= 3'b100; else if(ms_state == 3'b100 & data_data_ok) ms_next_state <= 3'b000; else ms_next_state <= ms_state; end assign ws_ready_go = 1'b1; assign ws_allowin = !ws_valid || ws_ready_go; always @(posedge clk) begin if (reset) begin ws_valid <= 1'b0; ws_pc <= 32'b0; ws_ex_tag <= 1'b0; end else if (ws_allowin) begin ws_valid <= ms_to_ws_valid; end if (ms_to_ws_valid && ws_allowin) begin ws_ex_tag <= ms_ex_tag; ws_pc <= ms_pc; ws_gr_we <= ms_gr_we; ws_dest <= ms_dest; ws_final_result <= final_result; HI <= next_HI; LO <= next_LO; end end reg [31:0] last_pc; wire once = (last_pc != ws_pc); always @(posedge clk) begin if (reset) last_pc <= 32'b0; else last_pc <= ws_pc; end assign next_HI = ms_ex_tag ? HI : ms_inst_MTHI ? ms_final_result : ms_mul_div[3:2] != 2'b0 ? mul_result[63:32] : ms_mul_div[1:0] != 2'b0 ? ms_div_result[31: 0] : HI; assign next_LO = ms_ex_tag ? LO : ms_inst_MTLO ? ms_final_result : ms_mul_div[3:2] != 2'b0 ? mul_result[31: 0] : ms_mul_div[1:0] != 2'b0 ? ms_div_result[63:32] : LO; assign rf_we = ws_gr_we && ws_valid && !ws_ex_tag && once; assign rf_waddr = ws_dest; assign rf_wdata = ws_final_result; assign debug_wb_pc = ws_pc; assign debug_wb_rf_wen = {4{rf_we}}; assign debug_wb_rf_wnum = ws_dest; assign debug_wb_rf_wdata = ws_final_result; wire count_cmp_eq; wire timer_int; wire [ 5:0] int_pending; assign set_ex_tag = !es_valid ? 1'b0 : es_inst_ERET ? 1'b1 : (status_value[1] | es_ex_tag) ? 1'b0 : es_exception; assign exception_commit = status_value[1] ? 1'b0 : es_exception; assign count_cmp_eq = cr_compare == cr_count; assign timer_int = cr_cause_TI; assign int_pending[ 5] = hw_int[5] | timer_int; assign int_pending[4:0] = hw_int[4:0]; assign cp0_ren = es_inst_MFC0; assign cp0_wen = es_inst_MTC0 & !es_ex_tag; assign cp0_addr = es_cp0_addr; assign cp0_raddr = es_inst_MFC0 ? cp0_addr : 8'h0; assign cp0_waddr = es_inst_MTC0 ? cp0_addr : 8'h0; assign cp0_wr_value = es_rt_value; assign cp0_rd_value = {32{cp0_raddr=={5'd8 , 3'd0}}} & badvaddr_value | {32{cp0_raddr=={5'd12, 3'd0}}} & status_value | {32{cp0_raddr=={5'd13, 3'd0}}} & cause_value | {32{cp0_raddr=={5'd14, 3'd0}}} & epc_value | {32{cp0_raddr=={5'd9 , 3'd0}}} & count_value | {32{cp0_raddr=={5'd11, 3'd0}}} & compare_value ; reg count_add_en; always @(posedge clk) count_add_en <= reset ? 1'b0 : ~count_add_en; always @(posedge clk) begin if (exception_commit && (exe_excode==6'h04 || exe_excode==6'h05) && (!es_ex_tag || es_inst_ERET)) cr_badvaddr <= (ex_data_ADES | ex_data_ADEL) ? alu_result : es_pc; end always @(posedge clk) begin if (reset) cr_count <= 32'h0; else if (cp0_wen && cp0_waddr=={5'd9, 3'd0}) cr_count <= cp0_wr_value[31:0]; else if (count_add_en) cr_count <= cr_count + 1'b1; end always @(posedge clk) begin if (reset) cr_compare <= 32'h0; else if (cp0_wen && cp0_waddr=={5'd11, 3'd0}) cr_compare <= cp0_wr_value[31:0]; end always @(posedge clk) begin if (reset) begin cr_status_IM7 <= 1'b0; cr_status_IM6 <= 1'b0; cr_status_IM5 <= 1'b0; cr_status_IM4 <= 1'b0; cr_status_IM3 <= 1'b0; cr_status_IM2 <= 1'b0; cr_status_IM1 <= 1'b0; cr_status_IM0 <= 1'b0; cr_status_EXL <= 1'b0; cr_status_IE <= 1'b0; end else begin if (exception_commit) cr_status_EXL <= 1'b1; else if (es_inst_ERET) begin cr_status_EXL <= 1'b0; end else if (cp0_wen && cp0_waddr=={5'd12, 3'd0}) begin cr_status_EXL <= cp0_wr_value[ 1]; end if (cp0_wen && cp0_waddr=={5'd12, 3'd0}) begin cr_status_IM7 <= cp0_wr_value[ 15]; cr_status_IM6 <= cp0_wr_value[ 14]; cr_status_IM5 <= cp0_wr_value[ 13]; cr_status_IM4 <= cp0_wr_value[ 12]; cr_status_IM3 <= cp0_wr_value[ 11]; cr_status_IM2 <= cp0_wr_value[ 10]; cr_status_IM1 <= cp0_wr_value[ 9]; cr_status_IM0 <= cp0_wr_value[ 8]; cr_status_IE <= cp0_wr_value[ 0]; end end end always @(posedge clk) begin if (reset) begin cr_cause_TI <= 1'b0; end else if (cp0_wen && cp0_waddr=={5'd11, 3'd0}) begin cr_cause_TI <= 1'b0; end else if (count_cmp_eq) begin cr_cause_TI <= 1'b1; end end always @(posedge clk) begin if (reset) begin cr_cause_BD <= 1'b0; cr_cause_IP7 <= 1'b0; cr_cause_IP6 <= 1'b0; cr_cause_IP5 <= 1'b0; cr_cause_IP4 <= 1'b0; cr_cause_IP3 <= 1'b0; cr_cause_IP2 <= 1'b0; cr_cause_IP1 <= 1'b0; cr_cause_IP0 <= 1'b0; cr_cause_ExcCode<= 5'h1f; end else begin if (exception_commit) begin cr_cause_ExcCode <= exe_excode[4:0]; if (!cr_status_EXL) cr_cause_BD <= es_inst_ADEL ? 1'b0 : ms_inst_BRANCH; end if (cp0_wen && cp0_waddr=={5'd13, 3'd0}) begin cr_cause_IP1 <= cp0_wr_value[ 9]; cr_cause_IP0 <= cp0_wr_value[ 8]; end cr_cause_IP7 <= int_pending[5]; cr_cause_IP6 <= int_pending[4]; cr_cause_IP5 <= int_pending[3]; cr_cause_IP4 <= int_pending[2]; cr_cause_IP3 <= int_pending[1]; cr_cause_IP2 <= int_pending[0]; end end wire [31:0] epc; always @(posedge clk) begin if (exception_commit && !cr_status_EXL) cr_epc <= epc; else if (cp0_wen && cp0_waddr=={5'd14, 3'd0}) cr_epc <= cp0_wr_value[31:0]; end wire [29:0] pc_w_m4 = es_pc[31:2] - 1'b1; assign epc = (ms_inst_BRANCH & !es_inst_ADEL) ? {pc_w_m4, es_pc[1:0]} : es_pc; endmodule
module mycpu( input [ 5:0] hw_int , input clk , input resetn , (*mark_debug = "true"*)output inst_req , (*mark_debug = "true"*)output inst_wr , (*mark_debug = "true"*)output [1 :0] inst_size , (*mark_debug = "true"*)output [31:0] inst_addr , (*mark_debug = "true"*)output [31:0] inst_wdata , (*mark_debug = "true"*)input [31:0] inst_rdata , (*mark_debug = "true"*)input inst_addr_ok , (*mark_debug = "true"*)input inst_data_ok , (*mark_debug = "true"*)output data_req , (*mark_debug = "true"*)output data_wr , (*mark_debug = "true"*)output [1 :0] data_size , (*mark_debug = "true"*)output [31:0] data_addr , (*mark_debug = "true"*)output [31:0] data_wdata , (*mark_debug = "true"*)input [31:0] data_rdata , (*mark_debug = "true"*)input data_addr_ok , (*mark_debug = "true"*)input data_data_ok , output [31:0] debug_wb_pc , output [ 3:0] debug_wb_rf_wen , output [ 4:0] debug_wb_rf_wnum , output [31:0] debug_wb_rf_wdata );
reg reset; always @(posedge clk) reset <= ~resetn; wire [31:0] seq_pc; wire [31:0] nextpc; wire to_fs_valid; wire ex_inst_ADEL; wire fs_allowin; wire fs_ready_go; wire fs_to_ds_valid; reg fs_valid; reg fs_inst_data_ok; reg [31:0] fs_inst; (*mark_debug = "true"*)reg [31:0] fs_pc; wire [31:0] inst; reg fs_inst_ADEL; wire ds_allowin; wire ds_ready_go; wire ds_to_es_valid; reg ds_valid; reg [31:0] ds_pc; reg [31:0] ds_inst; wire [ 5:0] op; wire [ 4:0] rs; wire [ 4:0] rt; wire [ 4:0] rd; wire [ 4:0] sa; wire [ 5:0] func; wire [15:0] imm; wire [25:0] jidx; wire [ 2:0] sel; wire [63:0] op_d; wire [31:0] rs_d; wire [31:0] rt_d; wire [31:0] rd_d; wire [31:0] sa_d; wire [63:0] func_d; wire inst_ADDU; wire inst_SUBU; wire inst_SLT; wire inst_SLTU; wire inst_AND; wire inst_OR; wire inst_XOR; wire inst_NOR; wire inst_SLL; wire inst_SRL; wire inst_SRA; wire inst_ADDIU; wire inst_LUI; wire inst_LW; wire inst_SW; wire inst_BEQ; wire inst_BNE; wire inst_JAL; wire inst_JR; wire inst_ADD; wire inst_ADDI; wire inst_SUB; wire inst_SLTI; wire inst_SLTIU; wire inst_ANDI; wire inst_ORI; wire inst_XORI; wire inst_SLLV; wire inst_SRAV; wire inst_SRLV; wire inst_DIV; wire inst_DIVU; wire inst_MULT; wire inst_MULTU; wire inst_MFHI; wire inst_MFLO; wire inst_MTHI; wire inst_MTLO; wire inst_J; wire inst_BGEZ; wire inst_BGTZ; wire inst_BLEZ; wire inst_BLTZ; wire inst_BLTZAL; wire inst_BGEZAL; wire inst_JALR; wire inst_LB; wire inst_LBU; wire inst_LH; wire inst_LHU; wire inst_LWL; wire inst_LWR; wire inst_SB; wire inst_SH; wire inst_SWL; wire inst_SWR; wire inst_MTC0; wire inst_MFC0; wire inst_ERET; wire inst_SYSCALL; wire inst_BREAK; wire [11:0] alu_op; wire src1_is_sa; wire src1_is_pc; wire src2_is_imm; wire src2_is_uimm; wire src2_is_8; wire res_from_mem; wire dst_is_r31; wire dst_is_rt; wire gr_we; wire not_read_rs; wire not_read_rt; wire inst_BRANCH; wire [ 4:0] dest; wire [ 6:0] load_mask; wire [ 4:0] save_mask; wire [ 4:0] rf_raddr1; wire [31:0] rf_rdata1; wire [ 4:0] rf_raddr2; wire [31:0] rf_rdata2; wire [31:0] rs_value; wire [31:0] rt_value; wire rs_eq_rt; wire rs_zero; wire rs_gez; wire rs_gtz; wire rs_lez; wire rs_ltz; wire br_taken; wire [31:0] br_target; wire [ 3:0] mul_div; wire rs_from_es; wire rs_from_ms; wire rs_from_ws; wire rt_from_es; wire rt_from_ms; wire rt_from_ws; wire rs_stall; wire rt_stall; wire stall; reg ds_ex_tag; reg ds_inst_ADEL; wire ds_exception; wire [ 4:0] excode; wire ex_INT; wire ex_RI; wire es_allowin; wire es_ready_go; wire es_to_ms_valid; reg es_valid; reg [31:0] es_pc; reg [31:0] es_rs_value; reg [31:0] es_rt_value; reg [15:0] es_imm; reg [11:0] es_alu_op; reg es_src1_is_sa; reg es_src1_is_pc; reg es_src2_is_imm; reg es_src2_is_uimm; reg es_src2_is_8; reg es_res_from_mem; reg es_gr_we; reg [ 3:0] es_mul_div; reg es_inst_MFHI; reg es_inst_MFLO; reg es_inst_MTHI; reg es_inst_MTLO; reg es_inst_MTC0; reg es_inst_MFC0; reg es_inst_ERET; reg es_inst_BRANCH; reg [ 4:0] es_dest; reg [ 6:0] es_load_mask; reg [ 4:0] es_save_mask; wire [ 4:0] mem_we; wire [31:0] mem_wdata; wire [63:0] mul_result; wire div_done; wire [63:0] div_result; wire [31:0] alu_src1; wire [31:0] alu_src2; wire [31:0] alu_result; wire es_exception; reg [ 7:0] es_cp0_addr; reg [ 4:0] es_excode; reg es_ex_tag; reg es_ex_occur; reg es_inst_ADEL; reg es_ov_add; reg es_ov_sub; wire ex_data_ADEL; (*mark_debug = "true"*)wire ex_data_ADES; wire ex_OV; wire cp0_ren; wire cp0_wen; wire [ 7:0] cp0_addr; wire [ 7:0] cp0_raddr; wire [ 7:0] cp0_waddr; wire [31:0] cp0_wr_value; wire [31:0] cp0_rd_value; wire ms_allowin; wire ms_ready_go; wire ms_to_ws_valid; reg ms_valid; reg [31:0] ms_pc; reg [ 4:0] ms_dest; reg [ 6:0] ms_load_mask; reg [ 4:0] ms_save_mask; reg ms_res_from_mem; reg ms_gr_we; reg [31:0] ms_final_result; reg [ 3:0] ms_mul_div; reg [63:0] ms_div_result; reg ms_inst_MTHI; reg ms_inst_MTLO; reg [31:0] ms_data_addr; reg ms_data_data_ok; reg [31:0] ms_data; reg [31:0] ms_rt_value; reg ms_inst_BRANCH; wire [31:0] mem_result; wire [31:0] mask_result; wire [31:0] final_result; reg ms_ex_tag; wire ws_allowin; wire ws_ready_go; reg ws_valid; reg [31:0] ws_pc; reg ws_gr_we; reg [ 4:0] ws_dest; reg [31:0] ws_final_result; wire rf_we; wire [ 4:0] rf_waddr; wire [31:0] rf_wdata; reg [31:0] HI; reg [31:0] LO; wire [31:0] next_HI; wire [31:0] next_LO; reg ws_ex_tag; wire exception_commit; wire set_ex_tag; wire [ 5:0] exe_excode; reg [31:0] cr_badvaddr; wire [31:0] badvaddr_value; assign badvaddr_value = cr_badvaddr; reg [31:0] cr_count; wire [31:0] count_value; assign count_value = cr_count; reg [31:0] cr_compare; wire [31:0] compare_value; assign compare_value = cr_compare; wire cr_status_BEV; reg cr_status_IM7; reg cr_status_IM6; reg cr_status_IM5; reg cr_status_IM4; reg cr_status_IM3; reg cr_status_IM2; reg cr_status_IM1; reg cr_status_IM0; reg cr_status_EXL; reg cr_status_IE; assign cr_status_BEV = 1'b1; wire [31:0] status_value; assign status_value = { 9'b0, cr_status_BEV, 6'b0, cr_status_IM7, cr_status_IM6, cr_status_IM5, cr_status_IM4, cr_status_IM3, cr_status_IM2, cr_status_IM1, cr_status_IM0, 6'b0, cr_status_EXL, cr_status_IE }; reg cr_cause_BD; reg cr_cause_TI; reg cr_cause_IP7; reg cr_cause_IP6; reg cr_cause_IP5; reg cr_cause_IP4; reg cr_cause_IP3; reg cr_cause_IP2; reg cr_cause_IP1; reg cr_cause_IP0; reg [4:0] cr_cause_ExcCode; wire [31:0] cause_value; assign cause_value = { cr_cause_BD, cr_cause_TI, 14'b0, cr_cause_IP7, cr_cause_IP6, cr_cause_IP5, cr_cause_IP4, cr_cause_IP3, cr_cause_IP2, cr_cause_IP1, cr_cause_IP0, 1'b0, cr_cause_ExcCode, 2'b00 }; reg [31:0] cr_epc; wire [31:0] epc_value; assign epc_value = cr_epc; assign to_fs_valid = ~reset; /; ds_pc <= fs_pc; ds_inst <= fs_inst; end else if(set_ex_tag & !es_inst_ERET) ds_ex_reg <= 1'b1; end assign op = ds_inst[31:26]; assign rs = ds_inst[25:21]; assign rt = ds_inst[20:16]; assign rd = ds_inst[15:11]; assign sa = ds_inst[10: 6]; assign func = ds_inst[ 5: 0]; assign imm = ds_inst[15: 0]; assign jidx = ds_inst[25: 0]; assign sel = ds_inst[ 2: 0]; decoder_6_64 u_dec0(.in(op ), .out(op_d )); decoder_6_64 u_dec1(.in(func), .out(func_d)); decoder_5_32 u_dec2(.in(rs ), .out(rs_d )); decoder_5_32 u_dec3(.in(rt ), .out(rt_d )); decoder_5_32 u_dec4(.in(rd ), .out(rd_d )); decoder_5_32 u_dec5(.in(sa ), .out(sa_d )); assign inst_ADDU = op_d[6'h00] & func_d[6'h21] & sa_d[5'h00]; assign inst_SUBU = op_d[6'h00] & func_d[6'h23] & sa_d[5'h00]; assign inst_SLT = op_d[6'h00] & func_d[6'h2a] & sa_d[5'h00]; assign inst_SLTU = op_d[6'h00] & func_d[6'h2b] & sa_d[5'h00]; assign inst_AND = op_d[6'h00] & func_d[6'h24] & sa_d[5'h00]; assign inst_OR = op_d[6'h00] & func_d[6'h25] & sa_d[5'h00]; assign inst_XOR = op_d[6'h00] & func_d[6'h26] & sa_d[5'h00]; assign inst_NOR = op_d[6'h00] & func_d[6'h27] & sa_d[5'h00]; assign inst_SLL = op_d[6'h00] & func_d[6'h00] & rs_d[5'h00]; assign inst_SRL = op_d[6'h00] & func_d[6'h02] & rs_d[5'h00]; assign inst_SRA = op_d[6'h00] & func_d[6'h03] & rs_d[5'h00]; assign inst_ADDIU = op_d[6'h09]; assign inst_LUI = op_d[6'h0f] & rs_d[5'h00]; assign inst_LW = op_d[6'h23]; assign inst_SW = op_d[6'h2b]; assign inst_BEQ = op_d[6'h04]; assign inst_BNE = op_d[6'h05]; assign inst_JAL = op_d[6'h03]; assign inst_JR = op_d[6'h00] & func_d[6'h08] & rt_d[5'h00] & rd_d[5'h00] & sa_d[5'h00]; assign inst_ADD = op_d[6'h00] & func_d[6'h20] & sa_d[5'h00]; assign inst_ADDI = op_d[6'h08]; assign inst_SUB = op_d[6'h00] & func_d[6'h22] & sa_d[5'h00]; assign inst_SLTI = op_d[6'h0a]; assign inst_SLTIU = op_d[6'h0b]; assign inst_ANDI = op_d[6'h0c]; assign inst_ORI = op_d[6'h0d]; assign inst_XORI = op_d[6'h0e]; assign inst_SLLV = op_d[6'h00] & func_d[6'h04] & sa_d[5'h00]; assign inst_SRAV = op_d[6'h00] & func_d[6'h07] & sa_d[5'h00]; assign inst_SRLV = op_d[6'h00] & func_d[6'h06] & sa_d[5'h00]; assign inst_DIV = op_d[6'h00] & func_d[6'h1a] & sa_d[5'h00] & rd_d[5'h00]; assign inst_DIVU = op_d[6'h00] & func_d[6'h1b] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MULT = op_d[6'h00] & func_d[6'h18] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MULTU = op_d[6'h00] & func_d[6'h19] & sa_d[5'h00] & rd_d[5'h00]; assign inst_MFHI = op_d[6'h00] & func_d[6'h10] & sa_d[5'h00] & rs_d[5'h00] & rt_d[5'h00]; assign inst_MFLO = op_d[6'h00] & func_d[6'h12] & sa_d[5'h00] & rs_d[5'h00] & rt_d[5'h00]; assign inst_MTHI = op_d[6'h00] & func_d[6'h11] & sa_d[5'h00] & rt_d[5'h00] & rd_d[5'h00]; assign inst_MTLO = op_d[6'h00] & func_d[6'h13] & sa_d[5'h00] & rt_d[5'h00] & rd_d[5'h00]; assign inst_J = op_d[6'h02]; assign inst_BGEZ = op_d[6'h01] & rt_d[5'h01]; assign inst_BGTZ = op_d[6'h07] & rt_d[5'h00]; assign inst_BLEZ = op_d[6'h06] & rt_d[5'h00]; assign inst_BLTZ = op_d[6'h01] & rt_d[5'h00]; assign inst_BLTZAL = op_d[6'h01] & rt_d[5'h10]; assign inst_BGEZAL = op_d[6'h01] & rt_d[5'h11]; assign inst_JALR = op_d[6'h00] & func_d[6'h09] & sa_d[5'h00] & rt_d[5'h00]; assign inst_LB = op_d[6'h20]; assign inst_LBU = op_d[6'h24]; assign inst_LH = op_d[6'h21]; assign inst_LHU = op_d[6'h25]; assign inst_LWL = op_d[6'h22]; assign inst_LWR = op_d[6'h26]; assign inst_SB = op_d[6'h28]; assign inst_SH = op_d[6'h29]; assign inst_SWL = op_d[6'h2a]; assign inst_SWR = op_d[6'h2e]; assign inst_ERET = op_d[6'h10] & func_d[6'h18]&rs_d[5'h10]&rt_d[5'h00]&rd_d[5'h00]&sa_d[5'h00]; assign inst_MFC0 = op_d[6'h10] & (func[5:3]==3'b0) & rs_d[5'h00] & sa_d[5'h00]; assign inst_MTC0 = op_d[6'h10] & (func[5:3]==3'b0) & rs_d[5'h04] & sa_d[5'h00]; assign inst_BREAK = op_d[6'h00] & func_d[6'h0d]; assign inst_SYSCALL= op_d[6'h00] & func_d[6'h0c]; assign alu_op[ 0] = inst_ADD | inst_ADDU | inst_ADDI | inst_ADDIU | inst_LW | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SW | inst_SB | inst_SH | inst_SWL | inst_SWR | inst_JAL | inst_BLTZAL | inst_BGEZAL | inst_JALR; assign alu_op[ 1] = inst_SUB | inst_SUBU | inst_BEQ | inst_BNE ; assign alu_op[ 2] = inst_SLT | inst_SLTI; assign alu_op[ 3] = inst_SLTU | inst_SLTIU; assign alu_op[ 4] = inst_AND | inst_ANDI; assign alu_op[ 5] = inst_NOR; assign alu_op[ 6] = inst_OR | inst_ORI | inst_MTHI | inst_MTLO; assign alu_op[ 7] = inst_XOR | inst_XORI; assign alu_op[ 8] = inst_SLL | inst_SLLV; assign alu_op[ 9] = inst_SRL | inst_SRLV; assign alu_op[10] = inst_SRA | inst_SRAV; assign alu_op[11] = inst_LUI; assign src1_is_sa = inst_SLL | inst_SRL | inst_SRA; assign src1_is_pc = inst_JAL | inst_JALR | inst_BLTZAL | inst_BGEZAL; assign src2_is_imm = inst_LUI | inst_LW | inst_SW | inst_ADDI | inst_ADDIU | inst_SLTI | inst_SLTIU | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SB | inst_SH | inst_SW | inst_SWR | inst_SWL; assign src2_is_uimm = inst_ORI | inst_ANDI | inst_XORI; assign src2_is_8 = inst_JAL | inst_JALR | inst_BLTZAL | inst_BGEZAL; assign res_from_mem = inst_LW | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR; assign dst_is_r31 = inst_JAL | inst_BLTZAL | inst_BGEZAL; assign dst_is_rt = inst_LUI | inst_LW | inst_ADDIU | inst_ORI | inst_ANDI | inst_XORI | inst_ADDI | inst_SLTI | inst_SLTIU | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_MFC0; assign gr_we = ~inst_SW & ~inst_BEQ & ~inst_BNE & ~inst_JR & ~inst_DIV & ~inst_DIVU & ~inst_MULT & ~inst_MULTU & ~inst_MTHI & ~inst_MTLO & ~inst_J & ~inst_BGEZ & ~inst_BGTZ & ~inst_BLEZ & ~inst_BLTZ & ~inst_SB & ~inst_SH & ~inst_SWL & ~inst_SWR & ~inst_MTC0 & ~inst_ERET & ~inst_SYSCALL & ~inst_BREAK; assign not_read_rs = inst_JAL | inst_J | inst_MFC0 | inst_MTC0 | inst_ERET | inst_BREAK | inst_SYSCALL; assign not_read_rt = inst_LUI | inst_ADDIU | inst_LW | inst_JAL | inst_ADDI | inst_SLTI | inst_SLTIU | inst_ANDI | inst_ORI | inst_XORI | inst_J | inst_BGEZ | inst_BLTZAL | inst_BGEZAL | inst_LB | inst_LBU |inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_MFC0 | inst_ERET | inst_BREAK | inst_SYSCALL; assign mul_div = {inst_MULT, inst_MULTU, inst_DIV, inst_DIVU}; assign dest = dst_is_r31 ? 5'd31 : dst_is_rt ? rt : rd; assign load_mask = {inst_LW, inst_LH, inst_LHU, inst_LB, inst_LBU, inst_LWL, inst_LWR}; assign save_mask = {inst_SW, inst_SH, inst_SB, inst_SWL, inst_SWR}; assign inst_BRANCH = inst_BEQ | inst_BNE | inst_BGEZ | inst_BGEZAL | inst_BLTZ | inst_BLTZAL | inst_BGTZ | inst_BLEZ| inst_JAL | inst_JALR | inst_JR | inst_J; assign rs_from_es = (!not_read_rs) && (rs != 5'b0) && (rs == es_dest) && es_gr_we && (!inst_BRANCH) && (!es_res_from_mem) && (!es_inst_MFHI) && (!es_inst_MFLO) &&(!es_inst_MFC0) && (!es_ex_tag) && es_ready_go; assign rs_from_ms = (!not_read_rs) && (rs != 5'b0) && (rs == ms_dest) && ms_gr_we && (!inst_BRANCH) && (!ms_ex_tag) && ms_ready_go; assign rs_from_ws = (!not_read_rs) && (rs != 5'b0) && (rs == ws_dest) && ws_gr_we && (!inst_BRANCH) && (!ws_ex_tag) && ws_ready_go; assign rt_from_es = (!not_read_rt) && (rt != 5'b0) && (rt == es_dest) && es_gr_we && (!inst_BRANCH) && (!es_res_from_mem) && (!es_inst_MFHI) && (!es_inst_MFLO) &&(!es_inst_MFC0) && (!es_ex_tag) && es_ready_go; assign rt_from_ms = (!not_read_rt) && (rt != 5'b0) && (rt == ms_dest) && ms_gr_we && (!inst_BRANCH) && (!ms_ex_tag) && ms_ready_go; assign rt_from_ws = (!not_read_rt) && (rt != 5'b0) && (rt == ws_dest) && ws_gr_we && (!inst_BRANCH) && (!ws_ex_tag) && ws_ready_go; assign rs_stall = (not_read_rs || rs == 5'b0 || rs_from_es || rs_from_ms || rs_from_ws) ? 1'b0 : (rs == es_dest || rs == ms_dest || rs == ws_dest); assign rt_stall = (not_read_rt || rt == 5'b0 || rt_from_es || rt_from_ms || rt_from_ws) ? 1'b0 : (rt == es_dest || rt == ms_dest || rt == ws_dest); assign stall = (rs_stall || rt_stall) & !set_ex_tag; assign rf_raddr1 = rs; assign rf_raddr2 = rt; regfile u_regfile( .clk (clk ), .raddr1 (rf_raddr1), .rdata1 (rf_rdata1), .raddr2 (rf_raddr2), .rdata2 (rf_rdata2), .we (rf_we ), .waddr (rf_waddr ), .wdata (rf_wdata ) ); assign rs_value = rs_from_es ? alu_result : rs_from_ms ? final_result : rs_from_ws ? ws_final_result : rf_rdata1; assign rt_value = rt_from_es ? alu_result : rt_from_ms ? final_result : rt_from_ws ? ws_final_result : rf_rdata2; assign rs_eq_rt = (rf_rdata1 == rf_rdata2); assign rs_zero = ~(|rf_rdata1); assign rs_gez = rs_zero | !rf_rdata1[31]; assign rs_gtz = !rs_zero & !rf_rdata1[31]; assign rs_lez = rs_zero | rf_rdata1[31]; assign rs_ltz = !rs_zero & rf_rdata1[31]; assign br_taken = ( rs_eq_rt && inst_BEQ || !rs_eq_rt && inst_BNE || rs_gez && (inst_BGEZ | inst_BGEZAL) || rs_ltz && (inst_BLTZ | inst_BLTZAL) || rs_gtz && inst_BGTZ || rs_lez && inst_BLEZ || inst_JAL || inst_JALR || inst_JR || inst_J )&& !ds_ex_tag; assign br_target = (inst_JAL || inst_J) ? ({fs_pc[31:28], jidx[25:0], 2'b0}) : (inst_JR || inst_JALR) ? rf_rdata1 : fs_pc + {{14{imm[15]}}, imm[15:0], 2'b0}; assign ex_INT = |(cause_value[15:8] & status_value[15:8]); assign ex_RI = !(inst_ADDU | inst_SUBU | inst_SLT | inst_SLTU | inst_AND | inst_OR | inst_XOR | inst_NOR | inst_SLL | inst_SRL | inst_SRA | inst_ADDIU | inst_LUI | inst_LW | inst_SW | inst_BEQ | inst_BNE | inst_JAL | inst_JR | inst_ADD | inst_ADDI | inst_SUB | inst_SLTI | inst_SLTIU | inst_ANDI | inst_ORI | inst_XORI | inst_SLLV | inst_SRAV | inst_SRLV | inst_DIV | inst_DIVU | inst_MULT | inst_MULTU | inst_MFHI | inst_MFLO | inst_MTHI | inst_MTLO | inst_J | inst_BGEZ | inst_BGTZ | inst_BLEZ | inst_BLTZ | inst_BLTZAL| inst_BGEZAL| inst_JALR | inst_LB | inst_LBU | inst_LH | inst_LHU | inst_LWL | inst_LWR | inst_SB | inst_SH | inst_SWL | inst_SWR | inst_ERET | inst_MFC0 | inst_MTC0 | inst_BREAK | inst_SYSCALL); assign excode = ex_INT ? 6'h00 : ex_RI ? 6'h0a : inst_SYSCALL ? 6'h08 : inst_BREAK ? 6'h09 : 6'h00 ; assign ds_exception = inst_SYSCALL | inst_BREAK | ex_RI | ex_INT; reg es_ex_reg; assign es_ready_go = (es_mul_div[1:0] == 2'b0 | es_ex_tag) ? 1'b1 : div_done; assign es_allowin = !es_valid || es_ready_go && ms_allowin; assign es_to_ms_valid = es_valid && es_ready_go || stall; always @(posedge clk) begin if (reset) begin es_valid <= 1'b0; es_mul_div <= 4'b0; es_ex_tag <= 1'b0; es_ex_reg <= 1'b0; es_ex_occur <= 1'b0; es_inst_ADEL <= 1'b0; end else if (es_allowin) begin es_valid <= ds_to_es_valid; end if(set_ex_tag & !(ds_to_es_valid && es_allowin)) es_ex_reg <= 1'b1; if (stall & !es_valid) begin es_res_from_mem <= 1'b0; es_gr_we <= 1'b0; es_dest <= 5'b0; end else if (ds_to_es_valid && es_allowin) begin es_pc <= ds_pc; es_rs_value <= rs_value; es_rt_value <= rt_value; es_imm <= imm; es_alu_op <= alu_op; es_src1_is_sa <= src1_is_sa; es_src1_is_pc <= src1_is_pc; es_src2_is_imm <= src2_is_imm; es_src2_is_uimm <= src2_is_uimm; es_src2_is_8 <= src2_is_8; es_res_from_mem <= res_from_mem; es_gr_we <= gr_we; es_dest <= gr_we ? dest : 5'b0; es_load_mask <= load_mask; es_save_mask <= save_mask; es_mul_div <= mul_div; es_inst_MFHI <= inst_MFHI; es_inst_MFLO <= inst_MFLO; es_inst_MTHI <= inst_MTHI; es_inst_MTLO <= inst_MTLO; es_inst_MTC0 <= inst_MTC0; es_inst_MFC0 <= inst_MFC0; es_inst_ERET <= inst_ERET; es_inst_BRANCH <= inst_BRANCH; es_excode <= excode; es_ex_occur <= ds_exception; es_inst_ADEL <= ds_inst_ADEL; es_cp0_addr <= {rd, sel}; es_ov_add <= inst_ADD | inst_ADDI; es_ov_sub <= inst_SUB; if(es_ex_reg || set_ex_tag) begin es_ex_tag <= 1'b1; es_ex_reg <= 1'b0; end else begin es_ex_tag <= ds_ex_tag; end end end assign alu_src1 = es_src1_is_sa ? {27'b0, es_imm[10:6]} : es_src1_is_pc ? es_pc[31:0] : es_rs_value; assign alu_src2 = es_src2_is_imm ? {{16{es_imm[15]}}, es_imm[15:0]} : es_src2_is_uimm ? {16'b0, es_imm[15:0]} : es_src2_is_8 ? 32'd8 : es_rt_value; alu u_alu( .alu_control (es_alu_op ), .alu_src1 (alu_src1 ), .alu_src2 (alu_src2 ), .alu_result (alu_result) ); mul u_mul( .mul_clk (clk), .resetn (resetn), .mul_signed (es_mul_div[3]), .x (es_rs_value), .y (es_rt_value), .result (mul_result) ); div u_div( .div_clk (clk), .resetn (resetn), .div ((es_mul_div[1] | es_mul_div[0]) & !es_ex_tag), .div_signed (es_mul_div[1]), .x (es_rs_value), .y (es_rt_value), .s (div_result[63:32]), .r (div_result[31: 0]), .complete (div_done) ); assign ex_OV = (~alu_src1[31]&~alu_src2[31]& alu_result[31] | alu_src1[31]& alu_src2[31]&~alu_result[31] ) & es_ov_add | (~alu_src1[31]& alu_src2[31]& alu_result[31] | alu_src1[31]&~alu_src2[31]&~alu_result[31] ) & es_ov_sub ; assign ex_data_ADES = (es_save_mask[4] & (alu_result[1] | alu_result[0])) | (es_save_mask[3] & alu_result[0]); assign ex_data_ADEL = (es_load_mask[6] & (alu_result[1] | alu_result[0])) | ((es_load_mask[5] | es_load_mask[4]) & alu_result[0]); assign es_exception = ex_data_ADEL | ex_data_ADES | ex_OV | es_ex_occur | es_inst_ADEL; assign exe_excode = (es_excode==6'h00 & es_ex_occur) ? 6'h00 : es_inst_ADEL ? 6'h04 : ex_OV ? 6'h0c : ex_data_ADEL ? 6'h04 : ex_data_ADES ? 6'h05 : es_excode ; reg ms_ex_reg; (*mark_debug = "true"*)reg [2:0] ms_state; reg [2:0] ms_next_state; assign ms_ready_go = ms_state == 3'b000; assign ms_allowin = !ms_valid || ms_ready_go && ws_allowin; assign ms_to_ws_valid = ms_valid && ms_ready_go; always @(posedge clk) begin if (reset) begin ms_valid <= 1'b0; ms_ex_tag <= 1'b0; ms_ex_reg <= 1'b0; ms_data_data_ok <= 1'b1; end else if (ms_allowin) begin ms_valid <= es_to_ms_valid; end ms_data_data_ok <= data_data_ok; if(data_data_ok) ms_data <= data_rdata; if (es_to_ms_valid && ms_allowin) begin ms_pc <= es_pc; ms_gr_we <= es_gr_we; ms_dest <= es_dest; ms_load_mask <= es_load_mask; ms_save_mask <= es_save_mask; ms_final_result <= es_inst_MFHI ? next_HI : es_inst_MFLO ? next_LO : es_inst_MFC0 ? cp0_rd_value : alu_result; ms_res_from_mem <= es_res_from_mem; ms_mul_div <= es_mul_div; ms_div_result <= div_result; ms_inst_MTHI <= es_inst_MTHI; ms_inst_MTLO <= es_inst_MTLO; ms_rt_value <= es_rt_value; ms_inst_BRANCH <= es_inst_BRANCH; if(ms_ex_reg || set_ex_tag) begin ms_ex_tag <= 1'b1; ms_ex_reg <= 1'b0; end else begin ms_ex_tag <= es_ex_tag; end end else if(set_ex_tag) ms_ex_reg <= 1'b1; end wire write_twice; wire [1 :0] w1_size; wire [31:0] w1_addr; wire [1 :0] w2_size; wire [31:0] w2_addr; assign write_twice = (ms_save_mask[1] & (ms_final_result[1:0]==2'b10)) | (ms_save_mask[0] & (ms_final_result[1:0]==2'b01)); assign w1_size = ms_save_mask[4] ? 2'b10 : ms_save_mask[3] & (ms_final_result[1:0]==2'b00) ? 2'b01 : ms_save_mask[3] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[2] & (ms_final_result[1:0]==2'b00) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b01) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b10) ? 2'b00 : ms_save_mask[2] & (ms_final_result[1:0]==2'b11) ? 2'b00 : ms_save_mask[1] & (ms_final_result[1:0]==2'b00) ? 2'b00 : ms_save_mask[1] & (ms_final_result[1:0]==2'b01) ? 2'b01 : ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[1] & (ms_final_result[1:0]==2'b11) ? 2'b10 : ms_save_mask[0] & (ms_final_result[1:0]==2'b00) ? 2'b10 : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? 2'b00 : ms_save_mask[0] & (ms_final_result[1:0]==2'b10) ? 2'b01 : ms_save_mask[0] & (ms_final_result[1:0]==2'b11) ? 2'b00 : 2'b11; assign w1_addr = ms_save_mask[1] ? {ms_final_result[31:2], 2'b00} : ms_final_result; assign w2_size = ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? 2'b00 : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? 2'b01 : 2'b11; assign w2_addr = ms_save_mask[0] ? {ms_final_result[31:2], 2'b10} : ms_final_result; assign mem_wdata = ms_save_mask[4] ? ms_rt_value : ms_save_mask[3] & (ms_final_result[1:0]==2'b00) ? {16'b0, ms_rt_value[15: 0]} : ms_save_mask[3] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[15: 0], 16'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b00) ? {24'b0, ms_rt_value[ 7: 0]} : ms_save_mask[2] & (ms_final_result[1:0]==2'b01) ? {16'b0, ms_rt_value[ 7: 0], 8'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b10) ? { 8'b0, ms_rt_value[ 7: 0], 16'b0} : ms_save_mask[2] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[ 7: 0], 24'b0} : ms_save_mask[1] & (ms_final_result[1:0]==2'b00) ? {24'b0, ms_rt_value[31:24]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b01) ? {16'b0, ms_rt_value[31:16]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b10) ? { 8'b0, ms_rt_value[31: 8]} : ms_save_mask[1] & (ms_final_result[1:0]==2'b11) ? ms_rt_value : ms_save_mask[0] & (ms_final_result[1:0]==2'b00) ? ms_rt_value : ms_save_mask[0] & (ms_final_result[1:0]==2'b01) ? {ms_rt_value[23: 0], 8'b0} : ms_save_mask[0] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[15: 0], 16'b0} : ms_save_mask[0] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[ 7: 0], 24'b0} : 32'b0; assign mem_result = data_rdata; assign mask_result = ms_load_mask[6] ? mem_result[31:0] : ms_load_mask[5] & (ms_final_result[1:0]==2'b00) ? {{16{mem_result[15]}}, mem_result[15: 0]} : ms_load_mask[5] & (ms_final_result[1:0]==2'b10) ? {{16{mem_result[31]}}, mem_result[31:16]} : ms_load_mask[4] & (ms_final_result[1:0]==2'b00) ? {16'b0, mem_result[15:0]} : ms_load_mask[4] & (ms_final_result[1:0]==2'b10) ? {16'b0, mem_result[31:16]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b00) ? {{24{mem_result[ 7]}}, mem_result[ 7: 0]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b01) ? {{24{mem_result[15]}}, mem_result[15: 8]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b10) ? {{24{mem_result[23]}}, mem_result[23:16]} : ms_load_mask[3] & (ms_final_result[1:0]==2'b11) ? {{24{mem_result[31]}}, mem_result[31:24]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b00) ? {24'b0, mem_result[ 7: 0]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b01) ? {24'b0, mem_result[15: 8]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b10) ? {24'b0, mem_result[23:16]} : ms_load_mask[2] & (ms_final_result[1:0]==2'b11) ? {24'b0, mem_result[31:24]} : ms_load_mask[1] & (ms_final_result[1:0]==2'b00) ? {mem_result[ 7: 0], ms_rt_value[23: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b01) ? {mem_result[15: 0], ms_rt_value[15: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b10) ? {mem_result[23: 0], ms_rt_value[ 7: 0]}: ms_load_mask[1] & (ms_final_result[1:0]==2'b11) ? {mem_result[31: 0]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b00) ? {mem_result[31: 0]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b01) ? {ms_rt_value[31:24], mem_result[31: 8]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b10) ? {ms_rt_value[31:16], mem_result[31:16]}: ms_load_mask[0] & (ms_final_result[1:0]==2'b11) ? {ms_rt_value[31: 8], mem_result[31:24]}: 32'b0; wire inst_LOAD = |es_load_mask; wire inst_STORE = |es_save_mask; assign data_req = ms_valid & (ms_state==3'b001 || ms_state==3'b011); assign data_wr = |ms_save_mask & data_req; assign data_size = |ms_load_mask ? 2'b10 : ms_state==3'b011 ? w2_size : w1_size; assign data_addr = |ms_load_mask ? ms_final_result : ms_state==3'b011 ? w2_addr : w1_addr; assign data_wdata = mem_wdata; assign final_result = ms_res_from_mem ? mask_result : ms_final_result; always @(posedge clk) begin if (reset) ms_state <= 3'b000; else ms_state <= ms_next_state; end always @(*) begin if(ms_state == 3'b000 & es_to_ms_valid & ms_allowin & (inst_LOAD|inst_STORE) & !es_ex_tag & !(ex_data_ADEL | ex_data_ADES | ex_OV)) ms_next_state <= 3'b001; else if(ms_state == 3'b001 & data_addr_ok) ms_next_state <= 3'b010; else if(ms_state == 3'b010 & data_data_ok & write_twice) ms_next_state <= 3'b011; else if(ms_state == 3'b010 & data_data_ok) ms_next_state <= 3'b000; else if(ms_state == 3'b011 & data_addr_ok) ms_next_state <= 3'b100; else if(ms_state == 3'b100 & data_data_ok) ms_next_state <= 3'b000; else ms_next_state <= ms_state; end assign ws_ready_go = 1'b1; assign ws_allowin = !ws_valid || ws_ready_go; always @(posedge clk) begin if (reset) begin ws_valid <= 1'b0; ws_pc <= 32'b0; ws_ex_tag <= 1'b0; end else if (ws_allowin) begin ws_valid <= ms_to_ws_valid; end if (ms_to_ws_valid && ws_allowin) begin ws_ex_tag <= ms_ex_tag; ws_pc <= ms_pc; ws_gr_we <= ms_gr_we; ws_dest <= ms_dest; ws_final_result <= final_result; HI <= next_HI; LO <= next_LO; end end reg [31:0] last_pc; wire once = (last_pc != ws_pc); always @(posedge clk) begin if (reset) last_pc <= 32'b0; else last_pc <= ws_pc; end assign next_HI = ms_ex_tag ? HI : ms_inst_MTHI ? ms_final_result : ms_mul_div[3:2] != 2'b0 ? mul_result[63:32] : ms_mul_div[1:0] != 2'b0 ? ms_div_result[31: 0] : HI; assign next_LO = ms_ex_tag ? LO : ms_inst_MTLO ? ms_final_result : ms_mul_div[3:2] != 2'b0 ? mul_result[31: 0] : ms_mul_div[1:0] != 2'b0 ? ms_div_result[63:32] : LO; assign rf_we = ws_gr_we && ws_valid && !ws_ex_tag && once; assign rf_waddr = ws_dest; assign rf_wdata = ws_final_result; assign debug_wb_pc = ws_pc; assign debug_wb_rf_wen = {4{rf_we}}; assign debug_wb_rf_wnum = ws_dest; assign debug_wb_rf_wdata = ws_final_result; wire count_cmp_eq; wire timer_int; wire [ 5:0] int_pending; assign set_ex_tag = !es_valid ? 1'b0 : es_inst_ERET ? 1'b1 : (status_value[1] | es_ex_tag) ? 1'b0 : es_exception; assign exception_commit = status_value[1] ? 1'b0 : es_exception; assign count_cmp_eq = cr_compare == cr_count; assign timer_int = cr_cause_TI; assign int_pending[ 5] = hw_int[5] | timer_int; assign int_pending[4:0] = hw_int[4:0]; assign cp0_ren = es_inst_MFC0; assign cp0_wen = es_inst_MTC0 & !es_ex_tag; assign cp0_addr = es_cp0_addr; assign cp0_raddr = es_inst_MFC0 ? cp0_addr : 8'h0; assign cp0_waddr = es_inst_MTC0 ? cp0_addr : 8'h0; assign cp0_wr_value = es_rt_value; assign cp0_rd_value = {32{cp0_raddr=={5'd8 , 3'd0}}} & badvaddr_value | {32{cp0_raddr=={5'd12, 3'd0}}} & status_value | {32{cp0_raddr=={5'd13, 3'd0}}} & cause_value | {32{cp0_raddr=={5'd14, 3'd0}}} & epc_value | {32{cp0_raddr=={5'd9 , 3'd0}}} & count_value | {32{cp0_raddr=={5'd11, 3'd0}}} & compare_value ; reg count_add_en; always @(posedge clk) count_add_en <= reset ? 1'b0 : ~count_add_en; always @(posedge clk) begin if (exception_commit && (exe_excode==6'h04 || exe_excode==6'h05) && (!es_ex_tag || es_inst_ERET)) cr_badvaddr <= (ex_data_ADES | ex_data_ADEL) ? alu_result : es_pc; end always @(posedge clk) begin if (reset) cr_count <= 32'h0; else if (cp0_wen && cp0_waddr=={5'd9, 3'd0}) cr_count <= cp0_wr_value[31:0]; else if (count_add_en) cr_count <= cr_count + 1'b1; end always @(posedge clk) begin if (reset) cr_compare <= 32'h0; else if (cp0_wen && cp0_waddr=={5'd11, 3'd0}) cr_compare <= cp0_wr_value[31:0]; end always @(posedge clk) begin if (reset) begin cr_status_IM7 <= 1'b0; cr_status_IM6 <= 1'b0; cr_status_IM5 <= 1'b0; cr_status_IM4 <= 1'b0; cr_status_IM3 <= 1'b0; cr_status_IM2 <= 1'b0; cr_status_IM1 <= 1'b0; cr_status_IM0 <= 1'b0; cr_status_EXL <= 1'b0; cr_status_IE <= 1'b0; end else begin if (exception_commit) cr_status_EXL <= 1'b1; else if (es_inst_ERET) begin cr_status_EXL <= 1'b0; end else if (cp0_wen && cp0_waddr=={5'd12, 3'd0}) begin cr_status_EXL <= cp0_wr_value[ 1]; end if (cp0_wen && cp0_waddr=={5'd12, 3'd0}) begin cr_status_IM7 <= cp0_wr_value[ 15]; cr_status_IM6 <= cp0_wr_value[ 14]; cr_status_IM5 <= cp0_wr_value[ 13]; cr_status_IM4 <= cp0_wr_value[ 12]; cr_status_IM3 <= cp0_wr_value[ 11]; cr_status_IM2 <= cp0_wr_value[ 10]; cr_status_IM1 <= cp0_wr_value[ 9]; cr_status_IM0 <= cp0_wr_value[ 8]; cr_status_IE <= cp0_wr_value[ 0]; end end end always @(posedge clk) begin if (reset) begin cr_cause_TI <= 1'b0; end else if (cp0_wen && cp0_waddr=={5'd11, 3'd0}) begin cr_cause_TI <= 1'b0; end else if (count_cmp_eq) begin cr_cause_TI <= 1'b1; end end always @(posedge clk) begin if (reset) begin cr_cause_BD <= 1'b0; cr_cause_IP7 <= 1'b0; cr_cause_IP6 <= 1'b0; cr_cause_IP5 <= 1'b0; cr_cause_IP4 <= 1'b0; cr_cause_IP3 <= 1'b0; cr_cause_IP2 <= 1'b0; cr_cause_IP1 <= 1'b0; cr_cause_IP0 <= 1'b0; cr_cause_ExcCode<= 5'h1f; end else begin if (exception_commit) begin cr_cause_ExcCode <= exe_excode[4:0]; if (!cr_status_EXL) cr_cause_BD <= es_inst_ADEL ? 1'b0 : ms_inst_BRANCH; end if (cp0_wen && cp0_waddr=={5'd13, 3'd0}) begin cr_cause_IP1 <= cp0_wr_value[ 9]; cr_cause_IP0 <= cp0_wr_value[ 8]; end cr_cause_IP7 <= int_pending[5]; cr_cause_IP6 <= int_pending[4]; cr_cause_IP5 <= int_pending[3]; cr_cause_IP4 <= int_pending[2]; cr_cause_IP3 <= int_pending[1]; cr_cause_IP2 <= int_pending[0]; end end wire [31:0] epc; always @(posedge clk) begin if (exception_commit && !cr_status_EXL) cr_epc <= epc; else if (cp0_wen && cp0_waddr=={5'd14, 3'd0}) cr_epc <= cp0_wr_value[31:0]; end wire [29:0] pc_w_m4 = es_pc[31:2] - 1'b1; assign epc = (ms_inst_BRANCH & !es_inst_ADEL) ? {pc_w_m4, es_pc[1:0]} : es_pc; endmodule
6
2,572
data/full_repos/permissive/166008742/src/led_driver_shift_reg.v
166,008,742
led_driver_shift_reg.v
v
67
85
[]
['general public license', 'free software foundation']
[]
[(18, 144)]
null
null
1: b'%Error: data/full_repos/permissive/166008742/src/led_driver_shift_reg.v:30: Cannot find include file: globals.vh\n `include "globals.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh\n data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.v\n data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.sv\n globals.vh\n globals.vh.v\n globals.vh.sv\n obj_dir/globals.vh\n obj_dir/globals.vh.v\n obj_dir/globals.vh.sv\n%Error: Exiting due to 1 error(s)\n'
37,524
module
module led_driver_shift_reg #(parameter DATA_WIDTH = 32, parameter SHIFT_WIDTH = 32) ( input clk, input reset, input [DATA_WIDTH-1:0] data_in, input load, input next_bit, output bit_val, output last_bit ); `include "globals.vh" localparam SHIFT_WIDTH_NBITS = clogb2(SHIFT_WIDTH) + 1; reg [SHIFT_WIDTH_NBITS-1:0] cnt; always @(posedge clk or posedge reset) begin if (reset) begin cnt <= 0; end else begin if (load) begin cnt <= SHIFT_WIDTH-1; end else if (next_bit) begin cnt <= cnt - 1; end end end assign last_bit = (cnt == 0); reg [DATA_WIDTH-1:0] data; assign bit_val = data[cnt]; always @(posedge clk or posedge reset) begin if (reset) begin data <= 0; end else begin if (load) begin data <= data_in; end end end endmodule
module led_driver_shift_reg #(parameter DATA_WIDTH = 32, parameter SHIFT_WIDTH = 32) ( input clk, input reset, input [DATA_WIDTH-1:0] data_in, input load, input next_bit, output bit_val, output last_bit );
`include "globals.vh" localparam SHIFT_WIDTH_NBITS = clogb2(SHIFT_WIDTH) + 1; reg [SHIFT_WIDTH_NBITS-1:0] cnt; always @(posedge clk or posedge reset) begin if (reset) begin cnt <= 0; end else begin if (load) begin cnt <= SHIFT_WIDTH-1; end else if (next_bit) begin cnt <= cnt - 1; end end end assign last_bit = (cnt == 0); reg [DATA_WIDTH-1:0] data; assign bit_val = data[cnt]; always @(posedge clk or posedge reset) begin if (reset) begin data <= 0; end else begin if (load) begin data <= data_in; end end end endmodule
0
2,574
data/full_repos/permissive/143278/ivltests/pr522.v
143,278
pr522.v
v
76
81
[]
[]
[]
[(32, 75)]
null
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr522.v:38: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr522.v:43: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr522.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr522.v:55: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr522.v:62: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Error: data/full_repos/permissive/143278/ivltests/pr522.v:65: Unsupported: wait statements\n wait (fred);\n ^~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
22,065
module
module top; integer loop_cntr, simple_fail, loop_fail; reg fred, abort; initial begin #1; simple_fail = 0; loop_fail = 0; fred = 0; abort = 1; #4; fred = 1; #4 if(simple_fail) $display("\n***** simple block disable FAILED *****"); else $display("\n***** simple block disable PASSED *****"); if(loop_fail) $display("***** complex block & loop disable FAILED *****\n"); else $display("***** complex block & loop disable PASSED *****\n"); $finish(0); end initial begin: block_name #2; disable block_name; simple_fail = 1; end initial begin #2; begin: configloop for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin wait (fred); if (abort) begin disable configloop; end loop_fail = 1; end end if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); end endmodule
module top;
integer loop_cntr, simple_fail, loop_fail; reg fred, abort; initial begin #1; simple_fail = 0; loop_fail = 0; fred = 0; abort = 1; #4; fred = 1; #4 if(simple_fail) $display("\n***** simple block disable FAILED *****"); else $display("\n***** simple block disable PASSED *****"); if(loop_fail) $display("***** complex block & loop disable FAILED *****\n"); else $display("***** complex block & loop disable PASSED *****\n"); $finish(0); end initial begin: block_name #2; disable block_name; simple_fail = 1; end initial begin #2; begin: configloop for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin wait (fred); if (abort) begin disable configloop; end loop_fail = 1; end end if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); end endmodule
110
2,575
data/full_repos/permissive/483776248/Vision/EEE2Rover_ah2719/DE10_LITE_D8M_VIP_16/db/ip/Qsys/submodules/Qsys_sw.v
483,776,248
Qsys_sw.v
v
60
73
[]
[]
['all rights reserved']
[(21, 58)]
null
null
1: b'%Warning-WIDTH: data/full_repos/permissive/483776248/Vision/EEE2Rover_ah2719/DE10_LITE_D8M_VIP_16/db/ip/Qsys/submodules/Qsys_sw.v:52: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'read_mux_out\' generates 10 bits.\n : ... In instance Qsys_sw\n readdata <= {32\'b0 | read_mux_out};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
240,641
module
module Qsys_sw ( address, clk, in_port, reset_n, readdata ) ; output [ 31: 0] readdata; input [ 1: 0] address; input clk; input [ 9: 0] in_port; input reset_n; wire clk_en; wire [ 9: 0] data_in; wire [ 9: 0] read_mux_out; reg [ 31: 0] readdata; assign clk_en = 1; assign read_mux_out = {10 {(address == 0)}} & data_in; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= {32'b0 | read_mux_out}; end assign data_in = in_port; endmodule
module Qsys_sw ( address, clk, in_port, reset_n, readdata ) ;
output [ 31: 0] readdata; input [ 1: 0] address; input clk; input [ 9: 0] in_port; input reset_n; wire clk_en; wire [ 9: 0] data_in; wire [ 9: 0] read_mux_out; reg [ 31: 0] readdata; assign clk_en = 1; assign read_mux_out = {10 {(address == 0)}} & data_in; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= {32'b0 | read_mux_out}; end assign data_in = in_port; endmodule
0
2,576
data/full_repos/permissive/364057178/ch_unit/src/bramController.sv
364,057,178
bramController.sv
sv
271
152
[]
[]
[]
null
line:57: before: ":"
null
1: b"%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:2: Expecting include filename. Found: SYMBOL\n`include dataSizes.sv \n ^~~~~~~~~\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:3: Expecting include filename. Found: SYMBOL\n`include dataTypes.sv \n ^~~~~~~~~\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:2: syntax error, unexpected '.'\n .sv\n ^\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:57: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import dataTypes_pkg::*;\n ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
170,928
module
module bramController #( parameter integer BRAM_ADDR_SIZE = 15, parameter integer BRAM_DATA_SIZE = 32, parameter integer BRAM_DEPTH = 32768 ) ( input clk, input resetN, input logic advanceBuffer, input logic clear, input logic [15:0] requestAddr, input logic [15:0] numReads, output logic [BRAM_DATA_SIZE - 1: 0] requestData, output logic dataValid, input logic [BRAM_DATA_SIZE - 1: 0] readData, input logic resetBusy, output logic [BRAM_ADDR_SIZE - 1 : 0] addr, output logic [BRAM_DATA_SIZE - 1 : 0] writeData, output logic bramEnable, output logic bramWe ); import dataTypes_pkg::*; typedef enum logic [3:0] {s_init, s_fifoReset, s_req, s_wait[0:3], s_insertInc, s_hold} bramControl_t; logic clearFIFO; logic read; logic wr_en; logic rd_rst_busy; logic wr_rst_busy; bramControl_t currState, nextState; logic wrAddr; logic wrNumReads; logic incAddr; logic incI; logic [15:0] i; logic [15:0] storedReads; oneshot readOS(.*, .pulse(advanceBuffer) , .oneshot(read)); always_comb begin clearFIFO = ~clear | ~resetN; end always_ff @(posedge clk) begin if(wrAddr) begin addr <= requestAddr; end else begin if(incAddr) begin addr <= addr + 1; end else begin addr <= addr; end end end always_ff @(posedge clk) begin if(wrNumReads) begin storedReads <= numReads; end else begin storedReads <= storedReads; end end always_ff @(posedge clk) begin if(clearFIFO) begin i <= 0; end else begin if(incI) begin i <= i + 1; end else begin i <= i; end end end always_ff @(posedge clk) begin if(!resetN || !clear) begin currState <= s_init; end else begin currState <= nextState; end end always_comb begin unique case(currState) s_init:begin if(resetN) begin nextState = currState.next; end else begin nextState = currState.first; end end s_fifoReset:begin if(wr_rst_busy || rd_rst_busy) begin nextState = currState; end else begin nextState = currState.next; end end s_req,s_wait0,s_wait1,s_wait2,s_wait3:begin nextState = currState.next; end s_insertInc:begin if(i < storedReads) begin nextState = s_req; end else begin nextState = s_hold; end end s_hold: begin if(clear) begin nextState = currState; end else begin nextState = s_fifoReset; end end endcase end always_comb begin unique case(currState) s_init: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00110000; s_fifoReset: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000000; s_req,s_wait0,s_wait1,s_wait2: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000010; s_wait3: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000011; s_insertInc: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00001100; s_hold: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b01110000; endcase end xpm_fifo_sync #( .DOUT_RESET_VALUE("0"), .ECC_MODE("no_ecc"), .FIFO_MEMORY_TYPE("distributed"), .FIFO_READ_LATENCY(1), .FIFO_WRITE_DEPTH(256), .FULL_RESET_VALUE(0), .READ_DATA_WIDTH(32), .READ_MODE("fwft"), .SIM_ASSERT_CHK(0), .USE_ADV_FEATURES("0000"), .WAKEUP_TIME(0), .WRITE_DATA_WIDTH(32) ) xpm_fifo_sync_inst ( .dout(requestData), .rd_rst_busy(rd_rst_busy), .wr_rst_busy(wr_rst_busy), .din(readData), .rd_en(read), .rst(clearFIFO), .wr_clk(clk), .wr_en(wr_en) ); endmodule
module bramController #( parameter integer BRAM_ADDR_SIZE = 15, parameter integer BRAM_DATA_SIZE = 32, parameter integer BRAM_DEPTH = 32768 ) ( input clk, input resetN, input logic advanceBuffer, input logic clear, input logic [15:0] requestAddr, input logic [15:0] numReads, output logic [BRAM_DATA_SIZE - 1: 0] requestData, output logic dataValid, input logic [BRAM_DATA_SIZE - 1: 0] readData, input logic resetBusy, output logic [BRAM_ADDR_SIZE - 1 : 0] addr, output logic [BRAM_DATA_SIZE - 1 : 0] writeData, output logic bramEnable, output logic bramWe );
import dataTypes_pkg::*; typedef enum logic [3:0] {s_init, s_fifoReset, s_req, s_wait[0:3], s_insertInc, s_hold} bramControl_t; logic clearFIFO; logic read; logic wr_en; logic rd_rst_busy; logic wr_rst_busy; bramControl_t currState, nextState; logic wrAddr; logic wrNumReads; logic incAddr; logic incI; logic [15:0] i; logic [15:0] storedReads; oneshot readOS(.*, .pulse(advanceBuffer) , .oneshot(read)); always_comb begin clearFIFO = ~clear | ~resetN; end always_ff @(posedge clk) begin if(wrAddr) begin addr <= requestAddr; end else begin if(incAddr) begin addr <= addr + 1; end else begin addr <= addr; end end end always_ff @(posedge clk) begin if(wrNumReads) begin storedReads <= numReads; end else begin storedReads <= storedReads; end end always_ff @(posedge clk) begin if(clearFIFO) begin i <= 0; end else begin if(incI) begin i <= i + 1; end else begin i <= i; end end end always_ff @(posedge clk) begin if(!resetN || !clear) begin currState <= s_init; end else begin currState <= nextState; end end always_comb begin unique case(currState) s_init:begin if(resetN) begin nextState = currState.next; end else begin nextState = currState.first; end end s_fifoReset:begin if(wr_rst_busy || rd_rst_busy) begin nextState = currState; end else begin nextState = currState.next; end end s_req,s_wait0,s_wait1,s_wait2,s_wait3:begin nextState = currState.next; end s_insertInc:begin if(i < storedReads) begin nextState = s_req; end else begin nextState = s_hold; end end s_hold: begin if(clear) begin nextState = currState; end else begin nextState = s_fifoReset; end end endcase end always_comb begin unique case(currState) s_init: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00110000; s_fifoReset: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000000; s_req,s_wait0,s_wait1,s_wait2: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000010; s_wait3: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000011; s_insertInc: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00001100; s_hold: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b01110000; endcase end xpm_fifo_sync #( .DOUT_RESET_VALUE("0"), .ECC_MODE("no_ecc"), .FIFO_MEMORY_TYPE("distributed"), .FIFO_READ_LATENCY(1), .FIFO_WRITE_DEPTH(256), .FULL_RESET_VALUE(0), .READ_DATA_WIDTH(32), .READ_MODE("fwft"), .SIM_ASSERT_CHK(0), .USE_ADV_FEATURES("0000"), .WAKEUP_TIME(0), .WRITE_DATA_WIDTH(32) ) xpm_fifo_sync_inst ( .dout(requestData), .rd_rst_busy(rd_rst_busy), .wr_rst_busy(wr_rst_busy), .din(readData), .rd_en(read), .rst(clearFIFO), .wr_clk(clk), .wr_en(wr_en) ); endmodule
0
2,577
data/full_repos/permissive/10003806/cpu.v
10,003,806
cpu.v
v
242
100
[]
[]
[]
[(23, 241)]
null
null
1: b'%Error: data/full_repos/permissive/10003806/cpu.v:80: Cannot find file containing module: \'instruction_rom\'\n instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom.v\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom.sv\n instruction_rom\n instruction_rom.v\n instruction_rom.sv\n obj_dir/instruction_rom\n obj_dir/instruction_rom.v\n obj_dir/instruction_rom.sv\n%Error: data/full_repos/permissive/10003806/cpu.v:85: Cannot find file containing module: \'data_ram\'\n data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (\n ^~~~~~~~\n%Error: data/full_repos/permissive/10003806/cpu.v:93: Cannot find file containing module: \'stack\'\n stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:113: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance cpu\n data_out = 32\'bX;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:116: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance cpu\n data_to_ram = 32\'bX;\n ^\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:118: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance cpu\n stack_data = 32\'bX;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
0
module
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read); parameter IADDR_WIDTH = 8; parameter DADDR_WIDTH = 15; parameter SADDR_WIDTH = 5; parameter DATA_WIDTH = 8; parameter INIT_RAM = 0; output reg [DATA_WIDTH - 1:0] data_out; output reg data_out_en; output reg data_read; input clk; input [DATA_WIDTH - 1:0] data_in; input data_available; reg [IADDR_WIDTH - 1:0] pc; reg [DADDR_WIDTH - 1:0] dp; reg [SADDR_WIDTH - 1:0] lsc; wire [3:0] ci; wire [DATA_WIDTH - 1:0] data_from_ram; reg [DATA_WIDTH - 1:0] data_to_ram; reg ram_write; wire [IADDR_WIDTH - 1:0] stack_top; reg [IADDR_WIDTH - 1:0] stack_data; reg stack_push; reg stack_pop; reg [IADDR_WIDTH - 1:0] next_pc; reg [DADDR_WIDTH - 1:0] next_dp; reg [SADDR_WIDTH - 1:0] next_lsc; instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom ( .address(pc), .data_out(ci) ); data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram ( .data_out(data_from_ram), .clk(clk), .address(next_dp), .data_in(data_to_ram), .write(ram_write) ); stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack ( .top(stack_top), .clk(clk), .pushd(stack_data), .push_en(stack_push), .pop_en(stack_pop) ); initial begin pc = 0; dp = 0; lsc = 0; end always @(*) begin data_out = 32'bX; data_out_en = 0; data_read = 0; data_to_ram = 32'bX; ram_write = 0; stack_data = 32'bX; stack_push = 0; stack_pop = 0; next_dp = dp; next_pc = pc + 1'b1; next_lsc = lsc; if (lsc == 0) begin case (ci) 4'h0: begin next_pc = pc; end 4'h8: begin next_dp = dp + 1'b1; end 4'h9: begin next_dp = dp - 1'b1; end 4'hA: begin data_to_ram = data_from_ram + 1'b1; ram_write = 1; end 4'hB: begin data_to_ram = data_from_ram - 1'b1; ram_write = 1; end 4'hC: begin if (data_from_ram == 0) begin next_lsc = 1; end else begin stack_data = next_pc; stack_push = 1; end end 4'hD: begin if (data_from_ram == 0) stack_pop = 1; else next_pc = stack_top; end 4'hE: begin data_out = data_from_ram; data_out_en = 1; end 4'hF: begin if (data_available) begin data_to_ram = data_in; ram_write = 1; data_read = 1; end else begin next_pc = pc; end end endcase end else begin case (ci) 4'hC: begin next_lsc = lsc + 1'b1; end 4'hD: begin next_lsc = lsc - 1'b1; end endcase end end always @(posedge clk) begin pc <= next_pc; dp <= next_dp; lsc <= next_lsc; end endmodule
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read);
parameter IADDR_WIDTH = 8; parameter DADDR_WIDTH = 15; parameter SADDR_WIDTH = 5; parameter DATA_WIDTH = 8; parameter INIT_RAM = 0; output reg [DATA_WIDTH - 1:0] data_out; output reg data_out_en; output reg data_read; input clk; input [DATA_WIDTH - 1:0] data_in; input data_available; reg [IADDR_WIDTH - 1:0] pc; reg [DADDR_WIDTH - 1:0] dp; reg [SADDR_WIDTH - 1:0] lsc; wire [3:0] ci; wire [DATA_WIDTH - 1:0] data_from_ram; reg [DATA_WIDTH - 1:0] data_to_ram; reg ram_write; wire [IADDR_WIDTH - 1:0] stack_top; reg [IADDR_WIDTH - 1:0] stack_data; reg stack_push; reg stack_pop; reg [IADDR_WIDTH - 1:0] next_pc; reg [DADDR_WIDTH - 1:0] next_dp; reg [SADDR_WIDTH - 1:0] next_lsc; instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom ( .address(pc), .data_out(ci) ); data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram ( .data_out(data_from_ram), .clk(clk), .address(next_dp), .data_in(data_to_ram), .write(ram_write) ); stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack ( .top(stack_top), .clk(clk), .pushd(stack_data), .push_en(stack_push), .pop_en(stack_pop) ); initial begin pc = 0; dp = 0; lsc = 0; end always @(*) begin data_out = 32'bX; data_out_en = 0; data_read = 0; data_to_ram = 32'bX; ram_write = 0; stack_data = 32'bX; stack_push = 0; stack_pop = 0; next_dp = dp; next_pc = pc + 1'b1; next_lsc = lsc; if (lsc == 0) begin case (ci) 4'h0: begin next_pc = pc; end 4'h8: begin next_dp = dp + 1'b1; end 4'h9: begin next_dp = dp - 1'b1; end 4'hA: begin data_to_ram = data_from_ram + 1'b1; ram_write = 1; end 4'hB: begin data_to_ram = data_from_ram - 1'b1; ram_write = 1; end 4'hC: begin if (data_from_ram == 0) begin next_lsc = 1; end else begin stack_data = next_pc; stack_push = 1; end end 4'hD: begin if (data_from_ram == 0) stack_pop = 1; else next_pc = stack_top; end 4'hE: begin data_out = data_from_ram; data_out_en = 1; end 4'hF: begin if (data_available) begin data_to_ram = data_in; ram_write = 1; data_read = 1; end else begin next_pc = pc; end end endcase end else begin case (ci) 4'hC: begin next_lsc = lsc + 1'b1; end 4'hD: begin next_lsc = lsc - 1'b1; end endcase end end always @(posedge clk) begin pc <= next_pc; dp <= next_dp; lsc <= next_lsc; end endmodule
0
2,578
data/full_repos/permissive/10003806/cpu_tb.v
10,003,806
cpu_tb.v
v
78
80
[]
[]
[]
[(23, 77)]
null
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #101 data_available = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Error: data/full_repos/permissive/10003806/cpu_tb.v:36: Cannot find file containing module: \'cpu\'\n cpu #(.INIT_RAM(1)) uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu.v\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
1
module
module cpu_tb; reg clk; reg [7:0] data_in; reg data_available; wire [7:0] data_out; wire data_out_en; wire data_read; cpu #(.INIT_RAM(1)) uut ( .clk(clk), .data_in(data_in), .data_available(data_available), .data_out(data_out), .data_out_en(data_out_en), .data_read(data_read) ); initial begin clk = 0; data_in = 0; data_available = 0; #101 data_available = 1; end always @(posedge clk) begin if (data_read) begin data_in <= data_in + 1'b1; end end always @(posedge clk) begin if (data_out_en) begin $write("%c", data_out); end end always begin #10 clk = 0; #10 clk = 1; end endmodule
module cpu_tb;
reg clk; reg [7:0] data_in; reg data_available; wire [7:0] data_out; wire data_out_en; wire data_read; cpu #(.INIT_RAM(1)) uut ( .clk(clk), .data_in(data_in), .data_available(data_available), .data_out(data_out), .data_out_en(data_out_en), .data_read(data_read) ); initial begin clk = 0; data_in = 0; data_available = 0; #101 data_available = 1; end always @(posedge clk) begin if (data_read) begin data_in <= data_in + 1'b1; end end always @(posedge clk) begin if (data_out_en) begin $write("%c", data_out); end end always begin #10 clk = 0; #10 clk = 1; end endmodule
0
2,579
data/full_repos/permissive/10003806/data_ram.v
10,003,806
data_ram.v
v
79
83
[]
[]
[]
[(23, 78)]
null
data/verilator_xmls/f8747044-ea52-433a-af12-40acf1e92214.xml
null
2
module
module data_ram(data_out, clk, address, data_in, write); parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 15; parameter INIT_RAM = 1; output [DATA_WIDTH - 1:0] data_out; input clk; input [ADDR_WIDTH - 1:0] address; input [DATA_WIDTH - 1:0] data_in; input write; reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1]; reg [DATA_WIDTH - 1:0] output_buffer; assign data_out = output_buffer; integer i; initial begin output_buffer = 0; if (INIT_RAM) begin for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) data[i] = 0; end end always @(posedge clk) begin if (write) begin data[address] <= data_in; output_buffer <= data_in; end else begin output_buffer <= data[address]; end end endmodule
module data_ram(data_out, clk, address, data_in, write);
parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 15; parameter INIT_RAM = 1; output [DATA_WIDTH - 1:0] data_out; input clk; input [ADDR_WIDTH - 1:0] address; input [DATA_WIDTH - 1:0] data_in; input write; reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1]; reg [DATA_WIDTH - 1:0] output_buffer; assign data_out = output_buffer; integer i; initial begin output_buffer = 0; if (INIT_RAM) begin for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) data[i] = 0; end end always @(posedge clk) begin if (write) begin data[address] <= data_in; output_buffer <= data_in; end else begin output_buffer <= data[address]; end end endmodule
0
2,580
data/full_repos/permissive/10003806/instruction_rom.v
10,003,806
instruction_rom.v
v
51
83
[]
[]
[]
[(23, 50)]
null
data/verilator_xmls/e96bc207-0b5b-4ceb-9a3a-f0a0a5664562.xml
null
3
module
module instruction_rom(data_out, address); parameter DATA_WIDTH = 4; parameter ADDR_WIDTH = 8; parameter ROM_FILE = "../rom.mif"; output [DATA_WIDTH - 1:0] data_out; input [ADDR_WIDTH - 1:0] address; reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1]; assign data_out = data[address]; initial begin $readmemh(ROM_FILE, data); end endmodule
module instruction_rom(data_out, address);
parameter DATA_WIDTH = 4; parameter ADDR_WIDTH = 8; parameter ROM_FILE = "../rom.mif"; output [DATA_WIDTH - 1:0] data_out; input [ADDR_WIDTH - 1:0] address; reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1]; assign data_out = data[address]; initial begin $readmemh(ROM_FILE, data); end endmodule
0
2,581
data/full_repos/permissive/10003806/stack.v
10,003,806
stack.v
v
87
77
[]
[]
[]
[(23, 86)]
null
data/verilator_xmls/2422a211-cc3d-42fd-977b-179a68182cf0.xml
null
4
module
module stack(top, clk, pushd, push_en, pop_en); parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 5; output [DATA_WIDTH - 1:0] top; input clk; input [DATA_WIDTH - 1:0] pushd; input push_en; input pop_en; reg [DATA_WIDTH - 1:0] stack_data[0:(1 << ADDR_WIDTH) - 1]; reg [ADDR_WIDTH - 1:0] stack_ptr; reg [DATA_WIDTH - 1:0] stack_top; assign top = stack_top; integer i; initial begin stack_ptr = 0; stack_top = 0; for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) stack_data[i] = 0; end always @(posedge clk) begin if (push_en) begin stack_data[stack_ptr] <= stack_top; stack_ptr <= stack_ptr + 1'b1; stack_top <= pushd; end else if (pop_en) begin stack_ptr <= stack_ptr - 1'b1; stack_top <= stack_data[stack_ptr - 1'b1]; end end endmodule
module stack(top, clk, pushd, push_en, pop_en);
parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 5; output [DATA_WIDTH - 1:0] top; input clk; input [DATA_WIDTH - 1:0] pushd; input push_en; input pop_en; reg [DATA_WIDTH - 1:0] stack_data[0:(1 << ADDR_WIDTH) - 1]; reg [ADDR_WIDTH - 1:0] stack_ptr; reg [DATA_WIDTH - 1:0] stack_top; assign top = stack_top; integer i; initial begin stack_ptr = 0; stack_top = 0; for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) stack_data[i] = 0; end always @(posedge clk) begin if (push_en) begin stack_data[stack_ptr] <= stack_top; stack_ptr <= stack_ptr + 1'b1; stack_top <= pushd; end else if (pop_en) begin stack_ptr <= stack_ptr - 1'b1; stack_top <= stack_data[stack_ptr - 1'b1]; end end endmodule
0
2,582
data/full_repos/permissive/10003806/stack_tb.v
10,003,806
stack_tb.v
v
79
73
[]
[]
[]
[(23, 78)]
null
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = 0;\n ^\n%Error: data/full_repos/permissive/10003806/stack_tb.v:36: Cannot find file containing module: \'stack\'\n stack uut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack.v\n data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack.sv\n stack\n stack.v\n stack.sv\n obj_dir/stack\n obj_dir/stack.v\n obj_dir/stack.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
5
module
module stack_tb; reg clk; reg rst; reg [15:0] pushd; reg push_en; reg pop_en; wire [15:0] top; stack uut ( .top(top), .clk(clk), .rst(rst), .pushd(pushd), .push_en(push_en), .pop_en(pop_en) ); initial begin clk = 0; rst = 0; pushd = 0; push_en = 0; pop_en = 0; rst = 1; clk = 1; #10 clk = 0; rst = 0; pushd = 16'hBEEF; push_en = 1; #10 clk = 1; #10 clk = 0; pushd = 16'hDEAD; push_en = 1; #10 clk = 1; #10 clk = 0; push_en = 0; pop_en = 1; #10 clk = 1; #10 clk = 0; #10 clk = 1; #10 clk = 0; end endmodule
module stack_tb;
reg clk; reg rst; reg [15:0] pushd; reg push_en; reg pop_en; wire [15:0] top; stack uut ( .top(top), .clk(clk), .rst(rst), .pushd(pushd), .push_en(push_en), .pop_en(pop_en) ); initial begin clk = 0; rst = 0; pushd = 0; push_en = 0; pop_en = 0; rst = 1; clk = 1; #10 clk = 0; rst = 0; pushd = 16'hBEEF; push_en = 1; #10 clk = 1; #10 clk = 0; pushd = 16'hDEAD; push_en = 1; #10 clk = 1; #10 clk = 0; push_en = 0; pop_en = 1; #10 clk = 1; #10 clk = 0; #10 clk = 1; #10 clk = 0; end endmodule
0
2,583
data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v
100,100,285
cpram_sclk_2w1r.v
v
140
73
[]
[]
[]
[(22, 139)]
null
null
1: b"%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v:69: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.v\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.sv\n dpram_sclk\n dpram_sclk.v\n dpram_sclk.sv\n obj_dir/dpram_sclk\n obj_dir/dpram_sclk.v\n obj_dir/dpram_sclk.sv\n%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v:88: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
7
module
module cpram_sclk_2w1r #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter CLEAR_ON_INIT = 1, parameter ENABLE_BYPASS = 1 ) ( clk, rst, we1, waddr1, wdata1, we2, waddr2, wdata2, re, raddr, rdata ); input clk; input rst; input we1; input [ADDR_WIDTH-1:0] waddr1; input [DATA_WIDTH-1:0] wdata1; input we2; input [ADDR_WIDTH-1:0] waddr2; input [DATA_WIDTH-1:0] wdata2; input re; input [ADDR_WIDTH-1:0] raddr; output [DATA_WIDTH-1:0] rdata; wire [DATA_WIDTH-1:0] dout; wire [DATA_WIDTH-1:0] dout0; wire [DATA_WIDTH-1:0] dout1; wire [DATA_WIDTH-1:0] dout2; wire [DATA_WIDTH-1:0] dout3; reg sel_map[(1<<ADDR_WIDTH)-1:0]; dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem0 ( .clk (clk), .rst (rst), .dout (dout0), .raddr (raddr), .re (re), .waddr (waddr1), .we (we1), .din (wdata1) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem1 ( .clk (clk), .rst (rst), .dout (dout2), .raddr (raddr), .re (re), .waddr (waddr2), .we (we2), .din (wdata2) ); assign dout = sel_map[raddr]==1'b0 ? dout0 : dout1; generate if (ENABLE_BYPASS) begin : bypass_gen assign rdata = (we2 && (raddr==waddr1)) ? wdata1 : (we1 && (raddr==waddr2)) ? wdata2 : dout; end else begin assign rdata = dout; end endgenerate always @(posedge clk) if (we1 && we2 && waddr1==waddr2) sel_map[waddr1] <= 1'b1; else if (we1 && we2) begin sel_map[waddr1] <= 1'b0; sel_map[waddr2] <= 1'b1; end else if (we1) sel_map[waddr1] <= 1'b0; else if (we2) sel_map[waddr2] <= 1'b1; endmodule
module cpram_sclk_2w1r #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter CLEAR_ON_INIT = 1, parameter ENABLE_BYPASS = 1 ) ( clk, rst, we1, waddr1, wdata1, we2, waddr2, wdata2, re, raddr, rdata );
input clk; input rst; input we1; input [ADDR_WIDTH-1:0] waddr1; input [DATA_WIDTH-1:0] wdata1; input we2; input [ADDR_WIDTH-1:0] waddr2; input [DATA_WIDTH-1:0] wdata2; input re; input [ADDR_WIDTH-1:0] raddr; output [DATA_WIDTH-1:0] rdata; wire [DATA_WIDTH-1:0] dout; wire [DATA_WIDTH-1:0] dout0; wire [DATA_WIDTH-1:0] dout1; wire [DATA_WIDTH-1:0] dout2; wire [DATA_WIDTH-1:0] dout3; reg sel_map[(1<<ADDR_WIDTH)-1:0]; dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem0 ( .clk (clk), .rst (rst), .dout (dout0), .raddr (raddr), .re (re), .waddr (waddr1), .we (we1), .din (wdata1) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem1 ( .clk (clk), .rst (rst), .dout (dout2), .raddr (raddr), .re (re), .waddr (waddr2), .we (we2), .din (wdata2) ); assign dout = sel_map[raddr]==1'b0 ? dout0 : dout1; generate if (ENABLE_BYPASS) begin : bypass_gen assign rdata = (we2 && (raddr==waddr1)) ? wdata1 : (we1 && (raddr==waddr2)) ? wdata2 : dout; end else begin assign rdata = dout; end endgenerate always @(posedge clk) if (we1 && we2 && waddr1==waddr2) sel_map[waddr1] <= 1'b1; else if (we1 && we2) begin sel_map[waddr1] <= 1'b0; sel_map[waddr2] <= 1'b1; end else if (we1) sel_map[waddr1] <= 1'b0; else if (we2) sel_map[waddr2] <= 1'b1; endmodule
3
2,584
data/full_repos/permissive/100100285/rtl/cpram_sclk_4w1r.v
100,100,285
cpram_sclk_4w1r.v
v
193
73
[]
[]
[]
[(21, 192)]
null
null
1: b"%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_4w1r.v:80: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.v\n data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.sv\n dpram_sclk\n dpram_sclk.v\n dpram_sclk.sv\n obj_dir/dpram_sclk\n obj_dir/dpram_sclk.v\n obj_dir/dpram_sclk.sv\n%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_4w1r.v:99: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_4w1r.v:118: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_4w1r.v:137: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
8
module
module cpram_sclk_4w1r #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter CLEAR_ON_INIT = 1, parameter ENABLE_BYPASS = 1 ) ( clk, rst, we1, waddr1, wdata1, we2, waddr2, wdata2, we3, waddr3, wdata3, we4, waddr4, wdata4, re, raddr, rdata ); input clk; input rst; input we1; input [ADDR_WIDTH-1:0] waddr1; input [DATA_WIDTH-1:0] wdata1; input we2; input [ADDR_WIDTH-1:0] waddr2; input [DATA_WIDTH-1:0] wdata2; input we3; input [ADDR_WIDTH-1:0] waddr3; input [DATA_WIDTH-1:0] wdata3; input we4; input [ADDR_WIDTH-1:0] waddr4; input [DATA_WIDTH-1:0] wdata4; input re; input [ADDR_WIDTH-1:0] raddr; output [DATA_WIDTH-1:0] rdata; wire [DATA_WIDTH-1:0] dout; wire [DATA_WIDTH-1:0] dout0; wire [DATA_WIDTH-1:0] dout1; wire [DATA_WIDTH-1:0] dout2; wire [DATA_WIDTH-1:0] dout3; reg [1:0] sel_map[(1<<ADDR_WIDTH)-1:0]; dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem0 ( .clk (clk), .rst (rst), .dout (dout0), .raddr (raddr), .re (re), .waddr (waddr1), .we (we1), .din (wdata1) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem1 ( .clk (clk), .rst (rst), .dout (dout2), .raddr (raddr), .re (re), .waddr (waddr2), .we (we2), .din (wdata2) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem2 ( .clk (clk), .rst (rst), .dout (dout3), .raddr (raddr), .re (re), .waddr (waddr3), .we (we3), .din (wdata3) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem3 ( .clk (clk), .rst (rst), .dout (dout3), .raddr (raddr), .re (re), .waddr (waddr4), .we (we4), .din (wdata4) ); assign dout = sel_map[raddr]==2'd0 ? dout0 : sel_map[raddr]==2'd1 ? dout1 : sel_map[raddr]==2'd2 ? dout2 : sel_map[raddr]==2'd3 ? dout3 : {DATA_WIDTH{1'b0}}; generate if (ENABLE_BYPASS) begin : bypass_gen assign rdata = (we1 && (raddr==waddr1)) ? wdata1 : (we2 && (raddr==waddr2)) ? wdata2 : (we3 && (raddr==waddr3)) ? wdata3 : (we4 && (raddr==waddr4)) ? wdata4 : dout; end else begin assign rdata = dout; end endgenerate always @(posedge clk) begin if (we1) sel_map[waddr1] <= 2'd0; if (we2) sel_map[waddr2] <= 2'd1; if (we3) sel_map[waddr3] <= 2'd2; if (we4) sel_map[waddr4] <= 2'd3; end endmodule
module cpram_sclk_4w1r #( parameter ADDR_WIDTH = 5, parameter DATA_WIDTH = 32, parameter CLEAR_ON_INIT = 1, parameter ENABLE_BYPASS = 1 ) ( clk, rst, we1, waddr1, wdata1, we2, waddr2, wdata2, we3, waddr3, wdata3, we4, waddr4, wdata4, re, raddr, rdata );
input clk; input rst; input we1; input [ADDR_WIDTH-1:0] waddr1; input [DATA_WIDTH-1:0] wdata1; input we2; input [ADDR_WIDTH-1:0] waddr2; input [DATA_WIDTH-1:0] wdata2; input we3; input [ADDR_WIDTH-1:0] waddr3; input [DATA_WIDTH-1:0] wdata3; input we4; input [ADDR_WIDTH-1:0] waddr4; input [DATA_WIDTH-1:0] wdata4; input re; input [ADDR_WIDTH-1:0] raddr; output [DATA_WIDTH-1:0] rdata; wire [DATA_WIDTH-1:0] dout; wire [DATA_WIDTH-1:0] dout0; wire [DATA_WIDTH-1:0] dout1; wire [DATA_WIDTH-1:0] dout2; wire [DATA_WIDTH-1:0] dout3; reg [1:0] sel_map[(1<<ADDR_WIDTH)-1:0]; dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem0 ( .clk (clk), .rst (rst), .dout (dout0), .raddr (raddr), .re (re), .waddr (waddr1), .we (we1), .din (wdata1) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem1 ( .clk (clk), .rst (rst), .dout (dout2), .raddr (raddr), .re (re), .waddr (waddr2), .we (we2), .din (wdata2) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem2 ( .clk (clk), .rst (rst), .dout (dout3), .raddr (raddr), .re (re), .waddr (waddr3), .we (we3), .din (wdata3) ); dpram_sclk #( .ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .CLEAR_ON_INIT (CLEAR_ON_INIT), .ENABLE_BYPASS (ENABLE_BYPASS) ) mem3 ( .clk (clk), .rst (rst), .dout (dout3), .raddr (raddr), .re (re), .waddr (waddr4), .we (we4), .din (wdata4) ); assign dout = sel_map[raddr]==2'd0 ? dout0 : sel_map[raddr]==2'd1 ? dout1 : sel_map[raddr]==2'd2 ? dout2 : sel_map[raddr]==2'd3 ? dout3 : {DATA_WIDTH{1'b0}}; generate if (ENABLE_BYPASS) begin : bypass_gen assign rdata = (we1 && (raddr==waddr1)) ? wdata1 : (we2 && (raddr==waddr2)) ? wdata2 : (we3 && (raddr==waddr3)) ? wdata3 : (we4 && (raddr==waddr4)) ? wdata4 : dout; end else begin assign rdata = dout; end endgenerate always @(posedge clk) begin if (we1) sel_map[waddr1] <= 2'd0; if (we2) sel_map[waddr2] <= 2'd1; if (we3) sel_map[waddr3] <= 2'd2; if (we4) sel_map[waddr4] <= 2'd3; end endmodule
3
2,585
data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv
100,152,754
ahb_master_test.sv
sv
147
103
[]
[]
[]
null
line:7: before: ";"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:61: Unsupported: Ignoring delay on this delayed statement.\nalways #10 i_hclk++;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ahb_master.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:89: syntax error, unexpected \'@\'\n repeat(10) @(posedge i_hclk);\n ^\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:128: syntax error, unexpected \'@\'\n repeat(10) @(posedge i_hclk);\n ^\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:143: syntax error, unexpected \'@\'\n @(posedge i_hclk);\n ^\n%Error: Exiting due to 5 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
11
module
module ahb_master_test; parameter DATA_WDT = 32; parameter BEAT_WDT = 32; bit i_hclk; bit i_hreset_n; logic [31:0] o_haddr; logic [2:0] o_hburst; logic [1:0] o_htrans; logic[DATA_WDT-1:0] o_hwdata; logic o_hwrite; logic [2:0] o_hsize; logic [DATA_WDT-1:0] i_hrdata; logic i_hready; logic [1:0] i_hresp; logic i_hgrant; logic o_hbusreq; logic o_next; logic [DATA_WDT-1:0]i_data; bit i_dav; bit [31:0] i_addr; bit [2:0] i_size; bit i_wr; bit i_rd; bit [BEAT_WDT-1:0]i_min_len; bit i_cont; logic[DATA_WDT-1:0] o_data; logic[31:0] o_addr; logic o_dav; logic [DATA_WDT-1:0] hwdata0, hwdata1; assign hwdata0 = U_AHB_MASTER.o_hwdata[0]; assign hwdata1 = U_AHB_MASTER.o_hwdata[1]; ahb_master #(.DATA_WDT(DATA_WDT), .BEAT_WDT(BEAT_WDT)) U_AHB_MASTER (.*); ahb_slave_sim #(.DATA_WDT(DATA_WDT)) U_AHB_SLAVE_SIM_1 ( .i_hclk (i_hclk), .i_hreset_n (i_hreset_n), .i_hburst (o_hburst), .i_htrans (o_htrans), .i_hwdata (o_hwdata), .i_hsel (1'd1), .i_haddr (o_haddr), .i_hwrite (o_hwrite), .i_hready (1'd1), .o_hrdata (i_hrdata), .o_hready (i_hready), .o_hresp (i_hresp) ); always #10 i_hclk++; always @ (posedge i_hclk) begin if ( o_hbusreq ) i_hgrant <= 1'd1; else i_hgrant <= 1'd0; end bit dav; bit [31:0] dat; initial begin $dumpfile("ahb_master.vcd"); $dumpvars; i_hgrant <= 1; i_hreset_n <= 1'd0; d(1); i_hreset_n <= 1'd1; i_rd <= 0; i_wr <= 0; repeat(10) @(posedge i_hclk); i_min_len <= 42; i_wr <= 1'd1; i_cont <= 1'd0; i_dav <= 1'd1; i_data <= 0; wait_for_next; repeat(100) begin: bk dav = $random; dat = dat + dav; i_cont <= 1'd1; i_dav <= dav; i_data <= dav ? dat : `ifdef X_INJECTION 32'dx; `else 0; `endif wait_for_next; end i_rd <= 1'd0; i_wr <= 1'd0; i_cont <= 1'd0; repeat(10) @(posedge i_hclk); $finish; end task wait_for_next; d(1); while(o_next !== 1) begin d(1); end endtask task d(int x); repeat(x) @(posedge i_hclk); endtask endmodule
module ahb_master_test;
parameter DATA_WDT = 32; parameter BEAT_WDT = 32; bit i_hclk; bit i_hreset_n; logic [31:0] o_haddr; logic [2:0] o_hburst; logic [1:0] o_htrans; logic[DATA_WDT-1:0] o_hwdata; logic o_hwrite; logic [2:0] o_hsize; logic [DATA_WDT-1:0] i_hrdata; logic i_hready; logic [1:0] i_hresp; logic i_hgrant; logic o_hbusreq; logic o_next; logic [DATA_WDT-1:0]i_data; bit i_dav; bit [31:0] i_addr; bit [2:0] i_size; bit i_wr; bit i_rd; bit [BEAT_WDT-1:0]i_min_len; bit i_cont; logic[DATA_WDT-1:0] o_data; logic[31:0] o_addr; logic o_dav; logic [DATA_WDT-1:0] hwdata0, hwdata1; assign hwdata0 = U_AHB_MASTER.o_hwdata[0]; assign hwdata1 = U_AHB_MASTER.o_hwdata[1]; ahb_master #(.DATA_WDT(DATA_WDT), .BEAT_WDT(BEAT_WDT)) U_AHB_MASTER (.*); ahb_slave_sim #(.DATA_WDT(DATA_WDT)) U_AHB_SLAVE_SIM_1 ( .i_hclk (i_hclk), .i_hreset_n (i_hreset_n), .i_hburst (o_hburst), .i_htrans (o_htrans), .i_hwdata (o_hwdata), .i_hsel (1'd1), .i_haddr (o_haddr), .i_hwrite (o_hwrite), .i_hready (1'd1), .o_hrdata (i_hrdata), .o_hready (i_hready), .o_hresp (i_hresp) ); always #10 i_hclk++; always @ (posedge i_hclk) begin if ( o_hbusreq ) i_hgrant <= 1'd1; else i_hgrant <= 1'd0; end bit dav; bit [31:0] dat; initial begin $dumpfile("ahb_master.vcd"); $dumpvars; i_hgrant <= 1; i_hreset_n <= 1'd0; d(1); i_hreset_n <= 1'd1; i_rd <= 0; i_wr <= 0; repeat(10) @(posedge i_hclk); i_min_len <= 42; i_wr <= 1'd1; i_cont <= 1'd0; i_dav <= 1'd1; i_data <= 0; wait_for_next; repeat(100) begin: bk dav = $random; dat = dat + dav; i_cont <= 1'd1; i_dav <= dav; i_data <= dav ? dat : `ifdef X_INJECTION 32'dx; `else 0; `endif wait_for_next; end i_rd <= 1'd0; i_wr <= 1'd0; i_cont <= 1'd0; repeat(10) @(posedge i_hclk); $finish; end task wait_for_next; d(1); while(o_next !== 1) begin d(1); end endtask task d(int x); repeat(x) @(posedge i_hclk); endtask endmodule
0
2,586
data/full_repos/permissive/100152754/ahb_master/bench/components/ahb_arbiter_sim.sv
100,152,754
ahb_arbiter_sim.sv
sv
70
76
[]
[]
[]
null
None: at end of input
null
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
12
module
module ahb_arbiter_sim ( input i_hclk, input i_hreset_n, input [15:0] i_hbusreq, input i_hready, input [1:0] i_hresp, output bit [15:0] o_hgrant, output bit [3:0] o_hmaster ); always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) begin o_hgrant <= 1'd1; end else if ( i_hbusreq[15:1] ) begin: blk1 bit done; integer i; o_hgrant <= 1'd0; done = 0; for(i=15;i>=0;i=i-1) begin if ( i_hbusreq[i] && !done ) begin o_hgrant[i] <= 1'd1; done = 1; end end end else o_hgrant <= 1'd1; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hmaster <= 0; else if ( i_hready ) begin: bk2 integer i; for(i=15;i>=0;i=i-1) begin if ( o_hgrant[i] == 1'd1 ) begin o_hmaster <= i; end end end end endmodule
module ahb_arbiter_sim ( input i_hclk, input i_hreset_n, input [15:0] i_hbusreq, input i_hready, input [1:0] i_hresp, output bit [15:0] o_hgrant, output bit [3:0] o_hmaster );
always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) begin o_hgrant <= 1'd1; end else if ( i_hbusreq[15:1] ) begin: blk1 bit done; integer i; o_hgrant <= 1'd0; done = 0; for(i=15;i>=0;i=i-1) begin if ( i_hbusreq[i] && !done ) begin o_hgrant[i] <= 1'd1; done = 1; end end end else o_hgrant <= 1'd1; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hmaster <= 0; else if ( i_hready ) begin: bk2 integer i; for(i=15;i>=0;i=i-1) begin if ( o_hgrant[i] == 1'd1 ) begin o_hmaster <= i; end end end end endmodule
0
2,587
data/full_repos/permissive/100152754/ahb_master/bench/components/ahb_slave_sim.sv
100,152,754
ahb_slave_sim.sv
sv
118
97
[]
[]
[]
null
None: at end of input
null
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
13
module
module ahb_slave_sim #(parameter DATA_WDT = 32) ( input i_hclk, input i_hreset_n, input [2:0] i_hburst, input [1:0] i_htrans, input [31:0] i_hwdata, input i_hsel, input [31:0] i_haddr, input i_hwrite, output reg [31:0] o_hrdata, input i_hready, output reg o_hready, output [1:0] o_hresp ); localparam [1:0] IDLE = 0; localparam [1:0] BUSY = 1; localparam [1:0] NONSEQ = 2; localparam [1:0] SEQ = 3; localparam [1:0] OKAY = 0; localparam [1:0] ERROR = 1; localparam [1:0] SPLIT = 2; localparam [1:0] RETRY = 3; localparam [2:0] SINGLE = 0; localparam [2:0] INCR = 1; localparam [2:0] WRAP4 = 2; localparam [2:0] INCR4 = 3; localparam [2:0] WRAP8 = 4; localparam [2:0] INCR8 = 5; localparam [2:0] WRAP16 = 6; localparam [2:0] INCR16 = 7; localparam [2:0] BYTE = 0; localparam [2:0] HWORD = 1; localparam [2:0] WORD = 2; localparam [2:0] DWORD = 3; localparam [2:0] BIT128 = 4; localparam [2:0] BIT256 = 5; localparam [2:0] BIT512 = 6; localparam [2:0] BIT1024 = 7; reg [7:0] mem [(2^32)-1:0]; reg write, read; reg [31:0] addr; reg [DATA_WDT-1:0] data; assign o_hresp = OKAY; always @ (posedge (i_hclk && o_hready && i_hready) or negedge i_hreset_n) begin if ( !i_hreset_n ) begin read <= 1'd0; write <= 1'd0; end else begin if ( i_hsel && (i_htrans == SEQ || i_htrans == NONSEQ) ) begin write <= i_hwrite; addr <= i_haddr; end else begin write <= 1'd0; end end end always @ (posedge (i_hclk && o_hready && i_hready) or negedge i_hreset_n) begin if ( i_hsel && (i_htrans == SEQ || i_htrans == NONSEQ) && !i_hwrite ) begin $display($time, "%m :: Reading data %x from address %x", mem[i_haddr], i_haddr); o_hrdata <= mem [i_haddr]; end end always @ (posedge (i_hclk && o_hready) or negedge i_hreset_n) begin if ( write ) begin $display($time, "%m :: Writing data %x to address %x...", i_hwdata, addr); mem [addr] <= i_hwdata; end end always @ (negedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hready <= 1'd0; else o_hready <= $random; end endmodule
module ahb_slave_sim #(parameter DATA_WDT = 32) ( input i_hclk, input i_hreset_n, input [2:0] i_hburst, input [1:0] i_htrans, input [31:0] i_hwdata, input i_hsel, input [31:0] i_haddr, input i_hwrite, output reg [31:0] o_hrdata, input i_hready, output reg o_hready, output [1:0] o_hresp );
localparam [1:0] IDLE = 0; localparam [1:0] BUSY = 1; localparam [1:0] NONSEQ = 2; localparam [1:0] SEQ = 3; localparam [1:0] OKAY = 0; localparam [1:0] ERROR = 1; localparam [1:0] SPLIT = 2; localparam [1:0] RETRY = 3; localparam [2:0] SINGLE = 0; localparam [2:0] INCR = 1; localparam [2:0] WRAP4 = 2; localparam [2:0] INCR4 = 3; localparam [2:0] WRAP8 = 4; localparam [2:0] INCR8 = 5; localparam [2:0] WRAP16 = 6; localparam [2:0] INCR16 = 7; localparam [2:0] BYTE = 0; localparam [2:0] HWORD = 1; localparam [2:0] WORD = 2; localparam [2:0] DWORD = 3; localparam [2:0] BIT128 = 4; localparam [2:0] BIT256 = 5; localparam [2:0] BIT512 = 6; localparam [2:0] BIT1024 = 7; reg [7:0] mem [(2^32)-1:0]; reg write, read; reg [31:0] addr; reg [DATA_WDT-1:0] data; assign o_hresp = OKAY; always @ (posedge (i_hclk && o_hready && i_hready) or negedge i_hreset_n) begin if ( !i_hreset_n ) begin read <= 1'd0; write <= 1'd0; end else begin if ( i_hsel && (i_htrans == SEQ || i_htrans == NONSEQ) ) begin write <= i_hwrite; addr <= i_haddr; end else begin write <= 1'd0; end end end always @ (posedge (i_hclk && o_hready && i_hready) or negedge i_hreset_n) begin if ( i_hsel && (i_htrans == SEQ || i_htrans == NONSEQ) && !i_hwrite ) begin $display($time, "%m :: Reading data %x from address %x", mem[i_haddr], i_haddr); o_hrdata <= mem [i_haddr]; end end always @ (posedge (i_hclk && o_hready) or negedge i_hreset_n) begin if ( write ) begin $display($time, "%m :: Writing data %x to address %x...", i_hwdata, addr); mem [addr] <= i_hwdata; end end always @ (negedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hready <= 1'd0; else o_hready <= $random; end endmodule
0
2,588
data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v
100,152,754
ahb_master.v
v
399
123
[]
[]
[]
null
line:307: before: "("
null
1: b'%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:170: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\nwire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:328: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\n if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:254: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:256: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:259: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:260: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:262: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:268: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s NEQ generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:270: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr);\n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:271: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr);\n ^\n%Error: Exiting due to 10 warning(s)\n'
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module
module ahb_master #(parameter DATA_WDT = 32, parameter BEAT_WDT = 32) ( input i_hclk, input i_hreset_n, output reg [31:0] o_haddr, output reg [2:0] o_hburst, output reg [1:0] o_htrans, output reg[DATA_WDT-1:0]o_hwdata, output reg o_hwrite, output reg [2:0] o_hsize, input [DATA_WDT-1:0]i_hrdata, input i_hready, input [1:0] i_hresp, input i_hgrant, output reg o_hbusreq, output reg o_next, input [DATA_WDT-1:0]i_data, input i_dav, input [31:0] i_addr, input [2:0] i_size, input i_wr, input i_rd, input [BEAT_WDT-1:0]i_min_len, input i_cont, output reg[DATA_WDT-1:0]o_data, output reg[31:0] o_addr, output reg o_dav ); localparam [1:0] IDLE = 0; localparam [1:0] BUSY = 1; localparam [1:0] NONSEQ = 2; localparam [1:0] SEQ = 3; localparam [1:0] OKAY = 0; localparam [1:0] ERROR = 1; localparam [1:0] SPLIT = 2; localparam [1:0] RETRY = 3; localparam [2:0] SINGLE = 0; localparam [2:0] INCR = 1; localparam [2:0] WRAP4 = 2; localparam [2:0] INCR4 = 3; localparam [2:0] WRAP8 = 4; localparam [2:0] INCR8 = 5; localparam [2:0] WRAP16 = 6; localparam [2:0] INCR16 = 7; localparam [2:0] BYTE = 0; localparam [2:0] HWORD = 1; localparam [2:0] WORD = 2; localparam [2:0] DWORD = 3; localparam [2:0] BIT128 = 4; localparam [2:0] BIT256 = 5; localparam [2:0] BIT512 = 6; localparam [2:0] BIT1024 = 7; localparam D = DATA_WDT-1; localparam B = BEAT_WDT-1; reg [4:0] burst_ctr; reg [B:0] beat_ctr; reg [1:0] gnt; reg [2:0] hburst; reg [D:0] hwdata [1:0]; reg [31:0] haddr [1:0]; reg [1:0] htrans [1:0]; reg [1:0] hwrite; reg [2:0] hsize [1:0]; reg [B:0] beat; reg pend_split; wire spl_ret_cyc_1 = gnt[1] && !i_hready && (i_hresp == RETRY || i_hresp == SPLIT); wire rd_wr = i_rd || (i_wr && i_dav); wire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10]; always @* {o_haddr, o_hburst, o_htrans, o_hwdata, o_hwrite, o_hsize} = {haddr[0], hburst, htrans[0], hwdata[1], hwrite[0], hsize[0]}; always @* o_next = (i_hready && i_hgrant && !pend_split); always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) gnt <= 2'd0; else if ( spl_ret_cyc_1 ) gnt <= 2'd0; else if ( i_hready ) gnt <= {gnt[0], i_hgrant}; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hbusreq <= 1'd0; else o_hbusreq <= i_rd | i_wr; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) begin htrans[0] <= IDLE; pend_split <= 1'd0; end else if ( spl_ret_cyc_1 ) begin htrans[0] <= IDLE; pend_split <= 1'd1; end else if ( i_hready && i_hgrant ) begin pend_split <= 1'd0; if ( pend_split ) begin {hwdata[0], hwrite[0], hsize[0]} <= {hwdata[1], hwrite[1], hsize[1]}; haddr[0] <= haddr[1]; hburst <= compute_hburst (beat, haddr[1], hsize[1]); htrans[0] <= NONSEQ; burst_ctr <= compute_burst_ctr(beat, haddr[1], hsize[1]); beat_ctr <= beat; end else begin {hwdata[0], hwrite[0], hsize[0]} <= {i_data, i_wr, i_size}; if ( !i_cont && !rd_wr ) begin htrans[0] <= IDLE; end else if ( (!i_cont && rd_wr) || !gnt[0] || (burst_ctr == 1 && o_hburst != INCR) || htrans[0] == IDLE || b1k_spec ) begin haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size); hburst <= compute_hburst (!i_cont ? i_min_len : beat_ctr, !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); htrans[0] <= rd_wr ? NONSEQ : IDLE; burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); end else begin haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size); htrans[0] <= rd_wr ? SEQ : BUSY; burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr); beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr); end end end end always @ (posedge i_hclk) begin if ( i_hready && gnt[0] ) {hwdata[1], haddr[1], hwrite[1], hsize[1], htrans[1], beat} <= {hwdata[0], haddr[0], hwrite[0], hsize[0], htrans[0], beat_ctr}; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_dav <= 1'd0; else if ( gnt[1] && i_hready && (htrans[1] == SEQ || htrans[1] == NONSEQ) ) begin o_dav <= !hwrite[1]; o_data <= i_hrdata; o_addr <= haddr[1]; end else o_dav <= 1'd0; end function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_hburst = (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 : (val >= 8 && no_cross(addr, 7, sz)) ? INCR8 : (val >= 4 && no_cross(addr, 3, sz)) ? INCR4 : INCR; $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst); end endfunction function [4:0] compute_burst_ctr(input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_burst_ctr = (val >= 16 && no_cross(addr, 15, sz)) ? 5'd16 : (val >= 8 && no_cross(addr, 7, sz)) ? 5'd8 : (val >= 4 && no_cross(addr, 3, sz)) ? 5'd4 : 5'd0; $display($time, "val = %d, addr = %d, sz = %d, compute_burst_ctr = %d", val, addr, sz, compute_burst_ctr); end endfunction function no_cross(input [31:0] addr, input [31:0] val, input [2:0] sz); if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] ) no_cross = 1'd0; else no_cross = 1'd1; endfunction `ifdef SIM wire [31:0] beat_ctr_nxt = !i_cont ? (i_min_len - rd_wr) : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); initial begin $display($time,"DEBUG MODE ENABLED! PLEASE MONITOR CAPITAL SIGNALS IN VCD..."); end `ifndef STRING `define STRING reg [256*8-1:0] `endif `STRING HBURST; `STRING HTRANS; `STRING HSIZE; `STRING HRESP; always @* begin case(o_hburst) INCR: HBURST = "INCR"; INCR4: HBURST = "INCR4"; INCR8: HBURST = "INCR8"; INCR16: HBURST = "INCR16"; default:HBURST = "<----?????--->"; endcase case(o_htrans) SINGLE: HTRANS = "IDLE"; BUSY: HTRANS = "BUSY"; SEQ: HTRANS = "SEQ"; NONSEQ: HTRANS = "NONSEQ"; default:HTRANS = "<----?????--->"; endcase case(i_hresp) OKAY: HRESP = "OKAY"; ERROR: HRESP = "ERROR"; SPLIT: HRESP = "SPLIT"; RETRY: HRESP = "RETRY"; default: HRESP = "<---?????---->"; endcase case(o_hsize) BYTE : HSIZE = "8BIT"; HWORD : HSIZE = "16BIT"; WORD : HSIZE = "32BIT"; DWORD : HSIZE = "64BIT"; BIT128 : HSIZE = "128BIT"; BIT256 : HSIZE = "256BIT"; BIT512 : HSIZE = "512BIT"; BIT1024 : HSIZE = "1024BIT"; default : HSIZE = "<---?????--->"; endcase end `endif endmodule
module ahb_master #(parameter DATA_WDT = 32, parameter BEAT_WDT = 32) ( input i_hclk, input i_hreset_n, output reg [31:0] o_haddr, output reg [2:0] o_hburst, output reg [1:0] o_htrans, output reg[DATA_WDT-1:0]o_hwdata, output reg o_hwrite, output reg [2:0] o_hsize, input [DATA_WDT-1:0]i_hrdata, input i_hready, input [1:0] i_hresp, input i_hgrant, output reg o_hbusreq, output reg o_next, input [DATA_WDT-1:0]i_data, input i_dav, input [31:0] i_addr, input [2:0] i_size, input i_wr, input i_rd, input [BEAT_WDT-1:0]i_min_len, input i_cont, output reg[DATA_WDT-1:0]o_data, output reg[31:0] o_addr, output reg o_dav );
localparam [1:0] IDLE = 0; localparam [1:0] BUSY = 1; localparam [1:0] NONSEQ = 2; localparam [1:0] SEQ = 3; localparam [1:0] OKAY = 0; localparam [1:0] ERROR = 1; localparam [1:0] SPLIT = 2; localparam [1:0] RETRY = 3; localparam [2:0] SINGLE = 0; localparam [2:0] INCR = 1; localparam [2:0] WRAP4 = 2; localparam [2:0] INCR4 = 3; localparam [2:0] WRAP8 = 4; localparam [2:0] INCR8 = 5; localparam [2:0] WRAP16 = 6; localparam [2:0] INCR16 = 7; localparam [2:0] BYTE = 0; localparam [2:0] HWORD = 1; localparam [2:0] WORD = 2; localparam [2:0] DWORD = 3; localparam [2:0] BIT128 = 4; localparam [2:0] BIT256 = 5; localparam [2:0] BIT512 = 6; localparam [2:0] BIT1024 = 7; localparam D = DATA_WDT-1; localparam B = BEAT_WDT-1; reg [4:0] burst_ctr; reg [B:0] beat_ctr; reg [1:0] gnt; reg [2:0] hburst; reg [D:0] hwdata [1:0]; reg [31:0] haddr [1:0]; reg [1:0] htrans [1:0]; reg [1:0] hwrite; reg [2:0] hsize [1:0]; reg [B:0] beat; reg pend_split; wire spl_ret_cyc_1 = gnt[1] && !i_hready && (i_hresp == RETRY || i_hresp == SPLIT); wire rd_wr = i_rd || (i_wr && i_dav); wire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10]; always @* {o_haddr, o_hburst, o_htrans, o_hwdata, o_hwrite, o_hsize} = {haddr[0], hburst, htrans[0], hwdata[1], hwrite[0], hsize[0]}; always @* o_next = (i_hready && i_hgrant && !pend_split); always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) gnt <= 2'd0; else if ( spl_ret_cyc_1 ) gnt <= 2'd0; else if ( i_hready ) gnt <= {gnt[0], i_hgrant}; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_hbusreq <= 1'd0; else o_hbusreq <= i_rd | i_wr; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) begin htrans[0] <= IDLE; pend_split <= 1'd0; end else if ( spl_ret_cyc_1 ) begin htrans[0] <= IDLE; pend_split <= 1'd1; end else if ( i_hready && i_hgrant ) begin pend_split <= 1'd0; if ( pend_split ) begin {hwdata[0], hwrite[0], hsize[0]} <= {hwdata[1], hwrite[1], hsize[1]}; haddr[0] <= haddr[1]; hburst <= compute_hburst (beat, haddr[1], hsize[1]); htrans[0] <= NONSEQ; burst_ctr <= compute_burst_ctr(beat, haddr[1], hsize[1]); beat_ctr <= beat; end else begin {hwdata[0], hwrite[0], hsize[0]} <= {i_data, i_wr, i_size}; if ( !i_cont && !rd_wr ) begin htrans[0] <= IDLE; end else if ( (!i_cont && rd_wr) || !gnt[0] || (burst_ctr == 1 && o_hburst != INCR) || htrans[0] == IDLE || b1k_spec ) begin haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size); hburst <= compute_hburst (!i_cont ? i_min_len : beat_ctr, !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); htrans[0] <= rd_wr ? NONSEQ : IDLE; burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); end else begin haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size); htrans[0] <= rd_wr ? SEQ : BUSY; burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr); beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr); end end end end always @ (posedge i_hclk) begin if ( i_hready && gnt[0] ) {hwdata[1], haddr[1], hwrite[1], hsize[1], htrans[1], beat} <= {hwdata[0], haddr[0], hwrite[0], hsize[0], htrans[0], beat_ctr}; end always @ (posedge i_hclk or negedge i_hreset_n) begin if ( !i_hreset_n ) o_dav <= 1'd0; else if ( gnt[1] && i_hready && (htrans[1] == SEQ || htrans[1] == NONSEQ) ) begin o_dav <= !hwrite[1]; o_data <= i_hrdata; o_addr <= haddr[1]; end else o_dav <= 1'd0; end function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_hburst = (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 : (val >= 8 && no_cross(addr, 7, sz)) ? INCR8 : (val >= 4 && no_cross(addr, 3, sz)) ? INCR4 : INCR; $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst); end endfunction function [4:0] compute_burst_ctr(input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_burst_ctr = (val >= 16 && no_cross(addr, 15, sz)) ? 5'd16 : (val >= 8 && no_cross(addr, 7, sz)) ? 5'd8 : (val >= 4 && no_cross(addr, 3, sz)) ? 5'd4 : 5'd0; $display($time, "val = %d, addr = %d, sz = %d, compute_burst_ctr = %d", val, addr, sz, compute_burst_ctr); end endfunction function no_cross(input [31:0] addr, input [31:0] val, input [2:0] sz); if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] ) no_cross = 1'd0; else no_cross = 1'd1; endfunction `ifdef SIM wire [31:0] beat_ctr_nxt = !i_cont ? (i_min_len - rd_wr) : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); initial begin $display($time,"DEBUG MODE ENABLED! PLEASE MONITOR CAPITAL SIGNALS IN VCD..."); end `ifndef STRING `define STRING reg [256*8-1:0] `endif `STRING HBURST; `STRING HTRANS; `STRING HSIZE; `STRING HRESP; always @* begin case(o_hburst) INCR: HBURST = "INCR"; INCR4: HBURST = "INCR4"; INCR8: HBURST = "INCR8"; INCR16: HBURST = "INCR16"; default:HBURST = "<----?????--->"; endcase case(o_htrans) SINGLE: HTRANS = "IDLE"; BUSY: HTRANS = "BUSY"; SEQ: HTRANS = "SEQ"; NONSEQ: HTRANS = "NONSEQ"; default:HTRANS = "<----?????--->"; endcase case(i_hresp) OKAY: HRESP = "OKAY"; ERROR: HRESP = "ERROR"; SPLIT: HRESP = "SPLIT"; RETRY: HRESP = "RETRY"; default: HRESP = "<---?????---->"; endcase case(o_hsize) BYTE : HSIZE = "8BIT"; HWORD : HSIZE = "16BIT"; WORD : HSIZE = "32BIT"; DWORD : HSIZE = "64BIT"; BIT128 : HSIZE = "128BIT"; BIT256 : HSIZE = "256BIT"; BIT512 : HSIZE = "512BIT"; BIT1024 : HSIZE = "1024BIT"; default : HSIZE = "<---?????--->"; endcase end `endif endmodule
0
2,589
data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v
100,152,754
ahb_master.v
v
399
123
[]
[]
[]
null
line:307: before: "("
null
1: b'%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:170: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\nwire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:328: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\n if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:254: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:256: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:259: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:260: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:262: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:268: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s NEQ generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:270: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr);\n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:271: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr);\n ^\n%Error: Exiting due to 10 warning(s)\n'
14
function
function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_hburst = (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 : (val >= 8 && no_cross(addr, 7, sz)) ? INCR8 : (val >= 4 && no_cross(addr, 3, sz)) ? INCR4 : INCR; $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst); end endfunction
function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz);
begin compute_hburst = (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 : (val >= 8 && no_cross(addr, 7, sz)) ? INCR8 : (val >= 4 && no_cross(addr, 3, sz)) ? INCR4 : INCR; $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst); end endfunction
0
2,590
data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v
100,152,754
ahb_master.v
v
399
123
[]
[]
[]
null
line:307: before: "("
null
1: b'%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:170: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\nwire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:328: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\n if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:254: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:256: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:259: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:260: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:262: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:268: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s NEQ generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:270: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr);\n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:271: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr);\n ^\n%Error: Exiting due to 10 warning(s)\n'
14
function
function [4:0] compute_burst_ctr(input [B:0] val, input [31:0] addr, input [2:0] sz); begin compute_burst_ctr = (val >= 16 && no_cross(addr, 15, sz)) ? 5'd16 : (val >= 8 && no_cross(addr, 7, sz)) ? 5'd8 : (val >= 4 && no_cross(addr, 3, sz)) ? 5'd4 : 5'd0; $display($time, "val = %d, addr = %d, sz = %d, compute_burst_ctr = %d", val, addr, sz, compute_burst_ctr); end endfunction
function [4:0] compute_burst_ctr(input [B:0] val, input [31:0] addr, input [2:0] sz);
begin compute_burst_ctr = (val >= 16 && no_cross(addr, 15, sz)) ? 5'd16 : (val >= 8 && no_cross(addr, 7, sz)) ? 5'd8 : (val >= 4 && no_cross(addr, 3, sz)) ? 5'd4 : 5'd0; $display($time, "val = %d, addr = %d, sz = %d, compute_burst_ctr = %d", val, addr, sz, compute_burst_ctr); end endfunction
0
2,591
data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v
100,152,754
ahb_master.v
v
399
123
[]
[]
[]
null
line:307: before: "("
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1: b'%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:170: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\nwire b1k_spec = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:328: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n : ... In instance ahb_master\n if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:254: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:256: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:259: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:260: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:262: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); \n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:268: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s NEQ generates 1 bits.\n : ... In instance ahb_master\n haddr[0] <= haddr[0] + ((htrans[0] != BUSY) << i_size);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:270: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr);\n ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:271: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n : ... In instance ahb_master\n beat_ctr <= o_hburst == INCR ? beat_ctr : (beat_ctr - rd_wr);\n ^\n%Error: Exiting due to 10 warning(s)\n'
14
function
function no_cross(input [31:0] addr, input [31:0] val, input [2:0] sz); if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] ) no_cross = 1'd0; else no_cross = 1'd1; endfunction
function no_cross(input [31:0] addr, input [31:0] val, input [2:0] sz);
if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] ) no_cross = 1'd0; else no_cross = 1'd1; endfunction
0
2,592
data/full_repos/permissive/100153725/gateware/ip_repo/USB_Device_1.0/src/usb_device.v
100,153,725
usb_device.v
v
71
53
[]
[]
[]
[(4, 71)]
null
null
1: b"%Error: data/full_repos/permissive/100153725/gateware/ip_repo/USB_Device_1.0/src/usb_device.v:41: Cannot find file containing module: 'usb_ulpi'\nusb_ulpi usb_ulpi(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100153725/gateware/ip_repo/USB_Device_1.0/src,data/full_repos/permissive/100153725/usb_ulpi\n data/full_repos/permissive/100153725/gateware/ip_repo/USB_Device_1.0/src,data/full_repos/permissive/100153725/usb_ulpi.v\n data/full_repos/permissive/100153725/gateware/ip_repo/USB_Device_1.0/src,data/full_repos/permissive/100153725/usb_ulpi.sv\n usb_ulpi\n usb_ulpi.v\n usb_ulpi.sv\n obj_dir/usb_ulpi\n obj_dir/usb_ulpi.v\n obj_dir/usb_ulpi.sv\n%Error: Exiting due to 1 error(s)\n"
16
module
module usb_device # ( parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_ADDR_WIDTH = 8 ) ( input wire [31 : 0] axi_awaddr, input wire [2 : 0] axi_awprot, input wire axi_awvalid, output wire axi_awready, input wire [31 : 0] axi_wdata, input wire [3 : 0] axi_wstrb, input wire axi_wvalid, output wire axi_wready, output wire [1 : 0] axi_bresp, output wire axi_bvalid, input wire axi_bready, input wire [31 : 0] axi_araddr, input wire [2 : 0] axi_arprot, input wire axi_arvalid, output wire axi_arready, output wire [31 : 0] axi_rdata, output wire [1 : 0] axi_rresp, output wire axi_rvalid, input wire axi_rready, inout [7:0] data, input dir, input nxt, output stp, output [7:0] debug, input reset, input usb_clk, input usb_rst ); usb_ulpi usb_ulpi( .data(data), .dir(dir), .nxt(nxt), .stp(stp), .reset(reset), .axi_awaddr(axi_awaddr), .axi_awprot(axi_awprot), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), .axi_bresp(axi_bresp), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready), .axi_araddr(axi_araddr), .axi_arprot(axi_arprot), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready), .debug(debug), .usb_clk(usb_clk), .usb_rst(usb_rst) ); endmodule
module usb_device # ( parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_ADDR_WIDTH = 8 ) ( input wire [31 : 0] axi_awaddr, input wire [2 : 0] axi_awprot, input wire axi_awvalid, output wire axi_awready, input wire [31 : 0] axi_wdata, input wire [3 : 0] axi_wstrb, input wire axi_wvalid, output wire axi_wready, output wire [1 : 0] axi_bresp, output wire axi_bvalid, input wire axi_bready, input wire [31 : 0] axi_araddr, input wire [2 : 0] axi_arprot, input wire axi_arvalid, output wire axi_arready, output wire [31 : 0] axi_rdata, output wire [1 : 0] axi_rresp, output wire axi_rvalid, input wire axi_rready, inout [7:0] data, input dir, input nxt, output stp, output [7:0] debug, input reset, input usb_clk, input usb_rst );
usb_ulpi usb_ulpi( .data(data), .dir(dir), .nxt(nxt), .stp(stp), .reset(reset), .axi_awaddr(axi_awaddr), .axi_awprot(axi_awprot), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), .axi_bresp(axi_bresp), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready), .axi_araddr(axi_araddr), .axi_arprot(axi_arprot), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready), .debug(debug), .usb_clk(usb_clk), .usb_rst(usb_rst) ); endmodule
9
2,595
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
[]
[]
[]
null
line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module BUF(A, Y); parameter tpdmin = 10; parameter tpdmax = 14.2; input A; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = A; endmodule
module BUF(A, Y);
parameter tpdmin = 10; parameter tpdmax = 14.2; input A; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = A; endmodule
0
2,596
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
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line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module NOT(A, Y); parameter tpdmin = 5; parameter tpdmax = 7.1; input A; output Y; assign #(tpdmin:tpdmax:tpdmax) Y = ~A; endmodule
module NOT(A, Y);
parameter tpdmin = 5; parameter tpdmax = 7.1; input A; output Y; assign #(tpdmin:tpdmax:tpdmax) Y = ~A; endmodule
0
2,597
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
[]
[]
[]
null
line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module NAND(A, B, Y); parameter tpdmin = 1.5; parameter tpdmax = 11.1; input A, B; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = ~(A & B); endmodule
module NAND(A, B, Y);
parameter tpdmin = 1.5; parameter tpdmax = 11.1; input A, B; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = ~(A & B); endmodule
0
2,598
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
[]
[]
[]
null
line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module NOR(A, B, Y); parameter tpdmin = 8.1; parameter tpdmax = 11.4; input A, B; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = ~(A | B); endmodule
module NOR(A, B, Y);
parameter tpdmin = 8.1; parameter tpdmax = 11.4; input A, B; output Y; assign # (tpdmin:tpdmax:tpdmax) Y = ~(A | B); endmodule
0
2,599
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
[]
[]
[]
null
line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module DFF(C, D, Q); parameter tpmin = 1.5; parameter tptyp = 7.7; parameter tpmax = 10.5; input C, D; output reg Q; always @(posedge C) # (tpmin:tptyp:tpmax) Q <= D; endmodule
module DFF(C, D, Q);
parameter tpmin = 1.5; parameter tptyp = 7.7; parameter tpmax = 10.5; input C, D; output reg Q; always @(posedge C) # (tpmin:tptyp:tpmax) Q <= D; endmodule
0
2,600
data/full_repos/permissive/100331186/lib/cmos_tech.v
100,331,186
cmos_tech.v
v
62
54
[]
[]
[]
null
line:8: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
20
module
module DFFSR(C, D, Q, S, R); parameter tpmin = 1.5; parameter tptyp = 7.7; parameter tpmax = 10.5; input C, D, S, R; output reg Q; always @(posedge C, posedge S, posedge R) if (S) # (tpmin:tptyp:tpmax) Q <= 1'b1; else if (R) # (tpmin:tptyp:tpmax) Q <= 1'b0; else # (tpmin:tptyp:tpmax) Q <= D; endmodule
module DFFSR(C, D, Q, S, R);
parameter tpmin = 1.5; parameter tptyp = 7.7; parameter tpmax = 10.5; input C, D, S, R; output reg Q; always @(posedge C, posedge S, posedge R) if (S) # (tpmin:tptyp:tpmax) Q <= 1'b1; else if (R) # (tpmin:tptyp:tpmax) Q <= 1'b0; else # (tpmin:tptyp:tpmax) Q <= D; endmodule
0
2,601
data/full_repos/permissive/100331186/tarea2/modulos/registro32bits.v
100,331,186
registro32bits.v
v
95
99
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line:54: before: "for"
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1: b"%Error: data/full_repos/permissive/100331186/tarea2/modulos/registro32bits.v:55: syntax error, unexpected assign, expecting '('\n assign sinint[x]=0\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
22
module
module registro32bits ( input clk, input enb, input dir, input s_in, input [1:0] modo, input [31:0] d, output [31:0] q, output s_out ); reg s_out; reg [7:0] s_in_interno; wire [7:0] s_out_interno; wire [1:0] modo_interno; assign modo_interno = (modo == 2'b01) ? 2'b00 : modo; for assign sinint[x]=0 registro r0(clk, enb, dir, s_in_interno[0], modo_interno, d[31:28], q[31:28], s_out_interno[0]); registro r1(clk, enb, dir, s_in_interno[1], modo_interno, d[27:24], q[27:24], s_out_interno[1]); registro r2(clk, enb, dir, s_in_interno[2], modo_interno, d[23:20], q[23:20], s_out_interno[2]); registro r3(clk, enb, dir, s_in_interno[3], modo_interno, d[19:16], q[19:16], s_out_interno[3]); registro r4(clk, enb, dir, s_in_interno[4], modo_interno, d[15:12], q[15:12], s_out_interno[4]); registro r5(clk, enb, dir, s_in_interno[5], modo_interno, d[11:8], q[11:8], s_out_interno[5]); registro r6(clk, enb, dir, s_in_interno[6], modo_interno, d[7:4], q[7:4], s_out_interno[6]); registro r7(clk, enb, dir, s_in_interno[7], modo_interno, d[3:0], q[3:0], s_out_interno[7]); always @ (posedge clk) begin s_out <= modo == 2'b00 ? dir ? s_out_interno[7] : s_out_interno[0] : 0; end always @ (*) begin s_in_interno[0] = (modo == 2'b01) ? dir ? q[0] : q[27] : dir ? s_in : q[27]; s_in_interno[1] = dir ? q[28] : q[23]; s_in_interno[2] = dir ? q[24] : q[19]; s_in_interno[3] = dir ? q[20] : q[15]; s_in_interno[4] = dir ? q[16] : q[11]; s_in_interno[5] = dir ? q[12] : q[7]; s_in_interno[6] = dir ? q[8] : q[3]; s_in_interno[7] = (modo == 2'b01) ? dir ? q[4] : q[31] : dir ? q[4] : s_in; end endmodule
module registro32bits ( input clk, input enb, input dir, input s_in, input [1:0] modo, input [31:0] d, output [31:0] q, output s_out );
reg s_out; reg [7:0] s_in_interno; wire [7:0] s_out_interno; wire [1:0] modo_interno; assign modo_interno = (modo == 2'b01) ? 2'b00 : modo; for assign sinint[x]=0 registro r0(clk, enb, dir, s_in_interno[0], modo_interno, d[31:28], q[31:28], s_out_interno[0]); registro r1(clk, enb, dir, s_in_interno[1], modo_interno, d[27:24], q[27:24], s_out_interno[1]); registro r2(clk, enb, dir, s_in_interno[2], modo_interno, d[23:20], q[23:20], s_out_interno[2]); registro r3(clk, enb, dir, s_in_interno[3], modo_interno, d[19:16], q[19:16], s_out_interno[3]); registro r4(clk, enb, dir, s_in_interno[4], modo_interno, d[15:12], q[15:12], s_out_interno[4]); registro r5(clk, enb, dir, s_in_interno[5], modo_interno, d[11:8], q[11:8], s_out_interno[5]); registro r6(clk, enb, dir, s_in_interno[6], modo_interno, d[7:4], q[7:4], s_out_interno[6]); registro r7(clk, enb, dir, s_in_interno[7], modo_interno, d[3:0], q[3:0], s_out_interno[7]); always @ (posedge clk) begin s_out <= modo == 2'b00 ? dir ? s_out_interno[7] : s_out_interno[0] : 0; end always @ (*) begin s_in_interno[0] = (modo == 2'b01) ? dir ? q[0] : q[27] : dir ? s_in : q[27]; s_in_interno[1] = dir ? q[28] : q[23]; s_in_interno[2] = dir ? q[24] : q[19]; s_in_interno[3] = dir ? q[20] : q[15]; s_in_interno[4] = dir ? q[16] : q[11]; s_in_interno[5] = dir ? q[12] : q[7]; s_in_interno[6] = dir ? q[8] : q[3]; s_in_interno[7] = (modo == 2'b01) ? dir ? q[4] : q[31] : dir ? q[4] : s_in; end endmodule
0
2,602
data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v
100,331,186
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81
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1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/registro/test1.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test1);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:48: Unsupported: Ignoring delay on this delayed statement.\n #0 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:49: Unsupported: Ignoring delay on this delayed statement.\n #0 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:50: Unsupported: Ignoring delay on this delayed statement.\n #0 s_in = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:51: Unsupported: Ignoring delay on this delayed statement.\n #0 d = 4\'b0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 modo = 2\'b00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 s_in = 2\'b0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:59: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:60: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:62: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2 s_in = 2\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:65: Unsupported: Ignoring delay on this delayed statement.\n #8 $finish;\n ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test1.v:70: Unsupported or unknown PLI call: $monitor\n $monitor(\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
24
module
module test1; initial begin $display("Test Bench 1 registro"); $display("Prueba la funcionalidad de carga en serie a la izquierda"); $display("********************************************************"); $dumpfile("tests/registro/test1.vcd"); $dumpvars(0, test1); end reg clk = 0; reg enb = 1; reg dir = 0; reg s_in = 1; reg [1:0] modo = 2'b10; reg [3:0] d = 4'b0000; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 0; #0 s_in = 1; #0 d = 4'b0000; #1; #2 modo = 2'b00; #10 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #8 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out ); end endmodule
module test1;
initial begin $display("Test Bench 1 registro"); $display("Prueba la funcionalidad de carga en serie a la izquierda"); $display("********************************************************"); $dumpfile("tests/registro/test1.vcd"); $dumpvars(0, test1); end reg clk = 0; reg enb = 1; reg dir = 0; reg s_in = 1; reg [1:0] modo = 2'b10; reg [3:0] d = 4'b0000; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 0; #0 s_in = 1; #0 d = 4'b0000; #1; #2 modo = 2'b00; #10 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #2 s_in = 2'b1; #2 s_in = 2'b0; #8 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out ); end endmodule
0
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data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v
100,331,186
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v
82
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1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/registro/test4.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test4);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:49: Unsupported: Ignoring delay on this delayed statement.\n #0 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:50: Unsupported: Ignoring delay on this delayed statement.\n #0 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:51: Unsupported: Ignoring delay on this delayed statement.\n #0 s_in = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:52: Unsupported: Ignoring delay on this delayed statement.\n #0 d = 4\'b0110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:55: Unsupported: Ignoring delay on this delayed statement.\n #2 modo = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10 s_in = 2\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10 s_in = 2\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10 s_in = 2\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'b0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'bxxxx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test4.v:72: Unsupported or unknown PLI call: $monitor\n $monitor(\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
27
module
module test4; initial begin $display("Test Bench 4 registro"); $display("Prueba la funcionalidad de rotacion circular a la derecha"); $display("*********************************************************"); $dumpfile("tests/registro/test4.vcd"); $dumpvars(0, test4); end reg clk = 0; reg enb = 1; reg dir = 1; reg s_in = 0; reg [1:0] modo = 2'b01; reg [3:0] d = 4'b0110; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 1; #0 s_in = 0; #0 d = 4'b0110; #2 modo = 2'b01; #10 s_in = 2'b0; #10 s_in = 2'b1; #10 s_in = 2'bx; #10 d = 4'b0000; #10 d = 4'b1111; #10 d = 4'bxxxx; #10 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out); end endmodule
module test4;
initial begin $display("Test Bench 4 registro"); $display("Prueba la funcionalidad de rotacion circular a la derecha"); $display("*********************************************************"); $dumpfile("tests/registro/test4.vcd"); $dumpvars(0, test4); end reg clk = 0; reg enb = 1; reg dir = 1; reg s_in = 0; reg [1:0] modo = 2'b01; reg [3:0] d = 4'b0110; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 1; #0 s_in = 0; #0 d = 4'b0110; #2 modo = 2'b01; #10 s_in = 2'b0; #10 s_in = 2'b1; #10 s_in = 2'bx; #10 d = 4'b0000; #10 d = 4'b1111; #10 d = 4'bxxxx; #10 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out); end endmodule
0
2,604
data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v
100,331,186
test5.v
v
86
81
[]
[]
[]
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line:71: before: "$"
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1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/registro/test5.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test5);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:49: Unsupported: Ignoring delay on this delayed statement.\n #0 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:50: Unsupported: Ignoring delay on this delayed statement.\n #0 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:51: Unsupported: Ignoring delay on this delayed statement.\n #0 s_in = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:52: Unsupported: Ignoring delay on this delayed statement.\n #0 d = 4\'b0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:56: Unsupported: Ignoring delay on this delayed statement.\n #2 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'b0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:60: Unsupported: Ignoring delay on this delayed statement.\n #2 enb = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 enb = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'bxxxx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 4\'b0x0x;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:68: Unsupported: Ignoring delay on this delayed statement.\n #4 d = 4\'b101x;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:69: Unsupported: Ignoring delay on this delayed statement.\n #4 d = 4\'bx10x;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:76: Unsupported or unknown PLI call: $monitor\n $monitor(\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
28
module
module test5; initial begin $display("Test Bench 5 registro"); $display("Prueba la funcionalidad de carga en paralelo"); $display("********************************************"); $dumpfile("tests/registro/test5.vcd"); $dumpvars(0, test5); end reg clk = 0; reg enb = 1; reg dir = 1; reg s_in = 0; reg [1:0] modo = 2'b01; reg [3:0] d = 4'b0110; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 1; #0 s_in = 0; #0 d = 4'b0000; #1; #2 modo = 2'b10; #10 d = 4'b0000; #2 enb = 0; #2 d = 4'b1111; #10 enb = 1; #2 d = 4'b1111; #10 d = 4'bxxxx; #10 d = 4'b0x0x; #4 d = 4'b101x; #4 d = 4'bx10x; #10 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out); end endmodule
module test5;
initial begin $display("Test Bench 5 registro"); $display("Prueba la funcionalidad de carga en paralelo"); $display("********************************************"); $dumpfile("tests/registro/test5.vcd"); $dumpvars(0, test5); end reg clk = 0; reg enb = 1; reg dir = 1; reg s_in = 0; reg [1:0] modo = 2'b01; reg [3:0] d = 4'b0110; wire [3:0] q; wire s_out; registro registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 1; #0 s_in = 0; #0 d = 4'b0000; #1; #2 modo = 2'b10; #10 d = 4'b0000; #2 enb = 0; #2 d = 4'b1111; #10 enb = 1; #2 d = 4'b1111; #10 d = 4'bxxxx; #10 d = 4'b0x0x; #4 d = 4'b101x; #4 d = 4'bx10x; #10 $finish; end initial begin $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n"); $monitor( "%d", $time, "\t%b", dir, "\t%b", s_in, "\t%2b", modo, "\t%4b", d, "\t%4b", q, "\t%b", s_out); end endmodule
0
2,605
data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v
100,331,186
test1.v
v
140
81
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line:124: before: "$"
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1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/registro32bits/test1.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test1);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:49: Unsupported: Ignoring delay on this delayed statement.\n #0 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:50: Unsupported: Ignoring delay on this delayed statement.\n #0 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:51: Unsupported: Ignoring delay on this delayed statement.\n #0 s_in = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:52: Unsupported: Ignoring delay on this delayed statement.\n #0 d = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:53: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:56: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffffffff;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:57: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfffffff0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:58: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffffff00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:59: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfffff000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:60: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffff0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfff00000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:62: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hff000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hf0000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:64: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'h00000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:66: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hf0000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:67: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hff000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:68: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfff00000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:69: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffff0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:70: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfffff000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:71: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffffff00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:72: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hfffffff0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:73: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'hffffffff;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:76: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:77: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'b0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:78: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'b0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:79: Unsupported: Ignoring delay on this delayed statement.\n #2 d = 32\'b1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:82: Unsupported: Ignoring delay on this delayed statement.\n #4 d = 32\'hffaebc13;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:86: Unsupported: Ignoring delay on this delayed statement.\n #4 s_in = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:87: Unsupported: Ignoring delay on this delayed statement.\n #4 modo = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:90: Unsupported: Ignoring delay on this delayed statement.\n #100 s_in = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:91: Unsupported: Ignoring delay on this delayed statement.\n #0 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:94: Unsupported: Ignoring delay on this delayed statement.\n #120 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:95: Unsupported: Ignoring delay on this delayed statement.\n #4 d = 32\'haf00f050;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:96: Unsupported: Ignoring delay on this delayed statement.\n #4 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:97: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:98: Unsupported: Ignoring delay on this delayed statement.\n #4 modo = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:100: Unsupported: Ignoring delay on this delayed statement.\n #120 modo = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:101: Unsupported: Ignoring delay on this delayed statement.\n #0 d = 32\'h000aa000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:102: Unsupported: Ignoring delay on this delayed statement.\n #4 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:103: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:104: Unsupported: Ignoring delay on this delayed statement.\n #4 modo = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:109: Unsupported: Ignoring delay on this delayed statement.\n #20 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:110: Unsupported: Ignoring delay on this delayed statement.\n #30 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:112: Unsupported: Ignoring delay on this delayed statement.\n #20 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:113: Unsupported: Ignoring delay on this delayed statement.\n #30 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:115: Unsupported: Ignoring delay on this delayed statement.\n #20 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n #30 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:118: Unsupported: Ignoring delay on this delayed statement.\n #20 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:119: Unsupported: Ignoring delay on this delayed statement.\n #30 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:121: Unsupported: Ignoring delay on this delayed statement.\n #20 dir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:122: Unsupported: Ignoring delay on this delayed statement.\n #30 dir = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:124: Unsupported: Ignoring delay on this delayed statement.\n #120 $finish;\n ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:129: Unsupported or unknown PLI call: $monitor\n $monitor(\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 53 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
29
module
module test1; initial begin $display("Test Bench 1 registro32bits"); $display("Prueba la funcionalidad de carga en serie a la izquierda"); $display("********************************************************"); $dumpfile("tests/registro32bits/test1.vcd"); $dumpvars(0, test1); end reg clk = 0; reg enb = 1; reg dir; reg s_in; reg [1:0] modo = 2'b0; reg [31:0] d = 4'h0; wire [31:0] q; wire s_out; registro32bits registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 0; #0 s_in = 1; #0 d = 32'h0; #4; #2 d = 32'hffffffff; #2 d = 32'hfffffff0; #2 d = 32'hffffff00; #2 d = 32'hfffff000; #2 d = 32'hffff0000; #2 d = 32'hfff00000; #2 d = 32'hff000000; #2 d = 32'hf0000000; #2 d = 32'h00000000; #2 d = 32'hf0000000; #2 d = 32'hff000000; #2 d = 32'hfff00000; #2 d = 32'hffff0000; #2 d = 32'hfffff000; #2 d = 32'hffffff00; #2 d = 32'hfffffff0; #2 d = 32'hffffffff; #2 d = 32'b0001; #2 d = 32'b0010; #2 d = 32'b0100; #2 d = 32'b1000; #4 d = 32'hffaebc13; #4 s_in = 0; #4 modo = 2'b00; #100 s_in = 1; #0 dir = 1; #120 modo = 2'b10; #4 d = 32'haf00f050; #4 dir = 0; #4; #4 modo = 2'b01; #120 modo = 2'b10; #0 d = 32'h000aa000; #4 dir = 0; #4; #4 modo = 2'b01; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #120 $finish; end initial begin $display("\t\ttiempo dir s_in modo d \t\t\t\tq \t\t\t\t s_out\n"); $monitor( "%d", $time, "\t%b ", dir, "%b ", s_in, "%2b ", modo, "%4b\t", d, "%4b ", q, "%b", s_out ); end endmodule
module test1;
initial begin $display("Test Bench 1 registro32bits"); $display("Prueba la funcionalidad de carga en serie a la izquierda"); $display("********************************************************"); $dumpfile("tests/registro32bits/test1.vcd"); $dumpvars(0, test1); end reg clk = 0; reg enb = 1; reg dir; reg s_in; reg [1:0] modo = 2'b0; reg [31:0] d = 4'h0; wire [31:0] q; wire s_out; registro32bits registro1(clk, enb, dir, s_in, modo, d, q, s_out); always #1 clk = ~clk; initial begin #0 modo = 2'b10; #0 dir = 0; #0 s_in = 1; #0 d = 32'h0; #4; #2 d = 32'hffffffff; #2 d = 32'hfffffff0; #2 d = 32'hffffff00; #2 d = 32'hfffff000; #2 d = 32'hffff0000; #2 d = 32'hfff00000; #2 d = 32'hff000000; #2 d = 32'hf0000000; #2 d = 32'h00000000; #2 d = 32'hf0000000; #2 d = 32'hff000000; #2 d = 32'hfff00000; #2 d = 32'hffff0000; #2 d = 32'hfffff000; #2 d = 32'hffffff00; #2 d = 32'hfffffff0; #2 d = 32'hffffffff; #2 d = 32'b0001; #2 d = 32'b0010; #2 d = 32'b0100; #2 d = 32'b1000; #4 d = 32'hffaebc13; #4 s_in = 0; #4 modo = 2'b00; #100 s_in = 1; #0 dir = 1; #120 modo = 2'b10; #4 d = 32'haf00f050; #4 dir = 0; #4; #4 modo = 2'b01; #120 modo = 2'b10; #0 d = 32'h000aa000; #4 dir = 0; #4; #4 modo = 2'b01; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #20 dir = 1; #30 dir = 0; #120 $finish; end initial begin $display("\t\ttiempo dir s_in modo d \t\t\t\tq \t\t\t\t s_out\n"); $monitor( "%d", $time, "\t%b ", dir, "%b ", s_in, "%2b ", modo, "%4b\t", d, "%4b ", q, "%b", s_out ); end endmodule
0
2,606
data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v
100,331,186
registro.v
v
76
81
[]
[]
[]
[(28, 75)]
null
null
1: b"%Error: data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:48: Duplicate declaration of signal: 's_out'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg s_out;\n ^~~~~\n data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:43: ... Location of original declaration\n output s_out \n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:49: Duplicate declaration of signal: 'q'\n reg [3:0] q;\n ^\n data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:42: ... Location of original declaration\n output [3:0] q, \n ^\n%Error: Exiting due to 2 error(s)\n"
30
module
module registro ( input clk, input enb, input dir, input s_in, input [1:0] modo, input [3:0] d, output [3:0] q, output s_out ); reg s_out; reg [3:0] q; always @(posedge clk) begin if (modo == 2'b00) s_out <= dir ? q[0] : q[3]; else s_out <= 0; if (enb) begin if (modo == 2'b00) q <= dir ? {s_in, q[3:1]} : {q[2:0], s_in}; else if (modo == 2'b01) q <= dir ? {q[0], q[3:1]} : {q[2:0], q[3]}; else if (modo == 2'b10) q <= d; end end endmodule
module registro ( input clk, input enb, input dir, input s_in, input [1:0] modo, input [3:0] d, output [3:0] q, output s_out );
reg s_out; reg [3:0] q; always @(posedge clk) begin if (modo == 2'b00) s_out <= dir ? q[0] : q[3]; else s_out <= 0; if (enb) begin if (modo == 2'b00) q <= dir ? {s_in, q[3:1]} : {q[2:0], s_in}; else if (modo == 2'b01) q <= dir ? {q[0], q[3:1]} : {q[2:0], q[3]}; else if (modo == 2'b10) q <= d; end end endmodule
0
2,607
data/full_repos/permissive/100331186/tarea3/modulos/ffD.v
100,331,186
ffD.v
v
90
81
[]
[]
[]
null
line:70: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:70: Unsupported: Ignoring delay on this delayed statement.\n if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:71: Unsupported: Ignoring delay on this delayed statement.\n else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:77: Unsupported: Ignoring delay on this delayed statement.\n #(tplhmin:tplhtyp:tplhmax) q <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:79: Unsupported: Ignoring delay on this delayed statement.\n #(tphlmin:tphltyp:tphlmax) q <= 0;\n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:39: Duplicate declaration of signal: \'d\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire d;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:32: ... Location of original declaration\n input d,\n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:40: Duplicate declaration of signal: \'clk\'\n wire clk;\n ^~~\n data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:33: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:43: Duplicate declaration of signal: \'q\'\n reg q;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:36: ... Location of original declaration\n output q,\n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:44: Duplicate declaration of signal: \'notq\'\n reg notq;\n ^~~~\n data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:37: ... Location of original declaration\n output notq\n ^~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
38
module
module ffD( input d, input clk, input notpreset, input notclear, output q, output notq ); wire d; wire clk; wire preset; wire clear; reg q; reg notq; parameter tplhmin = 1.5; parameter tplhtyp = 5.8; parameter tplhmax = 9.3; parameter tphlmin = 1.5; parameter tphltyp = 6.5; parameter tphlmax = 11.4; parameter tplhclkmin = 1.5; parameter tplhclktyp = 7.7; parameter tplhclkmax = 10.5; parameter tphlclkmin = 1.5; parameter tphlclktyp = 7.3; parameter tphlclkmax = 9.7; parameter Vcc = 3.3; parameter Cl = 0.05; integer c; initial c = 0; always @ (posedge clk) begin if (notpreset & notclear) begin if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d; else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d; end end always @ (*) begin if (~notpreset & notclear) begin #(tplhmin:tplhtyp:tplhmax) q <= 1; end else if (notpreset & ~notclear) begin #(tphlmin:tphltyp:tphlmax) q <= 0; end end always @ (q) begin notq <= ~q; c = c+1; $display(" Potencia disipada por el Flip Flop: %f", c * Cl * Vcc); end endmodule
module ffD( input d, input clk, input notpreset, input notclear, output q, output notq );
wire d; wire clk; wire preset; wire clear; reg q; reg notq; parameter tplhmin = 1.5; parameter tplhtyp = 5.8; parameter tplhmax = 9.3; parameter tphlmin = 1.5; parameter tphltyp = 6.5; parameter tphlmax = 11.4; parameter tplhclkmin = 1.5; parameter tplhclktyp = 7.7; parameter tplhclkmax = 10.5; parameter tphlclkmin = 1.5; parameter tphlclktyp = 7.3; parameter tphlclkmax = 9.7; parameter Vcc = 3.3; parameter Cl = 0.05; integer c; initial c = 0; always @ (posedge clk) begin if (notpreset & notclear) begin if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d; else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d; end end always @ (*) begin if (~notpreset & notclear) begin #(tplhmin:tplhtyp:tplhmax) q <= 1; end else if (notpreset & ~notclear) begin #(tphlmin:tphltyp:tphlmax) q <= 0; end end always @ (q) begin notq <= ~q; c = c+1; $display(" Potencia disipada por el Flip Flop: %f", c * Cl * Vcc); end endmodule
0
2,608
data/full_repos/permissive/100331186/tarea3/modulos/mux.v
100,331,186
mux.v
v
94
83
[]
[]
[]
null
line:70: before: ":"
null
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(tdismin:tdismax:tdismax) y = 1\'bz;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:75: Unsupported: Ignoring delay on this delayed statement.\n #(tpdmin:tpdmax:tpdmax) y = aRet[s];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:78: Unsupported: Ignoring delay on this delayed statement.\n #(tpdmin:tpdmax:tpdmax) y = aRet[s];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:85: Unsupported: Ignoring delay on this delayed statement.\n #tpin aRet = a;\n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:39: Duplicate declaration of signal: \'s\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire s;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/mux.v:34: ... Location of original declaration\n input s, \n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:40: Duplicate declaration of signal: \'a\'\n wire [1:0] a;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/mux.v:35: ... Location of original declaration\n input [1:0] a, \n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:41: Duplicate declaration of signal: \'notoe\'\n wire notoe;\n ^~~~~\n data/full_repos/permissive/100331186/tarea3/modulos/mux.v:36: ... Location of original declaration\n input notoe, \n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:42: Duplicate declaration of signal: \'y\'\n reg y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/mux.v:37: ... Location of original declaration\n output y\n ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n'
39
module
module mux( input s, input [1:0] a, input notoe, output y ); wire s; wire [1:0] a; wire notoe; reg y; parameter tpin = 0.25; parameter tpdmin = 1.8; parameter tpdmax = 5.3; parameter tenmin = 2; parameter tenmax = 5.3; parameter tdismin = 1.6; parameter tdismax = 5.5; parameter Vcc = 3.3; parameter Cl = 0.05; integer c; initial c = 0; reg [1:0] aRet; always @ (*) begin if (notoe) begin #(tdismin:tdismax:tdismax) y = 1'bz; end else begin if (a == 1'bz) begin #(tpdmin:tpdmax:tpdmax) y = aRet[s]; end else begin #(tpdmin:tpdmax:tpdmax) y = aRet[s]; end end end always @ (a) begin #tpin aRet = a; end always @ (y) begin c = c+1; end endmodule
module mux( input s, input [1:0] a, input notoe, output y );
wire s; wire [1:0] a; wire notoe; reg y; parameter tpin = 0.25; parameter tpdmin = 1.8; parameter tpdmax = 5.3; parameter tenmin = 2; parameter tenmax = 5.3; parameter tdismin = 1.6; parameter tdismax = 5.5; parameter Vcc = 3.3; parameter Cl = 0.05; integer c; initial c = 0; reg [1:0] aRet; always @ (*) begin if (notoe) begin #(tdismin:tdismax:tdismax) y = 1'bz; end else begin if (a == 1'bz) begin #(tpdmin:tpdmax:tpdmax) y = aRet[s]; end else begin #(tpdmin:tpdmax:tpdmax) y = aRet[s]; end end end always @ (a) begin #tpin aRet = a; end always @ (y) begin c = c+1; end endmodule
0
2,609
data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v
100,331,186
nandGate.v
v
57
83
[]
[]
[]
null
line:50: before: ":"
null
1: b"%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'a'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire a, b, y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:33: ... Location of original declaration\n input a, \n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'b'\n wire a, b, y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:34: ... Location of original declaration\n input b, \n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'y'\n wire a, b, y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:35: ... Location of original declaration\n output y \n ^\n%Error: Exiting due to 3 error(s)\n"
40
module
module nandGate ( input a, input b, output y ); parameter tpdmin = 1.5; parameter tpdmax = 11.1; parameter Vcc = 3.3; parameter Cl = 0.05; wire a, b, y; integer c; initial c=0; assign #(tpdmin:tpdmax:tpdmax) y = !(a & b); always @ (y) begin c=c+1; end endmodule
module nandGate ( input a, input b, output y );
parameter tpdmin = 1.5; parameter tpdmax = 11.1; parameter Vcc = 3.3; parameter Cl = 0.05; wire a, b, y; integer c; initial c=0; assign #(tpdmin:tpdmax:tpdmax) y = !(a & b); always @ (y) begin c=c+1; end endmodule
0
2,610
data/full_repos/permissive/100331186/tarea3/modulos/notGate.v
100,331,186
notGate.v
v
57
81
[]
[]
[]
null
line:50: before: ":"
null
1: b"%Error: data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:44: Duplicate declaration of signal: 'a'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire a, y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:32: ... Location of original declaration\n input a, \n ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:44: Duplicate declaration of signal: 'y'\n wire a, y;\n ^\n data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:33: ... Location of original declaration\n output y \n ^\n%Error: Exiting due to 2 error(s)\n"
42
module
module notGate ( input a, output y ); parameter tpdmin = 5; parameter tpdmax = 7.1; parameter Vcc = 3.3; parameter Cl = 0.0015; wire a, y; integer c; initial c = 0; assign #(tpdmin:tpdmax:tpdmax) y = ~a; always @ (y) begin c=c+1; end endmodule
module notGate ( input a, output y );
parameter tpdmin = 5; parameter tpdmax = 7.1; parameter Vcc = 3.3; parameter Cl = 0.0015; wire a, y; integer c; initial c = 0; assign #(tpdmin:tpdmax:tpdmax) y = ~a; always @ (y) begin c=c+1; end endmodule
0