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2,754 | data/full_repos/permissive/100975158/ProcessadorQuartus/Controle.v | 100,975,158 | Controle.v | v | 118 | 174 | [] | [] | [] | [(1, 117)] | null | data/verilator_xmls/316a03c4-fc23-4e70-8d71-5c71a69752da.xml | null | 191 | module | module Controle(input wire [5:0] opcode,
input wire [5:0] funct,
output reg [1:0] c_ALUOp,
output reg c_fonte_ula,
output reg [2:0] c_desvio,
output reg [1:0] c_memoria,
output reg c_memtoreg,
output reg c_escrever_reg,
output reg c_reg_destino,
output reg c_jal
);
always @ ( * ) begin
c_jal <= 1'b0;
case (opcode)
6'b000000: begin
c_ALUOp <= 2'b10;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b1;
if (funct == 6'b001000) begin
c_ALUOp <= 2'b01;
c_desvio <= 3'b101;
c_escrever_reg <= 1'b0;
end
end
6'b011100: begin
c_ALUOp <= 2'b10;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b1;
end
6'b101011: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b10;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b100011: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b01;
c_memtoreg <= 1'b1;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
end
6'b001000: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
end
6'b000100: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b001;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000101: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b010;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000010: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b011;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000011: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b100;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
c_jal <= 1'b1;
end
endcase
end
endmodule | module Controle(input wire [5:0] opcode,
input wire [5:0] funct,
output reg [1:0] c_ALUOp,
output reg c_fonte_ula,
output reg [2:0] c_desvio,
output reg [1:0] c_memoria,
output reg c_memtoreg,
output reg c_escrever_reg,
output reg c_reg_destino,
output reg c_jal
); |
always @ ( * ) begin
c_jal <= 1'b0;
case (opcode)
6'b000000: begin
c_ALUOp <= 2'b10;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b1;
if (funct == 6'b001000) begin
c_ALUOp <= 2'b01;
c_desvio <= 3'b101;
c_escrever_reg <= 1'b0;
end
end
6'b011100: begin
c_ALUOp <= 2'b10;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b1;
end
6'b101011: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b10;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b100011: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b01;
c_memtoreg <= 1'b1;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
end
6'b001000: begin
c_ALUOp <= 2'b00;
c_fonte_ula <= 1'b1;
c_desvio <= 3'b000;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
end
6'b000100: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b001;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000101: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b010;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000010: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b011;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b0;
c_reg_destino <= 1'b0;
end
6'b000011: begin
c_ALUOp <= 2'b01;
c_fonte_ula <= 1'b0;
c_desvio <= 3'b100;
c_memoria <= 2'b00;
c_memtoreg <= 1'b0;
c_escrever_reg <= 1'b1;
c_reg_destino <= 1'b0;
c_jal <= 1'b1;
end
endcase
end
endmodule | 0 |
2,755 | data/full_repos/permissive/100975158/ProcessadorQuartus/controleALU.v | 100,975,158 | controleALU.v | v | 39 | 95 | [] | [] | [] | [(1, 38)] | null | data/verilator_xmls/68286964-6908-4226-9ea0-e76d1576633a.xml | null | 192 | module | module controleALU( input[5:0] funct, input[1:0] opALU, output[2:0] sinalOperacao);
reg [2:0] microSinal;
always @ ( * ) begin
if (funct == 6'b100100 && opALU == 2'b10)
microSinal <= 3'b000;
else if (funct == 6'b100101 && opALU == 2'b10)
microSinal <=3'b001;
else if ((opALU == 2'b00) || (funct == 6'b100000 && opALU == 2'b10))
microSinal <=3'b010;
else if (funct == 6'b000010 && opALU == 2'b10)
microSinal <=3'b011;
else if (funct == 6'b011010 && opALU == 2'b10)
microSinal <=3'b100;
else if ((opALU == 2'b01) || (funct == 6'b100010 && opALU == 2'b10))
microSinal <=3'b110;
else if (funct == 6'b101010 && opALU == 2'b10)
microSinal <=3'b111;
end
assign sinalOperacao = microSinal;
endmodule | module controleALU( input[5:0] funct, input[1:0] opALU, output[2:0] sinalOperacao); |
reg [2:0] microSinal;
always @ ( * ) begin
if (funct == 6'b100100 && opALU == 2'b10)
microSinal <= 3'b000;
else if (funct == 6'b100101 && opALU == 2'b10)
microSinal <=3'b001;
else if ((opALU == 2'b00) || (funct == 6'b100000 && opALU == 2'b10))
microSinal <=3'b010;
else if (funct == 6'b000010 && opALU == 2'b10)
microSinal <=3'b011;
else if (funct == 6'b011010 && opALU == 2'b10)
microSinal <=3'b100;
else if ((opALU == 2'b01) || (funct == 6'b100010 && opALU == 2'b10))
microSinal <=3'b110;
else if (funct == 6'b101010 && opALU == 2'b10)
microSinal <=3'b111;
end
assign sinalOperacao = microSinal;
endmodule | 0 |
2,756 | data/full_repos/permissive/100975158/ProcessadorQuartus/Foward.v | 100,975,158 | Foward.v | v | 59 | 80 | [] | [] | [] | [(15, 58)] | null | data/verilator_xmls/d793d827-2f34-4244-9690-681689ba16de.xml | null | 193 | module | module Foward (
input reg_f4, reg_f5, clock,
input [4:0] escrita_f4, escrita_f5,
input [4:0] RS_f3, RT_f3,
output [1:0] fw_A, fw_B
);
reg [1:0] A, B;
always @ ( * ) begin
if(reg_f4 && escrita_f4 != 5'b0) begin
if(escrita_f4 == RS_f3)
A <= 2'b10;
if(escrita_f4 == RT_f3)
B <= 2'b10;
end
else if(reg_f5 && escrita_f5 != 5'b0) begin
if(escrita_f5 == RS_f3)
A <= 2'b01;
if(escrita_f5 == RT_f3)
B <= 2'b01;
end
else begin
A <= 2'b0;
B <= 2'b0;
end
end
assign fw_A = A;
assign fw_B = B;
endmodule | module Foward (
input reg_f4, reg_f5, clock,
input [4:0] escrita_f4, escrita_f5,
input [4:0] RS_f3, RT_f3,
output [1:0] fw_A, fw_B
); |
reg [1:0] A, B;
always @ ( * ) begin
if(reg_f4 && escrita_f4 != 5'b0) begin
if(escrita_f4 == RS_f3)
A <= 2'b10;
if(escrita_f4 == RT_f3)
B <= 2'b10;
end
else if(reg_f5 && escrita_f5 != 5'b0) begin
if(escrita_f5 == RS_f3)
A <= 2'b01;
if(escrita_f5 == RT_f3)
B <= 2'b01;
end
else begin
A <= 2'b0;
B <= 2'b0;
end
end
assign fw_A = A;
assign fw_B = B;
endmodule | 0 |
2,757 | data/full_repos/permissive/100975158/ProcessadorQuartus/Memoria.v | 100,975,158 | Memoria.v | v | 13 | 43 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/fc52a8e9-914c-47a4-952b-7cbf9201a91d.xml | null | 194 | module | module Memoria (
input wire[31:0] pc,
output wire[31:0] instrucao
);
reg [31:0] memoria [0:63];
initial begin
$readmemb("c:/arquivo.txt", memoria);
end
assign instrucao = memoria[pc[7:2]][31:0];
endmodule | module Memoria (
input wire[31:0] pc,
output wire[31:0] instrucao
); |
reg [31:0] memoria [0:63];
initial begin
$readmemb("c:/arquivo.txt", memoria);
end
assign instrucao = memoria[pc[7:2]][31:0];
endmodule | 0 |
2,758 | data/full_repos/permissive/100975158/ProcessadorQuartus/MemoriaDeDados.v | 100,975,158 | MemoriaDeDados.v | v | 15 | 75 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/2df99854-64a3-4cfa-af63-0a5a10e47014.xml | null | 195 | module | module MemoriaDeDados (input clock, sinal_ler, sinal_escrever,
input wire [6:0] endereco,
input wire [31:0] dado_escrever,
output wire [31:0] dado_ler);
reg [31:0] memoria [0:127];
always @ (posedge clock) begin
if (sinal_escrever)
memoria[endereco] <= dado_escrever;
end
assign dado_ler = (sinal_ler) ? memoria[endereco][31:0] : dado_escrever;
endmodule | module MemoriaDeDados (input clock, sinal_ler, sinal_escrever,
input wire [6:0] endereco,
input wire [31:0] dado_escrever,
output wire [31:0] dado_ler); |
reg [31:0] memoria [0:127];
always @ (posedge clock) begin
if (sinal_escrever)
memoria[endereco] <= dado_escrever;
end
assign dado_ler = (sinal_ler) ? memoria[endereco][31:0] : dado_escrever;
endmodule | 0 |
2,759 | data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v | 100,975,158 | Processador.v | v | 349 | 363 | [] | [] | [] | [(1, 348)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:43: Cannot find file containing module: \'Memoria\'\n Memoria memoria (.pc(pc), .instrucao(instrucao)); \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Memoria\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Memoria.v\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Memoria.sv\n Memoria\n Memoria.v\n Memoria.sv\n obj_dir/Memoria\n obj_dir/Memoria.v\n obj_dir/Memoria.sv\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:46: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(32)) if_id_pc (.clock(clock), .parada(parada), .limpar(limpar), .in(pc4), .out(pc_2)); \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:47: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(32)) if_id_inst (.clock(clock), .parada(parada), .limpar(limpar), .in(instrucao), .out(instrucao_2)); \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:89: Cannot find file containing module: \'BancoDeRegistradores\'\n BancoDeRegistradores registradores(.rs(rs), .rt(rt), .out_rs(out_rs), .out_rt(out_rt), .sinal_escrita(c_escrever_reg_5), .reg_escrita(reg_escrita_5), .dado_escrita(dado_escrita_5)); \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:95: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(96)) id_ex_dados_reg (.clock(clock), .parada(parada), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:100: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(6)) id_ex_funct (.clock(clock), .parada(parada), .limpar(limpar), .in(funct), .out(funct_3));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:103: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(10)) id_ex_registradores (.clock(clock), .parada(parada), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:108: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(5)) id_ex_registrador_rs(.clock(clock), .parada(parada), .limpar(1\'b0), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:113: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(32)) id_ex_pc (.clock(clock), .parada(parada), .limpar(1\'b0),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:117: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(64)) id_ex_desvios (.clock(clock), .parada(1\'b0), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:131: Cannot find file containing module: \'Controle\'\n Controle controle (.opcode(opcode), .c_ALUOp(c_ALUOp), .c_memoria(c_memoria), .c_desvio(c_desvio), .c_fonte_ula(c_fonte_ula), .c_memtoreg(c_memtoreg), .c_escrever_reg(c_escrever_reg), .c_reg_destino(c_reg_destino), .c_jal(c_jal));\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:141: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(9)) id_ex_micro_sinais(.clock(clock), .parada(1\'b0), .limpar(parada), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:145: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(3)) id_ex_branch_sinais(.clock(clock), .parada(1\'b0), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:158: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(5)) ex_me_micro_sinais(.clock(clock), .parada(1\'b0), .limpar(limpar), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:166: Cannot find file containing module: \'controleALU\'\n controleALU controle_alu (.funct(funct_3), .opALU(c_ALUOp_3), .sinalOperacao(operacao)); \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:185: Cannot find file containing module: \'ALU\'\n ALU alu (.sinalOperacao(operacao), .rs(dado1_antecipado), .rt(segundo_operando), .resultado(resultado_ula), .overflow(overflow), .zero(zero));\n ^~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:193: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(2)) ex_me_flags_ula(.clock(clock), .parada(1\'b0), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:198: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(32)) ex_me_ula_resultado(.clock(clock), .parada(1\'b0), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:214: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(64)) ex_me_dado_registrador(.clock(clock), .parada(1\'b0), .limpar(limpar),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:231: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(5)) ex_me_reg_escrita(.clock(clock), .parada(1\'b0), .limpar(limpar), .in(reg_escrita), .out(reg_escrita_4));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:234: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(64)) ex_me_end_branch(.clock(clock), .parada(1\'b0), .limpar(limpar), .in({branch_end_3, jump_end_3}), .out({branch_end_4, jump_end_4}));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:237: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(3)) ex_me_sinal_desvio(.clock(clock), .parada(1\'b0), .limpar(limpar), .in(c_desvio_3), .out(c_desvio_4));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:240: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(32)) ex_me_pc(.clock(clock), .parada(1\'b0), .limpar(limpar), .in(pc_3), .out(pc_4));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:246: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(3)) me_wb_microsinais(.clock(clock), .parada(1\'b0), .limpar(1\'b0), .in({c_memtoreg_4, c_escrever_reg_4, c_jal_4}), .out({c_memtoreg_5, c_escrever_reg_5, c_jal_5}) );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:248: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(5)) me_wb_registrador(.clock(clock), .parada(1\'b0), .limpar(1\'b0), .in(reg_escrita_4), .out(reg_escrita_5));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:251: Cannot find file containing module: \'MemoriaDeDados\'\n MemoriaDeDados memoria_dados(.clock(clock), .sinal_ler(c_memoria_4[0]), .sinal_escrever(c_memoria_4[1]), .endereco(resultado_ula_4[8:2]), .dado_ler(dado_lido_memoria), .dado_escrever(dado_rt_4));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:255: Cannot find file containing module: \'RegPipeline\'\n RegPipeline #(.TAM(96)) me_wb_dados(.clock(clock), .parada(1\'b0), .limpar(1\'b0),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:332: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'antecipar_a\' generates 2 bits.\n : ... In instance Processador\n assign t_antecipar_a = antecipar_a;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/Processador.v:333: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'antecipar_b\' generates 2 bits.\n : ... In instance Processador\n assign t_antecipar_b = antecipar_b;\n ^\n%Error: Exiting due to 27 error(s), 2 warning(s)\n' | 196 | module | module Processador(input clock,
output wire[31:0] t_pc, t_inst, t_alu_a, t_alu_b, t_wb_data, t_mem_write_data, t_alu_rst, t_d_rs, t_d_rt,
output wire[4:0] t_wb_reg, t_rs, t_rt, t_rd,
output wire t_fonte_pc, t_limpar, t_parada, t_escrever_reg,
output wire[2:0] t_antecipar_a, t_antecipar_b, t_operacao_alu);
reg[4:0] reg_pc;
initial begin
reg_pc <= 5'b11111;
end
reg limpar;
always @ ( * ) begin
limpar <= 0;
if (fonte_pc)
limpar <= 1;
end
assign t_fonte_pc = fonte_pc;
assign t_limpar = limpar;
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4;
assign pc4 = pc + 4;
always @(posedge clock) begin
if (parada)
pc <= pc;
else if (fonte_pc)
pc <= endereco_salto;
else
pc <= pc4;
end
wire [31:0] instrucao;
Memoria memoria (.pc(pc), .instrucao(instrucao));
wire[31:0] pc_2, instrucao_2;
RegPipeline #(.TAM(32)) if_id_pc (.clock(clock), .parada(parada), .limpar(limpar), .in(pc4), .out(pc_2));
RegPipeline #(.TAM(32)) if_id_inst (.clock(clock), .parada(parada), .limpar(limpar), .in(instrucao), .out(instrucao_2));
assign t_pc = pc;
assign t_inst = instrucao;
wire[5:0] opcode;
wire[4:0] rs, rt, rd;
wire[4:0] shift;
wire[5:0] funct;
wire[15:0] imediato;
assign opcode = instrucao_2[31:26];
assign rs = instrucao_2[25:21];
assign rt = instrucao_2[20:16];
assign rd = instrucao_2[15:11];
assign shift = instrucao_2[10:6];
assign funct = instrucao_2[5:0];
assign imediato = instrucao_2[15:0];
wire[31:0] se_imediato;
assign se_imediato = {{16{imediato[15]}}, imediato[15:0]};
wire [31:0] jump_end;
assign jump_end = {pc_2[31:28], instrucao_2[25:0], 2'b00};
wire [31:0] branch_end;
assign branch_end = pc_2 + {se_imediato[29:0], 2'b00};
wire [31:0] out_rs, out_rt;
assign t_rs = (rs);
assign t_rt = (rt);
assign t_rd = (rd);
BancoDeRegistradores registradores(.rs(rs), .rt(rt), .out_rs(out_rs), .out_rt(out_rt), .sinal_escrita(c_escrever_reg_5), .reg_escrita(reg_escrita_5), .dado_escrita(dado_escrita_5));
assign t_d_rs = out_rs;
assign t_d_rt = out_rt;
wire [31:0] dado_rs_3, dado_rt_3, se_imediato_3;
RegPipeline #(.TAM(96)) id_ex_dados_reg (.clock(clock), .parada(parada), .limpar(limpar),
.in({out_rs, out_rt, se_imediato}),
.out({dado_rs_3, dado_rt_3, se_imediato_3}));
wire [5:0] funct_3;
RegPipeline #(.TAM(6)) id_ex_funct (.clock(clock), .parada(parada), .limpar(limpar), .in(funct), .out(funct_3));
wire [4:0] rt_3, rd_3;
RegPipeline #(.TAM(10)) id_ex_registradores (.clock(clock), .parada(parada), .limpar(limpar),
.in({rt, rd}),
.out({rt_3, rd_3}));
wire [4:0] rs_3;
RegPipeline #(.TAM(5)) id_ex_registrador_rs(.clock(clock), .parada(parada), .limpar(1'b0),
.in (rs),
.out(rs_3));
wire [31:0] pc_3;
RegPipeline #(.TAM(32)) id_ex_pc (.clock(clock), .parada(parada), .limpar(1'b0),
.in(pc_2), .out(pc_3));
wire[31:0] branch_end_3, jump_end_3;
RegPipeline #(.TAM(64)) id_ex_desvios (.clock(clock), .parada(1'b0), .limpar(limpar),
.in({branch_end, jump_end}),
.out({branch_end_3, jump_end_3}));
wire[1:0] c_ALUOp;
wire[1:0] c_memoria;
wire[2:0] c_desvio;
wire c_fonte_ula;
wire c_memtoreg;
wire c_escrever_reg;
wire c_reg_destino;
wire c_jal;
Controle controle (.opcode(opcode), .c_ALUOp(c_ALUOp), .c_memoria(c_memoria), .c_desvio(c_desvio), .c_fonte_ula(c_fonte_ula), .c_memtoreg(c_memtoreg), .c_escrever_reg(c_escrever_reg), .c_reg_destino(c_reg_destino), .c_jal(c_jal));
wire[1:0] c_ALUOp_3;
wire[1:0] c_memoria_3;
wire[2:0] c_desvio_3;
wire c_fonte_ula_3;
wire c_memtoreg_3;
wire c_escrever_reg_3;
wire c_reg_destino_3;
wire c_jal_3;
RegPipeline #(.TAM(9)) id_ex_micro_sinais(.clock(clock), .parada(1'b0), .limpar(parada),
.in({c_ALUOp, c_memoria, c_fonte_ula, c_memtoreg, c_escrever_reg, c_reg_destino, c_jal}),
.out({c_ALUOp_3, c_memoria_3, c_fonte_ula_3, c_memtoreg_3, c_escrever_reg_3, c_reg_destino_3, c_jal_3}));
RegPipeline #(.TAM(3)) id_ex_branch_sinais(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({c_desvio}),
.out({c_desvio_3}));
wire[1:0] c_memoria_4;
wire c_memtoreg_4;
wire c_escrever_reg_4;
wire c_jal_4;
RegPipeline #(.TAM(5)) ex_me_micro_sinais(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({c_memoria_3, c_memtoreg_3, c_escrever_reg_3, c_jal_3}),
.out({c_memoria_4, c_memtoreg_4, c_escrever_reg_4, c_jal_4}));
wire [31:0] segundo_operando;
assign segundo_operando = (c_fonte_ula_3) ? se_imediato_3 : dado2_antecipado;
wire [2:0] operacao;
controleALU controle_alu (.funct(funct_3), .opALU(c_ALUOp_3), .sinalOperacao(operacao));
assign t_operacao_alu = operacao;
reg [31:0] dado1_antecipado;
always @ ( * ) begin
case (antecipar_a)
2'b01: dado1_antecipado <= resultado_ula_4;
2'b10: dado1_antecipado <= dado_escrita_5;
default: dado1_antecipado <= dado_rs_3;
endcase
end
wire [31:0] resultado_ula;
wire zero, overflow;
assign t_alu_a = dado1_antecipado;
assign t_alu_b = segundo_operando;
ALU alu (.sinalOperacao(operacao), .rs(dado1_antecipado), .rt(segundo_operando), .resultado(resultado_ula), .overflow(overflow), .zero(zero));
assign t_alu_rst = resultado_ula;
wire zero_4;
wire overflow_4;
RegPipeline #(.TAM(2)) ex_me_flags_ula(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({zero, overflow}),
.out({zero_4, overflow_4}));
wire [31:0] resultado_ula_4;
RegPipeline #(.TAM(32)) ex_me_ula_resultado(.clock(clock), .parada(1'b0), .limpar(limpar),
.in(resultado_ula),
.out(resultado_ula_4));
reg [31:0] dado2_antecipado;
always @ ( * ) begin
case (antecipar_b)
2'b01: dado2_antecipado <= resultado_ula_4;
2'b10: dado2_antecipado <= dado_escrita_5;
default: dado2_antecipado <= dado_rt_3;
endcase
end
wire [31:0] dado_rt_4, dado_rs_4;
RegPipeline #(.TAM(64)) ex_me_dado_registrador(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({dado2_antecipado, dado1_antecipado}),
.out({dado_rt_4, dado_rs_4}));
wire [4:0] reg_escrita;
reg[4:0] reg_escrita_mux;
always @ ( * ) begin
if (c_desvio_3 == 3'b100)
reg_escrita_mux <= reg_pc;
else if (c_reg_destino_3 == 1'b1)
reg_escrita_mux <= rd_3;
else
reg_escrita_mux <= rt_3;
end
assign reg_escrita = reg_escrita_mux;
wire [4:0] reg_escrita_4;
RegPipeline #(.TAM(5)) ex_me_reg_escrita(.clock(clock), .parada(1'b0), .limpar(limpar), .in(reg_escrita), .out(reg_escrita_4));
wire [31:0] branch_end_4, jump_end_4;
RegPipeline #(.TAM(64)) ex_me_end_branch(.clock(clock), .parada(1'b0), .limpar(limpar), .in({branch_end_3, jump_end_3}), .out({branch_end_4, jump_end_4}));
wire[2:0] c_desvio_4;
RegPipeline #(.TAM(3)) ex_me_sinal_desvio(.clock(clock), .parada(1'b0), .limpar(limpar), .in(c_desvio_3), .out(c_desvio_4));
wire [31:0] pc_4;
RegPipeline #(.TAM(32)) ex_me_pc(.clock(clock), .parada(1'b0), .limpar(limpar), .in(pc_3), .out(pc_4));
wire c_memtoreg_5, c_escrever_reg_5, c_jal_5;
RegPipeline #(.TAM(3)) me_wb_microsinais(.clock(clock), .parada(1'b0), .limpar(1'b0), .in({c_memtoreg_4, c_escrever_reg_4, c_jal_4}), .out({c_memtoreg_5, c_escrever_reg_5, c_jal_5}) );
wire[4:0] reg_escrita_5;
RegPipeline #(.TAM(5)) me_wb_registrador(.clock(clock), .parada(1'b0), .limpar(1'b0), .in(reg_escrita_4), .out(reg_escrita_5));
wire [31:0] dado_lido_memoria;
MemoriaDeDados memoria_dados(.clock(clock), .sinal_ler(c_memoria_4[0]), .sinal_escrever(c_memoria_4[1]), .endereco(resultado_ula_4[8:2]), .dado_ler(dado_lido_memoria), .dado_escrever(dado_rt_4));
assign t_mem_write_data = dado_rt_4;
wire[31:0] resultado_ula_5, dado_memoria_5, pc_5;
RegPipeline #(.TAM(96)) me_wb_dados(.clock(clock), .parada(1'b0), .limpar(1'b0),
.in({resultado_ula_4, dado_lido_memoria, pc_4}),
.out({resultado_ula_5, dado_memoria_5, pc_5}));
wire[31:0] endereco_salto;
reg[31:0] endereco_salto_mux;
reg fonte_pc;
always @ ( * ) begin
case (c_desvio_4)
3'b001: begin
fonte_pc <= zero_4;
endereco_salto_mux <= branch_end_4;
end
3'b010: begin
fonte_pc <= ~(zero_4);
endereco_salto_mux <= branch_end_4;
end
3'b011: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= jump_end_4;
end
3'b100: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= jump_end_4;
end
3'b101: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= dado_rs_4;
end
default: fonte_pc <= 1'b0;
endcase
end
assign endereco_salto = endereco_salto_mux;
wire[31:0] dado_escrita_5;
reg[31:0] dado_escrita_5_mux;
assign dado_escrita_5 = (c_jal_5) ? pc_5 : (c_memtoreg_5) ? dado_memoria_5 : resultado_ula_5;
assign t_wb_reg = reg_escrita_5;
assign t_wb_data = dado_escrita_5;
assign t_escrever_reg = c_escrever_reg_5;
reg [1:0] antecipar_a, antecipar_b;
always @ ( * ) begin
if (c_escrever_reg_4 && (reg_escrita_4 == rs_3))
antecipar_a <= 2'b01;
else if (c_escrever_reg_5 && (reg_escrita_5 == rs_3))
antecipar_a <= 2'b10;
else
antecipar_a <= 2'b00;
if (c_escrever_reg_4 && (reg_escrita_4 == rt_3))
antecipar_b <= 2'b01;
else if (c_escrever_reg_5 && (reg_escrita_5 == rt_3))
antecipar_b <= 2'b10;
else
antecipar_b <= 2'b00;
end
assign t_antecipar_a = antecipar_a;
assign t_antecipar_b = antecipar_b;
reg parada;
always @ ( * ) begin
if (c_memtoreg_3 && ((rt == rt_3) || (rs == rt_3)))
parada <= 1'b1;
else
parada <= 1'b0;
end
assign t_parada = parada;
endmodule | module Processador(input clock,
output wire[31:0] t_pc, t_inst, t_alu_a, t_alu_b, t_wb_data, t_mem_write_data, t_alu_rst, t_d_rs, t_d_rt,
output wire[4:0] t_wb_reg, t_rs, t_rt, t_rd,
output wire t_fonte_pc, t_limpar, t_parada, t_escrever_reg,
output wire[2:0] t_antecipar_a, t_antecipar_b, t_operacao_alu); |
reg[4:0] reg_pc;
initial begin
reg_pc <= 5'b11111;
end
reg limpar;
always @ ( * ) begin
limpar <= 0;
if (fonte_pc)
limpar <= 1;
end
assign t_fonte_pc = fonte_pc;
assign t_limpar = limpar;
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4;
assign pc4 = pc + 4;
always @(posedge clock) begin
if (parada)
pc <= pc;
else if (fonte_pc)
pc <= endereco_salto;
else
pc <= pc4;
end
wire [31:0] instrucao;
Memoria memoria (.pc(pc), .instrucao(instrucao));
wire[31:0] pc_2, instrucao_2;
RegPipeline #(.TAM(32)) if_id_pc (.clock(clock), .parada(parada), .limpar(limpar), .in(pc4), .out(pc_2));
RegPipeline #(.TAM(32)) if_id_inst (.clock(clock), .parada(parada), .limpar(limpar), .in(instrucao), .out(instrucao_2));
assign t_pc = pc;
assign t_inst = instrucao;
wire[5:0] opcode;
wire[4:0] rs, rt, rd;
wire[4:0] shift;
wire[5:0] funct;
wire[15:0] imediato;
assign opcode = instrucao_2[31:26];
assign rs = instrucao_2[25:21];
assign rt = instrucao_2[20:16];
assign rd = instrucao_2[15:11];
assign shift = instrucao_2[10:6];
assign funct = instrucao_2[5:0];
assign imediato = instrucao_2[15:0];
wire[31:0] se_imediato;
assign se_imediato = {{16{imediato[15]}}, imediato[15:0]};
wire [31:0] jump_end;
assign jump_end = {pc_2[31:28], instrucao_2[25:0], 2'b00};
wire [31:0] branch_end;
assign branch_end = pc_2 + {se_imediato[29:0], 2'b00};
wire [31:0] out_rs, out_rt;
assign t_rs = (rs);
assign t_rt = (rt);
assign t_rd = (rd);
BancoDeRegistradores registradores(.rs(rs), .rt(rt), .out_rs(out_rs), .out_rt(out_rt), .sinal_escrita(c_escrever_reg_5), .reg_escrita(reg_escrita_5), .dado_escrita(dado_escrita_5));
assign t_d_rs = out_rs;
assign t_d_rt = out_rt;
wire [31:0] dado_rs_3, dado_rt_3, se_imediato_3;
RegPipeline #(.TAM(96)) id_ex_dados_reg (.clock(clock), .parada(parada), .limpar(limpar),
.in({out_rs, out_rt, se_imediato}),
.out({dado_rs_3, dado_rt_3, se_imediato_3}));
wire [5:0] funct_3;
RegPipeline #(.TAM(6)) id_ex_funct (.clock(clock), .parada(parada), .limpar(limpar), .in(funct), .out(funct_3));
wire [4:0] rt_3, rd_3;
RegPipeline #(.TAM(10)) id_ex_registradores (.clock(clock), .parada(parada), .limpar(limpar),
.in({rt, rd}),
.out({rt_3, rd_3}));
wire [4:0] rs_3;
RegPipeline #(.TAM(5)) id_ex_registrador_rs(.clock(clock), .parada(parada), .limpar(1'b0),
.in (rs),
.out(rs_3));
wire [31:0] pc_3;
RegPipeline #(.TAM(32)) id_ex_pc (.clock(clock), .parada(parada), .limpar(1'b0),
.in(pc_2), .out(pc_3));
wire[31:0] branch_end_3, jump_end_3;
RegPipeline #(.TAM(64)) id_ex_desvios (.clock(clock), .parada(1'b0), .limpar(limpar),
.in({branch_end, jump_end}),
.out({branch_end_3, jump_end_3}));
wire[1:0] c_ALUOp;
wire[1:0] c_memoria;
wire[2:0] c_desvio;
wire c_fonte_ula;
wire c_memtoreg;
wire c_escrever_reg;
wire c_reg_destino;
wire c_jal;
Controle controle (.opcode(opcode), .c_ALUOp(c_ALUOp), .c_memoria(c_memoria), .c_desvio(c_desvio), .c_fonte_ula(c_fonte_ula), .c_memtoreg(c_memtoreg), .c_escrever_reg(c_escrever_reg), .c_reg_destino(c_reg_destino), .c_jal(c_jal));
wire[1:0] c_ALUOp_3;
wire[1:0] c_memoria_3;
wire[2:0] c_desvio_3;
wire c_fonte_ula_3;
wire c_memtoreg_3;
wire c_escrever_reg_3;
wire c_reg_destino_3;
wire c_jal_3;
RegPipeline #(.TAM(9)) id_ex_micro_sinais(.clock(clock), .parada(1'b0), .limpar(parada),
.in({c_ALUOp, c_memoria, c_fonte_ula, c_memtoreg, c_escrever_reg, c_reg_destino, c_jal}),
.out({c_ALUOp_3, c_memoria_3, c_fonte_ula_3, c_memtoreg_3, c_escrever_reg_3, c_reg_destino_3, c_jal_3}));
RegPipeline #(.TAM(3)) id_ex_branch_sinais(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({c_desvio}),
.out({c_desvio_3}));
wire[1:0] c_memoria_4;
wire c_memtoreg_4;
wire c_escrever_reg_4;
wire c_jal_4;
RegPipeline #(.TAM(5)) ex_me_micro_sinais(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({c_memoria_3, c_memtoreg_3, c_escrever_reg_3, c_jal_3}),
.out({c_memoria_4, c_memtoreg_4, c_escrever_reg_4, c_jal_4}));
wire [31:0] segundo_operando;
assign segundo_operando = (c_fonte_ula_3) ? se_imediato_3 : dado2_antecipado;
wire [2:0] operacao;
controleALU controle_alu (.funct(funct_3), .opALU(c_ALUOp_3), .sinalOperacao(operacao));
assign t_operacao_alu = operacao;
reg [31:0] dado1_antecipado;
always @ ( * ) begin
case (antecipar_a)
2'b01: dado1_antecipado <= resultado_ula_4;
2'b10: dado1_antecipado <= dado_escrita_5;
default: dado1_antecipado <= dado_rs_3;
endcase
end
wire [31:0] resultado_ula;
wire zero, overflow;
assign t_alu_a = dado1_antecipado;
assign t_alu_b = segundo_operando;
ALU alu (.sinalOperacao(operacao), .rs(dado1_antecipado), .rt(segundo_operando), .resultado(resultado_ula), .overflow(overflow), .zero(zero));
assign t_alu_rst = resultado_ula;
wire zero_4;
wire overflow_4;
RegPipeline #(.TAM(2)) ex_me_flags_ula(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({zero, overflow}),
.out({zero_4, overflow_4}));
wire [31:0] resultado_ula_4;
RegPipeline #(.TAM(32)) ex_me_ula_resultado(.clock(clock), .parada(1'b0), .limpar(limpar),
.in(resultado_ula),
.out(resultado_ula_4));
reg [31:0] dado2_antecipado;
always @ ( * ) begin
case (antecipar_b)
2'b01: dado2_antecipado <= resultado_ula_4;
2'b10: dado2_antecipado <= dado_escrita_5;
default: dado2_antecipado <= dado_rt_3;
endcase
end
wire [31:0] dado_rt_4, dado_rs_4;
RegPipeline #(.TAM(64)) ex_me_dado_registrador(.clock(clock), .parada(1'b0), .limpar(limpar),
.in({dado2_antecipado, dado1_antecipado}),
.out({dado_rt_4, dado_rs_4}));
wire [4:0] reg_escrita;
reg[4:0] reg_escrita_mux;
always @ ( * ) begin
if (c_desvio_3 == 3'b100)
reg_escrita_mux <= reg_pc;
else if (c_reg_destino_3 == 1'b1)
reg_escrita_mux <= rd_3;
else
reg_escrita_mux <= rt_3;
end
assign reg_escrita = reg_escrita_mux;
wire [4:0] reg_escrita_4;
RegPipeline #(.TAM(5)) ex_me_reg_escrita(.clock(clock), .parada(1'b0), .limpar(limpar), .in(reg_escrita), .out(reg_escrita_4));
wire [31:0] branch_end_4, jump_end_4;
RegPipeline #(.TAM(64)) ex_me_end_branch(.clock(clock), .parada(1'b0), .limpar(limpar), .in({branch_end_3, jump_end_3}), .out({branch_end_4, jump_end_4}));
wire[2:0] c_desvio_4;
RegPipeline #(.TAM(3)) ex_me_sinal_desvio(.clock(clock), .parada(1'b0), .limpar(limpar), .in(c_desvio_3), .out(c_desvio_4));
wire [31:0] pc_4;
RegPipeline #(.TAM(32)) ex_me_pc(.clock(clock), .parada(1'b0), .limpar(limpar), .in(pc_3), .out(pc_4));
wire c_memtoreg_5, c_escrever_reg_5, c_jal_5;
RegPipeline #(.TAM(3)) me_wb_microsinais(.clock(clock), .parada(1'b0), .limpar(1'b0), .in({c_memtoreg_4, c_escrever_reg_4, c_jal_4}), .out({c_memtoreg_5, c_escrever_reg_5, c_jal_5}) );
wire[4:0] reg_escrita_5;
RegPipeline #(.TAM(5)) me_wb_registrador(.clock(clock), .parada(1'b0), .limpar(1'b0), .in(reg_escrita_4), .out(reg_escrita_5));
wire [31:0] dado_lido_memoria;
MemoriaDeDados memoria_dados(.clock(clock), .sinal_ler(c_memoria_4[0]), .sinal_escrever(c_memoria_4[1]), .endereco(resultado_ula_4[8:2]), .dado_ler(dado_lido_memoria), .dado_escrever(dado_rt_4));
assign t_mem_write_data = dado_rt_4;
wire[31:0] resultado_ula_5, dado_memoria_5, pc_5;
RegPipeline #(.TAM(96)) me_wb_dados(.clock(clock), .parada(1'b0), .limpar(1'b0),
.in({resultado_ula_4, dado_lido_memoria, pc_4}),
.out({resultado_ula_5, dado_memoria_5, pc_5}));
wire[31:0] endereco_salto;
reg[31:0] endereco_salto_mux;
reg fonte_pc;
always @ ( * ) begin
case (c_desvio_4)
3'b001: begin
fonte_pc <= zero_4;
endereco_salto_mux <= branch_end_4;
end
3'b010: begin
fonte_pc <= ~(zero_4);
endereco_salto_mux <= branch_end_4;
end
3'b011: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= jump_end_4;
end
3'b100: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= jump_end_4;
end
3'b101: begin
fonte_pc <= 1'b1;
endereco_salto_mux <= dado_rs_4;
end
default: fonte_pc <= 1'b0;
endcase
end
assign endereco_salto = endereco_salto_mux;
wire[31:0] dado_escrita_5;
reg[31:0] dado_escrita_5_mux;
assign dado_escrita_5 = (c_jal_5) ? pc_5 : (c_memtoreg_5) ? dado_memoria_5 : resultado_ula_5;
assign t_wb_reg = reg_escrita_5;
assign t_wb_data = dado_escrita_5;
assign t_escrever_reg = c_escrever_reg_5;
reg [1:0] antecipar_a, antecipar_b;
always @ ( * ) begin
if (c_escrever_reg_4 && (reg_escrita_4 == rs_3))
antecipar_a <= 2'b01;
else if (c_escrever_reg_5 && (reg_escrita_5 == rs_3))
antecipar_a <= 2'b10;
else
antecipar_a <= 2'b00;
if (c_escrever_reg_4 && (reg_escrita_4 == rt_3))
antecipar_b <= 2'b01;
else if (c_escrever_reg_5 && (reg_escrita_5 == rt_3))
antecipar_b <= 2'b10;
else
antecipar_b <= 2'b00;
end
assign t_antecipar_a = antecipar_a;
assign t_antecipar_b = antecipar_b;
reg parada;
always @ ( * ) begin
if (c_memtoreg_3 && ((rt == rt_3) || (rs == rt_3)))
parada <= 1'b1;
else
parada <= 1'b0;
end
assign t_parada = parada;
endmodule | 0 |
2,760 | data/full_repos/permissive/100975158/ProcessadorQuartus/RegPipeline.v | 100,975,158 | RegPipeline.v | v | 28 | 111 | [] | [] | [] | [(7, 28)] | null | data/verilator_xmls/802da568-1d9f-4a0b-a804-a5a06a38a7bd.xml | null | 197 | module | module RegPipeline(
input clock, parada, limpar,
input wire [TAM-1:0] in,
output reg [TAM-1:0] out
);
parameter TAM = 32;
always @ ( posedge clock ) begin
if (limpar)
out <= {TAM{1'b0}};
else if (parada)
out <= out;
else
out <= in;
end
endmodule | module RegPipeline(
input clock, parada, limpar,
input wire [TAM-1:0] in,
output reg [TAM-1:0] out
); |
parameter TAM = 32;
always @ ( posedge clock ) begin
if (limpar)
out <= {TAM{1'b0}};
else if (parada)
out <= out;
else
out <= in;
end
endmodule | 0 |
2,761 | data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v | 100,975,158 | TB_Controle.v | v | 45 | 38 | [] | [] | [] | [(2, 45)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:28: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:30: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:32: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:34: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:36: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:38: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:40: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:42: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:15: Cannot find file containing module: \'Controle\'\n Controle teste_controle(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle.v\n data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle.sv\n Controle\n Controle.v\n Controle.sv\n obj_dir/Controle\n obj_dir/Controle.v\n obj_dir/Controle.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 198 | module | module TB_Controle ();
reg[5:0] opcode;
wire [1:0] c_ALUOp;
wire c_fonte_ula;
wire [2:0] c_desvio;
wire [1:0] c_memoria;
wire c_memtoreg;
wire c_escrever_reg;
wire c_reg_destino;
Controle teste_controle(
.opcode(opcode),
.c_ALUOp(c_ALUOp),
.c_fonte_ula(c_fonte_ula),
.c_desvio(c_desvio),
.c_memoria(c_memoria),
.c_memtoreg(c_memtoreg),
.c_escrever_reg(c_escrever_reg),
.c_reg_destino(c_reg_destino)
);
initial begin
opcode <= 6'b000000;
#50
opcode <= 6'b001000;
#50
opcode <= 6'b000011;
#50
opcode <= 6'b000010;
#50
opcode <= 6'b000101;
#50
opcode <= 6'b000100;
#50
opcode <= 6'b100011;
#50
opcode <= 6'b101011;
#50
opcode <= 6'b101011;
end
endmodule | module TB_Controle (); |
reg[5:0] opcode;
wire [1:0] c_ALUOp;
wire c_fonte_ula;
wire [2:0] c_desvio;
wire [1:0] c_memoria;
wire c_memtoreg;
wire c_escrever_reg;
wire c_reg_destino;
Controle teste_controle(
.opcode(opcode),
.c_ALUOp(c_ALUOp),
.c_fonte_ula(c_fonte_ula),
.c_desvio(c_desvio),
.c_memoria(c_memoria),
.c_memtoreg(c_memtoreg),
.c_escrever_reg(c_escrever_reg),
.c_reg_destino(c_reg_destino)
);
initial begin
opcode <= 6'b000000;
#50
opcode <= 6'b001000;
#50
opcode <= 6'b000011;
#50
opcode <= 6'b000010;
#50
opcode <= 6'b000101;
#50
opcode <= 6'b000100;
#50
opcode <= 6'b100011;
#50
opcode <= 6'b101011;
#50
opcode <= 6'b101011;
end
endmodule | 0 |
2,762 | data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v | 100,975,158 | TB_Foward.v | v | 48 | 127 | [] | [] | [] | null | line:47: before: "end" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:26: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b0; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:28: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:30: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:32: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00100; RT_f3 <= 5\'b00010; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:34: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00110; RT_f3 <= 5\'b00100; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:36: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b10000; RT_f3 <= 5\'b00010; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:38: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00110; RT_f3 <= 5\'b10000; #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:40: Unsupported: Ignoring delay on this delayed statement.\n reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00100; RT_f3 <= 5\'b00100; #100\n ^\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:47: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 199 | module | module TB_Foward ();
wire clock;
reg reg_f4, reg_f5;
reg [4:0] escrita_f4, escrita_f5;
reg [4:0] RS_f3, RT_f3;
wire [1:0] fw_A, fw_B;
Foward teste_foward(
.clock(clock),
.reg_f4(reg_f4),
.reg_f5(reg_f5),
.escrita_f4(escrita_f4),
.escrita_f5(escrita_f5),
.RS_f3(RS_f3),
.RT_f3(RT_f3),
.fw_A(fw_A),
.fw_B(fw_B)
);
initial begin
reg_f4 <= 1'b0; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110; RT_f3 <= 5'b00100; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110; RT_f3 <= 5'b10000; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100; RT_f3 <= 5'b00100; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000; RT_f3 <= 5'b10000; #100
end
endmodule | module TB_Foward (); |
wire clock;
reg reg_f4, reg_f5;
reg [4:0] escrita_f4, escrita_f5;
reg [4:0] RS_f3, RT_f3;
wire [1:0] fw_A, fw_B;
Foward teste_foward(
.clock(clock),
.reg_f4(reg_f4),
.reg_f5(reg_f5),
.escrita_f4(escrita_f4),
.escrita_f5(escrita_f5),
.RS_f3(RS_f3),
.RT_f3(RT_f3),
.fw_A(fw_A),
.fw_B(fw_B)
);
initial begin
reg_f4 <= 1'b0; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110; RT_f3 <= 5'b00100; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000; RT_f3 <= 5'b00010; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110; RT_f3 <= 5'b10000; #100
reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100; RT_f3 <= 5'b00100; #100
reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000; RT_f3 <= 5'b10000; #100
end
endmodule | 0 |
2,763 | data/full_repos/permissive/101171422/de2-115/blinkenlights/blinkenlights.v | 101,171,422 | blinkenlights.v | v | 40 | 54 | [] | [] | [] | [(3, 39)] | null | data/verilator_xmls/1b3bae52-f954-4e74-9f32-358bda4973f5.xml | null | 219 | module | module blinkenlights
(
input clk,
output [17:0] ledr,
output [7:0] ledg
);
parameter CLK_FREQ = 50_000_000;
parameter BLINK_FREQ = 1;
parameter CNT_MAX = CLK_FREQ/BLINK_FREQ/2 - 1;
reg [31:0] cnt;
reg blink;
always @ (posedge clk)
begin
if (cnt == CNT_MAX)
begin
cnt <= 0;
blink <= !blink;
end
else
cnt <= cnt + 1;
end
generate
genvar i;
for (i = 0; i <= 17; i = i+1)
begin : ledr_loop
assign ledr[i] = blink;
end
for (i = 0; i <= 7; i = i+1)
begin : ledg_loop
assign ledg[i] = !blink;
end
endgenerate
endmodule | module blinkenlights
(
input clk,
output [17:0] ledr,
output [7:0] ledg
); |
parameter CLK_FREQ = 50_000_000;
parameter BLINK_FREQ = 1;
parameter CNT_MAX = CLK_FREQ/BLINK_FREQ/2 - 1;
reg [31:0] cnt;
reg blink;
always @ (posedge clk)
begin
if (cnt == CNT_MAX)
begin
cnt <= 0;
blink <= !blink;
end
else
cnt <= cnt + 1;
end
generate
genvar i;
for (i = 0; i <= 17; i = i+1)
begin : ledr_loop
assign ledr[i] = blink;
end
for (i = 0; i <= 7; i = i+1)
begin : ledg_loop
assign ledg[i] = !blink;
end
endgenerate
endmodule | 0 |
2,764 | data/full_repos/permissive/101171422/de2-115/exbtn/exbtn.v | 101,171,422 | exbtn.v | v | 30 | 60 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/4ee334d4-2239-47e9-8cf9-b2fdc4b1736d.xml | null | 220 | module | module exbtn
(
inout wire [35:0] gpio,
output wire [8:0] ledg
);
generate
genvar i;
for (i = 0; i <= 8; i=i+1) begin : loop
assign gpio[i] = 1;
assign ledg[i] = gpio[i];
end
endgenerate
endmodule | module exbtn
(
inout wire [35:0] gpio,
output wire [8:0] ledg
); |
generate
genvar i;
for (i = 0; i <= 8; i=i+1) begin : loop
assign gpio[i] = 1;
assign ledg[i] = gpio[i];
end
endgenerate
endmodule | 0 |
2,765 | data/full_repos/permissive/101171422/de2-115/exled/exled.v | 101,171,422 | exled.v | v | 29 | 39 | [] | [] | [] | [(4, 29)] | null | data/verilator_xmls/b619f43d-a5ad-4d75-b58e-521bedb57d85.xml | null | 221 | module | module exled
(
input wire clk50,
output wire [35:0] gpio
);
localparam FREQ = 50_000_000;
reg [31:0] cnt;
reg [35:0] tog;
initial begin
cnt <= 0;
tog <= 0;
end
always @ (posedge clk50) begin
if (cnt == FREQ) begin
cnt <= 0;
tog <= ~tog;
end
else
cnt <= cnt + 1;
end
assign gpio = tog;
endmodule | module exled
(
input wire clk50,
output wire [35:0] gpio
); |
localparam FREQ = 50_000_000;
reg [31:0] cnt;
reg [35:0] tog;
initial begin
cnt <= 0;
tog <= 0;
end
always @ (posedge clk50) begin
if (cnt == FREQ) begin
cnt <= 0;
tog <= ~tog;
end
else
cnt <= cnt + 1;
end
assign gpio = tog;
endmodule | 0 |
2,766 | data/full_repos/permissive/101171422/de2-115/fsmcnt/fsmcnt.v | 101,171,422 | fsmcnt.v | v | 60 | 48 | [] | [] | [] | null | line:6: before: "(" | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/fsmcnt/fsmcnt.v:54: Cannot find file containing module: 'hexdigit'\n hexdigit h1(v[0], hex[7*1-1:7*0]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/fsmcnt,data/full_repos/permissive/101171422/hexdigit\n data/full_repos/permissive/101171422/de2-115/fsmcnt,data/full_repos/permissive/101171422/hexdigit.v\n data/full_repos/permissive/101171422/de2-115/fsmcnt,data/full_repos/permissive/101171422/hexdigit.sv\n hexdigit\n hexdigit.v\n hexdigit.sv\n obj_dir/hexdigit\n obj_dir/hexdigit.v\n obj_dir/hexdigit.sv\n%Error: data/full_repos/permissive/101171422/de2-115/fsmcnt/fsmcnt.v:55: Cannot find file containing module: 'hexdigit'\n hexdigit h2(v[1], hex[7*2-1:7*1]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/fsmcnt/fsmcnt.v:56: Cannot find file containing module: 'hexdigit'\n hexdigit h3(v[2], hex[7*3-1:7*2]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/fsmcnt/fsmcnt.v:57: Cannot find file containing module: 'hexdigit'\n hexdigit h4(v[3], hex[7*4-1:7*3]);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 222 | module | module fsmcnt
(
input wire clk,
output wire [8*7-1:0] hex
);
task inc(input integer n, input reg [2:0] s);
begin
if (cnt == 0) begin
v[n] = v[n] + 1;
state = s;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter CNT_MAX = CLK_FREQ;
reg [4:0] v[3:0];
reg [31:0] cnt;
reg [2:0] state;
initial begin
v[0] = 0;
v[1] = 0;
v[2] = 0;
v[3] = 0;
cnt = 1;
state = 0;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX)
cnt <= 0;
else
cnt <= cnt + 1;
end
always @ (posedge clk) begin
case (state)
0: inc(0, 1);
1: inc(2, 2);
2: inc(3, 3);
3: inc(1, 0);
endcase
end
generate
genvar i;
for (i = 7*4; i < 8*7; i = i + 1) begin: loop
assign hex[i] = 0;
end
endgenerate
hexdigit h1(v[0], hex[7*1-1:7*0]);
hexdigit h2(v[1], hex[7*2-1:7*1]);
hexdigit h3(v[2], hex[7*3-1:7*2]);
hexdigit h4(v[3], hex[7*4-1:7*3]);
endmodule | module fsmcnt
(
input wire clk,
output wire [8*7-1:0] hex
); |
task inc(input integer n, input reg [2:0] s);
begin
if (cnt == 0) begin
v[n] = v[n] + 1;
state = s;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter CNT_MAX = CLK_FREQ;
reg [4:0] v[3:0];
reg [31:0] cnt;
reg [2:0] state;
initial begin
v[0] = 0;
v[1] = 0;
v[2] = 0;
v[3] = 0;
cnt = 1;
state = 0;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX)
cnt <= 0;
else
cnt <= cnt + 1;
end
always @ (posedge clk) begin
case (state)
0: inc(0, 1);
1: inc(2, 2);
2: inc(3, 3);
3: inc(1, 0);
endcase
end
generate
genvar i;
for (i = 7*4; i < 8*7; i = i + 1) begin: loop
assign hex[i] = 0;
end
endgenerate
hexdigit h1(v[0], hex[7*1-1:7*0]);
hexdigit h2(v[1], hex[7*2-1:7*1]);
hexdigit h3(v[2], hex[7*3-1:7*2]);
hexdigit h4(v[3], hex[7*4-1:7*3]);
endmodule | 0 |
2,767 | data/full_repos/permissive/101171422/de2-115/fsmcnt/hexdigit.v | 101,171,422 | hexdigit.v | v | 27 | 27 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/ab9f12d7-0892-4f85-b592-f854c56bc603.xml | null | 223 | module | module hexdigit
(
input wire [3:0] in,
output reg [6:0] out
);
always @* begin
out = 7'b1111111;
case (in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'ha: out = 7'b0001000;
4'hb: out = 7'b0000011;
4'hc: out = 7'b1000110;
4'hd: out = 7'b0100001;
4'he: out = 7'b0000110;
4'hf: out = 7'b0001110;
endcase
end
endmodule | module hexdigit
(
input wire [3:0] in,
output reg [6:0] out
); |
always @* begin
out = 7'b1111111;
case (in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'ha: out = 7'b0001000;
4'hb: out = 7'b0000011;
4'hc: out = 7'b1000110;
4'hd: out = 7'b0100001;
4'he: out = 7'b0000110;
4'hf: out = 7'b0001110;
endcase
end
endmodule | 0 |
2,768 | data/full_repos/permissive/101171422/de2-115/lcdprint/lcd.v | 101,171,422 | lcd.v | v | 79 | 35 | [] | [] | [] | null | line:19: before: "]" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/lcdprint/lcd.v:25: Operator SUB expects 32 bits on the LHS, but LHS\'s CONST \'9\'h141\' generates 9 bits.\n : ... In instance lcd\n chr[i] = 9\'h141 - LINE1 + i;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/lcdprint/lcd.v:25: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance lcd\n chr[i] = 9\'h141 - LINE1 + i;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 224 | module | module lcd
(
input wire clk,
output reg [4:0] ctl,
output reg [7:0] data
);
localparam RW = 0;
localparam RS = 1;
localparam ON = 2;
localparam EN = 3;
localparam BLON = 4;
localparam INITIAL = 0;
localparam LINE1 = 5;
localparam CHLINE = LINE1 + 16;
localparam LINE2 = CHLINE + 1;
localparam SIZE = LINE2 + 16;
reg [8:0] chr[SIZE];
reg [63:0] cnt;
integer pos, state, i;
initial begin
for (i = 0; i < SIZE; i = i + 1)
chr[i] = 9'h141 - LINE1 + i;
chr[CHLINE] = 9'h0C0;
chr[INITIAL+0] = 9'h038;
chr[INITIAL+1] = 9'h00C;
chr[INITIAL+2] = 9'h001;
chr[INITIAL+3] = 9'h006;
chr[INITIAL+4] = 9'h080;
cnt <= 0;
pos <= 0;
state <= 0;
end
always @* begin
ctl[RW] <= 0;
ctl[ON] <= 1;
ctl[BLON] <= 1;
end
always @ (posedge clk) begin
if (pos < SIZE) begin
case (state)
0: begin
ctl[EN] <= 1;
ctl[RS] <= chr[pos][8];
data <= chr[pos][7:0];
cnt <= 0;
state <= 1;
end
1: begin
if (cnt < 16)
cnt <= cnt + 1;
else begin
ctl[EN] <= 0;
cnt <= 0;
state <= 2;
end
end
2: begin
if (cnt < 'h3FFFE)
cnt <= cnt + 1;
else begin
pos <= pos + 1;
state <= 0;
end
end
endcase
end
end
endmodule | module lcd
(
input wire clk,
output reg [4:0] ctl,
output reg [7:0] data
); |
localparam RW = 0;
localparam RS = 1;
localparam ON = 2;
localparam EN = 3;
localparam BLON = 4;
localparam INITIAL = 0;
localparam LINE1 = 5;
localparam CHLINE = LINE1 + 16;
localparam LINE2 = CHLINE + 1;
localparam SIZE = LINE2 + 16;
reg [8:0] chr[SIZE];
reg [63:0] cnt;
integer pos, state, i;
initial begin
for (i = 0; i < SIZE; i = i + 1)
chr[i] = 9'h141 - LINE1 + i;
chr[CHLINE] = 9'h0C0;
chr[INITIAL+0] = 9'h038;
chr[INITIAL+1] = 9'h00C;
chr[INITIAL+2] = 9'h001;
chr[INITIAL+3] = 9'h006;
chr[INITIAL+4] = 9'h080;
cnt <= 0;
pos <= 0;
state <= 0;
end
always @* begin
ctl[RW] <= 0;
ctl[ON] <= 1;
ctl[BLON] <= 1;
end
always @ (posedge clk) begin
if (pos < SIZE) begin
case (state)
0: begin
ctl[EN] <= 1;
ctl[RS] <= chr[pos][8];
data <= chr[pos][7:0];
cnt <= 0;
state <= 1;
end
1: begin
if (cnt < 16)
cnt <= cnt + 1;
else begin
ctl[EN] <= 0;
cnt <= 0;
state <= 2;
end
end
2: begin
if (cnt < 'h3FFFE)
cnt <= cnt + 1;
else begin
pos <= pos + 1;
state <= 0;
end
end
endcase
end
end
endmodule | 0 |
2,769 | data/full_repos/permissive/101171422/de2-115/lcdprint/lcdprint.v | 101,171,422 | lcdprint.v | v | 10 | 31 | [] | [] | [] | [(2, 9)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/lcdprint/lcdprint.v:8: Cannot find file containing module: 'lcd'\n lcd l(clk, lcdctl, lcddata);\n ^~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/lcdprint,data/full_repos/permissive/101171422/lcd\n data/full_repos/permissive/101171422/de2-115/lcdprint,data/full_repos/permissive/101171422/lcd.v\n data/full_repos/permissive/101171422/de2-115/lcdprint,data/full_repos/permissive/101171422/lcd.sv\n lcd\n lcd.v\n lcd.sv\n obj_dir/lcd\n obj_dir/lcd.v\n obj_dir/lcd.sv\n%Error: Exiting due to 1 error(s)\n" | 225 | module | module lcdprint
(
input wire clk,
output wire [4:0] lcdctl,
output wire [7:0] lcddata
);
lcd l(clk, lcdctl, lcddata);
endmodule | module lcdprint
(
input wire clk,
output wire [4:0] lcdctl,
output wire [7:0] lcddata
); |
lcd l(clk, lcdctl, lcddata);
endmodule | 0 |
2,770 | data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v | 101,171,422 | ledhex.v | v | 105 | 51 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:30: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h40\' generates 7 bits.\n : ... In instance ledhex\n 0: v = 7\'b1000000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h79\' generates 7 bits.\n : ... In instance ledhex\n 1: v = 7\'b1111001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h24\' generates 7 bits.\n : ... In instance ledhex\n 2: v = 7\'b0100100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:33: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h30\' generates 7 bits.\n : ... In instance ledhex\n 3: v = 7\'b0110000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:34: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h19\' generates 7 bits.\n : ... In instance ledhex\n 4: v = 7\'b0011001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h12\' generates 7 bits.\n : ... In instance ledhex\n 5: v = 7\'b0010010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance ledhex\n 6: v = 7\'b0000010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h78\' generates 7 bits.\n : ... In instance ledhex\n 7: v = 7\'b1111000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance ledhex\n 8: v = 7\'b0000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:39: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h10\' generates 7 bits.\n : ... In instance ledhex\n 9: v = 7\'b0010000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n : ... In instance ledhex\n default: v = 7\'b1111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/ledhex/ledhex.v:100: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n : ... In instance ledhex\n ledr[i] = (step >> i) & 1;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 226 | module | module ledhex
(
input wire [3:0] key,
input wire clk,
output reg [`NLEDR-1:0] ledr,
output reg [`NSEG*7-1:0] hex
);
task clear();
integer i;
for (i = 0; i < `NSEG*7; i = i + 1) begin
hex[i] = 1;
end
endtask
task digit(input integer hp, input integer n);
reg [7:0] v;
integer i;
begin
case (n)
0: v = 7'b1000000;
1: v = 7'b1111001;
2: v = 7'b0100100;
3: v = 7'b0110000;
4: v = 7'b0011001;
5: v = 7'b0010010;
6: v = 7'b0000010;
7: v = 7'b1111000;
8: v = 7'b0000000;
9: v = 7'b0010000;
default: v = 7'b1111111;
endcase
hp = hp*7;
for (i = 0; i < 7; i = i + 1) begin
hex[hp+i] = v[i];
end
end
endtask
task print(input integer n);
integer i;
begin
clear();
for (i = 0; i < `NSEG; i = i + 1) begin
digit(i, n % 10);
n = n / 10;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter EV_MAX = CLK_FREQ / 25;
parameter CNT_MAX = CLK_FREQ;
parameter MAX_NUM = 100_000_000;
reg [31:0] cnt, ev, val, step;
integer i;
initial begin
cnt = 0;
ev = 0;
val = 0;
step = 1;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX) begin
cnt = 0;
val = (val + step) % MAX_NUM;
end
else
cnt = cnt + 1;
if (ev >= EV_MAX) begin
ev = 0;
if (key[0] == 1'b0)
val = 0;
if (key[1] == 1'b0)
step = 1;
if (key[2] == 1'b0)
step = (step + 1) % MAX_NUM;
if (key[3] == 1'b0 && step > 0)
step = step - 1;
end
else
ev = ev + 1;
for (i = 0; i < `NLEDR; i = i + 1)
ledr[i] = (step >> i) & 1;
print(val);
end
endmodule | module ledhex
(
input wire [3:0] key,
input wire clk,
output reg [`NLEDR-1:0] ledr,
output reg [`NSEG*7-1:0] hex
); |
task clear();
integer i;
for (i = 0; i < `NSEG*7; i = i + 1) begin
hex[i] = 1;
end
endtask
task digit(input integer hp, input integer n);
reg [7:0] v;
integer i;
begin
case (n)
0: v = 7'b1000000;
1: v = 7'b1111001;
2: v = 7'b0100100;
3: v = 7'b0110000;
4: v = 7'b0011001;
5: v = 7'b0010010;
6: v = 7'b0000010;
7: v = 7'b1111000;
8: v = 7'b0000000;
9: v = 7'b0010000;
default: v = 7'b1111111;
endcase
hp = hp*7;
for (i = 0; i < 7; i = i + 1) begin
hex[hp+i] = v[i];
end
end
endtask
task print(input integer n);
integer i;
begin
clear();
for (i = 0; i < `NSEG; i = i + 1) begin
digit(i, n % 10);
n = n / 10;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter EV_MAX = CLK_FREQ / 25;
parameter CNT_MAX = CLK_FREQ;
parameter MAX_NUM = 100_000_000;
reg [31:0] cnt, ev, val, step;
integer i;
initial begin
cnt = 0;
ev = 0;
val = 0;
step = 1;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX) begin
cnt = 0;
val = (val + step) % MAX_NUM;
end
else
cnt = cnt + 1;
if (ev >= EV_MAX) begin
ev = 0;
if (key[0] == 1'b0)
val = 0;
if (key[1] == 1'b0)
step = 1;
if (key[2] == 1'b0)
step = (step + 1) % MAX_NUM;
if (key[3] == 1'b0 && step > 0)
step = step - 1;
end
else
ev = ev + 1;
for (i = 0; i < `NLEDR; i = i + 1)
ledr[i] = (step >> i) & 1;
print(val);
end
endmodule | 0 |
2,771 | data/full_repos/permissive/101171422/de2-115/ledsw/ledsw.v | 101,171,422 | ledsw.v | v | 19 | 56 | [] | [] | [] | [(3, 18)] | null | data/verilator_xmls/b2e5f1df-eb54-440e-a880-fcf9fbd090e5.xml | null | 227 | module | module ledsw
(
input wire [17:0] sw,
output reg [17:0] ledr
);
generate
genvar i;
for (i = 0; i <= 17; i=i+1)
begin: loop
always @* begin
ledr[i] <= sw[i];
end
end
endgenerate
endmodule | module ledsw
(
input wire [17:0] sw,
output reg [17:0] ledr
); |
generate
genvar i;
for (i = 0; i <= 17; i=i+1)
begin: loop
always @* begin
ledr[i] <= sw[i];
end
end
endgenerate
endmodule | 0 |
2,772 | data/full_repos/permissive/101171422/de2-115/memhex/memhex.v | 101,171,422 | memhex.v | v | 29 | 55 | [] | [] | [] | [(2, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:10: Cannot find file containing module: 'ram'\n ram r1(0, clk, 0, 1'b0, o1);\n ^~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/memhex,data/full_repos/permissive/101171422/ram\n data/full_repos/permissive/101171422/de2-115/memhex,data/full_repos/permissive/101171422/ram.v\n data/full_repos/permissive/101171422/de2-115/memhex,data/full_repos/permissive/101171422/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:11: Cannot find file containing module: 'ram'\n ram r2(1, clk, 0, 1'b0, o2);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:12: Cannot find file containing module: 'ram'\n ram r3(2, clk, 0, 1'b0, o3);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:13: Cannot find file containing module: 'ram'\n ram r4(3, clk, 0, 1'b0, o4);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:14: Cannot find file containing module: 'ram'\n ram r5(4, clk, 0, 1'b0, o5);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:15: Cannot find file containing module: 'ram'\n ram r6(5, clk, 0, 1'b0, o6);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:16: Cannot find file containing module: 'ram'\n ram r7(6, clk, 0, 1'b0, o7);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:17: Cannot find file containing module: 'ram'\n ram r8(7, clk, 0, 1'b0, o8);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:19: Cannot find file containing module: 'hexdigit'\n hexdigit d1(o1, hex[7*1-1:7*0]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:20: Cannot find file containing module: 'hexdigit'\n hexdigit d2(o2, hex[7*2-1:7*1]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:21: Cannot find file containing module: 'hexdigit'\n hexdigit d3(o3, hex[7*3-1:7*2]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:22: Cannot find file containing module: 'hexdigit'\n hexdigit d4(o4, hex[7*4-1:7*3]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:23: Cannot find file containing module: 'hexdigit'\n hexdigit d5(o5, hex[7*5-1:7*4]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:24: Cannot find file containing module: 'hexdigit'\n hexdigit d6(o6, hex[7*6-1:7*5]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:25: Cannot find file containing module: 'hexdigit'\n hexdigit d7(o7, hex[7*7-1:7*6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/memhex/memhex.v:26: Cannot find file containing module: 'hexdigit'\n hexdigit d8(o8, hex[7*8-1:7*7]);\n ^~~~~~~~\n%Error: Exiting due to 16 error(s)\n" | 229 | module | module memhex
(
input wire clk,
output wire [8*7-1:0] hex
);
wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8;
ram r1(0, clk, 0, 1'b0, o1);
ram r2(1, clk, 0, 1'b0, o2);
ram r3(2, clk, 0, 1'b0, o3);
ram r4(3, clk, 0, 1'b0, o4);
ram r5(4, clk, 0, 1'b0, o5);
ram r6(5, clk, 0, 1'b0, o6);
ram r7(6, clk, 0, 1'b0, o7);
ram r8(7, clk, 0, 1'b0, o8);
hexdigit d1(o1, hex[7*1-1:7*0]);
hexdigit d2(o2, hex[7*2-1:7*1]);
hexdigit d3(o3, hex[7*3-1:7*2]);
hexdigit d4(o4, hex[7*4-1:7*3]);
hexdigit d5(o5, hex[7*5-1:7*4]);
hexdigit d6(o6, hex[7*6-1:7*5]);
hexdigit d7(o7, hex[7*7-1:7*6]);
hexdigit d8(o8, hex[7*8-1:7*7]);
endmodule | module memhex
(
input wire clk,
output wire [8*7-1:0] hex
); |
wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8;
ram r1(0, clk, 0, 1'b0, o1);
ram r2(1, clk, 0, 1'b0, o2);
ram r3(2, clk, 0, 1'b0, o3);
ram r4(3, clk, 0, 1'b0, o4);
ram r5(4, clk, 0, 1'b0, o5);
ram r6(5, clk, 0, 1'b0, o6);
ram r7(6, clk, 0, 1'b0, o7);
ram r8(7, clk, 0, 1'b0, o8);
hexdigit d1(o1, hex[7*1-1:7*0]);
hexdigit d2(o2, hex[7*2-1:7*1]);
hexdigit d3(o3, hex[7*3-1:7*2]);
hexdigit d4(o4, hex[7*4-1:7*3]);
hexdigit d5(o5, hex[7*5-1:7*4]);
hexdigit d6(o6, hex[7*6-1:7*5]);
hexdigit d7(o7, hex[7*7-1:7*6]);
hexdigit d8(o8, hex[7*8-1:7*7]);
endmodule | 0 |
2,773 | data/full_repos/permissive/101171422/de2-115/nios_lights/top.v | 101,171,422 | top.v | v | 14 | 24 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/nios_lights/top.v:8: Cannot find file containing module: 'lights'\n lights l(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/nios_lights,data/full_repos/permissive/101171422/lights\n data/full_repos/permissive/101171422/de2-115/nios_lights,data/full_repos/permissive/101171422/lights.v\n data/full_repos/permissive/101171422/de2-115/nios_lights,data/full_repos/permissive/101171422/lights.sv\n lights\n lights.v\n lights.sv\n obj_dir/lights\n obj_dir/lights.v\n obj_dir/lights.sv\n%Error: Exiting due to 1 error(s)\n" | 234 | module | module top
(
input CLOCK_50,
input [7:0] SW,
input [0:0] KEY,
output [7:0] LEDR
);
lights l(
.clk_clk(CLOCK_50),
.reset_reset_n(KEY),
.switches_export(SW),
.leds_export(LEDR)
);
endmodule | module top
(
input CLOCK_50,
input [7:0] SW,
input [0:0] KEY,
output [7:0] LEDR
); |
lights l(
.clk_clk(CLOCK_50),
.reset_reset_n(KEY),
.switches_export(SW),
.leds_export(LEDR)
);
endmodule | 0 |
2,774 | data/full_repos/permissive/101171422/de2-115/nios_lights/lights/lights_bb.v | 101,171,422 | lights_bb.v | v | 13 | 30 | [] | [] | [] | [(2, 12)] | null | data/verilator_xmls/eb3266a3-a8fd-4739-8f65-17890deb0eaa.xml | null | 235 | module | module lights (
clk_clk,
reset_reset_n,
switches_export,
leds_export);
input clk_clk;
input reset_reset_n;
input [7:0] switches_export;
output [7:0] leds_export;
endmodule | module lights (
clk_clk,
reset_reset_n,
switches_export,
leds_export); |
input clk_clk;
input reset_reset_n;
input [7:0] switches_export;
output [7:0] leds_export;
endmodule | 0 |
2,775 | data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v | 101,171,422 | pllsim.v | v | 26 | 40 | [] | [] | [] | [(1, 9), (12, 26)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:8: Cannot find file containing module: \'atpll\'\n atpll a(rst, clk, c0, c1, c2, c3, c4);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.v\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.sv\n atpll\n atpll.v\n atpll.sv\n obj_dir/atpll\n obj_dir/atpll.v\n obj_dir/atpll.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 273 | module | module pllsim
(
input wire rst,
input wire clk
);
wire c0, c1, c2, c3, c4;
atpll a(rst, clk, c0, c1, c2, c3, c4);
endmodule | module pllsim
(
input wire rst,
input wire clk
); |
wire c0, c1, c2, c3, c4;
atpll a(rst, clk, c0, c1, c2, c3, c4);
endmodule | 0 |
2,776 | data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v | 101,171,422 | pllsim.v | v | 26 | 40 | [] | [] | [] | [(1, 9), (12, 26)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:8: Cannot find file containing module: \'atpll\'\n atpll a(rst, clk, c0, c1, c2, c3, c4);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.v\n data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.sv\n atpll\n atpll.v\n atpll.sv\n obj_dir/atpll\n obj_dir/atpll.v\n obj_dir/atpll.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 273 | module | module pllsim_test();
reg clk, rst;
initial begin
clk = 0;
rst = 1;
end
always begin
#10 clk = ~clk;
rst = 0;
end
pllsim p(rst, clk);
endmodule | module pllsim_test(); |
reg clk, rst;
initial begin
clk = 0;
rst = 1;
end
always begin
#10 clk = ~clk;
rst = 0;
end
pllsim p(rst, clk);
endmodule | 0 |
2,777 | data/full_repos/permissive/101171422/de2-115/swhex/swhex.v | 101,171,422 | swhex.v | v | 11 | 41 | [] | [] | [] | [(2, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/swhex/swhex.v:7: Cannot find file containing module: 'hexdigit'\n hexdigit h0(sw[3:0], hex[6:0]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/swhex,data/full_repos/permissive/101171422/hexdigit\n data/full_repos/permissive/101171422/de2-115/swhex,data/full_repos/permissive/101171422/hexdigit.v\n data/full_repos/permissive/101171422/de2-115/swhex,data/full_repos/permissive/101171422/hexdigit.sv\n hexdigit\n hexdigit.v\n hexdigit.sv\n obj_dir/hexdigit\n obj_dir/hexdigit.v\n obj_dir/hexdigit.sv\n%Error: data/full_repos/permissive/101171422/de2-115/swhex/swhex.v:8: Cannot find file containing module: 'hexdigit'\n hexdigit h1(sw[7:4], hex[13:7]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/swhex/swhex.v:9: Cannot find file containing module: 'hexdigit'\n hexdigit h2(sw[11:8], hex[20:14]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/swhex/swhex.v:10: Cannot find file containing module: 'hexdigit'\n hexdigit h3(sw[15:12], hex[27:21]);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 275 | module | module swhex
(
input wire [17:0] sw,
output wire [8*7-1:0] hex
);
hexdigit h0(sw[3:0], hex[6:0]);
hexdigit h1(sw[7:4], hex[13:7]);
hexdigit h2(sw[11:8], hex[20:14]);
hexdigit h3(sw[15:12], hex[27:21]);
endmodule | module swhex
(
input wire [17:0] sw,
output wire [8*7-1:0] hex
); |
hexdigit h0(sw[3:0], hex[6:0]);
hexdigit h1(sw[7:4], hex[13:7]);
hexdigit h2(sw[11:8], hex[20:14]);
hexdigit h3(sw[15:12], hex[27:21]);
endmodule | 0 |
2,778 | data/full_repos/permissive/101171422/de2-115/uart_echo/1_top_level.v | 101,171,422 | 1_top_level.v | v | 53 | 89 | [] | [] | [] | [(3, 52)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/1_top_level.v:24: Cannot find file containing module: 'pll'\n pll p0(clk_i, clk50);\n ^~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/pll\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/pll.v\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/1_top_level.v:26: Cannot find file containing module: 'uart'\n uart u0(\n ^~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/1_top_level.v:40: Cannot find file containing module: 'debounce'\n debounce d0(\n ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 276 | module | module uart_echo
(
input wire clk_i,
input wire btn_reset,
input wire btn_send_back,
input wire rx,
output wire tx,
output wire [7:0] LEDG,
output wire [6:0] seven_seg
);
wire clk50;
wire tx_full, rx_empty;
wire [7:0] rec_data;
wire [7:0] send_back_data;
wire top_level_reset;
wire top_level_sendback, send_back_db;
assign top_level_reset = ~btn_reset;
assign top_level_sendback = ~btn_send_back;
pll p0(clk_i, clk50);
uart u0(
.clk(clk50),
.reset(top_level_reset),
.rd_uart(send_back_db),
.wr_uart(send_back_db),
.rx(rx),
.w_data(send_back_data),
.tx_full(tx_full),
.rx_empty(rx_empty),
.r_data(rec_data),
.tx(tx)
);
debounce d0(
.clk(clk50),
.sw(top_level_sendback),
.db_level(),
.db_tick(send_back_db)
);
assign send_back_data = rec_data;
assign LEDG = rec_data;
assign seven_seg = {1'b1, ~tx_full, 2'b11, ~rx_empty, 2'b11};
endmodule | module uart_echo
(
input wire clk_i,
input wire btn_reset,
input wire btn_send_back,
input wire rx,
output wire tx,
output wire [7:0] LEDG,
output wire [6:0] seven_seg
); |
wire clk50;
wire tx_full, rx_empty;
wire [7:0] rec_data;
wire [7:0] send_back_data;
wire top_level_reset;
wire top_level_sendback, send_back_db;
assign top_level_reset = ~btn_reset;
assign top_level_sendback = ~btn_send_back;
pll p0(clk_i, clk50);
uart u0(
.clk(clk50),
.reset(top_level_reset),
.rd_uart(send_back_db),
.wr_uart(send_back_db),
.rx(rx),
.w_data(send_back_data),
.tx_full(tx_full),
.rx_empty(rx_empty),
.r_data(rec_data),
.tx(tx)
);
debounce d0(
.clk(clk50),
.sw(top_level_sendback),
.db_level(),
.db_tick(send_back_db)
);
assign send_back_data = rec_data;
assign LEDG = rec_data;
assign seven_seg = {1'b1, ~tx_full, 2'b11, ~rx_empty, 2'b11};
endmodule | 0 |
2,779 | data/full_repos/permissive/101171422/de2-115/uart_echo/2_debounce.v | 101,171,422 | 2_debounce.v | v | 81 | 73 | [] | [] | [] | [(5, 81)] | null | data/verilator_xmls/ab08ed76-658a-4f66-bc36-8f2eb3960c28.xml | null | 277 | module | module debounce
(
input wire clk,
input wire sw,
output reg db_level,
output reg db_tick
);
localparam N = 21;
localparam ZERO = 0;
localparam WAIT1 = 1;
localparam ONE = 2;
localparam WAIT0 = 3;
reg [1:0] state_reg, state_next;
reg [N-1:0] q_reg, q_next;
always @ (posedge clk) begin
state_reg <= state_next;
q_reg <= q_next;
end
always @ (state_reg, q_reg, sw, q_next) begin
state_next <= state_reg;
q_next <= q_reg;
db_tick <= 0;
case (state_reg)
ZERO: begin
db_level <= 0;
if (sw) begin
state_next <= WAIT1;
q_next <= ~0;
end
end
WAIT1: begin
db_level <= 0;
if (sw) begin
q_next <= q_reg - 1;
if (q_next == 0) begin
state_next <= ONE;
db_tick <= 1;
end
end
else
state_next <= ZERO;
end
ONE: begin
db_level <= 1;
if (!sw) begin
state_next <= WAIT0;
q_next <= ~0;
end
end
WAIT0: begin
db_level <= 1;
if (!sw) begin
q_next <= q_reg - 1;
if (q_next == 0)
state_next <= ZERO;
end
else
state_next <= ONE;
end
endcase
end
endmodule | module debounce
(
input wire clk,
input wire sw,
output reg db_level,
output reg db_tick
); |
localparam N = 21;
localparam ZERO = 0;
localparam WAIT1 = 1;
localparam ONE = 2;
localparam WAIT0 = 3;
reg [1:0] state_reg, state_next;
reg [N-1:0] q_reg, q_next;
always @ (posedge clk) begin
state_reg <= state_next;
q_reg <= q_next;
end
always @ (state_reg, q_reg, sw, q_next) begin
state_next <= state_reg;
q_next <= q_reg;
db_tick <= 0;
case (state_reg)
ZERO: begin
db_level <= 0;
if (sw) begin
state_next <= WAIT1;
q_next <= ~0;
end
end
WAIT1: begin
db_level <= 0;
if (sw) begin
q_next <= q_reg - 1;
if (q_next == 0) begin
state_next <= ONE;
db_tick <= 1;
end
end
else
state_next <= ZERO;
end
ONE: begin
db_level <= 1;
if (!sw) begin
state_next <= WAIT0;
q_next <= ~0;
end
end
WAIT0: begin
db_level <= 1;
if (!sw) begin
q_next <= q_reg - 1;
if (q_next == 0)
state_next <= ZERO;
end
else
state_next <= ONE;
end
endcase
end
endmodule | 0 |
2,780 | data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v | 101,171,422 | 2_uart.v | v | 94 | 86 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v:29: Cannot find file containing module: 'mod_m_counter'\n mod_m_counter#(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/mod_m_counter\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/mod_m_counter.v\n data/full_repos/permissive/101171422/de2-115/uart_echo,data/full_repos/permissive/101171422/mod_m_counter.sv\n mod_m_counter\n mod_m_counter.v\n mod_m_counter.sv\n obj_dir/mod_m_counter\n obj_dir/mod_m_counter.v\n obj_dir/mod_m_counter.sv\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v:39: Cannot find file containing module: 'fifo'\n fifo#(\n ^~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v:53: Cannot find file containing module: 'uart_rx'\n uart_rx#(\n ^~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v:65: Cannot find file containing module: 'fifo'\n fifo#(\n ^~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_echo/2_uart.v:79: Cannot find file containing module: 'uart_tx'\n uart_tx#(\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 278 | module | module uart
(
input wire clk,
input wire reset,
input wire rd_uart,
input wire wr_uart,
input wire rx,
input wire [7:0] w_data,
output wire tx_full,
output wire rx_empty,
output wire [7:0] r_data,
output wire tx
);
parameter DBIT = 8;
parameter SB_TICK = 16;
parameter DVSR = 163;
parameter DVSR_BIT = 9;
parameter FIFO_W = 5;
wire tick;
wire rx_done_tick;
wire [7:0] tx_fifo_out;
wire [7:0] rx_data_out;
wire tx_empty, tx_fifo_not_empty;
wire tx_done_tick;
mod_m_counter#(
.M(DVSR),
.N(DVSR_BIT)
) m(
.clk(clk),
.reset(reset),
.q(),
.max_tick(tick)
);
fifo#(
.B(DBIT),
.W(FIFO_W)
) f_rx(
.clk(clk),
.reset(reset),
.rd(rd_uart),
.wr(rx_done_tick),
.w_data(rx_data_out),
.empty(rx_empty),
.full(),
.r_data(r_data)
);
uart_rx#(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) u_rx(
.clk(clk),
.reset(reset),
.rx(rx),
.s_tick(tick),
.rx_done_tick(rx_done_tick),
.dout(rx_data_out)
);
fifo#(
.B(DBIT),
.W(FIFO_W)
) f_tx(
.clk(clk),
.reset(reset),
.rd(tx_done_tick),
.wr(wr_uart),
.w_data(w_data),
.empty(tx_empty),
.full(tx_full),
.r_data(tx_fifo_out)
);
uart_tx#(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) u_tx(
.clk(clk),
.reset(reset),
.tx_start(tx_fifo_not_empty),
.s_tick(tick),
.din(tx_fifo_out),
.tx_done_tick(tx_done_tick),
.tx(tx)
);
assign tx_fifo_not_empty = !tx_empty;
endmodule | module uart
(
input wire clk,
input wire reset,
input wire rd_uart,
input wire wr_uart,
input wire rx,
input wire [7:0] w_data,
output wire tx_full,
output wire rx_empty,
output wire [7:0] r_data,
output wire tx
); |
parameter DBIT = 8;
parameter SB_TICK = 16;
parameter DVSR = 163;
parameter DVSR_BIT = 9;
parameter FIFO_W = 5;
wire tick;
wire rx_done_tick;
wire [7:0] tx_fifo_out;
wire [7:0] rx_data_out;
wire tx_empty, tx_fifo_not_empty;
wire tx_done_tick;
mod_m_counter#(
.M(DVSR),
.N(DVSR_BIT)
) m(
.clk(clk),
.reset(reset),
.q(),
.max_tick(tick)
);
fifo#(
.B(DBIT),
.W(FIFO_W)
) f_rx(
.clk(clk),
.reset(reset),
.rd(rd_uart),
.wr(rx_done_tick),
.w_data(rx_data_out),
.empty(rx_empty),
.full(),
.r_data(r_data)
);
uart_rx#(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) u_rx(
.clk(clk),
.reset(reset),
.rx(rx),
.s_tick(tick),
.rx_done_tick(rx_done_tick),
.dout(rx_data_out)
);
fifo#(
.B(DBIT),
.W(FIFO_W)
) f_tx(
.clk(clk),
.reset(reset),
.rd(tx_done_tick),
.wr(wr_uart),
.w_data(w_data),
.empty(tx_empty),
.full(tx_full),
.r_data(tx_fifo_out)
);
uart_tx#(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) u_tx(
.clk(clk),
.reset(reset),
.tx_start(tx_fifo_not_empty),
.s_tick(tick),
.din(tx_fifo_out),
.tx_done_tick(tx_done_tick),
.tx(tx)
);
assign tx_fifo_not_empty = !tx_empty;
endmodule | 0 |
2,781 | data/full_repos/permissive/101171422/de2-115/uart_echo/3_fifo.v | 101,171,422 | 3_fifo.v | v | 111 | 91 | [] | [] | [] | null | line:96: before: "for" | data/verilator_xmls/7670be86-e4ae-468a-9c1d-1c95dea831ce.xml | null | 279 | module | module fifo
(
input wire clk,
input wire reset,
input wire rd,
input wire wr,
input wire [B-1:0] w_data,
output wire empty,
output wire full,
output wire [B-1:0] r_data
);
parameter B = 8;
parameter W = 4;
reg [B-1:0] array_reg[2**W-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next;
reg [W-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire [W-1:0] w_ptr_succ, r_ptr_succ;
wire [1:0] wr_op;
wire wr_en;
integer i;
always @ (posedge clk, posedge reset) begin
if (reset) begin
for (i = 0; i <= 2**W-1; i = i+1)
array_reg[i] <= 0;
end
else begin
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
end
end
assign r_data = array_reg[r_ptr_reg];
assign wr_en = wr && !full_reg;
always @ (posedge clk, posedge reset) begin
if (reset) begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end
else begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
assign w_ptr_succ = w_ptr_reg + 1;
assign r_ptr_succ = r_ptr_reg + 1;
assign wr_op = {wr, rd};
always @ (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg) begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg;
case (wr_op)
2'b00: begin
end
2'b01: begin
if (!empty_reg) begin
r_ptr_next <= r_ptr_succ;
full_next <= 0;
if (r_ptr_succ == w_ptr_reg)
empty_next <= 1;
end
end
2'b10: begin
if (!full_reg) begin
w_ptr_next <= w_ptr_succ;
empty_next <= 0;
if (w_ptr_succ == r_ptr_reg)
full_next <= 1;
end
end
default: begin
w_ptr_next <= w_ptr_succ;
w_ptr_next <= r_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
endmodule | module fifo
(
input wire clk,
input wire reset,
input wire rd,
input wire wr,
input wire [B-1:0] w_data,
output wire empty,
output wire full,
output wire [B-1:0] r_data
); |
parameter B = 8;
parameter W = 4;
reg [B-1:0] array_reg[2**W-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next;
reg [W-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire [W-1:0] w_ptr_succ, r_ptr_succ;
wire [1:0] wr_op;
wire wr_en;
integer i;
always @ (posedge clk, posedge reset) begin
if (reset) begin
for (i = 0; i <= 2**W-1; i = i+1)
array_reg[i] <= 0;
end
else begin
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
end
end
assign r_data = array_reg[r_ptr_reg];
assign wr_en = wr && !full_reg;
always @ (posedge clk, posedge reset) begin
if (reset) begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end
else begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
assign w_ptr_succ = w_ptr_reg + 1;
assign r_ptr_succ = r_ptr_reg + 1;
assign wr_op = {wr, rd};
always @ (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg) begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg;
case (wr_op)
2'b00: begin
end
2'b01: begin
if (!empty_reg) begin
r_ptr_next <= r_ptr_succ;
full_next <= 0;
if (r_ptr_succ == w_ptr_reg)
empty_next <= 1;
end
end
2'b10: begin
if (!full_reg) begin
w_ptr_next <= w_ptr_succ;
empty_next <= 0;
if (w_ptr_succ == r_ptr_reg)
full_next <= 1;
end
end
default: begin
w_ptr_next <= w_ptr_succ;
w_ptr_next <= r_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
endmodule | 0 |
2,782 | data/full_repos/permissive/101171422/de2-115/uart_echo/3_mod_m.v | 101,171,422 | 3_mod_m.v | v | 25 | 49 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/f1712226-34d6-4449-822d-3e7fbaaf36e9.xml | null | 280 | module | module mod_m_counter
(
input wire clk,
input wire reset,
output wire max_tick,
output wire [N-1:0] q
);
parameter N = 4;
parameter M = 10;
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @ (posedge clk, posedge reset) begin
if (reset)
r_reg <= 0;
else
r_reg <= r_next;
end
assign r_next = (r_reg == M-1) ? 0 : r_reg + 1;
assign q = r_reg;
assign max_tick = (r_reg == M-1) ? 1 : 0;
endmodule | module mod_m_counter
(
input wire clk,
input wire reset,
output wire max_tick,
output wire [N-1:0] q
); |
parameter N = 4;
parameter M = 10;
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @ (posedge clk, posedge reset) begin
if (reset)
r_reg <= 0;
else
r_reg <= r_next;
end
assign r_next = (r_reg == M-1) ? 0 : r_reg + 1;
assign q = r_reg;
assign max_tick = (r_reg == M-1) ? 1 : 0;
endmodule | 0 |
2,783 | data/full_repos/permissive/101171422/de2-115/uart_echo/3_uart_rx.v | 101,171,422 | 3_uart_rx.v | v | 100 | 94 | [] | [] | [] | [(2, 99)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_echo/3_uart_rx.v:87: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'s_reg\' generates 4 bits.\n : ... In instance uart_rx\n if (s_reg == SB_TICK-1) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 281 | module | module uart_rx
(
input wire clk,
input wire reset,
input wire rx,
input wire s_tick,
output reg rx_done_tick,
output wire [7:0] dout
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [3:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
end
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, rx) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= 0;
case (state_reg)
IDLE: begin
if (!rx) begin
state_next <= START;
s_next <= 0;
end
end
START: begin
if (s_tick) begin
if (s_reg == 7) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {rx, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
rx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign dout = b_reg;
endmodule | module uart_rx
(
input wire clk,
input wire reset,
input wire rx,
input wire s_tick,
output reg rx_done_tick,
output wire [7:0] dout
); |
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [3:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
end
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, rx) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= 0;
case (state_reg)
IDLE: begin
if (!rx) begin
state_next <= START;
s_next <= 0;
end
end
START: begin
if (s_tick) begin
if (s_reg == 7) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {rx, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
rx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign dout = b_reg;
endmodule | 0 |
2,784 | data/full_repos/permissive/101171422/de2-115/uart_echo/3_uart_tx.v | 101,171,422 | 3_uart_tx.v | v | 112 | 104 | [] | [] | [] | null | line:112 column:2: Illegal character '\x00' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_echo/3_uart_tx.v:85: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'n_reg\' generates 3 bits.\n : ... In instance uart_tx\n if (n_reg == DBIT-1)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_echo/3_uart_tx.v:98: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'s_reg\' generates 4 bits.\n : ... In instance uart_tx\n if (s_reg == SB_TICK-1) begin\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 282 | module | module uart_tx
(
input wire clk,
input wire reset,
input wire tx_start,
input wire s_tick,
input wire [7:0] din,
output reg tx_done_tick,
output wire tx
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [2:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
reg tx_reg, tx_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
end
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg;
tx_done_tick <= 0;
case (state_reg)
IDLE: begin
tx_next <= 1;
if (tx_start) begin
state_next <= START;
s_next <= 0;
b_next <= din;
end
end
START: begin
tx_next <= 0;
if (s_tick) begin
if (s_reg == 15) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
tx_next <= b_reg[0];
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {1'b0, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
tx_next <= 1;
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
tx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign tx = tx_reg;
endmodule | module uart_tx
(
input wire clk,
input wire reset,
input wire tx_start,
input wire s_tick,
input wire [7:0] din,
output reg tx_done_tick,
output wire tx
); |
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [2:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
reg tx_reg, tx_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
end
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg;
tx_done_tick <= 0;
case (state_reg)
IDLE: begin
tx_next <= 1;
if (tx_start) begin
state_next <= START;
s_next <= 0;
b_next <= din;
end
end
START: begin
tx_next <= 0;
if (s_tick) begin
if (s_reg == 15) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
tx_next <= b_reg[0];
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {1'b0, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
tx_next <= 1;
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
tx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign tx = tx_reg;
endmodule | 0 |
2,785 | data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v | 101,171,422 | uart_hello.v | v | 70 | 43 | [] | [] | [] | [(2, 44), (47, 69)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:59: Unsupported: Ignoring delay on this delayed statement.\n #20 clk50 = ~clk50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:12: Operator ASSIGN expects 113 bits on the Assign RHS, but Assign RHS\'s CONST \'112\'h48656c6c6f20576f726c64210d0a\' generates 112 bits.\n : ... In instance uart_hello_test.u0\n reg [8*14:0] text = "Hello World!\\r\\n";\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:32: Cannot find file containing module: \'reset_delay\'\n reset_delay r0(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.v\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.sv\n reset_delay\n reset_delay.v\n reset_delay.sv\n obj_dir/reset_delay\n obj_dir/reset_delay.v\n obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:37: Cannot find file containing module: \'uart_transmitter\'\n uart_transmitter t0(\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 285 | module | module uart_hello
(
input wire clk50,
input wire uart_rts,
input wire uart_rxd,
output wire uart_cts,
output wire uart_txd
);
`define LEN 14
reg [8*`LEN:0] text = "Hello World!\r\n";
reg [7:0] data;
wire rst;
wire nextch;
integer idx, i;
initial begin
idx <= 0;
end
always @ (posedge clk50) begin
for (i = 0; i < 8; i = i + 1)
data[i] = text[8*(`LEN-1-idx) + i];
if (nextch)
idx = (idx + 1) % `LEN;
end
assign uart_cts = 0;
reset_delay r0(
.clk(clk50),
.rst(rst)
);
uart_transmitter t0(
.clk(clk50),
.rst(rst),
.data(data),
.nextch(nextch),
.txd(uart_txd)
);
endmodule | module uart_hello
(
input wire clk50,
input wire uart_rts,
input wire uart_rxd,
output wire uart_cts,
output wire uart_txd
); |
`define LEN 14
reg [8*`LEN:0] text = "Hello World!\r\n";
reg [7:0] data;
wire rst;
wire nextch;
integer idx, i;
initial begin
idx <= 0;
end
always @ (posedge clk50) begin
for (i = 0; i < 8; i = i + 1)
data[i] = text[8*(`LEN-1-idx) + i];
if (nextch)
idx = (idx + 1) % `LEN;
end
assign uart_cts = 0;
reset_delay r0(
.clk(clk50),
.rst(rst)
);
uart_transmitter t0(
.clk(clk50),
.rst(rst),
.data(data),
.nextch(nextch),
.txd(uart_txd)
);
endmodule | 0 |
2,786 | data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v | 101,171,422 | uart_hello.v | v | 70 | 43 | [] | [] | [] | [(2, 44), (47, 69)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:59: Unsupported: Ignoring delay on this delayed statement.\n #20 clk50 = ~clk50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:12: Operator ASSIGN expects 113 bits on the Assign RHS, but Assign RHS\'s CONST \'112\'h48656c6c6f20576f726c64210d0a\' generates 112 bits.\n : ... In instance uart_hello_test.u0\n reg [8*14:0] text = "Hello World!\\r\\n";\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:32: Cannot find file containing module: \'reset_delay\'\n reset_delay r0(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.v\n data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.sv\n reset_delay\n reset_delay.v\n reset_delay.sv\n obj_dir/reset_delay\n obj_dir/reset_delay.v\n obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:37: Cannot find file containing module: \'uart_transmitter\'\n uart_transmitter t0(\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 285 | module | module uart_hello_test();
reg clk50;
wire uart_rts;
wire uart_rxd;
wire uart_cts;
wire uart_txd;
initial begin
clk50 = 0;
end
always begin
#20 clk50 = ~clk50;
end
uart_hello u0(
.clk50(clk50),
.uart_rts(uart_rts),
.uart_rxd(uart_rxd),
.uart_cts(uart_cts),
.uart_txd(uart_txd)
);
endmodule | module uart_hello_test(); |
reg clk50;
wire uart_rts;
wire uart_rxd;
wire uart_cts;
wire uart_txd;
initial begin
clk50 = 0;
end
always begin
#20 clk50 = ~clk50;
end
uart_hello u0(
.clk50(clk50),
.uart_rts(uart_rts),
.uart_rxd(uart_rxd),
.uart_cts(uart_cts),
.uart_txd(uart_txd)
);
endmodule | 0 |
2,787 | data/full_repos/permissive/101171422/de2-115/uart_hello/uart_transmitter.v | 101,171,422 | uart_transmitter.v | v | 88 | 80 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/0677fb4c-14ee-4cdf-8346-251e78721996.xml | null | 286 | module | module uart_transmitter
(
input wire clk,
input wire rst,
input wire [7:0] data,
output reg nextch,
output reg txd
);
parameter CLK = 50_000_000;
parameter BAUD = 9600;
localparam RATE = CLK/BAUD;
localparam INIT = 0;
localparam TXD = 1;
reg state, next;
reg [31:0] cnt;
reg [4:0] bitcnt;
reg [9:0] rshift;
reg shift, load, clear, getch, gotch;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
state <= INIT;
cnt <= 0;
bitcnt <= 0;
gotch <= 0;
end
else begin
if (nextch) begin
nextch <= 0;
gotch <= 1;
end
else if (getch && !gotch)
nextch <= 1;
cnt <= cnt + 1;
if (cnt >= RATE) begin
state <= next;
cnt <= 0;
if (load)
rshift <= {1'b1, data[7:0], 1'b0};
if (clear) begin
bitcnt <= 0;
gotch <= 0;
end
if (shift) begin
rshift <= rshift >> 1;
bitcnt <= bitcnt + 1;
end
end
end
end
always @ (state or bitcnt or rshift) begin
load <= 0;
shift <= 0;
clear <= 0;
getch <= 0;
txd <= 1;
case (state)
INIT: begin
next <= TXD;
load <= 1;
shift <= 0;
clear <= 0;
end
TXD: begin
if (bitcnt >= 9) begin
next <= INIT;
clear <= 1;
getch <= 1;
end
else begin
next <= TXD;
shift <= 1;
txd <= rshift[0];
end
end
endcase
end
endmodule | module uart_transmitter
(
input wire clk,
input wire rst,
input wire [7:0] data,
output reg nextch,
output reg txd
); |
parameter CLK = 50_000_000;
parameter BAUD = 9600;
localparam RATE = CLK/BAUD;
localparam INIT = 0;
localparam TXD = 1;
reg state, next;
reg [31:0] cnt;
reg [4:0] bitcnt;
reg [9:0] rshift;
reg shift, load, clear, getch, gotch;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
state <= INIT;
cnt <= 0;
bitcnt <= 0;
gotch <= 0;
end
else begin
if (nextch) begin
nextch <= 0;
gotch <= 1;
end
else if (getch && !gotch)
nextch <= 1;
cnt <= cnt + 1;
if (cnt >= RATE) begin
state <= next;
cnt <= 0;
if (load)
rshift <= {1'b1, data[7:0], 1'b0};
if (clear) begin
bitcnt <= 0;
gotch <= 0;
end
if (shift) begin
rshift <= rshift >> 1;
bitcnt <= bitcnt + 1;
end
end
end
end
always @ (state or bitcnt or rshift) begin
load <= 0;
shift <= 0;
clear <= 0;
getch <= 0;
txd <= 1;
case (state)
INIT: begin
next <= TXD;
load <= 1;
shift <= 0;
clear <= 0;
end
TXD: begin
if (bitcnt >= 9) begin
next <= INIT;
clear <= 1;
getch <= 1;
end
else begin
next <= TXD;
shift <= 1;
txd <= rshift[0];
end
end
endcase
end
endmodule | 0 |
2,788 | data/full_repos/permissive/101171422/de2-115/up3/up3.v | 101,171,422 | up3.v | v | 128 | 45 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/up3/up3.v:29: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'ar_\' generates 8 bits.\n : ... In instance up3\n assign ar = ar_;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/up3/up3.v:111: Cannot find file containing module: \'altsyncram\'\n altsyncram ram(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/up3,data/full_repos/permissive/101171422/altsyncram\n data/full_repos/permissive/101171422/de2-115/up3,data/full_repos/permissive/101171422/altsyncram.v\n data/full_repos/permissive/101171422/de2-115/up3,data/full_repos/permissive/101171422/altsyncram.sv\n altsyncram\n altsyncram.v\n altsyncram.sv\n obj_dir/altsyncram\n obj_dir/altsyncram.v\n obj_dir/altsyncram.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 287 | module | module up3
(
input wire clk,
input wire rst,
output reg [7:0] pc,
output reg [15:0] ra,
output wire [15:0] dr,
output reg [15:0] ir
);
localparam RESET = 0;
localparam FETCH = 1;
localparam DECODE = 2;
localparam OP_ADD = 3;
localparam OP_STORE = 4;
localparam OP_STORE2 = 5;
localparam OP_STORE3 = 6;
localparam OP_LOAD = 7;
localparam OP_JUMP = 8;
reg [3:0] state;
wire [15:0] dr_;
reg [7:0] ar_;
wire [15:0] ar;
reg rw_;
wire rw;
assign dr = dr_;
assign ar = ar_;
assign rw = rw_;
always @ (posedge clk or posedge rst) begin
if (rst)
state = RESET;
else
case (state)
RESET: begin
pc <= 0;
ra <= 0;
state <= FETCH;
end
FETCH: begin
ir <= dr;
pc <= pc + 1;
state <= DECODE;
end
DECODE: begin
case (ir[15:8])
'b00:
state <= OP_ADD;
'b01:
state <= OP_STORE;
'b10:
state <= OP_LOAD;
'b11:
state <= OP_JUMP;
default:
state <= FETCH;
endcase
end
OP_ADD: begin
ra <= ra + dr;
state <= FETCH;
end
OP_STORE:
state <= OP_STORE2;
OP_STORE2:
state <= OP_STORE3;
OP_LOAD: begin
ra <= dr;
state <= FETCH;
end
OP_JUMP: begin
pc <= ir[7:0];
state <= FETCH;
end
default:
state <= FETCH;
endcase
end
always @ (state or pc or ir) begin
case (state)
RESET: ar_ <= 0;
FETCH: ar_ <= pc;
DECODE: ar_ <= ir[7:0];
OP_ADD: ar_ <= pc;
OP_STORE: ar_ <= ir[7:0];
OP_STORE2: ar_ <= pc;
OP_LOAD: ar_ <= pc;
OP_JUMP: ar_ <= ir[7:0];
default: ar_ <= pc;
endcase
case (state)
OP_STORE: rw_ <= 1;
default: rw_ <= 0;
endcase
end
altsyncram ram(
.wren_a(rw),
.clock0(clk),
.address_a(ar),
.data_a(ra),
.q_a(dr_)
);
defparam
ram.operation_mode = "SINGLE_PORT",
ram.width_a = 16,
ram.widthad_a = 8,
ram.outdata_reg_a = "UNREGISTERED",
ram.lpm_type = "altsyncram",
ram.init_file = "program.mif",
ram.intended_device_family = "Cyclone";
endmodule | module up3
(
input wire clk,
input wire rst,
output reg [7:0] pc,
output reg [15:0] ra,
output wire [15:0] dr,
output reg [15:0] ir
); |
localparam RESET = 0;
localparam FETCH = 1;
localparam DECODE = 2;
localparam OP_ADD = 3;
localparam OP_STORE = 4;
localparam OP_STORE2 = 5;
localparam OP_STORE3 = 6;
localparam OP_LOAD = 7;
localparam OP_JUMP = 8;
reg [3:0] state;
wire [15:0] dr_;
reg [7:0] ar_;
wire [15:0] ar;
reg rw_;
wire rw;
assign dr = dr_;
assign ar = ar_;
assign rw = rw_;
always @ (posedge clk or posedge rst) begin
if (rst)
state = RESET;
else
case (state)
RESET: begin
pc <= 0;
ra <= 0;
state <= FETCH;
end
FETCH: begin
ir <= dr;
pc <= pc + 1;
state <= DECODE;
end
DECODE: begin
case (ir[15:8])
'b00:
state <= OP_ADD;
'b01:
state <= OP_STORE;
'b10:
state <= OP_LOAD;
'b11:
state <= OP_JUMP;
default:
state <= FETCH;
endcase
end
OP_ADD: begin
ra <= ra + dr;
state <= FETCH;
end
OP_STORE:
state <= OP_STORE2;
OP_STORE2:
state <= OP_STORE3;
OP_LOAD: begin
ra <= dr;
state <= FETCH;
end
OP_JUMP: begin
pc <= ir[7:0];
state <= FETCH;
end
default:
state <= FETCH;
endcase
end
always @ (state or pc or ir) begin
case (state)
RESET: ar_ <= 0;
FETCH: ar_ <= pc;
DECODE: ar_ <= ir[7:0];
OP_ADD: ar_ <= pc;
OP_STORE: ar_ <= ir[7:0];
OP_STORE2: ar_ <= pc;
OP_LOAD: ar_ <= pc;
OP_JUMP: ar_ <= ir[7:0];
default: ar_ <= pc;
endcase
case (state)
OP_STORE: rw_ <= 1;
default: rw_ <= 0;
endcase
end
altsyncram ram(
.wren_a(rw),
.clock0(clk),
.address_a(ar),
.data_a(ra),
.q_a(dr_)
);
defparam
ram.operation_mode = "SINGLE_PORT",
ram.width_a = 16,
ram.widthad_a = 8,
ram.outdata_reg_a = "UNREGISTERED",
ram.lpm_type = "altsyncram",
ram.init_file = "program.mif",
ram.intended_device_family = "Cyclone";
endmodule | 0 |
2,789 | data/full_repos/permissive/101171422/de2-115/vgadla/reset_delay.v | 101,171,422 | reset_delay.v | v | 16 | 30 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/d8f2453e-f200-4a6c-a23d-724c1105e6b5.xml | null | 289 | module | module reset_delay
(
input wire clk,
output reg rst
);
reg [19:0] cnt;
always @ (posedge clk) begin
if (cnt != 'hffff) begin
cnt <= cnt + 1;
rst <= 0;
end
else
rst <= 1;
end
endmodule | module reset_delay
(
input wire clk,
output reg rst
); |
reg [19:0] cnt;
always @ (posedge clk) begin
if (cnt != 'hffff) begin
cnt <= cnt + 1;
rst <= 0;
end
else
rst <= 1;
end
endmodule | 0 |
2,790 | data/full_repos/permissive/101171422/de2-115/vgadla/vga.v | 101,171,422 | vga.v | v | 108 | 71 | [] | [] | [] | null | line:40: before: "SYNC_BACK" | data/verilator_xmls/14f49774-c0bb-460e-bb2c-ea9e8f54fb59.xml | null | 290 | module | module vga
(
input wire clk,
input wire rst,
input wire [7:0] r,
input wire [7:0] g,
input wire [7:0] b,
output reg [9:0] x,
output reg [9:0] y,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output reg vga_hs,
output reg vga_vs,
output wire vga_sync,
output wire vga_blank
);
parameter H_SYNC_CYC = 96;
parameter H_SYNC_BACK = 45+3;
parameter H_SYNC_ACT = 640;
parameter H_SYNC_FRONT = 13+3;
parameter H_SYNC_TOTAL = 800;
parameter V_SYNC_CYC = 2;
parameter V_SYNC_BACK = 30+2;
parameter V_SYNC_ACT = 480;
parameter V_SYNC_FRONT = 9+2;
parameter V_SYNC_TOTAL = 525;
parameter X_START = H_SYNC_CYC+H_SYNC_BACK+4;
parameter Y_START = V_SYNC_CYC+V_SYNC_BACK;
reg [9:0] h_cnt;
reg [9:0] v_cnt;
assign vga_blank = vga_hs && vga_vs;
assign vga_sync = 0;
assign vga_r = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT)
? r : 0;
assign vga_g = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT)
? g : 0;
assign vga_b = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >=Y_START && v_cnt < Y_START+V_SYNC_ACT)
? b : 0;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
x <= 0;
y <= 0;
end
else begin
if (h_cnt >= X_START && h_cnt < X_START+H_SYNC_ACT &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT) begin
x <= h_cnt - X_START;
y <= v_cnt - Y_START;
end
end
end
always @ (posedge clk or negedge rst) begin
if (!rst) begin
h_cnt <= 0;
vga_hs <= 0;
end
else begin
if (h_cnt < H_SYNC_TOTAL)
h_cnt <= h_cnt + 1;
else
h_cnt <= 0;
if (h_cnt < H_SYNC_CYC)
vga_hs <= 0;
else
vga_hs <= 1;
end
end
always @ (posedge clk or negedge rst) begin
if (!rst) begin
v_cnt <= 0;
vga_vs <= 0;
end
else begin
if (h_cnt == 0) begin
if (v_cnt < V_SYNC_TOTAL)
v_cnt <= v_cnt + 1;
else
v_cnt <= 0;
if (v_cnt < V_SYNC_CYC)
vga_vs <= 0;
else
vga_vs <= 1;
end
end
end
endmodule | module vga
(
input wire clk,
input wire rst,
input wire [7:0] r,
input wire [7:0] g,
input wire [7:0] b,
output reg [9:0] x,
output reg [9:0] y,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output reg vga_hs,
output reg vga_vs,
output wire vga_sync,
output wire vga_blank
); |
parameter H_SYNC_CYC = 96;
parameter H_SYNC_BACK = 45+3;
parameter H_SYNC_ACT = 640;
parameter H_SYNC_FRONT = 13+3;
parameter H_SYNC_TOTAL = 800;
parameter V_SYNC_CYC = 2;
parameter V_SYNC_BACK = 30+2;
parameter V_SYNC_ACT = 480;
parameter V_SYNC_FRONT = 9+2;
parameter V_SYNC_TOTAL = 525;
parameter X_START = H_SYNC_CYC+H_SYNC_BACK+4;
parameter Y_START = V_SYNC_CYC+V_SYNC_BACK;
reg [9:0] h_cnt;
reg [9:0] v_cnt;
assign vga_blank = vga_hs && vga_vs;
assign vga_sync = 0;
assign vga_r = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT)
? r : 0;
assign vga_g = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT)
? g : 0;
assign vga_b = (h_cnt >= X_START+9 && h_cnt < X_START+H_SYNC_ACT+9 &&
v_cnt >=Y_START && v_cnt < Y_START+V_SYNC_ACT)
? b : 0;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
x <= 0;
y <= 0;
end
else begin
if (h_cnt >= X_START && h_cnt < X_START+H_SYNC_ACT &&
v_cnt >= Y_START && v_cnt < Y_START+V_SYNC_ACT) begin
x <= h_cnt - X_START;
y <= v_cnt - Y_START;
end
end
end
always @ (posedge clk or negedge rst) begin
if (!rst) begin
h_cnt <= 0;
vga_hs <= 0;
end
else begin
if (h_cnt < H_SYNC_TOTAL)
h_cnt <= h_cnt + 1;
else
h_cnt <= 0;
if (h_cnt < H_SYNC_CYC)
vga_hs <= 0;
else
vga_hs <= 1;
end
end
always @ (posedge clk or negedge rst) begin
if (!rst) begin
v_cnt <= 0;
vga_vs <= 0;
end
else begin
if (h_cnt == 0) begin
if (v_cnt < V_SYNC_TOTAL)
v_cnt <= v_cnt + 1;
else
v_cnt <= 0;
if (v_cnt < V_SYNC_CYC)
vga_vs <= 0;
else
vga_vs <= 1;
end
end
end
endmodule | 0 |
2,791 | data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v | 101,171,422 | vgadla.v | v | 320 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:288: Unsupported: Ignoring delay on this delayed statement.\n #5 key[0] = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:289: Unsupported: Ignoring delay on this delayed statement.\n #12000 key[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:293: Unsupported: Ignoring delay on this delayed statement.\n #20 clk50 = ~clk50;\n ^\n%Error: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:294: Unsupported or unknown PLI call: $monitor\n $monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 291 | module | module vgadla
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output wire [8:0] ledg,
output wire [17:0] ledr
);
localparam INIT = 0;
localparam TEST1 = 1;
localparam TEST2 = 2;
localparam TEST3 = 3;
localparam TEST4 = 4;
localparam TEST5 = 5;
localparam TEST6 = 6;
localparam DRAW = 7;
localparam UPDATE = 8;
localparam NEW = 9;
localparam FG = 16'hffff;
wire init;
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
wire xl, yl;
reg [9:0] xw, yw;
reg [30:0] xr;
reg [28:0] yr;
reg [19:0] addr;
reg [15:0] data;
reg [3:0] state;
reg [3:0] sum;
reg [8:0] ledg_;
reg [17:0] ledr_;
reg lock;
reg we;
assign sram_addr = addr;
assign sram_ub_n = 0;
assign sram_lb_n = 0;
assign sram_ce_n = 0;
assign sram_oe_n = 0;
assign sram_we_n = we;
assign sram_dq = (we) ? 16'hzzzz : data;
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
assign xl = xr[27] ^ xr[30];
assign yl = yr[26] ^ yr[28];
assign init = ~key[0];
assign ledg = ledg_;
assign ledr = ledr_;
always @ (posedge vga_ctrl_clk) begin
if (init) begin
addr <= {x, y};
we <= 1'b0;
data <= 16'b0;
xr <= 31'h55555555;
yr <= 29'h55555555;
xw <= 10'd155;
yw <= 10'd120;
state <= INIT;
end
else if ((~vga_vs | ~vga_hs) & key[1]) begin
case (state)
INIT: begin
addr <= {10'd160,10'd120};
we <= 1'b0;
data <= FG;
state <= TEST1;
end
TEST1: begin
lock <= 1'b1;
sum <= 0;
we <= 1'b1;
addr <= {xw - 10'd1, yw};
state <= TEST2;
end
TEST2: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw + 10'd1, yw};
state <= TEST3;
end
TEST3: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw - 10'd1};
state <= TEST4;
end
TEST4: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw + 10'd1};
state <= TEST5;
end
TEST5: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
state <= TEST6;
end
TEST6: begin
if (lock & sum > 0) begin
ledr_ <= {4'b0, xw[9:0], sum[3:0]};
ledg_ <= {yw[8:0]};
state <= DRAW;
end
else begin
ledr_ <= 18'b0;
ledg_ <= 9'b0;
state <= UPDATE;
end
end
DRAW: begin
we <= 1'b0;
addr <= {xw, yw};
data <= FG;
state <= NEW;
end
UPDATE: begin
we <= 1'b1;
if (xw < 10'd318 & xr[30] == 1)
xw <= xw + 1;
else if (xw > 10'd2 & xr[30] == 0)
xw <= xw - 1;
if (yw < 10'd237 & yr[28] == 1)
yw <= yw + 1;
else if (yw > 10'd2 & yr[28] == 0)
yw <= yw - 1;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
NEW: begin
we <= 1'b1;
if (xr[30])
xw <= 10'd318;
else
xw <= 10'd2;
if (yr[28])
yw <= 10'd238;
else
yw <= 10'd2;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
endcase
end
else begin
lock <= 1'b0;
addr <= {x, y};
we <= 1'b1;
end
end
reset_delay r0(
.clk(clk50),
.rst(rst)
);
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule | module vgadla
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output wire [8:0] ledg,
output wire [17:0] ledr
); |
localparam INIT = 0;
localparam TEST1 = 1;
localparam TEST2 = 2;
localparam TEST3 = 3;
localparam TEST4 = 4;
localparam TEST5 = 5;
localparam TEST6 = 6;
localparam DRAW = 7;
localparam UPDATE = 8;
localparam NEW = 9;
localparam FG = 16'hffff;
wire init;
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
wire xl, yl;
reg [9:0] xw, yw;
reg [30:0] xr;
reg [28:0] yr;
reg [19:0] addr;
reg [15:0] data;
reg [3:0] state;
reg [3:0] sum;
reg [8:0] ledg_;
reg [17:0] ledr_;
reg lock;
reg we;
assign sram_addr = addr;
assign sram_ub_n = 0;
assign sram_lb_n = 0;
assign sram_ce_n = 0;
assign sram_oe_n = 0;
assign sram_we_n = we;
assign sram_dq = (we) ? 16'hzzzz : data;
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
assign xl = xr[27] ^ xr[30];
assign yl = yr[26] ^ yr[28];
assign init = ~key[0];
assign ledg = ledg_;
assign ledr = ledr_;
always @ (posedge vga_ctrl_clk) begin
if (init) begin
addr <= {x, y};
we <= 1'b0;
data <= 16'b0;
xr <= 31'h55555555;
yr <= 29'h55555555;
xw <= 10'd155;
yw <= 10'd120;
state <= INIT;
end
else if ((~vga_vs | ~vga_hs) & key[1]) begin
case (state)
INIT: begin
addr <= {10'd160,10'd120};
we <= 1'b0;
data <= FG;
state <= TEST1;
end
TEST1: begin
lock <= 1'b1;
sum <= 0;
we <= 1'b1;
addr <= {xw - 10'd1, yw};
state <= TEST2;
end
TEST2: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw + 10'd1, yw};
state <= TEST3;
end
TEST3: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw - 10'd1};
state <= TEST4;
end
TEST4: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
addr <= {xw, yw + 10'd1};
state <= TEST5;
end
TEST5: begin
we <= 1'b1;
sum <= sum + {3'b0, sram_dq[15]};
state <= TEST6;
end
TEST6: begin
if (lock & sum > 0) begin
ledr_ <= {4'b0, xw[9:0], sum[3:0]};
ledg_ <= {yw[8:0]};
state <= DRAW;
end
else begin
ledr_ <= 18'b0;
ledg_ <= 9'b0;
state <= UPDATE;
end
end
DRAW: begin
we <= 1'b0;
addr <= {xw, yw};
data <= FG;
state <= NEW;
end
UPDATE: begin
we <= 1'b1;
if (xw < 10'd318 & xr[30] == 1)
xw <= xw + 1;
else if (xw > 10'd2 & xr[30] == 0)
xw <= xw - 1;
if (yw < 10'd237 & yr[28] == 1)
yw <= yw + 1;
else if (yw > 10'd2 & yr[28] == 0)
yw <= yw - 1;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
NEW: begin
we <= 1'b1;
if (xr[30])
xw <= 10'd318;
else
xw <= 10'd2;
if (yr[28])
yw <= 10'd238;
else
yw <= 10'd2;
xr <= {xr[29:0], xl} ;
yr <= {yr[27:0], yl} ;
state <= TEST1;
end
endcase
end
else begin
lock <= 1'b0;
addr <= {x, y};
we <= 1'b1;
end
end
reset_delay r0(
.clk(clk50),
.rst(rst)
);
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule | 0 |
2,792 | data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v | 101,171,422 | vgadla.v | v | 320 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:288: Unsupported: Ignoring delay on this delayed statement.\n #5 key[0] = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:289: Unsupported: Ignoring delay on this delayed statement.\n #12000 key[0] = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:293: Unsupported: Ignoring delay on this delayed statement.\n #20 clk50 = ~clk50;\n ^\n%Error: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:294: Unsupported or unknown PLI call: $monitor\n $monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 291 | module | module vgadla_test();
reg clk50;
reg [3:0] key;
reg [17:0] sw;
wire [15:0] sram_dq;
wire [19:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire vga_clk;
wire vga_hs;
wire vga_vs;
wire vga_blank;
wire vga_sync;
wire [7:0] vga_r;
wire [7:0] vga_g;
wire [7:0] vga_b;
wire [8:0] ledg;
wire [17:0] ledr;
initial begin
clk50 = 0;
key = 'hf;
sw = 0;
#5 key[0] = 0;
#12000 key[0] = 1;
end
always begin
#20 clk50 = ~clk50;
$monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",
$time, v.state, v.we, v.sram_dq, v.data, v.sum, v.xw, v.yw, v.xr, v.yr);
end
vgadla v(
.clk50(clk50),
.key(key),
.sw(sw),
.sram_dq(sram_dq),
.sram_addr(sram_addr),
.sram_ub_n(sram_ub_n),
.sram_lb_n(sram_lb_n),
.sram_we_n(sram_we_n),
.sram_ce_n(sram_ce_n),
.sram_oe_n(sram_oe_n),
.vga_clk(vga_clk),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.ledg(ledg),
.ledr(ledr)
);
endmodule | module vgadla_test(); |
reg clk50;
reg [3:0] key;
reg [17:0] sw;
wire [15:0] sram_dq;
wire [19:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire vga_clk;
wire vga_hs;
wire vga_vs;
wire vga_blank;
wire vga_sync;
wire [7:0] vga_r;
wire [7:0] vga_g;
wire [7:0] vga_b;
wire [8:0] ledg;
wire [17:0] ledr;
initial begin
clk50 = 0;
key = 'hf;
sw = 0;
#5 key[0] = 0;
#12000 key[0] = 1;
end
always begin
#20 clk50 = ~clk50;
$monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",
$time, v.state, v.we, v.sram_dq, v.data, v.sum, v.xw, v.yw, v.xr, v.yr);
end
vgadla v(
.clk50(clk50),
.key(key),
.sw(sw),
.sram_dq(sram_dq),
.sram_addr(sram_addr),
.sram_ub_n(sram_ub_n),
.sram_lb_n(sram_lb_n),
.sram_we_n(sram_we_n),
.sram_ce_n(sram_ce_n),
.sram_oe_n(sram_oe_n),
.vga_clk(vga_clk),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.ledg(ledg),
.ledr(ledr)
);
endmodule | 0 |
2,793 | data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v | 101,171,422 | vgaram.v | v | 89 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:43: Unsized numbers/parameters not allowed in replications.\n : ... In instance vgaram\n assign sram_we_n = {key[0] ? 1 : 0};\n ^\n ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:54: Cannot find file containing module: \'reset_delay\'\n reset_delay r0(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay\n data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay.v\n data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay.sv\n reset_delay\n reset_delay.v\n reset_delay.sv\n obj_dir/reset_delay\n obj_dir/reset_delay.v\n obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:64: Cannot find file containing module: \'pll\'\n pll p0(\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:72: Cannot find file containing module: \'vga\'\n vga v0(\n ^~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 295 | module | module vgaram
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b
);
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
assign sram_addr = {x[9:0], y[9:0]};
assign sram_ub_n = 0;
assign sram_lb_n = 0;
assign sram_ce_n = 0;
assign sram_oe_n = 0;
assign sram_we_n = {key[0] ? 1 : 0};
assign sram_dq = (key[0] ? 16'hzzzz :
(key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
sw[15:0]));
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
reset_delay r0(
.clk(clk50),
.rst(rst)
);
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule | module vgaram
(
input wire clk50,
input wire [3:0] key,
input wire [17:0] sw,
inout wire [15:0] sram_dq,
output wire [19:0] sram_addr,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_we_n,
output wire sram_ce_n,
output wire sram_oe_n,
output wire vga_clk,
output wire vga_hs,
output wire vga_vs,
output wire vga_blank,
output wire vga_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b
); |
wire rst;
wire vga_ctrl_clk;
wire [7:0] r, g, b;
wire [9:0] x, y;
assign sram_addr = {x[9:0], y[9:0]};
assign sram_ub_n = 0;
assign sram_lb_n = 0;
assign sram_ce_n = 0;
assign sram_oe_n = 0;
assign sram_we_n = {key[0] ? 1 : 0};
assign sram_dq = (key[0] ? 16'hzzzz :
(key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
sw[15:0]));
assign r = {sram_dq[15:12], 4'b0};
assign g = {sram_dq[11:8], 4'b0};
assign b = {sram_dq[7:4], 4'b0};
reset_delay r0(
.clk(clk50),
.rst(rst)
);
pll p0(
.areset(~rst),
.inclk0(clk50),
.c0(vga_ctrl_clk),
.c1(vga_clk)
);
vga v0(
.clk(vga_ctrl_clk),
.rst(rst),
.r(r),
.g(g),
.b(b),
.x(x),
.y(y),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.vga_blank(vga_blank),
.vga_sync(vga_sync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule | 0 |
2,794 | data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v | 101,171,422 | vga.v | v | 42 | 43 | [] | [] | [] | [(1, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v:38: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s OR generates 32 bits.\n : ... In instance vga\n assign rgb = (x^y)<<16 | (x+y)<<8;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v:40: Cannot find file containing module: \'vsg\'\n vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);\n ^~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg.v\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg.sv\n vsg\n vsg.v\n vsg.sv\n obj_dir/vsg\n obj_dir/vsg.v\n obj_dir/vsg.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 298 | module | module vga
(
input wire rst,
input wire clk,
output reg blank_n,
output reg hs,
output reg sync_n,
output reg vs,
output wire [23:0] rgb
);
reg [31:0] x, y;
wire l_hs, l_vs, l_blank_n;
always @ (posedge clk, negedge rst) begin
if (!rst) begin
x <= 0;
y <= 0;
end
else if (l_hs == 0 && l_vs == 0) begin
x <= 0;
y <= 0;
end
else if (l_blank_n == 1) begin
x = x + 1;
if (x == 640) begin
x = 0;
y = y + 1;
end
end
end
always @ (negedge clk) begin
hs <= l_hs;
vs <= l_vs;
blank_n <= l_blank_n;
end
assign rgb = (x^y)<<16 | (x+y)<<8;
vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);
endmodule | module vga
(
input wire rst,
input wire clk,
output reg blank_n,
output reg hs,
output reg sync_n,
output reg vs,
output wire [23:0] rgb
); |
reg [31:0] x, y;
wire l_hs, l_vs, l_blank_n;
always @ (posedge clk, negedge rst) begin
if (!rst) begin
x <= 0;
y <= 0;
end
else if (l_hs == 0 && l_vs == 0) begin
x <= 0;
y <= 0;
end
else if (l_blank_n == 1) begin
x = x + 1;
if (x == 640) begin
x = 0;
y = y + 1;
end
end
end
always @ (negedge clk) begin
hs <= l_hs;
vs <= l_vs;
blank_n <= l_blank_n;
end
assign rgb = (x^y)<<16 | (x+y)<<8;
vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);
endmodule | 0 |
2,795 | data/full_repos/permissive/101171422/de2-115/vgaxor/vgaxor.v | 101,171,422 | vgaxor.v | v | 21 | 42 | [] | [] | [] | [(1, 21)] | null | null | 1: b"%Error: data/full_repos/permissive/101171422/de2-115/vgaxor/vgaxor.v:13: Cannot find file containing module: 'reset_delay'\n reset_delay rd(clk50, rst);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/reset_delay\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/reset_delay.v\n data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/reset_delay.sv\n reset_delay\n reset_delay.v\n reset_delay.sv\n obj_dir/reset_delay\n obj_dir/reset_delay.v\n obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/vgaxor/vgaxor.v:15: Cannot find file containing module: 'pll'\n pll pl(~rst, clk50, clk25);\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/vgaxor/vgaxor.v:18: Cannot find file containing module: 'vga'\n vga vg(rst, clk25, vga_blank_n, vga_hs, \n ^~~\n%Error: Exiting due to 3 error(s)\n" | 299 | module | module vgaxor
(
input clk50,
output vga_clk,
output vga_blank_n,
output vga_hs,
output vga_sync_n,
output vga_vs,
output [23:0] vga_rgb
);
wire rst, clk25;
reset_delay rd(clk50, rst);
pll pl(~rst, clk50, clk25);
assign vga_clk = clk25;
vga vg(rst, clk25, vga_blank_n, vga_hs,
vga_sync_n, vga_vs, vga_rgb);
endmodule | module vgaxor
(
input clk50,
output vga_clk,
output vga_blank_n,
output vga_hs,
output vga_sync_n,
output vga_vs,
output [23:0] vga_rgb
); |
wire rst, clk25;
reset_delay rd(clk50, rst);
pll pl(~rst, clk50, clk25);
assign vga_clk = clk25;
vga vg(rst, clk25, vga_blank_n, vga_hs,
vga_sync_n, vga_vs, vga_rgb);
endmodule | 0 |
2,796 | data/full_repos/permissive/101171422/de2-115/vgaxor/vsg.v | 101,171,422 | vsg.v | v | 90 | 82 | [] | [] | [] | [(35, 90)] | null | data/verilator_xmls/09c3c6c3-e1a0-4746-9d58-060c44d4e547.xml | null | 300 | module | module vsg
(
input wire rst,
input wire clk,
output reg blank_n,
output reg hs,
output reg vs
);
parameter hori_line = 800;
parameter hori_back = 144;
parameter hori_front = 16;
parameter vert_line = 525;
parameter vert_back = 34;
parameter vert_front = 11;
parameter H_sync_cycle = 96;
parameter V_sync_cycle = 2;
reg [10:0] h_cnt;
reg [9:0] v_cnt;
wire c_hd, c_vd, c_blank_n;
wire h_valid, v_valid;
always @ (negedge clk, posedge rst) begin
if (rst) begin
h_cnt <= 0;
v_cnt <= 0;
end
else begin
if (h_cnt == hori_line - 1) begin
h_cnt <= 0;
if (v_cnt == vert_line - 1)
v_cnt <= 0;
else
v_cnt <= v_cnt + 1;
end
else
h_cnt <= h_cnt + 1;
end
end
assign c_hd = (h_cnt < H_sync_cycle) ? 0 : 1;
assign c_vd = (v_cnt < V_sync_cycle) ? 0 : 1;
assign h_valid = (h_cnt < (hori_line-hori_front) && h_cnt >= hori_back) ? 1 : 0;
assign v_valid = (v_cnt < (vert_line-vert_front) && v_cnt >= vert_back) ? 1 : 0;
assign c_blank_n = h_valid && v_valid;
always @ (negedge clk) begin
hs <= c_hd;
vs <= c_vd;
blank_n <= c_blank_n;
end
endmodule | module vsg
(
input wire rst,
input wire clk,
output reg blank_n,
output reg hs,
output reg vs
); |
parameter hori_line = 800;
parameter hori_back = 144;
parameter hori_front = 16;
parameter vert_line = 525;
parameter vert_back = 34;
parameter vert_front = 11;
parameter H_sync_cycle = 96;
parameter V_sync_cycle = 2;
reg [10:0] h_cnt;
reg [9:0] v_cnt;
wire c_hd, c_vd, c_blank_n;
wire h_valid, v_valid;
always @ (negedge clk, posedge rst) begin
if (rst) begin
h_cnt <= 0;
v_cnt <= 0;
end
else begin
if (h_cnt == hori_line - 1) begin
h_cnt <= 0;
if (v_cnt == vert_line - 1)
v_cnt <= 0;
else
v_cnt <= v_cnt + 1;
end
else
h_cnt <= h_cnt + 1;
end
end
assign c_hd = (h_cnt < H_sync_cycle) ? 0 : 1;
assign c_vd = (v_cnt < V_sync_cycle) ? 0 : 1;
assign h_valid = (h_cnt < (hori_line-hori_front) && h_cnt >= hori_back) ? 1 : 0;
assign v_valid = (v_cnt < (vert_line-vert_front) && v_cnt >= vert_back) ? 1 : 0;
assign c_blank_n = h_valid && v_valid;
always @ (negedge clk) begin
hs <= c_hd;
vs <= c_vd;
blank_n <= c_blank_n;
end
endmodule | 0 |
2,797 | data/full_repos/permissive/101171422/sim/counter.v | 101,171,422 | counter.v | v | 39 | 26 | [] | [] | [] | null | line:25: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301 | module | module counter
(
input clock,
input reset,
output reg [3:0] count
);
always @(posedge clock)
begin
if (reset == 1'b1)
count <= #1 4'b0000;
else
count <= #1 count + 1;
end
endmodule | module counter
(
input clock,
input reset,
output reg [3:0] count
); |
always @(posedge clock)
begin
if (reset == 1'b1)
count <= #1 4'b0000;
else
count <= #1 count + 1;
end
endmodule | 0 |
2,798 | data/full_repos/permissive/101171422/sim/counter.v | 101,171,422 | counter.v | v | 39 | 26 | [] | [] | [] | null | line:25: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301 | module | module test_counter();
reg clock, reset;
wire [3:0] count;
initial begin
clock = 1;
reset = 1;
#5 reset = 0;
#1000 $finish;
end
always begin
#5 clock = ~clock;
end
counter cnt(
clock,
reset,
count
);
endmodule | module test_counter(); |
reg clock, reset;
wire [3:0] count;
initial begin
clock = 1;
reset = 1;
#5 reset = 0;
#1000 $finish;
end
always begin
#5 clock = ~clock;
end
counter cnt(
clock,
reset,
count
);
endmodule | 0 |
2,799 | data/full_repos/permissive/101171422/sim/edge_wait.v | 101,171,422 | edge_wait.v | v | 44 | 58 | [] | [] | [] | null | line:12: before: "(" | null | 1: b'%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:13: syntax error, unexpected \'@\'\n @ (posedge G.clock);\n ^\n%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:24: Unsupported or unknown PLI call: $monitor\n $monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 G.enable = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n #15 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n #25 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n #30 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n #35 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1 G.clock = ~G.clock;\n ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n' | 302 | module | module G();
reg enable, clock;
endmodule | module G(); |
reg enable, clock;
endmodule | 0 |
2,800 | data/full_repos/permissive/101171422/sim/edge_wait.v | 101,171,422 | edge_wait.v | v | 44 | 58 | [] | [] | [] | null | line:12: before: "(" | null | 1: b'%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:13: syntax error, unexpected \'@\'\n @ (posedge G.clock);\n ^\n%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:24: Unsupported or unknown PLI call: $monitor\n $monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 G.enable = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n #15 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n #25 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n #30 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n #35 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1 G.clock = ~G.clock;\n ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n' | 302 | module | module edge_wait
(
output reg [1:0] trigger
);
always @ (posedge G.enable)
begin
trigger <= 0;
repeat (2) begin
@ (posedge G.clock);
end
trigger <= 1;
end
endmodule | module edge_wait
(
output reg [1:0] trigger
); |
always @ (posedge G.enable)
begin
trigger <= 0;
repeat (2) begin
@ (posedge G.clock);
end
trigger <= 1;
end
endmodule | 0 |
2,801 | data/full_repos/permissive/101171422/sim/edge_wait.v | 101,171,422 | edge_wait.v | v | 44 | 58 | [] | [] | [] | null | line:12: before: "(" | null | 1: b'%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:13: syntax error, unexpected \'@\'\n @ (posedge G.clock);\n ^\n%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:24: Unsupported or unknown PLI call: $monitor\n $monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 G.enable = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n #15 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n #25 G.enable = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n #30 G.enable = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n #35 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1 G.clock = ~G.clock;\n ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n' | 302 | module | module edge_wait_test();
wire [1:0] trigger;
initial begin
$monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",
$time, G.clock, G.enable, trigger);
G.clock = 0;
G.enable = 0;
#5 G.enable = 1;
#10 G.enable = 0;
#15 G.enable = 1;
#20 G.enable = 0;
#25 G.enable = 1;
#30 G.enable = 0;
#35 $finish;
end
always begin
#1 G.clock = ~G.clock;
end
edge_wait ew(trigger);
endmodule | module edge_wait_test(); |
wire [1:0] trigger;
initial begin
$monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",
$time, G.clock, G.enable, trigger);
G.clock = 0;
G.enable = 0;
#5 G.enable = 1;
#10 G.enable = 0;
#15 G.enable = 1;
#20 G.enable = 0;
#25 G.enable = 1;
#30 G.enable = 0;
#35 $finish;
end
always begin
#1 G.clock = ~G.clock;
end
edge_wait ew(trigger);
endmodule | 0 |
2,802 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | module | module gates
(
output wire o_and,
output wire o_nand,
output wire o_or,
output wire o_nor,
output wire o_xor,
output wire o_xnor,
output wire o_not1,
output wire o_not2,
output wire o_dff,
output wire o_one,
output wire o_zero,
output wire o_cp_and,
output wire o_cp_or,
output wire o_cp_xor
);
function f_nand
(
input x,
input y
);
f_nand = ~(x & y);
endfunction
function f_not
(
input x
);
f_not = f_nand(x, x);
endfunction
function f_and
(
input x,
input y
);
f_and = f_not(f_nand(x, y));
endfunction
function f_or
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_nand(x, x);
r2 = f_nand(y, y);
f_or = f_not(f_and(r1, r2));
end
endfunction
function f_nor
(
input x,
input y
);
f_nor = f_not(f_or(x, y));
endfunction
function f_xor
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_and(x, f_not(y));
r2 = f_and(f_not(x), y);
f_xor = f_or(r1, r2);
end
endfunction
function f_xnor
(
input x,
input y
);
f_xnor = f_not(f_xor(x, y));
endfunction
function f_dff
(
input d,
input clk
);
reg Q, Q_BAR;
reg X, Y;
begin
X = ~(d & clk);
Y = ~(X & clk);
Q = ~(Q_BAR & X);
Q_BAR = ~(Q & Y);
f_dff = Q;
end
endfunction
reg x, y;
initial begin
x = 0;
y = 0;
#5 x = 0;
y = 1;
#5 x = 1;
y = 0;
#5 x = 1;
y = 1;
#5 $finish;
end
assign o_cp_and = o_and;
assign o_cp_or = o_or;
assign o_cp_xor = o_xor;
assign o_nand = f_nand(x, y);
assign o_and = f_and(x, y);
assign o_nor = f_nor(x, y);
assign o_or = f_or(x, y);
assign o_xnor = f_xnor(x, y);
assign o_xor = f_xor(x, y);
assign o_not1 = f_not(x);
assign o_not2 = f_not(y);
assign o_dff = f_dff(x, y);
assign o_one = 1;
assign o_zero = 0;
endmodule | module gates
(
output wire o_and,
output wire o_nand,
output wire o_or,
output wire o_nor,
output wire o_xor,
output wire o_xnor,
output wire o_not1,
output wire o_not2,
output wire o_dff,
output wire o_one,
output wire o_zero,
output wire o_cp_and,
output wire o_cp_or,
output wire o_cp_xor
); |
function f_nand
(
input x,
input y
);
f_nand = ~(x & y);
endfunction
function f_not
(
input x
);
f_not = f_nand(x, x);
endfunction
function f_and
(
input x,
input y
);
f_and = f_not(f_nand(x, y));
endfunction
function f_or
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_nand(x, x);
r2 = f_nand(y, y);
f_or = f_not(f_and(r1, r2));
end
endfunction
function f_nor
(
input x,
input y
);
f_nor = f_not(f_or(x, y));
endfunction
function f_xor
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_and(x, f_not(y));
r2 = f_and(f_not(x), y);
f_xor = f_or(r1, r2);
end
endfunction
function f_xnor
(
input x,
input y
);
f_xnor = f_not(f_xor(x, y));
endfunction
function f_dff
(
input d,
input clk
);
reg Q, Q_BAR;
reg X, Y;
begin
X = ~(d & clk);
Y = ~(X & clk);
Q = ~(Q_BAR & X);
Q_BAR = ~(Q & Y);
f_dff = Q;
end
endfunction
reg x, y;
initial begin
x = 0;
y = 0;
#5 x = 0;
y = 1;
#5 x = 1;
y = 0;
#5 x = 1;
y = 1;
#5 $finish;
end
assign o_cp_and = o_and;
assign o_cp_or = o_or;
assign o_cp_xor = o_xor;
assign o_nand = f_nand(x, y);
assign o_and = f_and(x, y);
assign o_nor = f_nor(x, y);
assign o_or = f_or(x, y);
assign o_xnor = f_xnor(x, y);
assign o_xor = f_xor(x, y);
assign o_not1 = f_not(x);
assign o_not2 = f_not(y);
assign o_dff = f_dff(x, y);
assign o_one = 1;
assign o_zero = 0;
endmodule | 0 |
2,803 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_nand
(
input x,
input y
);
f_nand = ~(x & y);
endfunction | function f_nand
(
input x,
input y
); |
f_nand = ~(x & y);
endfunction | 0 |
2,804 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_not
(
input x
);
f_not = f_nand(x, x);
endfunction | function f_not
(
input x
); |
f_not = f_nand(x, x);
endfunction | 0 |
2,805 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_and
(
input x,
input y
);
f_and = f_not(f_nand(x, y));
endfunction | function f_and
(
input x,
input y
); |
f_and = f_not(f_nand(x, y));
endfunction | 0 |
2,806 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_or
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_nand(x, x);
r2 = f_nand(y, y);
f_or = f_not(f_and(r1, r2));
end
endfunction | function f_or
(
input x,
input y
); |
reg r1, r2;
begin
r1 = f_nand(x, x);
r2 = f_nand(y, y);
f_or = f_not(f_and(r1, r2));
end
endfunction | 0 |
2,807 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_nor
(
input x,
input y
);
f_nor = f_not(f_or(x, y));
endfunction | function f_nor
(
input x,
input y
); |
f_nor = f_not(f_or(x, y));
endfunction | 0 |
2,808 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_xor
(
input x,
input y
);
reg r1, r2;
begin
r1 = f_and(x, f_not(y));
r2 = f_and(f_not(x), y);
f_xor = f_or(r1, r2);
end
endfunction | function f_xor
(
input x,
input y
); |
reg r1, r2;
begin
r1 = f_and(x, f_not(y));
r2 = f_and(f_not(x), y);
f_xor = f_or(r1, r2);
end
endfunction | 0 |
2,809 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_xnor
(
input x,
input y
);
f_xnor = f_not(f_xor(x, y));
endfunction | function f_xnor
(
input x,
input y
); |
f_xnor = f_not(f_xor(x, y));
endfunction | 0 |
2,810 | data/full_repos/permissive/101171422/sim/gates.v | 101,171,422 | gates.v | v | 134 | 32 | [] | [] | [] | null | line:19: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n #5 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 303 | function | function f_dff
(
input d,
input clk
);
reg Q, Q_BAR;
reg X, Y;
begin
X = ~(d & clk);
Y = ~(X & clk);
Q = ~(Q_BAR & X);
Q_BAR = ~(Q & Y);
f_dff = Q;
end
endfunction | function f_dff
(
input d,
input clk
); |
reg Q, Q_BAR;
reg X, Y;
begin
X = ~(d & clk);
Y = ~(X & clk);
Q = ~(Q_BAR & X);
Q_BAR = ~(Q & Y);
f_dff = Q;
end
endfunction | 0 |
2,811 | data/full_repos/permissive/101171422/sim/hello_world.v | 101,171,422 | hello_world.v | v | 27 | 28 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:7: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304 | module | module hello_world
(
input clock
);
initial begin
$display("Hello World!");
#100 $finish;
end
endmodule | module hello_world
(
input clock
); |
initial begin
$display("Hello World!");
#100 $finish;
end
endmodule | 0 |
2,812 | data/full_repos/permissive/101171422/sim/hello_world.v | 101,171,422 | hello_world.v | v | 27 | 28 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:7: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = ~clock;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304 | module | module test_hello_world();
reg clock;
initial begin
clock = 1;
end
always begin
#5 clock = ~clock;
end
hello_world test_hello(
clock
);
endmodule | module test_hello_world(); |
reg clock;
initial begin
clock = 1;
end
always begin
#5 clock = ~clock;
end
hello_world test_hello(
clock
);
endmodule | 0 |
2,813 | data/full_repos/permissive/101171422/sim/level_wait.v | 101,171,422 | level_wait.v | v | 43 | 66 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:19: Unsupported: Ignoring delay on this delayed statement.\n wait (data_ready == 1) #1 data = data_bus;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/sim/level_wait.v:19: Unsupported: wait statements\n wait (data_ready == 1) #1 data = data_bus;\n ^~~~\n%Error: data/full_repos/permissive/101171422/sim/level_wait.v:23: Unsupported or unknown PLI call: $monitor\n $monitor("TIME = %g READ = %b READY = %b DATA = %b", \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 data_bus = 8\'hDE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10 mem_read = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20 data_ready = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 mem_read = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1 data_ready = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 data_bus = 8\'hAD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 mem_read = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20 data_ready = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 mem_read = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:37: Unsupported: Ignoring delay on this delayed statement.\n #1 data_ready = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 305 | module | module level_wait
(
output reg [7:0] data
);
reg mem_read, data_ready;
reg [7:0] data_bus;
always @ (mem_read or data_bus or data_ready)
begin
data = 0;
wait (data_ready == 1) #1 data = data_bus;
end
initial begin
$monitor("TIME = %g READ = %b READY = %b DATA = %b",
$time, mem_read, data_ready, data);
data_bus = 0;
mem_read = 0;
data_ready = 0;
#10 data_bus = 8'hDE;
#10 mem_read = 1;
#20 data_ready = 1;
#1 mem_read = 1;
#1 data_ready = 0;
#10 data_bus = 8'hAD;
#10 mem_read = 1;
#20 data_ready = 1;
#1 mem_read = 1;
#1 data_ready = 0;
#10 $finish;
end
endmodule | module level_wait
(
output reg [7:0] data
); |
reg mem_read, data_ready;
reg [7:0] data_bus;
always @ (mem_read or data_bus or data_ready)
begin
data = 0;
wait (data_ready == 1) #1 data = data_bus;
end
initial begin
$monitor("TIME = %g READ = %b READY = %b DATA = %b",
$time, mem_read, data_ready, data);
data_bus = 0;
mem_read = 0;
data_ready = 0;
#10 data_bus = 8'hDE;
#10 mem_read = 1;
#20 data_ready = 1;
#1 mem_read = 1;
#1 data_ready = 0;
#10 data_bus = 8'hAD;
#10 mem_read = 1;
#20 data_ready = 1;
#1 mem_read = 1;
#1 data_ready = 0;
#10 $finish;
end
endmodule | 0 |
2,814 | data/full_repos/permissive/101171422/sim/trainsim.v | 101,171,422 | trainsim.v | v | 177 | 64 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:165: Unsupported: Ignoring delay on this delayed statement.\n #5 rst = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:169: Unsupported: Ignoring delay on this delayed statement.\n initial forever #0.5 clk = !clk;\n ^\n%Warning-INFINITELOOP: data/full_repos/permissive/101171422/sim/trainsim.v:169: Infinite loop (condition always true)\n : ... In instance trainsim_test\n initial forever #0.5 clk = !clk;\n ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 306 | module | module trainsim
(
input wire rst,
input wire clk,
input wire [4:0] sensor,
output reg [2:0] sw,
output reg [1:0] dira,
output reg [1:0] dirb
);
localparam ABOUT = 0;
localparam AIN = 1;
localparam BIN = 2;
localparam ASTOP = 3;
localparam BSTOP = 4;
reg [2:0] state;
wire [1:0] s12 = {sensor[0], sensor[1]};
wire [1:0] s13 = {sensor[0], sensor[2]};
wire [1:0] s24 = {sensor[1], sensor[3]};
always @ (posedge clk) begin
sw[2] = 0;
end
always @ (posedge clk or posedge rst) begin
if (rst)
state = ABOUT;
else
case (state)
ABOUT:
case (s12)
'b00: state = ABOUT;
'b01: state = BIN;
'b10: state = AIN;
'b11: state = AIN;
default: state = ABOUT;
endcase
AIN:
case (s24)
'b00: state = AIN;
'b01: state = ABOUT;
'b10: state = BSTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
BIN:
case (s13)
'b00: state = BIN;
'b01: state = ABOUT;
'b10: state = ASTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
ASTOP:
if (sensor[2])
state = AIN;
else
state = ASTOP;
BSTOP:
if (sensor[3])
state = BIN;
else
state = BSTOP;
default:
state = ABOUT;
endcase
end
always @ (state) begin
case (state)
ABOUT: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
AIN: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
BIN: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b01;
dirb = 'b01;
end
ASTOP: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b00;
dirb = 'b01;
end
BSTOP: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b00;
end
default: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b00;
dirb = 'b00;
end
endcase
end
endmodule | module trainsim
(
input wire rst,
input wire clk,
input wire [4:0] sensor,
output reg [2:0] sw,
output reg [1:0] dira,
output reg [1:0] dirb
); |
localparam ABOUT = 0;
localparam AIN = 1;
localparam BIN = 2;
localparam ASTOP = 3;
localparam BSTOP = 4;
reg [2:0] state;
wire [1:0] s12 = {sensor[0], sensor[1]};
wire [1:0] s13 = {sensor[0], sensor[2]};
wire [1:0] s24 = {sensor[1], sensor[3]};
always @ (posedge clk) begin
sw[2] = 0;
end
always @ (posedge clk or posedge rst) begin
if (rst)
state = ABOUT;
else
case (state)
ABOUT:
case (s12)
'b00: state = ABOUT;
'b01: state = BIN;
'b10: state = AIN;
'b11: state = AIN;
default: state = ABOUT;
endcase
AIN:
case (s24)
'b00: state = AIN;
'b01: state = ABOUT;
'b10: state = BSTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
BIN:
case (s13)
'b00: state = BIN;
'b01: state = ABOUT;
'b10: state = ASTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
ASTOP:
if (sensor[2])
state = AIN;
else
state = ASTOP;
BSTOP:
if (sensor[3])
state = BIN;
else
state = BSTOP;
default:
state = ABOUT;
endcase
end
always @ (state) begin
case (state)
ABOUT: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
AIN: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
BIN: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b01;
dirb = 'b01;
end
ASTOP: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b00;
dirb = 'b01;
end
BSTOP: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b00;
end
default: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b00;
dirb = 'b00;
end
endcase
end
endmodule | 0 |
2,815 | data/full_repos/permissive/101171422/sim/trainsim.v | 101,171,422 | trainsim.v | v | 177 | 64 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:165: Unsupported: Ignoring delay on this delayed statement.\n #5 rst = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:169: Unsupported: Ignoring delay on this delayed statement.\n initial forever #0.5 clk = !clk;\n ^\n%Warning-INFINITELOOP: data/full_repos/permissive/101171422/sim/trainsim.v:169: Infinite loop (condition always true)\n : ... In instance trainsim_test\n initial forever #0.5 clk = !clk;\n ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 306 | module | module LFSR8_11D
(
input wire clk,
output reg [7:0] LFSR = 255
);
wire feedback = LFSR[7] ^ (LFSR[6:0] == 7'b0000000);
always @(posedge clk) begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1] ^ feedback;
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3] ^ feedback;
LFSR[5] <= LFSR[4];
LFSR[6] <= LFSR[5];
LFSR[7] <= LFSR[6];
end
endmodule | module LFSR8_11D
(
input wire clk,
output reg [7:0] LFSR = 255
); |
wire feedback = LFSR[7] ^ (LFSR[6:0] == 7'b0000000);
always @(posedge clk) begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1] ^ feedback;
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3] ^ feedback;
LFSR[5] <= LFSR[4];
LFSR[6] <= LFSR[5];
LFSR[7] <= LFSR[6];
end
endmodule | 0 |
2,816 | data/full_repos/permissive/101171422/sim/trainsim.v | 101,171,422 | trainsim.v | v | 177 | 64 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:165: Unsupported: Ignoring delay on this delayed statement.\n #5 rst = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:166: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:169: Unsupported: Ignoring delay on this delayed statement.\n initial forever #0.5 clk = !clk;\n ^\n%Warning-INFINITELOOP: data/full_repos/permissive/101171422/sim/trainsim.v:169: Infinite loop (condition always true)\n : ... In instance trainsim_test\n initial forever #0.5 clk = !clk;\n ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 306 | module | module trainsim_test();
reg rst, clk;
wire [7:0] rnd;
wire [4:0] sensor;
wire [2:0] sw;
wire [1:0] dira, dirb;
initial begin
clk = 0;
#5 rst = 1;
#1 rst = 0;
end
initial forever #0.5 clk = !clk;
assign sensor = rnd[4:0];
LFSR8_11D l(clk, rnd);
trainsim t(rst, clk, sensor, sw, dira, dirb);
endmodule | module trainsim_test(); |
reg rst, clk;
wire [7:0] rnd;
wire [4:0] sensor;
wire [2:0] sw;
wire [1:0] dira, dirb;
initial begin
clk = 0;
#5 rst = 1;
#1 rst = 0;
end
initial forever #0.5 clk = !clk;
assign sensor = rnd[4:0];
LFSR8_11D l(clk, rnd);
trainsim t(rst, clk, sensor, sw, dira, dirb);
endmodule | 0 |
2,817 | data/full_repos/permissive/101171422/zcu104/sim/cordic/testbench.v | 101,171,422 | testbench.v | v | 36 | 34 | [] | [] | [] | [(3, 35)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/zcu104/sim/cordic/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/zcu104/sim/cordic/testbench.v:29: Cannot find file containing module: \'cordic_0\'\n cordic_0 sqrt(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101171422/zcu104/sim/cordic,data/full_repos/permissive/101171422/cordic_0\n data/full_repos/permissive/101171422/zcu104/sim/cordic,data/full_repos/permissive/101171422/cordic_0.v\n data/full_repos/permissive/101171422/zcu104/sim/cordic,data/full_repos/permissive/101171422/cordic_0.sv\n cordic_0\n cordic_0.v\n cordic_0.sv\n obj_dir/cordic_0\n obj_dir/cordic_0.v\n obj_dir/cordic_0.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307 | module | module testbench;
reg clk;
reg rst;
reg [31:0] x;
wire [31:0] y;
wire valid;
initial begin
clk = 0;
forever clk = #1 ~clk;
end
initial begin
rst = 1;
#100 rst = 0;
end
always @(posedge clk)
begin
if (rst == 1)
x <= 0;
else
x <= x + 1;
end
cordic_0 sqrt(
.s_axis_cartesian_tdata(x),
.s_axis_cartesian_tvalid(~rst),
.m_axis_dout_tdata(y),
.m_axis_dout_tvalid(valid)
);
endmodule | module testbench; |
reg clk;
reg rst;
reg [31:0] x;
wire [31:0] y;
wire valid;
initial begin
clk = 0;
forever clk = #1 ~clk;
end
initial begin
rst = 1;
#100 rst = 0;
end
always @(posedge clk)
begin
if (rst == 1)
x <= 0;
else
x <= x + 1;
end
cordic_0 sqrt(
.s_axis_cartesian_tdata(x),
.s_axis_cartesian_tvalid(~rst),
.m_axis_dout_tdata(y),
.m_axis_dout_tvalid(valid)
);
endmodule | 0 |
2,819 | data/full_repos/permissive/101237473/lab8/Source Code/clk_500_Hz.v | 101,237,473 | clk_500_Hz.v | v | 59 | 81 | [] | [] | [] | [(26, 56)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/clk_500_Hz.v\n%Error: Exiting due to 3 error(s)\n' | 312 | module | module clk_500_Hz( clk_in, reset, clk_out );
input clk_in, reset;
output clk_out;
reg clk_out;
integer i;
always@ (posedge clk_in or posedge reset) begin
if (reset == 1'b1) begin
i = 0;
clk_out = 0;
end
else begin
i = i+1;
if (i >= ((100000000/500)/2)) begin
clk_out = ~clk_out;
i=0;
end
end
end
endmodule | module clk_500_Hz( clk_in, reset, clk_out ); |
input clk_in, reset;
output clk_out;
reg clk_out;
integer i;
always@ (posedge clk_in or posedge reset) begin
if (reset == 1'b1) begin
i = 0;
clk_out = 0;
end
else begin
i = i+1;
if (i >= ((100000000/500)/2)) begin
clk_out = ~clk_out;
i=0;
end
end
end
endmodule | 10 |
2,826 | data/full_repos/permissive/101237473/lab8/Source Code/led_clk.v | 101,237,473 | led_clk.v | v | 54 | 79 | [] | [] | [] | [(25, 51)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/led_clk.v\n%Error: Exiting due to 3 error(s)\n' | 322 | module | module led_clk( clk_in, reset, clk_out );
input clk_in, reset;
output reg clk_out;
integer i;
always @( posedge clk_in or posedge reset) begin
if ( reset == 1 ) begin
clk_out = 0;
i = 0;
end else begin
i = i+1;
if ( i >= ((100000000/480)/2)) begin
clk_out = ~clk_out;
i = 0;
end
end
end
endmodule | module led_clk( clk_in, reset, clk_out ); |
input clk_in, reset;
output reg clk_out;
integer i;
always @( posedge clk_in or posedge reset) begin
if ( reset == 1 ) begin
clk_out = 0;
i = 0;
end else begin
i = i+1;
if ( i >= ((100000000/480)/2)) begin
clk_out = ~clk_out;
i = 0;
end
end
end
endmodule | 10 |
2,827 | data/full_repos/permissive/101237473/lab8/Source Code/led_controller.v | 101,237,473 | led_controller.v | v | 86 | 79 | [] | [] | [] | [(26, 82)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/led_controller.v\n%Error: Exiting due to 3 error(s)\n' | 323 | module | module led_controller( clk, reset, an, seg_sel );
input clk, reset;
output reg [7:0] an;
output reg [2:0] seg_sel;
reg [2:0] present_state;
reg [2:0] next_state;
always @(present_state)
begin
case (present_state)
3'b000 : next_state = 3'b001;
3'b001 : next_state = 3'b010;
3'b010 : next_state = 3'b011;
3'b011 : next_state = 3'b100;
3'b100 : next_state = 3'b101;
3'b101 : next_state = 3'b110;
3'b110 : next_state = 3'b111;
3'b111 : next_state = 3'b000;
default : next_state = 3'b000;
endcase
end
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
present_state = 3'b000;
else
present_state = next_state;
end
always @(present_state)
begin
case (present_state)
3'b000 : {seg_sel, an} = 11'b000_11111110;
3'b001 : {seg_sel, an} = 11'b001_11111101;
3'b010 : {seg_sel, an} = 11'b010_11111011;
3'b011 : {seg_sel, an} = 11'b011_11110111;
3'b100 : {seg_sel, an} = 11'b100_11101111;
3'b101 : {seg_sel, an} = 11'b101_11011111;
3'b110 : {seg_sel, an} = 11'b110_10111111;
3'b111 : {seg_sel, an} = 11'b111_01111111;
default : {seg_sel, an} = 11'b000_11111110;
endcase
end
endmodule | module led_controller( clk, reset, an, seg_sel ); |
input clk, reset;
output reg [7:0] an;
output reg [2:0] seg_sel;
reg [2:0] present_state;
reg [2:0] next_state;
always @(present_state)
begin
case (present_state)
3'b000 : next_state = 3'b001;
3'b001 : next_state = 3'b010;
3'b010 : next_state = 3'b011;
3'b011 : next_state = 3'b100;
3'b100 : next_state = 3'b101;
3'b101 : next_state = 3'b110;
3'b110 : next_state = 3'b111;
3'b111 : next_state = 3'b000;
default : next_state = 3'b000;
endcase
end
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
present_state = 3'b000;
else
present_state = next_state;
end
always @(present_state)
begin
case (present_state)
3'b000 : {seg_sel, an} = 11'b000_11111110;
3'b001 : {seg_sel, an} = 11'b001_11111101;
3'b010 : {seg_sel, an} = 11'b010_11111011;
3'b011 : {seg_sel, an} = 11'b011_11110111;
3'b100 : {seg_sel, an} = 11'b100_11101111;
3'b101 : {seg_sel, an} = 11'b101_11011111;
3'b110 : {seg_sel, an} = 11'b110_10111111;
3'b111 : {seg_sel, an} = 11'b111_01111111;
default : {seg_sel, an} = 11'b000_11111110;
endcase
end
endmodule | 10 |
2,831 | data/full_repos/permissive/101237473/lab8/Source Code/ram1.v | 101,237,473 | ram1.v | v | 38 | 80 | [] | [] | [] | [(19, 36)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/ram1.v\n%Error: Exiting due to 3 error(s)\n' | 327 | module | module ram1( clk , we, addr, din, dout );
input clk, we;
input [15:0] addr;
input [15:0] din;
output [15:0] dout;
ram_256x16 ram (
.clka(clk),
.wea(we),
.addra(addr),
.dina(din),
.douta(dout)
);
endmodule | module ram1( clk , we, addr, din, dout ); |
input clk, we;
input [15:0] addr;
input [15:0] din;
output [15:0] dout;
ram_256x16 ram (
.clka(clk),
.wea(we),
.addra(addr),
.dina(din),
.douta(dout)
);
endmodule | 10 |
2,832 | data/full_repos/permissive/101237473/lab8/Source Code/reg16.v | 101,237,473 | reg16.v | v | 48 | 79 | [] | [] | [] | [(26, 46)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/reg16.v\n%Error: Exiting due to 3 error(s)\n' | 328 | module | module reg16( clk, reset, ld, Din, DA, DB, oeA, oeB );
input clk, reset, ld, oeA, oeB;
input [15:0] Din;
output [15:0] DA, DB;
reg [15:0] Dout;
always @ ( posedge clk or posedge reset )
if (reset)
Dout <= 16'b0;
else
if (ld)
Dout <= Din;
else Dout <= Dout;
assign DA = oeA ? Dout : 16'hz;
assign DB = oeB ? Dout : 16'hz;
endmodule | module reg16( clk, reset, ld, Din, DA, DB, oeA, oeB ); |
input clk, reset, ld, oeA, oeB;
input [15:0] Din;
output [15:0] DA, DB;
reg [15:0] Dout;
always @ ( posedge clk or posedge reset )
if (reset)
Dout <= 16'b0;
else
if (ld)
Dout <= Din;
else Dout <= Dout;
assign DA = oeA ? Dout : 16'hz;
assign DB = oeB ? Dout : 16'hz;
endmodule | 10 |
2,834 | data/full_repos/permissive/101237473/lab8/Source Code/RISC_Processor.v | 101,237,473 | RISC_Processor.v | v | 61 | 86 | [] | [] | [] | [(27, 60)] | null | null | 1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n ... Looked in:\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n Code,data/full_repos/permissive/101237473\n Code,data/full_repos/permissive/101237473.v\n Code,data/full_repos/permissive/101237473.sv\n obj_dir/Code,data/full_repos/permissive/101237473\n obj_dir/Code,data/full_repos/permissive/101237473.v\n obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/RISC_Processor.v\n%Error: Exiting due to 3 error(s)\n' | 330 | module | module RISC_Processor(clk, reset, D_out, Address, D_in, mw_en, status);
input clk, reset;
input [15:0] D_in;
output [15:0] D_out, Address;
output [7:0] status;
output mw_en;
wire [15:0] ir_out;
wire N, Z, C;
wire [2:0] W_Adr, R_Adr, S_Adr;
wire adr_sel, s_sel;
wire pc_ld, pc_inc, pc_sel, ir_ld;
wire rw_en;
wire [3:0] Alu_Op;
cu u0 ( .clk(clk), .reset(reset), .IR(ir_out), .N(N), .Z(Z), .C(C),
.W_Adr(W_Adr), .R_Adr(R_Adr), .S_Adr(S_Adr),
.adr_sel(adr_sel), .s_sel(s_sel),
.pc_ld(pc_ld), .pc_inc(pc_inc), .pc_sel(pc_sel), .ir_ld(ir_ld),
.mw_en(mw_en), .rw_en(rw_en), .alu_op(Alu_Op), .status(status));
CPU_EU u1 ( .clk(clk), .reset(reset),
.pc_ld(pc_ld), .pc_sel(pc_sel), .pc_inc(pc_inc), .ir_ld(ir_ld),
.adr_sel(adr_sel), .W_En(rw_en), .S_Sel(s_sel),
.address(Address), .D_out(D_out), .D_in(D_in), .C(C), .N(N), .Z(Z),
.W_Adr(W_Adr), .R_Adr(R_Adr), .S_Adr(S_Adr), .Alu_Op(Alu_Op), .ir_out(ir_out));
endmodule | module RISC_Processor(clk, reset, D_out, Address, D_in, mw_en, status); |
input clk, reset;
input [15:0] D_in;
output [15:0] D_out, Address;
output [7:0] status;
output mw_en;
wire [15:0] ir_out;
wire N, Z, C;
wire [2:0] W_Adr, R_Adr, S_Adr;
wire adr_sel, s_sel;
wire pc_ld, pc_inc, pc_sel, ir_ld;
wire rw_en;
wire [3:0] Alu_Op;
cu u0 ( .clk(clk), .reset(reset), .IR(ir_out), .N(N), .Z(Z), .C(C),
.W_Adr(W_Adr), .R_Adr(R_Adr), .S_Adr(S_Adr),
.adr_sel(adr_sel), .s_sel(s_sel),
.pc_ld(pc_ld), .pc_inc(pc_inc), .pc_sel(pc_sel), .ir_ld(ir_ld),
.mw_en(mw_en), .rw_en(rw_en), .alu_op(Alu_Op), .status(status));
CPU_EU u1 ( .clk(clk), .reset(reset),
.pc_ld(pc_ld), .pc_sel(pc_sel), .pc_inc(pc_inc), .ir_ld(ir_ld),
.adr_sel(adr_sel), .W_En(rw_en), .S_Sel(s_sel),
.address(Address), .D_out(D_out), .D_in(D_in), .C(C), .N(N), .Z(Z),
.W_Adr(W_Adr), .R_Adr(R_Adr), .S_Adr(S_Adr), .Alu_Op(Alu_Op), .ir_out(ir_out));
endmodule | 10 |
2,835 | data/full_repos/permissive/10136357/hardware/src/alu.v | 10,136,357 | alu.v | v | 58 | 84 | [] | [] | [] | [(177, 205)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:37: Define or directive not defined: \'`ALU_ADD\'\n `ALU_ADD: alu_out = op1 + op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:37: syntax error, unexpected \':\', expecting endcase\n `ALU_ADD: alu_out = op1 + op2;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:38: Define or directive not defined: \'`ALU_SLL\'\n `ALU_SLL: alu_out = op1 << op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:39: Define or directive not defined: \'`ALU_SLT\'\n `ALU_SLT: alu_out = $signed(op1) < $signed(op2) ? 1 : 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:40: Define or directive not defined: \'`ALU_SLTU\'\n `ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:41: Define or directive not defined: \'`ALU_XOR\'\n `ALU_XOR: alu_out = op1 ^ op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:42: Define or directive not defined: \'`ALU_SRL\'\n `ALU_SRL: alu_out = op1 >> op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:43: Define or directive not defined: \'`ALU_SRA\'\n `ALU_SRA: alu_out = $signed(op1) >>> op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:44: Define or directive not defined: \'`ALU_OR\'\n `ALU_OR: alu_out = op1 | op2;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:45: Define or directive not defined: \'`ALU_AND\'\n `ALU_AND: alu_out = op1 & op2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:46: Define or directive not defined: \'`ALU_MUL\'\n `ALU_MUL: alu_out = multiplier_result;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:47: Define or directive not defined: \'`ALU_DIV\'\n `ALU_DIV: alu_out = $signed(op1) / $signed(op2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:48: Define or directive not defined: \'`ALU_DIVU\'\n `ALU_DIVU: alu_out = op1 / op2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:49: Define or directive not defined: \'`ALU_REM\'\n `ALU_REM: alu_out = $signed(op1) % $signed(op2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:50: Define or directive not defined: \'`ALU_REMU\'\n `ALU_REMU: alu_out = op1 % op2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:51: Define or directive not defined: \'`ALU_LUI\'\n `ALU_LUI: alu_out = op1 << 12;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:52: Define or directive not defined: \'`ALU_NONE\'\n `ALU_NONE: alu_out = 0;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 331 | module | module alu (
output reg [31:0] alu_out,
input [31:0] op1,
input [31:0] op2,
input [31:0] multiplier_result,
input [4:0] alu_sel
);
always @ (*) begin
case (alu_sel)
`ALU_ADD: alu_out = op1 + op2;
`ALU_SLL: alu_out = op1 << op2;
`ALU_SLT: alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
`ALU_XOR: alu_out = op1 ^ op2;
`ALU_SRL: alu_out = op1 >> op2;
`ALU_SRA: alu_out = $signed(op1) >>> op2;
`ALU_OR: alu_out = op1 | op2;
`ALU_AND: alu_out = op1 & op2;
`ALU_MUL: alu_out = multiplier_result;
`ALU_DIV: alu_out = $signed(op1) / $signed(op2);
`ALU_DIVU: alu_out = op1 / op2;
`ALU_REM: alu_out = $signed(op1) % $signed(op2);
`ALU_REMU: alu_out = op1 % op2;
`ALU_LUI: alu_out = op1 << 12;
`ALU_NONE: alu_out = 0;
endcase
end
endmodule | module alu (
output reg [31:0] alu_out,
input [31:0] op1,
input [31:0] op2,
input [31:0] multiplier_result,
input [4:0] alu_sel
); |
always @ (*) begin
case (alu_sel)
`ALU_ADD: alu_out = op1 + op2;
`ALU_SLL: alu_out = op1 << op2;
`ALU_SLT: alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
`ALU_XOR: alu_out = op1 ^ op2;
`ALU_SRL: alu_out = op1 >> op2;
`ALU_SRA: alu_out = $signed(op1) >>> op2;
`ALU_OR: alu_out = op1 | op2;
`ALU_AND: alu_out = op1 & op2;
`ALU_MUL: alu_out = multiplier_result;
`ALU_DIV: alu_out = $signed(op1) / $signed(op2);
`ALU_DIVU: alu_out = op1 / op2;
`ALU_REM: alu_out = $signed(op1) % $signed(op2);
`ALU_REMU: alu_out = op1 % op2;
`ALU_LUI: alu_out = op1 << 12;
`ALU_NONE: alu_out = 0;
endcase
end
endmodule | 23 |
2,840 | data/full_repos/permissive/10136357/hardware/src/datapath.v | 10,136,357 | datapath.v | v | 186 | 91 | [] | [] | [] | [(177, 334)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:88: Define or directive not defined: \'`PC_START\'\n : ... Suggested alternative: \'`SV_COV_START\'\n pc <= `PC_START;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pc <= `PC_START;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:96: Define or directive not defined: \'`INSTR_NOP\'\n inst <= `INSTR_NOP;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n inst <= `INSTR_NOP;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:170: Define or directive not defined: \'`F3_MTPCR\'\n .pcr_write_data({1\'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1), \n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:170: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n .pcr_write_data({1\'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1), \n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:177: Define or directive not defined: \'`WB_ALU\'\n `WB_ALU: rf_wdata = alu_out;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:177: syntax error, unexpected \':\', expecting endcase\n `WB_ALU: rf_wdata = alu_out;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:178: Define or directive not defined: \'`WB_MEM\'\n `WB_MEM: rf_wdata = mem_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:179: Define or directive not defined: \'`WB_PC4\'\n `WB_PC4: rf_wdata = pc + 4;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/datapath.v:180: Define or directive not defined: \'`WB_PCR\'\n `WB_PCR: rf_wdata = pcr_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 337 | module | module datapath (
input clk,
input reset,
input stall,
output [31:0] fetch_addr,
output fetch_request,
input fetch_data_valid,
output [31:0] dmem_addr,
output [31:0] dmem_write_data,
output [3:0] dmem_write_mask,
output dmem_request,
output dmem_request_type,
input dmem_data_valid,
input [31:0] request_data,
output [31:0] ptbr,
output vm_enable,
output flush_tlb
);
reg [31:0] inst;
reg [31:0] pc;
wire [1:0] next_pc_sel;
wire [2:0] wb_sel;
wire rf_wr_en;
wire interrupt;
wire [31:0] evec;
wire branch_taken;
wire [31:0] branch_target;
wire jump_taken;
wire [31:0] jump_target;
reg [31:0] fetch_pc;
always @ (*) begin
if (stall)
fetch_pc = pc;
else if (interrupt)
fetch_pc = evec;
else if (jump_taken)
fetch_pc = jump_target;
else if (branch_taken)
fetch_pc = branch_target;
else
fetch_pc = pc + 4;
end
assign fetch_addr = fetch_pc;
assign fetch_request = !reset;
always @ (posedge clk) begin
if (reset)
pc <= `PC_START;
else
pc <= fetch_pc;
end
always @ (posedge clk) begin
if (reset)
inst <= `INSTR_NOP;
else if (fetch_data_valid)
inst <= request_data;
end
wire [4:0] ex_rs1;
wire [4:0] ex_rs2;
wire [4:0] ex_wd;
wire cp_enable;
wire [1:0] pcr_cmd;
decode d(.inst(inst),
.rs1(ex_rs1), .rs2(ex_rs2), .wd(ex_wd),
.wb_sel(wb_sel), .rf_wr_en(rf_wr_en),
.memory_request(dmem_request), .memory_request_type(dmem_request_type),
.pcr_enable(cp_enable), .pcr_cmd(pcr_cmd));
wire [31:0] rf_rd1;
wire [31:0] rf_rd2;
reg [31:0] rf_wdata;
regfile rf(.clk(clk), .reset(reset), .rd1(rf_rd1), .rd2(rf_rd2), .rs1(ex_rs1),
.rs2(ex_rs2), .wd(ex_wd), .w_data(rf_wdata), .w_enable(rf_wr_en),
.stall(stall));
wire [4:0] alu_sel;
wire [1:0] mul_sel;
wire [31:0] alu_op1;
wire [31:0] alu_op2;
alu_dec ad(.alu_sel(alu_sel), .mul_sel(mul_sel),
.op1(alu_op1), .op2(alu_op2),
.rs1(rf_rd1), .rs2(rf_rd2), .inst(inst));
wire [31:0] multiplier_result;
wire [31:0] alu_out;
wire alu_equal;
wire alu_less;
multiplier mul(.multiplier_result(multiplier_result),
.op1(alu_op1), .op2(alu_op2), .mul_sel(mul_sel));
alu alu(.alu_out(alu_out),
.op1(alu_op1), .op2(alu_op2), .multiplier_result(multiplier_result), .alu_sel(alu_sel));
branch_jump bj(.branch_taken(branch_taken), .branch_target(branch_target),
.jump(jump_taken), .jump_target(jump_target),
.inst(inst), .pc(pc), .rd1(rf_rd1), .alu_out(alu_out));
wire [31:0] mem_data;
reg [31:0] load_data;
always @ (posedge clk) begin
if (reset)
load_data <= 32'b0;
else if (dmem_data_valid)
load_data <= request_data;
end
data_memory m(.inst(inst), .data(rf_rd2), .addr(alu_out),
.memory_addr(dmem_addr),
.write_data(dmem_write_data), .write_mask(dmem_write_mask),
.load_data(load_data), .output_data(mem_data));
wire [31:0] pcr_data;
control_processor cp(.clk(clk), .reset(reset), .stall(stall),
.inst(inst), .pc(pc),
.enable(cp_enable),
.pcr_write_data({1'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1),
.pcr(ex_rs1), .cmd(pcr_cmd), .pcr_data(pcr_data),
.interrupt(interrupt), .evec(evec),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
always @ (*) begin
case (wb_sel)
`WB_ALU: rf_wdata = alu_out;
`WB_MEM: rf_wdata = mem_data;
`WB_PC4: rf_wdata = pc + 4;
`WB_PCR: rf_wdata = pcr_data;
default: rf_wdata = 32'b0;
endcase
end
endmodule | module datapath (
input clk,
input reset,
input stall,
output [31:0] fetch_addr,
output fetch_request,
input fetch_data_valid,
output [31:0] dmem_addr,
output [31:0] dmem_write_data,
output [3:0] dmem_write_mask,
output dmem_request,
output dmem_request_type,
input dmem_data_valid,
input [31:0] request_data,
output [31:0] ptbr,
output vm_enable,
output flush_tlb
); |
reg [31:0] inst;
reg [31:0] pc;
wire [1:0] next_pc_sel;
wire [2:0] wb_sel;
wire rf_wr_en;
wire interrupt;
wire [31:0] evec;
wire branch_taken;
wire [31:0] branch_target;
wire jump_taken;
wire [31:0] jump_target;
reg [31:0] fetch_pc;
always @ (*) begin
if (stall)
fetch_pc = pc;
else if (interrupt)
fetch_pc = evec;
else if (jump_taken)
fetch_pc = jump_target;
else if (branch_taken)
fetch_pc = branch_target;
else
fetch_pc = pc + 4;
end
assign fetch_addr = fetch_pc;
assign fetch_request = !reset;
always @ (posedge clk) begin
if (reset)
pc <= `PC_START;
else
pc <= fetch_pc;
end
always @ (posedge clk) begin
if (reset)
inst <= `INSTR_NOP;
else if (fetch_data_valid)
inst <= request_data;
end
wire [4:0] ex_rs1;
wire [4:0] ex_rs2;
wire [4:0] ex_wd;
wire cp_enable;
wire [1:0] pcr_cmd;
decode d(.inst(inst),
.rs1(ex_rs1), .rs2(ex_rs2), .wd(ex_wd),
.wb_sel(wb_sel), .rf_wr_en(rf_wr_en),
.memory_request(dmem_request), .memory_request_type(dmem_request_type),
.pcr_enable(cp_enable), .pcr_cmd(pcr_cmd));
wire [31:0] rf_rd1;
wire [31:0] rf_rd2;
reg [31:0] rf_wdata;
regfile rf(.clk(clk), .reset(reset), .rd1(rf_rd1), .rd2(rf_rd2), .rs1(ex_rs1),
.rs2(ex_rs2), .wd(ex_wd), .w_data(rf_wdata), .w_enable(rf_wr_en),
.stall(stall));
wire [4:0] alu_sel;
wire [1:0] mul_sel;
wire [31:0] alu_op1;
wire [31:0] alu_op2;
alu_dec ad(.alu_sel(alu_sel), .mul_sel(mul_sel),
.op1(alu_op1), .op2(alu_op2),
.rs1(rf_rd1), .rs2(rf_rd2), .inst(inst));
wire [31:0] multiplier_result;
wire [31:0] alu_out;
wire alu_equal;
wire alu_less;
multiplier mul(.multiplier_result(multiplier_result),
.op1(alu_op1), .op2(alu_op2), .mul_sel(mul_sel));
alu alu(.alu_out(alu_out),
.op1(alu_op1), .op2(alu_op2), .multiplier_result(multiplier_result), .alu_sel(alu_sel));
branch_jump bj(.branch_taken(branch_taken), .branch_target(branch_target),
.jump(jump_taken), .jump_target(jump_target),
.inst(inst), .pc(pc), .rd1(rf_rd1), .alu_out(alu_out));
wire [31:0] mem_data;
reg [31:0] load_data;
always @ (posedge clk) begin
if (reset)
load_data <= 32'b0;
else if (dmem_data_valid)
load_data <= request_data;
end
data_memory m(.inst(inst), .data(rf_rd2), .addr(alu_out),
.memory_addr(dmem_addr),
.write_data(dmem_write_data), .write_mask(dmem_write_mask),
.load_data(load_data), .output_data(mem_data));
wire [31:0] pcr_data;
control_processor cp(.clk(clk), .reset(reset), .stall(stall),
.inst(inst), .pc(pc),
.enable(cp_enable),
.pcr_write_data({1'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1),
.pcr(ex_rs1), .cmd(pcr_cmd), .pcr_data(pcr_data),
.interrupt(interrupt), .evec(evec),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
always @ (*) begin
case (wb_sel)
`WB_ALU: rf_wdata = alu_out;
`WB_MEM: rf_wdata = mem_data;
`WB_PC4: rf_wdata = pc + 4;
`WB_PCR: rf_wdata = pcr_data;
default: rf_wdata = 32'b0;
endcase
end
endmodule | 23 |
2,841 | data/full_repos/permissive/10136357/hardware/src/data_memory.v | 10,136,357 | data_memory.v | v | 113 | 84 | [] | [] | [] | [(177, 261)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:51: Define or directive not defined: \'`F3_SB\'\n `F3_SB: write_data_masked = data & 32\'hFF;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:51: syntax error, unexpected \':\', expecting endcase\n `F3_SB: write_data_masked = data & 32\'hFF;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:52: Define or directive not defined: \'`F3_SH\'\n `F3_SH: write_data_masked = data & 32\'hFFFF;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:53: Define or directive not defined: \'`F3_SW\'\n `F3_SW: write_data_masked = data & 32\'hFFFFFFFF;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:70: Define or directive not defined: \'`F3_SB\'\n `F3_SB: write_mask = 4\'b1 << addr[1:0];\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:71: Define or directive not defined: \'`F3_SH\'\n `F3_SH: write_mask = 4\'b11 << addr[1:0];\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:72: Define or directive not defined: \'`F3_SW\'\n `F3_SW: write_mask = 4\'b1111;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:81: Define or directive not defined: \'`F3_LB\'\n `F3_LB, `F3_LBU: case (addr[1:0])\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:81: Define or directive not defined: \'`F3_LBU\'\n `F3_LB, `F3_LBU: case (addr[1:0])\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:89: Define or directive not defined: \'`F3_LH\'\n `F3_LH, `F3_LHU: case (addr[1:0])\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:89: Define or directive not defined: \'`F3_LHU\'\n `F3_LH, `F3_LHU: case (addr[1:0])\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:95: Define or directive not defined: \'`F3_LW\'\n `F3_LW: load_data_shifted = load_data;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:105: Define or directive not defined: \'`F3_LB\'\n `F3_LB: output_data = lds[7] ? {24\'hFFFFFF, lds[7:0]} : {24\'h0, lds[7:0]};\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:106: Define or directive not defined: \'`F3_LH\'\n `F3_LH: output_data = lds[15] ? {16\'hFFFF, lds[15:0]} : {16\'h0, lds[15:0]};\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:107: Define or directive not defined: \'`F3_LW\'\n `F3_LW, `F3_LHU, `F3_LBU: output_data = lds;\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:107: Define or directive not defined: \'`F3_LHU\'\n `F3_LW, `F3_LHU, `F3_LBU: output_data = lds;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/data_memory.v:107: Define or directive not defined: \'`F3_LBU\'\n `F3_LW, `F3_LHU, `F3_LBU: output_data = lds;\n ^~~~~~~\n%Error: Cannot continue\n' | 338 | module | module data_memory (
input [31:0] inst,
input [31:0] data,
input [31:0] addr,
output [31:0] memory_addr,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input [31:0] load_data,
output reg [31:0] output_data
);
wire [2:0] funct3 = inst[9:7];
wire [6:0] opcode = inst[6:0];
assign memory_addr = {addr[31:2], 2'b0};
reg [31:0] write_data_masked;
always @ (*) begin
case (funct3)
`F3_SB: write_data_masked = data & 32'hFF;
`F3_SH: write_data_masked = data & 32'hFFFF;
`F3_SW: write_data_masked = data & 32'hFFFFFFFF;
default: write_data_masked = 32'h0;
endcase
end
always @ (*) begin
case (addr[1:0])
2'b00: write_data = write_data_masked;
2'b01: write_data = write_data_masked << 8;
2'b10: write_data = write_data_masked << 16;
2'b11: write_data = write_data_masked << 24;
default: write_data = 32'b0;
endcase
end
always @ (*) begin
case (funct3)
`F3_SB: write_mask = 4'b1 << addr[1:0];
`F3_SH: write_mask = 4'b11 << addr[1:0];
`F3_SW: write_mask = 4'b1111;
default: write_mask = 0;
endcase
end
reg [31:0] load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB, `F3_LBU: case (addr[1:0])
2'b00: load_data_shifted = {24'b0, load_data[7:0]};
2'b01: load_data_shifted = {24'b0, load_data[15:8]};
2'b10: load_data_shifted = {24'b0, load_data[23:16]};
2'b11: load_data_shifted = {24'b0, load_data[31:24]};
default: load_data_shifted = 32'b0;
endcase
`F3_LH, `F3_LHU: case (addr[1:0])
2'b00: load_data_shifted = {16'b0, load_data[15:0]};
2'b10: load_data_shifted = {16'b0, load_data[31:16]};
default: load_data_shifted = 32'b0;
endcase
`F3_LW: load_data_shifted = load_data;
default: load_data_shifted = 32'b0;
endcase
end
wire [31:0] lds = load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB: output_data = lds[7] ? {24'hFFFFFF, lds[7:0]} : {24'h0, lds[7:0]};
`F3_LH: output_data = lds[15] ? {16'hFFFF, lds[15:0]} : {16'h0, lds[15:0]};
`F3_LW, `F3_LHU, `F3_LBU: output_data = lds;
default: output_data = 32'b0;
endcase
end
endmodule | module data_memory (
input [31:0] inst,
input [31:0] data,
input [31:0] addr,
output [31:0] memory_addr,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input [31:0] load_data,
output reg [31:0] output_data
); |
wire [2:0] funct3 = inst[9:7];
wire [6:0] opcode = inst[6:0];
assign memory_addr = {addr[31:2], 2'b0};
reg [31:0] write_data_masked;
always @ (*) begin
case (funct3)
`F3_SB: write_data_masked = data & 32'hFF;
`F3_SH: write_data_masked = data & 32'hFFFF;
`F3_SW: write_data_masked = data & 32'hFFFFFFFF;
default: write_data_masked = 32'h0;
endcase
end
always @ (*) begin
case (addr[1:0])
2'b00: write_data = write_data_masked;
2'b01: write_data = write_data_masked << 8;
2'b10: write_data = write_data_masked << 16;
2'b11: write_data = write_data_masked << 24;
default: write_data = 32'b0;
endcase
end
always @ (*) begin
case (funct3)
`F3_SB: write_mask = 4'b1 << addr[1:0];
`F3_SH: write_mask = 4'b11 << addr[1:0];
`F3_SW: write_mask = 4'b1111;
default: write_mask = 0;
endcase
end
reg [31:0] load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB, `F3_LBU: case (addr[1:0])
2'b00: load_data_shifted = {24'b0, load_data[7:0]};
2'b01: load_data_shifted = {24'b0, load_data[15:8]};
2'b10: load_data_shifted = {24'b0, load_data[23:16]};
2'b11: load_data_shifted = {24'b0, load_data[31:24]};
default: load_data_shifted = 32'b0;
endcase
`F3_LH, `F3_LHU: case (addr[1:0])
2'b00: load_data_shifted = {16'b0, load_data[15:0]};
2'b10: load_data_shifted = {16'b0, load_data[31:16]};
default: load_data_shifted = 32'b0;
endcase
`F3_LW: load_data_shifted = load_data;
default: load_data_shifted = 32'b0;
endcase
end
wire [31:0] lds = load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB: output_data = lds[7] ? {24'hFFFFFF, lds[7:0]} : {24'h0, lds[7:0]};
`F3_LH: output_data = lds[15] ? {16'hFFFF, lds[15:0]} : {16'h0, lds[15:0]};
`F3_LW, `F3_LHU, `F3_LBU: output_data = lds;
default: output_data = 32'b0;
endcase
end
endmodule | 23 |
2,842 | data/full_repos/permissive/10136357/hardware/src/decode.v | 10,136,357 | decode.v | v | 91 | 84 | [] | [] | [] | [(177, 239)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:48: Define or directive not defined: \'`OPCODE_JAL\'\n assign wd = (opcode == `OPCODE_JAL) ? 5\'d1 : inst[31:27];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign wd = (opcode == `OPCODE_JAL) ? 5\'d1 : inst[31:27];\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:50: Define or directive not defined: \'`OPCODE_OP\'\n assign rf_wr_en = (opcode == `OPCODE_OP ||\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:50: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign rf_wr_en = (opcode == `OPCODE_OP ||\n ^~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:51: Define or directive not defined: \'`OPCODE_OP_IMM\'\n opcode == `OPCODE_OP_IMM ||\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:52: Define or directive not defined: \'`OPCODE_LUI\'\n opcode == `OPCODE_LUI ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:53: Define or directive not defined: \'`OPCODE_LOAD\'\n opcode == `OPCODE_LOAD ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:54: Define or directive not defined: \'`OPCODE_JAL\'\n opcode == `OPCODE_JAL ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:55: Define or directive not defined: \'`OPCODE_JALR\'\n opcode == `OPCODE_JALR ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:56: Define or directive not defined: \'`OPCODE_PCR\'\n opcode == `OPCODE_PCR);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:58: Define or directive not defined: \'`OPCODE_LOAD\'\n assign memory_request = (opcode == `OPCODE_LOAD || \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:58: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign memory_request = (opcode == `OPCODE_LOAD || \n ^~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:59: Define or directive not defined: \'`OPCODE_STORE\'\n opcode == `OPCODE_STORE);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:61: Define or directive not defined: \'`OPCODE_STORE\'\n assign memory_request_type = (opcode == `OPCODE_STORE) ? \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:61: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memory_request_type = (opcode == `OPCODE_STORE) ? \n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:62: Define or directive not defined: \'`MEM_REQ_WRITE\'\n `MEM_REQ_WRITE : `MEM_REQ_READ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:62: Define or directive not defined: \'`MEM_REQ_READ\'\n `MEM_REQ_WRITE : `MEM_REQ_READ;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: syntax error, unexpected \',\', expecting endcase\n `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:67: Define or directive not defined: \'`WB_ALU\'\n wb_sel = `WB_ALU;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:68: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:69: Define or directive not defined: \'`WB_MEM\'\n wb_sel = `WB_MEM;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:70: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_JAL, `OPCODE_JALR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:70: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JAL, `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:71: Define or directive not defined: \'`WB_PC4\'\n wb_sel = `WB_PC4;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:72: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:73: Define or directive not defined: \'`WB_PCR\'\n wb_sel = `WB_PCR;\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:80: Define or directive not defined: \'`OPCODE_PCR\'\n if (opcode == `OPCODE_PCR) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:84: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: Cannot continue\n' | 339 | module | module decode (
input [31:0] inst,
output [4:0] rs1,
output [4:0] rs2,
output [4:0] wd,
output reg [2:0] wb_sel,
output rf_wr_en,
output memory_request,
output memory_request_type,
output reg pcr_enable,
output reg [1:0] pcr_cmd
);
wire [6:0] opcode = inst[6:0];
assign rs1 = inst[26:22];
assign rs2 = inst[21:17];
assign wd = (opcode == `OPCODE_JAL) ? 5'd1 : inst[31:27];
assign rf_wr_en = (opcode == `OPCODE_OP ||
opcode == `OPCODE_OP_IMM ||
opcode == `OPCODE_LUI ||
opcode == `OPCODE_LOAD ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR ||
opcode == `OPCODE_PCR);
assign memory_request = (opcode == `OPCODE_LOAD ||
opcode == `OPCODE_STORE);
assign memory_request_type = (opcode == `OPCODE_STORE) ?
`MEM_REQ_WRITE : `MEM_REQ_READ;
always @ (*) begin
case (opcode)
`OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:
wb_sel = `WB_ALU;
`OPCODE_LOAD:
wb_sel = `WB_MEM;
`OPCODE_JAL, `OPCODE_JALR:
wb_sel = `WB_PC4;
`OPCODE_PCR:
wb_sel = `WB_PCR;
default:
wb_sel = 0;
endcase
end
always @ (*) begin
if (opcode == `OPCODE_PCR) begin
pcr_enable = 1;
pcr_cmd = inst[8:7];
end else begin
pcr_enable = 0;
pcr_cmd = 2'b00;
end
end
endmodule | module decode (
input [31:0] inst,
output [4:0] rs1,
output [4:0] rs2,
output [4:0] wd,
output reg [2:0] wb_sel,
output rf_wr_en,
output memory_request,
output memory_request_type,
output reg pcr_enable,
output reg [1:0] pcr_cmd
); |
wire [6:0] opcode = inst[6:0];
assign rs1 = inst[26:22];
assign rs2 = inst[21:17];
assign wd = (opcode == `OPCODE_JAL) ? 5'd1 : inst[31:27];
assign rf_wr_en = (opcode == `OPCODE_OP ||
opcode == `OPCODE_OP_IMM ||
opcode == `OPCODE_LUI ||
opcode == `OPCODE_LOAD ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR ||
opcode == `OPCODE_PCR);
assign memory_request = (opcode == `OPCODE_LOAD ||
opcode == `OPCODE_STORE);
assign memory_request_type = (opcode == `OPCODE_STORE) ?
`MEM_REQ_WRITE : `MEM_REQ_READ;
always @ (*) begin
case (opcode)
`OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:
wb_sel = `WB_ALU;
`OPCODE_LOAD:
wb_sel = `WB_MEM;
`OPCODE_JAL, `OPCODE_JALR:
wb_sel = `WB_PC4;
`OPCODE_PCR:
wb_sel = `WB_PCR;
default:
wb_sel = 0;
endcase
end
always @ (*) begin
if (opcode == `OPCODE_PCR) begin
pcr_enable = 1;
pcr_cmd = inst[8:7];
end else begin
pcr_enable = 0;
pcr_cmd = 2'b00;
end
end
endmodule | 23 |
2,843 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module reg_decoder (
output reg [23:0] str,
input [4:0] r
);
always @ (*) begin
case (r)
0 : str = " x0";
1 : str = " ra";
2 : str = " s0";
3 : str = " s1";
4 : str = " s2";
5 : str = " s3";
6 : str = " s4";
7 : str = " s5";
8 : str = " s6";
9 : str = " s7";
10: str = " s8";
11: str = " s9";
12: str = "s10";
13: str = "s11";
14: str = " sp";
15: str = " tp";
16: str = " v0";
17: str = " v1";
18: str = " a0";
19: str = " a1";
20: str = " a2";
21: str = " a3";
22: str = " a4";
23: str = " a5";
24: str = " a6";
25: str = " a7";
26: str = " a8";
27: str = " a9";
28: str = "a10";
29: str = "a11";
30: str = "a12";
31: str = "a13";
default: str = "???";
endcase
end
endmodule | module reg_decoder (
output reg [23:0] str,
input [4:0] r
); |
always @ (*) begin
case (r)
0 : str = " x0";
1 : str = " ra";
2 : str = " s0";
3 : str = " s1";
4 : str = " s2";
5 : str = " s3";
6 : str = " s4";
7 : str = " s5";
8 : str = " s6";
9 : str = " s7";
10: str = " s8";
11: str = " s9";
12: str = "s10";
13: str = "s11";
14: str = " sp";
15: str = " tp";
16: str = " v0";
17: str = " v1";
18: str = " a0";
19: str = " a1";
20: str = " a2";
21: str = " a3";
22: str = " a4";
23: str = " a5";
24: str = " a6";
25: str = " a7";
26: str = " a8";
27: str = " a9";
28: str = "a10";
29: str = "a11";
30: str = "a12";
31: str = "a13";
default: str = "???";
endcase
end
endmodule | 23 |
2,844 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module pcreg_decoder (
output reg [63:0] str,
input [4:0] r
);
always @ (*) begin
case (r)
0 : str = " status";
1 : str = " epc";
2 : str = "badvaddr";
3 : str = " evec";
4 : str = " count";
5 : str = " compare";
6 : str = " cause";
7 : str = " ptbr";
12: str = " k0";
13: str = " k1";
30: str = " tohost";
31: str = "fromhost";
default: str = "???";
endcase
end
endmodule | module pcreg_decoder (
output reg [63:0] str,
input [4:0] r
); |
always @ (*) begin
case (r)
0 : str = " status";
1 : str = " epc";
2 : str = "badvaddr";
3 : str = " evec";
4 : str = " count";
5 : str = " compare";
6 : str = " cause";
7 : str = " ptbr";
12: str = " k0";
13: str = " k1";
30: str = " tohost";
31: str = "fromhost";
default: str = "???";
endcase
end
endmodule | 23 |
2,845 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module imm_decoder (
output [47:0] str,
input [11:0] imm12
);
wire [11:0] imm = imm12[11] ? -$signed(imm12) : imm12;
wire [3:0] d0 = imm[3:0];
wire [3:0] d1 = imm[7:4];
wire [3:0] d2 = imm[11:8];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
assign str = {imm12[11] ? "-" : " ", "0x", d2_s, d1_s, d0_s};
endmodule | module imm_decoder (
output [47:0] str,
input [11:0] imm12
); |
wire [11:0] imm = imm12[11] ? -$signed(imm12) : imm12;
wire [3:0] d0 = imm[3:0];
wire [3:0] d1 = imm[7:4];
wire [3:0] d2 = imm[11:8];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
assign str = {imm12[11] ? "-" : " ", "0x", d2_s, d1_s, d0_s};
endmodule | 23 |
2,846 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module lui_decoder (
output [55:0] str,
input [19:0] imm
);
wire [3:0] d0 = imm[3:0];
wire [3:0] d1 = imm[7:4];
wire [3:0] d2 = imm[11:8];
wire [3:0] d3 = imm[15:12];
wire [3:0] d4 = imm[19:16];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
wire [7:0] d3_s = d3 <= 9 ? "0" + d3 : "A" + d3 - 10;
wire [7:0] d4_s = d4 <= 9 ? "0" + d4 : "A" + d4 - 10;
assign str = {"0x", d4_s, d3_s, d2_s, d1_s, d0_s};
endmodule | module lui_decoder (
output [55:0] str,
input [19:0] imm
); |
wire [3:0] d0 = imm[3:0];
wire [3:0] d1 = imm[7:4];
wire [3:0] d2 = imm[11:8];
wire [3:0] d3 = imm[15:12];
wire [3:0] d4 = imm[19:16];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
wire [7:0] d3_s = d3 <= 9 ? "0" + d3 : "A" + d3 - 10;
wire [7:0] d4_s = d4 <= 9 ? "0" + d4 : "A" + d4 - 10;
assign str = {"0x", d4_s, d3_s, d2_s, d1_s, d0_s};
endmodule | 23 |
2,847 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module addr_decoder (
output [79:0] str,
input [31:0] addr
);
wire [3:0] d0 = addr[3:0];
wire [3:0] d1 = addr[7:4];
wire [3:0] d2 = addr[11:8];
wire [3:0] d3 = addr[15:12];
wire [3:0] d4 = addr[19:16];
wire [3:0] d5 = addr[23:20];
wire [3:0] d6 = addr[27:24];
wire [3:0] d7 = addr[31:28];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
wire [7:0] d3_s = d3 <= 9 ? "0" + d3 : "A" + d3 - 10;
wire [7:0] d4_s = d4 <= 9 ? "0" + d4 : "A" + d4 - 10;
wire [7:0] d5_s = d5 <= 9 ? "0" + d5 : "A" + d5 - 10;
wire [7:0] d6_s = d6 <= 9 ? "0" + d6 : "A" + d6 - 10;
wire [7:0] d7_s = d7 <= 9 ? "0" + d7 : "A" + d7 - 10;
assign str = {"0x", d7_s, d6_s, d5_s, d4_s, d3_s, d2_s, d1_s, d0_s};
endmodule | module addr_decoder (
output [79:0] str,
input [31:0] addr
); |
wire [3:0] d0 = addr[3:0];
wire [3:0] d1 = addr[7:4];
wire [3:0] d2 = addr[11:8];
wire [3:0] d3 = addr[15:12];
wire [3:0] d4 = addr[19:16];
wire [3:0] d5 = addr[23:20];
wire [3:0] d6 = addr[27:24];
wire [3:0] d7 = addr[31:28];
wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;
wire [7:0] d3_s = d3 <= 9 ? "0" + d3 : "A" + d3 - 10;
wire [7:0] d4_s = d4 <= 9 ? "0" + d4 : "A" + d4 - 10;
wire [7:0] d5_s = d5 <= 9 ? "0" + d5 : "A" + d5 - 10;
wire [7:0] d6_s = d6 <= 9 ? "0" + d6 : "A" + d6 - 10;
wire [7:0] d7_s = d7 <= 9 ? "0" + d7 : "A" + d7 - 10;
assign str = {"0x", d7_s, d6_s, d5_s, d4_s, d3_s, d2_s, d1_s, d0_s};
endmodule | 23 |
2,848 | data/full_repos/permissive/10136357/hardware/src/inst_decoder.v | 10,136,357 | inst_decoder.v | v | 353 | 84 | [] | [] | [] | [(177, 218), (220, 241), (243, 259), (261, 280), (282, 307), (309, 500)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = \n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_J, `OPCODE_JAL:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n `OPCODE_BRANCH:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n `OPCODE_LOAD:\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n `OPCODE_STORE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n `OPCODE_PCR:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] =\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n str[(`STR_LEN - 8) * 8 - 1:0] = "";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n `OPCODE_OP:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n `F3_MUL: op_s = "mul ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n `F3_MULH: op_s = "mulh ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n `F3_MULHSU: op_s = "mulhsu ";\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n `F3_MULHU: op_s = "mulhu ";\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n `F3_DIV: op_s = "div ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n `F3_DIVU: op_s = "divu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n `F3_REM: op_s = "rem ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n `F3_REMU: op_s = "remu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst[16] ? "sub " : "add ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "sll ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slt ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xor ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n `F3_SR: op_s = inst[16] ? "sra " : "srl ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n `F3_OR: op_s = "or ";\n ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n `F3_AND: op_s = "and ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n `OPCODE_OP_IMM:\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n `F3_ADD: op_s = inst == 32\'h00000013 ? "nop " : "addi ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n `F3_SLL: op_s = "slli ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n `F3_SLT: op_s = "slti ";\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n `F3_SLTU: op_s = "sltiu ";\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n `F3_XOR: op_s = "xori ";\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 340 | module | module inst_decoder (
output reg [(`STR_LEN * 8) - 1:0] str,
input [31:0] jump_target,
input [31:0] branch_target,
input [31:0] inst
);
wire [6:0] opcode = inst[6:0];
wire [9:7] funct3 = inst[9:7];
wire [11:0] imm12 = inst[21:10];
wire [19:0] imm20 = inst[26:7];
wire [11:0] split_imm12 = {inst[31:27], inst[16:10]};
wire [4:0] wd = inst[31:27];
reg [(8 * 8) - 1:0] op_s;
reg [1:0] type;
wire [23:0] wd_s;
wire [23:0] rs1_s;
wire [23:0] rs2_s;
wire [63:0] pcr_s;
wire [47:0] imm12_s;
wire [47:0] split_imm12_s;
wire [55:0] imm20_s;
wire [79:0] addr_s;
wire [79:0] branch_addr_s;
reg_decoder r1(wd_s, wd);
reg_decoder r2(rs1_s, inst[26:22]);
reg_decoder r3(rs2_s, inst[21:17]);
pcreg_decoder r4(pcr_s, inst[26:22]);
imm_decoder id(imm12_s, imm12);
lui_decoder ld(imm20_s, imm20);
imm_decoder sid(split_imm12_s, split_imm12);
addr_decoder ad(addr_s, jump_target);
addr_decoder bd(branch_addr_s, branch_target);
always @ (*) begin
case (opcode)
`OPCODE_OP:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", rs2_s};
`OPCODE_OP_IMM: begin
if (inst != 32'h00000013)
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", imm12_s};
else
str[(`STR_LEN - 8) * 8 - 1:0] = "";
end
`OPCODE_LUI:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", imm20_s};
`OPCODE_J, `OPCODE_JAL:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", addr_s};
`OPCODE_JALR:
if (inst != 32'h004000eb)
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", addr_s};
else
str[(`STR_LEN - 8) * 8 - 1:0] = "";
`OPCODE_BRANCH:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", rs1_s, ",", rs2_s, ",", branch_addr_s};
`OPCODE_LOAD:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", imm12_s, "(", rs1_s, ")"};
`OPCODE_STORE:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", rs2_s, ",", split_imm12_s, "(", rs1_s, ")"};
`OPCODE_PCR:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs2_s, ",", pcr_s};
default:
str[(`STR_LEN - 8) * 8 - 1:0] = "";
endcase
end
always @ (*) begin
case (opcode)
`OPCODE_OP:
if (inst[10]) begin
case (funct3)
`F3_MUL: op_s = "mul ";
`F3_MULH: op_s = "mulh ";
`F3_MULHSU: op_s = "mulhsu ";
`F3_MULHU: op_s = "mulhu ";
`F3_DIV: op_s = "div ";
`F3_DIVU: op_s = "divu ";
`F3_REM: op_s = "rem ";
`F3_REMU: op_s = "remu ";
default: op_s = "??? ";
endcase
end else begin
case (funct3)
`F3_ADD: op_s = inst[16] ? "sub " : "add ";
`F3_SLL: op_s = "sll ";
`F3_SLT: op_s = "slt ";
`F3_SLTU: op_s = "sltu ";
`F3_XOR: op_s = "xor ";
`F3_SR: op_s = inst[16] ? "sra " : "srl ";
`F3_OR: op_s = "or ";
`F3_AND: op_s = "and ";
default: op_s = "??? ";
endcase
end
`OPCODE_OP_IMM:
case (funct3)
`F3_ADD: op_s = inst == 32'h00000013 ? "nop " : "addi ";
`F3_SLL: op_s = "slli ";
`F3_SLT: op_s = "slti ";
`F3_SLTU: op_s = "sltiu ";
`F3_XOR: op_s = "xori ";
`F3_SR: op_s = inst[16] ? "srai " : "srli ";
`F3_OR: op_s = "ori ";
`F3_AND: op_s = "andi ";
default: op_s = "??? ";
endcase
`OPCODE_LUI:
op_s = "lui ";
`OPCODE_J:
op_s = "j ";
`OPCODE_JAL:
op_s = "jal ";
`OPCODE_JALR:
if (inst == 32'h004000eb)
op_s = "ret ";
else
op_s = wd == 5'd0 ? "jr " : "jalr ";
`OPCODE_LOAD:
case (funct3)
`F3_LB: op_s = "lb ";
`F3_LH: op_s = "lh ";
`F3_LW: op_s = "lw ";
`F3_LBU: op_s = "lbu ";
`F3_LHU: op_s = "lhu ";
default: op_s = "??? ";
endcase
`OPCODE_STORE:
case (funct3)
`F3_SB: op_s = "sb ";
`F3_SH: op_s = "sh ";
`F3_SW: op_s = "sw ";
default: op_s = "??? ";
endcase
`OPCODE_BRANCH:
case (funct3)
`F3_BEQ: op_s = "beq ";
`F3_BNE: op_s = "bne ";
`F3_BLT: op_s = "blt ";
`F3_BGE: op_s = "bge ";
`F3_BLTU: op_s = "bltu ";
`F3_BGEU: op_s = "bgeu ";
default: op_s = "??? ";
endcase
`OPCODE_PCR:
case (funct3)
`F3_CLEARPCR: op_s = "clearpcr";
`F3_SETPCR: op_s = "setpcr ";
`F3_MFPCR: op_s = "mfpcr ";
`F3_MTPCR: op_s = "mtpcr ";
default: op_s = "??? ";
endcase
default:
op_s = "???";
endcase
str[(`STR_LEN * 8) - 1:((`STR_LEN - 8) * 8)] = op_s;
end
endmodule | module inst_decoder (
output reg [(`STR_LEN * 8) - 1:0] str,
input [31:0] jump_target,
input [31:0] branch_target,
input [31:0] inst
); |
wire [6:0] opcode = inst[6:0];
wire [9:7] funct3 = inst[9:7];
wire [11:0] imm12 = inst[21:10];
wire [19:0] imm20 = inst[26:7];
wire [11:0] split_imm12 = {inst[31:27], inst[16:10]};
wire [4:0] wd = inst[31:27];
reg [(8 * 8) - 1:0] op_s;
reg [1:0] type;
wire [23:0] wd_s;
wire [23:0] rs1_s;
wire [23:0] rs2_s;
wire [63:0] pcr_s;
wire [47:0] imm12_s;
wire [47:0] split_imm12_s;
wire [55:0] imm20_s;
wire [79:0] addr_s;
wire [79:0] branch_addr_s;
reg_decoder r1(wd_s, wd);
reg_decoder r2(rs1_s, inst[26:22]);
reg_decoder r3(rs2_s, inst[21:17]);
pcreg_decoder r4(pcr_s, inst[26:22]);
imm_decoder id(imm12_s, imm12);
lui_decoder ld(imm20_s, imm20);
imm_decoder sid(split_imm12_s, split_imm12);
addr_decoder ad(addr_s, jump_target);
addr_decoder bd(branch_addr_s, branch_target);
always @ (*) begin
case (opcode)
`OPCODE_OP:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", rs2_s};
`OPCODE_OP_IMM: begin
if (inst != 32'h00000013)
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", imm12_s};
else
str[(`STR_LEN - 8) * 8 - 1:0] = "";
end
`OPCODE_LUI:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", imm20_s};
`OPCODE_J, `OPCODE_JAL:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", addr_s};
`OPCODE_JALR:
if (inst != 32'h004000eb)
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs1_s, ",", addr_s};
else
str[(`STR_LEN - 8) * 8 - 1:0] = "";
`OPCODE_BRANCH:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", rs1_s, ",", rs2_s, ",", branch_addr_s};
`OPCODE_LOAD:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", imm12_s, "(", rs1_s, ")"};
`OPCODE_STORE:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", rs2_s, ",", split_imm12_s, "(", rs1_s, ")"};
`OPCODE_PCR:
str[(`STR_LEN - 8) * 8 - 1:0] =
{" ", wd_s, ",", rs2_s, ",", pcr_s};
default:
str[(`STR_LEN - 8) * 8 - 1:0] = "";
endcase
end
always @ (*) begin
case (opcode)
`OPCODE_OP:
if (inst[10]) begin
case (funct3)
`F3_MUL: op_s = "mul ";
`F3_MULH: op_s = "mulh ";
`F3_MULHSU: op_s = "mulhsu ";
`F3_MULHU: op_s = "mulhu ";
`F3_DIV: op_s = "div ";
`F3_DIVU: op_s = "divu ";
`F3_REM: op_s = "rem ";
`F3_REMU: op_s = "remu ";
default: op_s = "??? ";
endcase
end else begin
case (funct3)
`F3_ADD: op_s = inst[16] ? "sub " : "add ";
`F3_SLL: op_s = "sll ";
`F3_SLT: op_s = "slt ";
`F3_SLTU: op_s = "sltu ";
`F3_XOR: op_s = "xor ";
`F3_SR: op_s = inst[16] ? "sra " : "srl ";
`F3_OR: op_s = "or ";
`F3_AND: op_s = "and ";
default: op_s = "??? ";
endcase
end
`OPCODE_OP_IMM:
case (funct3)
`F3_ADD: op_s = inst == 32'h00000013 ? "nop " : "addi ";
`F3_SLL: op_s = "slli ";
`F3_SLT: op_s = "slti ";
`F3_SLTU: op_s = "sltiu ";
`F3_XOR: op_s = "xori ";
`F3_SR: op_s = inst[16] ? "srai " : "srli ";
`F3_OR: op_s = "ori ";
`F3_AND: op_s = "andi ";
default: op_s = "??? ";
endcase
`OPCODE_LUI:
op_s = "lui ";
`OPCODE_J:
op_s = "j ";
`OPCODE_JAL:
op_s = "jal ";
`OPCODE_JALR:
if (inst == 32'h004000eb)
op_s = "ret ";
else
op_s = wd == 5'd0 ? "jr " : "jalr ";
`OPCODE_LOAD:
case (funct3)
`F3_LB: op_s = "lb ";
`F3_LH: op_s = "lh ";
`F3_LW: op_s = "lw ";
`F3_LBU: op_s = "lbu ";
`F3_LHU: op_s = "lhu ";
default: op_s = "??? ";
endcase
`OPCODE_STORE:
case (funct3)
`F3_SB: op_s = "sb ";
`F3_SH: op_s = "sh ";
`F3_SW: op_s = "sw ";
default: op_s = "??? ";
endcase
`OPCODE_BRANCH:
case (funct3)
`F3_BEQ: op_s = "beq ";
`F3_BNE: op_s = "bne ";
`F3_BLT: op_s = "blt ";
`F3_BGE: op_s = "bge ";
`F3_BLTU: op_s = "bltu ";
`F3_BGEU: op_s = "bgeu ";
default: op_s = "??? ";
endcase
`OPCODE_PCR:
case (funct3)
`F3_CLEARPCR: op_s = "clearpcr";
`F3_SETPCR: op_s = "setpcr ";
`F3_MFPCR: op_s = "mfpcr ";
`F3_MTPCR: op_s = "mtpcr ";
default: op_s = "??? ";
endcase
default:
op_s = "???";
endcase
str[(`STR_LEN * 8) - 1:((`STR_LEN - 8) * 8)] = op_s;
end
endmodule | 23 |
2,850 | data/full_repos/permissive/10136357/hardware/src/mem_mux.v | 10,136,357 | mem_mux.v | v | 66 | 84 | [] | [] | [] | [(26, 64)] | null | data/verilator_xmls/606b23e1-90d6-4c39-bb5c-26ef12f35704.xml | null | 342 | module | module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
);
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule | module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
); |
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule | 23 |
2,851 | data/full_repos/permissive/10136357/hardware/src/multiplier.v | 10,136,357 | multiplier.v | v | 54 | 84 | [] | [] | [] | [(177, 202)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: Define or directive not defined: \'`MUL_LO\'\n `MUL_LO, `MUL_HI:\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: syntax error, unexpected \',\', expecting endcase\n `MUL_LO, `MUL_HI:\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: Define or directive not defined: \'`MUL_HI\'\n `MUL_LO, `MUL_HI:\n ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:43: Define or directive not defined: \'`MUL_HI_SU\'\n `MUL_HI_SU:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:45: Define or directive not defined: \'`MUL_HI_UU\'\n `MUL_HI_UU:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:52: Define or directive not defined: \'`MUL_LO\'\n assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];\n ^~~~~~~\n%Error: Cannot continue\n' | 343 | module | module multiplier (
output [31:0] multiplier_result,
input [31:0] op1,
input [31:0] op2,
input [1:0] mul_sel
);
wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};
reg [63:0] result;
always @ (*) begin
case (mul_sel)
`MUL_LO, `MUL_HI:
result = $signed(sext_op1) * $signed(sext_op2);
`MUL_HI_SU:
result = $signed(sext_op1) * {32'h0, op2};
`MUL_HI_UU:
result = {32'h0, op1} * {32'h0, op2};
default:
result = 0;
endcase
end
assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule | module multiplier (
output [31:0] multiplier_result,
input [31:0] op1,
input [31:0] op2,
input [1:0] mul_sel
); |
wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};
reg [63:0] result;
always @ (*) begin
case (mul_sel)
`MUL_LO, `MUL_HI:
result = $signed(sext_op1) * $signed(sext_op2);
`MUL_HI_SU:
result = $signed(sext_op1) * {32'h0, op2};
`MUL_HI_UU:
result = {32'h0, op1} * {32'h0, op2};
default:
result = 0;
endcase
end
assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule | 23 |
2,853 | data/full_repos/permissive/10136357/hardware/src/simulated_memory.v | 10,136,357 | simulated_memory.v | v | 78 | 98 | [] | [] | [] | [(179, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:28: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:55: Define or directive not defined: \'`MEM_CMD_READ\'\n if (enable && cmd == `MEM_CMD_READ) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (enable && cmd == `MEM_CMD_READ) begin\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:58: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:72: Define or directive not defined: \'`MEM_CMD_WRITE\'\n if (enable && cmd == `MEM_CMD_WRITE) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/simulated_memory.v:72: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (enable && cmd == `MEM_CMD_WRITE) begin\n ^\n%Error: Cannot continue\n' | 345 | module | module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule | module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
); |
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule | 23 |
2,854 | data/full_repos/permissive/10136357/hardware/src/tlb.v | 10,136,357 | tlb.v | v | 105 | 84 | [] | [] | [] | [(26, 102)] | null | data/verilator_xmls/abea8932-ebc8-42a3-aace-76a150d492f3.xml | null | 346 | module | module tlb (
input clk,
input reset,
input flush,
input vm_enable,
input enable,
input [31:0] virtual_address,
output reg [31:0] physical_address,
output reg tlb_hit,
output reg translation_required,
input [31:0] translated_address,
input translation_complete
);
localparam TLB_ENTRIES = 4;
reg [1:0] entry;
reg [40:0] tlb [TLB_ENTRIES-1:0];
integer i, j;
always @ (posedge clk) begin
if (reset || flush) begin
for (j = 0; j < TLB_ENTRIES; j = j + 1) begin
tlb[j] = 41'b0;
end
entry = 0;
end
end
localparam S_CHECK = 0;
localparam S_WAIT = 1;
reg state;
reg next_state;
always @ (posedge clk) begin
if (reset)
state <= S_CHECK;
else
state <= next_state;
end
always @ (*) begin
case (state)
S_CHECK: begin
tlb_hit = 0;
for (i = 0; i < TLB_ENTRIES; i = i + 1) begin
if (virtual_address[31:12] == tlb[i][39:20] && tlb[i][40]) begin
physical_address = {tlb[i][19:0], virtual_address[11:0]};
tlb_hit = 1;
end
end
translation_required = !tlb_hit && enable && vm_enable;
next_state = !translation_required ? S_CHECK : S_WAIT;
end
S_WAIT:
next_state = translation_complete ? S_CHECK : S_WAIT;
default:
next_state = S_CHECK;
endcase
end
always @ (*) begin
if (state == S_WAIT && translation_complete) begin
tlb[entry] = {1'b1, virtual_address[31:12], translated_address[31:12]};
entry = entry + 1;
end
end
endmodule | module tlb (
input clk,
input reset,
input flush,
input vm_enable,
input enable,
input [31:0] virtual_address,
output reg [31:0] physical_address,
output reg tlb_hit,
output reg translation_required,
input [31:0] translated_address,
input translation_complete
); |
localparam TLB_ENTRIES = 4;
reg [1:0] entry;
reg [40:0] tlb [TLB_ENTRIES-1:0];
integer i, j;
always @ (posedge clk) begin
if (reset || flush) begin
for (j = 0; j < TLB_ENTRIES; j = j + 1) begin
tlb[j] = 41'b0;
end
entry = 0;
end
end
localparam S_CHECK = 0;
localparam S_WAIT = 1;
reg state;
reg next_state;
always @ (posedge clk) begin
if (reset)
state <= S_CHECK;
else
state <= next_state;
end
always @ (*) begin
case (state)
S_CHECK: begin
tlb_hit = 0;
for (i = 0; i < TLB_ENTRIES; i = i + 1) begin
if (virtual_address[31:12] == tlb[i][39:20] && tlb[i][40]) begin
physical_address = {tlb[i][19:0], virtual_address[11:0]};
tlb_hit = 1;
end
end
translation_required = !tlb_hit && enable && vm_enable;
next_state = !translation_required ? S_CHECK : S_WAIT;
end
S_WAIT:
next_state = translation_complete ? S_CHECK : S_WAIT;
default:
next_state = S_CHECK;
endcase
end
always @ (*) begin
if (state == S_WAIT && translation_complete) begin
tlb[entry] = {1'b1, virtual_address[31:12], translated_address[31:12]};
entry = entry + 1;
end
end
endmodule | 23 |
2,855 | data/full_repos/permissive/10136357/hardware/src/top.v | 10,136,357 | top.v | v | 63 | 112 | [] | [] | [] | [(26, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/10136357/hardware/src/top.v:49: Cannot find file containing module: 'datapath'\n datapath dpath(.clk(clk), .reset(reset), .stall(stall),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/datapath\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/datapath.v\n data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/top.v:55: Cannot find file containing module: 'memory_system'\n memory_system ms(.clk(clk), .reset(reset), .stall(stall),\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 347 | module | module top (
input clk,
input reset
);
wire stall;
wire [31:0] fetch_addr;
wire fetch_request;
wire fetch_data_valid;
wire [31:0] memory_addr;
wire [31:0] write_data;
wire [3:0] write_mask;
wire memory_request;
wire memory_request_type;
wire memory_data_valid;
wire[31:0] request_data;
wire [31:0] ptbr;
wire vm_enable;
datapath dpath(.clk(clk), .reset(reset), .stall(stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid),
.request_data(request_data), .vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
memory_system ms(.clk(clk), .reset(reset), .stall(stall),
.request_data(request_data),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid));
endmodule | module top (
input clk,
input reset
); |
wire stall;
wire [31:0] fetch_addr;
wire fetch_request;
wire fetch_data_valid;
wire [31:0] memory_addr;
wire [31:0] write_data;
wire [3:0] write_mask;
wire memory_request;
wire memory_request_type;
wire memory_data_valid;
wire[31:0] request_data;
wire [31:0] ptbr;
wire vm_enable;
datapath dpath(.clk(clk), .reset(reset), .stall(stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid),
.request_data(request_data), .vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
memory_system ms(.clk(clk), .reset(reset), .stall(stall),
.request_data(request_data),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid));
endmodule | 23 |
2,857 | data/full_repos/permissive/10136357/hardware/src/tests/top_test.v | 10,136,357 | top_test.v | v | 91 | 97 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh\n data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh.v\n data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh.sv\n consts.vh\n consts.vh.v\n consts.vh.sv\n obj_dir/consts.vh\n obj_dir/consts.vh.v\n obj_dir/consts.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #(half_cycle) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:41: Define or directive not defined: \'`STR_LEN\'\n wire [(`STR_LEN * 8) - 1:0] s;\n ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:41: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [(`STR_LEN * 8) - 1:0] s;\n ^\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #(cycle);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(cycle);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n #(cycle);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n #(cycle);\n ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n' | 349 | module | module top_test ();
reg clk;
reg reset;
initial clk = 0;
parameter half_cycle = 5;
localparam cycle = 2 * half_cycle;
localparam timeout = 100;
always #(half_cycle) clk = ~clk;
wire [(`STR_LEN * 8) - 1:0] s;
top top(.clk(clk), .reset(reset));
inst_decoder id(.str(s),
.jump_target(top.dpath.jump_target),
.branch_target(top.dpath.branch_target),
.inst(top.dpath.inst));
integer i;
initial begin
$dumpvars();
i = 0;
#(cycle);
reset = 1;
#(cycle);
reset = 0;
#(cycle);
while (top.dpath.cp.tohost == 0 && i < timeout) begin
#(cycle);
i = i + 1;
$display("C %10d: pc=[%08x] [%s] W[r%2d=%08x][%b] R[r%2d=%08x] R[r%2d=%08x] inst=[%08x] %s",
i, top.dpath.pc, top.stall ? "S" : " ",
top.dpath.ex_wd, top.dpath.rf_wdata, top.dpath.rf_wr_en,
top.dpath.ex_rs1, top.dpath.rf_rd1,
top.dpath.ex_rs2, top.dpath.rf_rd2,
top.dpath.inst,
top.stall ? "" : s);
end
if (i == timeout) begin
$display("*** TIMEOUT ***");
$finish();
end
if (top.dpath.cp.tohost == 1) begin
$display("*** SUCCESS (tohost = 1) ***");
end else begin
$display("*** FAILURE (tohost = %d) ***", top.dpath.cp.tohost);
end
$finish();
end
endmodule | module top_test (); |
reg clk;
reg reset;
initial clk = 0;
parameter half_cycle = 5;
localparam cycle = 2 * half_cycle;
localparam timeout = 100;
always #(half_cycle) clk = ~clk;
wire [(`STR_LEN * 8) - 1:0] s;
top top(.clk(clk), .reset(reset));
inst_decoder id(.str(s),
.jump_target(top.dpath.jump_target),
.branch_target(top.dpath.branch_target),
.inst(top.dpath.inst));
integer i;
initial begin
$dumpvars();
i = 0;
#(cycle);
reset = 1;
#(cycle);
reset = 0;
#(cycle);
while (top.dpath.cp.tohost == 0 && i < timeout) begin
#(cycle);
i = i + 1;
$display("C %10d: pc=[%08x] [%s] W[r%2d=%08x][%b] R[r%2d=%08x] R[r%2d=%08x] inst=[%08x] %s",
i, top.dpath.pc, top.stall ? "S" : " ",
top.dpath.ex_wd, top.dpath.rf_wdata, top.dpath.rf_wr_en,
top.dpath.ex_rs1, top.dpath.rf_rd1,
top.dpath.ex_rs2, top.dpath.rf_rd2,
top.dpath.inst,
top.stall ? "" : s);
end
if (i == timeout) begin
$display("*** TIMEOUT ***");
$finish();
end
if (top.dpath.cp.tohost == 1) begin
$display("*** SUCCESS (tohost = 1) ***");
end else begin
$display("*** FAILURE (tohost = %d) ***", top.dpath.cp.tohost);
end
$finish();
end
endmodule | 23 |
2,858 | data/full_repos/permissive/101423580/v/control_test.v | 101,423,580 | control_test.v | v | 83 | 81 | [] | [] | [] | [(25, 81)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101423580/v/control_test.v:76: Unsupported: Ignoring delay on this delayed statement.\n #54; col <= col + 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101423580/v/control_test.v:46: Cannot find file containing module: \'control\'\n control uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control.v\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control.sv\n control\n control.v\n control.sv\n obj_dir/control\n obj_dir/control.v\n obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 352 | module | module control_test;
reg clk;
reg [9:0] col;
reg [8:0] row;
reg [3:0] RAMData;
reg rst;
reg [2:0] mode;
reg [11:0] Din;
wire [4:0] SyncAddr;
wire [11:0] Dout;
wire RAMaddrEN;
wire [2:0] ROMmux2;
wire [4:0] RAMaddr;
wire [3:0] ROMmux;
wire [12:0] ROMaddr;
control uut (
.clk(clk),
.col(col),
.row(row),
.RAMData(RAMData),
.rst(rst),
.mode(mode),
.Din(Din),
.SyncAddr(SyncAddr),
.Dout(Dout),
.RAMaddrEN(RAMaddrEN),
.ROMmux2(ROMmux2),
.RAMaddr(RAMaddr),
.ROMmux(ROMmux),
.ROMaddr(ROMaddr)
);
initial begin
clk = 0;
col = 144;
row = 20;
RAMData = 0;
rst = 0;
mode = 0;
Din = 0;
end
always @ *
begin
#54; col <= col + 1'b1;
end
endmodule | module control_test; |
reg clk;
reg [9:0] col;
reg [8:0] row;
reg [3:0] RAMData;
reg rst;
reg [2:0] mode;
reg [11:0] Din;
wire [4:0] SyncAddr;
wire [11:0] Dout;
wire RAMaddrEN;
wire [2:0] ROMmux2;
wire [4:0] RAMaddr;
wire [3:0] ROMmux;
wire [12:0] ROMaddr;
control uut (
.clk(clk),
.col(col),
.row(row),
.RAMData(RAMData),
.rst(rst),
.mode(mode),
.Din(Din),
.SyncAddr(SyncAddr),
.Dout(Dout),
.RAMaddrEN(RAMaddrEN),
.ROMmux2(ROMmux2),
.RAMaddr(RAMaddr),
.ROMmux(ROMmux),
.ROMaddr(ROMaddr)
);
initial begin
clk = 0;
col = 144;
row = 20;
RAMData = 0;
rst = 0;
mode = 0;
Din = 0;
end
always @ *
begin
#54; col <= col + 1'b1;
end
endmodule | 0 |
2,859 | data/full_repos/permissive/101423580/v/GPIO.v | 101,423,580 | GPIO.v | v | 49 | 98 | [] | [] | [] | [(21, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/101423580/v/GPIO.v:41: Cannot find file containing module: 'LED_P2S'\n LED_P2S #(.DATA_BITS(16), .DATA_COUNT_BITS(4))\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/LED_P2S\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/LED_P2S.v\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/LED_P2S.sv\n LED_P2S\n LED_P2S.v\n LED_P2S.sv\n obj_dir/LED_P2S\n obj_dir/LED_P2S.v\n obj_dir/LED_P2S.sv\n%Error: Exiting due to 1 error(s)\n" | 353 | module | module GPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output wire led_clk,
output wire led_sout,
output wire led_clrn,
output wire LED_PEN,
output reg[31:0] GPIOf0
);
wire [15:0]LED;
assign LED = {~{GPIOf0[0],GPIOf0[1],GPIOf0[2],GPIOf0[3],GPIOf0[4],GPIOf0[5],GPIOf0[6],GPIOf0[7],
GPIOf0[8],GPIOf0[9],GPIOf0[10],GPIOf0[11],GPIOf0[12],GPIOf0[13],GPIOf0[14],GPIOf0[15]}};
always @ (negedge clk or posedge rst)
if(rst) GPIOf0 <= 32'h00000000;
else if(EN) GPIOf0 <= P_Data;
else GPIOf0 <= GPIOf0;
LED_P2S #(.DATA_BITS(16), .DATA_COUNT_BITS(4))
LED_P2S (clk, rst, Start,
LED,
led_clk,
led_clrn,
led_sout,
LED_PEN
);
endmodule | module GPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output wire led_clk,
output wire led_sout,
output wire led_clrn,
output wire LED_PEN,
output reg[31:0] GPIOf0
); |
wire [15:0]LED;
assign LED = {~{GPIOf0[0],GPIOf0[1],GPIOf0[2],GPIOf0[3],GPIOf0[4],GPIOf0[5],GPIOf0[6],GPIOf0[7],
GPIOf0[8],GPIOf0[9],GPIOf0[10],GPIOf0[11],GPIOf0[12],GPIOf0[13],GPIOf0[14],GPIOf0[15]}};
always @ (negedge clk or posedge rst)
if(rst) GPIOf0 <= 32'h00000000;
else if(EN) GPIOf0 <= P_Data;
else GPIOf0 <= GPIOf0;
LED_P2S #(.DATA_BITS(16), .DATA_COUNT_BITS(4))
LED_P2S (clk, rst, Start,
LED,
led_clk,
led_clrn,
led_sout,
LED_PEN
);
endmodule | 0 |
2,860 | data/full_repos/permissive/101423580/v/Hex2Seg.v | 101,423,580 | Hex2Seg.v | v | 34 | 89 | [] | [] | [] | [(21, 33)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'a\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'b\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'c\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'d\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'e\'\n : ... Suggested alternative: \'en\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'f\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'g\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Warning-IMPLICIT: data/full_repos/permissive/101423580/v/Hex2Seg.v:32: Signal definition not found, creating implicitly: \'p\'\n assign Segment = {a,b,c,d,e,f,g,p}; \n ^\n%Error: data/full_repos/permissive/101423580/v/Hex2Seg.v:30: Cannot find file containing module: \'MC14495_sch\'\n MC14495_sch MSEG(.D3(Hex[3]),.D2(Hex[2]),.D1(Hex[1]),.D0(Hex[0]),.LE(en),.point(point),\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MC14495_sch\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MC14495_sch.v\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MC14495_sch.sv\n MC14495_sch\n MC14495_sch.v\n MC14495_sch.sv\n obj_dir/MC14495_sch\n obj_dir/MC14495_sch.v\n obj_dir/MC14495_sch.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n' | 354 | module | module Hex2Seg(
input [3:0]Hex,
input LE,
input point,
input flash,
output[7:0]Segment
);
wire en = LE & flash;
MC14495_sch MSEG(.D3(Hex[3]),.D2(Hex[2]),.D1(Hex[1]),.D0(Hex[0]),.LE(en),.point(point),
.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.p(p));
assign Segment = {a,b,c,d,e,f,g,p};
endmodule | module Hex2Seg(
input [3:0]Hex,
input LE,
input point,
input flash,
output[7:0]Segment
); |
wire en = LE & flash;
MC14495_sch MSEG(.D3(Hex[3]),.D2(Hex[2]),.D1(Hex[1]),.D0(Hex[0]),.LE(en),.point(point),
.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.p(p));
assign Segment = {a,b,c,d,e,f,g,p};
endmodule | 0 |
2,861 | data/full_repos/permissive/101423580/v/HexTo8SEG.v | 101,423,580 | HexTo8SEG.v | v | 36 | 83 | [] | [] | [] | [(21, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:27: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS0(Hexs[31:28],LES[7],points[7],flash,SEG_TXT[7:0]);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/Hex2Seg\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/Hex2Seg.v\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/Hex2Seg.sv\n Hex2Seg\n Hex2Seg.v\n Hex2Seg.sv\n obj_dir/Hex2Seg\n obj_dir/Hex2Seg.v\n obj_dir/Hex2Seg.sv\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:28: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS1(Hexs[27:24],LES[6],points[6],flash,SEG_TXT[15:8]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:29: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS2(Hexs[23:20],LES[5],points[5],flash,SEG_TXT[23:16]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:30: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS3(Hexs[19:16],LES[4],points[4],flash,SEG_TXT[31:24]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:31: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS4(Hexs[15:12],LES[3],points[3],flash,SEG_TXT[39:32]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:32: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS5(Hexs[11:8],LES[2],points[2],flash,SEG_TXT[47:40]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:33: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS6(Hexs[7:4],LES[1],points[1],flash,SEG_TXT[55:48]);\n ^~~~~~~\n%Error: data/full_repos/permissive/101423580/v/HexTo8SEG.v:34: Cannot find file containing module: 'Hex2Seg'\n Hex2Seg HTS7(Hexs[3:0],LES[0],points[0],flash,SEG_TXT[63:56]);\n ^~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 355 | module | module HexTo8SEG(input [31:0] Hexs,
input [7:0] points,
input [7:0] LES,
input flash,
output [63:0] SEG_TXT
);
Hex2Seg HTS0(Hexs[31:28],LES[7],points[7],flash,SEG_TXT[7:0]);
Hex2Seg HTS1(Hexs[27:24],LES[6],points[6],flash,SEG_TXT[15:8]);
Hex2Seg HTS2(Hexs[23:20],LES[5],points[5],flash,SEG_TXT[23:16]);
Hex2Seg HTS3(Hexs[19:16],LES[4],points[4],flash,SEG_TXT[31:24]);
Hex2Seg HTS4(Hexs[15:12],LES[3],points[3],flash,SEG_TXT[39:32]);
Hex2Seg HTS5(Hexs[11:8],LES[2],points[2],flash,SEG_TXT[47:40]);
Hex2Seg HTS6(Hexs[7:4],LES[1],points[1],flash,SEG_TXT[55:48]);
Hex2Seg HTS7(Hexs[3:0],LES[0],points[0],flash,SEG_TXT[63:56]);
endmodule | module HexTo8SEG(input [31:0] Hexs,
input [7:0] points,
input [7:0] LES,
input flash,
output [63:0] SEG_TXT
); |
Hex2Seg HTS0(Hexs[31:28],LES[7],points[7],flash,SEG_TXT[7:0]);
Hex2Seg HTS1(Hexs[27:24],LES[6],points[6],flash,SEG_TXT[15:8]);
Hex2Seg HTS2(Hexs[23:20],LES[5],points[5],flash,SEG_TXT[23:16]);
Hex2Seg HTS3(Hexs[19:16],LES[4],points[4],flash,SEG_TXT[31:24]);
Hex2Seg HTS4(Hexs[15:12],LES[3],points[3],flash,SEG_TXT[39:32]);
Hex2Seg HTS5(Hexs[11:8],LES[2],points[2],flash,SEG_TXT[47:40]);
Hex2Seg HTS6(Hexs[7:4],LES[1],points[1],flash,SEG_TXT[55:48]);
Hex2Seg HTS7(Hexs[3:0],LES[0],points[0],flash,SEG_TXT[63:56]);
endmodule | 0 |
2,862 | data/full_repos/permissive/101423580/v/LED_P2S_IO.v | 101,423,580 | LED_P2S_IO.v | v | 36 | 83 | [] | [] | [] | [(21, 35)] | null | data/verilator_xmls/6092b1fe-2738-4c97-9067-3ee94cfdc106.xml | null | 356 | module | module LED_P2S(input wire clk,
input wire rst,
input wire Serial,
input wire[DATA_BITS-1:0] P_Data,
output reg s_clk,
output wire s_clrn,
output wire sout,
output reg EN
);
parameter
DATA_BITS = 16,
DATA_COUNT_BITS = 4;
endmodule | module LED_P2S(input wire clk,
input wire rst,
input wire Serial,
input wire[DATA_BITS-1:0] P_Data,
output reg s_clk,
output wire s_clrn,
output wire sout,
output reg EN
); |
parameter
DATA_BITS = 16,
DATA_COUNT_BITS = 4;
endmodule | 0 |
2,863 | data/full_repos/permissive/101423580/v/Multi_8CH32.v | 101,423,580 | Multi_8CH32.v | v | 97 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xca in position 1108: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101423580/v/Multi_8CH32.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Multi_8CH32\n reg[7:0] cpu_blink = 8\'b11111111, cpu_point = 4\'b00000000;\n ^~~~~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101423580/v/Multi_8CH32.v:44: Cannot find file containing module: \'MUX8T1_32\'\n MUX8T1_32 MUX1_DispData( .I0(disp_data),\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MUX8T1_32\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MUX8T1_32.v\n data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/MUX8T1_32.sv\n MUX8T1_32\n MUX8T1_32.v\n MUX8T1_32.sv\n obj_dir/MUX8T1_32\n obj_dir/MUX8T1_32.v\n obj_dir/MUX8T1_32.sv\n%Error: data/full_repos/permissive/101423580/v/Multi_8CH32.v:58: Cannot find file containing module: \'MUX8T1_8\'\n MUX8T1_8 MUX2_Blink ( .I0(cpu_blink),\n ^~~~~~~~\n%Error: data/full_repos/permissive/101423580/v/Multi_8CH32.v:71: Cannot find file containing module: \'MUX8T1_8\'\n MUX8T1_8 MUX3_Point ( .I0(cpu_point),\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 357 | module | module Multi_8CH32( input clk,
input rst,
input EN,
input [2:0]Test,
input [63:0]point_in,
input [63:0]LES,
input [31:0] Data0,
input [31:0] Test_data1,
input [31:0] Test_data2,
input [31:0] Test_data3,
input [31:0] Test_data4,
input [31:0] Test_data5,
input [31:0] Test_data6,
input [31:0] Test_data7,
output [7:0] point_out,
output [7:0] blink_out,
output [31:0]Disp_num
);
reg[31:0] disp_data = 32'hAA5555AA;
reg[7:0] cpu_blink = 8'b11111111, cpu_point = 4'b00000000;
MUX8T1_32 MUX1_DispData( .I0(disp_data),
.I1(Test_data1),
.I2(Test_data2),
.I3(Test_data3),
.I4(Test_data4),
.I5(Test_data5),
.I6(Test_data6),
.I7(Test_daya7),
.S(Test),
.O(Disp_num)
);
MUX8T1_8 MUX2_Blink ( .I0(cpu_blink),
.I1(LES[15:8]),
.I2(LES[23:16]),
.I3(LES[31:24]),
.I4(LES[39:32]),
.I5(LES[47:40]),
.I6(LES[55:48]),
.I7(LES[63:56]),
.S(Test),
.O(LE_out)
);
MUX8T1_8 MUX3_Point ( .I0(cpu_point),
.I1(point_in[15:8]),
.I2(point_in[23:16]),
.I3(point_in[31:24]),
.I4(point_in[39:32]),
.I5(point_in[47:40]),
.I6(point_in[55:48]),
.I7(point_in[63:56]),
.S(Test),
.O(point_out)
);
always@(posedge clk)begin
if(EN) begin
disp_data <= Data0;
cpu_blink <= LES[7:0];
cpu_point <= point_in[7:0];
end
else begin
disp_data <= disp_data;
cpu_blink <= cpu_blink;
cpu_point <= cpu_point;
end
end
endmodule | module Multi_8CH32( input clk,
input rst,
input EN,
input [2:0]Test,
input [63:0]point_in,
input [63:0]LES,
input [31:0] Data0,
input [31:0] Test_data1,
input [31:0] Test_data2,
input [31:0] Test_data3,
input [31:0] Test_data4,
input [31:0] Test_data5,
input [31:0] Test_data6,
input [31:0] Test_data7,
output [7:0] point_out,
output [7:0] blink_out,
output [31:0]Disp_num
); |
reg[31:0] disp_data = 32'hAA5555AA;
reg[7:0] cpu_blink = 8'b11111111, cpu_point = 4'b00000000;
MUX8T1_32 MUX1_DispData( .I0(disp_data),
.I1(Test_data1),
.I2(Test_data2),
.I3(Test_data3),
.I4(Test_data4),
.I5(Test_data5),
.I6(Test_data6),
.I7(Test_daya7),
.S(Test),
.O(Disp_num)
);
MUX8T1_8 MUX2_Blink ( .I0(cpu_blink),
.I1(LES[15:8]),
.I2(LES[23:16]),
.I3(LES[31:24]),
.I4(LES[39:32]),
.I5(LES[47:40]),
.I6(LES[55:48]),
.I7(LES[63:56]),
.S(Test),
.O(LE_out)
);
MUX8T1_8 MUX3_Point ( .I0(cpu_point),
.I1(point_in[15:8]),
.I2(point_in[23:16]),
.I3(point_in[31:24]),
.I4(point_in[39:32]),
.I5(point_in[47:40]),
.I6(point_in[55:48]),
.I7(point_in[63:56]),
.S(Test),
.O(point_out)
);
always@(posedge clk)begin
if(EN) begin
disp_data <= Data0;
cpu_blink <= LES[7:0];
cpu_point <= point_in[7:0];
end
else begin
disp_data <= disp_data;
cpu_blink <= cpu_blink;
cpu_point <= cpu_point;
end
end
endmodule | 0 |
2,864 | data/full_repos/permissive/101423580/v/MUX16T1_12.v | 101,423,580 | MUX16T1_12.v | v | 63 | 83 | [] | [] | [] | [(21, 62)] | null | data/verilator_xmls/12687aeb-1d32-4c8b-986c-bd6e760d0a9b.xml | null | 358 | module | module MUX16T1_12( input [3:0]S,
input [11:0]D1,
input [11:0]D2,
input [11:0]D3,
input [11:0]D4,
input [11:0]D5,
input [11:0]D6,
input [11:0]D7,
input [11:0]D8,
input [11:0]D9,
input [11:0]D10,
input [11:0]D11,
input [11:0]D12,
input [11:0]D13,
input [11:0]D14,
input [11:0]D15,
output reg [11:0]Dout
);
always @ * begin
case(S)
4'h0: Dout <= 12'hfff;
4'h1: Dout <= D1;
4'h2: Dout <= D2;
4'h3: Dout <= D3;
4'h4: Dout <= D4;
4'h5: Dout <= D5;
4'h6: Dout <= D6;
4'h7: Dout <= D7;
4'h8: Dout <= D8;
4'h9: Dout <= D9;
4'hA: Dout <= D10;
4'hB: Dout <= D11;
4'hC: Dout <= D12;
4'hD: Dout <= D13;
4'hE: Dout <= D14;
4'hF: Dout <= D15;
default:;
endcase
end
endmodule | module MUX16T1_12( input [3:0]S,
input [11:0]D1,
input [11:0]D2,
input [11:0]D3,
input [11:0]D4,
input [11:0]D5,
input [11:0]D6,
input [11:0]D7,
input [11:0]D8,
input [11:0]D9,
input [11:0]D10,
input [11:0]D11,
input [11:0]D12,
input [11:0]D13,
input [11:0]D14,
input [11:0]D15,
output reg [11:0]Dout
); |
always @ * begin
case(S)
4'h0: Dout <= 12'hfff;
4'h1: Dout <= D1;
4'h2: Dout <= D2;
4'h3: Dout <= D3;
4'h4: Dout <= D4;
4'h5: Dout <= D5;
4'h6: Dout <= D6;
4'h7: Dout <= D7;
4'h8: Dout <= D8;
4'h9: Dout <= D9;
4'hA: Dout <= D10;
4'hB: Dout <= D11;
4'hC: Dout <= D12;
4'hD: Dout <= D13;
4'hE: Dout <= D14;
4'hF: Dout <= D15;
default:;
endcase
end
endmodule | 0 |
2,865 | data/full_repos/permissive/101423580/v/MUX2T1_4.v | 101,423,580 | MUX2T1_4.v | v | 37 | 83 | [] | [] | [] | [(21, 36)] | null | data/verilator_xmls/632f423a-5947-4e2d-8f72-f308a0ff2478.xml | null | 360 | module | module MUX2T1_4( input S,
input [3:0]D0,
input [3:0]D1,
output reg [3:0]Dout
);
always @ * begin
case(S)
1'd0: Dout <= D0;
1'd1: Dout <= D1;
default: ;
endcase
end
endmodule | module MUX2T1_4( input S,
input [3:0]D0,
input [3:0]D1,
output reg [3:0]Dout
); |
always @ * begin
case(S)
1'd0: Dout <= D0;
1'd1: Dout <= D1;
default: ;
endcase
end
endmodule | 0 |
2,866 | data/full_repos/permissive/101423580/v/MUX8T1_5.v | 101,423,580 | MUX8T1_5.v | v | 43 | 83 | [] | [] | [] | [(21, 42)] | null | data/verilator_xmls/a4e802a2-4605-4225-beb1-7bff41489e6f.xml | null | 363 | module | module MUX8T1_5( input [2:0]S,
input [4:0]D0,
input [4:0]D1,
input [4:0]D2,
input [4:0]D3,
input [4:0]D4,
input [4:0]D5,
output reg [4:0]Dout
);
always @ * begin
case(S)
3'd0: Dout <= D0;
3'd1: Dout <= D1;
3'd2: Dout <= D2;
3'd3: Dout <= D3;
3'd4: Dout <= D4;
3'd5: Dout <= D5;
default: ;
endcase
end
endmodule | module MUX8T1_5( input [2:0]S,
input [4:0]D0,
input [4:0]D1,
input [4:0]D2,
input [4:0]D3,
input [4:0]D4,
input [4:0]D5,
output reg [4:0]Dout
); |
always @ * begin
case(S)
3'd0: Dout <= D0;
3'd1: Dout <= D1;
3'd2: Dout <= D2;
3'd3: Dout <= D3;
3'd4: Dout <= D4;
3'd5: Dout <= D5;
default: ;
endcase
end
endmodule | 0 |
2,867 | data/full_repos/permissive/101423580/v/P2S_IO.v | 101,423,580 | P2S_IO.v | v | 35 | 83 | [] | [] | [] | [(21, 34)] | null | data/verilator_xmls/bea80fb3-6f12-45ca-a4e1-6ecfff5c0036.xml | null | 364 | module | module P2S(input wire clk,
input wire rst,
input wire Serial,
input wire[DATA_BITS-1:0] P_Data,
output reg s_clk,
output wire s_clrn,
output wire sout,
output reg EN
);
parameter
DATA_BITS = 64,
DATA_COUNT_BITS = 6;
endmodule | module P2S(input wire clk,
input wire rst,
input wire Serial,
input wire[DATA_BITS-1:0] P_Data,
output reg s_clk,
output wire s_clrn,
output wire sout,
output reg EN
); |
parameter
DATA_BITS = 64,
DATA_COUNT_BITS = 6;
endmodule | 0 |
2,868 | data/full_repos/permissive/101423580/v/PIO.v | 101,423,580 | PIO.v | v | 39 | 83 | [] | [] | [] | [(21, 38)] | null | data/verilator_xmls/ff8cd673-fcb4-42a9-a343-49581b5b97d8.xml | null | 365 | module | module PIO( input wire clk,
input wire rst,
input wire EN,
input wire[31:0] PData_in,
output wire[7:0] LED,
output reg[31:0] GPIOf0
);
assign LED = ~GPIOf0[7:0];
always @ (negedge clk or posedge rst) begin
if(rst) GPIOf0 <= 32'h00000000;
else if(EN) GPIOf0 <= PData_in;
else GPIOf0 <= GPIOf0;
end
endmodule | module PIO( input wire clk,
input wire rst,
input wire EN,
input wire[31:0] PData_in,
output wire[7:0] LED,
output reg[31:0] GPIOf0
); |
assign LED = ~GPIOf0[7:0];
always @ (negedge clk or posedge rst) begin
if(rst) GPIOf0 <= 32'h00000000;
else if(EN) GPIOf0 <= PData_in;
else GPIOf0 <= GPIOf0;
end
endmodule | 0 |
2,869 | data/full_repos/permissive/101423580/v/SAnti_jitter_IO.v | 101,423,580 | SAnti_jitter_IO.v | v | 37 | 83 | [] | [] | [] | [(21, 36)] | null | data/verilator_xmls/a6269ac6-5319-4157-84c0-aeab91cce098.xml | null | 366 | module | module SAnti_jitter(input wire clk,
input wire RSTN,
input wire readn,
input wire [3:0]Key_y,
output reg[4:0] Key_x,
input wire[15:0]SW,
output reg[4:0] Key_out,
output reg Key_ready,
output reg[3:0] pulse_out,
output reg[3:0] BTN_OK,
output reg[15:0]SW_OK,
output reg CR,
output reg rst
);
endmodule | module SAnti_jitter(input wire clk,
input wire RSTN,
input wire readn,
input wire [3:0]Key_y,
output reg[4:0] Key_x,
input wire[15:0]SW,
output reg[4:0] Key_out,
output reg Key_ready,
output reg[3:0] pulse_out,
output reg[3:0] BTN_OK,
output reg[15:0]SW_OK,
output reg CR,
output reg rst
); |
endmodule | 0 |
2,870 | data/full_repos/permissive/101423580/v/SEnter_2_32_IO.v | 101,423,580 | SEnter_2_32_IO.v | v | 34 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb6 in position 541: invalid start byte | data/verilator_xmls/b193a4ee-3758-459d-942c-4a1b8201ed96.xml | null | 367 | module | module SEnter_2_32(input clk,
input[2:0] BTN,
input [4:0] Ctrl,
input D_ready,
input [4:0]Din,
output reg readn,
output reg[31:0]Ai=32'h87654321,
output reg[31:0]Bi=32'h12345678,
output reg [7:0 ]blink
);
endmodule | module SEnter_2_32(input clk,
input[2:0] BTN,
input [4:0] Ctrl,
input D_ready,
input [4:0]Din,
output reg readn,
output reg[31:0]Ai=32'h87654321,
output reg[31:0]Bi=32'h12345678,
output reg [7:0 ]blink
); |
endmodule | 0 |
2,871 | data/full_repos/permissive/101423580/v/vga.v | 101,423,580 | vga.v | v | 73 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd0 in position 1013: invalid continuation byte | data/verilator_xmls/4d629a6c-7840-4ca7-9fce-10e2d0359200.xml | null | 368 | module | module vga( input clk,
input rst,
input [11:0]Din,
output reg [8:0]row,
output reg [9:0]col,
output reg rdn,
output reg [3:0]R, G, B,
output reg HS, VS
);
reg [9:0] h_count;
always @ (posedge clk) begin
if (rst) h_count <= 10'h0;
else if (h_count == 10'd799)
h_count <= 10'h0;
else h_count <= h_count + 10'h1;
end
reg [9:0] v_count;
always @ (posedge clk or posedge rst)begin
if (rst) v_count <= 10'h0;
else if (h_count == 10'd799) begin
if (v_count == 10'd524) v_count <= 10'h0;
else v_count <= v_count + 10'h1;
end
end
wire [9:0] row_addr = v_count - 10'd35;
wire [9:0] col_addr = h_count - 10'd143;
wire h_sync = (h_count > 10'd95);
wire v_sync = (v_count > 10'd1);
wire read = (h_count > 10'd142) &&
(h_count < 10'd783) &&
(v_count > 10'd34) &&
(v_count < 10'd515);
always @(posedge clk) begin
row <= row_addr[8:0];
col <= col_addr;
rdn <= ~read;
HS <= h_sync;
VS <= v_sync;
R <= rdn ? 4'h0 : Din[3:0];
G <= rdn ? 4'h0 : Din[7:4];
B <= rdn ? 4'h0 : Din[11:8];
end
endmodule | module vga( input clk,
input rst,
input [11:0]Din,
output reg [8:0]row,
output reg [9:0]col,
output reg rdn,
output reg [3:0]R, G, B,
output reg HS, VS
); |
reg [9:0] h_count;
always @ (posedge clk) begin
if (rst) h_count <= 10'h0;
else if (h_count == 10'd799)
h_count <= 10'h0;
else h_count <= h_count + 10'h1;
end
reg [9:0] v_count;
always @ (posedge clk or posedge rst)begin
if (rst) v_count <= 10'h0;
else if (h_count == 10'd799) begin
if (v_count == 10'd524) v_count <= 10'h0;
else v_count <= v_count + 10'h1;
end
end
wire [9:0] row_addr = v_count - 10'd35;
wire [9:0] col_addr = h_count - 10'd143;
wire h_sync = (h_count > 10'd95);
wire v_sync = (v_count > 10'd1);
wire read = (h_count > 10'd142) &&
(h_count < 10'd783) &&
(v_count > 10'd34) &&
(v_count < 10'd515);
always @(posedge clk) begin
row <= row_addr[8:0];
col <= col_addr;
rdn <= ~read;
HS <= h_sync;
VS <= v_sync;
R <= rdn ? 4'h0 : Din[3:0];
G <= rdn ? 4'h0 : Din[7:4];
B <= rdn ? 4'h0 : Din[11:8];
end
endmodule | 0 |
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