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2,872 | data/full_repos/permissive/101423580/v/vgademo.v | 101,423,580 | vgademo.v | v | 79 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd0 in position 758: invalid continuation byte | null | 1: b"%Error: data/full_repos/permissive/101423580/v/vgademo.v:37: Duplicate declaration of signal: 'vga_data'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [11:0] vga_data;\n ^~~~~~~~\n data/full_repos/permissive/101423580/v/vgademo.v:29: ... Location of original declaration\n output [11:0]vga_data,\n ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 369 | module | module vgademo( input clk,
input rst,
input keyReady,
input [4:0]keyCode,
input [15:0]SW,
input [8:0]row,
input [9:0]col,
output [11:0]vga_data,
output [31:0]Ccircle,
output reg rdn
);
reg [9:0] x;
reg [8:0] y;
reg [11:0] vga_data;
wire [19:0] x_sqr, y_sqr, r_sqr;
reg wasReady;
reg [9:0] radius = 10'd100;
assign Ccircle = {7'b0, x, 8'b0, y};
always @(posedge clk) begin
if(rst) begin
x <= 10'd320;
y <= 9'd240;
radius <= 10'd100;
end
else begin
wasReady <= keyReady;
rdn <= 0;
if(!wasReady && keyReady) begin
rdn <= 1;
case(keyCode)
5'hc: radius <= radius - 10'd5;
5'he: radius <= radius + 10'd5;
5'h8: x <= x - 10'd20;
5'ha: x <= x + 10'd20;
5'h5: y <= y - 9'd20;
5'hd: y <= y + 9'd20;
default : ;
endcase
end
end
end
assign x_sqr = (x - col) * (x - col);
assign y_sqr = (y - row) * (y - row);
assign r_sqr = radius * radius;
always @ (*) begin
if ((x_sqr + y_sqr < r_sqr))
vga_data <= SW[12:1] ;
else if(SW[14]) vga_data <= {row[8:0], col[9:7]};
else vga_data <= 12'hfff;
end
endmodule | module vgademo( input clk,
input rst,
input keyReady,
input [4:0]keyCode,
input [15:0]SW,
input [8:0]row,
input [9:0]col,
output [11:0]vga_data,
output [31:0]Ccircle,
output reg rdn
); |
reg [9:0] x;
reg [8:0] y;
reg [11:0] vga_data;
wire [19:0] x_sqr, y_sqr, r_sqr;
reg wasReady;
reg [9:0] radius = 10'd100;
assign Ccircle = {7'b0, x, 8'b0, y};
always @(posedge clk) begin
if(rst) begin
x <= 10'd320;
y <= 9'd240;
radius <= 10'd100;
end
else begin
wasReady <= keyReady;
rdn <= 0;
if(!wasReady && keyReady) begin
rdn <= 1;
case(keyCode)
5'hc: radius <= radius - 10'd5;
5'he: radius <= radius + 10'd5;
5'h8: x <= x - 10'd20;
5'ha: x <= x + 10'd20;
5'h5: y <= y - 9'd20;
5'hd: y <= y + 9'd20;
default : ;
endcase
end
end
end
assign x_sqr = (x - col) * (x - col);
assign y_sqr = (y - row) * (y - row);
assign r_sqr = radius * radius;
always @ (*) begin
if ((x_sqr + y_sqr < r_sqr))
vga_data <= SW[12:1] ;
else if(SW[14]) vga_data <= {row[8:0], col[9:7]};
else vga_data <= 12'hfff;
end
endmodule | 0 |
2,875 | data/full_repos/permissive/101427397/v/Counter_3_IO.v | 101,427,397 | Counter_3_IO.v | v | 125 | 115 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f73cd7ef-cd1e-4806-9997-53d86e899230.xml | null | 376 | module | module Counter_x(input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch,
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
reg [32:0] counter0,counter1,counter2;
reg [31:0] counter0_Lock,counter1_Lock,counter2_Lock;
reg [23:0] counter_Ctrl;
reg sq0,sq1,sq2,M0,M1,M2,clr0,clr1,clr2;
always @ (posedge clk or posedge rst) begin
if (rst )
begin counter0_Lock <=0;counter1_Lock <=0;counter2_Lock <=0;counter_Ctrl<=0; end
else
if (counter_we) begin
case(counter_ch)
2'h0: begin counter0_Lock <= counter_val; M0<=1; end
2'h1: begin counter1_Lock <= counter_val; M1<=1; end
2'h2: begin counter2_Lock <= counter_val; M2<=1; end
2'h3: begin counter_Ctrl <= counter_val[23:0]; end
endcase
end
else begin counter0_Lock <=counter0_Lock;
counter1_Lock <=counter1_Lock;
counter2_Lock <=counter2_Lock;
counter_Ctrl<=counter_Ctrl;
if(clr0) M0<=0;
if(clr1) M1<=0;
if(clr2) M2<=0;
end
end
always @ (posedge clk0 or posedge rst) begin
if (rst )
begin counter0<=0; sq0<=0; end
else
case(counter_Ctrl[2:1])
2'b00: begin if (M0) begin counter0 <= {1'b0,counter0_Lock}; clr0<=1; end
else if (counter0[32]==0)begin counter0 <= counter0 - 1'b1; clr0<=0; end
end
2'b01: begin if (counter0[32]==0) counter0 <= counter0 - 1'b1; else counter0 <={1'b0,counter0_Lock}; end
2'b10: begin sq0<=counter0[32];
if (sq0!=counter0[32]) counter0[31:0] <= {1'b0,counter0_Lock[31:1]}; else counter0 <= counter0 - 1'b1;end
2'b11: counter0 <= counter0 - 1'b1;
endcase
end
assign counter0_OUT=counter0[32];
assign counter1_OUT=counter1[32];
assign counter2_OUT=counter2[32];
assign counter_out = counter0[31:0];
endmodule | module Counter_x(input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch,
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
); |
reg [32:0] counter0,counter1,counter2;
reg [31:0] counter0_Lock,counter1_Lock,counter2_Lock;
reg [23:0] counter_Ctrl;
reg sq0,sq1,sq2,M0,M1,M2,clr0,clr1,clr2;
always @ (posedge clk or posedge rst) begin
if (rst )
begin counter0_Lock <=0;counter1_Lock <=0;counter2_Lock <=0;counter_Ctrl<=0; end
else
if (counter_we) begin
case(counter_ch)
2'h0: begin counter0_Lock <= counter_val; M0<=1; end
2'h1: begin counter1_Lock <= counter_val; M1<=1; end
2'h2: begin counter2_Lock <= counter_val; M2<=1; end
2'h3: begin counter_Ctrl <= counter_val[23:0]; end
endcase
end
else begin counter0_Lock <=counter0_Lock;
counter1_Lock <=counter1_Lock;
counter2_Lock <=counter2_Lock;
counter_Ctrl<=counter_Ctrl;
if(clr0) M0<=0;
if(clr1) M1<=0;
if(clr2) M2<=0;
end
end
always @ (posedge clk0 or posedge rst) begin
if (rst )
begin counter0<=0; sq0<=0; end
else
case(counter_Ctrl[2:1])
2'b00: begin if (M0) begin counter0 <= {1'b0,counter0_Lock}; clr0<=1; end
else if (counter0[32]==0)begin counter0 <= counter0 - 1'b1; clr0<=0; end
end
2'b01: begin if (counter0[32]==0) counter0 <= counter0 - 1'b1; else counter0 <={1'b0,counter0_Lock}; end
2'b10: begin sq0<=counter0[32];
if (sq0!=counter0[32]) counter0[31:0] <= {1'b0,counter0_Lock[31:1]}; else counter0 <= counter0 - 1'b1;end
2'b11: counter0 <= counter0 - 1'b1;
endcase
end
assign counter0_OUT=counter0[32];
assign counter1_OUT=counter1[32];
assign counter2_OUT=counter2[32];
assign counter_out = counter0[31:0];
endmodule | 3 |
2,878 | data/full_repos/permissive/101427397/v/MUX16T1_32.v | 101,427,397 | MUX16T1_32.v | v | 61 | 83 | [] | [] | [] | [(21, 60)] | null | data/verilator_xmls/7275dc4f-6e34-4ca9-b91d-f3b776f436d3.xml | null | 380 | module | module MUX16T1_32(input [3:0]s,
input [31:0]I0,
input [31:0]I1,
input [31:0]I2,
input [31:0]I3,
input [31:0]I4,
input [31:0]I5,
input [31:0]I6,
input [31:0]I7,
input [31:0]I8,
input [31:0]I9,
input [31:0]I10,
input [31:0]I11,
input [31:0]I12,
input [31:0]I13,
input [31:0]I14,
input [31:0]I15,
output reg [31:0]o
);
always @ *
case(s)
4'd0: o = I0;
4'd1: o = I1;
4'd2: o = I2;
4'd3: o = I3;
4'd4: o = I4;
4'd5: o = I5;
4'd6: o = I6;
4'd7: o = I7;
4'd8: o = I8;
4'd9: o = I9;
4'd10: o = I10;
4'd11: o = I11;
4'd12: o = I12;
4'd13: o = I13;
4'd14: o = I14;
4'd15: o = I15;
endcase
endmodule | module MUX16T1_32(input [3:0]s,
input [31:0]I0,
input [31:0]I1,
input [31:0]I2,
input [31:0]I3,
input [31:0]I4,
input [31:0]I5,
input [31:0]I6,
input [31:0]I7,
input [31:0]I8,
input [31:0]I9,
input [31:0]I10,
input [31:0]I11,
input [31:0]I12,
input [31:0]I13,
input [31:0]I14,
input [31:0]I15,
output reg [31:0]o
); |
always @ *
case(s)
4'd0: o = I0;
4'd1: o = I1;
4'd2: o = I2;
4'd3: o = I3;
4'd4: o = I4;
4'd5: o = I5;
4'd6: o = I6;
4'd7: o = I7;
4'd8: o = I8;
4'd9: o = I9;
4'd10: o = I10;
4'd11: o = I11;
4'd12: o = I12;
4'd13: o = I13;
4'd14: o = I14;
4'd15: o = I15;
endcase
endmodule | 3 |
2,880 | data/full_repos/permissive/101427397/v/MUX4T1_5.v | 101,427,397 | MUX4T1_5.v | v | 37 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 662: invalid start byte | data/verilator_xmls/e4d917fd-edf7-468c-bd3c-ad81f9ab5e66.xml | null | 383 | module | module MUX4T1_5(input [1:0]s,
input [4:0]I0,
input [4:0]I1,
input [4:0]I2,
input [4:0]I3,
output reg[4:0]o
);
always @ *
case(s)
2'd0: o <= I0;
2'd1: o <= I1;
2'd2: o <= I2;
2'd3: o <= I3;
endcase
endmodule | module MUX4T1_5(input [1:0]s,
input [4:0]I0,
input [4:0]I1,
input [4:0]I2,
input [4:0]I3,
output reg[4:0]o
); |
always @ *
case(s)
2'd0: o <= I0;
2'd1: o <= I1;
2'd2: o <= I2;
2'd3: o <= I3;
endcase
endmodule | 3 |
2,886 | data/full_repos/permissive/101427397/v/PIO_IO.v | 101,427,397 | PIO_IO.v | v | 31 | 83 | [] | [] | [] | [(21, 30)] | null | data/verilator_xmls/0a754a2e-00c5-4150-bcc9-77ebad3c5bb5.xml | null | 390 | module | module PIO(input wire clk,
input wire rst,
input wire EN,
input wire[31:0] PData_in,
output reg[1:0] counter_set,
output[7:0] LED_out,
output reg[21:0]GPIOf0
);
endmodule | module PIO(input wire clk,
input wire rst,
input wire EN,
input wire[31:0] PData_in,
output reg[1:0] counter_set,
output[7:0] LED_out,
output reg[21:0]GPIOf0
); |
endmodule | 3 |
2,888 | data/full_repos/permissive/101427397/v/Seg7_Dev_IO.v | 101,427,397 | Seg7_Dev_IO.v | v | 32 | 83 | [] | [] | [] | [(21, 31)] | null | data/verilator_xmls/ae838eed-af36-4f2c-9bf2-570956c9eb73.xml | null | 393 | module | module Seg7_Dev(input[2:0] Scan,
input SW0,
input flash,
input[31:0]Hexs,
input[7:0]point,
input[7:0]LES,
output[7:0]SEGMENT,
output[3:0]AN
);
endmodule | module Seg7_Dev(input[2:0] Scan,
input SW0,
input flash,
input[31:0]Hexs,
input[7:0]point,
input[7:0]LES,
output[7:0]SEGMENT,
output[3:0]AN
); |
endmodule | 3 |
2,890 | data/full_repos/permissive/101427397/v/signExt_16T32.v | 101,427,397 | signExt_16T32.v | v | 26 | 83 | [] | [] | [] | [(28, 106)] | null | data/verilator_xmls/76cf9838-2d93-4cd3-8c66-d77423beb6b2.xml | null | 395 | module | module signExt_16T32( input [15:0] i,
output [31:0] o
);
assign o = i[15] ? {16'hFFFF,i[15:0]} : {16'h0000,i[15:0]};
endmodule | module signExt_16T32( input [15:0] i,
output [31:0] o
); |
assign o = i[15] ? {16'hFFFF,i[15:0]} : {16'h0000,i[15:0]};
endmodule | 3 |
2,891 | data/full_repos/permissive/101427397/v/SPIO_IO.v | 101,427,397 | SPIO_IO.v | v | 36 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 514: invalid continuation byte | data/verilator_xmls/228ba020-8083-4295-9915-b354fbcd566c.xml | null | 397 | module | module SPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output reg[1:0] counter_set,
output [15:0] LED_out,
output wire led_clk,
output wire led_sout,
output wire led_clrn,
output wire LED_PEN,
output reg[13:0] GPIOf0
);
endmodule | module SPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output reg[1:0] counter_set,
output [15:0] LED_out,
output wire led_clk,
output wire led_sout,
output wire led_clrn,
output wire LED_PEN,
output reg[13:0] GPIOf0
); |
endmodule | 3 |
2,892 | data/full_repos/permissive/101427397/v/SSeg7_Dev_IO.v | 101,427,397 | SSeg7_Dev_IO.v | v | 36 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 516: invalid continuation byte | data/verilator_xmls/3398ffe9-bbac-4572-8055-c2b09c1d63a5.xml | null | 399 | module | module SSeg7_Dev(input clk,
input rst,
input Start,
input SW0,
input flash,
input[31:0]Hexs,
input[7:0]point,
input[7:0]LES,
output seg_clk,
output seg_sout,
output SEG_PEN,
output seg_clrn
);
endmodule | module SSeg7_Dev(input clk,
input rst,
input Start,
input SW0,
input flash,
input[31:0]Hexs,
input[7:0]point,
input[7:0]LES,
output seg_clk,
output seg_sout,
output SEG_PEN,
output seg_clrn
); |
endmodule | 3 |
2,893 | data/full_repos/permissive/101427397/v/zeroExt_16T32.v | 101,427,397 | zeroExt_16T32.v | v | 26 | 83 | [] | [] | [] | [(21, 25)] | null | data/verilator_xmls/d88060c6-69fd-4d03-bf10-9e2135be0c92.xml | null | 401 | module | module zeroExt_16T32( input [15:0] i,
output[31:0] o
);
assign o = {16'h0000,i[15:0]};
endmodule | module zeroExt_16T32( input [15:0] i,
output[31:0] o
); |
assign o = {16'h0000,i[15:0]};
endmodule | 3 |
2,894 | data/full_repos/permissive/101427841/test_v/micro_test1.v | 101,427,841 | micro_test1.v | v | 180 | 118 | [] | [] | [] | [(25, 178)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:75: Unsupported: Ignoring delay on this delayed statement.\n #90;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:80: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:84: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:88: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:92: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:96: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:100: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:104: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:108: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:112: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:120: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:124: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:128: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:132: Unsupported: Ignoring delay on this delayed statement.\n #160; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:135: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:143: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:151: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:154: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:158: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:160: Unsupported: Ignoring delay on this delayed statement.\n #150;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:164: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:168: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/101427841/test_v/micro_test1.v:46: Cannot find file containing module: \'MCPU_v1\'\n MCPU_v1 uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1\n data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1.v\n data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1.sv\n MCPU_v1\n MCPU_v1.v\n MCPU_v1.sv\n obj_dir/MCPU_v1\n obj_dir/MCPU_v1.v\n obj_dir/MCPU_v1.sv\n%Error: Exiting due to 1 error(s), 25 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 402 | module | module micro_test1;
reg clk;
reg reset;
reg [31:0] Data_in;
reg [4:0] test_reg_index;
reg INT;
reg MIO_ready;
wire mem_w;
wire [31:0] Addr_out;
wire [31:0] Data_out;
wire [4:0] state;
wire [31:0] PC_out;
wire [31:0] inst_out;
wire [31:0] test_reg_result;
wire CPU_MIO;
MCPU_v1 uut (
.clk(clk),
.reset(reset),
.mem_w(mem_w),
.Addr_out(Addr_out),
.Data_out(Data_out),
.Data_in(Data_in),
.state(state),
.PC_out(PC_out),
.inst_out(inst_out),
.test_reg_index(test_reg_index),
.test_reg_result(test_reg_result),
.INT(INT),
.MIO_ready(MIO_ready),
.CPU_MIO(CPU_MIO)
);
initial begin
clk = 0;
reset = 0;
Data_in = 0;
test_reg_index = 0;
INT = 0;
MIO_ready = 0;
#10;
reset = 1;
#90;
reset = 0;
Data_in = 32'h20210001;
test_reg_index = 1;
#160;
Data_in = 32'h00211020;
test_reg_index = 2;
#160;
Data_in = 32'h34630003;
test_reg_index = 3;
#160;
Data_in = 32'h00622022;
test_reg_index = 4;
#160;
Data_in = 32'h00432827;
test_reg_index = 5;
#160;
Data_in = 32'h00433026;
test_reg_index = 6;
#160;
Data_in = 32'h0043382A;
test_reg_index = 7;
#160;
Data_in = 32'h28E8FFFF;
test_reg_index = 8;
#160;
Data_in = 32'h00014FC0;
test_reg_index = 9;
#160;
Data_in = 32'h000957C2;
test_reg_index = 10;
#160;
Data_in = 32'h01405825;
test_reg_index = 11;
#160;
Data_in = 32'h316CFFFF;
test_reg_index = 12;
#160;
Data_in = 32'h3C0DFFFF;
test_reg_index = 13;
#160;
Data_in = 32'h39AE0000;
test_reg_index = 14;
#160;
Data_in = 32'h11C0FFF1;
#120;
Data_in = 32'h1400FFF0;
#120;
Data_in = 32'h08000011;
#120;
Data_in = 32'hAC0E0008;
#160;
Data_in = 32'h8C0F0008;
test_reg_index = 15;
#50;
Data_in = 32'h12345678;
#150;
Data_in = 32'h0C000016;
test_reg_index = 31;
#120;
Data_in = 32'h01E08009;
test_reg_index = 16;
#120;
end
always @ * begin
#20;
clk <= ~clk;
end
endmodule | module micro_test1; |
reg clk;
reg reset;
reg [31:0] Data_in;
reg [4:0] test_reg_index;
reg INT;
reg MIO_ready;
wire mem_w;
wire [31:0] Addr_out;
wire [31:0] Data_out;
wire [4:0] state;
wire [31:0] PC_out;
wire [31:0] inst_out;
wire [31:0] test_reg_result;
wire CPU_MIO;
MCPU_v1 uut (
.clk(clk),
.reset(reset),
.mem_w(mem_w),
.Addr_out(Addr_out),
.Data_out(Data_out),
.Data_in(Data_in),
.state(state),
.PC_out(PC_out),
.inst_out(inst_out),
.test_reg_index(test_reg_index),
.test_reg_result(test_reg_result),
.INT(INT),
.MIO_ready(MIO_ready),
.CPU_MIO(CPU_MIO)
);
initial begin
clk = 0;
reset = 0;
Data_in = 0;
test_reg_index = 0;
INT = 0;
MIO_ready = 0;
#10;
reset = 1;
#90;
reset = 0;
Data_in = 32'h20210001;
test_reg_index = 1;
#160;
Data_in = 32'h00211020;
test_reg_index = 2;
#160;
Data_in = 32'h34630003;
test_reg_index = 3;
#160;
Data_in = 32'h00622022;
test_reg_index = 4;
#160;
Data_in = 32'h00432827;
test_reg_index = 5;
#160;
Data_in = 32'h00433026;
test_reg_index = 6;
#160;
Data_in = 32'h0043382A;
test_reg_index = 7;
#160;
Data_in = 32'h28E8FFFF;
test_reg_index = 8;
#160;
Data_in = 32'h00014FC0;
test_reg_index = 9;
#160;
Data_in = 32'h000957C2;
test_reg_index = 10;
#160;
Data_in = 32'h01405825;
test_reg_index = 11;
#160;
Data_in = 32'h316CFFFF;
test_reg_index = 12;
#160;
Data_in = 32'h3C0DFFFF;
test_reg_index = 13;
#160;
Data_in = 32'h39AE0000;
test_reg_index = 14;
#160;
Data_in = 32'h11C0FFF1;
#120;
Data_in = 32'h1400FFF0;
#120;
Data_in = 32'h08000011;
#120;
Data_in = 32'hAC0E0008;
#160;
Data_in = 32'h8C0F0008;
test_reg_index = 15;
#50;
Data_in = 32'h12345678;
#150;
Data_in = 32'h0C000016;
test_reg_index = 31;
#120;
Data_in = 32'h01E08009;
test_reg_index = 16;
#120;
end
always @ * begin
#20;
clk <= ~clk;
end
endmodule | 1 |
2,898 | data/full_repos/permissive/101428364/clk_div.v | 101,428,364 | clk_div.v | v | 77 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd6 in position 701: invalid continuation byte | data/verilator_xmls/a813a316-ec82-48e5-b91e-ca89bfeb71a8.xml | null | 437 | module | module clk_div(input clk,
input rst,
input SW2,
input SW15,
input keyReady,
input [3:0] BTN_OK,
output reg[31:0]clkdiv,
output Clk_CPU,
output reg readn
);
wire auto_clk;
reg [31:0] step;
reg [4:0] counter;
reg wasReady;
always @ (posedge clk or posedge rst) begin
if (rst) clkdiv <= 0;
else clkdiv <= clkdiv + 1'b1;
end
assign auto_clk =(SW2)? clkdiv[24] : clkdiv[4];
assign Clk_CPU = (SW15) ? step[0] : auto_clk;
always @ (posedge clk or posedge rst) begin
if(rst) begin
step <= 0;
counter <= 0;
end
else begin
if(counter != 0 && clkdiv[24]) begin
step <= step + 1'b1;
counter <= counter - 1'b1;
end
else begin
wasReady <= keyReady;
readn <= 1;
if(!wasReady && keyReady) begin
readn <= 0;
if(BTN_OK[0]) counter <= 5'd2;
else if(BTN_OK[1]) counter <= 5'd4;
else if(BTN_OK[2]) counter <= 5'd10;
else if(BTN_OK[3]) counter <= 5'd20;
end
end
end
end
endmodule | module clk_div(input clk,
input rst,
input SW2,
input SW15,
input keyReady,
input [3:0] BTN_OK,
output reg[31:0]clkdiv,
output Clk_CPU,
output reg readn
); |
wire auto_clk;
reg [31:0] step;
reg [4:0] counter;
reg wasReady;
always @ (posedge clk or posedge rst) begin
if (rst) clkdiv <= 0;
else clkdiv <= clkdiv + 1'b1;
end
assign auto_clk =(SW2)? clkdiv[24] : clkdiv[4];
assign Clk_CPU = (SW15) ? step[0] : auto_clk;
always @ (posedge clk or posedge rst) begin
if(rst) begin
step <= 0;
counter <= 0;
end
else begin
if(counter != 0 && clkdiv[24]) begin
step <= step + 1'b1;
counter <= counter - 1'b1;
end
else begin
wasReady <= keyReady;
readn <= 1;
if(!wasReady && keyReady) begin
readn <= 0;
if(BTN_OK[0]) counter <= 5'd2;
else if(BTN_OK[1]) counter <= 5'd4;
else if(BTN_OK[2]) counter <= 5'd10;
else if(BTN_OK[3]) counter <= 5'd20;
end
end
end
end
endmodule | 5 |
2,900 | data/full_repos/permissive/101428364/first_decoder.v | 101,428,364 | first_decoder.v | v | 39 | 108 | [] | [] | [] | [(21, 38)] | null | data/verilator_xmls/146dd00b-1391-4365-932d-4194c1b6e6b8.xml | null | 441 | module | module first_decoder( input [5:0] opcode, func, input [31:0] inst_in,
output rtype_ALU, itype_ALU,
lw, sw, beq, bne, jal, jalr, shift, nop, j, jr
);
assign nop = (inst_in == 32'h0) ? 1 : 0;
assign rtype_ALU = (opcode == 6'b000000 && inst_in != 32'h0) ? 1 : 0;
assign itype_ALU = (opcode < 6'b010000 && opcode > 6'b000111) ? 1 : 0;
assign lw = (opcode == 6'b100011) ? 1 : 0;
assign sw = (opcode == 6'b101011) ? 1 : 0;
assign beq = (opcode == 6'b000100) ? 1 : 0;
assign bne = (opcode == 6'b000101) ? 1 : 0;
assign j = (opcode == 6'b000010) ? 1 : 0;
assign jr = (opcode == 6'b000000 && func == 6'd8) ? 1 : 0;
assign jal = (opcode == 6'b000011) ? 1 : 0;
assign jalr = (opcode == 6'b000000 && func == 6'd9) ? 1'b1 : 1'b0;
assign shift = (inst_in != 32'h0 && opcode == 6'b000000 && (func == 6'd2 || func == 6'd0)) ? 1'b1 : 1'b0;
endmodule | module first_decoder( input [5:0] opcode, func, input [31:0] inst_in,
output rtype_ALU, itype_ALU,
lw, sw, beq, bne, jal, jalr, shift, nop, j, jr
); |
assign nop = (inst_in == 32'h0) ? 1 : 0;
assign rtype_ALU = (opcode == 6'b000000 && inst_in != 32'h0) ? 1 : 0;
assign itype_ALU = (opcode < 6'b010000 && opcode > 6'b000111) ? 1 : 0;
assign lw = (opcode == 6'b100011) ? 1 : 0;
assign sw = (opcode == 6'b101011) ? 1 : 0;
assign beq = (opcode == 6'b000100) ? 1 : 0;
assign bne = (opcode == 6'b000101) ? 1 : 0;
assign j = (opcode == 6'b000010) ? 1 : 0;
assign jr = (opcode == 6'b000000 && func == 6'd8) ? 1 : 0;
assign jal = (opcode == 6'b000011) ? 1 : 0;
assign jalr = (opcode == 6'b000000 && func == 6'd9) ? 1'b1 : 1'b0;
assign shift = (inst_in != 32'h0 && opcode == 6'b000000 && (func == 6'd2 || func == 6'd0)) ? 1'b1 : 1'b0;
endmodule | 5 |
2,902 | data/full_repos/permissive/101428364/SCPU_v1.v | 101,428,364 | SCPU_v1.v | v | 128 | 103 | [] | [] | [] | [(21, 127)] | null | null | 1: b"%Error: data/full_repos/permissive/101428364/SCPU_v1.v:46: Duplicate declaration of signal: 'PC_out'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire [31:0] PC_out;\n ^~~~~~\n data/full_repos/permissive/101428364/SCPU_v1.v:24: ... Location of original declaration\n output [31:0] Addr_out, Data_out, PC_out,\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 457 | module | module SCPU_v1( input [31:0] inst_in, Data_in,
input clk, reset,
output MemW,
output [31:0] Addr_out, Data_out, PC_out,
input [4:0] test_reg_index,
output [31:0] test_reg_result
);
wire RegW, beq, bne, branch;
wire [1:0] sourceA, sourceB, destReg, toReg, jump;
wire [3:0] ALU_op;
wire zero, overflow;
wire [31:0] ALU_in_A, ALU_in_B, res;
wire [32:0] PC_inc_o, offset_add_o;
wire [31:0] addr_ext_o, addr_signext_o, addr_zeroext_o;
wire [31:0] addr_shift1_o;
wire [27:0] addr_shift2_o;
wire [4:0] destReg_Mux_out;
wire [31:0] toReg_out, sourceB_in_0, sourceA_in_0, branch_mux_o,jump_mux_o;
wire [31:0] PC_out;
reg [31:0] PC = 0;
always @ (posedge clk) begin
if(reset)
PC <= 0;
else
PC <= jump_mux_o;
end
assign PC_out = PC;
assign Data_out = sourceB_in_0;
assign Addr_out = res;
assign addr_shift1_o = addr_ext_o << 2;
assign addr_shift2_o = {inst_in[25:0], 2'b00};
assign branch = beq&zero | bne&~zero;
MUX2T1_32 branch_Mux(.I0(PC_inc_o[31:0]), .I1(offset_add_o[31:0]), .s(branch), .o(branch_mux_o)),
extend_mode(.I0(addr_zeroext_o), .I1(addr_signext_o), .s(ext), .o(addr_ext_o));
MUX4T1_32 sourceA_Mux(.I0(sourceA_in_0), .I1(addr_ext_o),
.I2(sourceB_in_0), .I3(), .s(sourceA), .o(ALU_in_A)),
jump_Mux(.I0(branch_mux_o), .I1({PC_out[31:28], addr_shift2_o}),
.I2(sourceA_in_0), .I3(), .s(jump), .o(jump_mux_o)),
SourceB_Mux(.I0(sourceB_in_0), .I1(addr_ext_o),
.I2(inst_in), .I3(32'h00000400), .s(sourceB), .o(ALU_in_B)),
ToReg_Mux(.I0(res), .I1(Data_in),
.I2(PC_inc_o), .I3(), .s(toReg), .o(toReg_out));
MUX4T1_5 DestReg_Mux(.I0(inst_in[15:11]), .I1(inst_in[20:16]),
.I2(5'b11111), .I3(), .s(destReg), .o(destReg_Mux_out));
Regs Regs( .clk(clk), .rst(reset), .reg_Rs_addr_A(inst_in[25:21]), .reg_Rt_addr_B(inst_in[20:16]),
.reg_Wt_addr(destReg_Mux_out), .wdata(toReg_out), .rdata_A(sourceA_in_0), .rdata_B(sourceB_in_0),
.we(RegW),
.test_reg_index(test_reg_index), .test_reg_result(test_reg_result));
ALU_v1 ALU( .A(ALU_in_A), .B(ALU_in_B), .ALU_operation(ALU_op), .zero(zero), .overflow(overflow),
.res(res) );
controller Controller( .opcode(inst_in[31:26]), .func(inst_in[5:0]), .ext(ext),
.inst_in(inst_in),
.MemW(MemW), .RegW(RegW), .sourceB(sourceB), .sourceA(sourceA),
.toReg(toReg), .destReg(destReg), .beq(beq), .bne(bne), .jump(jump),
.ALUopcode(ALU_op) );
ADC32 PC_inc(.C0(1'b0), .A(PC_out), .B(32'h00000004), .S(PC_inc_o), .overflow()),
offset_add(.C0(1'b0), .A(PC_inc_o[31:0]), .B(addr_shift1_o), .S(offset_add_o), .overflow());
signExt_16T32 signExt_1(.i(inst_in[15:0]), .o(addr_signext_o));
zeroExt_16T32 zeroExt_1(.i(inst_in[15:0]), .o(addr_zeroext_o));
endmodule | module SCPU_v1( input [31:0] inst_in, Data_in,
input clk, reset,
output MemW,
output [31:0] Addr_out, Data_out, PC_out,
input [4:0] test_reg_index,
output [31:0] test_reg_result
); |
wire RegW, beq, bne, branch;
wire [1:0] sourceA, sourceB, destReg, toReg, jump;
wire [3:0] ALU_op;
wire zero, overflow;
wire [31:0] ALU_in_A, ALU_in_B, res;
wire [32:0] PC_inc_o, offset_add_o;
wire [31:0] addr_ext_o, addr_signext_o, addr_zeroext_o;
wire [31:0] addr_shift1_o;
wire [27:0] addr_shift2_o;
wire [4:0] destReg_Mux_out;
wire [31:0] toReg_out, sourceB_in_0, sourceA_in_0, branch_mux_o,jump_mux_o;
wire [31:0] PC_out;
reg [31:0] PC = 0;
always @ (posedge clk) begin
if(reset)
PC <= 0;
else
PC <= jump_mux_o;
end
assign PC_out = PC;
assign Data_out = sourceB_in_0;
assign Addr_out = res;
assign addr_shift1_o = addr_ext_o << 2;
assign addr_shift2_o = {inst_in[25:0], 2'b00};
assign branch = beq&zero | bne&~zero;
MUX2T1_32 branch_Mux(.I0(PC_inc_o[31:0]), .I1(offset_add_o[31:0]), .s(branch), .o(branch_mux_o)),
extend_mode(.I0(addr_zeroext_o), .I1(addr_signext_o), .s(ext), .o(addr_ext_o));
MUX4T1_32 sourceA_Mux(.I0(sourceA_in_0), .I1(addr_ext_o),
.I2(sourceB_in_0), .I3(), .s(sourceA), .o(ALU_in_A)),
jump_Mux(.I0(branch_mux_o), .I1({PC_out[31:28], addr_shift2_o}),
.I2(sourceA_in_0), .I3(), .s(jump), .o(jump_mux_o)),
SourceB_Mux(.I0(sourceB_in_0), .I1(addr_ext_o),
.I2(inst_in), .I3(32'h00000400), .s(sourceB), .o(ALU_in_B)),
ToReg_Mux(.I0(res), .I1(Data_in),
.I2(PC_inc_o), .I3(), .s(toReg), .o(toReg_out));
MUX4T1_5 DestReg_Mux(.I0(inst_in[15:11]), .I1(inst_in[20:16]),
.I2(5'b11111), .I3(), .s(destReg), .o(destReg_Mux_out));
Regs Regs( .clk(clk), .rst(reset), .reg_Rs_addr_A(inst_in[25:21]), .reg_Rt_addr_B(inst_in[20:16]),
.reg_Wt_addr(destReg_Mux_out), .wdata(toReg_out), .rdata_A(sourceA_in_0), .rdata_B(sourceB_in_0),
.we(RegW),
.test_reg_index(test_reg_index), .test_reg_result(test_reg_result));
ALU_v1 ALU( .A(ALU_in_A), .B(ALU_in_B), .ALU_operation(ALU_op), .zero(zero), .overflow(overflow),
.res(res) );
controller Controller( .opcode(inst_in[31:26]), .func(inst_in[5:0]), .ext(ext),
.inst_in(inst_in),
.MemW(MemW), .RegW(RegW), .sourceB(sourceB), .sourceA(sourceA),
.toReg(toReg), .destReg(destReg), .beq(beq), .bne(bne), .jump(jump),
.ALUopcode(ALU_op) );
ADC32 PC_inc(.C0(1'b0), .A(PC_out), .B(32'h00000004), .S(PC_inc_o), .overflow()),
offset_add(.C0(1'b0), .A(PC_inc_o[31:0]), .B(addr_shift1_o), .S(offset_add_o), .overflow());
signExt_16T32 signExt_1(.i(inst_in[15:0]), .o(addr_signext_o));
zeroExt_16T32 zeroExt_1(.i(inst_in[15:0]), .o(addr_zeroext_o));
endmodule | 5 |
2,903 | data/full_repos/permissive/101428364/SC_top_sim.v | 101,428,364 | SC_top_sim.v | v | 267 | 83 | [] | [] | [] | [(23, 266)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:82: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:94: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:117: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:147: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:152: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:163: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:172: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:175: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:186: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:197: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:208: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:218: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:231: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:241: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/101428364/SC_top_sim.v:247: Cannot find file containing module: \'SCPU_v1\'\n SCPU_v1 uut2(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1\n data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1.v\n data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1.sv\n SCPU_v1\n SCPU_v1.v\n SCPU_v1.sv\n obj_dir/SCPU_v1\n obj_dir/SCPU_v1.v\n obj_dir/SCPU_v1.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 458 | module | module SC_top_sim();
reg clk;
reg reset;
reg MIO_ready;
reg [31:0]inst_in;
reg [31:0]Data_in;
wire mem_w;
wire[31:0]PC_out;
wire[31:0]Addr_out;
wire[31:0]Data_out;
reg[5:0] OPCODE;
reg[4:0] RS;
reg[4:0] RT;
reg[4:0] RD;
reg[4:0] SHAMT;
reg[5:0] FUNC;
always #50 clk = ~clk;
initial begin
reset = 1;
clk = 1;
inst_in = 0;
Data_in = 0;
inst_in = 0;
#100;
reset = 0;
OPCODE = 0;
RS = 17;
RT = 18;
RD = 19;
SHAMT = 0;
FUNC = 6'b100000;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100000;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100100;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100010;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 6'b100011;
RS = 15;
RT = 16;
inst_in = {OPCODE, RS, RT, 16'h0004};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000100;
RS = 15;
RT = 15;
inst_in = {OPCODE, RS, RT, 16'hFFFC};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000010;
RS = 15;
RT = 15;
inst_in = {OPCODE, 26'h4};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000000;
RS = 15;
FUNC = 6'b001000;
inst_in = {OPCODE, RS, 15'b0, FUNC};
#50
OPCODE = 6'b000000;
RS = 16;
FUNC = 6'b001000;
inst_in = {OPCODE, RS, 15'b0, FUNC};
#50
OPCODE = 6'b001000;
RS = 14;
RT = 14;
inst_in = {OPCODE, RS, RT, 16'h8000};
#100;
OPCODE = 6'b001010;
RS = 13;
RT = 13;
inst_in = {OPCODE, RS, RT, 16'hd};
#50;
inst_in = {OPCODE, RS, RT, 16'he};
#50;
OPCODE = 6'b001100;
RS = 12;
RT = 12;
inst_in = {OPCODE, RS, RT, 16'hcdc8};
#100;
OPCODE = 6'b001101;
RS = 11;
RT = 11;
inst_in = {OPCODE, RS, RT, 16'hcdcd};
#100;
OPCODE = 6'b101011;
RS = 10;
RT = 10;
inst_in = {OPCODE, RS, RT, 16'h0004};
#100;
OPCODE = 6'b001111;
RT = 9;
inst_in = {OPCODE, 5'b0, RT, 16'hcdcd};
#100;
OPCODE = 6'b000000;
RT = 9;
RD = 8;
SHAMT = 3;
FUNC = 6'b000010;
inst_in = {OPCODE, 5'b0, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 6'b000011;
inst_in = {OPCODE, 26'hf};
#100;
$finish;
end
SCPU_v1 uut2(
.clk(clk),
.reset(reset),
.inst_in(inst_in),
.Data_in(Data_in),
.mem_w(mem_w),
.PC_out(PC_out),
.Addr_out(Addr_out),
.Data_out(Data_out),
.test_reg_index(),
.test_reg_result()
);
endmodule | module SC_top_sim(); |
reg clk;
reg reset;
reg MIO_ready;
reg [31:0]inst_in;
reg [31:0]Data_in;
wire mem_w;
wire[31:0]PC_out;
wire[31:0]Addr_out;
wire[31:0]Data_out;
reg[5:0] OPCODE;
reg[4:0] RS;
reg[4:0] RT;
reg[4:0] RD;
reg[4:0] SHAMT;
reg[5:0] FUNC;
always #50 clk = ~clk;
initial begin
reset = 1;
clk = 1;
inst_in = 0;
Data_in = 0;
inst_in = 0;
#100;
reset = 0;
OPCODE = 0;
RS = 17;
RT = 18;
RD = 19;
SHAMT = 0;
FUNC = 6'b100000;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100000;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100100;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 0;
RS = 18;
RT = 19;
RD = 19;
SHAMT = 0;
FUNC = 6'b100010;
inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 6'b100011;
RS = 15;
RT = 16;
inst_in = {OPCODE, RS, RT, 16'h0004};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000100;
RS = 15;
RT = 15;
inst_in = {OPCODE, RS, RT, 16'hFFFC};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000010;
RS = 15;
RT = 15;
inst_in = {OPCODE, 26'h4};
Data_in = 32'hcdcdcdcd;
#100;
OPCODE = 6'b000000;
RS = 15;
FUNC = 6'b001000;
inst_in = {OPCODE, RS, 15'b0, FUNC};
#50
OPCODE = 6'b000000;
RS = 16;
FUNC = 6'b001000;
inst_in = {OPCODE, RS, 15'b0, FUNC};
#50
OPCODE = 6'b001000;
RS = 14;
RT = 14;
inst_in = {OPCODE, RS, RT, 16'h8000};
#100;
OPCODE = 6'b001010;
RS = 13;
RT = 13;
inst_in = {OPCODE, RS, RT, 16'hd};
#50;
inst_in = {OPCODE, RS, RT, 16'he};
#50;
OPCODE = 6'b001100;
RS = 12;
RT = 12;
inst_in = {OPCODE, RS, RT, 16'hcdc8};
#100;
OPCODE = 6'b001101;
RS = 11;
RT = 11;
inst_in = {OPCODE, RS, RT, 16'hcdcd};
#100;
OPCODE = 6'b101011;
RS = 10;
RT = 10;
inst_in = {OPCODE, RS, RT, 16'h0004};
#100;
OPCODE = 6'b001111;
RT = 9;
inst_in = {OPCODE, 5'b0, RT, 16'hcdcd};
#100;
OPCODE = 6'b000000;
RT = 9;
RD = 8;
SHAMT = 3;
FUNC = 6'b000010;
inst_in = {OPCODE, 5'b0, RT, RD, SHAMT, FUNC};
#100;
OPCODE = 6'b000011;
inst_in = {OPCODE, 26'hf};
#100;
$finish;
end
SCPU_v1 uut2(
.clk(clk),
.reset(reset),
.inst_in(inst_in),
.Data_in(Data_in),
.mem_w(mem_w),
.PC_out(PC_out),
.Addr_out(Addr_out),
.Data_out(Data_out),
.test_reg_index(),
.test_reg_result()
);
endmodule | 5 |
2,904 | data/full_repos/permissive/101428364/second_decoder.v | 101,428,364 | second_decoder.v | v | 124 | 104 | [] | [] | [] | [(21, 123)] | null | data/verilator_xmls/eef613b8-41e5-4919-ad64-d91bcc64d2bf.xml | null | 459 | module | module second_decoder( input [5:0] func, opcode,
input wire rtype_ALU, itype_ALU, lw, sw, j, jr, jal, jalr, shift, beq, bne, nop,
output RegW, MemW, ext,
output [1:0] sourceA, sourceB, toReg, destReg, jump,
output [3:0] ALUopcode
);
reg [3:0] ALU_reg;
reg [1:0] sourceA_reg, sourceB_reg, toReg_reg, destReg_reg, jump_reg;
always @ * begin
if(rtype_ALU) begin
case(func)
6'h0: ALU_reg <= 4'b1000;
6'd2: ALU_reg <= 4'b0101;
6'd9: ALU_reg <= 4'b0010;
6'd32: ALU_reg <= 4'b0010;
6'd34: ALU_reg <= 4'b0110;
6'd36: ALU_reg <= 4'b0000;
6'd37: ALU_reg <= 4'b0001;
6'd38: ALU_reg <= 4'b0011;
6'd39: ALU_reg <= 4'b0100;
6'd42: ALU_reg <= 4'b0111;
endcase
end
else if(itype_ALU) begin
case(opcode)
6'h8: ALU_reg <= 4'b0010;
6'ha: ALU_reg <= 4'b0111;
6'hc: ALU_reg <= 4'b0000;
6'hd: ALU_reg <= 4'b0001;
6'he: ALU_reg <= 4'b0011;
6'hf: ALU_reg <= 4'b1000;
endcase
end
else if(beq || bne)
ALU_reg <= 4'b0110;
else
ALU_reg <= 4'b0010;
end
assign ALUopcode = ALU_reg;
always @ * begin
if(opcode == 6'hf)
sourceA_reg <= 2'b01;
else if(shift)
sourceA_reg <= 2'b10;
else
sourceA_reg <= 2'b00;
end
assign sourceA = sourceA_reg;
always @ *
if(lw || sw || (itype_ALU && opcode != 6'h0f))
sourceB_reg <= 2'b01;
else if(shift)
sourceB_reg <= 2'b10;
else if(opcode == 6'h0f)
sourceB_reg <= 2'b11;
else
sourceB_reg <= 2'b00;
assign sourceB = sourceB_reg;
always @ *
if(lw)
toReg_reg <= 2'b01;
else if(jal | jalr)
toReg_reg <= 2'b10;
else
toReg_reg <= 2'b00;
assign toReg = toReg_reg;
always @ *
if(lw | itype_ALU )
destReg_reg <= 2'b01;
else if(jal)
destReg_reg <= 2'b10;
else
destReg_reg <= 2'b00;
assign destReg = destReg_reg;
always @ *
if(j | jal)
jump_reg <= 2'b01;
else if(jalr | jr)
jump_reg <= 2'b10;
else
jump_reg <= 2'b00;
assign jump = jump_reg;
assign RegW = lw | itype_ALU | (rtype_ALU & ~nop) | jal ;
assign MemW = sw;
assign ext = (opcode == 6'h8 || opcode == 6'ha || beq || bne) ? 1 : 0;
endmodule | module second_decoder( input [5:0] func, opcode,
input wire rtype_ALU, itype_ALU, lw, sw, j, jr, jal, jalr, shift, beq, bne, nop,
output RegW, MemW, ext,
output [1:0] sourceA, sourceB, toReg, destReg, jump,
output [3:0] ALUopcode
); |
reg [3:0] ALU_reg;
reg [1:0] sourceA_reg, sourceB_reg, toReg_reg, destReg_reg, jump_reg;
always @ * begin
if(rtype_ALU) begin
case(func)
6'h0: ALU_reg <= 4'b1000;
6'd2: ALU_reg <= 4'b0101;
6'd9: ALU_reg <= 4'b0010;
6'd32: ALU_reg <= 4'b0010;
6'd34: ALU_reg <= 4'b0110;
6'd36: ALU_reg <= 4'b0000;
6'd37: ALU_reg <= 4'b0001;
6'd38: ALU_reg <= 4'b0011;
6'd39: ALU_reg <= 4'b0100;
6'd42: ALU_reg <= 4'b0111;
endcase
end
else if(itype_ALU) begin
case(opcode)
6'h8: ALU_reg <= 4'b0010;
6'ha: ALU_reg <= 4'b0111;
6'hc: ALU_reg <= 4'b0000;
6'hd: ALU_reg <= 4'b0001;
6'he: ALU_reg <= 4'b0011;
6'hf: ALU_reg <= 4'b1000;
endcase
end
else if(beq || bne)
ALU_reg <= 4'b0110;
else
ALU_reg <= 4'b0010;
end
assign ALUopcode = ALU_reg;
always @ * begin
if(opcode == 6'hf)
sourceA_reg <= 2'b01;
else if(shift)
sourceA_reg <= 2'b10;
else
sourceA_reg <= 2'b00;
end
assign sourceA = sourceA_reg;
always @ *
if(lw || sw || (itype_ALU && opcode != 6'h0f))
sourceB_reg <= 2'b01;
else if(shift)
sourceB_reg <= 2'b10;
else if(opcode == 6'h0f)
sourceB_reg <= 2'b11;
else
sourceB_reg <= 2'b00;
assign sourceB = sourceB_reg;
always @ *
if(lw)
toReg_reg <= 2'b01;
else if(jal | jalr)
toReg_reg <= 2'b10;
else
toReg_reg <= 2'b00;
assign toReg = toReg_reg;
always @ *
if(lw | itype_ALU )
destReg_reg <= 2'b01;
else if(jal)
destReg_reg <= 2'b10;
else
destReg_reg <= 2'b00;
assign destReg = destReg_reg;
always @ *
if(j | jal)
jump_reg <= 2'b01;
else if(jalr | jr)
jump_reg <= 2'b10;
else
jump_reg <= 2'b00;
assign jump = jump_reg;
assign RegW = lw | itype_ALU | (rtype_ALU & ~nop) | jal ;
assign MemW = sw;
assign ext = (opcode == 6'h8 || opcode == 6'ha || beq || bne) ? 1 : 0;
endmodule | 5 |
2,907 | data/full_repos/permissive/101468463/mix.v | 101,468,463 | mix.v | v | 60 | 108 | [] | [] | [] | [(5, 59)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/101468463/mix.v:46: Operator NEQ expects 5 bits on the RHS, but RHS\'s VARREF \'a\' generates 4 bits.\n : ... In instance mix\n if(i != a && i != b && i != c && i != d)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101468463/mix.v:46: Operator NEQ expects 5 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance mix\n if(i != a && i != b && i != c && i != d)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/101468463/mix.v:46: Operator NEQ expects 5 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n : ... In instance mix\n if(i != a && i != b && i != c && i != d)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/101468463/mix.v:46: Operator NEQ expects 5 bits on the RHS, but RHS\'s VARREF \'d\' generates 4 bits.\n : ... In instance mix\n if(i != a && i != b && i != c && i != d)\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 471 | module | module mix(
input clk,
input wire [64*16-1:0] v,
input wire [3:0] a, b, c, d,
input wire [63:0] x, y,
output reg [64*16-1:0] v_out
);
reg [63:0]
a0, a1,
b0, b1, b2, b3,
c0, c1,
d0, d1, d2, d3;
reg [4:0] i;
always @(posedge clk)
begin
a0 = v[a*64+:64] + v[b*64+:64] + x;
d0 = v[d*64+:64] ^ a0;
d1 = { d0[0+:32], d0[32+:32] };
c0 = v[c*64+:64] + d1;
b0 = v[b*64+:64] ^ c0;
b1 = { b0[0+:24], b0[24+:40] };
a1 = a0 + b1 + y;
d2 = d1 ^ a1;
d3 = { d2[0+:16], d2[16+:48]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = { b2[0+:63], b2[63+:1] };
for(i = 0; i < 16; i = i + 1)
begin
if(i != a && i != b && i != c && i != d)
begin
v_out[i*64+:64] <= v[i*64+:64];
end
end
v_out[a*64+:64] <= a1;
v_out[b*64+:64] <= b3;
v_out[c*64+:64] <= c1;
v_out[d*64+:64] <= d3;
end
endmodule | module mix(
input clk,
input wire [64*16-1:0] v,
input wire [3:0] a, b, c, d,
input wire [63:0] x, y,
output reg [64*16-1:0] v_out
); |
reg [63:0]
a0, a1,
b0, b1, b2, b3,
c0, c1,
d0, d1, d2, d3;
reg [4:0] i;
always @(posedge clk)
begin
a0 = v[a*64+:64] + v[b*64+:64] + x;
d0 = v[d*64+:64] ^ a0;
d1 = { d0[0+:32], d0[32+:32] };
c0 = v[c*64+:64] + d1;
b0 = v[b*64+:64] ^ c0;
b1 = { b0[0+:24], b0[24+:40] };
a1 = a0 + b1 + y;
d2 = d1 ^ a1;
d3 = { d2[0+:16], d2[16+:48]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = { b2[0+:63], b2[63+:1] };
for(i = 0; i < 16; i = i + 1)
begin
if(i != a && i != b && i != c && i != d)
begin
v_out[i*64+:64] <= v[i*64+:64];
end
end
v_out[a*64+:64] <= a1;
v_out[b*64+:64] <= b3;
v_out[c*64+:64] <= c1;
v_out[d*64+:64] <= d3;
end
endmodule | 3 |
2,908 | data/full_repos/permissive/101468463/mix_test.v | 101,468,463 | mix_test.v | v | 51 | 120 | [] | [] | [] | null | line:9: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101468463/mix_test.v:44: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("output.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/101468463/mix_test.v:45: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 $display("%x %x %x %x\\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 472 | module | module mix_test();
reg clk=0;
reg [64*16-1:0] v;
reg [3:0]
a = 4'd0,
b = 4'd4,
c = 4'd8,
d = 4'd12;
reg [63:0]
x = 64'h6f6c6c6568,
y = 64'h0;
wire [64*16-1:0] v_out;
mix _mix(
.clk(clk),
.v(v),
.a(a),
.b(b),
.c(c),
.d(d),
.x(x),
.y(y),
.v_out(v_out)
);
always
begin
#1 clk = ~clk;
end
initial
begin
v[0*64+:64] = 64'h6a09e667f2bdc91c;
v[4*64+:64] = 64'h510e527fade682d1;
v[8*64+:64] = 64'h6a09e667f3bcc908;
v[12*64+:64] = 64'h510e527fade682d4;
$display("starting!");
$dumpfile("output.vcd");
$dumpvars;
#10 $display("%x %x %x %x\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);
#10 $finish;
end
endmodule | module mix_test(); |
reg clk=0;
reg [64*16-1:0] v;
reg [3:0]
a = 4'd0,
b = 4'd4,
c = 4'd8,
d = 4'd12;
reg [63:0]
x = 64'h6f6c6c6568,
y = 64'h0;
wire [64*16-1:0] v_out;
mix _mix(
.clk(clk),
.v(v),
.a(a),
.b(b),
.c(c),
.d(d),
.x(x),
.y(y),
.v_out(v_out)
);
always
begin
#1 clk = ~clk;
end
initial
begin
v[0*64+:64] = 64'h6a09e667f2bdc91c;
v[4*64+:64] = 64'h510e527fade682d1;
v[8*64+:64] = 64'h6a09e667f3bcc908;
v[12*64+:64] = 64'h510e527fade682d4;
$display("starting!");
$dumpfile("output.vcd");
$dumpvars;
#10 $display("%x %x %x %x\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);
#10 $finish;
end
endmodule | 3 |
2,909 | data/full_repos/permissive/101509620/EightLockins/qsys_system/qsys_system_bb.v | 101,509,620 | qsys_system_bb.v | v | 55 | 36 | [] | [] | [] | [(14, 249)] | null | data/verilator_xmls/b844b687-143e-4092-b8a8-090cc649f70b.xml | null | 482 | module | module qsys_system (
clk_clk,
control_bits_export,
dac_div_export,
dac_gain_export,
gain_ctrl_export,
lia_1_x_export,
lia_1_y_export,
phase_incr_1_export,
phase_incr_2_export,
phase_incr_3_export,
phase_incr_4_export,
phase_incr_5_export,
phase_incr_6_export,
phase_incr_7_export,
phase_incr_8_export,
phase_offs_1_export,
phase_offs_2_export,
phase_offs_3_export,
phase_offs_4_export,
phase_offs_5_export,
phase_offs_6_export,
phase_offs_7_export,
phase_offs_8_export,
reset_reset_n,
resetrequest_reset);
input clk_clk;
output [7:0] control_bits_export;
output [7:0] dac_div_export;
output [7:0] dac_gain_export;
output [5:0] gain_ctrl_export;
input [15:0] lia_1_x_export;
input [15:0] lia_1_y_export;
output [19:0] phase_incr_1_export;
output [19:0] phase_incr_2_export;
output [19:0] phase_incr_3_export;
output [19:0] phase_incr_4_export;
output [19:0] phase_incr_5_export;
output [19:0] phase_incr_6_export;
output [19:0] phase_incr_7_export;
output [19:0] phase_incr_8_export;
output [19:0] phase_offs_1_export;
output [19:0] phase_offs_2_export;
output [19:0] phase_offs_3_export;
output [19:0] phase_offs_4_export;
output [19:0] phase_offs_5_export;
output [19:0] phase_offs_6_export;
output [19:0] phase_offs_7_export;
output [19:0] phase_offs_8_export;
input reset_reset_n;
output resetrequest_reset;
endmodule | module qsys_system (
clk_clk,
control_bits_export,
dac_div_export,
dac_gain_export,
gain_ctrl_export,
lia_1_x_export,
lia_1_y_export,
phase_incr_1_export,
phase_incr_2_export,
phase_incr_3_export,
phase_incr_4_export,
phase_incr_5_export,
phase_incr_6_export,
phase_incr_7_export,
phase_incr_8_export,
phase_offs_1_export,
phase_offs_2_export,
phase_offs_3_export,
phase_offs_4_export,
phase_offs_5_export,
phase_offs_6_export,
phase_offs_7_export,
phase_offs_8_export,
reset_reset_n,
resetrequest_reset); |
input clk_clk;
output [7:0] control_bits_export;
output [7:0] dac_div_export;
output [7:0] dac_gain_export;
output [5:0] gain_ctrl_export;
input [15:0] lia_1_x_export;
input [15:0] lia_1_y_export;
output [19:0] phase_incr_1_export;
output [19:0] phase_incr_2_export;
output [19:0] phase_incr_3_export;
output [19:0] phase_incr_4_export;
output [19:0] phase_incr_5_export;
output [19:0] phase_incr_6_export;
output [19:0] phase_incr_7_export;
output [19:0] phase_incr_8_export;
output [19:0] phase_offs_1_export;
output [19:0] phase_offs_2_export;
output [19:0] phase_offs_3_export;
output [19:0] phase_offs_4_export;
output [19:0] phase_offs_5_export;
output [19:0] phase_offs_6_export;
output [19:0] phase_offs_7_export;
output [19:0] phase_offs_8_export;
input reset_reset_n;
output resetrequest_reset;
endmodule | 2 |
2,910 | data/full_repos/permissive/101548714/Array_Dataflow.v | 101,548,714 | Array_Dataflow.v | v | 21 | 82 | [] | [] | [] | [(10, 18)] | null | data/verilator_xmls/f4024878-dec3-4596-9533-f3b39e2d567d.xml | null | 535 | module | module Array_Mult_Dataflow(a,b,out);
input [1:0] a,b;
output [3:0] out;
assign out[0] = a[0] & b[0];
assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule | module Array_Mult_Dataflow(a,b,out); |
input [1:0] a,b;
output [3:0] out;
assign out[0] = a[0] & b[0];
assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule | 1 |
2,914 | data/full_repos/permissive/101548714/Half_Adder_structural.v | 101,548,714 | Half_Adder_structural.v | v | 17 | 82 | [] | [] | [] | [(10, 16)] | null | data/verilator_xmls/210b72a0-7d4e-4e94-9d79-478f470df65b.xml | null | 540 | module | module HA_Structural(a,b,sum,cout);
input a,b;
output sum,cout;
xor u1(sum, a, b);
and u2(cout, a, b);
endmodule | module HA_Structural(a,b,sum,cout); |
input a,b;
output sum,cout;
xor u1(sum, a, b);
and u2(cout, a, b);
endmodule | 1 |
2,916 | data/full_repos/permissive/101548714/RS_FlipFlop.v | 101,548,714 | RS_FlipFlop.v | v | 26 | 82 | [] | [] | [] | [(10, 25)] | null | data/verilator_xmls/2eaff417-5a28-480f-b379-dda537bb12b8.xml | null | 542 | module | module RSFF(RS,clk,q,qbar);
input [1:0] RS;
output q,qbar;
input clk;
reg q,qbar;
always @(posedge clk) begin
case (RS)
2'd0: q = q;
2'd1: q = 0;
2'd2: q = 1;
2'd3: q = 1'bx;
endcase
qbar = ~q;
end
endmodule | module RSFF(RS,clk,q,qbar); |
input [1:0] RS;
output q,qbar;
input clk;
reg q,qbar;
always @(posedge clk) begin
case (RS)
2'd0: q = q;
2'd1: q = 0;
2'd2: q = 1;
2'd3: q = 1'bx;
endcase
qbar = ~q;
end
endmodule | 1 |
2,917 | data/full_repos/permissive/101548714/T_Flip_Flop.v | 101,548,714 | T_Flip_Flop.v | v | 24 | 82 | [] | [] | [] | [(10, 23)] | null | data/verilator_xmls/f0376c94-d048-442b-88d8-33a1ec2e6e53.xml | null | 543 | module | module TFF(T,rst,clk,q);
input T,rst,clk;
output q;
reg q;
always @(posedge clk) begin
if(rst==1) begin
q<=0;
end
else begin
q<=~T;
end
end
endmodule | module TFF(T,rst,clk,q); |
input T,rst,clk;
output q;
reg q;
always @(posedge clk) begin
if(rst==1) begin
q<=0;
end
else begin
q<=~T;
end
end
endmodule | 1 |
2,920 | data/full_repos/permissive/101786773/blink/blink2/blink.v | 101,786,773 | blink.v | v | 26 | 80 | [] | [] | [] | [(16, 25)] | null | data/verilator_xmls/9cc665b0-96aa-4f30-89ee-7581937ca546.xml | null | 547 | module | module blink(input clk, output LED);
reg [22:0] count;
assign LED = count[22];
always @(posedge clk)
count <= count + 1;
endmodule | module blink(input clk, output LED); |
reg [22:0] count;
assign LED = count[22];
always @(posedge clk)
count <= count + 1;
endmodule | 3 |
2,925 | data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v | 101,793,969 | messbauer_test_environment.v | v | 78 | 221 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:44: Cannot find file containing module: 'messbauer_generator'\nmessbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v1_start), .channel(v1_channel));\n^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101793969/messbauer_test_environment/src,data/full_repos/permissive/101793969/messbauer_generator\n data/full_repos/permissive/101793969/messbauer_test_environment/src,data/full_repos/permissive/101793969/messbauer_generator.v\n data/full_repos/permissive/101793969/messbauer_test_environment/src,data/full_repos/permissive/101793969/messbauer_generator.sv\n messbauer_generator\n messbauer_generator.v\n messbauer_generator.sv\n obj_dir/messbauer_generator\n obj_dir/messbauer_generator.v\n obj_dir/messbauer_generator.sv\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:46: Cannot find file containing module: 'messbauer_saw_tooth_generator'\nmessbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v1_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v1_velocity_reference));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:48: Cannot find file containing module: 'messbauer_diff_discriminator_signals'\nmessbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:52: Cannot find file containing module: 'messbauer_generator'\nmessbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v2_start), .channel(v2_channel));\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:54: Cannot find file containing module: 'messbauer_saw_tooth_generator'\nmessbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v2_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v2_velocity_reference));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/src/messbauer_test_environment.v:56: Cannot find file containing module: 'messbauer_diff_discriminator_signals'\nmessbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 552 | module | module messbauer_test_environment
(
input wire global_clock,
input wire global_reset,
output wire v1_channel,
output wire v1_start,
output wire [11:0] v1_velocity_reference,
output wire v1_lower_threshold,
output wire v1_upper_threshold,
output wire v2_channel,
output wire v2_start,
output wire [11:0] v2_velocity_reference,
output wire v2_lower_threshold,
output wire v2_upper_threshold
);
reg internal_reset;
reg [5:0] counter;
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v1_start), .channel(v1_channel));
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v1_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v1_velocity_reference));
messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold));
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v2_start), .channel(v2_channel));
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v2_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v2_velocity_reference));
messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold));
always @(posedge global_clock)
begin
if(~global_reset)
begin
internal_reset <= 1;
counter <= 0;
end
if(counter < 16)
counter <= counter + 1'b1;
if(counter >= 16 && counter < 32)
begin
counter <= counter + 1'b1;
internal_reset <= 0;
end
if(counter == 32)
internal_reset <= 1;
end
endmodule | module messbauer_test_environment
(
input wire global_clock,
input wire global_reset,
output wire v1_channel,
output wire v1_start,
output wire [11:0] v1_velocity_reference,
output wire v1_lower_threshold,
output wire v1_upper_threshold,
output wire v2_channel,
output wire v2_start,
output wire [11:0] v2_velocity_reference,
output wire v2_lower_threshold,
output wire v2_upper_threshold
); |
reg internal_reset;
reg [5:0] counter;
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v1_start), .channel(v1_channel));
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v1_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v1_velocity_reference));
messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold));
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v2_start), .channel(v2_channel));
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v2_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v2_velocity_reference));
messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold));
always @(posedge global_clock)
begin
if(~global_reset)
begin
internal_reset <= 1;
counter <= 0;
end
if(counter < 16)
counter <= counter + 1'b1;
if(counter >= 16 && counter < 32)
begin
counter <= counter + 1'b1;
internal_reset <= 0;
end
if(counter == 32)
internal_reset <= 1;
end
endmodule | 3 |
2,927 | data/full_repos/permissive/101793969/messbauer_test_environment/tests/messbauer_generator_testbench_channelafter.v | 101,793,969 | messbauer_generator_testbench_channelafter.v | v | 63 | 127 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101793969/messbauer_test_environment/tests/messbauer_generator_testbench_channelafter.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101793969/messbauer_test_environment/tests/messbauer_generator_testbench_channelafter.v:58: Unsupported: Ignoring delay on this delayed statement.\n #20 aclk = ~aclk;\n ^\n%Error: data/full_repos/permissive/101793969/messbauer_test_environment/tests/messbauer_generator_testbench_channelafter.v:36: Cannot find file containing module: \'messbauer_generator\'\n messbauer_generator # (.CHANNEL_TYPE(2)) \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101793969/messbauer_test_environment/tests,data/full_repos/permissive/101793969/messbauer_generator\n data/full_repos/permissive/101793969/messbauer_test_environment/tests,data/full_repos/permissive/101793969/messbauer_generator.v\n data/full_repos/permissive/101793969/messbauer_test_environment/tests,data/full_repos/permissive/101793969/messbauer_generator.sv\n messbauer_generator\n messbauer_generator.v\n messbauer_generator.sv\n obj_dir/messbauer_generator\n obj_dir/messbauer_generator.v\n obj_dir/messbauer_generator.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 554 | module | module messbauer_generator_testbench_channelafter;
reg aclk;
reg areset_n;
wire start;
wire channel;
messbauer_generator # (.CHANNEL_TYPE(2))
uut
(
.aclk(aclk),
.areset_n(areset_n),
.start(start),
.channel(channel)
);
initial begin
aclk = 0;
areset_n = 0;
#100;
areset_n = 1;
end
always
begin
#20 aclk = ~aclk;
end
endmodule | module messbauer_generator_testbench_channelafter; |
reg aclk;
reg areset_n;
wire start;
wire channel;
messbauer_generator # (.CHANNEL_TYPE(2))
uut
(
.aclk(aclk),
.areset_n(areset_n),
.start(start),
.channel(channel)
);
initial begin
aclk = 0;
areset_n = 0;
#100;
areset_n = 1;
end
always
begin
#20 aclk = ~aclk;
end
endmodule | 3 |
2,928 | data/full_repos/permissive/101862289/baud_gen.v | 101,862,289 | baud_gen.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | data/verilator_xmls/52781b4a-712f-4252-901d-51e6e0a57ede.xml | null | 556 | module | module baud_gen(
input clk,
input rst,
output cy
);
reg[15:0] Q;
assign cy=(Q==16'd3);
always@(posedge clk)
begin
if(rst|cy) Q<=16'd0;
else Q<=Q+1;
end
endmodule | module baud_gen(
input clk,
input rst,
output cy
); |
reg[15:0] Q;
assign cy=(Q==16'd3);
always@(posedge clk)
begin
if(rst|cy) Q<=16'd0;
else Q<=Q+1;
end
endmodule | 0 |
2,929 | data/full_repos/permissive/101862289/bitcounter.v | 101,862,289 | bitcounter.v | v | 45 | 83 | [] | [] | [] | [(21, 44)] | null | data/verilator_xmls/f8b84d85-2fa2-4c04-9d87-a36c1eda3ace.xml | null | 557 | module | module bitcounter(
input start,
input en,
input clk,
input rst,
output [3:0] out
);
wire engedelyezes;
wire nemnulla;
reg[3:0] Q;
assign nemnulla =(Q>4'b0);
assign engedelyezes = (en&(start|nemnulla));
always@(posedge clk)
begin
if(rst|(en&Q==10)) Q<=4'b0;
else if(engedelyezes) Q<=Q+1;
end
assign out = Q;
endmodule | module bitcounter(
input start,
input en,
input clk,
input rst,
output [3:0] out
); |
wire engedelyezes;
wire nemnulla;
reg[3:0] Q;
assign nemnulla =(Q>4'b0);
assign engedelyezes = (en&(start|nemnulla));
always@(posedge clk)
begin
if(rst|(en&Q==10)) Q<=4'b0;
else if(engedelyezes) Q<=Q+1;
end
assign out = Q;
endmodule | 0 |
2,930 | data/full_repos/permissive/101862289/bitgenerator.v | 101,862,289 | bitgenerator.v | v | 41 | 125 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/02f0ed64-9fa9-4291-9eb5-776b291f6c60.xml | null | 558 | module | module bitgenerator(
input [7:0] sw,
output [10:0] out
);
assign out[0]=1;
assign out[1]=0;
assign out[2]=sw[0];
assign out[3]=sw[1];
assign out[4]=sw[2];
assign out[5]=sw[3];
assign out[6]=sw[4];
assign out[7]=sw[5];
assign out[8]=sw[6];
assign out[9]=sw[0]^sw[1]^sw[2]^sw[3]^sw[4]^sw[5]^sw[6]^sw[7];
assign out[10]=1;
endmodule | module bitgenerator(
input [7:0] sw,
output [10:0] out
); |
assign out[0]=1;
assign out[1]=0;
assign out[2]=sw[0];
assign out[3]=sw[1];
assign out[4]=sw[2];
assign out[5]=sw[3];
assign out[6]=sw[4];
assign out[7]=sw[5];
assign out[8]=sw[6];
assign out[9]=sw[0]^sw[1]^sw[2]^sw[3]^sw[4]^sw[5]^sw[6]^sw[7];
assign out[10]=1;
endmodule | 0 |
2,931 | data/full_repos/permissive/101862289/btn1_pergesmentesito.v | 101,862,289 | btn1_pergesmentesito.v | v | 57 | 83 | [] | [] | [] | [(21, 56)] | null | data/verilator_xmls/f8908a4d-039a-430e-a0cb-5b1b0f795f00.xml | null | 559 | module | module btn1_pergesmentesito(
input btn,
input clk,
input en,
output btn1_en
);
wire rst = ~btn;
wire carry;
wire engedelyezes;
reg[15:0] Q;
assign carry=(Q==4);
assign engedelyezes=((btn^carry)&en);
always@(posedge clk)
begin
if(rst) Q<=16'b0;
else if(engedelyezes) Q<=Q+1;
end
reg dff;
always@(posedge clk)
begin
if(en) dff<=carry;
end
assign btn1_en=(dff&~carry);
endmodule | module btn1_pergesmentesito(
input btn,
input clk,
input en,
output btn1_en
); |
wire rst = ~btn;
wire carry;
wire engedelyezes;
reg[15:0] Q;
assign carry=(Q==4);
assign engedelyezes=((btn^carry)&en);
always@(posedge clk)
begin
if(rst) Q<=16'b0;
else if(engedelyezes) Q<=Q+1;
end
reg dff;
always@(posedge clk)
begin
if(en) dff<=carry;
end
assign btn1_en=(dff&~carry);
endmodule | 0 |
2,932 | data/full_repos/permissive/101862289/btn2_pergesmentesito.v | 101,862,289 | btn2_pergesmentesito.v | v | 45 | 83 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/d26d6163-ae96-4895-831b-bb58e958e9e7.xml | null | 560 | module | module btn2_pergesmentesito(
input btn,
input clk,
input en,
output btn2_en
);
wire rst = ~btn;
wire engedelyezes;
reg[15:0] Q;
assign btn2_en=(Q==4);
assign engedelyezes=((btn^btn2_en)&en);
always@(posedge clk)
begin
if(rst) Q<=16'b0;
else if(engedelyezes) Q<=Q+1;
end
endmodule | module btn2_pergesmentesito(
input btn,
input clk,
input en,
output btn2_en
); |
wire rst = ~btn;
wire engedelyezes;
reg[15:0] Q;
assign btn2_en=(Q==4);
assign engedelyezes=((btn^btn2_en)&en);
always@(posedge clk)
begin
if(rst) Q<=16'b0;
else if(engedelyezes) Q<=Q+1;
end
endmodule | 0 |
2,933 | data/full_repos/permissive/101862289/proba1.v | 101,862,289 | proba1.v | v | 79 | 81 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:68: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:70: Unsupported: Ignoring delay on this delayed statement.\n #500;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:77: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk=~clk;\n ^\n%Error: data/full_repos/permissive/101862289/proba1.v:43: Cannot find file containing module: \'top_level\'\n top_level uut (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level.v\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level.sv\n top_level\n top_level.v\n top_level.sv\n obj_dir/top_level\n obj_dir/top_level.v\n obj_dir/top_level.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 561 | module | module proba1;
reg clk;
reg rst;
reg btn1;
reg btn2;
reg [7:0] sw;
wire kimenet;
wire[10:0] bitgen_dbg;
wire[3:0] dbgki;
wire startki;
wire btn1enki;
wire btn2enki;
top_level uut (
.clk(clk),
.rst(rst),
.btn1(btn1),
.btn2(btn2),
.sw(sw),
.kimenet(kimenet),
.bitgen_dbg(bitgen_dbg),
.dbgki(dbgki),
.startki(startki),
.btn1enki(btn1enki),
.btn2enki(btn2enki)
);
initial begin
clk = 0;
rst = 1;
btn1 = 0;
btn2 = 0;
sw = 8'b01010101;
#10;
rst=0;
#2;
btn2=1;
#500;
btn2=0;
end
always #1 clk=~clk;
endmodule | module proba1; |
reg clk;
reg rst;
reg btn1;
reg btn2;
reg [7:0] sw;
wire kimenet;
wire[10:0] bitgen_dbg;
wire[3:0] dbgki;
wire startki;
wire btn1enki;
wire btn2enki;
top_level uut (
.clk(clk),
.rst(rst),
.btn1(btn1),
.btn2(btn2),
.sw(sw),
.kimenet(kimenet),
.bitgen_dbg(bitgen_dbg),
.dbgki(dbgki),
.startki(startki),
.btn1enki(btn1enki),
.btn2enki(btn2enki)
);
initial begin
clk = 0;
rst = 1;
btn1 = 0;
btn2 = 0;
sw = 8'b01010101;
#10;
rst=0;
#2;
btn2=1;
#500;
btn2=0;
end
always #1 clk=~clk;
endmodule | 0 |
2,934 | data/full_repos/permissive/101862289/top_level.v | 101,862,289 | top_level.v | v | 65 | 92 | [] | [] | [] | [(21, 64)] | null | null | 1: b"%Error: data/full_repos/permissive/101862289/top_level.v:37: Cannot find file containing module: 'baud_gen'\n baud_gen baud_generator(.clk(clk), .rst(rst), .cy(en)); \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/baud_gen\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/baud_gen.v\n data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/baud_gen.sv\n baud_gen\n baud_gen.v\n baud_gen.sv\n obj_dir/baud_gen\n obj_dir/baud_gen.v\n obj_dir/baud_gen.sv\n%Error: data/full_repos/permissive/101862289/top_level.v:41: Cannot find file containing module: 'bitgenerator'\n bitgenerator bitgen(.sw(sw), .out(swk_allasa));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/101862289/top_level.v:47: Cannot find file containing module: 'btn1_pergesmentesito'\n btn1_pergesmentesito btn1_p(.btn(btn1), .clk(clk), .en(en), .btn1_en(btn1_en));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101862289/top_level.v:48: Cannot find file containing module: 'btn2_pergesmentesito'\n btn2_pergesmentesito btn2_p(.btn(btn2), .clk(clk), .en(en), .btn2_en(btn2_en));\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101862289/top_level.v:56: Cannot find file containing module: 'bitcounter'\n bitcounter bitcntr(.start(start), .en(en), .clk(clk), .rst(rst), .out(mpx_select));\n ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 562 | module | module top_level(
input clk,
input rst,
input btn1,
input btn2,
input[7:0] sw,
output kimenet,
output[10:0] bitgen_dbg,
output[3:0] dbgki,
output startki,
output btn1enki,
output btn2enki
);
wire en;
baud_gen baud_generator(.clk(clk), .rst(rst), .cy(en));
wire[10:0] swk_allasa;
bitgenerator bitgen(.sw(sw), .out(swk_allasa));
wire start;
wire btn1_en;
wire btn2_en;
btn1_pergesmentesito btn1_p(.btn(btn1), .clk(clk), .en(en), .btn1_en(btn1_en));
btn2_pergesmentesito btn2_p(.btn(btn2), .clk(clk), .en(en), .btn2_en(btn2_en));
assign start=(btn1_en||btn2_en);
assign startki=start;
assign btn1enki=btn1_en;
assign btn2enki=btn2_en;
wire[3:0] mpx_select;
bitcounter bitcntr(.start(start), .en(en), .clk(clk), .rst(rst), .out(mpx_select));
assign kimenet=swk_allasa[mpx_select];
assign bitgen_dbg=swk_allasa;
assign dbgki=mpx_select;
endmodule | module top_level(
input clk,
input rst,
input btn1,
input btn2,
input[7:0] sw,
output kimenet,
output[10:0] bitgen_dbg,
output[3:0] dbgki,
output startki,
output btn1enki,
output btn2enki
); |
wire en;
baud_gen baud_generator(.clk(clk), .rst(rst), .cy(en));
wire[10:0] swk_allasa;
bitgenerator bitgen(.sw(sw), .out(swk_allasa));
wire start;
wire btn1_en;
wire btn2_en;
btn1_pergesmentesito btn1_p(.btn(btn1), .clk(clk), .en(en), .btn1_en(btn1_en));
btn2_pergesmentesito btn2_p(.btn(btn2), .clk(clk), .en(en), .btn2_en(btn2_en));
assign start=(btn1_en||btn2_en);
assign startki=start;
assign btn1enki=btn1_en;
assign btn2enki=btn2_en;
wire[3:0] mpx_select;
bitcounter bitcntr(.start(start), .en(en), .clk(clk), .rst(rst), .out(mpx_select));
assign kimenet=swk_allasa[mpx_select];
assign bitgen_dbg=swk_allasa;
assign dbgki=mpx_select;
endmodule | 0 |
2,956 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function new(string name);
extern virtual task setup();
extern virtual protected task run_test();
extern virtual protected task miniTB_tests();
extern virtual task teardown();
extern virtual function void update_exit_status();
extern task run();
extern function void report();
extern local function void fail(string s);
extern task wait_for_error();
extern function integer get_error_count();
extern task give_up();
extern function bit fail_if(bit b, string s, string f, int l);
extern function bit fail_unless(bit b, string s, string f, int l);
extern function string get_name();
extern function results_t get_results();
endclass
function miniTB_logger::new(string name);
this.name = name;
endfunction | function new(string name); |
extern virtual task setup();
extern virtual protected task run_test();
extern virtual protected task miniTB_tests();
extern virtual task teardown();
extern virtual function void update_exit_status();
extern task run();
extern function void report();
extern local function void fail(string s);
extern task wait_for_error();
extern function integer get_error_count();
extern task give_up();
extern function bit fail_if(bit b, string s, string f, int l);
extern function bit fail_unless(bit b, string s, string f, int l);
extern function string get_name();
extern function results_t get_results();
endclass
function miniTB_logger::new(string name);
this.name = name;
endfunction | 8 |
2,957 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function void miniTB_logger::fail(string s);
error_count++;
`ERROR($psprintf("%s: FAIL", s));
endfunction | function void miniTB_logger::fail(string s); |
error_count++;
`ERROR($psprintf("%s: FAIL", s));
endfunction | 8 |
2,958 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function integer miniTB_logger::get_error_count();
return error_count;
endfunction | function integer miniTB_logger::get_error_count(); |
return error_count;
endfunction | 8 |
2,959 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function bit miniTB_logger::fail_if(bit b, string s, string f, int l);
if (b) begin
fail($psprintf("fail_if: %s (at %s line:%0d)", s, f, l));
return 1;
end
else begin
return 0;
end
endfunction | function bit miniTB_logger::fail_if(bit b, string s, string f, int l); |
if (b) begin
fail($psprintf("fail_if: %s (at %s line:%0d)", s, f, l));
return 1;
end
else begin
return 0;
end
endfunction | 8 |
2,960 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function bit miniTB_logger::fail_unless(bit b, string s, string f, int l);
if (!b) begin
fail($psprintf("fail_unless: %s (at %s line:%0d)", s, f, l));
return 1;
end
else begin
return 0;
end
endfunction | function bit miniTB_logger::fail_unless(bit b, string s, string f, int l); |
if (!b) begin
fail($psprintf("fail_unless: %s (at %s line:%0d)", s, f, l));
return 1;
end
else begin
return 0;
end
endfunction | 8 |
2,961 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function string miniTB_logger::get_name();
return name;
endfunction | function string miniTB_logger::get_name(); |
return name;
endfunction | 8 |
2,962 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function results_t miniTB_logger::get_results();
return success;
endfunction | function results_t miniTB_logger::get_results(); |
return success;
endfunction | 8 |
2,963 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function void miniTB_logger::report();
$display("\n");
if (success == PASS)
`INFO("MiniTB Exit Status: PASSED");
else
`INFO("MiniTB Exit Status: FAILED");
$display("\n");
endfunction | function void miniTB_logger::report(); |
$display("\n");
if (success == PASS)
`INFO("MiniTB Exit Status: PASSED");
else
`INFO("MiniTB Exit Status: FAILED");
$display("\n");
endfunction | 8 |
2,964 | data/full_repos/permissive/10200931/verilog/miniTB_logger.sv | 10,200,931 | miniTB_logger.sv | sv | 266 | 78 | [] | ['apache license'] | [] | null | line:25: before: "class" | null | 1: b'%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:25: Unsupported: classes\nclass miniTB_logger;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:39: Unsupported: \'local\' class item\n local int unsigned error_count = 0;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: Unsupported: \'local\' class item\n local results_t success;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:46: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local results_t success;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:56: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: virtual class member qualifier\n extern virtual task setup();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:58: Unsupported: extern class method prototype\n extern virtual task setup();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: virtual class member qualifier\n extern virtual protected task run_test();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:60: Unsupported: extern class method prototype\n extern virtual protected task run_test();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: virtual class member qualifier\n extern virtual protected task miniTB_tests();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:62: Unsupported: extern class method prototype\n extern virtual protected task miniTB_tests();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: virtual class member qualifier\n extern virtual task teardown();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:64: Unsupported: extern class method prototype\n extern virtual task teardown();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: virtual class member qualifier\n extern virtual function void update_exit_status();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:66: Unsupported: extern class method prototype\n extern virtual function void update_exit_status();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:68: Unsupported: extern class method prototype\n extern task run();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:69: Unsupported: extern class method prototype\n extern function void report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: \'local\' class item\n extern local function void fail(string s);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:71: Unsupported: extern class method prototype\n extern local function void fail(string s);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:73: Unsupported: extern class method prototype\n extern task wait_for_error();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:74: Unsupported: extern class method prototype\n extern function integer get_error_count();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:75: Unsupported: extern class method prototype\n extern task give_up();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:77: Unsupported: extern class method prototype\n extern function bit fail_if(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:78: Unsupported: extern class method prototype\n extern function bit fail_unless(bit b, string s, string f, int l);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:80: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:81: syntax error, unexpected IDENTIFIER, expecting \';\'\n extern function results_t get_results();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Hierarchical class references\nfunction miniTB_logger::new(string name);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped class reference\nfunction miniTB_logger::new(string name);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: scoped new constructor\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:95: Unsupported: this\n this.name = name;\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Hierarchical class references\nfunction void miniTB_logger::fail(string s);\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: scoped class reference\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:94: Unsupported: Out of class block function declaration\nfunction miniTB_logger::new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Define or directive not defined: \'`ERROR\'\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: Unsupported or unknown PLI call: $psprintf\n `ERROR($psprintf("%s: FAIL", s));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:108: syntax error, unexpected \';\'\n `ERROR($psprintf("%s: FAIL", s));\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Hierarchical class references\ntask miniTB_logger::wait_for_error();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: scoped class reference\ntask miniTB_logger::wait_for_error();\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:106: Unsupported: Out of class block function declaration\nfunction void miniTB_logger::fail(string s);\n ^~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:118: syntax error, unexpected \'@\'\n @(error_count);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Hierarchical class references\nfunction integer miniTB_logger::get_error_count();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: scoped class reference\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:117: Unsupported: Out of class block function declaration\ntask miniTB_logger::wait_for_error();\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: Hierarchical class references\ntask miniTB_logger::give_up();\n ^~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:135: Unsupported: scoped class reference\ntask miniTB_logger::give_up();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:126: Unsupported: Out of class block function declaration\nfunction integer miniTB_logger::get_error_count();\n ^~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:136: Unsupported: event data types\n event never;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:137: syntax error, unexpected \'@\'\n @(never);\n ^\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_logger.sv:152: Unsupported: Hierarchical class references\nfunction bit miniTB_logger::fail_if(bit b, string s, string f, int l);\n ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 574 | function | function void miniTB_logger::update_exit_status();
if (error_count == 0)
success = PASS;
else
success = FAIL;
endfunction | function void miniTB_logger::update_exit_status(); |
if (error_count == 0)
success = PASS;
else
success = FAIL;
endfunction | 8 |
2,965 | data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv | 10,200,931 | miniTB_testrunner.sv | sv | 101 | 72 | [] | ['apache license'] | [] | null | line:26: before: "class" | null | 1: b"%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: Unsupported: classes\nclass miniTB_testrunner;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: Unsupported: 'local' class item\n local miniTB_testsuite list_of_suites[$];\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local miniTB_testsuite list_of_suites[$];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:46: Unsupported: 'local' class item\n local results_t success = PASS;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:50: syntax error, unexpected IDENTIFIER, expecting ')'\n extern function void add_testsuite(miniTB_testsuite suite);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:51: Unsupported: extern class method prototype\n extern task report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:52: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: Internal Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: ../V3ParseSym.h:114: Symbols suggest ending TASK 'add_testsuite' but parser thinks ending CLASS 'miniTB_testrunner'\nclass miniTB_testrunner;\n^~~~~\n ... See the manual and https://verilator.org for more assistance.\n" | 576 | function | function new(string name);
extern function void add_testsuite(miniTB_testsuite suite);
extern task report();
extern function string get_name();
endclass
function miniTB_testrunner::new(string name);
this.name = name;
endfunction | function new(string name); |
extern function void add_testsuite(miniTB_testsuite suite);
extern task report();
extern function string get_name();
endclass
function miniTB_testrunner::new(string name);
this.name = name;
endfunction | 8 |
2,966 | data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv | 10,200,931 | miniTB_testrunner.sv | sv | 101 | 72 | [] | ['apache license'] | [] | null | line:26: before: "class" | null | 1: b"%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: Unsupported: classes\nclass miniTB_testrunner;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: Unsupported: 'local' class item\n local miniTB_testsuite list_of_suites[$];\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local miniTB_testsuite list_of_suites[$];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:46: Unsupported: 'local' class item\n local results_t success = PASS;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:50: syntax error, unexpected IDENTIFIER, expecting ')'\n extern function void add_testsuite(miniTB_testsuite suite);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:51: Unsupported: extern class method prototype\n extern task report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:52: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: Internal Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: ../V3ParseSym.h:114: Symbols suggest ending TASK 'add_testsuite' but parser thinks ending CLASS 'miniTB_testrunner'\nclass miniTB_testrunner;\n^~~~~\n ... See the manual and https://verilator.org for more assistance.\n" | 576 | function | function void miniTB_testrunner::add_testsuite(miniTB_testsuite suite);
list_of_suites.push_back(suite);
endfunction | function void miniTB_testrunner::add_testsuite(miniTB_testsuite suite); |
list_of_suites.push_back(suite);
endfunction | 8 |
2,967 | data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv | 10,200,931 | miniTB_testrunner.sv | sv | 101 | 72 | [] | ['apache license'] | [] | null | line:26: before: "class" | null | 1: b"%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: Unsupported: classes\nclass miniTB_testrunner;\n^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: Unsupported: 'local' class item\n local miniTB_testsuite list_of_suites[$];\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:39: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n local miniTB_testsuite list_of_suites[$];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:46: Unsupported: 'local' class item\n local results_t success = PASS;\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: new constructor\n extern function new(string name);\n ^~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:49: Unsupported: extern class\n extern function new(string name);\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:50: syntax error, unexpected IDENTIFIER, expecting ')'\n extern function void add_testsuite(miniTB_testsuite suite);\n ^~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:51: Unsupported: extern class method prototype\n extern task report();\n ^~~~~~\n%Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:52: Unsupported: extern class method prototype\n extern function string get_name();\n ^~~~~~\n%Error: Internal Error: data/full_repos/permissive/10200931/verilog/miniTB_testrunner.sv:26: ../V3ParseSym.h:114: Symbols suggest ending TASK 'add_testsuite' but parser thinks ending CLASS 'miniTB_testrunner'\nclass miniTB_testrunner;\n^~~~~\n ... See the manual and https://verilator.org for more assistance.\n" | 576 | function | function string miniTB_testrunner::get_name();
return name;
endfunction | function string miniTB_testrunner::get_name(); |
return name;
endfunction | 8 |
2,976 | data/full_repos/permissive/102039998/control.v | 102,039,998 | control.v | v | 117 | 102 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/102039998/control.v:1: Cannot find include file: mips.h\n`include "mips.h" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.sv\n mips.h\n mips.h.v\n mips.h.sv\n obj_dir/mips.h\n obj_dir/mips.h.v\n obj_dir/mips.h.sv\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ADDI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ORI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`LW\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`J\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`JAL\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BEQ\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BNE\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:34: Define or directive not defined: \'`LW\'\n memread <= (opcode ==`LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memread <= (opcode ==`LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:37: Define or directive not defined: \'`LW\'\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`AND\'\n `AND: aluop = `ALU_AND;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:41: syntax error, unexpected \':\', expecting endcase\n `AND: aluop = `ALU_AND;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`ALU_AND\'\n `AND: aluop = `ALU_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`OR\'\n `OR: aluop = `ALU_OR;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`ALU_OR\'\n `OR: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ORI\'\n `ORI: aluop = `ALU_OR;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ALU_OR\'\n `ORI: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ADD\'\n `ADD: aluop = `ALU_add;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ALU_add\'\n `ADD: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ADDI\'\n `ADDI: aluop = `ALU_add;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ALU_add\'\n `ADDI: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ADDIU\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ALU_add\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`LW\'\n `LW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`ALU_add\'\n `LW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`SW\'\n `SW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`ALU_add\'\n `SW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`SUB\'\n `SUB: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`ALU_sub\'\n `SUB: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`BEQ\'\n `BEQ: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`ALU_sub\'\n `BEQ: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`BNE\'\n `BNE: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`ALU_sub\'\n `BNE: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`SLT\'\n `SLT: aluop = `ALU_slt;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`ALU_slt\'\n `SLT: aluop = `ALU_slt;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:53: Define or directive not defined: \'`ALU_undef\'\n : ... Suggested alternative: \'`undef\'\n default: aluop = `ALU_undef;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:59: Define or directive not defined: \'`SW\'\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDIU\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ORI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`LW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`SW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:64: Define or directive not defined: \'`SW\'\n regwrite <= (opcode == `SW||opcode == `BEQ||opcode == `BNE||opcode == `J||opcode == `JR) ? 0 : 1;\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 582 | module | module control (input [31:26] opcode,
output reg regdst,jump,
branch,memread,memtoreg,
output reg [3:0] aluop,
output reg rtype, memwrite,
alusrc,regwrite,invertzero);
initial begin
regdst <= 0;
jump <= 0;
branch <= 0;
memread <= 0;
memtoreg <= 0;
aluop <= 0;
rtype <= 0;
memwrite <= 0;
alusrc <= 0;
regwrite <= 0;
invertzero <= 0;
end
always @(opcode) begin
regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;
jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;
branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;
memread <= (opcode ==`LW) ? 1 : 0;
memtoreg <= (opcode == `LW) ? 1 : 0;
case(opcode)
`AND: aluop = `ALU_AND;
`OR: aluop = `ALU_OR;
`ORI: aluop = `ALU_OR;
`ADD: aluop = `ALU_add;
`ADDI: aluop = `ALU_add;
`ADDIU: aluop = `ALU_add;
`LW: aluop = `ALU_add;
`SW: aluop = `ALU_add;
`SUB: aluop = `ALU_sub;
`BEQ: aluop = `ALU_sub;
`BNE: aluop = `ALU_sub;
`SLT: aluop = `ALU_slt;
default: aluop = `ALU_undef;
endcase;
rtype <= (opcode == 6'h0) ? 1 : 0;
memwrite <= (opcode ==`SW) ? 1 : 0;
alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;
regwrite <= (opcode == `SW||opcode == `BEQ||opcode == `BNE||opcode == `J||opcode == `JR) ? 0 : 1;
regdst <= (opcode == `ADDI||opcode == `ADDIU||opcode == `LW||opcode == `ORI) ? 0 : 1;
invertzero <= (opcode == `BNE) ? 1 : 0;
end
endmodule | module control (input [31:26] opcode,
output reg regdst,jump,
branch,memread,memtoreg,
output reg [3:0] aluop,
output reg rtype, memwrite,
alusrc,regwrite,invertzero); |
initial begin
regdst <= 0;
jump <= 0;
branch <= 0;
memread <= 0;
memtoreg <= 0;
aluop <= 0;
rtype <= 0;
memwrite <= 0;
alusrc <= 0;
regwrite <= 0;
invertzero <= 0;
end
always @(opcode) begin
regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;
jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;
branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;
memread <= (opcode ==`LW) ? 1 : 0;
memtoreg <= (opcode == `LW) ? 1 : 0;
case(opcode)
`AND: aluop = `ALU_AND;
`OR: aluop = `ALU_OR;
`ORI: aluop = `ALU_OR;
`ADD: aluop = `ALU_add;
`ADDI: aluop = `ALU_add;
`ADDIU: aluop = `ALU_add;
`LW: aluop = `ALU_add;
`SW: aluop = `ALU_add;
`SUB: aluop = `ALU_sub;
`BEQ: aluop = `ALU_sub;
`BNE: aluop = `ALU_sub;
`SLT: aluop = `ALU_slt;
default: aluop = `ALU_undef;
endcase;
rtype <= (opcode == 6'h0) ? 1 : 0;
memwrite <= (opcode ==`SW) ? 1 : 0;
alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;
regwrite <= (opcode == `SW||opcode == `BEQ||opcode == `BNE||opcode == `J||opcode == `JR) ? 0 : 1;
regdst <= (opcode == `ADDI||opcode == `ADDIU||opcode == `LW||opcode == `ORI) ? 0 : 1;
invertzero <= (opcode == `BNE) ? 1 : 0;
end
endmodule | 2 |
2,977 | data/full_repos/permissive/102039998/control.v | 102,039,998 | control.v | v | 117 | 102 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/102039998/control.v:1: Cannot find include file: mips.h\n`include "mips.h" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.sv\n mips.h\n mips.h.v\n mips.h.sv\n obj_dir/mips.h\n obj_dir/mips.h.v\n obj_dir/mips.h.sv\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ADDI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ORI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`LW\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`J\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`JAL\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BEQ\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BNE\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:34: Define or directive not defined: \'`LW\'\n memread <= (opcode ==`LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memread <= (opcode ==`LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:37: Define or directive not defined: \'`LW\'\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`AND\'\n `AND: aluop = `ALU_AND;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:41: syntax error, unexpected \':\', expecting endcase\n `AND: aluop = `ALU_AND;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`ALU_AND\'\n `AND: aluop = `ALU_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`OR\'\n `OR: aluop = `ALU_OR;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`ALU_OR\'\n `OR: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ORI\'\n `ORI: aluop = `ALU_OR;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ALU_OR\'\n `ORI: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ADD\'\n `ADD: aluop = `ALU_add;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ALU_add\'\n `ADD: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ADDI\'\n `ADDI: aluop = `ALU_add;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ALU_add\'\n `ADDI: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ADDIU\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ALU_add\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`LW\'\n `LW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`ALU_add\'\n `LW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`SW\'\n `SW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`ALU_add\'\n `SW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`SUB\'\n `SUB: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`ALU_sub\'\n `SUB: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`BEQ\'\n `BEQ: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`ALU_sub\'\n `BEQ: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`BNE\'\n `BNE: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`ALU_sub\'\n `BNE: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`SLT\'\n `SLT: aluop = `ALU_slt;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`ALU_slt\'\n `SLT: aluop = `ALU_slt;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:53: Define or directive not defined: \'`ALU_undef\'\n : ... Suggested alternative: \'`undef\'\n default: aluop = `ALU_undef;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:59: Define or directive not defined: \'`SW\'\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDIU\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ORI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`LW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`SW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:64: Define or directive not defined: \'`SW\'\n regwrite <= (opcode == `SW||opcode == `BEQ||opcode == `BNE||opcode == `J||opcode == `JR) ? 0 : 1;\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 582 | module | module ALU_control (input [3:0] aluop_from_control,
input [5:0] functioncode,
input rtype,
output reg [3:0] aluop_out);
always @(*) begin
if (rtype) begin
case(functioncode)
`AND: aluop_out = `ALU_AND;
`OR: aluop_out = `ALU_OR;
`ORI: aluop_out = `ALU_OR;
`ADD: aluop_out = `ALU_add;
`ADDI: aluop_out = `ALU_add;
`ADDU: aluop_out = `ALU_add;
`LW: aluop_out = `ALU_add;
`SW: aluop_out = `ALU_add;
`SUB: aluop_out = `ALU_sub;
`BEQ: aluop_out = `ALU_sub;
`BNE: aluop_out = `ALU_sub;
`SLT: aluop_out = `ALU_slt;
`SYSCALL: aluop_out = `ALU_add;
default: aluop_out = `ALU_undef;
endcase
end
else begin
aluop_out = aluop_from_control;
end
end
endmodule | module ALU_control (input [3:0] aluop_from_control,
input [5:0] functioncode,
input rtype,
output reg [3:0] aluop_out); |
always @(*) begin
if (rtype) begin
case(functioncode)
`AND: aluop_out = `ALU_AND;
`OR: aluop_out = `ALU_OR;
`ORI: aluop_out = `ALU_OR;
`ADD: aluop_out = `ALU_add;
`ADDI: aluop_out = `ALU_add;
`ADDU: aluop_out = `ALU_add;
`LW: aluop_out = `ALU_add;
`SW: aluop_out = `ALU_add;
`SUB: aluop_out = `ALU_sub;
`BEQ: aluop_out = `ALU_sub;
`BNE: aluop_out = `ALU_sub;
`SLT: aluop_out = `ALU_slt;
`SYSCALL: aluop_out = `ALU_add;
default: aluop_out = `ALU_undef;
endcase
end
else begin
aluop_out = aluop_from_control;
end
end
endmodule | 2 |
2,978 | data/full_repos/permissive/102039998/control.v | 102,039,998 | control.v | v | 117 | 102 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/102039998/control.v:1: Cannot find include file: mips.h\n`include "mips.h" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/mips.h.sv\n mips.h\n mips.h.v\n mips.h.sv\n obj_dir/mips.h\n obj_dir/mips.h.v\n obj_dir/mips.h.sv\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ADDI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`ORI\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:25: Define or directive not defined: \'`LW\'\n regdst <= (opcode == `ADDI || opcode == `ORI || opcode == `LW) ? 0 : 1;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`J\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:28: Define or directive not defined: \'`JAL\'\n jump <= (opcode == `J||opcode == `JAL) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BEQ\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:31: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:31: Define or directive not defined: \'`BNE\'\n branch <= (opcode ==`BEQ||opcode == `BNE) ? 1 : 0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:34: Define or directive not defined: \'`LW\'\n memread <= (opcode ==`LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memread <= (opcode ==`LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:37: Define or directive not defined: \'`LW\'\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memtoreg <= (opcode == `LW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`AND\'\n `AND: aluop = `ALU_AND;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:41: syntax error, unexpected \':\', expecting endcase\n `AND: aluop = `ALU_AND;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:41: Define or directive not defined: \'`ALU_AND\'\n `AND: aluop = `ALU_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`OR\'\n `OR: aluop = `ALU_OR;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:42: Define or directive not defined: \'`ALU_OR\'\n `OR: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ORI\'\n `ORI: aluop = `ALU_OR;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:43: Define or directive not defined: \'`ALU_OR\'\n `ORI: aluop = `ALU_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ADD\'\n `ADD: aluop = `ALU_add;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:44: Define or directive not defined: \'`ALU_add\'\n `ADD: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ADDI\'\n `ADDI: aluop = `ALU_add;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:45: Define or directive not defined: \'`ALU_add\'\n `ADDI: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ADDIU\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:46: Define or directive not defined: \'`ALU_add\'\n `ADDIU: aluop = `ALU_add; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`LW\'\n `LW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:47: Define or directive not defined: \'`ALU_add\'\n `LW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`SW\'\n `SW: aluop = `ALU_add;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:48: Define or directive not defined: \'`ALU_add\'\n `SW: aluop = `ALU_add;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`SUB\'\n `SUB: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:49: Define or directive not defined: \'`ALU_sub\'\n `SUB: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`BEQ\'\n `BEQ: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:50: Define or directive not defined: \'`ALU_sub\'\n `BEQ: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`BNE\'\n `BNE: aluop = `ALU_sub;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:51: Define or directive not defined: \'`ALU_sub\'\n `BNE: aluop = `ALU_sub;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`SLT\'\n `SLT: aluop = `ALU_slt;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:52: Define or directive not defined: \'`ALU_slt\'\n `SLT: aluop = `ALU_slt;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:53: Define or directive not defined: \'`ALU_undef\'\n : ... Suggested alternative: \'`undef\'\n default: aluop = `ALU_undef;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:59: Define or directive not defined: \'`SW\'\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n memwrite <= (opcode ==`SW) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ADDIU\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`ORI\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`LW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:62: Define or directive not defined: \'`SW\'\n alusrc <= (opcode==`ADDI||opcode == `ADDIU||opcode==`ORI||opcode==`LW||opcode==`SW)?1:0;\n ^~~\n%Error: data/full_repos/permissive/102039998/control.v:64: Define or directive not defined: \'`SW\'\n regwrite <= (opcode == `SW||opcode == `BEQ||opcode == `BNE||opcode == `J||opcode == `JR) ? 0 : 1;\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 582 | module | module SYSCALL_controller(input [31:0]instruction, input clk, output reg syscall);
initial
syscall <= 0;
always @(negedge clk) begin
syscall = (instruction == {28'h0,`SYSCALL}) ? 1 : 0;
end
endmodule | module SYSCALL_controller(input [31:0]instruction, input clk, output reg syscall); |
initial
syscall <= 0;
always @(negedge clk) begin
syscall = (instruction == {28'h0,`SYSCALL}) ? 1 : 0;
end
endmodule | 2 |
2,991 | data/full_repos/permissive/102039998/tests.v | 102,039,998 | tests.v | v | 99 | 102 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/102039998/tests.v:1: Cannot find include file: processor.v\n`include "processor.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.sv\n processor.v\n processor.v.v\n processor.v.sv\n obj_dir/processor.v\n obj_dir/processor.v.v\n obj_dir/processor.v.sv\n%Error: data/full_repos/permissive/102039998/tests.v:2: Cannot find include file: mips.h\n`include "mips.h" \n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: Define or directive not defined: \'`op\'\n control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rs\'\n registers register_file(instruction[`rs], instruction[`rt],\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n registers register_file(instruction[`rs], instruction[`rt],\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rt\'\n registers register_file(instruction[`rs], instruction[`rt],\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rd\'\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rt\'\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: Define or directive not defined: \'`function\'\n ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:57: Define or directive not defined: \'`target\'\n jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:77: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("processor.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:78: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, processor);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102039998/tests.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2000; $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 16 error(s), 1 warning(s)\n' | 584 | module | module complete_processor(output [31:0] instruction, output clock);
wire clock;
wire [31:0] pc_adder_mux, branch_adder_mux;
wire [31:0] mux_pc;
wire [31:0] instruction;
reg [31:0] four;
wire [31:0] address;
wire [31:0] jump_address, branch_address;
wire [3:0] aluop_from_control, aluop_to_alu;
wire [31:0] read_data1,read_data2, alusrc_mux_output, alu_result;
wire regdst, jump, branch, memread, memtoreg, rtype, regwrite, alusrc, memwrite, invertzero;
wire syscall;
wire branch_zero_and_output, branch_mux_control;
wire [4:0] regdst_mux_output;
wire [31:0] memtoreg_mux_output;
wire [31:0] read_data;
clock_gen clk(clock);
PC p_counter(mux_pc, clock, address);
adder pc_incrementer(address, four, pc_adder_mux);
instruction_memory imem(address, instruction);
control control(instruction[`op], regdst, jump, branch, memread, memtoreg,
aluop_from_control, rtype, memwrite, alusrc, regwrite, invertzero);
SYSCALL_controller syscaller(instruction, clock, syscall);
registers register_file(instruction[`rs], instruction[`rt],
regdst_mux_output, memtoreg_mux_output,
regwrite, syscall, clock,
read_data1, read_data2);
mux32_2 memtoreg_mux(read_data, alu_result, memtoreg, memtoreg_mux_output);
mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);
data_memory dmem(alu_result, read_data2, memwrite, memread, clock, read_data);
ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);
ALU alu(aluop_to_alu, read_data1, alusrc_mux_output, alu_result, zero);
mux32_2 alusrc_mux({16'h0, instruction[15:0]},
read_data2, alusrc, alusrc_mux_output);
mux32_2 jump_mux(jump_address, branch_address, jump, mux_pc);
jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);
and1_2 branch_zero_and(branch, zero, branch_zero_and_output);
inverter invertzero_inverter(branch_zero_and_output, invertzero, branch_mux_control);
mux32_2 branch_mux(branch_adder_mux, pc_adder_mux, branch_mux_control, branch_address);
adder branch_adder(pc_adder_mux,
{16'h0, instruction[15:0]}<<2,
branch_adder_mux);
initial
four = 4;
endmodule | module complete_processor(output [31:0] instruction, output clock); |
wire clock;
wire [31:0] pc_adder_mux, branch_adder_mux;
wire [31:0] mux_pc;
wire [31:0] instruction;
reg [31:0] four;
wire [31:0] address;
wire [31:0] jump_address, branch_address;
wire [3:0] aluop_from_control, aluop_to_alu;
wire [31:0] read_data1,read_data2, alusrc_mux_output, alu_result;
wire regdst, jump, branch, memread, memtoreg, rtype, regwrite, alusrc, memwrite, invertzero;
wire syscall;
wire branch_zero_and_output, branch_mux_control;
wire [4:0] regdst_mux_output;
wire [31:0] memtoreg_mux_output;
wire [31:0] read_data;
clock_gen clk(clock);
PC p_counter(mux_pc, clock, address);
adder pc_incrementer(address, four, pc_adder_mux);
instruction_memory imem(address, instruction);
control control(instruction[`op], regdst, jump, branch, memread, memtoreg,
aluop_from_control, rtype, memwrite, alusrc, regwrite, invertzero);
SYSCALL_controller syscaller(instruction, clock, syscall);
registers register_file(instruction[`rs], instruction[`rt],
regdst_mux_output, memtoreg_mux_output,
regwrite, syscall, clock,
read_data1, read_data2);
mux32_2 memtoreg_mux(read_data, alu_result, memtoreg, memtoreg_mux_output);
mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);
data_memory dmem(alu_result, read_data2, memwrite, memread, clock, read_data);
ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);
ALU alu(aluop_to_alu, read_data1, alusrc_mux_output, alu_result, zero);
mux32_2 alusrc_mux({16'h0, instruction[15:0]},
read_data2, alusrc, alusrc_mux_output);
mux32_2 jump_mux(jump_address, branch_address, jump, mux_pc);
jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);
and1_2 branch_zero_and(branch, zero, branch_zero_and_output);
inverter invertzero_inverter(branch_zero_and_output, invertzero, branch_mux_control);
mux32_2 branch_mux(branch_adder_mux, pc_adder_mux, branch_mux_control, branch_address);
adder branch_adder(pc_adder_mux,
{16'h0, instruction[15:0]}<<2,
branch_adder_mux);
initial
four = 4;
endmodule | 2 |
2,992 | data/full_repos/permissive/102039998/tests.v | 102,039,998 | tests.v | v | 99 | 102 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/102039998/tests.v:1: Cannot find include file: processor.v\n`include "processor.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.v\n data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.sv\n processor.v\n processor.v.v\n processor.v.sv\n obj_dir/processor.v\n obj_dir/processor.v.v\n obj_dir/processor.v.sv\n%Error: data/full_repos/permissive/102039998/tests.v:2: Cannot find include file: mips.h\n`include "mips.h" \n ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: Define or directive not defined: \'`op\'\n control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rs\'\n registers register_file(instruction[`rs], instruction[`rt],\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n registers register_file(instruction[`rs], instruction[`rt],\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rt\'\n registers register_file(instruction[`rs], instruction[`rt],\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rd\'\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rt\'\n mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: Define or directive not defined: \'`function\'\n ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:57: Define or directive not defined: \'`target\'\n jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n ^~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n ^\n%Error: data/full_repos/permissive/102039998/tests.v:77: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("processor.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:78: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, processor);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102039998/tests.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2000; $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 16 error(s), 1 warning(s)\n' | 584 | module | module test;
wire [31:0] instruction;
wire clock;
complete_processor processor(instruction, clock);
initial begin
$dumpfile("processor.vcd");
$dumpvars(0, processor);
#2000; $finish;
end
endmodule | module test; |
wire [31:0] instruction;
wire clock;
complete_processor processor(instruction, clock);
initial begin
$dumpfile("processor.vcd");
$dumpvars(0, processor);
#2000; $finish;
end
endmodule | 2 |
2,993 | data/full_repos/permissive/102197798/f_calculator.v | 102,197,798 | f_calculator.v | v | 17 | 89 | [] | [] | [] | [(1, 16)] | null | null | 1: b"%Error: data/full_repos/permissive/102197798/f_calculator.v:2: Input/output/inout declaration not found for port: 'llr_a'\n llr_a, \n ^~~~~\n%Error: data/full_repos/permissive/102197798/f_calculator.v:3: Input/output/inout declaration not found for port: 'llr_b'\n llr_b, \n ^~~~~\n%Error: data/full_repos/permissive/102197798/f_calculator.v:6: Input/output/inout does not appear in port list: 'first_channel'\n input [31:0] first_channel;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102197798/f_calculator.v:7: Input/output/inout does not appear in port list: 'second_channel'\n input [31:0] second_channel;\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 585 | module | module f_calculator(
llr_a,
llr_b,
f_result
);
input [31:0] first_channel;
input [31:0] second_channel;
output [31:0] f_result;
always @ (*)
begin
end
endmodule | module f_calculator(
llr_a,
llr_b,
f_result
); |
input [31:0] first_channel;
input [31:0] second_channel;
output [31:0] f_result;
always @ (*)
begin
end
endmodule | 1 |
2,996 | data/full_repos/permissive/102261675/src/nexys4/toplevel.v | 102,261,675 | toplevel.v | v | 31 | 49 | [] | [] | [] | [(3, 30)] | null | null | 1: b"%Error: data/full_repos/permissive/102261675/src/nexys4/toplevel.v:17: Cannot find file containing module: 'Murax'\n Murax murax ( \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/102261675/src/nexys4,data/full_repos/permissive/102261675/Murax\n data/full_repos/permissive/102261675/src/nexys4,data/full_repos/permissive/102261675/Murax.v\n data/full_repos/permissive/102261675/src/nexys4,data/full_repos/permissive/102261675/Murax.sv\n Murax\n Murax.v\n Murax.sv\n obj_dir/Murax\n obj_dir/Murax.v\n obj_dir/Murax.sv\n%Error: Exiting due to 1 error(s)\n" | 588 | module | module toplevel(
input io_e3,
input io_c12,
output io_c4,
input io_d4,
output [7:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
assign io_led = io_gpioA_write[7 : 0];
Murax murax (
.io_asyncReset(0),
.io_mainClk (io_e3),
.io_jtag_tck(0),
.io_jtag_tdi(0),
.io_jtag_tdo(0),
.io_jtag_tms(0),
.io_gpioA_read(io_gpioA_read),
.io_gpioA_write(io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_c4),
.io_uart_rxd(io_d4)
);
endmodule | module toplevel(
input io_e3,
input io_c12,
output io_c4,
input io_d4,
output [7:0] io_led
); |
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
assign io_led = io_gpioA_write[7 : 0];
Murax murax (
.io_asyncReset(0),
.io_mainClk (io_e3),
.io_jtag_tck(0),
.io_jtag_tdi(0),
.io_jtag_tdo(0),
.io_jtag_tms(0),
.io_gpioA_read(io_gpioA_read),
.io_gpioA_write(io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_c4),
.io_uart_rxd(io_d4)
);
endmodule | 0 |
3,002 | data/full_repos/permissive/102388603/pwm2digit.v | 102,388,603 | pwm2digit.v | v | 52 | 36 | [] | [] | [] | [(3, 38)] | null | data/verilator_xmls/7bdcb843-be75-49b8-9c71-3d14afe7e87a.xml | null | 594 | module | module pwm2digit#(parameter N=8)
(
input in,
output reg [N-1:0] out,
input clk,
input rst
);
reg [N-1:0]count;
reg [N-1:0] countPeriod;
always @(posedge clk, posedge rst)
if(rst)
count <= 0;
else
count <= count + 1;
always @(posedge clk, posedge rst)
if(rst)
begin
out <= 0;
countPeriod <= 0;
end
else
begin
if(count == 0)
begin
countPeriod <= 0;
out <= countPeriod;
end
else if(in)
countPeriod <= countPeriod + 1;
end
endmodule | module pwm2digit#(parameter N=8)
(
input in,
output reg [N-1:0] out,
input clk,
input rst
); |
reg [N-1:0]count;
reg [N-1:0] countPeriod;
always @(posedge clk, posedge rst)
if(rst)
count <= 0;
else
count <= count + 1;
always @(posedge clk, posedge rst)
if(rst)
begin
out <= 0;
countPeriod <= 0;
end
else
begin
if(count == 0)
begin
countPeriod <= 0;
out <= countPeriod;
end
else if(in)
countPeriod <= countPeriod + 1;
end
endmodule | 5 |
3,005 | data/full_repos/permissive/102388603/rmii_rx_byte.v | 102,388,603 | rmii_rx_byte.v | v | 111 | 202 | [] | [] | [] | [(3, 109)] | null | data/verilator_xmls/33c905a7-bc2d-4d49-b9a7-c12e97671a6b.xml | null | 597 | module | module rmii_rx_byte
(
input rst,
input clk,
input rmii_clk,
input fast_eth,
input [1:0]rm_rx_data,
input rm_crs_dv,
output reg [7:0]data,
output reg rdy,
output reg busy
);
reg [1:0]s_rm_rx_data;
reg s_rm_crs_dv;
reg s_rmii_clk;
always @(posedge rst, posedge clk)
if(rst)
{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= 0;
else
{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= {rm_rx_data, rm_crs_dv, rmii_clk};
reg [4:0]wait_cnt;
reg [7:0]rx_data;
reg [1:0]stop;
always @(posedge rst, posedge clk)
begin
if(rst)
begin
data <= 0;
rx_data <= 0;
wait_cnt <= 0;
rdy <= 0;
busy <= 0;
stop <= 0;
end
else
begin
if(rdy)
rdy <= 0;
if(wait_cnt == 0)
begin
if(!busy)
begin
stop <= 0;
if(s_rm_crs_dv)
begin
if(s_rmii_clk)
begin
if(rx_data == 8'hD5)
begin
busy <= 1;
rx_data <= {s_rm_rx_data, 6'b11_0000};
end
else
rx_data <= {s_rm_rx_data, rx_data[7:2]};
if(!fast_eth)
wait_cnt <= 18;
end
end
else
rx_data <= 0;
end
else
begin
if((s_rm_crs_dv) | (stop == 2'b01))
begin
if(s_rmii_clk)
begin
if(rx_data[1:0] == 2'b11)
begin
data <= {s_rm_rx_data, rx_data[7:2]};
rx_data <= 8'b11_00_0000;
if(stop==2'b01)
stop <= 2'b10;
rdy <= 1;
end
else
rx_data <= {s_rm_rx_data, rx_data[7:2]};
if(!fast_eth)
wait_cnt <= 18;
end
end
else
begin
if((fast_eth )|(stop == 2'b10))
begin
stop <= 0;
busy <= 0;
rx_data <= 0;
end
else
stop <= 2'b01;
end
end
end
else
wait_cnt <= wait_cnt - 1;
end
end
endmodule | module rmii_rx_byte
(
input rst,
input clk,
input rmii_clk,
input fast_eth,
input [1:0]rm_rx_data,
input rm_crs_dv,
output reg [7:0]data,
output reg rdy,
output reg busy
); |
reg [1:0]s_rm_rx_data;
reg s_rm_crs_dv;
reg s_rmii_clk;
always @(posedge rst, posedge clk)
if(rst)
{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= 0;
else
{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= {rm_rx_data, rm_crs_dv, rmii_clk};
reg [4:0]wait_cnt;
reg [7:0]rx_data;
reg [1:0]stop;
always @(posedge rst, posedge clk)
begin
if(rst)
begin
data <= 0;
rx_data <= 0;
wait_cnt <= 0;
rdy <= 0;
busy <= 0;
stop <= 0;
end
else
begin
if(rdy)
rdy <= 0;
if(wait_cnt == 0)
begin
if(!busy)
begin
stop <= 0;
if(s_rm_crs_dv)
begin
if(s_rmii_clk)
begin
if(rx_data == 8'hD5)
begin
busy <= 1;
rx_data <= {s_rm_rx_data, 6'b11_0000};
end
else
rx_data <= {s_rm_rx_data, rx_data[7:2]};
if(!fast_eth)
wait_cnt <= 18;
end
end
else
rx_data <= 0;
end
else
begin
if((s_rm_crs_dv) | (stop == 2'b01))
begin
if(s_rmii_clk)
begin
if(rx_data[1:0] == 2'b11)
begin
data <= {s_rm_rx_data, rx_data[7:2]};
rx_data <= 8'b11_00_0000;
if(stop==2'b01)
stop <= 2'b10;
rdy <= 1;
end
else
rx_data <= {s_rm_rx_data, rx_data[7:2]};
if(!fast_eth)
wait_cnt <= 18;
end
end
else
begin
if((fast_eth )|(stop == 2'b10))
begin
stop <= 0;
busy <= 0;
rx_data <= 0;
end
else
stop <= 2'b01;
end
end
end
else
wait_cnt <= wait_cnt - 1;
end
end
endmodule | 5 |
3,006 | data/full_repos/permissive/102388603/rmii_send_pack.v | 102,388,603 | rmii_send_pack.v | v | 93 | 164 | [] | [] | [] | [(5, 91)] | null | null | 1: b'%Error: data/full_repos/permissive/102388603/rmii_send_pack.v:18: Cannot find file containing module: \'timer\'\ntimer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer.v\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer.sv\n timer\n timer.v\n timer.sv\n obj_dir/timer\n obj_dir/timer.v\n obj_dir/timer.sv\n%Error: data/full_repos/permissive/102388603/rmii_send_pack.v:38: Cannot find file containing module: \'rmii_tx\'\nrmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/102388603/rmii_send_pack.v:66: Bit extraction of array[71:0] requires 7 bit index, not 16 bits.\n : ... In instance rmii_send_pack\n byteSendRmii <= packUDP[countByteSend]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/rmii_send_pack.v:80: Bit extraction of array[71:0] requires 7 bit index, not 16 bits.\n : ... In instance rmii_send_pack\n byteSendRmii <= packUDP[countByteSend]; \n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 598 | module | module rmii_send_pack
( input clk,
input nrst,
output [1:0]PhyTxd,
output reg PhyClk50Mhz,
output PhyTxEn,
output reg PhyRstn);
wire rst;
assign rst = ~nrst;
wire start;
timer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));
parameter lenPack = 72;
reg [7:0]packUDP[0:lenPack-1];
initial $readmemh("packUDP.hex",packUDP);
reg [15:0]countByteSend;
reg [7:0]byteSendRmii;
reg startSendRmii;
always @(posedge clk, posedge rst)
if(rst)
PhyClk50Mhz <= 0;
else
PhyClk50Mhz <= ~PhyClk50Mhz;
wire getByte;
wire readyRMII;
rmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),
.ready(readyRMII), .dataOut(PhyTxd), .TXEN(PhyTxEn), .getByte(getByte));
reg [1:0] state;
parameter idle = 2'b00;
parameter send = 2'b01;
reg tmpGetByte;
always @(posedge clk, posedge rst)
if(rst)
begin
countByteSend <= 0;
byteSendRmii <= 0;
startSendRmii <= 0;
state <= idle;
tmpGetByte <= 0;
PhyRstn <= 0;
end
else
begin
PhyRstn <= 1;
tmpGetByte <= getByte;
case(state)
idle:
begin
if(start)
begin
countByteSend <= 1;
byteSendRmii <= packUDP[countByteSend];
startSendRmii <= 1;
state <= send;
end
end
send:
begin
if((getByte == 1) && (tmpGetByte == 0))
begin
startSendRmii <= 0;
countByteSend <= countByteSend + 1;
byteSendRmii <= packUDP[countByteSend];
end
else if(readyRMII & (countByteSend >= lenPack))
begin
state <= idle;
countByteSend <= 0;
end
end
endcase
end
endmodule | module rmii_send_pack
( input clk,
input nrst,
output [1:0]PhyTxd,
output reg PhyClk50Mhz,
output PhyTxEn,
output reg PhyRstn); |
wire rst;
assign rst = ~nrst;
wire start;
timer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));
parameter lenPack = 72;
reg [7:0]packUDP[0:lenPack-1];
initial $readmemh("packUDP.hex",packUDP);
reg [15:0]countByteSend;
reg [7:0]byteSendRmii;
reg startSendRmii;
always @(posedge clk, posedge rst)
if(rst)
PhyClk50Mhz <= 0;
else
PhyClk50Mhz <= ~PhyClk50Mhz;
wire getByte;
wire readyRMII;
rmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),
.ready(readyRMII), .dataOut(PhyTxd), .TXEN(PhyTxEn), .getByte(getByte));
reg [1:0] state;
parameter idle = 2'b00;
parameter send = 2'b01;
reg tmpGetByte;
always @(posedge clk, posedge rst)
if(rst)
begin
countByteSend <= 0;
byteSendRmii <= 0;
startSendRmii <= 0;
state <= idle;
tmpGetByte <= 0;
PhyRstn <= 0;
end
else
begin
PhyRstn <= 1;
tmpGetByte <= getByte;
case(state)
idle:
begin
if(start)
begin
countByteSend <= 1;
byteSendRmii <= packUDP[countByteSend];
startSendRmii <= 1;
state <= send;
end
end
send:
begin
if((getByte == 1) && (tmpGetByte == 0))
begin
startSendRmii <= 0;
countByteSend <= countByteSend + 1;
byteSendRmii <= packUDP[countByteSend];
end
else if(readyRMII & (countByteSend >= lenPack))
begin
state <= idle;
countByteSend <= 0;
end
end
endcase
end
endmodule | 5 |
3,007 | data/full_repos/permissive/102388603/rmii_tx.v | 102,388,603 | rmii_tx.v | v | 106 | 72 | [] | [] | [] | [(4, 104)] | null | data/verilator_xmls/ae7a0491-2127-4ac3-bafe-79cc3d084be8.xml | null | 599 | module | module rmii_tx
( input clk,
input rst,
input [7:0]dataIn,
input [15:0]dataLen,
input start,
output reg getByte,
output ready,
output [1:0]dataOut,
output reg TXEN,
output [15:0]numByteSend);
reg clkDev2;
always @(posedge clk, posedge rst)
if(rst)
clkDev2 <= 0;
else
clkDev2 <= ~clkDev2;
reg [7:0]dataTransmit;
assign dataOut = dataTransmit[1:0];
reg [1:0]state;
parameter idle = 2'b00;
parameter send = 2'b01;
reg [4:0]countBitSend;
reg [15:0]countByteSend;
reg [15:0]lenByteSend;
assign numByteSend = countByteSend;
assign ready = (state == idle) ? 1:0;
always @(negedge clk, posedge rst)
if(rst)
begin
dataTransmit <= 0;
countBitSend <= 0;
TXEN <= 0;
state <= idle;
countByteSend <= 0;
lenByteSend <= 0;
getByte <= 0;
end
else
begin
if(clkDev2)
begin
case(state)
idle:
begin
if(start)
begin
countByteSend <= 1;
lenByteSend <= dataLen;
dataTransmit <= dataIn;
state <= send;
TXEN <= 1;
countBitSend <= 0;
end
else
TXEN <= 0;
end
send:
begin
if(countBitSend == 2)
getByte <= 1;
else
getByte <= 0;
if(countBitSend < 3)
begin
dataTransmit <= dataTransmit >> 2;
countBitSend <= countBitSend + 1;
end
else if(countBitSend == 3)
begin
dataTransmit <= dataIn;
countBitSend <= 0;
countByteSend <= countByteSend + 1;
if(countByteSend >= lenByteSend)
begin
state <= idle;
TXEN <= 0;
end
end
end
endcase
end
end
endmodule | module rmii_tx
( input clk,
input rst,
input [7:0]dataIn,
input [15:0]dataLen,
input start,
output reg getByte,
output ready,
output [1:0]dataOut,
output reg TXEN,
output [15:0]numByteSend); |
reg clkDev2;
always @(posedge clk, posedge rst)
if(rst)
clkDev2 <= 0;
else
clkDev2 <= ~clkDev2;
reg [7:0]dataTransmit;
assign dataOut = dataTransmit[1:0];
reg [1:0]state;
parameter idle = 2'b00;
parameter send = 2'b01;
reg [4:0]countBitSend;
reg [15:0]countByteSend;
reg [15:0]lenByteSend;
assign numByteSend = countByteSend;
assign ready = (state == idle) ? 1:0;
always @(negedge clk, posedge rst)
if(rst)
begin
dataTransmit <= 0;
countBitSend <= 0;
TXEN <= 0;
state <= idle;
countByteSend <= 0;
lenByteSend <= 0;
getByte <= 0;
end
else
begin
if(clkDev2)
begin
case(state)
idle:
begin
if(start)
begin
countByteSend <= 1;
lenByteSend <= dataLen;
dataTransmit <= dataIn;
state <= send;
TXEN <= 1;
countBitSend <= 0;
end
else
TXEN <= 0;
end
send:
begin
if(countBitSend == 2)
getByte <= 1;
else
getByte <= 0;
if(countBitSend < 3)
begin
dataTransmit <= dataTransmit >> 2;
countBitSend <= countBitSend + 1;
end
else if(countBitSend == 3)
begin
dataTransmit <= dataIn;
countBitSend <= 0;
countByteSend <= countByteSend + 1;
if(countByteSend >= lenByteSend)
begin
state <= idle;
TXEN <= 0;
end
end
end
endcase
end
end
endmodule | 5 |
3,011 | data/full_repos/permissive/102388603/timer32.v | 102,388,603 | timer32.v | v | 36 | 66 | [] | [] | [] | [(7, 35)] | null | data/verilator_xmls/7b114562-b96f-45cc-81bf-9f8aabbb289b.xml | null | 602 | module | module timer32(
input clk,
input rst,
input [31:0]period,
output reg out);
reg [31:0]counter;
always @(posedge clk, posedge rst)
if(rst)
begin
counter <= 0;
end
else
if(counter == 0)
begin
counter <= period - 1;
out <= 1;
end
else
begin
counter <= counter - 1;
out <= 0;
end
endmodule | module timer32(
input clk,
input rst,
input [31:0]period,
output reg out); |
reg [31:0]counter;
always @(posedge clk, posedge rst)
if(rst)
begin
counter <= 0;
end
else
if(counter == 0)
begin
counter <= period - 1;
out <= 1;
end
else
begin
counter <= counter - 1;
out <= 0;
end
endmodule | 5 |
3,014 | data/full_repos/permissive/102388603/uart_tx.v | 102,388,603 | uart_tx.v | v | 120 | 63 | [] | [] | [] | null | line:17: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:48: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_tx\nassign ready = (state == idle) ? 1:0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n : ... In instance uart_tx\n state <= idle;\n ^~\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:73: Selection index out of range: 12:11 outside 10:0\n : ... In instance uart_tx\n dataUart[dataLen + 4:dataLen + 3] <= 2\'b11;\n ^\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:80: Selection index out of range: 11:10 outside 10:0\n : ... In instance uart_tx\n dataUart[dataLen + 3:dataLen + 2] <= 2\'b11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n : ... In instance uart_tx\n state <= send;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:92: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n : ... In instance uart_tx\n state <= idle;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:99: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitSnd\' generates 3 bits.\n : ... In instance uart_tx\n state <= waitSnd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:108: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n : ... In instance uart_tx\n state <= send;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:105: Operator GT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'waitSndTimer\' generates 14 bits.\n : ... In instance uart_tx\n if(waitSndTimer > periodUart)\n ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:61: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_tx\n case(state)\n ^~~~\n%Error: Exiting due to 10 warning(s)\n' | 604 | module | module uart_tx #(
parameter T = 9600,
par = 0,
parType = 0,
stop = 1,
dataLen = 8)
( input clk,
input rst,
input [dataLen-1:0]data,
input start,
output ready,
output reg dataOut);
function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter F_clk_Gz = 100_000_000;
parameter periodUart = F_clk_Gz/T;
parameter dataLenUart = dataLen + stop + 1 + par;
reg [log2(periodUart)-1:0]waitSndTimer;
reg [dataLenUart:0]dataUart;
reg [1:0]state;
parameter idle = 3'b00;
parameter send = 3'b01;
parameter waitSnd = 3'b10;
parameter parity = 3'b11;
reg [3:0]countBitSend;
assign ready = (state == idle) ? 1:0;
always @(posedge clk, posedge rst)
if(rst)
begin
dataOut <= 1;
dataUart <= 0;
countBitSend <= 0;
state <= idle;
waitSndTimer <= 0;
end
else
begin
case(state)
idle:
begin
if(start)
begin
dataUart[dataLen:0] <= {data, 1'b0};
if(par == 1)
begin
dataUart[dataLen + 1] <= ^data;
if(stop == 1)
dataUart[dataLen + 2] <= 1;
else if(stop == 2)
dataUart[dataLen + 4:dataLen + 3] <= 2'b11;
end
else if(par == 0)
begin
if(stop == 1)
dataUart[dataLen + 1] <= 1;
else if(stop == 2)
dataUart[dataLen + 3:dataLen + 2] <= 2'b11;
end
state <= send;
end
end
send:
begin
if(countBitSend > dataLenUart - 1)
begin
countBitSend <= 0;
dataOut <= 1;
state <= idle;
end
else
begin
dataUart <= dataUart >> 1;
dataOut <= dataUart[0];
countBitSend <= countBitSend + 1;
state <= waitSnd;
end
end
waitSnd:
begin
if(waitSndTimer > periodUart)
begin
waitSndTimer <= 0;
state <= send;
end
else
waitSndTimer <= waitSndTimer + 1;
end
endcase
end
endmodule | module uart_tx #(
parameter T = 9600,
par = 0,
parType = 0,
stop = 1,
dataLen = 8)
( input clk,
input rst,
input [dataLen-1:0]data,
input start,
output ready,
output reg dataOut); |
function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter F_clk_Gz = 100_000_000;
parameter periodUart = F_clk_Gz/T;
parameter dataLenUart = dataLen + stop + 1 + par;
reg [log2(periodUart)-1:0]waitSndTimer;
reg [dataLenUart:0]dataUart;
reg [1:0]state;
parameter idle = 3'b00;
parameter send = 3'b01;
parameter waitSnd = 3'b10;
parameter parity = 3'b11;
reg [3:0]countBitSend;
assign ready = (state == idle) ? 1:0;
always @(posedge clk, posedge rst)
if(rst)
begin
dataOut <= 1;
dataUart <= 0;
countBitSend <= 0;
state <= idle;
waitSndTimer <= 0;
end
else
begin
case(state)
idle:
begin
if(start)
begin
dataUart[dataLen:0] <= {data, 1'b0};
if(par == 1)
begin
dataUart[dataLen + 1] <= ^data;
if(stop == 1)
dataUart[dataLen + 2] <= 1;
else if(stop == 2)
dataUart[dataLen + 4:dataLen + 3] <= 2'b11;
end
else if(par == 0)
begin
if(stop == 1)
dataUart[dataLen + 1] <= 1;
else if(stop == 2)
dataUart[dataLen + 3:dataLen + 2] <= 2'b11;
end
state <= send;
end
end
send:
begin
if(countBitSend > dataLenUart - 1)
begin
countBitSend <= 0;
dataOut <= 1;
state <= idle;
end
else
begin
dataUart <= dataUart >> 1;
dataOut <= dataUart[0];
countBitSend <= countBitSend + 1;
state <= waitSnd;
end
end
waitSnd:
begin
if(waitSndTimer > periodUart)
begin
waitSndTimer <= 0;
state <= send;
end
else
waitSndTimer <= waitSndTimer + 1;
end
endcase
end
endmodule | 5 |
3,015 | data/full_repos/permissive/102388603/uart_tx.v | 102,388,603 | uart_tx.v | v | 120 | 63 | [] | [] | [] | null | line:17: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:48: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_tx\nassign ready = (state == idle) ? 1:0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n : ... In instance uart_tx\n state <= idle;\n ^~\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:73: Selection index out of range: 12:11 outside 10:0\n : ... In instance uart_tx\n dataUart[dataLen + 4:dataLen + 3] <= 2\'b11;\n ^\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:80: Selection index out of range: 11:10 outside 10:0\n : ... In instance uart_tx\n dataUart[dataLen + 3:dataLen + 2] <= 2\'b11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n : ... In instance uart_tx\n state <= send;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:92: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n : ... In instance uart_tx\n state <= idle;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:99: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitSnd\' generates 3 bits.\n : ... In instance uart_tx\n state <= waitSnd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:108: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n : ... In instance uart_tx\n state <= send;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:105: Operator GT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'waitSndTimer\' generates 14 bits.\n : ... In instance uart_tx\n if(waitSndTimer > periodUart)\n ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:61: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n : ... In instance uart_tx\n case(state)\n ^~~~\n%Error: Exiting due to 10 warning(s)\n' | 604 | function | function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function integer log2; |
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 5 |
3,016 | data/full_repos/permissive/102388603/udp_rx.v | 102,388,603 | udp_rx.v | v | 284 | 304 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/102388603/udp_rx.v:38: Cannot find file containing module: \'mem_2port\'\nmem_2port #(.N(8), .L(10), .do_clk_b(0))\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port.v\n data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port.sv\n mem_2port\n mem_2port.v\n mem_2port.sv\n obj_dir/mem_2port\n obj_dir/mem_2port.v\n obj_dir/mem_2port.sv\n%Error: data/full_repos/permissive/102388603/udp_rx.v:48: Cannot find file containing module: \'rmii_rx_byte\'\nrmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/102388603/udp_rx.v:178: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'rmiiRcvByte\' generates 8 bits.\n : ... In instance udp_rx\n 33: crc16Ip[8:0] <= rmiiRcvByte; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102388603/udp_rx.v:263: Cannot find file containing module: \'crc_32_802_3\'\ncrc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 605 | module | module udp_rx #(parameter packSizePow2 = 10)
( input clk,
input rst,
output ready,
reg [3:0]packStatus,
input modeTransp,
input [47:0]macLoc,
output reg [47:0]macRem,
output reg [31:0]ipLoc,
output reg [31:0]ipRem,
output reg [15:0]ipID,
output reg [15:0]portLoc,
output reg [15:0]portRem,
output reg [15:0]lenUdp,
input [1:0]PhyRxd,
input PhyClk50Mhz,
input PhyCRsDv,
input PhyRstn
);
reg en_a, we_a, en_b, we_b;
reg [9:0] addr_a;
reg [7:0] w_data_a;
wire [7:0] r_data_a;
wire [7:0] r_data_b;
mem_2port #(.N(8), .L(10), .do_clk_b(0))
mem2pr(.clk(clk), .en_a(en_a), .we_a(we_a), .addr_a(addr_a), .w_data_a(w_data_a), .r_data_a(r_data_a),
.clk_b(clk), .en_b(0), .we_b(0), .addr_b(0), .w_data_b(0), .r_data_b(r_data_b));
reg [7:0] rmiiRcvByte;
wire rmiiRcvRdy;
wire rmiiRcvBusy;
rmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),
.rm_crs_dv(PhyCRsDv), .data(rmiiRcvByte), .rdy(rmiiRcvRdy), .busy(rmiiRcvBusy));
parameter lenAllEthHeader = 8 + 14+ 20;
parameter lenIpUdpHeaders = 20;
reg [15:0] lenEthPack;
reg [15:0] lenIpPack;
reg [15:0] countEthByteRcv;
reg [3:0] countHeaderByte;
reg [5:0]stateEth;
parameter idle = 0;
parameter recvHead = 1;
parameter sendMAC = 2;
parameter sendIpHead = 3;
parameter sendIpAddr = 4;
parameter sendUDPHead = 5;
parameter reciveUDPData = 6;
parameter sendEthCRC = 7;
parameter packStOk = 0;
parameter packStErrCRCEth = 1;
parameter packStErrMACAddr = 2;
parameter packStErrIpAddr = 3;
parameter packStErrUDPPort = 4;
parameter packStErrCRCIp = 5;
parameter packStErrCRCType = 6;
parameter packStErrVer = 7;
reg getByteUDPEn;
wire getByte;
always @(posedge clk, posedge rst)
if(rst)
begin
getByteUDPEn <= 0;
lenIpPack <= 0;
lenEthPack <= 0;
stateEth <= idle;
countEthByteRcv <= 0;
countHeaderByte <= 0;
en_a <= 0;
we_a <= 0;
addr_a <= 0;
w_data_a <= 0;
end
else
begin
case(stateEth)
idle:
begin
if(PhyCRsDv)
begin
countEthByteRcv <= 1;
packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
stateEth <= recvHead;
end
end
recvHead:
begin
if(PhyCRsDv)
begin
countEthByteRcv <= countEthByteRcv + 1;
case(countEthByteRcv)
0,1,2,3,4,5,6: packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
7: begin
packStatus <= (rmiiRcvByte == 8'hD5) ? packStOk : packStErrCRCIp;
crc32En <= 1;
end
8: macRem[47:40] <= rmiiRcvByte;
9: macRem[39:32] <= rmiiRcvByte;
10: macRem[31:24] <= rmiiRcvByte;
11: macRem[23:16] <= rmiiRcvByte;
12: macRem[15:8] <= rmiiRcvByte;
13: macRem[7:0] <= rmiiRcvByte;
14: packStatus <= (rmiiRcvByte == macLoc[47:40]) ? packStOk : packStErrCRCIp;
15: packStatus <= (rmiiRcvByte == macLoc[39:32]) ? packStOk : packStErrCRCIp;
16: packStatus <= (rmiiRcvByte == macLoc[31:24]) ? packStOk : packStErrCRCIp;
17: packStatus <= (rmiiRcvByte == macLoc[23:16]) ? packStOk : packStErrCRCIp;
18: packStatus <= (rmiiRcvByte == macLoc[15:8]) ? packStOk : packStErrCRCIp;
19: packStatus <= (rmiiRcvByte == macLoc[7:0]) ? packStOk : packStErrCRCIp;
20: packStatus <= (rmiiRcvByte == 8'h08) ? packStOk : packStErrCRCType;
21: packStatus <= (rmiiRcvByte == 8'h00) ? packStOk : packStErrCRCType;
22: packStatus <= (rmiiRcvByte == 8'h45) ? packStOk : packStErrVer;
23: packStatus <= (rmiiRcvByte == 8'h00) ? packStOk : packStErrVer;
24: lenIpPack[15:8] <= rmiiRcvByte;
25: lenIpPack[7:0] <= rmiiRcvByte;
26: ipID[15:8] <= rmiiRcvByte;
27: ipID[7:0] <= rmiiRcvByte;
28: rmiiRcvByte <= 0;
29: rmiiRcvByte <= 0;
30: rmiiRcvByte <= 8'h80;
31: packStatus <= (rmiiRcvByte == 8'h11) ? packStOk : packStErrVer;
32: crc16Ip[15:8] <= rmiiRcvByte;
33: crc16Ip[8:0] <= rmiiRcvByte;
34: ipLoc[31:24] <= rmiiRcvByte;
35: ipLoc[23:16] <= rmiiRcvByte;
36: ipLoc[15:8] <= rmiiRcvByte;
37: ipLoc[7:0] <= rmiiRcvByte;
38: ipRem[31:24] <= rmiiRcvByte;
39: ipRem[23:16] <= rmiiRcvByte;
40: ipRem[15:8] <= rmiiRcvByte;
41: ipRem[7:0] <= rmiiRcvByte;
42: portLoc[15:8] <= rmiiRcvByte;
43: portLoc[7:0] <= rmiiRcvByte;
44: portRem[15:8] <= rmiiRcvByte;
45: portRem[7:0] <= rmiiRcvByte;
46: lenUdp[15:8] <= rmiiRcvByte;
47: lenUdp[7:0] <= rmiiRcvByte;
48: ;
49: begin
;
getByteUDPEn <= 1;
en_a <= 1;
stateEth <= reciveUDPData;
end
endcase
end
end
reciveUDPData:
begin
if(rmiiRcvRdy)
begin
we_a <= 1;
countEthByteRcv <= countEthByteRcv + 1;
if(countEthByteRcv < lenEthPack - 4)
begin
w_data_a <= rmiiRcvByte;
addr_a <= addr_a + 1;
end
else
begin
crc32En <= 0;
rmiiRcvByte <= ~crc32Eth[31:24];
crc32EthBuf <= ~crc32Eth << 8;
getByteUDPEn <= 0;
stateEth <= sendEthCRC;
end
end
else
we_a <= 0;
end
sendEthCRC:
begin
if(rmiiRcvRdy)
begin
countEthByteRcv <= countEthByteRcv + 1;
rmiiRcvByte <= crc32EthBuf[31:24];
crc32EthBuf <= crc32EthBuf << 8;
end
if(countEthByteRcv > lenEthPack)
stateEth <= idle;
end
endcase
end
reg [15:0]countByteSend;
wire [15:0]crc16Ip;
wire [31:0]ip_crc_step0;
wire [31:0]ip_crc_step1;
assign ip_crc_step0 = 32'h4500 + 32'h002E + 32'hB3FE + 32'h8011 + {16'd0,ipLoc[31:16]} + {16'd0,ipLoc[15:0]} + {16'd0,ipRem[31:16]} + {16'd0,ipRem[15:0]};
assign ip_crc_step1 = {16'd0 ,ip_crc_step0[31:16]}+{16'd0,ip_crc_step0[15:0]};
assign crc16Ip = ~{ip_crc_step1[31:16]+ip_crc_step1[15:0]};
reg [31:0] crc32Eth;
reg [31:0] crc32EthBuf;
wire [31:0] crc32Res;
reg crc32En;
crc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));
always @(posedge clk, posedge rst)
if(rst)
begin
crc32Eth <= 0;
end
else
begin
if(countByteSend == 0)
crc32Eth <= -1;
else if((countEthByteRcv > 7) & rmiiRcvRdy)
crc32Eth <= crc32Res;
else
crc32Eth <= crc32Eth;
end
endmodule | module udp_rx #(parameter packSizePow2 = 10)
( input clk,
input rst,
output ready,
reg [3:0]packStatus,
input modeTransp,
input [47:0]macLoc,
output reg [47:0]macRem,
output reg [31:0]ipLoc,
output reg [31:0]ipRem,
output reg [15:0]ipID,
output reg [15:0]portLoc,
output reg [15:0]portRem,
output reg [15:0]lenUdp,
input [1:0]PhyRxd,
input PhyClk50Mhz,
input PhyCRsDv,
input PhyRstn
); |
reg en_a, we_a, en_b, we_b;
reg [9:0] addr_a;
reg [7:0] w_data_a;
wire [7:0] r_data_a;
wire [7:0] r_data_b;
mem_2port #(.N(8), .L(10), .do_clk_b(0))
mem2pr(.clk(clk), .en_a(en_a), .we_a(we_a), .addr_a(addr_a), .w_data_a(w_data_a), .r_data_a(r_data_a),
.clk_b(clk), .en_b(0), .we_b(0), .addr_b(0), .w_data_b(0), .r_data_b(r_data_b));
reg [7:0] rmiiRcvByte;
wire rmiiRcvRdy;
wire rmiiRcvBusy;
rmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),
.rm_crs_dv(PhyCRsDv), .data(rmiiRcvByte), .rdy(rmiiRcvRdy), .busy(rmiiRcvBusy));
parameter lenAllEthHeader = 8 + 14+ 20;
parameter lenIpUdpHeaders = 20;
reg [15:0] lenEthPack;
reg [15:0] lenIpPack;
reg [15:0] countEthByteRcv;
reg [3:0] countHeaderByte;
reg [5:0]stateEth;
parameter idle = 0;
parameter recvHead = 1;
parameter sendMAC = 2;
parameter sendIpHead = 3;
parameter sendIpAddr = 4;
parameter sendUDPHead = 5;
parameter reciveUDPData = 6;
parameter sendEthCRC = 7;
parameter packStOk = 0;
parameter packStErrCRCEth = 1;
parameter packStErrMACAddr = 2;
parameter packStErrIpAddr = 3;
parameter packStErrUDPPort = 4;
parameter packStErrCRCIp = 5;
parameter packStErrCRCType = 6;
parameter packStErrVer = 7;
reg getByteUDPEn;
wire getByte;
always @(posedge clk, posedge rst)
if(rst)
begin
getByteUDPEn <= 0;
lenIpPack <= 0;
lenEthPack <= 0;
stateEth <= idle;
countEthByteRcv <= 0;
countHeaderByte <= 0;
en_a <= 0;
we_a <= 0;
addr_a <= 0;
w_data_a <= 0;
end
else
begin
case(stateEth)
idle:
begin
if(PhyCRsDv)
begin
countEthByteRcv <= 1;
packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
stateEth <= recvHead;
end
end
recvHead:
begin
if(PhyCRsDv)
begin
countEthByteRcv <= countEthByteRcv + 1;
case(countEthByteRcv)
0,1,2,3,4,5,6: packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
7: begin
packStatus <= (rmiiRcvByte == 8'hD5) ? packStOk : packStErrCRCIp;
crc32En <= 1;
end
8: macRem[47:40] <= rmiiRcvByte;
9: macRem[39:32] <= rmiiRcvByte;
10: macRem[31:24] <= rmiiRcvByte;
11: macRem[23:16] <= rmiiRcvByte;
12: macRem[15:8] <= rmiiRcvByte;
13: macRem[7:0] <= rmiiRcvByte;
14: packStatus <= (rmiiRcvByte == macLoc[47:40]) ? packStOk : packStErrCRCIp;
15: packStatus <= (rmiiRcvByte == macLoc[39:32]) ? packStOk : packStErrCRCIp;
16: packStatus <= (rmiiRcvByte == macLoc[31:24]) ? packStOk : packStErrCRCIp;
17: packStatus <= (rmiiRcvByte == macLoc[23:16]) ? packStOk : packStErrCRCIp;
18: packStatus <= (rmiiRcvByte == macLoc[15:8]) ? packStOk : packStErrCRCIp;
19: packStatus <= (rmiiRcvByte == macLoc[7:0]) ? packStOk : packStErrCRCIp;
20: packStatus <= (rmiiRcvByte == 8'h08) ? packStOk : packStErrCRCType;
21: packStatus <= (rmiiRcvByte == 8'h00) ? packStOk : packStErrCRCType;
22: packStatus <= (rmiiRcvByte == 8'h45) ? packStOk : packStErrVer;
23: packStatus <= (rmiiRcvByte == 8'h00) ? packStOk : packStErrVer;
24: lenIpPack[15:8] <= rmiiRcvByte;
25: lenIpPack[7:0] <= rmiiRcvByte;
26: ipID[15:8] <= rmiiRcvByte;
27: ipID[7:0] <= rmiiRcvByte;
28: rmiiRcvByte <= 0;
29: rmiiRcvByte <= 0;
30: rmiiRcvByte <= 8'h80;
31: packStatus <= (rmiiRcvByte == 8'h11) ? packStOk : packStErrVer;
32: crc16Ip[15:8] <= rmiiRcvByte;
33: crc16Ip[8:0] <= rmiiRcvByte;
34: ipLoc[31:24] <= rmiiRcvByte;
35: ipLoc[23:16] <= rmiiRcvByte;
36: ipLoc[15:8] <= rmiiRcvByte;
37: ipLoc[7:0] <= rmiiRcvByte;
38: ipRem[31:24] <= rmiiRcvByte;
39: ipRem[23:16] <= rmiiRcvByte;
40: ipRem[15:8] <= rmiiRcvByte;
41: ipRem[7:0] <= rmiiRcvByte;
42: portLoc[15:8] <= rmiiRcvByte;
43: portLoc[7:0] <= rmiiRcvByte;
44: portRem[15:8] <= rmiiRcvByte;
45: portRem[7:0] <= rmiiRcvByte;
46: lenUdp[15:8] <= rmiiRcvByte;
47: lenUdp[7:0] <= rmiiRcvByte;
48: ;
49: begin
;
getByteUDPEn <= 1;
en_a <= 1;
stateEth <= reciveUDPData;
end
endcase
end
end
reciveUDPData:
begin
if(rmiiRcvRdy)
begin
we_a <= 1;
countEthByteRcv <= countEthByteRcv + 1;
if(countEthByteRcv < lenEthPack - 4)
begin
w_data_a <= rmiiRcvByte;
addr_a <= addr_a + 1;
end
else
begin
crc32En <= 0;
rmiiRcvByte <= ~crc32Eth[31:24];
crc32EthBuf <= ~crc32Eth << 8;
getByteUDPEn <= 0;
stateEth <= sendEthCRC;
end
end
else
we_a <= 0;
end
sendEthCRC:
begin
if(rmiiRcvRdy)
begin
countEthByteRcv <= countEthByteRcv + 1;
rmiiRcvByte <= crc32EthBuf[31:24];
crc32EthBuf <= crc32EthBuf << 8;
end
if(countEthByteRcv > lenEthPack)
stateEth <= idle;
end
endcase
end
reg [15:0]countByteSend;
wire [15:0]crc16Ip;
wire [31:0]ip_crc_step0;
wire [31:0]ip_crc_step1;
assign ip_crc_step0 = 32'h4500 + 32'h002E + 32'hB3FE + 32'h8011 + {16'd0,ipLoc[31:16]} + {16'd0,ipLoc[15:0]} + {16'd0,ipRem[31:16]} + {16'd0,ipRem[15:0]};
assign ip_crc_step1 = {16'd0 ,ip_crc_step0[31:16]}+{16'd0,ip_crc_step0[15:0]};
assign crc16Ip = ~{ip_crc_step1[31:16]+ip_crc_step1[15:0]};
reg [31:0] crc32Eth;
reg [31:0] crc32EthBuf;
wire [31:0] crc32Res;
reg crc32En;
crc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));
always @(posedge clk, posedge rst)
if(rst)
begin
crc32Eth <= 0;
end
else
begin
if(countByteSend == 0)
crc32Eth <= -1;
else if((countEthByteRcv > 7) & rmiiRcvRdy)
crc32Eth <= crc32Res;
else
crc32Eth <= crc32Eth;
end
endmodule | 5 |
3,018 | data/full_repos/permissive/102394571/binto7seg.v | 102,394,571 | binto7seg.v | v | 62 | 83 | [] | [] | [] | [(21, 62)] | null | data/verilator_xmls/fa58695a-cdf1-414a-a205-758e0b3ebd38.xml | null | 607 | module | module binto7seg(
input clk,
input [3:0] binary,
output reg [6:0] seg
);
always @(posedge clk)
case (binary)
4'b0000 :
seg = 7'b1000000;
4'b0001 :
seg = 7'b1111001;
4'b0010 :
seg = 7'b0100100;
4'b0011 :
seg = 7'b0110000;
4'b0100 :
seg = 7'b0011001;
4'b0101 :
seg = 7'b0010010;
4'b0110 :
seg = 7'b0000010;
4'b0111 :
seg = 7'b1111000;
4'b1000 :
seg = 7'b0000000;
4'b1001 :
seg = 7'b0010000;
4'b1010 :
seg = 7'b0001000;
4'b1011 :
seg = 7'b0000011;
4'b1100 :
seg = 7'b1000110;
4'b1101 :
seg = 7'b0100001;
4'b1110 :
seg = 7'b0000110;
4'b1111 :
seg = 7'b0001110;
endcase
endmodule | module binto7seg(
input clk,
input [3:0] binary,
output reg [6:0] seg
); |
always @(posedge clk)
case (binary)
4'b0000 :
seg = 7'b1000000;
4'b0001 :
seg = 7'b1111001;
4'b0010 :
seg = 7'b0100100;
4'b0011 :
seg = 7'b0110000;
4'b0100 :
seg = 7'b0011001;
4'b0101 :
seg = 7'b0010010;
4'b0110 :
seg = 7'b0000010;
4'b0111 :
seg = 7'b1111000;
4'b1000 :
seg = 7'b0000000;
4'b1001 :
seg = 7'b0010000;
4'b1010 :
seg = 7'b0001000;
4'b1011 :
seg = 7'b0000011;
4'b1100 :
seg = 7'b1000110;
4'b1101 :
seg = 7'b0100001;
4'b1110 :
seg = 7'b0000110;
4'b1111 :
seg = 7'b0001110;
endcase
endmodule | 1 |
3,019 | data/full_repos/permissive/102394571/clock_divisor.v | 102,394,571 | clock_divisor.v | v | 55 | 83 | [] | [] | [] | [(21, 54)] | null | data/verilator_xmls/bb6e254b-2e9a-450f-92a4-28722a405921.xml | null | 608 | module | module clock_divisor(
input clk_100MHz,
input reset,
output reg clk_1Hz
);
reg[25:0] contador = 0;
reg reset_last = 0;
initial clk_1Hz = 0 ;
always @(posedge clk_100MHz)
begin
if (reset && reset != reset_last)
begin
contador = 0;
clk_1Hz = 0;
reset_last = reset;
end
else
begin
if(contador != 50000000)
begin
contador = contador + 1 ;
end
else
begin
contador = 0;
clk_1Hz = ~clk_1Hz;
end
reset_last = reset;
end
end
endmodule | module clock_divisor(
input clk_100MHz,
input reset,
output reg clk_1Hz
); |
reg[25:0] contador = 0;
reg reset_last = 0;
initial clk_1Hz = 0 ;
always @(posedge clk_100MHz)
begin
if (reset && reset != reset_last)
begin
contador = 0;
clk_1Hz = 0;
reset_last = reset;
end
else
begin
if(contador != 50000000)
begin
contador = contador + 1 ;
end
else
begin
contador = 0;
clk_1Hz = ~clk_1Hz;
end
reset_last = reset;
end
end
endmodule | 1 |
3,022 | data/full_repos/permissive/102394571/Contador.v | 102,394,571 | Contador.v | v | 38 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/31434d0d-a321-4c82-8468-e7b605fd1a9f.xml | null | 611 | module | module Contador(
input clk,
input one,
input five,
input reset,
output reg [3:0] total
);
always @(posedge clk)
if (reset) total <= 0 ;
else
begin
if (one) total <= total + 1 ;
if (five) total <= total + 5 ;
end
endmodule | module Contador(
input clk,
input one,
input five,
input reset,
output reg [3:0] total
); |
always @(posedge clk)
if (reset) total <= 0 ;
else
begin
if (one) total <= total + 1 ;
if (five) total <= total + 5 ;
end
endmodule | 1 |
3,023 | data/full_repos/permissive/102394571/ContadorTest.v | 102,394,571 | ContadorTest.v | v | 70 | 83 | [] | [] | [] | [(21, 70)] | null | null | 1: b"%Error: data/full_repos/permissive/102394571/ContadorTest.v:40: Cannot find file containing module: 'seven_segment'\n seven_segment seven_seg(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/seven_segment\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/seven_segment.v\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/seven_segment.sv\n seven_segment\n seven_segment.v\n seven_segment.sv\n obj_dir/seven_segment\n obj_dir/seven_segment.v\n obj_dir/seven_segment.sv\n%Error: data/full_repos/permissive/102394571/ContadorTest.v:46: Cannot find file containing module: 'Contador'\n Contador monedero(\n ^~~~~~~~\n%Error: data/full_repos/permissive/102394571/ContadorTest.v:53: Cannot find file containing module: 'Debouncer'\n Debouncer cancel(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102394571/ContadorTest.v:58: Cannot find file containing module: 'Debouncer'\n Debouncer hundred_coin(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102394571/ContadorTest.v:63: Cannot find file containing module: 'Debouncer'\n Debouncer five_hundred_coin(\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 612 | module | module ContadorTest(
input clk,
input btnl,
input btnd,
input btnr,
output [7:3] led,
output [6:0] seg,
output [3:0] an
);
wire [3:0] total;
wire test;
wire cancel_wire;
wire hundred_wire;
wire five_hundred_wire;
seven_segment seven_seg(
.clk(clk),
.in(total),
.seg(seg),
.an(an)
);
Contador monedero(
.clk(clk),
.one(hundred_wire),
.five(five_hundred_wire),
.reset(cancel_wire),
.total(total)
);
Debouncer cancel(
.clk(clk),
.signal(btnd),
.signal_state(cancel_wire)
);
Debouncer hundred_coin(
.clk(clk),
.signal(btnl),
.signal_up(hundred_wire)
);
Debouncer five_hundred_coin(
.clk(clk),
.signal(btnr),
.signal_up(five_hundred_wire)
);
endmodule | module ContadorTest(
input clk,
input btnl,
input btnd,
input btnr,
output [7:3] led,
output [6:0] seg,
output [3:0] an
); |
wire [3:0] total;
wire test;
wire cancel_wire;
wire hundred_wire;
wire five_hundred_wire;
seven_segment seven_seg(
.clk(clk),
.in(total),
.seg(seg),
.an(an)
);
Contador monedero(
.clk(clk),
.one(hundred_wire),
.five(five_hundred_wire),
.reset(cancel_wire),
.total(total)
);
Debouncer cancel(
.clk(clk),
.signal(btnd),
.signal_state(cancel_wire)
);
Debouncer hundred_coin(
.clk(clk),
.signal(btnl),
.signal_up(hundred_wire)
);
Debouncer five_hundred_coin(
.clk(clk),
.signal(btnr),
.signal_up(five_hundred_wire)
);
endmodule | 1 |
3,024 | data/full_repos/permissive/102394571/Debouncer.v | 102,394,571 | Debouncer.v | v | 53 | 103 | [] | [] | [] | [(21, 53)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102394571/Debouncer.v:48: Operator ADD expects 20 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n : ... In instance Debouncer\n signal_cnt <= signal_cnt + 16\'d1; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 613 | module | module Debouncer(
input clk,
input signal,
output reg signal_state,
output signal_up
);
reg signal_sync_0; always @(posedge clk) signal_sync_0 <= signal;
reg signal_sync_1; always @(posedge clk) signal_sync_1 <= signal_sync_0;
reg [19:0] signal_cnt;
wire signal_idle = (signal_state==signal_sync_1);
wire signal_cnt_max = &signal_cnt;
always @(posedge clk)
if(signal_idle)
signal_cnt <= 0;
else
begin
signal_cnt <= signal_cnt + 16'd1;
if(signal_cnt_max) signal_state <= ~signal_state;
end
assign signal_up = ~signal_idle & signal_cnt_max & signal_state;
endmodule | module Debouncer(
input clk,
input signal,
output reg signal_state,
output signal_up
); |
reg signal_sync_0; always @(posedge clk) signal_sync_0 <= signal;
reg signal_sync_1; always @(posedge clk) signal_sync_1 <= signal_sync_0;
reg [19:0] signal_cnt;
wire signal_idle = (signal_state==signal_sync_1);
wire signal_cnt_max = &signal_cnt;
always @(posedge clk)
if(signal_idle)
signal_cnt <= 0;
else
begin
signal_cnt <= signal_cnt + 16'd1;
if(signal_cnt_max) signal_state <= ~signal_state;
end
assign signal_up = ~signal_idle & signal_cnt_max & signal_state;
endmodule | 1 |
3,026 | data/full_repos/permissive/102394571/deco.v | 102,394,571 | deco.v | v | 38 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/09d63bd8-adc0-4188-8404-71a27e1e9097.xml | null | 615 | module | module deco(
input clk,
input [1:0] in,
output reg [3:0] out
);
always@(posedge clk)
begin
case (in)
2'b00 : out <= 4'b1110;
2'b01 : out <= 4'b1101;
2'b10 : out <= 4'b1011;
2'b11 : out <= 4'b0111;
default : out <= 0;
endcase
end
endmodule | module deco(
input clk,
input [1:0] in,
output reg [3:0] out
); |
always@(posedge clk)
begin
case (in)
2'b00 : out <= 4'b1110;
2'b01 : out <= 4'b1101;
2'b10 : out <= 4'b1011;
2'b11 : out <= 4'b0111;
default : out <= 0;
endcase
end
endmodule | 1 |
3,028 | data/full_repos/permissive/102394571/FSM.v | 102,394,571 | FSM.v | v | 213 | 132 | [] | [] | [] | null | line:213: before: "/" | data/verilator_xmls/7ae33c30-337b-4b7d-b89a-352480f6c731.xml | null | 617 | module | module FSM(
input clk,
input ok,
input t_expired,
input reset,
input [2:0] c_type,
output reg [2:0]ing_type,
output reg start_timer,
output reg[7:3] ingredientes,
output reg expired,
output reg cobrar,
output reg [2:0] c_type_saved
);
parameter INICIO = 4'b0000,AGUA = 4'b0010,CAFE = 4'b0100, MILK = 4'b0110,CHOCO = 4'b1000,AZUC = 4'b1010, COBRAR_WAIT = 4'b1111;
parameter LAGUA = 4'b0001,LCAFE = 4'b0011, LMILK = 4'b0101,LCHOCO = 4'b0111,LAZUC = 4'b1001, COBRAR = 4'b1011;
reg [3:0] state = 0;
reg expired_last = 0;
initial begin
ingredientes = 5'b00000;
start_timer = 0;
ing_type = 0;
expired = 0;
cobrar = 0;
c_type_saved = 0;
end
always @ (posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
state = INICIO;
end
else begin
case(state)
INICIO : if (ok == 1'b1)
begin
state = LAGUA;
c_type_saved = c_type;
end
else
state = INICIO;
LAGUA : state = AGUA;
AGUA : if (t_expired) begin
state = LCAFE; end
else
state = AGUA;
LCAFE: state = CAFE;
CAFE :if (t_expired)begin
state = LMILK; end
else
state = CAFE;
LMILK: state = MILK;
MILK :if (t_expired) begin
state = LCHOCO; end
else
state = MILK;
LCHOCO : state = CHOCO;
CHOCO : if (t_expired) begin
state = LAZUC; end
else
state = CHOCO;
LAZUC: state = AZUC;
AZUC : if (t_expired) begin
state = COBRAR; end
else
state = AZUC;
COBRAR: begin
c_type_saved = 0;
state = COBRAR_WAIT;
end
COBRAR_WAIT: begin
c_type_saved = 0;
state = INICIO;
end
default : state = INICIO;
endcase
end
end
always @(state)
begin
case(state)
INICIO : begin
ing_type = 3'b000;
start_timer = 1'b0;
ingredientes = 5'b00000;
cobrar = 0;
end
LAGUA : begin
ing_type = 3'b001;
start_timer = 1'b0;
ingredientes = 5'b10000;
cobrar = 0;
end
AGUA : begin
ing_type = 3'b001;
start_timer = 1'b1;
ingredientes = 5'b10000;
cobrar = 0;
end
LCAFE : begin
ing_type = 3'b010;
start_timer = 1'b0;
ingredientes = 5'b01000;
cobrar = 0;
end
CAFE : begin
ing_type = 3'b010;
start_timer = 1'b1;
ingredientes = 5'b01000;
cobrar = 0;
end
LMILK: begin
ing_type = 3'b011;
start_timer = 1'b0;
ingredientes = 5'b00100;
cobrar = 0;
end
MILK: begin
ing_type = 3'b011;
start_timer = 1'b1;
ingredientes = 5'b00100;
cobrar = 0;
end
LCHOCO : begin
ing_type = 3'b100;
start_timer = 1'b0;
ingredientes = 5'b00010;
cobrar = 0;
end
CHOCO : begin
ing_type = 3'b100;
start_timer = 1'b1;
ingredientes = 5'b00010;
cobrar = 0;
end
LAZUC : begin
ing_type = 3'b101;
start_timer= 1'b0;
ingredientes= 5'b00001;
cobrar = 0;
end
AZUC : begin
ing_type = 3'b101;
start_timer= 1'b1;
ingredientes= 5'b00001;
cobrar = 0;
end
COBRAR : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes= 5'b00000;
cobrar = 1;
end
COBRAR_WAIT : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes= 5'b00000;
cobrar = 0;
end
default : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes = 5'b00000;
cobrar = 0;
end
endcase
end
always@(posedge t_expired)
begin
expired = ~expired;
end
endmodule | module FSM(
input clk,
input ok,
input t_expired,
input reset,
input [2:0] c_type,
output reg [2:0]ing_type,
output reg start_timer,
output reg[7:3] ingredientes,
output reg expired,
output reg cobrar,
output reg [2:0] c_type_saved
); |
parameter INICIO = 4'b0000,AGUA = 4'b0010,CAFE = 4'b0100, MILK = 4'b0110,CHOCO = 4'b1000,AZUC = 4'b1010, COBRAR_WAIT = 4'b1111;
parameter LAGUA = 4'b0001,LCAFE = 4'b0011, LMILK = 4'b0101,LCHOCO = 4'b0111,LAZUC = 4'b1001, COBRAR = 4'b1011;
reg [3:0] state = 0;
reg expired_last = 0;
initial begin
ingredientes = 5'b00000;
start_timer = 0;
ing_type = 0;
expired = 0;
cobrar = 0;
c_type_saved = 0;
end
always @ (posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
state = INICIO;
end
else begin
case(state)
INICIO : if (ok == 1'b1)
begin
state = LAGUA;
c_type_saved = c_type;
end
else
state = INICIO;
LAGUA : state = AGUA;
AGUA : if (t_expired) begin
state = LCAFE; end
else
state = AGUA;
LCAFE: state = CAFE;
CAFE :if (t_expired)begin
state = LMILK; end
else
state = CAFE;
LMILK: state = MILK;
MILK :if (t_expired) begin
state = LCHOCO; end
else
state = MILK;
LCHOCO : state = CHOCO;
CHOCO : if (t_expired) begin
state = LAZUC; end
else
state = CHOCO;
LAZUC: state = AZUC;
AZUC : if (t_expired) begin
state = COBRAR; end
else
state = AZUC;
COBRAR: begin
c_type_saved = 0;
state = COBRAR_WAIT;
end
COBRAR_WAIT: begin
c_type_saved = 0;
state = INICIO;
end
default : state = INICIO;
endcase
end
end
always @(state)
begin
case(state)
INICIO : begin
ing_type = 3'b000;
start_timer = 1'b0;
ingredientes = 5'b00000;
cobrar = 0;
end
LAGUA : begin
ing_type = 3'b001;
start_timer = 1'b0;
ingredientes = 5'b10000;
cobrar = 0;
end
AGUA : begin
ing_type = 3'b001;
start_timer = 1'b1;
ingredientes = 5'b10000;
cobrar = 0;
end
LCAFE : begin
ing_type = 3'b010;
start_timer = 1'b0;
ingredientes = 5'b01000;
cobrar = 0;
end
CAFE : begin
ing_type = 3'b010;
start_timer = 1'b1;
ingredientes = 5'b01000;
cobrar = 0;
end
LMILK: begin
ing_type = 3'b011;
start_timer = 1'b0;
ingredientes = 5'b00100;
cobrar = 0;
end
MILK: begin
ing_type = 3'b011;
start_timer = 1'b1;
ingredientes = 5'b00100;
cobrar = 0;
end
LCHOCO : begin
ing_type = 3'b100;
start_timer = 1'b0;
ingredientes = 5'b00010;
cobrar = 0;
end
CHOCO : begin
ing_type = 3'b100;
start_timer = 1'b1;
ingredientes = 5'b00010;
cobrar = 0;
end
LAZUC : begin
ing_type = 3'b101;
start_timer= 1'b0;
ingredientes= 5'b00001;
cobrar = 0;
end
AZUC : begin
ing_type = 3'b101;
start_timer= 1'b1;
ingredientes= 5'b00001;
cobrar = 0;
end
COBRAR : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes= 5'b00000;
cobrar = 1;
end
COBRAR_WAIT : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes= 5'b00000;
cobrar = 0;
end
default : begin
ing_type = 3'b000;
start_timer= 1'b0;
ingredientes = 5'b00000;
cobrar = 0;
end
endcase
end
always@(posedge t_expired)
begin
expired = ~expired;
end
endmodule | 1 |
3,030 | data/full_repos/permissive/102394571/fsmtest_sim.v | 102,394,571 | fsmtest_sim.v | v | 83 | 81 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 btnr = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1 btnr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;speed = 4\'b0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:80: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ! clk;\n ^\n%Error: data/full_repos/permissive/102394571/fsmtest_sim.v:72: Can\'t find definition of variable: \'t_expired\'\n #10 t_expired = 1;speed = 4\'b0001;\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 620 | module | module fsmtest_sim;
reg clk;
reg btnl;
reg btnd;
reg btnr;
reg btnp;
reg btnu;
reg [3:0] speed;
wire [7:2] led;
wire [6:0] seg;
wire [3:0] an;
FSMTest uut (
.clk(clk),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.btnp(btnp),
.btnu(btnu),
.speed(speed),
.led(led),
.seg(seg),
.an(an)
);
initial begin
clk = 0;
btnl = 0;
btnd = 0;
btnr = 0;
btnp = 0;
btnu = 0;
speed = 0;
#100;
#10 speed = 4'b0001;
#10 btnr = 1;
#1 btnr = 0;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;speed = 4'b0001;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;speed = 4'b0001;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;
end
always
#1 clk = ! clk;
endmodule | module fsmtest_sim; |
reg clk;
reg btnl;
reg btnd;
reg btnr;
reg btnp;
reg btnu;
reg [3:0] speed;
wire [7:2] led;
wire [6:0] seg;
wire [3:0] an;
FSMTest uut (
.clk(clk),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.btnp(btnp),
.btnu(btnu),
.speed(speed),
.led(led),
.seg(seg),
.an(an)
);
initial begin
clk = 0;
btnl = 0;
btnd = 0;
btnr = 0;
btnp = 0;
btnu = 0;
speed = 0;
#100;
#10 speed = 4'b0001;
#10 btnr = 1;
#1 btnr = 0;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;speed = 4'b0001;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;speed = 4'b0001;
#10 t_expired = 1;speed = 4'b0001;
#10 t_expired = 0;
end
always
#1 clk = ! clk;
endmodule | 1 |
3,031 | data/full_repos/permissive/102394571/FSM_sim.v | 102,394,571 | FSM_sim.v | v | 82 | 81 | [] | [] | [] | [(25, 80)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10 c_type = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 ok = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 t_expired = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:79: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ! clk; \n ^\n%Error: data/full_repos/permissive/102394571/FSM_sim.v:40: Cannot find file containing module: \'FSM\'\n FSM uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM.v\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM.sv\n FSM\n FSM.v\n FSM.sv\n obj_dir/FSM\n obj_dir/FSM.v\n obj_dir/FSM.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 621 | module | module FSM_sim;
reg clk;
reg ok;
reg [1:0] c_type;
reg t_expired;
reg reset;
wire [2:0] ing_type;
wire start_timer;
wire [7:3] ingredientes;
FSM uut (
.clk(clk),
.ok(ok),
.c_type(c_type),
.t_expired(t_expired),
.reset(reset),
.ing_type(ing_type),
.start_timer(start_timer),
.ingredientes(ingredientes)
);
initial begin
clk = 0;
ok = 0;
c_type = 0;
t_expired = 0;
reset = 0;
#100;
#10 c_type = 2;
#10 ok = 1;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
end
always
#5 clk = ! clk;
endmodule | module FSM_sim; |
reg clk;
reg ok;
reg [1:0] c_type;
reg t_expired;
reg reset;
wire [2:0] ing_type;
wire start_timer;
wire [7:3] ingredientes;
FSM uut (
.clk(clk),
.ok(ok),
.c_type(c_type),
.t_expired(t_expired),
.reset(reset),
.ing_type(ing_type),
.start_timer(start_timer),
.ingredientes(ingredientes)
);
initial begin
clk = 0;
ok = 0;
c_type = 0;
t_expired = 0;
reset = 0;
#100;
#10 c_type = 2;
#10 ok = 1;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
#10 t_expired = 1;
#10 t_expired = 0;
end
always
#5 clk = ! clk;
endmodule | 1 |
3,039 | data/full_repos/permissive/102394571/testdivisor.v | 102,394,571 | testdivisor.v | v | 34 | 83 | [] | [] | [] | [(21, 33)] | null | null | 1: b"%Error: data/full_repos/permissive/102394571/testdivisor.v:28: Cannot find file containing module: 'clock_divisor'\n clock_divisor div(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/clock_divisor\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/clock_divisor.v\n data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/clock_divisor.sv\n clock_divisor\n clock_divisor.v\n clock_divisor.sv\n obj_dir/clock_divisor\n obj_dir/clock_divisor.v\n obj_dir/clock_divisor.sv\n%Error: Exiting due to 1 error(s)\n" | 629 | module | module testdivisor(
input clk,
output [7:3] led
);
clock_divisor div(
.clk_100MHz(clk),
.clk_1Hz(led[7])
);
endmodule | module testdivisor(
input clk,
output [7:3] led
); |
clock_divisor div(
.clk_100MHz(clk),
.clk_1Hz(led[7])
);
endmodule | 1 |
3,041 | data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 631 | module | module AXILiteControl(
input clock,
input reset,
output io_slave_writeAddr_ready,
input io_slave_writeAddr_valid,
input [63:0] io_slave_writeAddr_bits_addr,
output io_slave_writeData_ready,
input io_slave_writeData_valid,
input [31:0] io_slave_writeData_bits_data,
input [3:0] io_slave_writeData_bits_strb,
input io_slave_writeResp_ready,
output io_slave_writeResp_valid,
output io_slave_readAddr_ready,
input io_slave_readAddr_valid,
input [63:0] io_slave_readAddr_bits_addr,
input io_slave_readData_ready,
output io_slave_readData_valid,
output [31:0] io_slave_readData_bits_data,
output io_ap_start,
input io_ap_done
);
reg ap_start;
reg [31:0] _RAND_0;
reg auto_restart;
reg [31:0] _RAND_1;
reg ap_idle;
reg [31:0] _RAND_2;
reg ap_done;
reg [31:0] _RAND_3;
reg ap_start_r;
reg [31:0] _RAND_4;
wire _T_50;
wire ap_start_pulse;
wire _GEN_0;
wire _T_53;
wire _T_54;
wire _GEN_1;
wire _T_59;
wire _T_60;
wire _GEN_2;
reg [2:0] stateSlaveWrite;
reg [31:0] _RAND_5;
reg [5:0] writeAddr;
reg [31:0] _RAND_6;
reg [2:0] stateSlaveRead;
reg [31:0] _RAND_7;
reg [31:0] readData;
reg [31:0] _RAND_8;
wire _T_69;
wire _T_70;
wire _T_71;
wire _T_72;
wire _T_118;
wire addrwr_handshake;
wire write_handshake;
wire [63:0] _GEN_3;
wire [2:0] _GEN_4;
wire _T_121;
wire [2:0] _GEN_5;
wire [2:0] _GEN_6;
wire _T_124;
wire _T_125;
wire [2:0] _GEN_7;
wire _T_127;
wire [2:0] _GEN_8;
wire [2:0] _GEN_9;
wire _T_132;
wire _T_133;
wire _T_134;
wire [2:0] _GEN_10;
wire _T_136;
wire [2:0] _GEN_11;
wire [2:0] _GEN_12;
wire _T_143;
wire _T_144;
wire [2:0] _GEN_13;
wire _T_147;
wire _T_148;
wire _T_149;
wire addrrd_handshake;
wire [2:0] _GEN_14;
wire _T_152;
wire [2:0] _GEN_15;
wire [2:0] _GEN_16;
wire _T_155;
wire _T_156;
wire _T_157;
wire [2:0] _GEN_17;
wire _T_159;
wire [2:0] _GEN_18;
wire [2:0] _GEN_19;
wire _T_163;
wire _T_164;
wire [2:0] _GEN_20;
wire _T_165;
wire [1:0] _GEN_27;
wire [1:0] _T_166;
wire [1:0] _GEN_28;
wire [1:0] _T_167;
wire [2:0] _GEN_29;
wire [2:0] _T_168;
wire [2:0] _GEN_30;
wire [2:0] _T_169;
wire [3:0] _GEN_31;
wire [3:0] _T_170;
wire [3:0] _GEN_32;
wire [3:0] _T_171;
wire [7:0] _GEN_33;
wire [7:0] _T_172;
wire [7:0] _GEN_34;
wire [7:0] _T_173;
wire [31:0] _GEN_21;
wire [31:0] _GEN_22;
wire _T_174;
wire _T_175;
wire _T_176;
wire _T_177;
wire _T_178;
wire _T_179;
wire _GEN_23;
wire _T_182;
wire _T_183;
wire _GEN_24;
wire _T_185;
wire _GEN_25;
wire _T_191;
wire _GEN_26;
assign io_slave_writeAddr_ready = _T_71;
assign io_slave_writeData_ready = _T_72;
assign io_slave_writeResp_valid = _T_118;
assign io_slave_readAddr_ready = _T_148;
assign io_slave_readData_valid = _T_149;
assign io_slave_readData_bits_data = readData;
assign io_ap_start = ap_start;
assign _T_50 = ap_start_r == 1'h0;
assign ap_start_pulse = ap_start & _T_50;
assign _GEN_0 = ap_done ? 1'h1 : ap_idle;
assign _T_53 = ap_done == 1'h0;
assign _T_54 = _T_53 & ap_start_pulse;
assign _GEN_1 = _T_54 ? 1'h0 : _GEN_0;
assign _T_59 = ap_start_pulse == 1'h0;
assign _T_60 = _T_53 & _T_59;
assign _GEN_2 = _T_60 ? ap_idle : _GEN_1;
assign _T_69 = reset == 1'h0;
assign _T_70 = stateSlaveWrite == 3'h0;
assign _T_71 = _T_69 & _T_70;
assign _T_72 = stateSlaveWrite == 3'h1;
assign _T_118 = stateSlaveWrite == 3'h2;
assign addrwr_handshake = io_slave_writeAddr_valid & io_slave_writeAddr_ready;
assign write_handshake = io_slave_writeData_valid & io_slave_writeData_ready;
assign _GEN_3 = addrwr_handshake ? io_slave_writeAddr_bits_addr : {{58'd0}, writeAddr};
assign _GEN_4 = io_slave_writeAddr_valid ? 3'h1 : stateSlaveWrite;
assign _T_121 = io_slave_writeAddr_valid == 1'h0;
assign _GEN_5 = _T_121 ? 3'h0 : _GEN_4;
assign _GEN_6 = _T_70 ? _GEN_5 : stateSlaveWrite;
assign _T_124 = _T_70 == 1'h0;
assign _T_125 = _T_124 & _T_72;
assign _GEN_7 = io_slave_writeData_valid ? 3'h2 : _GEN_6;
assign _T_127 = io_slave_writeData_valid == 1'h0;
assign _GEN_8 = _T_127 ? 3'h1 : _GEN_7;
assign _GEN_9 = _T_125 ? _GEN_8 : _GEN_6;
assign _T_132 = _T_72 == 1'h0;
assign _T_133 = _T_124 & _T_132;
assign _T_134 = _T_133 & _T_118;
assign _GEN_10 = io_slave_writeResp_ready ? 3'h0 : _GEN_9;
assign _T_136 = io_slave_writeResp_ready == 1'h0;
assign _GEN_11 = _T_136 ? 3'h2 : _GEN_10;
assign _GEN_12 = _T_134 ? _GEN_11 : _GEN_9;
assign _T_143 = _T_118 == 1'h0;
assign _T_144 = _T_133 & _T_143;
assign _GEN_13 = _T_144 ? 3'h0 : _GEN_12;
assign _T_147 = stateSlaveRead == 3'h0;
assign _T_148 = _T_69 & _T_147;
assign _T_149 = stateSlaveRead == 3'h3;
assign addrrd_handshake = io_slave_readAddr_valid & io_slave_readAddr_ready;
assign _GEN_14 = io_slave_readAddr_valid ? 3'h3 : stateSlaveRead;
assign _T_152 = io_slave_readAddr_valid == 1'h0;
assign _GEN_15 = _T_152 ? 3'h0 : _GEN_14;
assign _GEN_16 = _T_147 ? _GEN_15 : stateSlaveRead;
assign _T_155 = _T_147 == 1'h0;
assign _T_156 = _T_155 & _T_149;
assign _T_157 = io_slave_readData_valid & io_slave_readData_ready;
assign _GEN_17 = _T_157 ? 3'h0 : _GEN_16;
assign _T_159 = _T_157 == 1'h0;
assign _GEN_18 = _T_159 ? 3'h3 : _GEN_17;
assign _GEN_19 = _T_156 ? _GEN_18 : _GEN_16;
assign _T_163 = _T_149 == 1'h0;
assign _T_164 = _T_155 & _T_163;
assign _GEN_20 = _T_164 ? 3'h0 : _GEN_19;
assign _T_165 = io_slave_readAddr_bits_addr == 64'h0;
assign _GEN_27 = {{1'd0}, ap_done};
assign _T_166 = _GEN_27 << 1;
assign _GEN_28 = {{1'd0}, ap_start};
assign _T_167 = _GEN_28 | _T_166;
assign _GEN_29 = {{2'd0}, ap_idle};
assign _T_168 = _GEN_29 << 2;
assign _GEN_30 = {{1'd0}, _T_167};
assign _T_169 = _GEN_30 | _T_168;
assign _GEN_31 = {{3'd0}, ap_done};
assign _T_170 = _GEN_31 << 3;
assign _GEN_32 = {{1'd0}, _T_169};
assign _T_171 = _GEN_32 | _T_170;
assign _GEN_33 = {{7'd0}, auto_restart};
assign _T_172 = _GEN_33 << 7;
assign _GEN_34 = {{4'd0}, _T_171};
assign _T_173 = _GEN_34 | _T_172;
assign _GEN_21 = _T_165 ? {{24'd0}, _T_173} : readData;
assign _GEN_22 = addrrd_handshake ? _GEN_21 : readData;
assign _T_174 = writeAddr == 6'h0;
assign _T_175 = write_handshake & _T_174;
assign _T_176 = io_slave_writeData_bits_strb[0];
assign _T_177 = _T_175 & _T_176;
assign _T_178 = io_slave_writeData_bits_data[0];
assign _T_179 = _T_177 & _T_178;
assign _GEN_23 = _T_179 ? 1'h1 : ap_start;
assign _T_182 = _T_179 == 1'h0;
assign _T_183 = _T_182 & ap_done;
assign _GEN_24 = _T_183 ? auto_restart : _GEN_23;
assign _T_185 = addrrd_handshake & _T_165;
assign _GEN_25 = _T_185 ? 1'h0 : io_ap_done;
assign _T_191 = io_slave_writeData_bits_data[7];
assign _GEN_26 = _T_177 ? _T_191 : auto_restart;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
ap_start = _RAND_0[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
auto_restart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
ap_idle = _RAND_2[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{$random}};
ap_done = _RAND_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{$random}};
ap_start_r = _RAND_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{$random}};
stateSlaveWrite = _RAND_5[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{$random}};
writeAddr = _RAND_6[5:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{$random}};
stateSlaveRead = _RAND_7[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{$random}};
readData = _RAND_8[31:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ap_start <= 1'h0;
end else begin
if (_T_183) begin
ap_start <= auto_restart;
end else begin
if (_T_179) begin
ap_start <= 1'h1;
end
end
end
if (reset) begin
auto_restart <= 1'h0;
end else begin
if (_T_177) begin
auto_restart <= _T_191;
end
end
if (reset) begin
ap_idle <= 1'h1;
end else begin
if (!(_T_60)) begin
if (_T_54) begin
ap_idle <= 1'h0;
end else begin
if (ap_done) begin
ap_idle <= 1'h1;
end
end
end
end
if (reset) begin
ap_done <= 1'h0;
end else begin
if (_T_185) begin
ap_done <= 1'h0;
end else begin
ap_done <= io_ap_done;
end
end
if (reset) begin
ap_start_r <= 1'h0;
end else begin
ap_start_r <= ap_start;
end
if (reset) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_144) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_134) begin
if (_T_136) begin
stateSlaveWrite <= 3'h2;
end else begin
if (io_slave_writeResp_ready) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end
if (reset) begin
writeAddr <= 6'h0;
end else begin
writeAddr <= _GEN_3[5:0];
end
if (reset) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_164) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_156) begin
if (_T_159) begin
stateSlaveRead <= 3'h3;
end else begin
if (_T_157) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end
if (reset) begin
readData <= 32'h0;
end else begin
if (addrrd_handshake) begin
if (_T_165) begin
readData <= {{24'd0}, _T_173};
end
end
end
end
endmodule | module AXILiteControl(
input clock,
input reset,
output io_slave_writeAddr_ready,
input io_slave_writeAddr_valid,
input [63:0] io_slave_writeAddr_bits_addr,
output io_slave_writeData_ready,
input io_slave_writeData_valid,
input [31:0] io_slave_writeData_bits_data,
input [3:0] io_slave_writeData_bits_strb,
input io_slave_writeResp_ready,
output io_slave_writeResp_valid,
output io_slave_readAddr_ready,
input io_slave_readAddr_valid,
input [63:0] io_slave_readAddr_bits_addr,
input io_slave_readData_ready,
output io_slave_readData_valid,
output [31:0] io_slave_readData_bits_data,
output io_ap_start,
input io_ap_done
); |
reg ap_start;
reg [31:0] _RAND_0;
reg auto_restart;
reg [31:0] _RAND_1;
reg ap_idle;
reg [31:0] _RAND_2;
reg ap_done;
reg [31:0] _RAND_3;
reg ap_start_r;
reg [31:0] _RAND_4;
wire _T_50;
wire ap_start_pulse;
wire _GEN_0;
wire _T_53;
wire _T_54;
wire _GEN_1;
wire _T_59;
wire _T_60;
wire _GEN_2;
reg [2:0] stateSlaveWrite;
reg [31:0] _RAND_5;
reg [5:0] writeAddr;
reg [31:0] _RAND_6;
reg [2:0] stateSlaveRead;
reg [31:0] _RAND_7;
reg [31:0] readData;
reg [31:0] _RAND_8;
wire _T_69;
wire _T_70;
wire _T_71;
wire _T_72;
wire _T_118;
wire addrwr_handshake;
wire write_handshake;
wire [63:0] _GEN_3;
wire [2:0] _GEN_4;
wire _T_121;
wire [2:0] _GEN_5;
wire [2:0] _GEN_6;
wire _T_124;
wire _T_125;
wire [2:0] _GEN_7;
wire _T_127;
wire [2:0] _GEN_8;
wire [2:0] _GEN_9;
wire _T_132;
wire _T_133;
wire _T_134;
wire [2:0] _GEN_10;
wire _T_136;
wire [2:0] _GEN_11;
wire [2:0] _GEN_12;
wire _T_143;
wire _T_144;
wire [2:0] _GEN_13;
wire _T_147;
wire _T_148;
wire _T_149;
wire addrrd_handshake;
wire [2:0] _GEN_14;
wire _T_152;
wire [2:0] _GEN_15;
wire [2:0] _GEN_16;
wire _T_155;
wire _T_156;
wire _T_157;
wire [2:0] _GEN_17;
wire _T_159;
wire [2:0] _GEN_18;
wire [2:0] _GEN_19;
wire _T_163;
wire _T_164;
wire [2:0] _GEN_20;
wire _T_165;
wire [1:0] _GEN_27;
wire [1:0] _T_166;
wire [1:0] _GEN_28;
wire [1:0] _T_167;
wire [2:0] _GEN_29;
wire [2:0] _T_168;
wire [2:0] _GEN_30;
wire [2:0] _T_169;
wire [3:0] _GEN_31;
wire [3:0] _T_170;
wire [3:0] _GEN_32;
wire [3:0] _T_171;
wire [7:0] _GEN_33;
wire [7:0] _T_172;
wire [7:0] _GEN_34;
wire [7:0] _T_173;
wire [31:0] _GEN_21;
wire [31:0] _GEN_22;
wire _T_174;
wire _T_175;
wire _T_176;
wire _T_177;
wire _T_178;
wire _T_179;
wire _GEN_23;
wire _T_182;
wire _T_183;
wire _GEN_24;
wire _T_185;
wire _GEN_25;
wire _T_191;
wire _GEN_26;
assign io_slave_writeAddr_ready = _T_71;
assign io_slave_writeData_ready = _T_72;
assign io_slave_writeResp_valid = _T_118;
assign io_slave_readAddr_ready = _T_148;
assign io_slave_readData_valid = _T_149;
assign io_slave_readData_bits_data = readData;
assign io_ap_start = ap_start;
assign _T_50 = ap_start_r == 1'h0;
assign ap_start_pulse = ap_start & _T_50;
assign _GEN_0 = ap_done ? 1'h1 : ap_idle;
assign _T_53 = ap_done == 1'h0;
assign _T_54 = _T_53 & ap_start_pulse;
assign _GEN_1 = _T_54 ? 1'h0 : _GEN_0;
assign _T_59 = ap_start_pulse == 1'h0;
assign _T_60 = _T_53 & _T_59;
assign _GEN_2 = _T_60 ? ap_idle : _GEN_1;
assign _T_69 = reset == 1'h0;
assign _T_70 = stateSlaveWrite == 3'h0;
assign _T_71 = _T_69 & _T_70;
assign _T_72 = stateSlaveWrite == 3'h1;
assign _T_118 = stateSlaveWrite == 3'h2;
assign addrwr_handshake = io_slave_writeAddr_valid & io_slave_writeAddr_ready;
assign write_handshake = io_slave_writeData_valid & io_slave_writeData_ready;
assign _GEN_3 = addrwr_handshake ? io_slave_writeAddr_bits_addr : {{58'd0}, writeAddr};
assign _GEN_4 = io_slave_writeAddr_valid ? 3'h1 : stateSlaveWrite;
assign _T_121 = io_slave_writeAddr_valid == 1'h0;
assign _GEN_5 = _T_121 ? 3'h0 : _GEN_4;
assign _GEN_6 = _T_70 ? _GEN_5 : stateSlaveWrite;
assign _T_124 = _T_70 == 1'h0;
assign _T_125 = _T_124 & _T_72;
assign _GEN_7 = io_slave_writeData_valid ? 3'h2 : _GEN_6;
assign _T_127 = io_slave_writeData_valid == 1'h0;
assign _GEN_8 = _T_127 ? 3'h1 : _GEN_7;
assign _GEN_9 = _T_125 ? _GEN_8 : _GEN_6;
assign _T_132 = _T_72 == 1'h0;
assign _T_133 = _T_124 & _T_132;
assign _T_134 = _T_133 & _T_118;
assign _GEN_10 = io_slave_writeResp_ready ? 3'h0 : _GEN_9;
assign _T_136 = io_slave_writeResp_ready == 1'h0;
assign _GEN_11 = _T_136 ? 3'h2 : _GEN_10;
assign _GEN_12 = _T_134 ? _GEN_11 : _GEN_9;
assign _T_143 = _T_118 == 1'h0;
assign _T_144 = _T_133 & _T_143;
assign _GEN_13 = _T_144 ? 3'h0 : _GEN_12;
assign _T_147 = stateSlaveRead == 3'h0;
assign _T_148 = _T_69 & _T_147;
assign _T_149 = stateSlaveRead == 3'h3;
assign addrrd_handshake = io_slave_readAddr_valid & io_slave_readAddr_ready;
assign _GEN_14 = io_slave_readAddr_valid ? 3'h3 : stateSlaveRead;
assign _T_152 = io_slave_readAddr_valid == 1'h0;
assign _GEN_15 = _T_152 ? 3'h0 : _GEN_14;
assign _GEN_16 = _T_147 ? _GEN_15 : stateSlaveRead;
assign _T_155 = _T_147 == 1'h0;
assign _T_156 = _T_155 & _T_149;
assign _T_157 = io_slave_readData_valid & io_slave_readData_ready;
assign _GEN_17 = _T_157 ? 3'h0 : _GEN_16;
assign _T_159 = _T_157 == 1'h0;
assign _GEN_18 = _T_159 ? 3'h3 : _GEN_17;
assign _GEN_19 = _T_156 ? _GEN_18 : _GEN_16;
assign _T_163 = _T_149 == 1'h0;
assign _T_164 = _T_155 & _T_163;
assign _GEN_20 = _T_164 ? 3'h0 : _GEN_19;
assign _T_165 = io_slave_readAddr_bits_addr == 64'h0;
assign _GEN_27 = {{1'd0}, ap_done};
assign _T_166 = _GEN_27 << 1;
assign _GEN_28 = {{1'd0}, ap_start};
assign _T_167 = _GEN_28 | _T_166;
assign _GEN_29 = {{2'd0}, ap_idle};
assign _T_168 = _GEN_29 << 2;
assign _GEN_30 = {{1'd0}, _T_167};
assign _T_169 = _GEN_30 | _T_168;
assign _GEN_31 = {{3'd0}, ap_done};
assign _T_170 = _GEN_31 << 3;
assign _GEN_32 = {{1'd0}, _T_169};
assign _T_171 = _GEN_32 | _T_170;
assign _GEN_33 = {{7'd0}, auto_restart};
assign _T_172 = _GEN_33 << 7;
assign _GEN_34 = {{4'd0}, _T_171};
assign _T_173 = _GEN_34 | _T_172;
assign _GEN_21 = _T_165 ? {{24'd0}, _T_173} : readData;
assign _GEN_22 = addrrd_handshake ? _GEN_21 : readData;
assign _T_174 = writeAddr == 6'h0;
assign _T_175 = write_handshake & _T_174;
assign _T_176 = io_slave_writeData_bits_strb[0];
assign _T_177 = _T_175 & _T_176;
assign _T_178 = io_slave_writeData_bits_data[0];
assign _T_179 = _T_177 & _T_178;
assign _GEN_23 = _T_179 ? 1'h1 : ap_start;
assign _T_182 = _T_179 == 1'h0;
assign _T_183 = _T_182 & ap_done;
assign _GEN_24 = _T_183 ? auto_restart : _GEN_23;
assign _T_185 = addrrd_handshake & _T_165;
assign _GEN_25 = _T_185 ? 1'h0 : io_ap_done;
assign _T_191 = io_slave_writeData_bits_data[7];
assign _GEN_26 = _T_177 ? _T_191 : auto_restart;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
ap_start = _RAND_0[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
auto_restart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
ap_idle = _RAND_2[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{$random}};
ap_done = _RAND_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{$random}};
ap_start_r = _RAND_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{$random}};
stateSlaveWrite = _RAND_5[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{$random}};
writeAddr = _RAND_6[5:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{$random}};
stateSlaveRead = _RAND_7[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{$random}};
readData = _RAND_8[31:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ap_start <= 1'h0;
end else begin
if (_T_183) begin
ap_start <= auto_restart;
end else begin
if (_T_179) begin
ap_start <= 1'h1;
end
end
end
if (reset) begin
auto_restart <= 1'h0;
end else begin
if (_T_177) begin
auto_restart <= _T_191;
end
end
if (reset) begin
ap_idle <= 1'h1;
end else begin
if (!(_T_60)) begin
if (_T_54) begin
ap_idle <= 1'h0;
end else begin
if (ap_done) begin
ap_idle <= 1'h1;
end
end
end
end
if (reset) begin
ap_done <= 1'h0;
end else begin
if (_T_185) begin
ap_done <= 1'h0;
end else begin
ap_done <= io_ap_done;
end
end
if (reset) begin
ap_start_r <= 1'h0;
end else begin
ap_start_r <= ap_start;
end
if (reset) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_144) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_134) begin
if (_T_136) begin
stateSlaveWrite <= 3'h2;
end else begin
if (io_slave_writeResp_ready) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end
if (reset) begin
writeAddr <= 6'h0;
end else begin
writeAddr <= _GEN_3[5:0];
end
if (reset) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_164) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_156) begin
if (_T_159) begin
stateSlaveRead <= 3'h3;
end else begin
if (_T_157) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end
if (reset) begin
readData <= 32'h0;
end else begin
if (addrrd_handshake) begin
if (_T_165) begin
readData <= {{24'd0}, _T_173};
end
end
end
end
endmodule | 17 |
3,042 | data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 631 | module | module MyKernel(
input clock,
input reset,
input io_ap_start,
output io_ap_done
);
reg [4:0] value;
reg [31:0] _RAND_0;
reg regFlagStart;
reg [31:0] _RAND_1;
reg doneReg;
reg [31:0] _RAND_2;
wire _T_18;
wire _T_19;
wire _T_21;
wire [5:0] _T_23;
wire [4:0] _T_24;
wire [4:0] _GEN_0;
wire [4:0] _GEN_1;
wire _GEN_2;
wire _T_28;
wire _GEN_3;
assign io_ap_done = doneReg;
assign _T_18 = regFlagStart == 1'h0;
assign _T_19 = io_ap_start & _T_18;
assign _T_21 = value == 5'h1d;
assign _T_23 = value + 5'h1;
assign _T_24 = _T_23[4:0];
assign _GEN_0 = _T_21 ? 5'h0 : _T_24;
assign _GEN_1 = _T_19 ? _GEN_0 : value;
assign _GEN_2 = _T_19 ? 1'h1 : regFlagStart;
assign _T_28 = value > 5'h0;
assign _GEN_3 = _T_28 ? 1'h1 : doneReg;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
regFlagStart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
doneReg = _RAND_2[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
value <= 5'h0;
end else begin
if (_T_19) begin
if (_T_21) begin
value <= 5'h0;
end else begin
value <= _T_24;
end
end
end
if (reset) begin
regFlagStart <= 1'h0;
end else begin
if (_T_19) begin
regFlagStart <= 1'h1;
end
end
if (reset) begin
doneReg <= 1'h0;
end else begin
if (_T_28) begin
doneReg <= 1'h1;
end
end
end
endmodule | module MyKernel(
input clock,
input reset,
input io_ap_start,
output io_ap_done
); |
reg [4:0] value;
reg [31:0] _RAND_0;
reg regFlagStart;
reg [31:0] _RAND_1;
reg doneReg;
reg [31:0] _RAND_2;
wire _T_18;
wire _T_19;
wire _T_21;
wire [5:0] _T_23;
wire [4:0] _T_24;
wire [4:0] _GEN_0;
wire [4:0] _GEN_1;
wire _GEN_2;
wire _T_28;
wire _GEN_3;
assign io_ap_done = doneReg;
assign _T_18 = regFlagStart == 1'h0;
assign _T_19 = io_ap_start & _T_18;
assign _T_21 = value == 5'h1d;
assign _T_23 = value + 5'h1;
assign _T_24 = _T_23[4:0];
assign _GEN_0 = _T_21 ? 5'h0 : _T_24;
assign _GEN_1 = _T_19 ? _GEN_0 : value;
assign _GEN_2 = _T_19 ? 1'h1 : regFlagStart;
assign _T_28 = value > 5'h0;
assign _GEN_3 = _T_28 ? 1'h1 : doneReg;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
regFlagStart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
doneReg = _RAND_2[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
value <= 5'h0;
end else begin
if (_T_19) begin
if (_T_21) begin
value <= 5'h0;
end else begin
value <= _T_24;
end
end
end
if (reset) begin
regFlagStart <= 1'h0;
end else begin
if (_T_19) begin
regFlagStart <= 1'h1;
end
end
if (reset) begin
doneReg <= 1'h0;
end else begin
if (_T_28) begin
doneReg <= 1'h1;
end
end
end
endmodule | 17 |
3,043 | data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_builds/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 631 | module | module SDAChiselWrapper(
input clock,
input reset,
input io_m0_writeAddr_ready,
output io_m0_writeAddr_valid,
output [63:0] io_m0_writeAddr_bits_addr,
output [2:0] io_m0_writeAddr_bits_size,
output [7:0] io_m0_writeAddr_bits_len,
output [1:0] io_m0_writeAddr_bits_burst,
output io_m0_writeAddr_bits_id,
output io_m0_writeAddr_bits_lock,
output [3:0] io_m0_writeAddr_bits_cache,
output [2:0] io_m0_writeAddr_bits_prot,
output [3:0] io_m0_writeAddr_bits_qos,
input io_m0_writeData_ready,
output io_m0_writeData_valid,
output [511:0] io_m0_writeData_bits_data,
output [63:0] io_m0_writeData_bits_strb,
output io_m0_writeData_bits_last,
output io_m0_writeResp_ready,
input io_m0_writeResp_valid,
input io_m0_writeResp_bits_id,
input [1:0] io_m0_writeResp_bits_resp,
input io_m0_readAddr_ready,
output io_m0_readAddr_valid,
output [63:0] io_m0_readAddr_bits_addr,
output [2:0] io_m0_readAddr_bits_size,
output [7:0] io_m0_readAddr_bits_len,
output [1:0] io_m0_readAddr_bits_burst,
output io_m0_readAddr_bits_id,
output io_m0_readAddr_bits_lock,
output [3:0] io_m0_readAddr_bits_cache,
output [2:0] io_m0_readAddr_bits_prot,
output [3:0] io_m0_readAddr_bits_qos,
output io_m0_readData_ready,
input io_m0_readData_valid,
input [511:0] io_m0_readData_bits_data,
input io_m0_readData_bits_id,
input io_m0_readData_bits_last,
input [1:0] io_m0_readData_bits_resp,
output io_s0_writeAddr_ready,
input io_s0_writeAddr_valid,
input [63:0] io_s0_writeAddr_bits_addr,
input [2:0] io_s0_writeAddr_bits_prot,
output io_s0_writeData_ready,
input io_s0_writeData_valid,
input [31:0] io_s0_writeData_bits_data,
input [3:0] io_s0_writeData_bits_strb,
input io_s0_writeResp_ready,
output io_s0_writeResp_valid,
output [1:0] io_s0_writeResp_bits,
output io_s0_readAddr_ready,
input io_s0_readAddr_valid,
input [63:0] io_s0_readAddr_bits_addr,
input [2:0] io_s0_readAddr_bits_prot,
input io_s0_readData_ready,
output io_s0_readData_valid,
output [31:0] io_s0_readData_bits_data,
output [1:0] io_s0_readData_bits_resp
);
wire slave_fsm_clock;
wire slave_fsm_reset;
wire slave_fsm_io_slave_writeAddr_ready;
wire slave_fsm_io_slave_writeAddr_valid;
wire [63:0] slave_fsm_io_slave_writeAddr_bits_addr;
wire slave_fsm_io_slave_writeData_ready;
wire slave_fsm_io_slave_writeData_valid;
wire [31:0] slave_fsm_io_slave_writeData_bits_data;
wire [3:0] slave_fsm_io_slave_writeData_bits_strb;
wire slave_fsm_io_slave_writeResp_ready;
wire slave_fsm_io_slave_writeResp_valid;
wire slave_fsm_io_slave_readAddr_ready;
wire slave_fsm_io_slave_readAddr_valid;
wire [63:0] slave_fsm_io_slave_readAddr_bits_addr;
wire slave_fsm_io_slave_readData_ready;
wire slave_fsm_io_slave_readData_valid;
wire [31:0] slave_fsm_io_slave_readData_bits_data;
wire slave_fsm_io_ap_start;
wire slave_fsm_io_ap_done;
wire RTLKernel_clock;
wire RTLKernel_reset;
wire RTLKernel_io_ap_start;
wire RTLKernel_io_ap_done;
wire _T_88;
AXILiteControl slave_fsm (
.clock(slave_fsm_clock),
.reset(slave_fsm_reset),
.io_slave_writeAddr_ready(slave_fsm_io_slave_writeAddr_ready),
.io_slave_writeAddr_valid(slave_fsm_io_slave_writeAddr_valid),
.io_slave_writeAddr_bits_addr(slave_fsm_io_slave_writeAddr_bits_addr),
.io_slave_writeData_ready(slave_fsm_io_slave_writeData_ready),
.io_slave_writeData_valid(slave_fsm_io_slave_writeData_valid),
.io_slave_writeData_bits_data(slave_fsm_io_slave_writeData_bits_data),
.io_slave_writeData_bits_strb(slave_fsm_io_slave_writeData_bits_strb),
.io_slave_writeResp_ready(slave_fsm_io_slave_writeResp_ready),
.io_slave_writeResp_valid(slave_fsm_io_slave_writeResp_valid),
.io_slave_readAddr_ready(slave_fsm_io_slave_readAddr_ready),
.io_slave_readAddr_valid(slave_fsm_io_slave_readAddr_valid),
.io_slave_readAddr_bits_addr(slave_fsm_io_slave_readAddr_bits_addr),
.io_slave_readData_ready(slave_fsm_io_slave_readData_ready),
.io_slave_readData_valid(slave_fsm_io_slave_readData_valid),
.io_slave_readData_bits_data(slave_fsm_io_slave_readData_bits_data),
.io_ap_start(slave_fsm_io_ap_start),
.io_ap_done(slave_fsm_io_ap_done)
);
MyKernel RTLKernel (
.clock(RTLKernel_clock),
.reset(RTLKernel_reset),
.io_ap_start(RTLKernel_io_ap_start),
.io_ap_done(RTLKernel_io_ap_done)
);
assign io_m0_writeAddr_valid = 1'h0;
assign io_m0_writeAddr_bits_addr = 64'h0;
assign io_m0_writeAddr_bits_size = 3'h0;
assign io_m0_writeAddr_bits_len = 8'h0;
assign io_m0_writeAddr_bits_burst = 2'h0;
assign io_m0_writeAddr_bits_id = 1'h0;
assign io_m0_writeAddr_bits_lock = 1'h0;
assign io_m0_writeAddr_bits_cache = 4'h0;
assign io_m0_writeAddr_bits_prot = 3'h0;
assign io_m0_writeAddr_bits_qos = 4'h0;
assign io_m0_writeData_valid = 1'h0;
assign io_m0_writeData_bits_data = 512'h0;
assign io_m0_writeData_bits_strb = 64'h0;
assign io_m0_writeData_bits_last = 1'h0;
assign io_m0_writeResp_ready = 1'h0;
assign io_m0_readAddr_valid = 1'h0;
assign io_m0_readAddr_bits_addr = 64'h0;
assign io_m0_readAddr_bits_size = 3'h0;
assign io_m0_readAddr_bits_len = 8'h0;
assign io_m0_readAddr_bits_burst = 2'h0;
assign io_m0_readAddr_bits_id = 1'h0;
assign io_m0_readAddr_bits_lock = 1'h0;
assign io_m0_readAddr_bits_cache = 4'h0;
assign io_m0_readAddr_bits_prot = 3'h0;
assign io_m0_readAddr_bits_qos = 4'h0;
assign io_m0_readData_ready = 1'h0;
assign io_s0_writeAddr_ready = slave_fsm_io_slave_writeAddr_ready;
assign io_s0_writeData_ready = slave_fsm_io_slave_writeData_ready;
assign io_s0_writeResp_valid = slave_fsm_io_slave_writeResp_valid;
assign io_s0_writeResp_bits = 2'h0;
assign io_s0_readAddr_ready = slave_fsm_io_slave_readAddr_ready;
assign io_s0_readData_valid = slave_fsm_io_slave_readData_valid;
assign io_s0_readData_bits_data = slave_fsm_io_slave_readData_bits_data;
assign io_s0_readData_bits_resp = 2'h0;
assign slave_fsm_clock = clock;
assign slave_fsm_reset = _T_88;
assign slave_fsm_io_slave_writeAddr_valid = io_s0_writeAddr_valid;
assign slave_fsm_io_slave_writeAddr_bits_addr = io_s0_writeAddr_bits_addr;
assign slave_fsm_io_slave_writeData_valid = io_s0_writeData_valid;
assign slave_fsm_io_slave_writeData_bits_data = io_s0_writeData_bits_data;
assign slave_fsm_io_slave_writeData_bits_strb = io_s0_writeData_bits_strb;
assign slave_fsm_io_slave_writeResp_ready = io_s0_writeResp_ready;
assign slave_fsm_io_slave_readAddr_valid = io_s0_readAddr_valid;
assign slave_fsm_io_slave_readAddr_bits_addr = io_s0_readAddr_bits_addr;
assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;
assign slave_fsm_io_ap_done = RTLKernel_io_ap_done;
assign RTLKernel_clock = clock;
assign RTLKernel_reset = _T_88;
assign RTLKernel_io_ap_start = slave_fsm_io_ap_start;
assign _T_88 = reset == 1'h0;
endmodule | module SDAChiselWrapper(
input clock,
input reset,
input io_m0_writeAddr_ready,
output io_m0_writeAddr_valid,
output [63:0] io_m0_writeAddr_bits_addr,
output [2:0] io_m0_writeAddr_bits_size,
output [7:0] io_m0_writeAddr_bits_len,
output [1:0] io_m0_writeAddr_bits_burst,
output io_m0_writeAddr_bits_id,
output io_m0_writeAddr_bits_lock,
output [3:0] io_m0_writeAddr_bits_cache,
output [2:0] io_m0_writeAddr_bits_prot,
output [3:0] io_m0_writeAddr_bits_qos,
input io_m0_writeData_ready,
output io_m0_writeData_valid,
output [511:0] io_m0_writeData_bits_data,
output [63:0] io_m0_writeData_bits_strb,
output io_m0_writeData_bits_last,
output io_m0_writeResp_ready,
input io_m0_writeResp_valid,
input io_m0_writeResp_bits_id,
input [1:0] io_m0_writeResp_bits_resp,
input io_m0_readAddr_ready,
output io_m0_readAddr_valid,
output [63:0] io_m0_readAddr_bits_addr,
output [2:0] io_m0_readAddr_bits_size,
output [7:0] io_m0_readAddr_bits_len,
output [1:0] io_m0_readAddr_bits_burst,
output io_m0_readAddr_bits_id,
output io_m0_readAddr_bits_lock,
output [3:0] io_m0_readAddr_bits_cache,
output [2:0] io_m0_readAddr_bits_prot,
output [3:0] io_m0_readAddr_bits_qos,
output io_m0_readData_ready,
input io_m0_readData_valid,
input [511:0] io_m0_readData_bits_data,
input io_m0_readData_bits_id,
input io_m0_readData_bits_last,
input [1:0] io_m0_readData_bits_resp,
output io_s0_writeAddr_ready,
input io_s0_writeAddr_valid,
input [63:0] io_s0_writeAddr_bits_addr,
input [2:0] io_s0_writeAddr_bits_prot,
output io_s0_writeData_ready,
input io_s0_writeData_valid,
input [31:0] io_s0_writeData_bits_data,
input [3:0] io_s0_writeData_bits_strb,
input io_s0_writeResp_ready,
output io_s0_writeResp_valid,
output [1:0] io_s0_writeResp_bits,
output io_s0_readAddr_ready,
input io_s0_readAddr_valid,
input [63:0] io_s0_readAddr_bits_addr,
input [2:0] io_s0_readAddr_bits_prot,
input io_s0_readData_ready,
output io_s0_readData_valid,
output [31:0] io_s0_readData_bits_data,
output [1:0] io_s0_readData_bits_resp
); |
wire slave_fsm_clock;
wire slave_fsm_reset;
wire slave_fsm_io_slave_writeAddr_ready;
wire slave_fsm_io_slave_writeAddr_valid;
wire [63:0] slave_fsm_io_slave_writeAddr_bits_addr;
wire slave_fsm_io_slave_writeData_ready;
wire slave_fsm_io_slave_writeData_valid;
wire [31:0] slave_fsm_io_slave_writeData_bits_data;
wire [3:0] slave_fsm_io_slave_writeData_bits_strb;
wire slave_fsm_io_slave_writeResp_ready;
wire slave_fsm_io_slave_writeResp_valid;
wire slave_fsm_io_slave_readAddr_ready;
wire slave_fsm_io_slave_readAddr_valid;
wire [63:0] slave_fsm_io_slave_readAddr_bits_addr;
wire slave_fsm_io_slave_readData_ready;
wire slave_fsm_io_slave_readData_valid;
wire [31:0] slave_fsm_io_slave_readData_bits_data;
wire slave_fsm_io_ap_start;
wire slave_fsm_io_ap_done;
wire RTLKernel_clock;
wire RTLKernel_reset;
wire RTLKernel_io_ap_start;
wire RTLKernel_io_ap_done;
wire _T_88;
AXILiteControl slave_fsm (
.clock(slave_fsm_clock),
.reset(slave_fsm_reset),
.io_slave_writeAddr_ready(slave_fsm_io_slave_writeAddr_ready),
.io_slave_writeAddr_valid(slave_fsm_io_slave_writeAddr_valid),
.io_slave_writeAddr_bits_addr(slave_fsm_io_slave_writeAddr_bits_addr),
.io_slave_writeData_ready(slave_fsm_io_slave_writeData_ready),
.io_slave_writeData_valid(slave_fsm_io_slave_writeData_valid),
.io_slave_writeData_bits_data(slave_fsm_io_slave_writeData_bits_data),
.io_slave_writeData_bits_strb(slave_fsm_io_slave_writeData_bits_strb),
.io_slave_writeResp_ready(slave_fsm_io_slave_writeResp_ready),
.io_slave_writeResp_valid(slave_fsm_io_slave_writeResp_valid),
.io_slave_readAddr_ready(slave_fsm_io_slave_readAddr_ready),
.io_slave_readAddr_valid(slave_fsm_io_slave_readAddr_valid),
.io_slave_readAddr_bits_addr(slave_fsm_io_slave_readAddr_bits_addr),
.io_slave_readData_ready(slave_fsm_io_slave_readData_ready),
.io_slave_readData_valid(slave_fsm_io_slave_readData_valid),
.io_slave_readData_bits_data(slave_fsm_io_slave_readData_bits_data),
.io_ap_start(slave_fsm_io_ap_start),
.io_ap_done(slave_fsm_io_ap_done)
);
MyKernel RTLKernel (
.clock(RTLKernel_clock),
.reset(RTLKernel_reset),
.io_ap_start(RTLKernel_io_ap_start),
.io_ap_done(RTLKernel_io_ap_done)
);
assign io_m0_writeAddr_valid = 1'h0;
assign io_m0_writeAddr_bits_addr = 64'h0;
assign io_m0_writeAddr_bits_size = 3'h0;
assign io_m0_writeAddr_bits_len = 8'h0;
assign io_m0_writeAddr_bits_burst = 2'h0;
assign io_m0_writeAddr_bits_id = 1'h0;
assign io_m0_writeAddr_bits_lock = 1'h0;
assign io_m0_writeAddr_bits_cache = 4'h0;
assign io_m0_writeAddr_bits_prot = 3'h0;
assign io_m0_writeAddr_bits_qos = 4'h0;
assign io_m0_writeData_valid = 1'h0;
assign io_m0_writeData_bits_data = 512'h0;
assign io_m0_writeData_bits_strb = 64'h0;
assign io_m0_writeData_bits_last = 1'h0;
assign io_m0_writeResp_ready = 1'h0;
assign io_m0_readAddr_valid = 1'h0;
assign io_m0_readAddr_bits_addr = 64'h0;
assign io_m0_readAddr_bits_size = 3'h0;
assign io_m0_readAddr_bits_len = 8'h0;
assign io_m0_readAddr_bits_burst = 2'h0;
assign io_m0_readAddr_bits_id = 1'h0;
assign io_m0_readAddr_bits_lock = 1'h0;
assign io_m0_readAddr_bits_cache = 4'h0;
assign io_m0_readAddr_bits_prot = 3'h0;
assign io_m0_readAddr_bits_qos = 4'h0;
assign io_m0_readData_ready = 1'h0;
assign io_s0_writeAddr_ready = slave_fsm_io_slave_writeAddr_ready;
assign io_s0_writeData_ready = slave_fsm_io_slave_writeData_ready;
assign io_s0_writeResp_valid = slave_fsm_io_slave_writeResp_valid;
assign io_s0_writeResp_bits = 2'h0;
assign io_s0_readAddr_ready = slave_fsm_io_slave_readAddr_ready;
assign io_s0_readData_valid = slave_fsm_io_slave_readData_valid;
assign io_s0_readData_bits_data = slave_fsm_io_slave_readData_bits_data;
assign io_s0_readData_bits_resp = 2'h0;
assign slave_fsm_clock = clock;
assign slave_fsm_reset = _T_88;
assign slave_fsm_io_slave_writeAddr_valid = io_s0_writeAddr_valid;
assign slave_fsm_io_slave_writeAddr_bits_addr = io_s0_writeAddr_bits_addr;
assign slave_fsm_io_slave_writeData_valid = io_s0_writeData_valid;
assign slave_fsm_io_slave_writeData_bits_data = io_s0_writeData_bits_data;
assign slave_fsm_io_slave_writeData_bits_strb = io_s0_writeData_bits_strb;
assign slave_fsm_io_slave_writeResp_ready = io_s0_writeResp_ready;
assign slave_fsm_io_slave_readAddr_valid = io_s0_readAddr_valid;
assign slave_fsm_io_slave_readAddr_bits_addr = io_s0_readAddr_bits_addr;
assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;
assign slave_fsm_io_ap_done = RTLKernel_io_ap_done;
assign RTLKernel_clock = clock;
assign RTLKernel_reset = _T_88;
assign RTLKernel_io_ap_start = slave_fsm_io_ap_start;
assign _T_88 = reset == 1'h0;
endmodule | 17 |
3,044 | data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 632 | module | module AXILiteControl(
input ap_clk,
input ap_rst_n,
output io_slave_writeAddr_ready,
input io_slave_writeAddr_valid,
input [63:0] io_slave_writeAddr_bits_addr,
output io_slave_writeData_ready,
input io_slave_writeData_valid,
input [31:0] io_slave_writeData_bits_data,
input [3:0] io_slave_writeData_bits_strb,
input io_slave_writeResp_ready,
output io_slave_writeResp_valid,
output io_slave_readAddr_ready,
input io_slave_readAddr_valid,
input [63:0] io_slave_readAddr_bits_addr,
input io_slave_readData_ready,
output io_slave_readData_valid,
output [31:0] io_slave_readData_bits_data,
output io_ap_start,
input io_ap_done
);
reg ap_start;
reg [31:0] _RAND_0;
reg auto_restart;
reg [31:0] _RAND_1;
reg ap_idle;
reg [31:0] _RAND_2;
reg ap_done;
reg [31:0] _RAND_3;
reg ap_start_r;
reg [31:0] _RAND_4;
wire _T_50;
wire ap_start_pulse;
wire _GEN_0;
wire _T_53;
wire _T_54;
wire _GEN_1;
wire _T_59;
wire _T_60;
wire _GEN_2;
reg [2:0] stateSlaveWrite;
reg [31:0] _RAND_5;
reg [5:0] writeAddr;
reg [31:0] _RAND_6;
reg [2:0] stateSlaveRead;
reg [31:0] _RAND_7;
reg [31:0] readData;
reg [31:0] _RAND_8;
wire _T_69;
wire _T_70;
wire _T_71;
wire _T_72;
wire _T_118;
wire addrwr_handshake;
wire write_handshake;
wire [63:0] _GEN_3;
wire [2:0] _GEN_4;
wire _T_121;
wire [2:0] _GEN_5;
wire [2:0] _GEN_6;
wire _T_124;
wire _T_125;
wire [2:0] _GEN_7;
wire _T_127;
wire [2:0] _GEN_8;
wire [2:0] _GEN_9;
wire _T_132;
wire _T_133;
wire _T_134;
wire [2:0] _GEN_10;
wire _T_136;
wire [2:0] _GEN_11;
wire [2:0] _GEN_12;
wire _T_143;
wire _T_144;
wire [2:0] _GEN_13;
wire _T_147;
wire _T_148;
wire _T_149;
wire addrrd_handshake;
wire [2:0] _GEN_14;
wire _T_152;
wire [2:0] _GEN_15;
wire [2:0] _GEN_16;
wire _T_155;
wire _T_156;
wire _T_157;
wire [2:0] _GEN_17;
wire _T_159;
wire [2:0] _GEN_18;
wire [2:0] _GEN_19;
wire _T_163;
wire _T_164;
wire [2:0] _GEN_20;
wire _T_165;
wire [1:0] _GEN_27;
wire [1:0] _T_166;
wire [1:0] _GEN_28;
wire [1:0] _T_167;
wire [2:0] _GEN_29;
wire [2:0] _T_168;
wire [2:0] _GEN_30;
wire [2:0] _T_169;
wire [3:0] _GEN_31;
wire [3:0] _T_170;
wire [3:0] _GEN_32;
wire [3:0] _T_171;
wire [7:0] _GEN_33;
wire [7:0] _T_172;
wire [7:0] _GEN_34;
wire [7:0] _T_173;
wire [31:0] _GEN_21;
wire [31:0] _GEN_22;
wire _T_174;
wire _T_175;
wire _T_176;
wire _T_177;
wire _T_178;
wire _T_179;
wire _GEN_23;
wire _T_182;
wire _T_183;
wire _GEN_24;
wire _T_185;
wire _GEN_25;
wire _T_191;
wire _GEN_26;
assign io_slave_writeAddr_ready = _T_71;
assign io_slave_writeData_ready = _T_72;
assign io_slave_writeResp_valid = _T_118;
assign io_slave_readAddr_ready = _T_148;
assign io_slave_readData_valid = _T_149;
assign io_slave_readData_bits_data = readData;
assign io_ap_start = ap_start;
assign _T_50 = ap_start_r == 1'h0;
assign ap_start_pulse = ap_start & _T_50;
assign _GEN_0 = ap_done ? 1'h1 : ap_idle;
assign _T_53 = ap_done == 1'h0;
assign _T_54 = _T_53 & ap_start_pulse;
assign _GEN_1 = _T_54 ? 1'h0 : _GEN_0;
assign _T_59 = ap_start_pulse == 1'h0;
assign _T_60 = _T_53 & _T_59;
assign _GEN_2 = _T_60 ? ap_idle : _GEN_1;
assign _T_69 = ap_rst_n == 1'h0;
assign _T_70 = stateSlaveWrite == 3'h0;
assign _T_71 = _T_69 & _T_70;
assign _T_72 = stateSlaveWrite == 3'h1;
assign _T_118 = stateSlaveWrite == 3'h2;
assign addrwr_handshake = io_slave_writeAddr_valid & io_slave_writeAddr_ready;
assign write_handshake = io_slave_writeData_valid & io_slave_writeData_ready;
assign _GEN_3 = addrwr_handshake ? io_slave_writeAddr_bits_addr : {{58'd0}, writeAddr};
assign _GEN_4 = io_slave_writeAddr_valid ? 3'h1 : stateSlaveWrite;
assign _T_121 = io_slave_writeAddr_valid == 1'h0;
assign _GEN_5 = _T_121 ? 3'h0 : _GEN_4;
assign _GEN_6 = _T_70 ? _GEN_5 : stateSlaveWrite;
assign _T_124 = _T_70 == 1'h0;
assign _T_125 = _T_124 & _T_72;
assign _GEN_7 = io_slave_writeData_valid ? 3'h2 : _GEN_6;
assign _T_127 = io_slave_writeData_valid == 1'h0;
assign _GEN_8 = _T_127 ? 3'h1 : _GEN_7;
assign _GEN_9 = _T_125 ? _GEN_8 : _GEN_6;
assign _T_132 = _T_72 == 1'h0;
assign _T_133 = _T_124 & _T_132;
assign _T_134 = _T_133 & _T_118;
assign _GEN_10 = io_slave_writeResp_ready ? 3'h0 : _GEN_9;
assign _T_136 = io_slave_writeResp_ready == 1'h0;
assign _GEN_11 = _T_136 ? 3'h2 : _GEN_10;
assign _GEN_12 = _T_134 ? _GEN_11 : _GEN_9;
assign _T_143 = _T_118 == 1'h0;
assign _T_144 = _T_133 & _T_143;
assign _GEN_13 = _T_144 ? 3'h0 : _GEN_12;
assign _T_147 = stateSlaveRead == 3'h0;
assign _T_148 = _T_69 & _T_147;
assign _T_149 = stateSlaveRead == 3'h3;
assign addrrd_handshake = io_slave_readAddr_valid & io_slave_readAddr_ready;
assign _GEN_14 = io_slave_readAddr_valid ? 3'h3 : stateSlaveRead;
assign _T_152 = io_slave_readAddr_valid == 1'h0;
assign _GEN_15 = _T_152 ? 3'h0 : _GEN_14;
assign _GEN_16 = _T_147 ? _GEN_15 : stateSlaveRead;
assign _T_155 = _T_147 == 1'h0;
assign _T_156 = _T_155 & _T_149;
assign _T_157 = io_slave_readData_valid & io_slave_readData_ready;
assign _GEN_17 = _T_157 ? 3'h0 : _GEN_16;
assign _T_159 = _T_157 == 1'h0;
assign _GEN_18 = _T_159 ? 3'h3 : _GEN_17;
assign _GEN_19 = _T_156 ? _GEN_18 : _GEN_16;
assign _T_163 = _T_149 == 1'h0;
assign _T_164 = _T_155 & _T_163;
assign _GEN_20 = _T_164 ? 3'h0 : _GEN_19;
assign _T_165 = io_slave_readAddr_bits_addr == 64'h0;
assign _GEN_27 = {{1'd0}, ap_done};
assign _T_166 = _GEN_27 << 1;
assign _GEN_28 = {{1'd0}, ap_start};
assign _T_167 = _GEN_28 | _T_166;
assign _GEN_29 = {{2'd0}, ap_idle};
assign _T_168 = _GEN_29 << 2;
assign _GEN_30 = {{1'd0}, _T_167};
assign _T_169 = _GEN_30 | _T_168;
assign _GEN_31 = {{3'd0}, ap_done};
assign _T_170 = _GEN_31 << 3;
assign _GEN_32 = {{1'd0}, _T_169};
assign _T_171 = _GEN_32 | _T_170;
assign _GEN_33 = {{7'd0}, auto_restart};
assign _T_172 = _GEN_33 << 7;
assign _GEN_34 = {{4'd0}, _T_171};
assign _T_173 = _GEN_34 | _T_172;
assign _GEN_21 = _T_165 ? {{24'd0}, _T_173} : readData;
assign _GEN_22 = addrrd_handshake ? _GEN_21 : readData;
assign _T_174 = writeAddr == 6'h0;
assign _T_175 = write_handshake & _T_174;
assign _T_176 = io_slave_writeData_bits_strb[0];
assign _T_177 = _T_175 & _T_176;
assign _T_178 = io_slave_writeData_bits_data[0];
assign _T_179 = _T_177 & _T_178;
assign _GEN_23 = _T_179 ? 1'h1 : ap_start;
assign _T_182 = _T_179 == 1'h0;
assign _T_183 = _T_182 & ap_done;
assign _GEN_24 = _T_183 ? auto_restart : _GEN_23;
assign _T_185 = addrrd_handshake & _T_165;
assign _GEN_25 = _T_185 ? 1'h0 : io_ap_done;
assign _T_191 = io_slave_writeData_bits_data[7];
assign _GEN_26 = _T_177 ? _T_191 : auto_restart;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
ap_start = _RAND_0[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
auto_restart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
ap_idle = _RAND_2[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{$random}};
ap_done = _RAND_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{$random}};
ap_start_r = _RAND_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{$random}};
stateSlaveWrite = _RAND_5[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{$random}};
writeAddr = _RAND_6[5:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{$random}};
stateSlaveRead = _RAND_7[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{$random}};
readData = _RAND_8[31:0];
`endif
end
`endif
always @(posedge ap_clk) begin
if (ap_rst_n) begin
ap_start <= 1'h0;
end else begin
if (_T_183) begin
ap_start <= auto_restart;
end else begin
if (_T_179) begin
ap_start <= 1'h1;
end
end
end
if (ap_rst_n) begin
auto_restart <= 1'h0;
end else begin
if (_T_177) begin
auto_restart <= _T_191;
end
end
if (ap_rst_n) begin
ap_idle <= 1'h1;
end else begin
if (!(_T_60)) begin
if (_T_54) begin
ap_idle <= 1'h0;
end else begin
if (ap_done) begin
ap_idle <= 1'h1;
end
end
end
end
if (ap_rst_n) begin
ap_done <= 1'h0;
end else begin
if (_T_185) begin
ap_done <= 1'h0;
end else begin
ap_done <= io_ap_done;
end
end
if (ap_rst_n) begin
ap_start_r <= 1'h0;
end else begin
ap_start_r <= ap_start;
end
if (ap_rst_n) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_144) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_134) begin
if (_T_136) begin
stateSlaveWrite <= 3'h2;
end else begin
if (io_slave_writeResp_ready) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end
if (ap_rst_n) begin
writeAddr <= 6'h0;
end else begin
writeAddr <= _GEN_3[5:0];
end
if (ap_rst_n) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_164) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_156) begin
if (_T_159) begin
stateSlaveRead <= 3'h3;
end else begin
if (_T_157) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end
if (ap_rst_n) begin
readData <= 32'h0;
end else begin
if (addrrd_handshake) begin
if (_T_165) begin
readData <= {{24'd0}, _T_173};
end
end
end
end
endmodule | module AXILiteControl(
input ap_clk,
input ap_rst_n,
output io_slave_writeAddr_ready,
input io_slave_writeAddr_valid,
input [63:0] io_slave_writeAddr_bits_addr,
output io_slave_writeData_ready,
input io_slave_writeData_valid,
input [31:0] io_slave_writeData_bits_data,
input [3:0] io_slave_writeData_bits_strb,
input io_slave_writeResp_ready,
output io_slave_writeResp_valid,
output io_slave_readAddr_ready,
input io_slave_readAddr_valid,
input [63:0] io_slave_readAddr_bits_addr,
input io_slave_readData_ready,
output io_slave_readData_valid,
output [31:0] io_slave_readData_bits_data,
output io_ap_start,
input io_ap_done
); |
reg ap_start;
reg [31:0] _RAND_0;
reg auto_restart;
reg [31:0] _RAND_1;
reg ap_idle;
reg [31:0] _RAND_2;
reg ap_done;
reg [31:0] _RAND_3;
reg ap_start_r;
reg [31:0] _RAND_4;
wire _T_50;
wire ap_start_pulse;
wire _GEN_0;
wire _T_53;
wire _T_54;
wire _GEN_1;
wire _T_59;
wire _T_60;
wire _GEN_2;
reg [2:0] stateSlaveWrite;
reg [31:0] _RAND_5;
reg [5:0] writeAddr;
reg [31:0] _RAND_6;
reg [2:0] stateSlaveRead;
reg [31:0] _RAND_7;
reg [31:0] readData;
reg [31:0] _RAND_8;
wire _T_69;
wire _T_70;
wire _T_71;
wire _T_72;
wire _T_118;
wire addrwr_handshake;
wire write_handshake;
wire [63:0] _GEN_3;
wire [2:0] _GEN_4;
wire _T_121;
wire [2:0] _GEN_5;
wire [2:0] _GEN_6;
wire _T_124;
wire _T_125;
wire [2:0] _GEN_7;
wire _T_127;
wire [2:0] _GEN_8;
wire [2:0] _GEN_9;
wire _T_132;
wire _T_133;
wire _T_134;
wire [2:0] _GEN_10;
wire _T_136;
wire [2:0] _GEN_11;
wire [2:0] _GEN_12;
wire _T_143;
wire _T_144;
wire [2:0] _GEN_13;
wire _T_147;
wire _T_148;
wire _T_149;
wire addrrd_handshake;
wire [2:0] _GEN_14;
wire _T_152;
wire [2:0] _GEN_15;
wire [2:0] _GEN_16;
wire _T_155;
wire _T_156;
wire _T_157;
wire [2:0] _GEN_17;
wire _T_159;
wire [2:0] _GEN_18;
wire [2:0] _GEN_19;
wire _T_163;
wire _T_164;
wire [2:0] _GEN_20;
wire _T_165;
wire [1:0] _GEN_27;
wire [1:0] _T_166;
wire [1:0] _GEN_28;
wire [1:0] _T_167;
wire [2:0] _GEN_29;
wire [2:0] _T_168;
wire [2:0] _GEN_30;
wire [2:0] _T_169;
wire [3:0] _GEN_31;
wire [3:0] _T_170;
wire [3:0] _GEN_32;
wire [3:0] _T_171;
wire [7:0] _GEN_33;
wire [7:0] _T_172;
wire [7:0] _GEN_34;
wire [7:0] _T_173;
wire [31:0] _GEN_21;
wire [31:0] _GEN_22;
wire _T_174;
wire _T_175;
wire _T_176;
wire _T_177;
wire _T_178;
wire _T_179;
wire _GEN_23;
wire _T_182;
wire _T_183;
wire _GEN_24;
wire _T_185;
wire _GEN_25;
wire _T_191;
wire _GEN_26;
assign io_slave_writeAddr_ready = _T_71;
assign io_slave_writeData_ready = _T_72;
assign io_slave_writeResp_valid = _T_118;
assign io_slave_readAddr_ready = _T_148;
assign io_slave_readData_valid = _T_149;
assign io_slave_readData_bits_data = readData;
assign io_ap_start = ap_start;
assign _T_50 = ap_start_r == 1'h0;
assign ap_start_pulse = ap_start & _T_50;
assign _GEN_0 = ap_done ? 1'h1 : ap_idle;
assign _T_53 = ap_done == 1'h0;
assign _T_54 = _T_53 & ap_start_pulse;
assign _GEN_1 = _T_54 ? 1'h0 : _GEN_0;
assign _T_59 = ap_start_pulse == 1'h0;
assign _T_60 = _T_53 & _T_59;
assign _GEN_2 = _T_60 ? ap_idle : _GEN_1;
assign _T_69 = ap_rst_n == 1'h0;
assign _T_70 = stateSlaveWrite == 3'h0;
assign _T_71 = _T_69 & _T_70;
assign _T_72 = stateSlaveWrite == 3'h1;
assign _T_118 = stateSlaveWrite == 3'h2;
assign addrwr_handshake = io_slave_writeAddr_valid & io_slave_writeAddr_ready;
assign write_handshake = io_slave_writeData_valid & io_slave_writeData_ready;
assign _GEN_3 = addrwr_handshake ? io_slave_writeAddr_bits_addr : {{58'd0}, writeAddr};
assign _GEN_4 = io_slave_writeAddr_valid ? 3'h1 : stateSlaveWrite;
assign _T_121 = io_slave_writeAddr_valid == 1'h0;
assign _GEN_5 = _T_121 ? 3'h0 : _GEN_4;
assign _GEN_6 = _T_70 ? _GEN_5 : stateSlaveWrite;
assign _T_124 = _T_70 == 1'h0;
assign _T_125 = _T_124 & _T_72;
assign _GEN_7 = io_slave_writeData_valid ? 3'h2 : _GEN_6;
assign _T_127 = io_slave_writeData_valid == 1'h0;
assign _GEN_8 = _T_127 ? 3'h1 : _GEN_7;
assign _GEN_9 = _T_125 ? _GEN_8 : _GEN_6;
assign _T_132 = _T_72 == 1'h0;
assign _T_133 = _T_124 & _T_132;
assign _T_134 = _T_133 & _T_118;
assign _GEN_10 = io_slave_writeResp_ready ? 3'h0 : _GEN_9;
assign _T_136 = io_slave_writeResp_ready == 1'h0;
assign _GEN_11 = _T_136 ? 3'h2 : _GEN_10;
assign _GEN_12 = _T_134 ? _GEN_11 : _GEN_9;
assign _T_143 = _T_118 == 1'h0;
assign _T_144 = _T_133 & _T_143;
assign _GEN_13 = _T_144 ? 3'h0 : _GEN_12;
assign _T_147 = stateSlaveRead == 3'h0;
assign _T_148 = _T_69 & _T_147;
assign _T_149 = stateSlaveRead == 3'h3;
assign addrrd_handshake = io_slave_readAddr_valid & io_slave_readAddr_ready;
assign _GEN_14 = io_slave_readAddr_valid ? 3'h3 : stateSlaveRead;
assign _T_152 = io_slave_readAddr_valid == 1'h0;
assign _GEN_15 = _T_152 ? 3'h0 : _GEN_14;
assign _GEN_16 = _T_147 ? _GEN_15 : stateSlaveRead;
assign _T_155 = _T_147 == 1'h0;
assign _T_156 = _T_155 & _T_149;
assign _T_157 = io_slave_readData_valid & io_slave_readData_ready;
assign _GEN_17 = _T_157 ? 3'h0 : _GEN_16;
assign _T_159 = _T_157 == 1'h0;
assign _GEN_18 = _T_159 ? 3'h3 : _GEN_17;
assign _GEN_19 = _T_156 ? _GEN_18 : _GEN_16;
assign _T_163 = _T_149 == 1'h0;
assign _T_164 = _T_155 & _T_163;
assign _GEN_20 = _T_164 ? 3'h0 : _GEN_19;
assign _T_165 = io_slave_readAddr_bits_addr == 64'h0;
assign _GEN_27 = {{1'd0}, ap_done};
assign _T_166 = _GEN_27 << 1;
assign _GEN_28 = {{1'd0}, ap_start};
assign _T_167 = _GEN_28 | _T_166;
assign _GEN_29 = {{2'd0}, ap_idle};
assign _T_168 = _GEN_29 << 2;
assign _GEN_30 = {{1'd0}, _T_167};
assign _T_169 = _GEN_30 | _T_168;
assign _GEN_31 = {{3'd0}, ap_done};
assign _T_170 = _GEN_31 << 3;
assign _GEN_32 = {{1'd0}, _T_169};
assign _T_171 = _GEN_32 | _T_170;
assign _GEN_33 = {{7'd0}, auto_restart};
assign _T_172 = _GEN_33 << 7;
assign _GEN_34 = {{4'd0}, _T_171};
assign _T_173 = _GEN_34 | _T_172;
assign _GEN_21 = _T_165 ? {{24'd0}, _T_173} : readData;
assign _GEN_22 = addrrd_handshake ? _GEN_21 : readData;
assign _T_174 = writeAddr == 6'h0;
assign _T_175 = write_handshake & _T_174;
assign _T_176 = io_slave_writeData_bits_strb[0];
assign _T_177 = _T_175 & _T_176;
assign _T_178 = io_slave_writeData_bits_data[0];
assign _T_179 = _T_177 & _T_178;
assign _GEN_23 = _T_179 ? 1'h1 : ap_start;
assign _T_182 = _T_179 == 1'h0;
assign _T_183 = _T_182 & ap_done;
assign _GEN_24 = _T_183 ? auto_restart : _GEN_23;
assign _T_185 = addrrd_handshake & _T_165;
assign _GEN_25 = _T_185 ? 1'h0 : io_ap_done;
assign _T_191 = io_slave_writeData_bits_data[7];
assign _GEN_26 = _T_177 ? _T_191 : auto_restart;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
ap_start = _RAND_0[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
auto_restart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
ap_idle = _RAND_2[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{$random}};
ap_done = _RAND_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{$random}};
ap_start_r = _RAND_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{$random}};
stateSlaveWrite = _RAND_5[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{$random}};
writeAddr = _RAND_6[5:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{$random}};
stateSlaveRead = _RAND_7[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{$random}};
readData = _RAND_8[31:0];
`endif
end
`endif
always @(posedge ap_clk) begin
if (ap_rst_n) begin
ap_start <= 1'h0;
end else begin
if (_T_183) begin
ap_start <= auto_restart;
end else begin
if (_T_179) begin
ap_start <= 1'h1;
end
end
end
if (ap_rst_n) begin
auto_restart <= 1'h0;
end else begin
if (_T_177) begin
auto_restart <= _T_191;
end
end
if (ap_rst_n) begin
ap_idle <= 1'h1;
end else begin
if (!(_T_60)) begin
if (_T_54) begin
ap_idle <= 1'h0;
end else begin
if (ap_done) begin
ap_idle <= 1'h1;
end
end
end
end
if (ap_rst_n) begin
ap_done <= 1'h0;
end else begin
if (_T_185) begin
ap_done <= 1'h0;
end else begin
ap_done <= io_ap_done;
end
end
if (ap_rst_n) begin
ap_start_r <= 1'h0;
end else begin
ap_start_r <= ap_start;
end
if (ap_rst_n) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_144) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_134) begin
if (_T_136) begin
stateSlaveWrite <= 3'h2;
end else begin
if (io_slave_writeResp_ready) begin
stateSlaveWrite <= 3'h0;
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end else begin
if (_T_125) begin
if (_T_127) begin
stateSlaveWrite <= 3'h1;
end else begin
if (io_slave_writeData_valid) begin
stateSlaveWrite <= 3'h2;
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end else begin
if (_T_70) begin
if (_T_121) begin
stateSlaveWrite <= 3'h0;
end else begin
if (io_slave_writeAddr_valid) begin
stateSlaveWrite <= 3'h1;
end
end
end
end
end
end
end
if (ap_rst_n) begin
writeAddr <= 6'h0;
end else begin
writeAddr <= _GEN_3[5:0];
end
if (ap_rst_n) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_164) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_156) begin
if (_T_159) begin
stateSlaveRead <= 3'h3;
end else begin
if (_T_157) begin
stateSlaveRead <= 3'h0;
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end else begin
if (_T_147) begin
if (_T_152) begin
stateSlaveRead <= 3'h0;
end else begin
if (io_slave_readAddr_valid) begin
stateSlaveRead <= 3'h3;
end
end
end
end
end
end
if (ap_rst_n) begin
readData <= 32'h0;
end else begin
if (addrrd_handshake) begin
if (_T_165) begin
readData <= {{24'd0}, _T_173};
end
end
end
end
endmodule | 17 |
3,045 | data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 632 | module | module MyKernel(
input ap_clk,
input ap_rst_n,
input io_ap_start,
output io_ap_done
);
reg [4:0] value;
reg [31:0] _RAND_0;
reg regFlagStart;
reg [31:0] _RAND_1;
reg doneReg;
reg [31:0] _RAND_2;
wire _T_18;
wire _T_19;
wire _T_21;
wire [5:0] _T_23;
wire [4:0] _T_24;
wire [4:0] _GEN_0;
wire [4:0] _GEN_1;
wire _GEN_2;
wire _T_28;
wire _GEN_3;
assign io_ap_done = doneReg;
assign _T_18 = regFlagStart == 1'h0;
assign _T_19 = io_ap_start & _T_18;
assign _T_21 = value == 5'h1d;
assign _T_23 = value + 5'h1;
assign _T_24 = _T_23[4:0];
assign _GEN_0 = _T_21 ? 5'h0 : _T_24;
assign _GEN_1 = _T_19 ? _GEN_0 : value;
assign _GEN_2 = _T_19 ? 1'h1 : regFlagStart;
assign _T_28 = value > 5'h0;
assign _GEN_3 = _T_28 ? 1'h1 : doneReg;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
regFlagStart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
doneReg = _RAND_2[0:0];
`endif
end
`endif
always @(posedge ap_clk) begin
if (ap_rst_n) begin
value <= 5'h0;
end else begin
if (_T_19) begin
if (_T_21) begin
value <= 5'h0;
end else begin
value <= _T_24;
end
end
end
if (ap_rst_n) begin
regFlagStart <= 1'h0;
end else begin
if (_T_19) begin
regFlagStart <= 1'h1;
end
end
if (ap_rst_n) begin
doneReg <= 1'h0;
end else begin
if (_T_28) begin
doneReg <= 1'h1;
end
end
end
endmodule | module MyKernel(
input ap_clk,
input ap_rst_n,
input io_ap_start,
output io_ap_done
); |
reg [4:0] value;
reg [31:0] _RAND_0;
reg regFlagStart;
reg [31:0] _RAND_1;
reg doneReg;
reg [31:0] _RAND_2;
wire _T_18;
wire _T_19;
wire _T_21;
wire [5:0] _T_23;
wire [4:0] _T_24;
wire [4:0] _GEN_0;
wire [4:0] _GEN_1;
wire _GEN_2;
wire _T_28;
wire _GEN_3;
assign io_ap_done = doneReg;
assign _T_18 = regFlagStart == 1'h0;
assign _T_19 = io_ap_start & _T_18;
assign _T_21 = value == 5'h1d;
assign _T_23 = value + 5'h1;
assign _T_24 = _T_23[4:0];
assign _GEN_0 = _T_21 ? 5'h0 : _T_24;
assign _GEN_1 = _T_19 ? _GEN_0 : value;
assign _GEN_2 = _T_19 ? 1'h1 : regFlagStart;
assign _T_28 = value > 5'h0;
assign _GEN_3 = _T_28 ? 1'h1 : doneReg;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
regFlagStart = _RAND_1[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
doneReg = _RAND_2[0:0];
`endif
end
`endif
always @(posedge ap_clk) begin
if (ap_rst_n) begin
value <= 5'h0;
end else begin
if (_T_19) begin
if (_T_21) begin
value <= 5'h0;
end else begin
value <= _T_24;
end
end
end
if (ap_rst_n) begin
regFlagStart <= 1'h0;
end else begin
if (_T_19) begin
regFlagStart <= 1'h1;
end
end
if (ap_rst_n) begin
doneReg <= 1'h0;
end else begin
if (_T_28) begin
doneReg <= 1'h1;
end
end
end
endmodule | 17 |
3,046 | data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v | 102,486,364 | SDAChiselWrapper.v | v | 699 | 90 | [] | [] | [] | [(14, 455), (456, 536), (537, 698)] | null | null | 1: b'%Error: data/full_repos/permissive/102486364/verilog_xilinx/SDAChiselWrapper.v:692: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance SDAChiselWrapper\n assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;\n ^\n%Error: Exiting due to 1 error(s)\n' | 632 | module | module SDAChiselWrapper(
input ap_clk,
input ap_rst_n,
input m_axi_gmem_AWREADY,
output m_axi_gmem_AWVALID,
output [63:0] m_axi_gmem_AWADDR,
output [2:0] m_axi_gmem_AWSIZE,
output [7:0] m_axi_gmem_AWLEN,
output [1:0] m_axi_gmem_AWBURST,
output m_axi_gmem_AWID,
output m_axi_gmem_AWLOCK,
output [3:0] m_axi_gmem_AWCACHE,
output [2:0] m_axi_gmem_AWPROT,
output [3:0] m_axi_gmem_AWQOS,
input m_axi_gmem_WREADY,
output m_axi_gmem_WVALID,
output [511:0] m_axi_gmem_WDATA,
output [63:0] m_axi_gmem_WSTRB,
output m_axi_gmem_WLAST,
output m_axi_gmem_BREADY,
input m_axi_gmem_BVALID,
input m_axi_gmem_BID,
input [1:0] m_axi_gmem_BRESP,
input m_axi_gmem_ARREADY,
output m_axi_gmem_ARVALID,
output [63:0] m_axi_gmem_ARADDR,
output [2:0] m_axi_gmem_ARSIZE,
output [7:0] m_axi_gmem_ARLEN,
output [1:0] m_axi_gmem_ARBURST,
output m_axi_gmem_ARID,
output m_axi_gmem_ARLOCK,
output [3:0] m_axi_gmem_ARCACHE,
output [2:0] m_axi_gmem_ARPROT,
output [3:0] m_axi_gmem_ARQOS,
output m_axi_gmem_RREADY,
input m_axi_gmem_RVALID,
input [511:0] m_axi_gmem_RDATA,
input m_axi_gmem_RID,
input m_axi_gmem_RLAST,
input [1:0] m_axi_gmem_RRESP,
output S_AXI_CONTROL_AWREADY,
input S_AXI_CONTROL_AWVALID,
input [63:0] S_AXI_CONTROL_AWADDR,
input [2:0] S_AXI_CONTROL_AWPROT,
output S_AXI_CONTROL_WREADY,
input S_AXI_CONTROL_WVALID,
input [31:0] S_AXI_CONTROL_WDATA,
input [3:0] S_AXI_CONTROL_WSTRB,
input S_AXI_CONTROL_BREADY,
output S_AXI_CONTROL_BVALID,
output [1:0] S_AXI_CONTROL_BRESP,
output S_AXI_CONTROL_ARREADY,
input S_AXI_CONTROL_ARVALID,
input [63:0] S_AXI_CONTROL_ARADDR,
input [2:0] S_AXI_CONTROL_ARPROT,
input S_AXI_CONTROL_RREADY,
output S_AXI_CONTROL_RVALID,
output [31:0] S_AXI_CONTROL_RDATA,
output [1:0] S_AXI_CONTROL_RRESP
);
wire slave_fsm_ap_clk;
wire slave_fsm_ap_rst_n;
wire slave_fsm_io_slave_writeAddr_ready;
wire slave_fsm_io_slave_writeAddr_valid;
wire [63:0] slave_fsm_io_slave_writeAddr_bits_addr;
wire slave_fsm_io_slave_writeData_ready;
wire slave_fsm_io_slave_writeData_valid;
wire [31:0] slave_fsm_io_slave_writeData_bits_data;
wire [3:0] slave_fsm_io_slave_writeData_bits_strb;
wire slave_fsm_io_slave_writeResp_ready;
wire slave_fsm_io_slave_writeResp_valid;
wire slave_fsm_io_slave_readAddr_ready;
wire slave_fsm_io_slave_readAddr_valid;
wire [63:0] slave_fsm_io_slave_readAddr_bits_addr;
wire slave_fsm_io_slave_readData_ready;
wire slave_fsm_io_slave_readData_valid;
wire [31:0] slave_fsm_io_slave_readData_bits_data;
wire slave_fsm_io_ap_start;
wire slave_fsm_io_ap_done;
wire RTLKernel_ap_clk;
wire RTLKernel_ap_rst_n;
wire RTLKernel_io_ap_start;
wire RTLKernel_io_ap_done;
wire _T_88;
AXILiteControl slave_fsm (
.ap_clk(slave_fsm_ap_clk),
.ap_rst_n(slave_fsm_ap_rst_n),
.io_slave_writeAddr_ready(slave_fsm_io_slave_writeAddr_ready),
.io_slave_writeAddr_valid(slave_fsm_io_slave_writeAddr_valid),
.io_slave_writeAddr_bits_addr(slave_fsm_io_slave_writeAddr_bits_addr),
.io_slave_writeData_ready(slave_fsm_io_slave_writeData_ready),
.io_slave_writeData_valid(slave_fsm_io_slave_writeData_valid),
.io_slave_writeData_bits_data(slave_fsm_io_slave_writeData_bits_data),
.io_slave_writeData_bits_strb(slave_fsm_io_slave_writeData_bits_strb),
.io_slave_writeResp_ready(slave_fsm_io_slave_writeResp_ready),
.io_slave_writeResp_valid(slave_fsm_io_slave_writeResp_valid),
.io_slave_readAddr_ready(slave_fsm_io_slave_readAddr_ready),
.io_slave_readAddr_valid(slave_fsm_io_slave_readAddr_valid),
.io_slave_readAddr_bits_addr(slave_fsm_io_slave_readAddr_bits_addr),
.io_slave_readData_ready(slave_fsm_io_slave_readData_ready),
.io_slave_readData_valid(slave_fsm_io_slave_readData_valid),
.io_slave_readData_bits_data(slave_fsm_io_slave_readData_bits_data),
.io_ap_start(slave_fsm_io_ap_start),
.io_ap_done(slave_fsm_io_ap_done)
);
MyKernel RTLKernel (
.ap_clk(RTLKernel_ap_clk),
.ap_rst_n(RTLKernel_ap_rst_n),
.io_ap_start(RTLKernel_io_ap_start),
.io_ap_done(RTLKernel_io_ap_done)
);
assign m_axi_gmem_AWVALID = 1'h0;
assign m_axi_gmem_AWADDR = 64'h0;
assign m_axi_gmem_AWSIZE = 3'h0;
assign m_axi_gmem_AWLEN = 8'h0;
assign m_axi_gmem_AWBURST = 2'h0;
assign m_axi_gmem_AWID = 1'h0;
assign m_axi_gmem_AWLOCK = 1'h0;
assign m_axi_gmem_AWCACHE = 4'h0;
assign m_axi_gmem_AWPROT = 3'h0;
assign m_axi_gmem_AWQOS = 4'h0;
assign m_axi_gmem_WVALID = 1'h0;
assign m_axi_gmem_WDATA = 512'h0;
assign m_axi_gmem_WSTRB = 64'h0;
assign m_axi_gmem_WLAST = 1'h0;
assign m_axi_gmem_BREADY = 1'h0;
assign m_axi_gmem_ARVALID = 1'h0;
assign m_axi_gmem_ARADDR = 64'h0;
assign m_axi_gmem_ARSIZE = 3'h0;
assign m_axi_gmem_ARLEN = 8'h0;
assign m_axi_gmem_ARBURST = 2'h0;
assign m_axi_gmem_ARID = 1'h0;
assign m_axi_gmem_ARLOCK = 1'h0;
assign m_axi_gmem_ARCACHE = 4'h0;
assign m_axi_gmem_ARPROT = 3'h0;
assign m_axi_gmem_ARQOS = 4'h0;
assign m_axi_gmem_RREADY = 1'h0;
assign S_AXI_CONTROL_AWREADY = slave_fsm_io_slave_writeAddr_ready;
assign S_AXI_CONTROL_WREADY = slave_fsm_io_slave_writeData_ready;
assign S_AXI_CONTROL_BVALID = slave_fsm_io_slave_writeResp_valid;
assign S_AXI_CONTROL_BRESP = 2'h0;
assign S_AXI_CONTROL_ARREADY = slave_fsm_io_slave_readAddr_ready;
assign S_AXI_CONTROL_RVALID = slave_fsm_io_slave_readData_valid;
assign S_AXI_CONTROL_RDATA = slave_fsm_io_slave_readData_bits_data;
assign S_AXI_CONTROL_RRESP = 2'h0;
assign slave_fsm_ap_clk = ap_clk;
assign slave_fsm_ap_rst_n = _T_88;
assign slave_fsm_io_slave_writeAddr_valid = S_AXI_CONTROL_AWVALID;
assign slave_fsm_io_slave_writeAddr_bits_addr = S_AXI_CONTROL_AWADDR;
assign slave_fsm_io_slave_writeData_valid = S_AXI_CONTROL_WVALID;
assign slave_fsm_io_slave_writeData_bits_data = S_AXI_CONTROL_WDATA;
assign slave_fsm_io_slave_writeData_bits_strb = S_AXI_CONTROL_WSTRB;
assign slave_fsm_io_slave_writeResp_ready = S_AXI_CONTROL_BREADY;
assign slave_fsm_io_slave_readAddr_valid = S_AXI_CONTROL_ARVALID;
assign slave_fsm_io_slave_readAddr_bits_addr = S_AXI_CONTROL_ARADDR;
assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;
assign slave_fsm_io_ap_done = RTLKernel_io_ap_done;
assign RTLKernel_ap_clk = ap_clk;
assign RTLKernel_ap_rst_n = _T_88;
assign RTLKernel_io_ap_start = slave_fsm_io_ap_start;
assign _T_88 = ap_rst_n == 1'h0;
endmodule | module SDAChiselWrapper(
input ap_clk,
input ap_rst_n,
input m_axi_gmem_AWREADY,
output m_axi_gmem_AWVALID,
output [63:0] m_axi_gmem_AWADDR,
output [2:0] m_axi_gmem_AWSIZE,
output [7:0] m_axi_gmem_AWLEN,
output [1:0] m_axi_gmem_AWBURST,
output m_axi_gmem_AWID,
output m_axi_gmem_AWLOCK,
output [3:0] m_axi_gmem_AWCACHE,
output [2:0] m_axi_gmem_AWPROT,
output [3:0] m_axi_gmem_AWQOS,
input m_axi_gmem_WREADY,
output m_axi_gmem_WVALID,
output [511:0] m_axi_gmem_WDATA,
output [63:0] m_axi_gmem_WSTRB,
output m_axi_gmem_WLAST,
output m_axi_gmem_BREADY,
input m_axi_gmem_BVALID,
input m_axi_gmem_BID,
input [1:0] m_axi_gmem_BRESP,
input m_axi_gmem_ARREADY,
output m_axi_gmem_ARVALID,
output [63:0] m_axi_gmem_ARADDR,
output [2:0] m_axi_gmem_ARSIZE,
output [7:0] m_axi_gmem_ARLEN,
output [1:0] m_axi_gmem_ARBURST,
output m_axi_gmem_ARID,
output m_axi_gmem_ARLOCK,
output [3:0] m_axi_gmem_ARCACHE,
output [2:0] m_axi_gmem_ARPROT,
output [3:0] m_axi_gmem_ARQOS,
output m_axi_gmem_RREADY,
input m_axi_gmem_RVALID,
input [511:0] m_axi_gmem_RDATA,
input m_axi_gmem_RID,
input m_axi_gmem_RLAST,
input [1:0] m_axi_gmem_RRESP,
output S_AXI_CONTROL_AWREADY,
input S_AXI_CONTROL_AWVALID,
input [63:0] S_AXI_CONTROL_AWADDR,
input [2:0] S_AXI_CONTROL_AWPROT,
output S_AXI_CONTROL_WREADY,
input S_AXI_CONTROL_WVALID,
input [31:0] S_AXI_CONTROL_WDATA,
input [3:0] S_AXI_CONTROL_WSTRB,
input S_AXI_CONTROL_BREADY,
output S_AXI_CONTROL_BVALID,
output [1:0] S_AXI_CONTROL_BRESP,
output S_AXI_CONTROL_ARREADY,
input S_AXI_CONTROL_ARVALID,
input [63:0] S_AXI_CONTROL_ARADDR,
input [2:0] S_AXI_CONTROL_ARPROT,
input S_AXI_CONTROL_RREADY,
output S_AXI_CONTROL_RVALID,
output [31:0] S_AXI_CONTROL_RDATA,
output [1:0] S_AXI_CONTROL_RRESP
); |
wire slave_fsm_ap_clk;
wire slave_fsm_ap_rst_n;
wire slave_fsm_io_slave_writeAddr_ready;
wire slave_fsm_io_slave_writeAddr_valid;
wire [63:0] slave_fsm_io_slave_writeAddr_bits_addr;
wire slave_fsm_io_slave_writeData_ready;
wire slave_fsm_io_slave_writeData_valid;
wire [31:0] slave_fsm_io_slave_writeData_bits_data;
wire [3:0] slave_fsm_io_slave_writeData_bits_strb;
wire slave_fsm_io_slave_writeResp_ready;
wire slave_fsm_io_slave_writeResp_valid;
wire slave_fsm_io_slave_readAddr_ready;
wire slave_fsm_io_slave_readAddr_valid;
wire [63:0] slave_fsm_io_slave_readAddr_bits_addr;
wire slave_fsm_io_slave_readData_ready;
wire slave_fsm_io_slave_readData_valid;
wire [31:0] slave_fsm_io_slave_readData_bits_data;
wire slave_fsm_io_ap_start;
wire slave_fsm_io_ap_done;
wire RTLKernel_ap_clk;
wire RTLKernel_ap_rst_n;
wire RTLKernel_io_ap_start;
wire RTLKernel_io_ap_done;
wire _T_88;
AXILiteControl slave_fsm (
.ap_clk(slave_fsm_ap_clk),
.ap_rst_n(slave_fsm_ap_rst_n),
.io_slave_writeAddr_ready(slave_fsm_io_slave_writeAddr_ready),
.io_slave_writeAddr_valid(slave_fsm_io_slave_writeAddr_valid),
.io_slave_writeAddr_bits_addr(slave_fsm_io_slave_writeAddr_bits_addr),
.io_slave_writeData_ready(slave_fsm_io_slave_writeData_ready),
.io_slave_writeData_valid(slave_fsm_io_slave_writeData_valid),
.io_slave_writeData_bits_data(slave_fsm_io_slave_writeData_bits_data),
.io_slave_writeData_bits_strb(slave_fsm_io_slave_writeData_bits_strb),
.io_slave_writeResp_ready(slave_fsm_io_slave_writeResp_ready),
.io_slave_writeResp_valid(slave_fsm_io_slave_writeResp_valid),
.io_slave_readAddr_ready(slave_fsm_io_slave_readAddr_ready),
.io_slave_readAddr_valid(slave_fsm_io_slave_readAddr_valid),
.io_slave_readAddr_bits_addr(slave_fsm_io_slave_readAddr_bits_addr),
.io_slave_readData_ready(slave_fsm_io_slave_readData_ready),
.io_slave_readData_valid(slave_fsm_io_slave_readData_valid),
.io_slave_readData_bits_data(slave_fsm_io_slave_readData_bits_data),
.io_ap_start(slave_fsm_io_ap_start),
.io_ap_done(slave_fsm_io_ap_done)
);
MyKernel RTLKernel (
.ap_clk(RTLKernel_ap_clk),
.ap_rst_n(RTLKernel_ap_rst_n),
.io_ap_start(RTLKernel_io_ap_start),
.io_ap_done(RTLKernel_io_ap_done)
);
assign m_axi_gmem_AWVALID = 1'h0;
assign m_axi_gmem_AWADDR = 64'h0;
assign m_axi_gmem_AWSIZE = 3'h0;
assign m_axi_gmem_AWLEN = 8'h0;
assign m_axi_gmem_AWBURST = 2'h0;
assign m_axi_gmem_AWID = 1'h0;
assign m_axi_gmem_AWLOCK = 1'h0;
assign m_axi_gmem_AWCACHE = 4'h0;
assign m_axi_gmem_AWPROT = 3'h0;
assign m_axi_gmem_AWQOS = 4'h0;
assign m_axi_gmem_WVALID = 1'h0;
assign m_axi_gmem_WDATA = 512'h0;
assign m_axi_gmem_WSTRB = 64'h0;
assign m_axi_gmem_WLAST = 1'h0;
assign m_axi_gmem_BREADY = 1'h0;
assign m_axi_gmem_ARVALID = 1'h0;
assign m_axi_gmem_ARADDR = 64'h0;
assign m_axi_gmem_ARSIZE = 3'h0;
assign m_axi_gmem_ARLEN = 8'h0;
assign m_axi_gmem_ARBURST = 2'h0;
assign m_axi_gmem_ARID = 1'h0;
assign m_axi_gmem_ARLOCK = 1'h0;
assign m_axi_gmem_ARCACHE = 4'h0;
assign m_axi_gmem_ARPROT = 3'h0;
assign m_axi_gmem_ARQOS = 4'h0;
assign m_axi_gmem_RREADY = 1'h0;
assign S_AXI_CONTROL_AWREADY = slave_fsm_io_slave_writeAddr_ready;
assign S_AXI_CONTROL_WREADY = slave_fsm_io_slave_writeData_ready;
assign S_AXI_CONTROL_BVALID = slave_fsm_io_slave_writeResp_valid;
assign S_AXI_CONTROL_BRESP = 2'h0;
assign S_AXI_CONTROL_ARREADY = slave_fsm_io_slave_readAddr_ready;
assign S_AXI_CONTROL_RVALID = slave_fsm_io_slave_readData_valid;
assign S_AXI_CONTROL_RDATA = slave_fsm_io_slave_readData_bits_data;
assign S_AXI_CONTROL_RRESP = 2'h0;
assign slave_fsm_ap_clk = ap_clk;
assign slave_fsm_ap_rst_n = _T_88;
assign slave_fsm_io_slave_writeAddr_valid = S_AXI_CONTROL_AWVALID;
assign slave_fsm_io_slave_writeAddr_bits_addr = S_AXI_CONTROL_AWADDR;
assign slave_fsm_io_slave_writeData_valid = S_AXI_CONTROL_WVALID;
assign slave_fsm_io_slave_writeData_bits_data = S_AXI_CONTROL_WDATA;
assign slave_fsm_io_slave_writeData_bits_strb = S_AXI_CONTROL_WSTRB;
assign slave_fsm_io_slave_writeResp_ready = S_AXI_CONTROL_BREADY;
assign slave_fsm_io_slave_readAddr_valid = S_AXI_CONTROL_ARVALID;
assign slave_fsm_io_slave_readAddr_bits_addr = S_AXI_CONTROL_ARADDR;
assign slave_fsm_io_slave_readData_ready = slave_fsm_io_slave_readData_ready;
assign slave_fsm_io_ap_done = RTLKernel_io_ap_done;
assign RTLKernel_ap_clk = ap_clk;
assign RTLKernel_ap_rst_n = _T_88;
assign RTLKernel_io_ap_start = slave_fsm_io_ap_start;
assign _T_88 = ap_rst_n == 1'h0;
endmodule | 17 |
3,048 | data/full_repos/permissive/102490099/sdram_rw_de2.v | 102,490,099 | sdram_rw_de2.v | v | 275 | 81 | [] | [] | [] | [(41, 273)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102490099/sdram_rw_de2.v:204: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 bits.\n : ... In instance sdram_rw\n if( (read_cntr & 32\'h01))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102490099/sdram_rw_de2.v:228: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 bits.\n : ... In instance sdram_rw\n if( read_cntr & 32\'h01)\n ^~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:265: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg0 ( hex0, state[3:0]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT\n data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT.v\n data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT.sv\n SEG7_LUT\n SEG7_LUT.v\n SEG7_LUT.sv\n obj_dir/SEG7_LUT\n obj_dir/SEG7_LUT.v\n obj_dir/SEG7_LUT.sv\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:266: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg1 ( hex1, time_count[3:0]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:267: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg2 ( hex2, time_count[7:4]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:268: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg3 ( hex3, time_count[11:8]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:269: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg4 ( hex4, time_count[15:12]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:270: Cannot find file containing module: \'SEG7_LUT\'\n SEG7_LUT seg5 ( hex5, time_count[19:16]);\n ^~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n' | 636 | module | module sdram_rw
(
input clk_i,
input rst_i,
output [24:0] addr_i,
output [31:0] dat_i,
input [31:0] dat_o,
output we_i,
input ack_o,
output stb_i,
output cyc_i,
input init_done,
output [0:0] green_led,
output [0:0] red_led,
output [7:0] hex0,
output [7:0] hex1,
output [7:0] hex2,
output [7:0] hex3,
output [7:0] hex4,
output [7:0] hex5,
input [9:0] switches
);
parameter START_WRITE_ST = 4'b0000,
WRITE_ST = 4'b0001,
WAIT_WRITE_ACK_ST = 4'b0010,
READ_ST = 4'b0011,
WAIT_READ_ACK_ST = 4'b0100,
WRITE_WAIT_ST = 4'b0101,
START_READ_ST = 4'b0110,
READ_WAIT_ST = 4'b0111,
DONE_ST = 4'b1000,
DONE_WAIT_ST = 4'b1001,
WRITE_SECOND_BANK = 4'b1010,
WAIT_WRITE2_ACK_ST = 4'b1011;
parameter MAX_RW = 24'd0002000;
parameter R_TO_W_WAIT_TIME = 24'd1;
parameter INITIAL_MEM_VALUE =32'h00005678;
reg [24:0] addr_i_r;
reg [31:0] dat_i_r;
reg we_i_r;
reg stb_i_r;
reg cyc_i_r;
reg [23:0] rw_cntr;
reg [23:0] cntr;
reg [31:0] number;
reg [31:0] mem_value;
reg [3:0] state;
reg [31:0] read_cntr, time_count;
reg [7:0] bad_count;
reg [0:0] red_led_r;
reg [0:0] green_led_r;
assign dat_i = dat_i_r;
assign addr_i = addr_i_r;
assign we_i = we_i_r;
assign stb_i = stb_i_r;
assign cyc_i = cyc_i_r;
assign red_led = red_led_r;
assign green_led = green_led_r;
initial begin
mem_value <= INITIAL_MEM_VALUE;
cntr <= 24'b0;
rw_cntr <= 24'b0;
state <= DONE_WAIT_ST;
we_i_r <= 1'b0;
addr_i_r <= 25'b0;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
red_led_r <= 1'b0;
green_led_r <= 1'b0;
read_cntr <= 0;
end
always@ (posedge clk_i or posedge rst_i) begin
if( rst_i && state == DONE_WAIT_ST ) begin
state <= START_WRITE_ST;
red_led_r <= 1'b0;
green_led_r <= 1'b0;
rw_cntr <= 24'b0;
addr_i_r <= 25'd0;
bad_count <= switches[7:0];
time_count <= 0;
end else begin
case (state)
START_WRITE_ST:
begin
state <= WRITE_ST;
end
WRITE_ST:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
dat_i_r <= mem_value;
we_i_r <= 1'b1;
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
state <= WAIT_WRITE_ACK_ST;
end
WAIT_WRITE_ACK_ST:
if (ack_o) begin
state <= WRITE_SECOND_BANK;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
read_cntr <= 0;
bad_count <= 0;
end
else rw_cntr <= rw_cntr + 24'b1;
WRITE_SECOND_BANK:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
dat_i_r <= mem_value + 1;
we_i_r <= 1'b1;
addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
state <= WAIT_WRITE2_ACK_ST;
end
WAIT_WRITE2_ACK_ST:
if (ack_o) begin
state <= READ_ST;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
read_cntr <= 0;
bad_count <= 0;
end
else rw_cntr <= rw_cntr + 24'b1;
READ_ST:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
we_i_r <= 1'b0;
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
state <= WAIT_READ_ACK_ST;
end
WAIT_READ_ACK_ST:
if (ack_o) begin
state <= READ_WAIT_ST;
number <= dat_o;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
end
else rw_cntr <= rw_cntr + 24'b1;
READ_WAIT_ST:
begin
if( (read_cntr & 32'h01))
begin
if (mem_value + 1 != number) begin
bad_count <= bad_count + 1;
red_led_r[0] <= 1'b1;
end
end else
begin
if (mem_value != number) begin
bad_count <= bad_count + 1;
red_led_r[0] <= 1'b1;
end
end
read_cntr <= read_cntr + 1;
if( read_cntr == 'h00ffffff)
begin
mem_value <= mem_value + 1'b1;
state <= DONE_ST;
time_count <= number;
end else begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
we_i_r <= 1'b0;
if( read_cntr & 32'h01)
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
else
addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
state <= WAIT_READ_ACK_ST;
end
end
DONE_ST:
begin
state <= DONE_WAIT_ST;
if (!red_led_r[0])
green_led_r[0] <= 1'b1;
else
green_led_r[0] <= 1'b0;
end
DONE_WAIT_ST:
begin
end
endcase
end
end
always@ (posedge clk_i) begin
if (rst_i) begin
cntr <= 24'b0;
end else if (state == WRITE_WAIT_ST) begin
cntr <= R_TO_W_WAIT_TIME;
end else
cntr <= cntr - 24'b1;
end
SEG7_LUT seg0 ( hex0, state[3:0]);
SEG7_LUT seg1 ( hex1, time_count[3:0]);
SEG7_LUT seg2 ( hex2, time_count[7:4]);
SEG7_LUT seg3 ( hex3, time_count[11:8]);
SEG7_LUT seg4 ( hex4, time_count[15:12]);
SEG7_LUT seg5 ( hex5, time_count[19:16]);
endmodule | module sdram_rw
(
input clk_i,
input rst_i,
output [24:0] addr_i,
output [31:0] dat_i,
input [31:0] dat_o,
output we_i,
input ack_o,
output stb_i,
output cyc_i,
input init_done,
output [0:0] green_led,
output [0:0] red_led,
output [7:0] hex0,
output [7:0] hex1,
output [7:0] hex2,
output [7:0] hex3,
output [7:0] hex4,
output [7:0] hex5,
input [9:0] switches
); |
parameter START_WRITE_ST = 4'b0000,
WRITE_ST = 4'b0001,
WAIT_WRITE_ACK_ST = 4'b0010,
READ_ST = 4'b0011,
WAIT_READ_ACK_ST = 4'b0100,
WRITE_WAIT_ST = 4'b0101,
START_READ_ST = 4'b0110,
READ_WAIT_ST = 4'b0111,
DONE_ST = 4'b1000,
DONE_WAIT_ST = 4'b1001,
WRITE_SECOND_BANK = 4'b1010,
WAIT_WRITE2_ACK_ST = 4'b1011;
parameter MAX_RW = 24'd0002000;
parameter R_TO_W_WAIT_TIME = 24'd1;
parameter INITIAL_MEM_VALUE =32'h00005678;
reg [24:0] addr_i_r;
reg [31:0] dat_i_r;
reg we_i_r;
reg stb_i_r;
reg cyc_i_r;
reg [23:0] rw_cntr;
reg [23:0] cntr;
reg [31:0] number;
reg [31:0] mem_value;
reg [3:0] state;
reg [31:0] read_cntr, time_count;
reg [7:0] bad_count;
reg [0:0] red_led_r;
reg [0:0] green_led_r;
assign dat_i = dat_i_r;
assign addr_i = addr_i_r;
assign we_i = we_i_r;
assign stb_i = stb_i_r;
assign cyc_i = cyc_i_r;
assign red_led = red_led_r;
assign green_led = green_led_r;
initial begin
mem_value <= INITIAL_MEM_VALUE;
cntr <= 24'b0;
rw_cntr <= 24'b0;
state <= DONE_WAIT_ST;
we_i_r <= 1'b0;
addr_i_r <= 25'b0;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
red_led_r <= 1'b0;
green_led_r <= 1'b0;
read_cntr <= 0;
end
always@ (posedge clk_i or posedge rst_i) begin
if( rst_i && state == DONE_WAIT_ST ) begin
state <= START_WRITE_ST;
red_led_r <= 1'b0;
green_led_r <= 1'b0;
rw_cntr <= 24'b0;
addr_i_r <= 25'd0;
bad_count <= switches[7:0];
time_count <= 0;
end else begin
case (state)
START_WRITE_ST:
begin
state <= WRITE_ST;
end
WRITE_ST:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
dat_i_r <= mem_value;
we_i_r <= 1'b1;
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
state <= WAIT_WRITE_ACK_ST;
end
WAIT_WRITE_ACK_ST:
if (ack_o) begin
state <= WRITE_SECOND_BANK;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
read_cntr <= 0;
bad_count <= 0;
end
else rw_cntr <= rw_cntr + 24'b1;
WRITE_SECOND_BANK:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
dat_i_r <= mem_value + 1;
we_i_r <= 1'b1;
addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
state <= WAIT_WRITE2_ACK_ST;
end
WAIT_WRITE2_ACK_ST:
if (ack_o) begin
state <= READ_ST;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
read_cntr <= 0;
bad_count <= 0;
end
else rw_cntr <= rw_cntr + 24'b1;
READ_ST:
begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
we_i_r <= 1'b0;
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
state <= WAIT_READ_ACK_ST;
end
WAIT_READ_ACK_ST:
if (ack_o) begin
state <= READ_WAIT_ST;
number <= dat_o;
stb_i_r <= 1'b0;
cyc_i_r <= 1'b0;
end
else rw_cntr <= rw_cntr + 24'b1;
READ_WAIT_ST:
begin
if( (read_cntr & 32'h01))
begin
if (mem_value + 1 != number) begin
bad_count <= bad_count + 1;
red_led_r[0] <= 1'b1;
end
end else
begin
if (mem_value != number) begin
bad_count <= bad_count + 1;
red_led_r[0] <= 1'b1;
end
end
read_cntr <= read_cntr + 1;
if( read_cntr == 'h00ffffff)
begin
mem_value <= mem_value + 1'b1;
state <= DONE_ST;
time_count <= number;
end else begin
stb_i_r <= 1'b1;
cyc_i_r <= 1'b1;
we_i_r <= 1'b0;
if( read_cntr & 32'h01)
addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
else
addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
state <= WAIT_READ_ACK_ST;
end
end
DONE_ST:
begin
state <= DONE_WAIT_ST;
if (!red_led_r[0])
green_led_r[0] <= 1'b1;
else
green_led_r[0] <= 1'b0;
end
DONE_WAIT_ST:
begin
end
endcase
end
end
always@ (posedge clk_i) begin
if (rst_i) begin
cntr <= 24'b0;
end else if (state == WRITE_WAIT_ST) begin
cntr <= R_TO_W_WAIT_TIME;
end else
cntr <= cntr - 24'b1;
end
SEG7_LUT seg0 ( hex0, state[3:0]);
SEG7_LUT seg1 ( hex1, time_count[3:0]);
SEG7_LUT seg2 ( hex2, time_count[7:4]);
SEG7_LUT seg3 ( hex3, time_count[11:8]);
SEG7_LUT seg4 ( hex4, time_count[15:12]);
SEG7_LUT seg5 ( hex5, time_count[19:16]);
endmodule | 1 |
3,049 | data/full_repos/permissive/102515926/Modules/CIRCUIT1.v | 102,515,926 | CIRCUIT1.v | v | 28 | 83 | [] | [] | [] | [(9, 27)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:19: Cannot find file containing module: 'ADD'\n ADD #(8) ADD_1(a, b, d);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:20: Cannot find file containing module: 'ADD'\n ADD #(8) ADD_2(a, c, e);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:21: Cannot find file containing module: 'COMP'\n COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:22: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:23: Cannot find file containing module: 'MUL'\n MUL #(8) MUL_1(a, c, f);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:24: Cannot find file containing module: 'SUB'\n SUB #(16) SUB_1(f, d, xwire);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:25: Cannot find file containing module: 'REG'\n REG #(16) REG_1(xwire, Clk, Rst, x);\n ^~~\n%Error: Exiting due to 7 error(s)\n" | 639 | module | module CIRCUIT1(a, b, c, x, z, Clk, Rst);
input Clk, Rst;
input [7:0] a, b, c;
output [7:0] z;
output [15:0] x;
wire [7:0] d, e;
wire [15:0] f, g_lt, g_gt, g_eq, xwire;
ADD #(8) ADD_1(a, b, d);
ADD #(8) ADD_2(a, c, e);
COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);
MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);
MUL #(8) MUL_1(a, c, f);
SUB #(16) SUB_1(f, d, xwire);
REG #(16) REG_1(xwire, Clk, Rst, x);
endmodule | module CIRCUIT1(a, b, c, x, z, Clk, Rst); |
input Clk, Rst;
input [7:0] a, b, c;
output [7:0] z;
output [15:0] x;
wire [7:0] d, e;
wire [15:0] f, g_lt, g_gt, g_eq, xwire;
ADD #(8) ADD_1(a, b, d);
ADD #(8) ADD_2(a, c, e);
COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);
MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);
MUL #(8) MUL_1(a, c, f);
SUB #(16) SUB_1(f, d, xwire);
REG #(16) REG_1(xwire, Clk, Rst, x);
endmodule | 0 |
3,050 | data/full_repos/permissive/102515926/Modules/CIRCUIT2.v | 102,515,926 | CIRCUIT2.v | v | 29 | 83 | [] | [] | [] | [(9, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:18: Cannot find file containing module: 'ADD'\n ADD #(32) ADD_1(a, b, d);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:19: Cannot find file containing module: 'ADD'\n ADD #(32) ADD_2(a, c, e);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:20: Cannot find file containing module: 'SUB'\n SUB #(32) SUB_1(a, b, f);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:21: Cannot find file containing module: 'COMP'\n COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:22: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:23: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:24: Cannot find file containing module: 'SHL'\n SHL #(32) SHL_1(g, dLTe, xwire);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:25: Cannot find file containing module: 'SHR'\n SHR #(32) SHR_1(h, dEQe, zwire);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:26: Cannot find file containing module: 'REG'\n REG #(32) REG_1(xwire, Clk, Rst, x);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:27: Cannot find file containing module: 'REG'\n REG #(32) REG_2(zwire, Clk, Rst, z);\n ^~~\n%Error: Exiting due to 10 error(s)\n" | 640 | module | module CIRCUIT2(a, b, c, x, z, Clk, Rst);
input [31:0] a, b, c;
input Clk, Rst;
output [31:0] x, z;
wire [31:0] d, e, f, g, h;
wire dLTe, dEQe, dGTe;
wire [31:0] xwire, zwire;
ADD #(32) ADD_1(a, b, d);
ADD #(32) ADD_2(a, c, e);
SUB #(32) SUB_1(a, b, f);
COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);
MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);
MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);
SHL #(32) SHL_1(g, dLTe, xwire);
SHR #(32) SHR_1(h, dEQe, zwire);
REG #(32) REG_1(xwire, Clk, Rst, x);
REG #(32) REG_2(zwire, Clk, Rst, z);
endmodule | module CIRCUIT2(a, b, c, x, z, Clk, Rst); |
input [31:0] a, b, c;
input Clk, Rst;
output [31:0] x, z;
wire [31:0] d, e, f, g, h;
wire dLTe, dEQe, dGTe;
wire [31:0] xwire, zwire;
ADD #(32) ADD_1(a, b, d);
ADD #(32) ADD_2(a, c, e);
SUB #(32) SUB_1(a, b, f);
COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);
MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);
MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);
SHL #(32) SHL_1(g, dLTe, xwire);
SHR #(32) SHR_1(h, dEQe, zwire);
REG #(32) REG_1(xwire, Clk, Rst, x);
REG #(32) REG_2(zwire, Clk, Rst, z);
endmodule | 0 |
3,051 | data/full_repos/permissive/102515926/Modules/CIRCUIT3.v | 102,515,926 | CIRCUIT3.v | v | 31 | 83 | [] | [] | [] | [(9, 30)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:18: Cannot find file containing module: 'ADD'\n ADD #(16) ADD_1(a, b, l00);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:19: Cannot find file containing module: 'ADD'\n ADD #(16) ADD_2(c, d, l01);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:20: Cannot find file containing module: 'ADD'\n ADD #(16) ADD_3(e, f, l02);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:21: Cannot find file containing module: 'ADD'\n ADD #(16) ADD_4(g, h, l03);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:22: Cannot find file containing module: 'ADD'\n ADD #(32) ADD_5(l00, l01, l10);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:23: Cannot find file containing module: 'ADD'\n ADD #(32) ADD_6(l02, l03, l11);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:24: Cannot find file containing module: 'ADD'\n ADD #(32) ADD_7(l10, l11, l2);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:25: Cannot find file containing module: 'SHR'\n SHR #(32) SHR_1(l2, sa, l2div2);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:26: Cannot find file containing module: 'SHR'\n SHR #(32) SHR_2(l2div2, sa, l2div4);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:27: Cannot find file containing module: 'SHR'\n SHR #(32) SHR_3(l2div4, sa, l2div8);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:28: Cannot find file containing module: 'REG'\n REG #(32) REG_1(l2div8, Clk, Rst, avg);\n ^~~\n%Error: Exiting due to 11 error(s)\n" | 641 | module | module CIRCUIT3(a, b, c, d, e, f, g, h, sa, avg, Clk, Rst);
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h;
input [7:0] sa;
output [15:0] avg;
wire [31:0] l00, l01, l02, l03, l10, l11, l2, l2div2, l2div4, l2div8;
ADD #(16) ADD_1(a, b, l00);
ADD #(16) ADD_2(c, d, l01);
ADD #(16) ADD_3(e, f, l02);
ADD #(16) ADD_4(g, h, l03);
ADD #(32) ADD_5(l00, l01, l10);
ADD #(32) ADD_6(l02, l03, l11);
ADD #(32) ADD_7(l10, l11, l2);
SHR #(32) SHR_1(l2, sa, l2div2);
SHR #(32) SHR_2(l2div2, sa, l2div4);
SHR #(32) SHR_3(l2div4, sa, l2div8);
REG #(32) REG_1(l2div8, Clk, Rst, avg);
endmodule | module CIRCUIT3(a, b, c, d, e, f, g, h, sa, avg, Clk, Rst); |
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h;
input [7:0] sa;
output [15:0] avg;
wire [31:0] l00, l01, l02, l03, l10, l11, l2, l2div2, l2div4, l2div8;
ADD #(16) ADD_1(a, b, l00);
ADD #(16) ADD_2(c, d, l01);
ADD #(16) ADD_3(e, f, l02);
ADD #(16) ADD_4(g, h, l03);
ADD #(32) ADD_5(l00, l01, l10);
ADD #(32) ADD_6(l02, l03, l11);
ADD #(32) ADD_7(l10, l11, l2);
SHR #(32) SHR_1(l2, sa, l2div2);
SHR #(32) SHR_2(l2div2, sa, l2div4);
SHR #(32) SHR_3(l2div4, sa, l2div8);
REG #(32) REG_1(l2div8, Clk, Rst, avg);
endmodule | 0 |
3,052 | data/full_repos/permissive/102515926/Modules/CIRCUIT4.v | 102,515,926 | CIRCUIT4.v | v | 34 | 83 | [] | [] | [] | [(9, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT4.v:9: Unexpected 'final': 'final' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule CIRCUIT4(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, Clk, Rst, final);\n ^~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT4.v:13: Unexpected 'final': 'final' is a SystemVerilog keyword misused as an identifier.\n output [31:0] final;\n ^~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT4.v:32: syntax error, unexpected final, expecting ')'\n REG #(32) reg1(t14, Clk, Rst, final);\n ^~~~~\n%Error: Exiting due to 3 error(s)\n" | 642 | module | module CIRCUIT4(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, Clk, Rst, final);
input Clk, Rst;
input [7:0] a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
output [31:0] final;
wire [31:0] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14;
ADD #(8) add1(a, b, t1);
ADD #(32) add2(t1, c, t2);
ADD #(32) add3(t2, d, t3);
ADD #(32) add4(t3, e, t4);
ADD #(32) add5(t4, f, t5);
ADD #(32) add6(t5, g, t6);
ADD #(32) add7(t6, h, t7);
ADD #(32) add8(t7, i, t8);
ADD #(32) add9(t8, j, t9);
ADD #(32) add10(t9, l, t10);
ADD #(32) add11(t10, m, t11);
ADD #(32) add12(t11, n, t12);
ADD #(32) add13(t12, o, t13);
ADD #(32) add14(t13, p, t14);
REG #(32) reg1(t14, Clk, Rst, final);
endmodule | module CIRCUIT4(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, Clk, Rst, final); |
input Clk, Rst;
input [7:0] a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
output [31:0] final;
wire [31:0] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14;
ADD #(8) add1(a, b, t1);
ADD #(32) add2(t1, c, t2);
ADD #(32) add3(t2, d, t3);
ADD #(32) add4(t3, e, t4);
ADD #(32) add5(t4, f, t5);
ADD #(32) add6(t5, g, t6);
ADD #(32) add7(t6, h, t7);
ADD #(32) add8(t7, i, t8);
ADD #(32) add9(t8, j, t9);
ADD #(32) add10(t9, l, t10);
ADD #(32) add11(t10, m, t11);
ADD #(32) add12(t11, n, t12);
ADD #(32) add13(t12, o, t13);
ADD #(32) add14(t13, p, t14);
REG #(32) reg1(t14, Clk, Rst, final);
endmodule | 0 |
3,053 | data/full_repos/permissive/102515926/Modules/CIRCUIT5.v | 102,515,926 | CIRCUIT5.v | v | 38 | 83 | [] | [] | [] | null | line:24: before: "," | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:21: Cannot find file containing module: 'ADD'\n ADD #(64) add1(a, b, d);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:22: Cannot find file containing module: 'ADD'\n ADD #(64) add2(a, c, e);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:23: Cannot find file containing module: 'SUB'\n SUB #(64) sub1(a, b, f);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:24: Cannot find file containing module: 'COMP'\n COMP #(64) comp1(d, e, , , dEQe);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:25: Cannot find file containing module: 'COMP'\n COMP #(64) comp2(d, e, , dLTe, );\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:26: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(64) mux1(e, d, dLTe, g);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:27: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(64) mux2(f, g, dEQe, h);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:28: Cannot find file containing module: 'SHL'\n SHL #(64) shl1(hreg, dLTe, xrin);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:29: Cannot find file containing module: 'SHR'\n SHR #(64) shr1(greg, dEQe, zrin);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:31: Cannot find file containing module: 'REG'\n REG #(64) reg1(xrin, Clk, Rst, x);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT5.v:32: Cannot find file containing module: 'REG'\n REG #(64) reg2(zrin, Clk, Rst, z);\n ^~~\n%Error: Exiting due to 11 error(s)\n" | 643 | module | module CIRCUIT5(a, b, c, Clk, Rst, x, z);
input Clk, Rst;
input [63:0] a, b, c;
output [31:0] x, z;
wire [63:0] d, e, f, g, h;
wire dLTe, dEQe;
wire [63:0] xrin, zrin;
reg [63:0] greg, hreg;
ADD #(64) add1(a, b, d);
ADD #(64) add2(a, c, e);
SUB #(64) sub1(a, b, f);
COMP #(64) comp1(d, e, , , dEQe);
COMP #(64) comp2(d, e, , dLTe, );
MUX2x1 #(64) mux1(e, d, dLTe, g);
MUX2x1 #(64) mux2(f, g, dEQe, h);
SHL #(64) shl1(hreg, dLTe, xrin);
SHR #(64) shr1(greg, dEQe, zrin);
REG #(64) reg1(xrin, Clk, Rst, x);
REG #(64) reg2(zrin, Clk, Rst, z);
always @(g, h) begin
greg <= g; hreg <= h;
end
endmodule | module CIRCUIT5(a, b, c, Clk, Rst, x, z); |
input Clk, Rst;
input [63:0] a, b, c;
output [31:0] x, z;
wire [63:0] d, e, f, g, h;
wire dLTe, dEQe;
wire [63:0] xrin, zrin;
reg [63:0] greg, hreg;
ADD #(64) add1(a, b, d);
ADD #(64) add2(a, c, e);
SUB #(64) sub1(a, b, f);
COMP #(64) comp1(d, e, , , dEQe);
COMP #(64) comp2(d, e, , dLTe, );
MUX2x1 #(64) mux1(e, d, dLTe, g);
MUX2x1 #(64) mux2(f, g, dEQe, h);
SHL #(64) shl1(hreg, dLTe, xrin);
SHR #(64) shr1(greg, dEQe, zrin);
REG #(64) reg1(xrin, Clk, Rst, x);
REG #(64) reg2(zrin, Clk, Rst, z);
always @(g, h) begin
greg <= g; hreg <= h;
end
endmodule | 0 |
3,054 | data/full_repos/permissive/102515926/Modules/CIRCUIT6.v | 102,515,926 | CIRCUIT6.v | v | 42 | 83 | [] | [] | [] | [(9, 42)] | null | null | 1: b'%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:21: Cannot find file containing module: \'ADD\'\n ADD #(16) add1(a, b, t1);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:22: Cannot find file containing module: \'ADD\'\n ADD #(16) add2(r1, c, t2);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:23: Cannot find file containing module: \'ADD\'\n ADD #(16) add3(r2, d, t3);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:24: Cannot find file containing module: \'ADD\'\n ADD #(16) add4(r3, e, t4);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:25: Cannot find file containing module: \'ADD\'\n ADD #(16) add5(r4, f, t5);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:26: Cannot find file containing module: \'ADD\'\n ADD #(16) add6(r5, g, t6);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:27: Cannot find file containing module: \'ADD\'\n ADD #(16) add7(r6, h, t7);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:29: Cannot find file containing module: \'DIV\'\n DIV #(16) div1(r7, num, avgwire);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:30: Cannot find file containing module: \'REG\'\n REG #(16) reg8(avgwire, Clk, Rst, avg);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:33: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t1\' generates 32 bits.\n : ... In instance CIRCUIT6\n r1 <= t1;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:34: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t2\' generates 32 bits.\n : ... In instance CIRCUIT6\n r2 <= t2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:35: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t3\' generates 32 bits.\n : ... In instance CIRCUIT6\n r3 <= t3;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:36: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t4\' generates 32 bits.\n : ... In instance CIRCUIT6\n r4 <= t4;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:37: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t5\' generates 32 bits.\n : ... In instance CIRCUIT6\n r5 <= t5;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:38: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t6\' generates 32 bits.\n : ... In instance CIRCUIT6\n r6 <= t6;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:39: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t7\' generates 32 bits.\n : ... In instance CIRCUIT6\n r7 <= t7;\n ^~\n%Error: Exiting due to 9 error(s), 7 warning(s)\n' | 644 | module | module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg);
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h, num;
output [15:0] avg;
reg [15:0] r1, r2, r3, r4, r5, r6, r7;
wire [15:0] avgwire;
wire [31:0] t1, t2, t3, t4, t5, t6, t7;
ADD #(16) add1(a, b, t1);
ADD #(16) add2(r1, c, t2);
ADD #(16) add3(r2, d, t3);
ADD #(16) add4(r3, e, t4);
ADD #(16) add5(r4, f, t5);
ADD #(16) add6(r5, g, t6);
ADD #(16) add7(r6, h, t7);
DIV #(16) div1(r7, num, avgwire);
REG #(16) reg8(avgwire, Clk, Rst, avg);
always @(r1, r2, r3, r4, r5, r6, r7) begin
r1 <= t1;
r2 <= t2;
r3 <= t3;
r4 <= t4;
r5 <= t5;
r6 <= t6;
r7 <= t7;
end
endmodule | module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg); |
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h, num;
output [15:0] avg;
reg [15:0] r1, r2, r3, r4, r5, r6, r7;
wire [15:0] avgwire;
wire [31:0] t1, t2, t3, t4, t5, t6, t7;
ADD #(16) add1(a, b, t1);
ADD #(16) add2(r1, c, t2);
ADD #(16) add3(r2, d, t3);
ADD #(16) add4(r3, e, t4);
ADD #(16) add5(r4, f, t5);
ADD #(16) add6(r5, g, t6);
ADD #(16) add7(r6, h, t7);
DIV #(16) div1(r7, num, avgwire);
REG #(16) reg8(avgwire, Clk, Rst, avg);
always @(r1, r2, r3, r4, r5, r6, r7) begin
r1 <= t1;
r2 <= t2;
r3 <= t3;
r4 <= t4;
r5 <= t5;
r6 <= t6;
r7 <= t7;
end
endmodule | 0 |
3,055 | data/full_repos/permissive/102515926/Modules/CIRCUIT7.v | 102,515,926 | CIRCUIT7.v | v | 26 | 83 | [] | [] | [] | [(9, 26)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:19: Cannot find file containing module: 'DIV'\n DIV #(64) div1(a, b, e);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DIV\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DIV.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DIV.sv\n DIV\n DIV.v\n DIV.sv\n obj_dir/DIV\n obj_dir/DIV.v\n obj_dir/DIV.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:20: Cannot find file containing module: 'DIV'\n DIV #(64) div2(c, d, f);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:21: Cannot find file containing module: 'MOD'\n MOD #(64) mod1(a, b, g);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:22: Cannot find file containing module: 'COMP'\n COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:23: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(64) mux1(f, e, gEQz, zwire);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT7.v:24: Cannot find file containing module: 'REG'\n REG #(64) reg1(zwire, Clk, Rst, z);\n ^~~\n%Error: Exiting due to 6 error(s)\n" | 645 | module | module CIRCUIT7(a, b, c, d, zero, Clk, Rst, z);
input Clk, Rst;
input [63:0] a, b, c, d, zero;
output [63:0] z;
wire [63:0] e, f, g, zwire;
wire gEQz, gLTz, gGTz;
DIV #(64) div1(a, b, e);
DIV #(64) div2(c, d, f);
MOD #(64) mod1(a, b, g);
COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
MUX2x1 #(64) mux1(f, e, gEQz, zwire);
REG #(64) reg1(zwire, Clk, Rst, z);
endmodule | module CIRCUIT7(a, b, c, d, zero, Clk, Rst, z); |
input Clk, Rst;
input [63:0] a, b, c, d, zero;
output [63:0] z;
wire [63:0] e, f, g, zwire;
wire gEQz, gLTz, gGTz;
DIV #(64) div1(a, b, e);
DIV #(64) div2(c, d, f);
MOD #(64) mod1(a, b, g);
COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
MUX2x1 #(64) mux1(f, e, gEQz, zwire);
REG #(64) reg1(zwire, Clk, Rst, z);
endmodule | 0 |
3,056 | data/full_repos/permissive/102515926/Modules/CIRCUIT8.v | 102,515,926 | CIRCUIT8.v | v | 27 | 83 | [] | [] | [] | [(9, 27)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:19: Cannot find file containing module: 'DEC'\n DEC #(64) dec1(a, e);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC.sv\n DEC\n DEC.v\n DEC.sv\n obj_dir/DEC\n obj_dir/DEC.v\n obj_dir/DEC.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:20: Cannot find file containing module: 'INC'\n INC #(64) inc1(c, f);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:21: Cannot find file containing module: 'MOD'\n MOD #(64) mod1(a, c, g);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:22: Cannot find file containing module: 'COMP'\n COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:23: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(64) mux1(f, e, gEQz, zwire);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:24: Cannot find file containing module: 'REG'\n REG #(64) reg1(zwire, Clk, Rst, z);\n ^~~\n%Error: Exiting due to 6 error(s)\n" | 646 | module | module CIRCUIT8(a, b, c, zero, Clk, Rst, z);
input Clk, Rst;
input [63:0] a, b, c, zero;
output [63:0] z;
wire [63:0] e, f, g, zwire;
wire gEQz, gLTz, gGTz;
DEC #(64) dec1(a, e);
INC #(64) inc1(c, f);
MOD #(64) mod1(a, c, g);
COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
MUX2x1 #(64) mux1(f, e, gEQz, zwire);
REG #(64) reg1(zwire, Clk, Rst, z);
endmodule | module CIRCUIT8(a, b, c, zero, Clk, Rst, z); |
input Clk, Rst;
input [63:0] a, b, c, zero;
output [63:0] z;
wire [63:0] e, f, g, zwire;
wire gEQz, gLTz, gGTz;
DEC #(64) dec1(a, e);
INC #(64) inc1(c, f);
MOD #(64) mod1(a, c, g);
COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
MUX2x1 #(64) mux1(f, e, gEQz, zwire);
REG #(64) reg1(zwire, Clk, Rst, z);
endmodule | 0 |
3,057 | data/full_repos/permissive/102515926/Modules/COMP.v | 102,515,926 | COMP.v | v | 33 | 83 | [] | [] | [] | [(10, 33)] | null | data/verilator_xmls/4e8197ed-b720-48f1-85d1-70f9e63aeeb2.xml | null | 647 | module | module COMP(a, b, gt, lt, eq);
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
output reg gt, lt, eq;
initial begin
gt <= 0; lt <= 0; eq <= 0;
end
always @(*) begin
gt <= 0; lt <= 0; eq <= 0;
if($signed(a) > $signed(b))
gt <= 1;
else if($signed(a) < $signed(b))
lt <= 1;
else
eq <= 1;
end
endmodule | module COMP(a, b, gt, lt, eq); |
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
output reg gt, lt, eq;
initial begin
gt <= 0; lt <= 0; eq <= 0;
end
always @(*) begin
gt <= 0; lt <= 0; eq <= 0;
if($signed(a) > $signed(b))
gt <= 1;
else if($signed(a) < $signed(b))
lt <= 1;
else
eq <= 1;
end
endmodule | 0 |
3,058 | data/full_repos/permissive/102515926/Modules/DIV.v | 102,515,926 | DIV.v | v | 23 | 83 | [] | [] | [] | [(10, 23)] | null | data/verilator_xmls/beeae784-af35-417c-94a6-cb55e97d80a6.xml | null | 649 | module | module DIV(a, b, quot);
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a, b;
output reg [DATAWIDTH - 1:0] quot;
always @(*) begin
quot <= a / b;
end
endmodule | module DIV(a, b, quot); |
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a, b;
output reg [DATAWIDTH - 1:0] quot;
always @(*) begin
quot <= a / b;
end
endmodule | 0 |
3,059 | data/full_repos/permissive/102515926/Modules/INC.v | 102,515,926 | INC.v | v | 23 | 83 | [] | [] | [] | [(10, 23)] | null | data/verilator_xmls/6666e945-9c56-457c-9e8e-a6782ea21387.xml | null | 650 | module | module INC(a, d);
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
d <= a + 1;
end
endmodule | module INC(a, d); |
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
d <= a + 1;
end
endmodule | 0 |
3,060 | data/full_repos/permissive/102515926/Modules/MAIN.v | 102,515,926 | MAIN.v | v | 52 | 170 | [] | [] | [] | [(23, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:39: Cannot find file containing module: 'ADD'\n ADD #(DATAWIDTH) ADD_1(a, b, a1);\n ^~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n ADD\n ADD.v\n ADD.sv\n obj_dir/ADD\n obj_dir/ADD.v\n obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:40: Cannot find file containing module: 'COMP'\n COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);\n ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:41: Cannot find file containing module: 'DEC'\n DEC #(DATAWIDTH) DEC_1(e, a3);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:42: Cannot find file containing module: 'DIV'\n DIV #(DATAWIDTH) DIV_1(f, g, a4);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:43: Cannot find file containing module: 'INC'\n INC #(DATAWIDTH) INC_1(h, a5);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:44: Cannot find file containing module: 'MOD'\n MOD #(DATAWIDTH) MOD_1(i, j, a6);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:45: Cannot find file containing module: 'MUL'\n MUL #(DATAWIDTH) MUL_1(k, l, a7);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:46: Cannot find file containing module: 'MUX2x1'\n MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);\n ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:47: Cannot find file containing module: 'REG'\n REG #(DATAWIDTH) REG_1(o, clk, rst, a9);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:48: Cannot find file containing module: 'SHL'\n SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:49: Cannot find file containing module: 'SHR'\n SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);\n ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:50: Cannot find file containing module: 'SUB'\n SUB #(DATAWIDTH) SUB_1(r, s, a12);\n ^~~\n%Error: Exiting due to 12 error(s)\n" | 651 | module | module MAIN(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a, b; output [DATAWIDTH - 1:0] a1;
input [DATAWIDTH - 1:0] c, d; output a2_gt, a2_lt, a2_eq;
input [DATAWIDTH - 1:0] e; output [DATAWIDTH - 1:0] a3;
input [DATAWIDTH - 1:0] f, g; output [DATAWIDTH - 1:0] a4;
input [DATAWIDTH - 1:0] h; output [DATAWIDTH - 1:0] a5;
input [DATAWIDTH - 1:0] i, j; output [DATAWIDTH - 1:0] a6;
input [DATAWIDTH - 1:0] k, l; output [DATAWIDTH - 1:0] a7;
input [DATAWIDTH - 1:0] m, n; input a8_sel; output [DATAWIDTH - 1:0] a8;
input [DATAWIDTH - 1:0] o; input clk, rst; output [DATAWIDTH - 1:0] a9;
input [DATAWIDTH - 1:0] p; input [$clog2(DATAWIDTH) - 1:0] p_amt; output [DATAWIDTH - 1:0] a10;
input [DATAWIDTH - 1:0] q; input [$clog2(DATAWIDTH) - 1:0] q_amt; output [DATAWIDTH - 1:0] a11;
input [DATAWIDTH - 1:0] r, s; output [DATAWIDTH - 1:0] a12;
ADD #(DATAWIDTH) ADD_1(a, b, a1);
COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);
DEC #(DATAWIDTH) DEC_1(e, a3);
DIV #(DATAWIDTH) DIV_1(f, g, a4);
INC #(DATAWIDTH) INC_1(h, a5);
MOD #(DATAWIDTH) MOD_1(i, j, a6);
MUL #(DATAWIDTH) MUL_1(k, l, a7);
MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);
REG #(DATAWIDTH) REG_1(o, clk, rst, a9);
SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);
SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);
SUB #(DATAWIDTH) SUB_1(r, s, a12);
endmodule | module MAIN(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12); |
parameter DATAWIDTH = 2;
input [DATAWIDTH - 1:0] a, b; output [DATAWIDTH - 1:0] a1;
input [DATAWIDTH - 1:0] c, d; output a2_gt, a2_lt, a2_eq;
input [DATAWIDTH - 1:0] e; output [DATAWIDTH - 1:0] a3;
input [DATAWIDTH - 1:0] f, g; output [DATAWIDTH - 1:0] a4;
input [DATAWIDTH - 1:0] h; output [DATAWIDTH - 1:0] a5;
input [DATAWIDTH - 1:0] i, j; output [DATAWIDTH - 1:0] a6;
input [DATAWIDTH - 1:0] k, l; output [DATAWIDTH - 1:0] a7;
input [DATAWIDTH - 1:0] m, n; input a8_sel; output [DATAWIDTH - 1:0] a8;
input [DATAWIDTH - 1:0] o; input clk, rst; output [DATAWIDTH - 1:0] a9;
input [DATAWIDTH - 1:0] p; input [$clog2(DATAWIDTH) - 1:0] p_amt; output [DATAWIDTH - 1:0] a10;
input [DATAWIDTH - 1:0] q; input [$clog2(DATAWIDTH) - 1:0] q_amt; output [DATAWIDTH - 1:0] a11;
input [DATAWIDTH - 1:0] r, s; output [DATAWIDTH - 1:0] a12;
ADD #(DATAWIDTH) ADD_1(a, b, a1);
COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);
DEC #(DATAWIDTH) DEC_1(e, a3);
DIV #(DATAWIDTH) DIV_1(f, g, a4);
INC #(DATAWIDTH) INC_1(h, a5);
MOD #(DATAWIDTH) MOD_1(i, j, a6);
MUL #(DATAWIDTH) MUL_1(k, l, a7);
MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);
REG #(DATAWIDTH) REG_1(o, clk, rst, a9);
SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);
SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);
SUB #(DATAWIDTH) SUB_1(r, s, a12);
endmodule | 0 |
3,061 | data/full_repos/permissive/102515926/Modules/MAIN_TB.v | 102,515,926 | MAIN_TB.v | v | 66 | 187 | [] | [] | [] | [(23, 65)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n #20 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n #15 o <= 3; rst <= 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n #15 o <= 3; rst <= 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n #15 o <= 2; rst <= 0; \n ^\n%Error: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:39: Cannot find file containing module: \'MAIN\'\n MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN.v\n data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN.sv\n MAIN\n MAIN.v\n MAIN.sv\n obj_dir/MAIN\n obj_dir/MAIN.v\n obj_dir/MAIN.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 652 | module | module MAIN_TB();
parameter DATAWIDTH = 8;
reg [DATAWIDTH - 1:0] a, b; wire [DATAWIDTH - 1:0] a1;
reg [DATAWIDTH - 1:0] c, d; wire a2_gt, a2_lt, a2_eq;
reg [DATAWIDTH - 1:0] e; wire [DATAWIDTH - 1:0] a3;
reg [DATAWIDTH - 1:0] f, g; wire [DATAWIDTH - 1:0] a4;
reg [DATAWIDTH - 1:0] h; wire [DATAWIDTH - 1:0] a5;
reg [DATAWIDTH - 1:0] i, j; wire [DATAWIDTH - 1:0] a6;
reg [DATAWIDTH - 1:0] k, l; wire [DATAWIDTH - 1:0] a7;
reg [DATAWIDTH - 1:0] m, n; reg a8_sel; wire [DATAWIDTH - 1:0] a8;
reg [DATAWIDTH - 1:0] o; reg clk, rst; wire [DATAWIDTH - 1:0] a9;
reg [DATAWIDTH - 1:0] p; reg [$clog2(DATAWIDTH) - 1:0] p_amt; wire [DATAWIDTH - 1:0] a10;
reg [DATAWIDTH - 1:0] q; reg [$clog2(DATAWIDTH) - 1:0] q_amt; wire [DATAWIDTH - 1:0] a11;
reg [DATAWIDTH - 1:0] r, s; wire [DATAWIDTH - 1:0] a12;
MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);
always
#10 clk <= ~clk;
initial begin
clk <= 0;
rst <= 1;
#20 rst <= 0;
#10;
a <= 1; b <= 2;
c <= 4; d <= 3;
e <= 4;
f <= 6; g <= 3;
h <= 5;
i <= 7; j <= 3;
k <= 4; l <= 2;
m <= 2; n <= 3; a8_sel <= 1;
o <= 4;
#15 o <= 3; rst <= 1;
#15 o <= 3; rst <= 1;
#15 o <= 2; rst <= 0;
p <= 1; p_amt <= 1;
q <= 8; q_amt <= 2;
r <= 5; s <= 4;
end
endmodule | module MAIN_TB(); |
parameter DATAWIDTH = 8;
reg [DATAWIDTH - 1:0] a, b; wire [DATAWIDTH - 1:0] a1;
reg [DATAWIDTH - 1:0] c, d; wire a2_gt, a2_lt, a2_eq;
reg [DATAWIDTH - 1:0] e; wire [DATAWIDTH - 1:0] a3;
reg [DATAWIDTH - 1:0] f, g; wire [DATAWIDTH - 1:0] a4;
reg [DATAWIDTH - 1:0] h; wire [DATAWIDTH - 1:0] a5;
reg [DATAWIDTH - 1:0] i, j; wire [DATAWIDTH - 1:0] a6;
reg [DATAWIDTH - 1:0] k, l; wire [DATAWIDTH - 1:0] a7;
reg [DATAWIDTH - 1:0] m, n; reg a8_sel; wire [DATAWIDTH - 1:0] a8;
reg [DATAWIDTH - 1:0] o; reg clk, rst; wire [DATAWIDTH - 1:0] a9;
reg [DATAWIDTH - 1:0] p; reg [$clog2(DATAWIDTH) - 1:0] p_amt; wire [DATAWIDTH - 1:0] a10;
reg [DATAWIDTH - 1:0] q; reg [$clog2(DATAWIDTH) - 1:0] q_amt; wire [DATAWIDTH - 1:0] a11;
reg [DATAWIDTH - 1:0] r, s; wire [DATAWIDTH - 1:0] a12;
MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);
always
#10 clk <= ~clk;
initial begin
clk <= 0;
rst <= 1;
#20 rst <= 0;
#10;
a <= 1; b <= 2;
c <= 4; d <= 3;
e <= 4;
f <= 6; g <= 3;
h <= 5;
i <= 7; j <= 3;
k <= 4; l <= 2;
m <= 2; n <= 3; a8_sel <= 1;
o <= 4;
#15 o <= 3; rst <= 1;
#15 o <= 3; rst <= 1;
#15 o <= 2; rst <= 0;
p <= 1; p_amt <= 1;
q <= 8; q_amt <= 2;
r <= 5; s <= 4;
end
endmodule | 0 |
3,062 | data/full_repos/permissive/102515926/Modules/MUX2x1.v | 102,515,926 | MUX2x1.v | v | 28 | 83 | [] | [] | [] | [(10, 28)] | null | data/verilator_xmls/3ca89e6d-3277-42f6-8437-ef5b80202d32.xml | null | 655 | module | module MUX2x1(a, b, sel, d);
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
input sel;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
if(sel == 0)
d <= a;
else
d <= b;
end
endmodule | module MUX2x1(a, b, sel, d); |
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
input sel;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
if(sel == 0)
d <= a;
else
d <= b;
end
endmodule | 0 |
3,063 | data/full_repos/permissive/102515926/Modules/REG.v | 102,515,926 | REG.v | v | 27 | 83 | [] | [] | [] | [(10, 26)] | null | data/verilator_xmls/969e3893-9fb9-44f2-8580-9d033ec24943.xml | null | 656 | module | module REG(d, Clk, Rst, q);
parameter DATAWIDTH = 8;
input Clk, Rst;
input [DATAWIDTH - 1:0] d;
output reg [DATAWIDTH - 1:0] q;
always @(posedge Clk) begin
if(Rst)
q <= 0;
else
q <= d;
end
endmodule | module REG(d, Clk, Rst, q); |
parameter DATAWIDTH = 8;
input Clk, Rst;
input [DATAWIDTH - 1:0] d;
output reg [DATAWIDTH - 1:0] q;
always @(posedge Clk) begin
if(Rst)
q <= 0;
else
q <= d;
end
endmodule | 0 |
3,064 | data/full_repos/permissive/102515926/Modules/SHR.v | 102,515,926 | SHR.v | v | 25 | 83 | [] | [] | [] | [(10, 25)] | null | data/verilator_xmls/010173d8-b660-45af-9f40-4daad532d567.xml | null | 658 | module | module SHR(a, sh_amt, d);
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a;
input [$clog2(DATAWIDTH) - 1:0] sh_amt;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
d <= a >> sh_amt;
end
endmodule | module SHR(a, sh_amt, d); |
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a;
input [$clog2(DATAWIDTH) - 1:0] sh_amt;
output reg [DATAWIDTH - 1:0] d;
always @(*) begin
d <= a >> sh_amt;
end
endmodule | 0 |
3,065 | data/full_repos/permissive/102515926/Modules/SUB.v | 102,515,926 | SUB.v | v | 23 | 83 | [] | [] | [] | [(10, 23)] | null | data/verilator_xmls/5889adc2-dc47-46d8-a87a-1132e3e5638c.xml | null | 659 | module | module SUB(a, b, diff);
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
output reg [DATAWIDTH - 1:0] diff;
always @(*) begin
diff <= a - b;
end
endmodule | module SUB(a, b, diff); |
parameter DATAWIDTH = 64;
input [DATAWIDTH - 1:0] a, b;
output reg [DATAWIDTH - 1:0] diff;
always @(*) begin
diff <= a - b;
end
endmodule | 0 |
3,066 | data/full_repos/permissive/102543783/hdl/snes_gamepad.v | 102,543,783 | snes_gamepad.v | v | 171 | 82 | [] | [] | [] | [(22, 170)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102543783/hdl/snes_gamepad.v:119: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'counter_ff\' generates 11 bits.\n : ... In instance snes_gamepad\n if(counter_ff)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102543783/hdl/snes_gamepad.v:153: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 5 bits.\n : ... In instance snes_gamepad\n btn_counter_ns = btn_counter_ff + 5\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102543783/hdl/snes_gamepad.v:135: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'counter_ff\' generates 11 bits.\n : ... In instance snes_gamepad\n if(counter_ff)\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 660 | module | module snes_gamepad
(
input wire clk,
input wire rst,
input wire rd,
output reg busy,
output wire snes_clk,
output reg snes_latch,
input wire snes_data,
output wire [15:0] buttons
);
localparam S_IDLE = 2'b00,
S_LATCH = 2'b01,
S_CLOCK = 2'b10;
localparam CLOCK_VALUE = 11'd599,
LATCH_VALUE = 11'd1199;
reg [1:0] state_ff, state_ns;
reg [10:0] counter_ff, counter_ns;
reg snes_clk_ff, snes_clk_ns;
reg [3:0] btn_counter_ff, btn_counter_ns;
reg [15:0] buttons_ff, buttons_ns;
always @(posedge clk, posedge rst)
if(rst)
begin
state_ff <= S_IDLE;
counter_ff <= 11'd0;
snes_clk_ff <= 1'b1;
btn_counter_ff <= 4'd0;
buttons_ff <= {16{1'b1}};
end
else
begin
state_ff <= state_ns;
counter_ff <= counter_ns;
snes_clk_ff <= snes_clk_ns;
btn_counter_ff <= btn_counter_ns;
buttons_ff <= buttons_ns;
end
always @*
begin
state_ns = state_ff;
counter_ns = counter_ff;
busy = 1'b0;
snes_latch = 1'b0;
snes_clk_ns = snes_clk_ff;
btn_counter_ns = btn_counter_ff;
buttons_ns = buttons_ff;
case(state_ff)
S_IDLE:
begin
if(rd)
begin
counter_ns = LATCH_VALUE;
btn_counter_ns = 4'd0;
buttons_ns = {16{1'b1}};
state_ns = S_LATCH;
end
end
S_LATCH:
begin
busy = 1'b1;
snes_latch = 1'b1;
if(counter_ff)
begin
counter_ns = counter_ff - 11'd1;
end
else
begin
counter_ns = CLOCK_VALUE;
state_ns = S_CLOCK;
end
end
S_CLOCK:
begin
busy = 1'b1;
if(counter_ff)
begin
counter_ns = counter_ff - 11'd1;
end
else
begin
counter_ns = CLOCK_VALUE;
snes_clk_ns = ~snes_clk_ff;
if(snes_clk_ff)
buttons_ns = {snes_data, buttons_ff[15:1]};
else
if(btn_counter_ff == 4'd15)
state_ns = S_IDLE;
else
btn_counter_ns = btn_counter_ff + 5'd1;
end
end
default:
begin
state_ns = S_IDLE;
end
endcase
end
assign snes_clk = snes_clk_ff;
assign buttons = ~buttons_ff;
endmodule | module snes_gamepad
(
input wire clk,
input wire rst,
input wire rd,
output reg busy,
output wire snes_clk,
output reg snes_latch,
input wire snes_data,
output wire [15:0] buttons
); |
localparam S_IDLE = 2'b00,
S_LATCH = 2'b01,
S_CLOCK = 2'b10;
localparam CLOCK_VALUE = 11'd599,
LATCH_VALUE = 11'd1199;
reg [1:0] state_ff, state_ns;
reg [10:0] counter_ff, counter_ns;
reg snes_clk_ff, snes_clk_ns;
reg [3:0] btn_counter_ff, btn_counter_ns;
reg [15:0] buttons_ff, buttons_ns;
always @(posedge clk, posedge rst)
if(rst)
begin
state_ff <= S_IDLE;
counter_ff <= 11'd0;
snes_clk_ff <= 1'b1;
btn_counter_ff <= 4'd0;
buttons_ff <= {16{1'b1}};
end
else
begin
state_ff <= state_ns;
counter_ff <= counter_ns;
snes_clk_ff <= snes_clk_ns;
btn_counter_ff <= btn_counter_ns;
buttons_ff <= buttons_ns;
end
always @*
begin
state_ns = state_ff;
counter_ns = counter_ff;
busy = 1'b0;
snes_latch = 1'b0;
snes_clk_ns = snes_clk_ff;
btn_counter_ns = btn_counter_ff;
buttons_ns = buttons_ff;
case(state_ff)
S_IDLE:
begin
if(rd)
begin
counter_ns = LATCH_VALUE;
btn_counter_ns = 4'd0;
buttons_ns = {16{1'b1}};
state_ns = S_LATCH;
end
end
S_LATCH:
begin
busy = 1'b1;
snes_latch = 1'b1;
if(counter_ff)
begin
counter_ns = counter_ff - 11'd1;
end
else
begin
counter_ns = CLOCK_VALUE;
state_ns = S_CLOCK;
end
end
S_CLOCK:
begin
busy = 1'b1;
if(counter_ff)
begin
counter_ns = counter_ff - 11'd1;
end
else
begin
counter_ns = CLOCK_VALUE;
snes_clk_ns = ~snes_clk_ff;
if(snes_clk_ff)
buttons_ns = {snes_data, buttons_ff[15:1]};
else
if(btn_counter_ff == 4'd15)
state_ns = S_IDLE;
else
btn_counter_ns = btn_counter_ff + 5'd1;
end
end
default:
begin
state_ns = S_IDLE;
end
endcase
end
assign snes_clk = snes_clk_ff;
assign buttons = ~buttons_ff;
endmodule | 2 |
3,067 | data/full_repos/permissive/102543783/hdl/top.v | 102,543,783 | top.v | v | 113 | 81 | [] | [] | [] | [(20, 112)] | null | null | 1: b'%Error: data/full_repos/permissive/102543783/hdl/top.v:65: Cannot find file containing module: \'snes_gamepad\'\n snes_gamepad gamepad\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102543783/hdl,data/full_repos/permissive/102543783/snes_gamepad\n data/full_repos/permissive/102543783/hdl,data/full_repos/permissive/102543783/snes_gamepad.v\n data/full_repos/permissive/102543783/hdl,data/full_repos/permissive/102543783/snes_gamepad.sv\n snes_gamepad\n snes_gamepad.v\n snes_gamepad.sv\n obj_dir/snes_gamepad\n obj_dir/snes_gamepad.v\n obj_dir/snes_gamepad.sv\n%Warning-WIDTH: data/full_repos/permissive/102543783/hdl/top.v:98: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'rd_counter_ff\' generates 21 bits.\n : ... In instance top\n assign rd = (rd_counter_ff) ? 1\'b0 : 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102543783/hdl/top.v:101: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'rd_counter_ff\' generates 21 bits.\n : ... In instance top\n assign rd_counter_ns = (rd_counter_ff) ? rd_counter_ff - 21\'d1\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 661 | module | module top
(
input clk,
input rst_n,
output snes_clk,
output snes_latch,
input snes_data,
output [15:0] led
);
localparam RD_COUNTER_MAX = 21'd1666666;
wire rst;
wire rd, busy;
wire [15:0] buttons;
reg [20:0] rd_counter_ff;
wire [20:0] rd_counter_ns;
reg busy_ff;
wire negedge_busy;
reg [15:0] led_ff;
wire [15:0] led_ns;
assign rst = ~rst_n;
assign negedge_busy = busy_ff & ~busy;
snes_gamepad gamepad
(
.clk(clk),
.rst(rst),
.rd(rd),
.busy(busy),
.snes_clk(snes_clk),
.snes_latch(snes_latch),
.snes_data(snes_data),
.buttons(buttons)
);
always @(posedge clk, posedge rst)
if(rst)
begin
rd_counter_ff <= RD_COUNTER_MAX;
busy_ff <= 1'b0;
led_ff <= 16'd0;
end
else
begin
rd_counter_ff <= rd_counter_ns;
busy_ff <= busy;
led_ff <= led_ns;
end
assign rd = (rd_counter_ff) ? 1'b0 : 1'b1;
assign rd_counter_ns = (rd_counter_ff) ? rd_counter_ff - 21'd1
: RD_COUNTER_MAX;
assign led_ns = (negedge_busy) ? buttons : led_ff;
assign led = led_ff;
endmodule | module top
(
input clk,
input rst_n,
output snes_clk,
output snes_latch,
input snes_data,
output [15:0] led
); |
localparam RD_COUNTER_MAX = 21'd1666666;
wire rst;
wire rd, busy;
wire [15:0] buttons;
reg [20:0] rd_counter_ff;
wire [20:0] rd_counter_ns;
reg busy_ff;
wire negedge_busy;
reg [15:0] led_ff;
wire [15:0] led_ns;
assign rst = ~rst_n;
assign negedge_busy = busy_ff & ~busy;
snes_gamepad gamepad
(
.clk(clk),
.rst(rst),
.rd(rd),
.busy(busy),
.snes_clk(snes_clk),
.snes_latch(snes_latch),
.snes_data(snes_data),
.buttons(buttons)
);
always @(posedge clk, posedge rst)
if(rst)
begin
rd_counter_ff <= RD_COUNTER_MAX;
busy_ff <= 1'b0;
led_ff <= 16'd0;
end
else
begin
rd_counter_ff <= rd_counter_ns;
busy_ff <= busy;
led_ff <= led_ns;
end
assign rd = (rd_counter_ff) ? 1'b0 : 1'b1;
assign rd_counter_ns = (rd_counter_ff) ? rd_counter_ff - 21'd1
: RD_COUNTER_MAX;
assign led_ns = (negedge_busy) ? buttons : led_ff;
assign led = led_ff;
endmodule | 2 |
3,072 | data/full_repos/permissive/102564818/Transmitter.v | 102,564,818 | Transmitter.v | v | 97 | 146 | [] | [] | [] | [(6, 97)] | null | null | 1: b"%Error: data/full_repos/permissive/102564818/Transmitter.v:22: Cannot find file containing module: 'BaudGeneratorTx'\n BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx.v\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx.sv\n BaudGeneratorTx\n BaudGeneratorTx.v\n BaudGeneratorTx.sv\n obj_dir/BaudGeneratorTx\n obj_dir/BaudGeneratorTx.v\n obj_dir/BaudGeneratorTx.sv\n%Error: Exiting due to 1 error(s)\n" | 666 | module | module Transmitter(CLK, RST, BaudRate, ParityMode, StopBits, TxBegin, TxData, TxBusy, Tx);
input CLK;
input RST;
input[1:0] BaudRate;
input[1:0] ParityMode;
input StopBits;
input TxBegin;
input[7:0] TxData;
output reg TxBusy;
output reg Tx;
wire BaudPulse;
reg[3:0] State;
reg TxBeginPending;
reg[7:0] TxDataS;
BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));
always @ (posedge CLK) begin
if(TxBegin && ~TxBusy) TxDataS <= TxData;
else TxDataS <= TxDataS;
end
always @ (posedge CLK or posedge RST) begin
if(RST) begin
State <= 4'b0000;
TxBeginPending <= 1'b0;
end else begin
if(TxBegin) TxBeginPending <= 1'b1;
case(State)
4'b0000: if(TxBeginPending & BaudPulse) begin State <= 4'b0001; TxBeginPending <= 1'b0; end
4'b0001: if(BaudPulse) State <= 4'b0010;
4'b0010: if(BaudPulse) State <= 4'b0011;
4'b0011: if(BaudPulse) State <= 4'b0100;
4'b0100: if(BaudPulse) State <= 4'b0101;
4'b0101: if(BaudPulse) State <= 4'b0110;
4'b0110: if(BaudPulse) State <= 4'b0111;
4'b0111: if(BaudPulse) State <= 4'b1000;
4'b1000: if(BaudPulse) State <= 4'b1001;
4'b1001: begin
if(BaudPulse) begin
if(ParityMode[1] == 1'b1) State <= 4'b1010;
else State <= 4'b1100;
end
end
4'b1010: begin
if(BaudPulse) begin
if(StopBits == 1'b0) State <= 4'b0000;
if(StopBits == 1'b1) State <= 4'b1011;
end
end
4'b1011: if(BaudPulse) State <= 4'b0000;
4'b1100: if(BaudPulse) State <= 4'b1010;
default: State <= 4'b0000;
endcase
end
end
always @ (State or TxDataS or ParityMode) begin
case(State)
4'b0001: Tx <= 1'b0;
4'b0010: Tx <= TxDataS[0];
4'b0011: Tx <= TxDataS[1];
4'b0100: Tx <= TxDataS[2];
4'b0101: Tx <= TxDataS[3];
4'b0110: Tx <= TxDataS[4];
4'b0111: Tx <= TxDataS[5];
4'b1000: Tx <= TxDataS[6];
4'b1001: Tx <= TxDataS[7];
4'b1010: Tx <= 1'b1;
4'b1011: Tx <= 1'b1;
4'b1100: begin
if(ParityMode[0] == 1'b0) begin
Tx <= (TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
end else begin
Tx <= ~(TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
end
end
default: Tx <= 1'b1;
endcase
end
always @ (State) begin
case(State)
4'b0000: TxBusy <= 1'b0;
4'b1101: TxBusy <= 1'b0;
4'b1110: TxBusy <= 1'b0;
4'b1111: TxBusy <= 1'b0;
default: TxBusy <= 1'b1;
endcase
end
endmodule | module Transmitter(CLK, RST, BaudRate, ParityMode, StopBits, TxBegin, TxData, TxBusy, Tx); |
input CLK;
input RST;
input[1:0] BaudRate;
input[1:0] ParityMode;
input StopBits;
input TxBegin;
input[7:0] TxData;
output reg TxBusy;
output reg Tx;
wire BaudPulse;
reg[3:0] State;
reg TxBeginPending;
reg[7:0] TxDataS;
BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));
always @ (posedge CLK) begin
if(TxBegin && ~TxBusy) TxDataS <= TxData;
else TxDataS <= TxDataS;
end
always @ (posedge CLK or posedge RST) begin
if(RST) begin
State <= 4'b0000;
TxBeginPending <= 1'b0;
end else begin
if(TxBegin) TxBeginPending <= 1'b1;
case(State)
4'b0000: if(TxBeginPending & BaudPulse) begin State <= 4'b0001; TxBeginPending <= 1'b0; end
4'b0001: if(BaudPulse) State <= 4'b0010;
4'b0010: if(BaudPulse) State <= 4'b0011;
4'b0011: if(BaudPulse) State <= 4'b0100;
4'b0100: if(BaudPulse) State <= 4'b0101;
4'b0101: if(BaudPulse) State <= 4'b0110;
4'b0110: if(BaudPulse) State <= 4'b0111;
4'b0111: if(BaudPulse) State <= 4'b1000;
4'b1000: if(BaudPulse) State <= 4'b1001;
4'b1001: begin
if(BaudPulse) begin
if(ParityMode[1] == 1'b1) State <= 4'b1010;
else State <= 4'b1100;
end
end
4'b1010: begin
if(BaudPulse) begin
if(StopBits == 1'b0) State <= 4'b0000;
if(StopBits == 1'b1) State <= 4'b1011;
end
end
4'b1011: if(BaudPulse) State <= 4'b0000;
4'b1100: if(BaudPulse) State <= 4'b1010;
default: State <= 4'b0000;
endcase
end
end
always @ (State or TxDataS or ParityMode) begin
case(State)
4'b0001: Tx <= 1'b0;
4'b0010: Tx <= TxDataS[0];
4'b0011: Tx <= TxDataS[1];
4'b0100: Tx <= TxDataS[2];
4'b0101: Tx <= TxDataS[3];
4'b0110: Tx <= TxDataS[4];
4'b0111: Tx <= TxDataS[5];
4'b1000: Tx <= TxDataS[6];
4'b1001: Tx <= TxDataS[7];
4'b1010: Tx <= 1'b1;
4'b1011: Tx <= 1'b1;
4'b1100: begin
if(ParityMode[0] == 1'b0) begin
Tx <= (TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
end else begin
Tx <= ~(TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
end
end
default: Tx <= 1'b1;
endcase
end
always @ (State) begin
case(State)
4'b0000: TxBusy <= 1'b0;
4'b1101: TxBusy <= 1'b0;
4'b1110: TxBusy <= 1'b0;
4'b1111: TxBusy <= 1'b0;
default: TxBusy <= 1'b1;
endcase
end
endmodule | 2 |
3,073 | data/full_repos/permissive/102564818/UART.v | 102,564,818 | UART.v | v | 42 | 70 | [] | [] | [] | [(7, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/102564818/UART.v:22: Cannot find file containing module: 'Transmitter'\n Transmitter T1( .CLK(CLK), \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter.v\n data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter.sv\n Transmitter\n Transmitter.v\n Transmitter.sv\n obj_dir/Transmitter\n obj_dir/Transmitter.v\n obj_dir/Transmitter.sv\n%Error: data/full_repos/permissive/102564818/UART.v:32: Cannot find file containing module: 'Receiver'\n Receiver R1( .CLK(CLK),\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 667 | module | module UART(CLK, RST, BaudRate, ParityMode, StopBits, Tx, Rx, Error);
input CLK;
input RST;
input[1:0] BaudRate;
input[1:0] ParityMode;
input StopBits;
output Tx;
input Rx;
output Error;
wire TxBusy;
wire[7:0] RxData;
wire RxDataReady;
Transmitter T1( .CLK(CLK),
.RST(RST),
.BaudRate(BaudRate),
.ParityMode(ParityMode),
.StopBits(StopBits),
.TxBegin(RxDataReady),
.TxData(RxData),
.TxBusy(TxBusy),
.Tx(Tx));
Receiver R1( .CLK(CLK),
.RST(RST),
.BaudRate(BaudRate),
.ParityMode(ParityMode),
.StopBits(StopBits),
.Rx(Rx),
.RxData(RxData),
.RxDataReady(RxDataReady),
.Error(Error));
endmodule | module UART(CLK, RST, BaudRate, ParityMode, StopBits, Tx, Rx, Error); |
input CLK;
input RST;
input[1:0] BaudRate;
input[1:0] ParityMode;
input StopBits;
output Tx;
input Rx;
output Error;
wire TxBusy;
wire[7:0] RxData;
wire RxDataReady;
Transmitter T1( .CLK(CLK),
.RST(RST),
.BaudRate(BaudRate),
.ParityMode(ParityMode),
.StopBits(StopBits),
.TxBegin(RxDataReady),
.TxData(RxData),
.TxBusy(TxBusy),
.Tx(Tx));
Receiver R1( .CLK(CLK),
.RST(RST),
.BaudRate(BaudRate),
.ParityMode(ParityMode),
.StopBits(StopBits),
.Rx(Rx),
.RxData(RxData),
.RxDataReady(RxDataReady),
.Error(Error));
endmodule | 2 |
3,074 | data/full_repos/permissive/102821975/Processor/ALU.v | 102,821,975 | ALU.v | v | 138 | 40 | [] | [] | [] | [(3, 138)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/ALU.v:126: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance ALU\n if (A>B) ALUOut=2\'d1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/ALU.v:127: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance ALU\n else if(A==B) ALUOut=2\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/ALU.v:128: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance ALU\n else ALUOut=2\'d2;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 820 | module | module ALU(A, B, ALUOp , ALUOut, Zero);
output reg [31:0] ALUOut;
output reg [0:0] Zero;
input [31:0] A, B;
input [4:0] ALUOp;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
parameter on = 1'd1;
parameter off = 1'd0;
initial begin
ALUOut=32'd0;
Zero=1'd0;
end
always @ (A or B or ALUOp) begin
case (ALUOp)
ADD:
begin
ALUOut = A+B;
Zero=off;
end
SUB:
begin
ALUOut = A-B;
Zero=off;
end
ADDI:
begin
ALUOut = A+B;
Zero=off;
end
SUBI:
begin
ALUOut = A-B;
Zero=off;
end
MLT:
begin
ALUOut = A*B;
Zero=off;
end
MLTI:
begin
ALUOut = A*B;
Zero=off;
end
AND:
begin
ALUOut = A&B;
Zero=off;
end
OR:
begin
ALUOut = A|B;
Zero=off;
end
ANDI:
begin
ALUOut = A&B;
Zero=off;
end
ORI:
begin
ALUOut = A|B;
Zero=off;
end
SLR:
begin
ALUOut = A>>B;
Zero=off;
end
SLL:
begin
ALUOut = A<<B;
Zero=off;
end
LDR:
begin
ALUOut = A+B;
Zero=off;
end
STR:
begin
ALUOut = A+B;
Zero=off;
end
BNE:
begin
ALUOut = 32'd0;
if(A==B) Zero=on;
else Zero=off;
end
BEQ:
begin
ALUOut = 32'd0;
if (A==B) Zero=on;
else Zero=off;
end
CMP:
begin
if (A>B) ALUOut=2'd1;
else if(A==B) ALUOut=2'd0;
else ALUOut=2'd2;
Zero=off;
end
default:
begin
ALUOut = 32'd0;
Zero=off;
end
endcase
end
endmodule | module ALU(A, B, ALUOp , ALUOut, Zero); |
output reg [31:0] ALUOut;
output reg [0:0] Zero;
input [31:0] A, B;
input [4:0] ALUOp;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
parameter on = 1'd1;
parameter off = 1'd0;
initial begin
ALUOut=32'd0;
Zero=1'd0;
end
always @ (A or B or ALUOp) begin
case (ALUOp)
ADD:
begin
ALUOut = A+B;
Zero=off;
end
SUB:
begin
ALUOut = A-B;
Zero=off;
end
ADDI:
begin
ALUOut = A+B;
Zero=off;
end
SUBI:
begin
ALUOut = A-B;
Zero=off;
end
MLT:
begin
ALUOut = A*B;
Zero=off;
end
MLTI:
begin
ALUOut = A*B;
Zero=off;
end
AND:
begin
ALUOut = A&B;
Zero=off;
end
OR:
begin
ALUOut = A|B;
Zero=off;
end
ANDI:
begin
ALUOut = A&B;
Zero=off;
end
ORI:
begin
ALUOut = A|B;
Zero=off;
end
SLR:
begin
ALUOut = A>>B;
Zero=off;
end
SLL:
begin
ALUOut = A<<B;
Zero=off;
end
LDR:
begin
ALUOut = A+B;
Zero=off;
end
STR:
begin
ALUOut = A+B;
Zero=off;
end
BNE:
begin
ALUOut = 32'd0;
if(A==B) Zero=on;
else Zero=off;
end
BEQ:
begin
ALUOut = 32'd0;
if (A==B) Zero=on;
else Zero=off;
end
CMP:
begin
if (A>B) ALUOut=2'd1;
else if(A==B) ALUOut=2'd0;
else ALUOut=2'd2;
Zero=off;
end
default:
begin
ALUOut = 32'd0;
Zero=off;
end
endcase
end
endmodule | 1 |
3,075 | data/full_repos/permissive/102821975/Processor/ControlUnit.v | 102,821,975 | ControlUnit.v | v | 228 | 130 | [] | [] | [] | [(3, 228)] | null | data/verilator_xmls/eb76bcb3-ed1e-4de5-95e0-edb363459d65.xml | null | 821 | module | module ControlUnit (clk,OPCODE,BOpCode,Zero,BSelector,MemRD,MemWD,RegWrite,RegSelector,PCSelect,Enable1,Enable2,Enable3,Enable4);
input wire clk;
input [4:0] OPCODE;
input [0:0] Zero;
input [4:0] BOpCode;
output reg[0:0] BSelector;
output reg[0:0] MemRD;
output reg[0:0] MemWD;
output reg[0:0] RegWrite;
output reg[1:0] RegSelector;
output reg[0:0] PCSelect;
output reg[0:0] Enable1;
output reg[0:0] Enable2;
output reg[0:0] Enable3;
output reg[0:0] Enable4;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
initial begin
BSelector = 1'd0;
PCSelect= 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
Enable1 = 1'd1;
Enable2 = 1'd1;
Enable3 = 1'd1;
Enable4 = 1'd1;
end
always @ (posedge clk) begin
case(OPCODE)
ADD:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
SUB:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd0 ;
end
ADDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SUBI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
MLT:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
MLTI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
AND:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
OR:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
ANDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
ORI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SLR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd1;
end
SLL:
begin
BSelector = 1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
LDR:
begin
BSelector =1'd1;
MemRD = 1'd1;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
STR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd1;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
BNE:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
BEQ:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
J:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
CMP:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD =1'd0 ;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
NOP:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
default:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
endcase
end
always @ (Zero,BOpCode) begin
if (BOpCode==BNE && !Zero) PCSelect=1'd1;
else if (BOpCode==BEQ && Zero) PCSelect=1'd1;
else PCSelect=1'd0;
end
endmodule | module ControlUnit (clk,OPCODE,BOpCode,Zero,BSelector,MemRD,MemWD,RegWrite,RegSelector,PCSelect,Enable1,Enable2,Enable3,Enable4); |
input wire clk;
input [4:0] OPCODE;
input [0:0] Zero;
input [4:0] BOpCode;
output reg[0:0] BSelector;
output reg[0:0] MemRD;
output reg[0:0] MemWD;
output reg[0:0] RegWrite;
output reg[1:0] RegSelector;
output reg[0:0] PCSelect;
output reg[0:0] Enable1;
output reg[0:0] Enable2;
output reg[0:0] Enable3;
output reg[0:0] Enable4;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
initial begin
BSelector = 1'd0;
PCSelect= 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
Enable1 = 1'd1;
Enable2 = 1'd1;
Enable3 = 1'd1;
Enable4 = 1'd1;
end
always @ (posedge clk) begin
case(OPCODE)
ADD:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
SUB:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd0 ;
end
ADDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SUBI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
MLT:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
MLTI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
AND:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
OR:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
ANDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
ORI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SLR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd1;
end
SLL:
begin
BSelector = 1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
LDR:
begin
BSelector =1'd1;
MemRD = 1'd1;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
STR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd1;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
BNE:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
BEQ:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
J:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
CMP:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD =1'd0 ;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
NOP:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
default:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
endcase
end
always @ (Zero,BOpCode) begin
if (BOpCode==BNE && !Zero) PCSelect=1'd1;
else if (BOpCode==BEQ && Zero) PCSelect=1'd1;
else PCSelect=1'd0;
end
endmodule | 1 |
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