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3,286 | data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv | 10,379,745 | hp_display.sv | sv | 94 | 69 | [] | [] | [] | null | line:58 column:26: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv:74: Cannot find include file: log2.inc\n`include "log2.inc" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.v\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.sv\n log2.inc\n log2.inc.v\n log2.inc.sv\n obj_dir/log2.inc\n obj_dir/log2.inc.v\n obj_dir/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 1,042 | module | module so_reg_left #( parameter D = 8)
( input CLK,
input UPDATE,
input SHIFT,
input [D-1:0] DATA,
output OUT,
output EMPTY );
`include "log2.inc"
localparam C = log2(D-1);
logic [D-1:0] sreg;
logic [C-1:0] cnt;
always_ff@(posedge CLK)
if (UPDATE) sreg <= DATA;
else if(SHIFT) sreg <= {sreg[D-2:0], 1'b0};
always_ff@(posedge CLK)
if (UPDATE) cnt <= (D-1);
else if(SHIFT) cnt <= cnt - 1'b1;
assign OUT = sreg[D-1];
assign EMPTY = (cnt == '0);
endmodule | module so_reg_left #( parameter D = 8)
( input CLK,
input UPDATE,
input SHIFT,
input [D-1:0] DATA,
output OUT,
output EMPTY ); |
`include "log2.inc"
localparam C = log2(D-1);
logic [D-1:0] sreg;
logic [C-1:0] cnt;
always_ff@(posedge CLK)
if (UPDATE) sreg <= DATA;
else if(SHIFT) sreg <= {sreg[D-2:0], 1'b0};
always_ff@(posedge CLK)
if (UPDATE) cnt <= (D-1);
else if(SHIFT) cnt <= cnt - 1'b1;
assign OUT = sreg[D-1];
assign EMPTY = (cnt == '0);
endmodule | 5 |
3,287 | data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv | 10,379,745 | i2c.sv | sv | 193 | 95 | [] | [] | [] | null | line:116: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:26: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) len_cnt( .CLK ( CLK ), \n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.v\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.sv\n inv_ld_counter\n inv_ld_counter.v\n inv_ld_counter.sv\n obj_dir/inv_ld_counter\n obj_dir/inv_ld_counter.v\n obj_dir/inv_ld_counter.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:32: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) wlen_cnt( .CLK ( CLK ), \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:38: Cannot find file containing module: 'ffd'\nffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:42: Cannot find file containing module: 'counter'\ncounter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:44: Cannot find file containing module: 'shift_out_reg_left'\nshift_out_reg_left #(8) sr_out( .CLK ( CLK ), \n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:53: Cannot find file containing module: 'shift_in_reg_left'\nshift_in_reg_left #(8) sr_in( .CLK ( CLK ),\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:88: Cannot find file containing module: 'ffds'\nffds #(1) scl_fd(CLK, l_scl, scl_q);\n^~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:89: Cannot find file containing module: 'ffds'\nffds #(1) sda_fd(CLK, l_sda, sda_q);\n^~~~\n%Error: Exiting due to 8 error(s)\n" | 1,043 | module | module i2c ( input CLK,
input RESET,
input START,
output BUSY,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
output RD_ADV,
output WR_ADV,
inout SDA,
inout SCL );
parameter TAU = 63;
logic ld_len, ld_wlen, adv, l_done, byte_done, read_mode, half_period;
logic l_scl, l_sda, scl_q, sda_q, l_data, l_ack, sreg_out, next_byte, adv_wlen;
logic s_idle, s_start, s_stop_lo, s_stop_hi, s_data_lo, s_data_hi, s_ack_lo, s_ack_hi;
logic shift_in, nack_hack;
assign next_byte = ( half_period & s_data_hi & byte_done & ~l_done );
assign adv_wlen = ( half_period & s_ack_hi & byte_done & ~read_mode);
assign RD_ADV = (next_byte & ~read_mode) | ld_len | ld_wlen;
inv_ld_counter #(7) len_cnt( .CLK ( CLK ),
.SET ( ld_len ),
.IN ( DATA_IN[6:0] ),
.EN ( next_byte ),
.ZERO ( l_done ) );
inv_ld_counter #(7) wlen_cnt( .CLK ( CLK ),
.SET ( ld_wlen ),
.IN ( DATA_IN[6:0] ),
.EN ( adv_wlen ),
.ZERO ( read_mode ));
ffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);
logic [5:0] time_cnt;
assign half_period = (time_cnt == TAU);
counter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);
shift_out_reg_left #(8) sr_out( .CLK ( CLK ),
.UPDATE ( half_period & (s_start | s_ack_hi) ),
.SHIFT ( half_period & s_data_hi & ~byte_done ),
.DATA ( DATA_IN ),
.OUT ( sreg_out ),
.EMPTY ( byte_done ));
assign shift_in = read_mode & half_period & s_data_hi;
assign WR_ADV = read_mode & half_period & s_ack_hi & byte_done;
shift_in_reg_left #(8) sr_in( .CLK ( CLK ),
.RESET ( half_period & (s_start | s_ack_hi) ),
.SHIFT ( shift_in ),
.IN ( SDA ),
.DATA ( DATA_OUT ));
i2c_fsm i2c_fsm( .CLK ( CLK ),
.RESET ( RESET ),
.START ( START ),
.TIME ( half_period ),
.L_DONE ( l_done ),
.W_DONE ( byte_done ),
.LD_LEN ( ld_len ),
.LD_WLEN ( ld_wlen ),
.S_DATA_LO ( s_data_lo ),
.S_DATA_HI ( s_data_hi ),
.S_ACK_LO ( s_ack_lo ),
.S_ACK_HI ( s_ack_hi ),
.S_START ( s_start ),
.S_STOP_LO ( s_stop_lo ),
.S_STOP_HI ( s_stop_hi ),
.S_IDLE ( s_idle ));
assign BUSY = ~s_idle;
assign l_scl = (s_data_lo | s_ack_lo | s_stop_lo) ? 1'b0 : 1'b1;
assign l_data = sreg_out | read_mode;
assign l_ack = ~read_mode ^ (nack_hack & l_done);
assign l_sda = (s_start | s_stop_lo | s_stop_hi ) ? 1'b0 :
(s_data_lo | s_data_hi) ? l_data :
(s_ack_lo | s_ack_hi ) ? l_ack :
1'b1;
ffds #(1) scl_fd(CLK, l_scl, scl_q);
ffds #(1) sda_fd(CLK, l_sda, sda_q);
assign SDA = sda_q ? 1'bZ : 1'b0;
assign SCL = scl_q ? 1'bZ : 1'b0;
endmodule | module i2c ( input CLK,
input RESET,
input START,
output BUSY,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
output RD_ADV,
output WR_ADV,
inout SDA,
inout SCL ); |
parameter TAU = 63;
logic ld_len, ld_wlen, adv, l_done, byte_done, read_mode, half_period;
logic l_scl, l_sda, scl_q, sda_q, l_data, l_ack, sreg_out, next_byte, adv_wlen;
logic s_idle, s_start, s_stop_lo, s_stop_hi, s_data_lo, s_data_hi, s_ack_lo, s_ack_hi;
logic shift_in, nack_hack;
assign next_byte = ( half_period & s_data_hi & byte_done & ~l_done );
assign adv_wlen = ( half_period & s_ack_hi & byte_done & ~read_mode);
assign RD_ADV = (next_byte & ~read_mode) | ld_len | ld_wlen;
inv_ld_counter #(7) len_cnt( .CLK ( CLK ),
.SET ( ld_len ),
.IN ( DATA_IN[6:0] ),
.EN ( next_byte ),
.ZERO ( l_done ) );
inv_ld_counter #(7) wlen_cnt( .CLK ( CLK ),
.SET ( ld_wlen ),
.IN ( DATA_IN[6:0] ),
.EN ( adv_wlen ),
.ZERO ( read_mode ));
ffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);
logic [5:0] time_cnt;
assign half_period = (time_cnt == TAU);
counter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);
shift_out_reg_left #(8) sr_out( .CLK ( CLK ),
.UPDATE ( half_period & (s_start | s_ack_hi) ),
.SHIFT ( half_period & s_data_hi & ~byte_done ),
.DATA ( DATA_IN ),
.OUT ( sreg_out ),
.EMPTY ( byte_done ));
assign shift_in = read_mode & half_period & s_data_hi;
assign WR_ADV = read_mode & half_period & s_ack_hi & byte_done;
shift_in_reg_left #(8) sr_in( .CLK ( CLK ),
.RESET ( half_period & (s_start | s_ack_hi) ),
.SHIFT ( shift_in ),
.IN ( SDA ),
.DATA ( DATA_OUT ));
i2c_fsm i2c_fsm( .CLK ( CLK ),
.RESET ( RESET ),
.START ( START ),
.TIME ( half_period ),
.L_DONE ( l_done ),
.W_DONE ( byte_done ),
.LD_LEN ( ld_len ),
.LD_WLEN ( ld_wlen ),
.S_DATA_LO ( s_data_lo ),
.S_DATA_HI ( s_data_hi ),
.S_ACK_LO ( s_ack_lo ),
.S_ACK_HI ( s_ack_hi ),
.S_START ( s_start ),
.S_STOP_LO ( s_stop_lo ),
.S_STOP_HI ( s_stop_hi ),
.S_IDLE ( s_idle ));
assign BUSY = ~s_idle;
assign l_scl = (s_data_lo | s_ack_lo | s_stop_lo) ? 1'b0 : 1'b1;
assign l_data = sreg_out | read_mode;
assign l_ack = ~read_mode ^ (nack_hack & l_done);
assign l_sda = (s_start | s_stop_lo | s_stop_hi ) ? 1'b0 :
(s_data_lo | s_data_hi) ? l_data :
(s_ack_lo | s_ack_hi ) ? l_ack :
1'b1;
ffds #(1) scl_fd(CLK, l_scl, scl_q);
ffds #(1) sda_fd(CLK, l_sda, sda_q);
assign SDA = sda_q ? 1'bZ : 1'b0;
assign SCL = scl_q ? 1'bZ : 1'b0;
endmodule | 5 |
3,288 | data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv | 10,379,745 | i2c.sv | sv | 193 | 95 | [] | [] | [] | null | line:116: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:26: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) len_cnt( .CLK ( CLK ), \n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.v\n data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.sv\n inv_ld_counter\n inv_ld_counter.v\n inv_ld_counter.sv\n obj_dir/inv_ld_counter\n obj_dir/inv_ld_counter.v\n obj_dir/inv_ld_counter.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:32: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) wlen_cnt( .CLK ( CLK ), \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:38: Cannot find file containing module: 'ffd'\nffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:42: Cannot find file containing module: 'counter'\ncounter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:44: Cannot find file containing module: 'shift_out_reg_left'\nshift_out_reg_left #(8) sr_out( .CLK ( CLK ), \n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:53: Cannot find file containing module: 'shift_in_reg_left'\nshift_in_reg_left #(8) sr_in( .CLK ( CLK ),\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:88: Cannot find file containing module: 'ffds'\nffds #(1) scl_fd(CLK, l_scl, scl_q);\n^~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:89: Cannot find file containing module: 'ffds'\nffds #(1) sda_fd(CLK, l_sda, sda_q);\n^~~~\n%Error: Exiting due to 8 error(s)\n" | 1,043 | module | module i2c_fsm ( input CLK,
input RESET,
input START,
input TIME,
input L_DONE,
input W_DONE,
output LD_LEN,
output LD_WLEN,
output S_DATA_LO,
output S_DATA_HI,
output S_ACK_LO,
output S_ACK_HI,
output S_START,
output S_STOP_LO,
output S_STOP_HI,
output S_IDLE );
enum int unsigned { ST_IDLE = 0,
ST_RD_LEN = 1,
ST_RD_WLEN = 2,
ST_START = 3,
ST_DATA_LO = 4,
ST_DATA_HI = 5,
ST_ACK_LO = 6,
ST_ACK_HI = 7,
ST_STOP_LO = 8,
ST_STOP_HI = 9,
ST_WAIT = 10 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_IDLE;
else state <= next;
always_comb
case(state)
ST_IDLE: if(START) next = ST_RD_LEN;
else next = state;
ST_RD_LEN: next = ST_RD_WLEN;
ST_RD_WLEN: if(L_DONE) next = ST_IDLE;
else next = ST_START;
ST_START: if(TIME) next = ST_DATA_LO;
else next = state;
ST_DATA_LO: if(TIME) next = ST_DATA_HI;
else next = state;
ST_DATA_HI: if(TIME)
begin
if(W_DONE) next = ST_ACK_LO;
else next = ST_DATA_LO;
end
else next = state;
ST_ACK_LO: if(TIME) next = ST_ACK_HI;
else next = state;
ST_ACK_HI: if(TIME)
begin
if(L_DONE) next = ST_STOP_LO;
else next = ST_DATA_LO;
end
else next = state;
ST_STOP_LO: if(TIME) next = ST_STOP_HI;
else next = state;
ST_STOP_HI: if(TIME) next = ST_WAIT;
else next = state;
ST_WAIT: if(TIME) next = ST_RD_LEN;
else next = state;
default: next = ST_IDLE;
endcase
assign LD_LEN = (state == ST_RD_LEN);
assign LD_WLEN = (state == ST_RD_WLEN);
assign S_DATA_LO = (state == ST_DATA_LO);
assign S_DATA_HI = (state == ST_DATA_HI);
assign S_ACK_LO = (state == ST_ACK_LO);
assign S_ACK_HI = (state == ST_ACK_HI);
assign S_START = (state == ST_START);
assign S_STOP_LO = (state == ST_STOP_LO);
assign S_STOP_HI = (state == ST_STOP_HI);
assign S_IDLE = (state == ST_IDLE);
endmodule | module i2c_fsm ( input CLK,
input RESET,
input START,
input TIME,
input L_DONE,
input W_DONE,
output LD_LEN,
output LD_WLEN,
output S_DATA_LO,
output S_DATA_HI,
output S_ACK_LO,
output S_ACK_HI,
output S_START,
output S_STOP_LO,
output S_STOP_HI,
output S_IDLE ); |
enum int unsigned { ST_IDLE = 0,
ST_RD_LEN = 1,
ST_RD_WLEN = 2,
ST_START = 3,
ST_DATA_LO = 4,
ST_DATA_HI = 5,
ST_ACK_LO = 6,
ST_ACK_HI = 7,
ST_STOP_LO = 8,
ST_STOP_HI = 9,
ST_WAIT = 10 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_IDLE;
else state <= next;
always_comb
case(state)
ST_IDLE: if(START) next = ST_RD_LEN;
else next = state;
ST_RD_LEN: next = ST_RD_WLEN;
ST_RD_WLEN: if(L_DONE) next = ST_IDLE;
else next = ST_START;
ST_START: if(TIME) next = ST_DATA_LO;
else next = state;
ST_DATA_LO: if(TIME) next = ST_DATA_HI;
else next = state;
ST_DATA_HI: if(TIME)
begin
if(W_DONE) next = ST_ACK_LO;
else next = ST_DATA_LO;
end
else next = state;
ST_ACK_LO: if(TIME) next = ST_ACK_HI;
else next = state;
ST_ACK_HI: if(TIME)
begin
if(L_DONE) next = ST_STOP_LO;
else next = ST_DATA_LO;
end
else next = state;
ST_STOP_LO: if(TIME) next = ST_STOP_HI;
else next = state;
ST_STOP_HI: if(TIME) next = ST_WAIT;
else next = state;
ST_WAIT: if(TIME) next = ST_RD_LEN;
else next = state;
default: next = ST_IDLE;
endcase
assign LD_LEN = (state == ST_RD_LEN);
assign LD_WLEN = (state == ST_RD_WLEN);
assign S_DATA_LO = (state == ST_DATA_LO);
assign S_DATA_HI = (state == ST_DATA_HI);
assign S_ACK_LO = (state == ST_ACK_LO);
assign S_ACK_HI = (state == ST_ACK_HI);
assign S_START = (state == ST_START);
assign S_STOP_LO = (state == ST_STOP_LO);
assign S_STOP_HI = (state == ST_STOP_HI);
assign S_IDLE = (state == ST_IDLE);
endmodule | 5 |
3,302 | data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv | 10,379,745 | simple_fifo.sv | sv | 72 | 67 | [] | [] | [] | null | line:13: before: "read_ptr" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:26: Cannot find file containing module: 'counter_ll'\ncounter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty, read_ptr);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.sv\n counter_ll\n counter_ll.v\n counter_ll.sv\n obj_dir/counter_ll\n obj_dir/counter_ll.v\n obj_dir/counter_ll.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:27: Cannot find file containing module: 'counter'\ncounter #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:28: Cannot find file containing module: 'ffd'\nffd #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);\n^~~\n%Error: Exiting due to 3 error(s)\n" | 1,050 | module | module simple_fifo #(parameter D = 11, W = 16)
( input CLK,
input RESET,
input RE,
input WE,
output [W-1:0] R_DATA,
input [W-1:0] W_DATA,
output [D-1:0] FILL,
output NOT_EMPTY,
output OVFLOW );
logic unsigned [D-1:0] read_ptr, write_ptr, next_fill, fill;
logic empty;
assign next_fill = write_ptr - read_ptr;
assign empty = (fill == '0);
assign OVFLOW = ((next_fill == '1) && WE);
assign NOT_EMPTY = ~empty;
assign FILL = fill;
counter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty, read_ptr);
counter #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);
ffd #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);
dp_ram #(D, W) dp_ram ( .CLK ( CLK ),
.R_ADDR ( read_ptr ),
.R_DATA ( R_DATA ),
.WE ( WE ),
.W_ADDR ( write_ptr ),
.W_DATA ( W_DATA ));
endmodule | module simple_fifo #(parameter D = 11, W = 16)
( input CLK,
input RESET,
input RE,
input WE,
output [W-1:0] R_DATA,
input [W-1:0] W_DATA,
output [D-1:0] FILL,
output NOT_EMPTY,
output OVFLOW ); |
logic unsigned [D-1:0] read_ptr, write_ptr, next_fill, fill;
logic empty;
assign next_fill = write_ptr - read_ptr;
assign empty = (fill == '0);
assign OVFLOW = ((next_fill == '1) && WE);
assign NOT_EMPTY = ~empty;
assign FILL = fill;
counter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty, read_ptr);
counter #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);
ffd #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);
dp_ram #(D, W) dp_ram ( .CLK ( CLK ),
.R_ADDR ( read_ptr ),
.R_DATA ( R_DATA ),
.WE ( WE ),
.W_ADDR ( write_ptr ),
.W_DATA ( W_DATA ));
endmodule | 5 |
3,303 | data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv | 10,379,745 | simple_fifo.sv | sv | 72 | 67 | [] | [] | [] | null | line:13: before: "read_ptr" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:26: Cannot find file containing module: 'counter_ll'\ncounter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty, read_ptr);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.sv\n counter_ll\n counter_ll.v\n counter_ll.sv\n obj_dir/counter_ll\n obj_dir/counter_ll.v\n obj_dir/counter_ll.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:27: Cannot find file containing module: 'counter'\ncounter #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:28: Cannot find file containing module: 'ffd'\nffd #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);\n^~~\n%Error: Exiting due to 3 error(s)\n" | 1,050 | module | module dp_ram #( parameter DEPTH = 11,
parameter WIDTH = 16 )
( input CLK,
input [DEPTH-1:0] R_ADDR,
output [WIDTH-1:0] R_DATA,
input WE,
input [DEPTH-1:0] W_ADDR,
input [WIDTH-1:0] W_DATA );
logic [WIDTH-1:0] ram[0:2**DEPTH-1];
logic [WIDTH-1:0] rd;
initial
begin
for(int i = 0; i < (2**DEPTH); i = i + 1)
ram[i] = '0;
end
always_ff@(posedge CLK)
begin
if(WE) ram[W_ADDR] <= W_DATA;
rd <= ram[R_ADDR];
end
assign R_DATA = rd;
endmodule | module dp_ram #( parameter DEPTH = 11,
parameter WIDTH = 16 )
( input CLK,
input [DEPTH-1:0] R_ADDR,
output [WIDTH-1:0] R_DATA,
input WE,
input [DEPTH-1:0] W_ADDR,
input [WIDTH-1:0] W_DATA ); |
logic [WIDTH-1:0] ram[0:2**DEPTH-1];
logic [WIDTH-1:0] rd;
initial
begin
for(int i = 0; i < (2**DEPTH); i = i + 1)
ram[i] = '0;
end
always_ff@(posedge CLK)
begin
if(WE) ram[W_ADDR] <= W_DATA;
rd <= ram[R_ADDR];
end
assign R_DATA = rd;
endmodule | 5 |
3,304 | data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv | 10,379,745 | uart_rx.sv | sv | 129 | 78 | [] | [] | [] | null | line:77: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:23: Cannot find file containing module: 'sync_edetect'\nsync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.sv\n sync_edetect\n sync_edetect.v\n sync_edetect.sv\n obj_dir/sync_edetect\n obj_dir/sync_edetect.v\n obj_dir/sync_edetect.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:33: Cannot find file containing module: 'counter'\ncounter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:36: Cannot find file containing module: 'counter'\ncounter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:38: Cannot find file containing module: 'shift_in_reg_right'\nshift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:41: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);\n^~~\n%Error: Exiting due to 5 error(s)\n" | 1,051 | module | module uart_rx ( input CLK,
input RESET,
input [15:0] BIT_TIME,
input PARITY_EN,
input PARITY_ODD,
output [7:0] DATA,
output EN,
output PARITY_ERR,
output IDLE,
input RX );
logic any_edge, neg_edge, count_en, half_period, full_period,
byte_done, data_bit, dp_bit, start_bit, cnt_reset, resync,
par_fd_in, par_fd_q, shift_bit, shift_bit_p, rx_s;
logic [15:0] bit_cnt_q;
logic [2:0] byte_cnt_q;
sync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);
assign resync = (half_period & start_bit);
assign shift_bit = (full_period & data_bit);
assign shift_bit_p = (full_period & dp_bit);
assign half_period = (bit_cnt_q == {1'b0, BIT_TIME[15:1]});
assign full_period = (bit_cnt_q == BIT_TIME);
assign cnt_reset = ~count_en | resync | shift_bit_p;
counter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );
assign byte_done = (byte_cnt_q == 3'd7);
counter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );
shift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );
assign par_fd_in = resync ? PARITY_ODD : (par_fd_q ^ rx_s);
ffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);
uart_rx_fsm fsm( .CLK ( CLK ),
.RESET ( RESET ),
.NEG_EDGE ( neg_edge ),
.ANY_EDGE ( any_edge ),
.HALF_PERIOD ( half_period ),
.FULL_PERIOD ( full_period ),
.BYTE_DONE ( byte_done ),
.PARITY_EN ( PARITY_EN ),
.COUNT_EN ( count_en ),
.START_BIT ( start_bit ),
.DATA_BIT ( data_bit ),
.DP_BIT ( dp_bit ),
.DONE ( EN ),
.READY ( IDLE ) );
assign PARITY_ERR = par_fd_q & EN;
endmodule | module uart_rx ( input CLK,
input RESET,
input [15:0] BIT_TIME,
input PARITY_EN,
input PARITY_ODD,
output [7:0] DATA,
output EN,
output PARITY_ERR,
output IDLE,
input RX ); |
logic any_edge, neg_edge, count_en, half_period, full_period,
byte_done, data_bit, dp_bit, start_bit, cnt_reset, resync,
par_fd_in, par_fd_q, shift_bit, shift_bit_p, rx_s;
logic [15:0] bit_cnt_q;
logic [2:0] byte_cnt_q;
sync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);
assign resync = (half_period & start_bit);
assign shift_bit = (full_period & data_bit);
assign shift_bit_p = (full_period & dp_bit);
assign half_period = (bit_cnt_q == {1'b0, BIT_TIME[15:1]});
assign full_period = (bit_cnt_q == BIT_TIME);
assign cnt_reset = ~count_en | resync | shift_bit_p;
counter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );
assign byte_done = (byte_cnt_q == 3'd7);
counter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );
shift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );
assign par_fd_in = resync ? PARITY_ODD : (par_fd_q ^ rx_s);
ffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);
uart_rx_fsm fsm( .CLK ( CLK ),
.RESET ( RESET ),
.NEG_EDGE ( neg_edge ),
.ANY_EDGE ( any_edge ),
.HALF_PERIOD ( half_period ),
.FULL_PERIOD ( full_period ),
.BYTE_DONE ( byte_done ),
.PARITY_EN ( PARITY_EN ),
.COUNT_EN ( count_en ),
.START_BIT ( start_bit ),
.DATA_BIT ( data_bit ),
.DP_BIT ( dp_bit ),
.DONE ( EN ),
.READY ( IDLE ) );
assign PARITY_ERR = par_fd_q & EN;
endmodule | 5 |
3,305 | data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv | 10,379,745 | uart_rx.sv | sv | 129 | 78 | [] | [] | [] | null | line:77: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:23: Cannot find file containing module: 'sync_edetect'\nsync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.sv\n sync_edetect\n sync_edetect.v\n sync_edetect.sv\n obj_dir/sync_edetect\n obj_dir/sync_edetect.v\n obj_dir/sync_edetect.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:33: Cannot find file containing module: 'counter'\ncounter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:36: Cannot find file containing module: 'counter'\ncounter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:38: Cannot find file containing module: 'shift_in_reg_right'\nshift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:41: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);\n^~~\n%Error: Exiting due to 5 error(s)\n" | 1,051 | module | module uart_rx_fsm( input CLK,
input RESET,
input NEG_EDGE,
input ANY_EDGE,
input HALF_PERIOD,
input FULL_PERIOD,
input BYTE_DONE,
input PARITY_EN,
output COUNT_EN,
output START_BIT,
output DATA_BIT,
output DP_BIT,
output DONE,
output READY );
enum int unsigned { ST_READY = 0,
ST_START_BIT = 1,
ST_DATA_BIT = 2,
ST_PARITY_BIT = 3,
ST_DONE = 4 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_READY;
else state <= next;
always_comb begin
next = ST_READY;
case(state)
ST_READY: if(NEG_EDGE) next = ST_START_BIT;
else next = state;
ST_START_BIT: if(ANY_EDGE) next = ST_READY;
else if(HALF_PERIOD) next = ST_DATA_BIT;
else next = state;
ST_DATA_BIT: if(FULL_PERIOD &
BYTE_DONE)
begin
if(PARITY_EN) next = ST_PARITY_BIT;
else next = ST_DONE;
end
else next = state;
ST_PARITY_BIT: if(FULL_PERIOD) next = ST_DONE;
else next = state;
ST_DONE: next = ST_READY;
default: next = ST_READY;
endcase
end
assign START_BIT = (state == ST_START_BIT);
assign DATA_BIT = (state == ST_DATA_BIT);
assign DP_BIT = DATA_BIT | (state == ST_PARITY_BIT);
assign COUNT_EN = DP_BIT | (state == ST_START_BIT);
assign DONE = (state == ST_DONE);
assign READY = (state == ST_READY);
endmodule | module uart_rx_fsm( input CLK,
input RESET,
input NEG_EDGE,
input ANY_EDGE,
input HALF_PERIOD,
input FULL_PERIOD,
input BYTE_DONE,
input PARITY_EN,
output COUNT_EN,
output START_BIT,
output DATA_BIT,
output DP_BIT,
output DONE,
output READY ); |
enum int unsigned { ST_READY = 0,
ST_START_BIT = 1,
ST_DATA_BIT = 2,
ST_PARITY_BIT = 3,
ST_DONE = 4 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_READY;
else state <= next;
always_comb begin
next = ST_READY;
case(state)
ST_READY: if(NEG_EDGE) next = ST_START_BIT;
else next = state;
ST_START_BIT: if(ANY_EDGE) next = ST_READY;
else if(HALF_PERIOD) next = ST_DATA_BIT;
else next = state;
ST_DATA_BIT: if(FULL_PERIOD &
BYTE_DONE)
begin
if(PARITY_EN) next = ST_PARITY_BIT;
else next = ST_DONE;
end
else next = state;
ST_PARITY_BIT: if(FULL_PERIOD) next = ST_DONE;
else next = state;
ST_DONE: next = ST_READY;
default: next = ST_READY;
endcase
end
assign START_BIT = (state == ST_START_BIT);
assign DATA_BIT = (state == ST_DATA_BIT);
assign DP_BIT = DATA_BIT | (state == ST_PARITY_BIT);
assign COUNT_EN = DP_BIT | (state == ST_START_BIT);
assign DONE = (state == ST_DONE);
assign READY = (state == ST_READY);
endmodule | 5 |
3,306 | data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv | 10,379,745 | uart_top.sv | sv | 49 | 82 | [] | [] | [] | [(1, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:15: Cannot find file containing module: 'ffd'\nffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);\n^~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd.sv\n ffd\n ffd.v\n ffd.sv\n obj_dir/ffd\n obj_dir/ffd.v\n obj_dir/ffd.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:16: Cannot find file containing module: 'ffd'\nffd #(2) par_fd(CLK, RESET, WE & (A == 3'd6), WD[1:0], {par_odd, par_en}); \n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:18: Cannot find file containing module: 'buffered_rx'\nbuffered_rx #(5, 434) buffered_rx ( .CLK ( CLK ),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:30: Cannot find file containing module: 'buffered_tx'\nbuffered_tx #(5, 434) buffered_tx ( .CLK ( CLK ),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:41: Cannot find file containing module: 'mux4'\nmux4 #(32) omux( A[2:1],\n^~~~\n%Error: Exiting due to 5 error(s)\n" | 1,052 | module | module uart_top ( input CLK,
input RESET,
input WE,
input RE,
input [2:0] A,
input [31:0] WD,
output [31:0] RD,
output UART_TX,
input UART_RX );
logic [31:0] rx_rd, tx_rd;
logic [15:0] bit_time;
logic par_en, par_odd;
ffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);
ffd #(2) par_fd(CLK, RESET, WE & (A == 3'd6), WD[1:0], {par_odd, par_en});
buffered_rx #(5, 434) buffered_rx ( .CLK ( CLK ),
.RESET ( RESET ),
.BIT_TIME ( bit_time ),
.PARITY_EN ( par_en ),
.PARITY_ODD ( par_odd ),
.RE ( RE & ~A[2] & A[1] ),
.WE ( WE & ~A[2] & A[1] ),
.A ( A[0] ),
.RD ( rx_rd ),
.UART_RX ( UART_RX ) );
buffered_tx #(5, 434) buffered_tx ( .CLK ( CLK ),
.RESET ( RESET ),
.BIT_TIME ( bit_time ),
.PARITY_EN ( par_en ),
.PARITY_ODD ( par_odd ),
.WE ( WE & ~A[2] & ~A[1] ),
.A ( A[0] ),
.WD ( WD ),
.RD ( tx_rd ),
.UART_TX ( UART_TX ) );
mux4 #(32) omux( A[2:1],
tx_rd,
rx_rd,
{16'd0, bit_time},
{30'd0, par_odd, par_en},
RD );
endmodule | module uart_top ( input CLK,
input RESET,
input WE,
input RE,
input [2:0] A,
input [31:0] WD,
output [31:0] RD,
output UART_TX,
input UART_RX ); |
logic [31:0] rx_rd, tx_rd;
logic [15:0] bit_time;
logic par_en, par_odd;
ffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);
ffd #(2) par_fd(CLK, RESET, WE & (A == 3'd6), WD[1:0], {par_odd, par_en});
buffered_rx #(5, 434) buffered_rx ( .CLK ( CLK ),
.RESET ( RESET ),
.BIT_TIME ( bit_time ),
.PARITY_EN ( par_en ),
.PARITY_ODD ( par_odd ),
.RE ( RE & ~A[2] & A[1] ),
.WE ( WE & ~A[2] & A[1] ),
.A ( A[0] ),
.RD ( rx_rd ),
.UART_RX ( UART_RX ) );
buffered_tx #(5, 434) buffered_tx ( .CLK ( CLK ),
.RESET ( RESET ),
.BIT_TIME ( bit_time ),
.PARITY_EN ( par_en ),
.PARITY_ODD ( par_odd ),
.WE ( WE & ~A[2] & ~A[1] ),
.A ( A[0] ),
.WD ( WD ),
.RD ( tx_rd ),
.UART_TX ( UART_TX ) );
mux4 #(32) omux( A[2:1],
tx_rd,
rx_rd,
{16'd0, bit_time},
{30'd0, par_odd, par_en},
RD );
endmodule | 5 |
3,307 | data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv | 10,379,745 | uart_tx.sv | sv | 110 | 78 | [] | [] | [] | null | line:63: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:23: Cannot find file containing module: 'shift_out_reg_right'\nshift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);\n^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.sv\n shift_out_reg_right\n shift_out_reg_right.v\n shift_out_reg_right.sv\n obj_dir/shift_out_reg_right\n obj_dir/shift_out_reg_right.v\n obj_dir/shift_out_reg_right.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:25: Cannot find file containing module: 'counter'\ncounter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:27: Cannot find file containing module: 'counter'\ncounter #(3) byte_counter(CLK, ready, bit_inc, byte_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:31: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:32: Cannot find file containing module: 'ffd'\nffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );\n^~~\n%Error: Exiting due to 5 error(s)\n" | 1,053 | module | module uart_tx ( input CLK,
input RESET,
input [7:0] DATA,
input EN,
output READY,
input [15:0] BIT_TIME,
input PARITY_EN,
input PARITY_ODD,
output TX );
logic ready, par_ovr, fsm_ovr, fsm_val, sr_q, tx_logic,
bit_done, byte_done, bit_inc, par_fd_in, par_fd_q;
logic [15:0] bit_cnt;
logic [2:0] byte_cnt;
assign bit_done = (bit_cnt == BIT_TIME);
assign byte_done = (byte_cnt == 3'd7);
assign bit_inc = bit_done & ~fsm_ovr;
shift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);
counter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt );
counter #(3) byte_counter(CLK, ready, bit_inc, byte_cnt );
assign par_fd_in = (EN & ready) ? PARITY_ODD : (par_fd_q ^ sr_q);
ffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);
ffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );
uart_tx_fsm fsm( .CLK ( CLK ),
.RESET ( RESET ),
.EN ( EN ),
.BIT_DONE ( bit_done ),
.BYTE_DONE ( byte_done ),
.PARITY_EN ( PARITY_EN ),
.READY ( ready ),
.PAR_OVR ( par_ovr ),
.FSM_OVR ( fsm_ovr ),
.FSM_VAL ( fsm_val ) );
assign READY = ready;
assign tx_logic = par_ovr ? par_fd_q :
fsm_ovr ? fsm_val :
sr_q ;
endmodule | module uart_tx ( input CLK,
input RESET,
input [7:0] DATA,
input EN,
output READY,
input [15:0] BIT_TIME,
input PARITY_EN,
input PARITY_ODD,
output TX ); |
logic ready, par_ovr, fsm_ovr, fsm_val, sr_q, tx_logic,
bit_done, byte_done, bit_inc, par_fd_in, par_fd_q;
logic [15:0] bit_cnt;
logic [2:0] byte_cnt;
assign bit_done = (bit_cnt == BIT_TIME);
assign byte_done = (byte_cnt == 3'd7);
assign bit_inc = bit_done & ~fsm_ovr;
shift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);
counter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt );
counter #(3) byte_counter(CLK, ready, bit_inc, byte_cnt );
assign par_fd_in = (EN & ready) ? PARITY_ODD : (par_fd_q ^ sr_q);
ffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);
ffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );
uart_tx_fsm fsm( .CLK ( CLK ),
.RESET ( RESET ),
.EN ( EN ),
.BIT_DONE ( bit_done ),
.BYTE_DONE ( byte_done ),
.PARITY_EN ( PARITY_EN ),
.READY ( ready ),
.PAR_OVR ( par_ovr ),
.FSM_OVR ( fsm_ovr ),
.FSM_VAL ( fsm_val ) );
assign READY = ready;
assign tx_logic = par_ovr ? par_fd_q :
fsm_ovr ? fsm_val :
sr_q ;
endmodule | 5 |
3,308 | data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv | 10,379,745 | uart_tx.sv | sv | 110 | 78 | [] | [] | [] | null | line:63: before: "unsigned" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:23: Cannot find file containing module: 'shift_out_reg_right'\nshift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);\n^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.v\n data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.sv\n shift_out_reg_right\n shift_out_reg_right.v\n shift_out_reg_right.sv\n obj_dir/shift_out_reg_right\n obj_dir/shift_out_reg_right.v\n obj_dir/shift_out_reg_right.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:25: Cannot find file containing module: 'counter'\ncounter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:27: Cannot find file containing module: 'counter'\ncounter #(3) byte_counter(CLK, ready, bit_inc, byte_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:31: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:32: Cannot find file containing module: 'ffd'\nffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );\n^~~\n%Error: Exiting due to 5 error(s)\n" | 1,053 | module | module uart_tx_fsm( input CLK,
input RESET,
input EN,
input BIT_DONE,
input BYTE_DONE,
input PARITY_EN,
output READY,
output PAR_OVR,
output FSM_OVR,
output FSM_VAL );
enum int unsigned { ST_READY = 0,
ST_START_BIT = 1,
ST_DATA_BIT = 2,
ST_PARITY_BIT = 3,
ST_STOP_BIT = 4 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_READY;
else state <= next;
always_comb begin
next = ST_READY;
case(state)
ST_READY: if(EN) next = ST_START_BIT;
else next = state;
ST_START_BIT: if(BIT_DONE) next = ST_DATA_BIT;
else next = state;
ST_DATA_BIT: if(BIT_DONE &
BYTE_DONE)
begin
if(PARITY_EN) next = ST_PARITY_BIT;
else next = ST_STOP_BIT;
end
else next = state;
ST_PARITY_BIT: if(BIT_DONE) next = ST_STOP_BIT;
else next = state;
ST_STOP_BIT: if(BIT_DONE) next = ST_READY;
else next = state;
default: next = ST_READY;
endcase
end
assign READY = (state == ST_READY );
assign PAR_OVR = (state == ST_PARITY_BIT);
assign FSM_OVR = (state != ST_DATA_BIT);
assign FSM_VAL = ((state == ST_READY) |
(state == ST_STOP_BIT));
endmodule | module uart_tx_fsm( input CLK,
input RESET,
input EN,
input BIT_DONE,
input BYTE_DONE,
input PARITY_EN,
output READY,
output PAR_OVR,
output FSM_OVR,
output FSM_VAL ); |
enum int unsigned { ST_READY = 0,
ST_START_BIT = 1,
ST_DATA_BIT = 2,
ST_PARITY_BIT = 3,
ST_STOP_BIT = 4 } state, next;
always_ff@(posedge CLK)
if(RESET) state <= ST_READY;
else state <= next;
always_comb begin
next = ST_READY;
case(state)
ST_READY: if(EN) next = ST_START_BIT;
else next = state;
ST_START_BIT: if(BIT_DONE) next = ST_DATA_BIT;
else next = state;
ST_DATA_BIT: if(BIT_DONE &
BYTE_DONE)
begin
if(PARITY_EN) next = ST_PARITY_BIT;
else next = ST_STOP_BIT;
end
else next = state;
ST_PARITY_BIT: if(BIT_DONE) next = ST_STOP_BIT;
else next = state;
ST_STOP_BIT: if(BIT_DONE) next = ST_READY;
else next = state;
default: next = ST_READY;
endcase
end
assign READY = (state == ST_READY );
assign PAR_OVR = (state == ST_PARITY_BIT);
assign FSM_OVR = (state != ST_DATA_BIT);
assign FSM_VAL = ((state == ST_READY) |
(state == ST_STOP_BIT));
endmodule | 5 |
3,309 | data/full_repos/permissive/103842408/bin/fsm-template.v | 103,842,408 | fsm-template.v | v | 118 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:16: syntax error, unexpected \'{\', expecting \'[\'\n{% for interface_name in interfaces|sort %}\n^\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:39: syntax error, unexpected \'{\', expecting IDENTIFIER or \'=\' or do or final\nreg [{{state_var_w}}:0] {{state_var}};\n ^\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:40: syntax error, unexpected \'{\', expecting \',\' or \';\'\nreg [{{state_var_w}}:0] n_{{state_var}};\n ^\n%Error: Exiting due to 4 error(s)\n' | 1,055 | module | module rvm_control(
input wire clk ,
input wire resetn ,
{% for interface_name in interfaces|sort %}
{% set interface = interfaces[interface_name] %}
{% for signal_name in interface.signals|sort -%}
{% set signal = interface.signals[signal_name] -%}
{{signal.direction()}} [{{signal.get_range()}}] {{signal.verilog_name()}}
{%- if not loop.last -%},{% endif %}
{% endfor -%}
{%- if not loop.last -%},{%- endif -%}
{% endfor %}
);
{% for state in states|sort %}
localparam {{states[state].verilog_name()}} = {{states[state].get_encoding()}};
{%- endfor %}
reg [{{state_var_w}}:0] {{state_var}};
reg [{{state_var_w}}:0] n_{{state_var}};
{% for interface_name in interfaces|sort %}
{%- set interface = interfaces[interface_name] %}
{% for signal_name in interface.signals|sort -%}
{%- set signal = interface.signals[signal_name] -%}
{%- if signal.writable %}
assign {{signal_name}} =
{%- if signal.values|length == 0 -%} 0; {%-endif-%}
{% for assignment in signal.values|sort(attribute="value") -%}
({ {{signal|length}} { {{state_var-}}
==
{{-assignment.state.verilog_name()-}} } } & {{assignment.value}})
{%- if(loop.last) -%}
;
{%- else %} |
{%- endif %}
{% endfor %}
{%- endif -%}
{%- endfor -%}
{% endfor %}
always @(*) begin : p_ctrl_next_state
case ({{state_var}})
{%- for state_name in states|sort %}
{% set state = states[state_name] %}
{{state.verilog_name()}}: begin
{% if state.single_next_state -%}
n_{{state_var}} = {{state.next_state.verilog_name()}};
{%- else -%}
n_{{state_var}} = {{default_next_state}};
{% for ass in state.next_state|sort(attribute="value") %}
if ({{ass.condition}}) n_{{state_var}} = {{ass.value}};
{% endfor -%}
{%- endif %}
end
{%- endfor %}
default:
n_{{state_var}} = {{default_next_state}};
endcase end
always @(posedge clk, negedge resetn) begin : p_ctrl_progress_state
if(!resetn) begin
{{state_var}} <= {{default_next_state}};
end else begin
{{state_var}} <= n_{{state_var}};
end
end
endmodule | module rvm_control(
input wire clk ,
input wire resetn ,
{% for interface_name in interfaces|sort %}
{% set interface = interfaces[interface_name] %}
{% for signal_name in interface.signals|sort -%}
{% set signal = interface.signals[signal_name] -%}
{{signal.direction()}} [{{signal.get_range()}}] {{signal.verilog_name()}}
{%- if not loop.last -%},{% endif %}
{% endfor -%}
{%- if not loop.last -%},{%- endif -%}
{% endfor %}
); |
{% for state in states|sort %}
localparam {{states[state].verilog_name()}} = {{states[state].get_encoding()}};
{%- endfor %}
reg [{{state_var_w}}:0] {{state_var}};
reg [{{state_var_w}}:0] n_{{state_var}};
{% for interface_name in interfaces|sort %}
{%- set interface = interfaces[interface_name] %}
{% for signal_name in interface.signals|sort -%}
{%- set signal = interface.signals[signal_name] -%}
{%- if signal.writable %}
assign {{signal_name}} =
{%- if signal.values|length == 0 -%} 0; {%-endif-%}
{% for assignment in signal.values|sort(attribute="value") -%}
({ {{signal|length}} { {{state_var-}}
==
{{-assignment.state.verilog_name()-}} } } & {{assignment.value}})
{%- if(loop.last) -%}
;
{%- else %} |
{%- endif %}
{% endfor %}
{%- endif -%}
{%- endfor -%}
{% endfor %}
always @(*) begin : p_ctrl_next_state
case ({{state_var}})
{%- for state_name in states|sort %}
{% set state = states[state_name] %}
{{state.verilog_name()}}: begin
{% if state.single_next_state -%}
n_{{state_var}} = {{state.next_state.verilog_name()}};
{%- else -%}
n_{{state_var}} = {{default_next_state}};
{% for ass in state.next_state|sort(attribute="value") %}
if ({{ass.condition}}) n_{{state_var}} = {{ass.value}};
{% endfor -%}
{%- endif %}
end
{%- endfor %}
default:
n_{{state_var}} = {{default_next_state}};
endcase end
always @(posedge clk, negedge resetn) begin : p_ctrl_progress_state
if(!resetn) begin
{{state_var}} <= {{default_next_state}};
end else begin
{{state_var}} <= n_{{state_var}};
end
end
endmodule | 3 |
3,310 | data/full_repos/permissive/103842408/rtl/template.v | 103,842,408 | template.v | v | 20 | 37 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/template.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,056 | module | module rvm_(
);
endmodule | module rvm_(
); |
endmodule | 3 |
3,311 | data/full_repos/permissive/103842408/rtl/main/rvm_adder.v | 103,842,408 | rvm_adder.v | v | 55 | 76 | [] | [] | [] | [(164, 198)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:18: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:34: Define or directive not defined: \'`RVM_ARITH_NOP\'\nwire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:34: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:35: Define or directive not defined: \'`RVM_ARITH_NOP\'\nwire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:35: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:37: Define or directive not defined: \'`RVM_ARITH_NOP\'\nassign valid = op != `RVM_ARITH_NOP;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign valid = op != `RVM_ARITH_NOP;\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:39: Define or directive not defined: \'`RVM_ARITH_GE\'\nwire result_ge = op == `RVM_ARITH_GE && $signed(lhs) >= $signed(rhs);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:39: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_ge = op == `RVM_ARITH_GE && $signed(lhs) >= $signed(rhs);\n ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:40: Define or directive not defined: \'`RVM_ARITH_GEU\'\nwire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:40: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);\n ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:41: Define or directive not defined: \'`RVM_ARITH_LT\'\nwire result_lt = op == `RVM_ARITH_LT && $signed(lhs) < $signed(rhs);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:41: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_lt = op == `RVM_ARITH_LT && $signed(lhs) < $signed(rhs);\n ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:42: Define or directive not defined: \'`RVM_ARITH_LTU\'\nwire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs < rhs);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:42: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs < rhs);\n ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:46: Define or directive not defined: \'`RVM_ARITH_ADD\'\nassign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:46: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nassign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:47: Define or directive not defined: \'`RVM_ARITH_SUB\'\n ({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:48: Define or directive not defined: \'`RVM_ARITH_GE\'\n ({33{op == `RVM_ARITH_GE }} & (result_ge )) |\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:49: Define or directive not defined: \'`RVM_ARITH_GEU\'\n ({33{op == `RVM_ARITH_GEU}} & (result_geu )) |\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:50: Define or directive not defined: \'`RVM_ARITH_LT\'\n ({33{op == `RVM_ARITH_LT }} & (result_lt )) |\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:51: Define or directive not defined: \'`RVM_ARITH_LTU\'\n ({33{op == `RVM_ARITH_LTU}} & (result_ltu )) ;\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n' | 1,058 | module | module rvm_adder(
input wire [31:0] lhs,
input wire [31:0] rhs,
input wire [2:0] op,
output wire valid,
output wire [31:0] result,
output wire overflow
);
wire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};
assign valid = op != `RVM_ARITH_NOP;
wire result_ge = op == `RVM_ARITH_GE && $signed(lhs) >= $signed(rhs);
wire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);
wire result_lt = op == `RVM_ARITH_LT && $signed(lhs) < $signed(rhs);
wire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs < rhs);
assign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |
({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |
({33{op == `RVM_ARITH_GE }} & (result_ge )) |
({33{op == `RVM_ARITH_GEU}} & (result_geu )) |
({33{op == `RVM_ARITH_LT }} & (result_lt )) |
({33{op == `RVM_ARITH_LTU}} & (result_ltu )) ;
endmodule | module rvm_adder(
input wire [31:0] lhs,
input wire [31:0] rhs,
input wire [2:0] op,
output wire valid,
output wire [31:0] result,
output wire overflow
); |
wire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};
assign valid = op != `RVM_ARITH_NOP;
wire result_ge = op == `RVM_ARITH_GE && $signed(lhs) >= $signed(rhs);
wire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);
wire result_lt = op == `RVM_ARITH_LT && $signed(lhs) < $signed(rhs);
wire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs < rhs);
assign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |
({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |
({33{op == `RVM_ARITH_GE }} & (result_ge )) |
({33{op == `RVM_ARITH_GEU}} & (result_geu )) |
({33{op == `RVM_ARITH_LT }} & (result_lt )) |
({33{op == `RVM_ARITH_LTU}} & (result_ltu )) ;
endmodule | 3 |
3,312 | data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v | 103,842,408 | rvm_bitwise.v | v | 43 | 73 | [] | [] | [] | [(163, 186)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:17: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:31: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nwire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:31: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:32: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nwire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:32: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:34: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nassign valid = op != `RVM_BITWISE_NOP;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign valid = op != `RVM_BITWISE_NOP;\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:38: Define or directive not defined: \'`RVM_BITWISE_OR\'\nassign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:38: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nassign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |\n ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:39: Define or directive not defined: \'`RVM_BITWISE_AND\'\n ({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:40: Define or directive not defined: \'`RVM_BITWISE_XOR\'\n ({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n' | 1,059 | module | module rvm_bitwise(
input wire [31:0] lhs,
input wire [31:0] rhs,
input wire [2:0] op,
output wire valid,
output wire [31:0] result
);
wire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};
assign valid = op != `RVM_BITWISE_NOP;
assign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |
({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |
({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;
endmodule | module rvm_bitwise(
input wire [31:0] lhs,
input wire [31:0] rhs,
input wire [2:0] op,
output wire valid,
output wire [31:0] result
); |
wire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};
assign valid = op != `RVM_BITWISE_NOP;
assign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |
({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |
({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;
endmodule | 3 |
3,313 | data/full_repos/permissive/103842408/rtl/main/rvm_core.v | 103,842,408 | rvm_core.v | v | 257 | 80 | [] | [] | [] | [(157, 399)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_core.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,061 | module | module rvm_core(
input wire clk,
input wire resetn,
output wire [31:0] mem_addr,
input wire [31:0] mem_rdata,
output wire [31:0] mem_wdata,
output wire mem_c_en,
output wire mem_w_en,
output wire [ 3:0] mem_b_en,
input wire mem_error,
input wire mem_stall
);
wire scu_instr_retired;
wire scu_goto_mtvec ;
wire [ 3:0] f_scu_op ;
wire [31:0] f_scu_result ;
wire [31:0] s_epc ;
wire [31:2] s_mtvec ;
wire [31:0] f_add_lhs ;
wire [31:0] f_add_rhs ;
wire [ 2:0] f_add_op ;
wire f_add_valid ;
wire [31:0] f_add_result;
wire f_add_overflow;
wire [31:0] f_bit_lhs ;
wire [31:0] f_bit_rhs ;
wire [ 1:0] f_bit_op ;
wire f_bit_valid ;
wire [31:0] f_bit_result;
wire [31:0] f_shf_lhs ;
wire [ 4:0] f_shf_rhs ;
wire [ 1:0] f_shf_op ;
wire f_shf_valid ;
wire [31:0] f_shf_result;
wire s_rs1_en ;
wire [4 :0] s_rs1_addr ;
wire [31:0] s_rs1_rdata ;
wire s_rs2_en ;
wire [4 :0] s_rs2_addr ;
wire [31:0] s_rs2_rdata ;
wire d_rd_wen ;
wire [4 :0] d_rd_addr ;
wire [31:0] d_rd_wdata ;
wire d_pc_w_en;
wire [31:0] d_pc_wdata;
wire [31:0] s_pc;
wire ctrl_illegal_instr;
wire ctrl_fdu_mem_valid;
wire [ 4:0] i_rs1_addr ;
wire [ 4:0] i_rs2_addr ;
wire [ 4:0] i_rd_addr ;
wire [31:0] i_immediate ;
wire [ 5:0] i_instr ;
rvm_fdu i_rvm_fdu(
.clk (clk ),
.resetn (resetn ),
.mem_rdata (mem_rdata ),
.mem_valid (ctrl_fdu_mem_valid),
.illegal_instr(ctrl_illegal_instr),
.rs1 (i_rs1_addr ),
.rs2 (i_rs2_addr ),
.dest (i_rd_addr ),
.imm (i_immediate ),
.instr (i_instr )
);
rvm_pcu i_rvm_pcu (
.clk (clk ),
.resetn (resetn ),
.pc_w_en (d_pc_w_en ),
.pc_wdata(d_pc_wdata),
.pc (s_pc )
);
rvm_gprs i_rvm_gprs (
.clk (clk ),
.resetn (resetn ),
.rs1_en (s_rs1_en ),
.rs1_addr (s_rs1_addr ),
.rs1_rdata (s_rs1_rdata),
.rs2_en (s_rs2_en ),
.rs2_addr (s_rs2_addr ),
.rs2_rdata (s_rs2_rdata),
.rd_wen (d_rd_wen ),
.rd_addr (d_rd_addr ),
.rd_wdata (d_rd_wdata )
);
rvm_adder i_rvm_add(
.lhs (f_add_lhs ),
.rhs (f_add_rhs ),
.op (f_add_op ),
.valid (f_add_valid ),
.result(f_add_result),
.overflow(f_add_overflow)
);
rvm_bitwise i_rvm_bitwise(
.lhs (f_bit_lhs ),
.rhs (f_bit_rhs ),
.op (f_bit_op ),
.valid (f_bit_valid ),
.result(f_bit_result)
);
rvm_shift i_rvm_shift(
.lhs (f_shf_lhs ),
.rhs (f_shf_rhs ),
.op (f_shf_op ),
.valid (f_shf_valid ),
.result(f_shf_result)
);
rvm_control i_rvm_control(
.clk (clk ),
.resetn (resetn ),
.f_scu_op (f_scu_op ),
.f_scu_result (f_scu_result ),
.f_scu_mtvec (s_mtvec ),
.f_scu_mepc (s_epc ),
.scu_instr_retired(scu_instr_retired ),
.f_add_lhs (f_add_lhs ),
.f_add_rhs (f_add_rhs ),
.f_add_op (f_add_op ),
.f_add_valid (f_add_valid ),
.f_add_result (f_add_result),
.f_bit_lhs (f_bit_lhs ),
.f_bit_rhs (f_bit_rhs ),
.f_bit_op (f_bit_op ),
.f_bit_valid (f_bit_valid ),
.f_bit_result (f_bit_result),
.f_shf_lhs (f_shf_lhs ),
.f_shf_rhs (f_shf_rhs ),
.f_shf_op (f_shf_op ),
.f_shf_valid (f_shf_valid ),
.f_shf_result (f_shf_result),
.ctrl_illegal_instr(ctrl_illegal_instr),
.ctrl_fdu_mem_valid(ctrl_fdu_mem_valid),
.i_rs1_addr (i_rs1_addr ),
.i_rs2_addr (i_rs2_addr ),
.i_rd_addr (i_rd_addr ),
.i_immediate (i_immediate ),
.i_instr (i_instr ),
.s_rs1_en (s_rs1_en ),
.s_rs1_addr (s_rs1_addr ),
.s_rs1_rdata (s_rs1_rdata ),
.s_rs2_en (s_rs2_en ),
.s_rs2_addr (s_rs2_addr ),
.s_rs2_rdata (s_rs2_rdata ),
.d_rd_wen (d_rd_wen ),
.d_rd_addr (d_rd_addr ),
.d_rd_wdata (d_rd_wdata ),
.d_pc_w_en (d_pc_w_en ),
.d_pc_wdata (d_pc_wdata ),
.s_pc (s_pc ),
.mem_addr (mem_addr ),
.mem_rdata (mem_rdata ),
.mem_wdata (mem_wdata ),
.mem_c_en (mem_c_en ),
.mem_w_en (mem_w_en ),
.mem_b_en (mem_b_en ),
.mem_error (mem_error ),
.mem_stall (mem_stall )
);
rvm_scu i_scu(
.clk (clk),
.resetn (resetn),
.core_stall (1'b0),
.pc (s_pc),
.instr_retired (scu_instr_retired),
.goto_mtvec (scu_goto_mtvec ),
.scu_op (f_scu_op ),
.arg_rs1_addr (i_rs1_addr),
.arg_rs1 (s_rs1_rdata),
.arg_rs2 (s_rs2_rdata),
.arg_imm (i_immediate),
.wb_val (f_scu_result),
.ld_bad_addr (1'b0),
.bad_addr_val (mem_addr),
.trap_msi (1'b0),
.trap_mei (1'b0),
.trap_iaddr_misalign(1'b0),
.trap_iaddr_fault (1'b0),
.trap_illegal_instr (1'b0),
.trap_breakpoint (1'b0),
.trap_laddr_misalign(1'b0),
.trap_laddr_fault (1'b0),
.trap_saddr_misalign(1'b0),
.trap_saddr_fault (1'b0),
.mepc (s_epc),
.mtvec (s_mtvec)
);
endmodule | module rvm_core(
input wire clk,
input wire resetn,
output wire [31:0] mem_addr,
input wire [31:0] mem_rdata,
output wire [31:0] mem_wdata,
output wire mem_c_en,
output wire mem_w_en,
output wire [ 3:0] mem_b_en,
input wire mem_error,
input wire mem_stall
); |
wire scu_instr_retired;
wire scu_goto_mtvec ;
wire [ 3:0] f_scu_op ;
wire [31:0] f_scu_result ;
wire [31:0] s_epc ;
wire [31:2] s_mtvec ;
wire [31:0] f_add_lhs ;
wire [31:0] f_add_rhs ;
wire [ 2:0] f_add_op ;
wire f_add_valid ;
wire [31:0] f_add_result;
wire f_add_overflow;
wire [31:0] f_bit_lhs ;
wire [31:0] f_bit_rhs ;
wire [ 1:0] f_bit_op ;
wire f_bit_valid ;
wire [31:0] f_bit_result;
wire [31:0] f_shf_lhs ;
wire [ 4:0] f_shf_rhs ;
wire [ 1:0] f_shf_op ;
wire f_shf_valid ;
wire [31:0] f_shf_result;
wire s_rs1_en ;
wire [4 :0] s_rs1_addr ;
wire [31:0] s_rs1_rdata ;
wire s_rs2_en ;
wire [4 :0] s_rs2_addr ;
wire [31:0] s_rs2_rdata ;
wire d_rd_wen ;
wire [4 :0] d_rd_addr ;
wire [31:0] d_rd_wdata ;
wire d_pc_w_en;
wire [31:0] d_pc_wdata;
wire [31:0] s_pc;
wire ctrl_illegal_instr;
wire ctrl_fdu_mem_valid;
wire [ 4:0] i_rs1_addr ;
wire [ 4:0] i_rs2_addr ;
wire [ 4:0] i_rd_addr ;
wire [31:0] i_immediate ;
wire [ 5:0] i_instr ;
rvm_fdu i_rvm_fdu(
.clk (clk ),
.resetn (resetn ),
.mem_rdata (mem_rdata ),
.mem_valid (ctrl_fdu_mem_valid),
.illegal_instr(ctrl_illegal_instr),
.rs1 (i_rs1_addr ),
.rs2 (i_rs2_addr ),
.dest (i_rd_addr ),
.imm (i_immediate ),
.instr (i_instr )
);
rvm_pcu i_rvm_pcu (
.clk (clk ),
.resetn (resetn ),
.pc_w_en (d_pc_w_en ),
.pc_wdata(d_pc_wdata),
.pc (s_pc )
);
rvm_gprs i_rvm_gprs (
.clk (clk ),
.resetn (resetn ),
.rs1_en (s_rs1_en ),
.rs1_addr (s_rs1_addr ),
.rs1_rdata (s_rs1_rdata),
.rs2_en (s_rs2_en ),
.rs2_addr (s_rs2_addr ),
.rs2_rdata (s_rs2_rdata),
.rd_wen (d_rd_wen ),
.rd_addr (d_rd_addr ),
.rd_wdata (d_rd_wdata )
);
rvm_adder i_rvm_add(
.lhs (f_add_lhs ),
.rhs (f_add_rhs ),
.op (f_add_op ),
.valid (f_add_valid ),
.result(f_add_result),
.overflow(f_add_overflow)
);
rvm_bitwise i_rvm_bitwise(
.lhs (f_bit_lhs ),
.rhs (f_bit_rhs ),
.op (f_bit_op ),
.valid (f_bit_valid ),
.result(f_bit_result)
);
rvm_shift i_rvm_shift(
.lhs (f_shf_lhs ),
.rhs (f_shf_rhs ),
.op (f_shf_op ),
.valid (f_shf_valid ),
.result(f_shf_result)
);
rvm_control i_rvm_control(
.clk (clk ),
.resetn (resetn ),
.f_scu_op (f_scu_op ),
.f_scu_result (f_scu_result ),
.f_scu_mtvec (s_mtvec ),
.f_scu_mepc (s_epc ),
.scu_instr_retired(scu_instr_retired ),
.f_add_lhs (f_add_lhs ),
.f_add_rhs (f_add_rhs ),
.f_add_op (f_add_op ),
.f_add_valid (f_add_valid ),
.f_add_result (f_add_result),
.f_bit_lhs (f_bit_lhs ),
.f_bit_rhs (f_bit_rhs ),
.f_bit_op (f_bit_op ),
.f_bit_valid (f_bit_valid ),
.f_bit_result (f_bit_result),
.f_shf_lhs (f_shf_lhs ),
.f_shf_rhs (f_shf_rhs ),
.f_shf_op (f_shf_op ),
.f_shf_valid (f_shf_valid ),
.f_shf_result (f_shf_result),
.ctrl_illegal_instr(ctrl_illegal_instr),
.ctrl_fdu_mem_valid(ctrl_fdu_mem_valid),
.i_rs1_addr (i_rs1_addr ),
.i_rs2_addr (i_rs2_addr ),
.i_rd_addr (i_rd_addr ),
.i_immediate (i_immediate ),
.i_instr (i_instr ),
.s_rs1_en (s_rs1_en ),
.s_rs1_addr (s_rs1_addr ),
.s_rs1_rdata (s_rs1_rdata ),
.s_rs2_en (s_rs2_en ),
.s_rs2_addr (s_rs2_addr ),
.s_rs2_rdata (s_rs2_rdata ),
.d_rd_wen (d_rd_wen ),
.d_rd_addr (d_rd_addr ),
.d_rd_wdata (d_rd_wdata ),
.d_pc_w_en (d_pc_w_en ),
.d_pc_wdata (d_pc_wdata ),
.s_pc (s_pc ),
.mem_addr (mem_addr ),
.mem_rdata (mem_rdata ),
.mem_wdata (mem_wdata ),
.mem_c_en (mem_c_en ),
.mem_w_en (mem_w_en ),
.mem_b_en (mem_b_en ),
.mem_error (mem_error ),
.mem_stall (mem_stall )
);
rvm_scu i_scu(
.clk (clk),
.resetn (resetn),
.core_stall (1'b0),
.pc (s_pc),
.instr_retired (scu_instr_retired),
.goto_mtvec (scu_goto_mtvec ),
.scu_op (f_scu_op ),
.arg_rs1_addr (i_rs1_addr),
.arg_rs1 (s_rs1_rdata),
.arg_rs2 (s_rs2_rdata),
.arg_imm (i_immediate),
.wb_val (f_scu_result),
.ld_bad_addr (1'b0),
.bad_addr_val (mem_addr),
.trap_msi (1'b0),
.trap_mei (1'b0),
.trap_iaddr_misalign(1'b0),
.trap_iaddr_fault (1'b0),
.trap_illegal_instr (1'b0),
.trap_breakpoint (1'b0),
.trap_laddr_misalign(1'b0),
.trap_laddr_fault (1'b0),
.trap_saddr_misalign(1'b0),
.trap_saddr_fault (1'b0),
.mepc (s_epc),
.mtvec (s_mtvec)
);
endmodule | 3 |
3,314 | data/full_repos/permissive/103842408/rtl/main/rvm_core_axi4.v | 103,842,408 | rvm_core_axi4.v | v | 168 | 78 | [] | [] | [] | [(157, 311)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_core_axi4.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,062 | module | module rvm_core_axi4(
input ACLK ,
input ARESETn ,
output [31:0] M_AXI_ARADDR,
input M_AXI_ARREADY,
output [ 2:0] M_AXI_ARSIZE,
output M_AXI_ARVALID,
output [31:0] M_AXI_AWADDR,
input M_AXI_AWREADY,
output [ 2:0] M_AXI_AWSIZE,
output M_AXI_AWVALID,
output M_AXI_BREADY,
input [ 1:0] M_AXI_BRESP,
input M_AXI_BVALID,
input [31:0] M_AXI_RDATA,
output M_AXI_RREADY,
input [ 1:0] M_AXI_RRESP,
input M_AXI_RVALID,
output [31:0] M_AXI_WDATA,
input M_AXI_WREADY,
output [ 3:0] M_AXI_WSTRB,
output M_AXI_WVALID
);
wire [31:0] mem_addr;
wire [31:0] mem_rdata;
wire [31:0] mem_wdata;
wire mem_c_en;
wire mem_w_en;
wire [ 3:0] mem_b_en;
wire mem_error;
wire mem_stall;
reg aw_ready;
reg wd_ready;
reg ar_ready;
reg rd_out;
wire n_rd_out;
reg wr_out;
wire n_wr_out;
assign n_rd_out = rd_out && !M_AXI_RVALID || (mem_c_en && !mem_w_en) ;
assign n_wr_out = wr_out && !M_AXI_BVALID || (mem_c_en && mem_w_en) ;
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
rd_out <= 1'b0;
end else begin
rd_out <= n_rd_out;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
wr_out <= 1'b0;
end else begin
wr_out <= n_wr_out;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
ar_ready <= 1'b0;
end else begin
ar_ready <= (ar_ready || M_AXI_ARREADY) && !M_AXI_RVALID;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
aw_ready <= 1'b0;
end else begin
aw_ready <= (aw_ready || M_AXI_AWREADY) && !M_AXI_BVALID;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
wd_ready <= 1'b0;
end else begin
wd_ready <= (wd_ready || M_AXI_WREADY) && !M_AXI_BVALID;
end
end
assign mem_stall = (wr_out && !M_AXI_BVALID) ||
(rd_out && !M_AXI_RVALID) ;
assign mem_error = M_AXI_BVALID && M_AXI_BRESP != 2'b0 ||
M_AXI_RVALID && M_AXI_RRESP != 2'b0 ;
assign M_AXI_BREADY = 1'b1;
assign M_AXI_RREADY = 1'b1;
assign M_AXI_ARADDR = mem_addr;
assign M_AXI_ARSIZE = 3'b010;
assign M_AXI_ARVALID = n_rd_out;
assign mem_rdata = M_AXI_RDATA;
assign M_AXI_AWADDR = mem_addr;
assign M_AXI_AWSIZE = 3'b010;
assign M_AXI_AWVALID = n_wr_out && !aw_ready;
assign M_AXI_WSTRB = mem_b_en;
assign M_AXI_WDATA = mem_wdata;
assign M_AXI_WVALID = n_wr_out && !wd_ready;
rvm_core i_rvm_core(
.clk (ACLK ),
.resetn (ARESETn ),
.mem_addr (mem_addr ),
.mem_rdata (mem_rdata),
.mem_wdata (mem_wdata),
.mem_c_en (mem_c_en ),
.mem_w_en (mem_w_en ),
.mem_b_en (mem_b_en ),
.mem_error (mem_error),
.mem_stall (mem_stall)
);
endmodule | module rvm_core_axi4(
input ACLK ,
input ARESETn ,
output [31:0] M_AXI_ARADDR,
input M_AXI_ARREADY,
output [ 2:0] M_AXI_ARSIZE,
output M_AXI_ARVALID,
output [31:0] M_AXI_AWADDR,
input M_AXI_AWREADY,
output [ 2:0] M_AXI_AWSIZE,
output M_AXI_AWVALID,
output M_AXI_BREADY,
input [ 1:0] M_AXI_BRESP,
input M_AXI_BVALID,
input [31:0] M_AXI_RDATA,
output M_AXI_RREADY,
input [ 1:0] M_AXI_RRESP,
input M_AXI_RVALID,
output [31:0] M_AXI_WDATA,
input M_AXI_WREADY,
output [ 3:0] M_AXI_WSTRB,
output M_AXI_WVALID
); |
wire [31:0] mem_addr;
wire [31:0] mem_rdata;
wire [31:0] mem_wdata;
wire mem_c_en;
wire mem_w_en;
wire [ 3:0] mem_b_en;
wire mem_error;
wire mem_stall;
reg aw_ready;
reg wd_ready;
reg ar_ready;
reg rd_out;
wire n_rd_out;
reg wr_out;
wire n_wr_out;
assign n_rd_out = rd_out && !M_AXI_RVALID || (mem_c_en && !mem_w_en) ;
assign n_wr_out = wr_out && !M_AXI_BVALID || (mem_c_en && mem_w_en) ;
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
rd_out <= 1'b0;
end else begin
rd_out <= n_rd_out;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
wr_out <= 1'b0;
end else begin
wr_out <= n_wr_out;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
ar_ready <= 1'b0;
end else begin
ar_ready <= (ar_ready || M_AXI_ARREADY) && !M_AXI_RVALID;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
aw_ready <= 1'b0;
end else begin
aw_ready <= (aw_ready || M_AXI_AWREADY) && !M_AXI_BVALID;
end
end
always @(posedge ACLK, negedge ARESETn) begin
if(!ARESETn) begin
wd_ready <= 1'b0;
end else begin
wd_ready <= (wd_ready || M_AXI_WREADY) && !M_AXI_BVALID;
end
end
assign mem_stall = (wr_out && !M_AXI_BVALID) ||
(rd_out && !M_AXI_RVALID) ;
assign mem_error = M_AXI_BVALID && M_AXI_BRESP != 2'b0 ||
M_AXI_RVALID && M_AXI_RRESP != 2'b0 ;
assign M_AXI_BREADY = 1'b1;
assign M_AXI_RREADY = 1'b1;
assign M_AXI_ARADDR = mem_addr;
assign M_AXI_ARSIZE = 3'b010;
assign M_AXI_ARVALID = n_rd_out;
assign mem_rdata = M_AXI_RDATA;
assign M_AXI_AWADDR = mem_addr;
assign M_AXI_AWSIZE = 3'b010;
assign M_AXI_AWVALID = n_wr_out && !aw_ready;
assign M_AXI_WSTRB = mem_b_en;
assign M_AXI_WDATA = mem_wdata;
assign M_AXI_WVALID = n_wr_out && !wd_ready;
rvm_core i_rvm_core(
.clk (ACLK ),
.resetn (ARESETn ),
.mem_addr (mem_addr ),
.mem_rdata (mem_rdata),
.mem_wdata (mem_wdata),
.mem_c_en (mem_c_en ),
.mem_w_en (mem_w_en ),
.mem_b_en (mem_b_en ),
.mem_error (mem_error),
.mem_stall (mem_stall)
);
endmodule | 3 |
3,315 | data/full_repos/permissive/103842408/rtl/main/rvm_fdu.v | 103,842,408 | rvm_fdu.v | v | 58 | 72 | [] | [] | [] | [(157, 201)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_fdu.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,063 | module | module rvm_fdu(
input wire clk,
input wire resetn,
input wire [31:0] mem_rdata ,
input wire mem_valid ,
output wire illegal_instr,
output wire [ 4:0] rs1 ,
output wire [ 4:0] rs2 ,
output wire [ 4:0] dest ,
output wire [31:0] imm ,
output wire [ 5:0] instr
);
reg [31:0] fetched_data;
always @(posedge clk, negedge resetn) begin : p_decode_catch_rdata
if(!resetn) begin
fetched_data <= 32'b0;
end else if (mem_valid) begin
fetched_data <= mem_rdata;
end
end
rv32ui_decoder i_rvm_decoder(
.inputword (fetched_data ),
.decode_en (1'b1 ),
.illegal_instr(illegal_instr),
.rs1 (rs1 ),
.rs2 (rs2 ),
.dest (dest ),
.imm (imm ),
.instr (instr )
);
endmodule | module rvm_fdu(
input wire clk,
input wire resetn,
input wire [31:0] mem_rdata ,
input wire mem_valid ,
output wire illegal_instr,
output wire [ 4:0] rs1 ,
output wire [ 4:0] rs2 ,
output wire [ 4:0] dest ,
output wire [31:0] imm ,
output wire [ 5:0] instr
); |
reg [31:0] fetched_data;
always @(posedge clk, negedge resetn) begin : p_decode_catch_rdata
if(!resetn) begin
fetched_data <= 32'b0;
end else if (mem_valid) begin
fetched_data <= mem_rdata;
end
end
rv32ui_decoder i_rvm_decoder(
.inputword (fetched_data ),
.decode_en (1'b1 ),
.illegal_instr(illegal_instr),
.rs1 (rs1 ),
.rs2 (rs2 ),
.dest (dest ),
.imm (imm ),
.instr (instr )
);
endmodule | 3 |
3,317 | data/full_repos/permissive/103842408/rtl/main/rvm_pcu.v | 103,842,408 | rvm_pcu.v | v | 31 | 70 | [] | [] | [] | [(157, 174)] | null | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_pcu.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_pcu.v:24: Define or directive not defined: \'`RVM_PC_POST_RESET\'\n pc <= `RVM_PC_POST_RESET;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_pcu.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pc <= `RVM_PC_POST_RESET;\n ^\n%Error: Exiting due to 3 error(s)\n' | 1,065 | module | module rvm_pcu(
input wire clk,
input wire resetn,
input wire pc_w_en,
input wire [31:0] pc_wdata,
output reg [31:0] pc
);
always @(posedge clk, negedge resetn) begin: p_update_pc
if(!resetn) begin
pc <= `RVM_PC_POST_RESET;
end else if(pc_w_en) begin
pc <= pc_wdata;
end
end
endmodule | module rvm_pcu(
input wire clk,
input wire resetn,
input wire pc_w_en,
input wire [31:0] pc_wdata,
output reg [31:0] pc
); |
always @(posedge clk, negedge resetn) begin: p_update_pc
if(!resetn) begin
pc <= `RVM_PC_POST_RESET;
end else if(pc_w_en) begin
pc <= pc_wdata;
end
end
endmodule | 3 |
3,321 | data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v | 103,842,408 | rvm_core_tb.v | v | 212 | 79 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v\n data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v.v\n data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v.sv\n rvm_constants.v\n rvm_constants.v.v\n rvm_constants.v.sv\n obj_dir/rvm_constants.v\n obj_dir/rvm_constants.v.v\n obj_dir/rvm_constants.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #16 assign resetn = 1\'b1; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #5 assign clk = !clk; \n ^\n%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:86: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("work/waves.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:87: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,rvm_core_tb);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 1,069 | module | module rvm_core_tb();
parameter SRAM_SIZE = 16384;
reg timeout;
integer cycle_count;
integer max_cycle_count;
reg [100*8:0] imem_file;
reg test_finished;
reg test_pass;
reg [31:0] halt_addr;
reg [31:0] pass_addr;
reg [31:0] fail_addr;
reg fail_hit ;
reg clk;
reg resetn =1'b0;
wire clk_req;
wire [31:0] M_AXI_ARADDR;
wire M_AXI_ARREADY;
wire [ 2:0] M_AXI_ARSIZE;
wire M_AXI_ARVALID;
wire [31:0] M_AXI_AWADDR;
wire M_AXI_AWREADY;
wire [ 2:0] M_AXI_AWSIZE;
wire M_AXI_AWVALID;
wire M_AXI_BREADY;
wire [ 1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire [31:0] M_AXI_RDATA;
wire M_AXI_RREADY;
wire [ 1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
wire [31:0] M_AXI_WDATA;
wire M_AXI_WREADY;
wire [ 3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
initial begin
#16 assign resetn = 1'b1;
end
always begin
#5 assign clk = !clk;
end
initial begin
clk = 1'b0;
resetn = 1'b0;
cycle_count = 0;
max_cycle_count = 500;
halt_addr = 32'b0;
if($value$plusargs("IMEM=%s" , imem_file) )begin end
if($value$plusargs("MAX_CYCLE_COUNT=%d" , max_cycle_count) )begin end
if($value$plusargs("HALT_ADDR=%h" , halt_addr) )begin end
if($value$plusargs("PASS_ADDR=%h" , pass_addr) )begin end
if($value$plusargs("FAIL_ADDR=%h" , fail_addr) )begin end
$display("Simulation Parameters: ");
$display("> MAX_CYCLE_COUNT: %d", max_cycle_count);
$display("> IMEM : %s", imem_file);
$display("> Halt Address : %h", halt_addr);
$display("> Pass Address : %h", pass_addr);
$display("> Fail Address : %h", fail_addr);
$dumpfile("work/waves.vcd");
$dumpvars(0,rvm_core_tb);
end
integer i;
always @(posedge clk) begin
cycle_count = cycle_count + 1;
test_finished = 0;
test_pass = 0;
timeout = 0;
fail_hit = 0;
if(M_AXI_ARADDR == halt_addr) begin
test_finished = 1;
test_pass = 0;
timeout = 0;
end else if(M_AXI_ARADDR == pass_addr) begin
test_finished = 1;
test_pass = 1;
timeout = 0;
end else if(M_AXI_ARADDR == fail_addr) begin
test_finished = 1;
test_pass = 0;
fail_hit = 1;
timeout = 0;
end else if(cycle_count > max_cycle_count) begin
$display("Cycle timeout Reached: %d/%d", cycle_count,max_cycle_count);
test_finished = 1;
test_pass = 0;
timeout = 1;
end
if(test_finished) begin
$display("Register file values after %d cycles:", cycle_count);
for (i = 0; i < 32; i = i + 1) begin
$display("\t%d\t: 0x%h", i, `CORE_PATH.i_rvm_gprs.registers[i]);
end
$display("Program Counter: %h", `CORE_PATH.s_pc);
$display("Processor Cycles: %d", cycle_count);
if(test_pass) begin
$display("TEST PASS ");
end else if (timeout) begin
$display("TEST FAIL - TIMEOUT ");
end else if (fail_hit) begin
$display("TEST FAIL - FAIL ADDRESS ");
end else begin
$display("TEST FAIL - UNKNOWN ERROR");
end
$finish(0);
end
end
rvm_core_axi4 i_dut(
.ACLK (clk ) ,
.ARESETn (resetn ) ,
.M_AXI_ARADDR (M_AXI_ARADDR ) ,
.M_AXI_ARREADY (M_AXI_ARREADY ) ,
.M_AXI_ARSIZE (M_AXI_ARSIZE ) ,
.M_AXI_ARVALID (M_AXI_ARVALID ) ,
.M_AXI_AWADDR (M_AXI_AWADDR ) ,
.M_AXI_AWREADY (M_AXI_AWREADY ) ,
.M_AXI_AWSIZE (M_AXI_AWSIZE ) ,
.M_AXI_AWVALID (M_AXI_AWVALID ) ,
.M_AXI_BREADY (M_AXI_BREADY ) ,
.M_AXI_BRESP (M_AXI_BRESP ) ,
.M_AXI_BVALID (M_AXI_BVALID ) ,
.M_AXI_RDATA (M_AXI_RDATA ) ,
.M_AXI_RREADY (M_AXI_RREADY ) ,
.M_AXI_RRESP (M_AXI_RRESP ) ,
.M_AXI_RVALID (M_AXI_RVALID ) ,
.M_AXI_WDATA (M_AXI_WDATA ) ,
.M_AXI_WREADY (M_AXI_WREADY ) ,
.M_AXI_WSTRB (M_AXI_WSTRB ) ,
.M_AXI_WVALID (M_AXI_WVALID )
);
axi_sram #(
.addr_w(32),
.data_w(32),
.size(SRAM_SIZE)
) i_ram(
.memfile (imem_file ),
.ACLK (clk ) ,
.ARESETn (resetn ) ,
.M_AXI_ARADDR (M_AXI_ARADDR ) ,
.M_AXI_ARREADY (M_AXI_ARREADY ) ,
.M_AXI_ARSIZE (M_AXI_ARSIZE ) ,
.M_AXI_ARVALID (M_AXI_ARVALID ) ,
.M_AXI_AWADDR (M_AXI_AWADDR ) ,
.M_AXI_AWREADY (M_AXI_AWREADY ) ,
.M_AXI_AWSIZE (M_AXI_AWSIZE ) ,
.M_AXI_AWVALID (M_AXI_AWVALID ) ,
.M_AXI_BREADY (M_AXI_BREADY ) ,
.M_AXI_BRESP (M_AXI_BRESP ) ,
.M_AXI_BVALID (M_AXI_BVALID ) ,
.M_AXI_RDATA (M_AXI_RDATA ) ,
.M_AXI_RREADY (M_AXI_RREADY ) ,
.M_AXI_RRESP (M_AXI_RRESP ) ,
.M_AXI_RVALID (M_AXI_RVALID ) ,
.M_AXI_WDATA (M_AXI_WDATA ) ,
.M_AXI_WREADY (M_AXI_WREADY ) ,
.M_AXI_WSTRB (M_AXI_WSTRB ) ,
.M_AXI_WVALID (M_AXI_WVALID )
);
endmodule | module rvm_core_tb(); |
parameter SRAM_SIZE = 16384;
reg timeout;
integer cycle_count;
integer max_cycle_count;
reg [100*8:0] imem_file;
reg test_finished;
reg test_pass;
reg [31:0] halt_addr;
reg [31:0] pass_addr;
reg [31:0] fail_addr;
reg fail_hit ;
reg clk;
reg resetn =1'b0;
wire clk_req;
wire [31:0] M_AXI_ARADDR;
wire M_AXI_ARREADY;
wire [ 2:0] M_AXI_ARSIZE;
wire M_AXI_ARVALID;
wire [31:0] M_AXI_AWADDR;
wire M_AXI_AWREADY;
wire [ 2:0] M_AXI_AWSIZE;
wire M_AXI_AWVALID;
wire M_AXI_BREADY;
wire [ 1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire [31:0] M_AXI_RDATA;
wire M_AXI_RREADY;
wire [ 1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
wire [31:0] M_AXI_WDATA;
wire M_AXI_WREADY;
wire [ 3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
initial begin
#16 assign resetn = 1'b1;
end
always begin
#5 assign clk = !clk;
end
initial begin
clk = 1'b0;
resetn = 1'b0;
cycle_count = 0;
max_cycle_count = 500;
halt_addr = 32'b0;
if($value$plusargs("IMEM=%s" , imem_file) )begin end
if($value$plusargs("MAX_CYCLE_COUNT=%d" , max_cycle_count) )begin end
if($value$plusargs("HALT_ADDR=%h" , halt_addr) )begin end
if($value$plusargs("PASS_ADDR=%h" , pass_addr) )begin end
if($value$plusargs("FAIL_ADDR=%h" , fail_addr) )begin end
$display("Simulation Parameters: ");
$display("> MAX_CYCLE_COUNT: %d", max_cycle_count);
$display("> IMEM : %s", imem_file);
$display("> Halt Address : %h", halt_addr);
$display("> Pass Address : %h", pass_addr);
$display("> Fail Address : %h", fail_addr);
$dumpfile("work/waves.vcd");
$dumpvars(0,rvm_core_tb);
end
integer i;
always @(posedge clk) begin
cycle_count = cycle_count + 1;
test_finished = 0;
test_pass = 0;
timeout = 0;
fail_hit = 0;
if(M_AXI_ARADDR == halt_addr) begin
test_finished = 1;
test_pass = 0;
timeout = 0;
end else if(M_AXI_ARADDR == pass_addr) begin
test_finished = 1;
test_pass = 1;
timeout = 0;
end else if(M_AXI_ARADDR == fail_addr) begin
test_finished = 1;
test_pass = 0;
fail_hit = 1;
timeout = 0;
end else if(cycle_count > max_cycle_count) begin
$display("Cycle timeout Reached: %d/%d", cycle_count,max_cycle_count);
test_finished = 1;
test_pass = 0;
timeout = 1;
end
if(test_finished) begin
$display("Register file values after %d cycles:", cycle_count);
for (i = 0; i < 32; i = i + 1) begin
$display("\t%d\t: 0x%h", i, `CORE_PATH.i_rvm_gprs.registers[i]);
end
$display("Program Counter: %h", `CORE_PATH.s_pc);
$display("Processor Cycles: %d", cycle_count);
if(test_pass) begin
$display("TEST PASS ");
end else if (timeout) begin
$display("TEST FAIL - TIMEOUT ");
end else if (fail_hit) begin
$display("TEST FAIL - FAIL ADDRESS ");
end else begin
$display("TEST FAIL - UNKNOWN ERROR");
end
$finish(0);
end
end
rvm_core_axi4 i_dut(
.ACLK (clk ) ,
.ARESETn (resetn ) ,
.M_AXI_ARADDR (M_AXI_ARADDR ) ,
.M_AXI_ARREADY (M_AXI_ARREADY ) ,
.M_AXI_ARSIZE (M_AXI_ARSIZE ) ,
.M_AXI_ARVALID (M_AXI_ARVALID ) ,
.M_AXI_AWADDR (M_AXI_AWADDR ) ,
.M_AXI_AWREADY (M_AXI_AWREADY ) ,
.M_AXI_AWSIZE (M_AXI_AWSIZE ) ,
.M_AXI_AWVALID (M_AXI_AWVALID ) ,
.M_AXI_BREADY (M_AXI_BREADY ) ,
.M_AXI_BRESP (M_AXI_BRESP ) ,
.M_AXI_BVALID (M_AXI_BVALID ) ,
.M_AXI_RDATA (M_AXI_RDATA ) ,
.M_AXI_RREADY (M_AXI_RREADY ) ,
.M_AXI_RRESP (M_AXI_RRESP ) ,
.M_AXI_RVALID (M_AXI_RVALID ) ,
.M_AXI_WDATA (M_AXI_WDATA ) ,
.M_AXI_WREADY (M_AXI_WREADY ) ,
.M_AXI_WSTRB (M_AXI_WSTRB ) ,
.M_AXI_WVALID (M_AXI_WVALID )
);
axi_sram #(
.addr_w(32),
.data_w(32),
.size(SRAM_SIZE)
) i_ram(
.memfile (imem_file ),
.ACLK (clk ) ,
.ARESETn (resetn ) ,
.M_AXI_ARADDR (M_AXI_ARADDR ) ,
.M_AXI_ARREADY (M_AXI_ARREADY ) ,
.M_AXI_ARSIZE (M_AXI_ARSIZE ) ,
.M_AXI_ARVALID (M_AXI_ARVALID ) ,
.M_AXI_AWADDR (M_AXI_AWADDR ) ,
.M_AXI_AWREADY (M_AXI_AWREADY ) ,
.M_AXI_AWSIZE (M_AXI_AWSIZE ) ,
.M_AXI_AWVALID (M_AXI_AWVALID ) ,
.M_AXI_BREADY (M_AXI_BREADY ) ,
.M_AXI_BRESP (M_AXI_BRESP ) ,
.M_AXI_BVALID (M_AXI_BVALID ) ,
.M_AXI_RDATA (M_AXI_RDATA ) ,
.M_AXI_RREADY (M_AXI_RREADY ) ,
.M_AXI_RRESP (M_AXI_RRESP ) ,
.M_AXI_RVALID (M_AXI_RVALID ) ,
.M_AXI_WDATA (M_AXI_WDATA ) ,
.M_AXI_WREADY (M_AXI_WREADY ) ,
.M_AXI_WSTRB (M_AXI_WSTRB ) ,
.M_AXI_WVALID (M_AXI_WVALID )
);
endmodule | 3 |
3,322 | data/full_repos/permissive/103842408/rtl/test/sram.v | 103,842,408 | sram.v | v | 111 | 83 | [] | [] | [] | [(10, 110)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103842408/rtl/test/sram.v:49: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'b_en\' generates 4 bits.\n : ... In instance sram\n if(b_en) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,070 | module | module sram(
input wire [255*8:0] memfile,
input wire gclk,
input wire resetn,
input wire [addr_w-1:0] addr,
output reg [data_w-1:0] rdata,
input wire [data_w-1:0] wdata,
input wire [3:0] b_en,
input wire w_en,
output wire stall,
output reg error
);
parameter addr_w = 32;
parameter data_w = 32;
parameter size = 8192;
wire [addr_w-1:0] addr_idx;
assign addr_idx = addr >> (data_w <= 32? 2 : 3);
integer i;
reg [data_w-1:0] memory [0: size-1];
reg [data_w-1:0] n_output_data;
assign stall = 1'b0;
always @(posedge gclk) begin
error = 1'b0;
if(b_en) begin
if(addr < size) begin
n_output_data = memory[addr_idx];
end else if(resetn) begin
$display("ERROR: Requested read addr %h out of range.", addr);
error = 1'b1;
end
end
end
always @(posedge gclk) begin : do_writes
if(|b_en && w_en == 1'b1) begin
if(addr < size) begin
memory[addr_idx][31:24] = b_en[3] ? wdata[31:24] : memory[addr_idx][31:24];
memory[addr_idx][23:16] = b_en[2] ? wdata[23:16] : memory[addr_idx][23:16];
memory[addr_idx][15: 8] = b_en[1] ? wdata[15: 8] : memory[addr_idx][15: 8];
memory[addr_idx][ 7: 0] = b_en[0] ? wdata[ 7: 0] : memory[addr_idx][ 7: 0];
end else if(resetn) begin
$display("ERROR: Requested write addr %h out of range.", addr);
error = 1'b1;
end
end
end
always @(posedge gclk, negedge resetn) begin
if(resetn == 1'b0) begin
rdata = {data_w{1'b0}};
end else if(|b_en == 1'b1) begin
rdata = n_output_data;
end
end
initial begin
n_output_data = 32'b0;
for(i = 0; i < size; i = i + 1) begin
memory[i] = {data_w{1'bx}};
end
end
always @(posedge resetn) begin
if(memfile != "") begin
$display("In Reset -> Loading memory file: %s", memfile);
$readmemh(memfile, memory, 0, size-1);
end else begin
$display("No memory file specified: Memory will be blank.");
end
end
endmodule | module sram(
input wire [255*8:0] memfile,
input wire gclk,
input wire resetn,
input wire [addr_w-1:0] addr,
output reg [data_w-1:0] rdata,
input wire [data_w-1:0] wdata,
input wire [3:0] b_en,
input wire w_en,
output wire stall,
output reg error
); |
parameter addr_w = 32;
parameter data_w = 32;
parameter size = 8192;
wire [addr_w-1:0] addr_idx;
assign addr_idx = addr >> (data_w <= 32? 2 : 3);
integer i;
reg [data_w-1:0] memory [0: size-1];
reg [data_w-1:0] n_output_data;
assign stall = 1'b0;
always @(posedge gclk) begin
error = 1'b0;
if(b_en) begin
if(addr < size) begin
n_output_data = memory[addr_idx];
end else if(resetn) begin
$display("ERROR: Requested read addr %h out of range.", addr);
error = 1'b1;
end
end
end
always @(posedge gclk) begin : do_writes
if(|b_en && w_en == 1'b1) begin
if(addr < size) begin
memory[addr_idx][31:24] = b_en[3] ? wdata[31:24] : memory[addr_idx][31:24];
memory[addr_idx][23:16] = b_en[2] ? wdata[23:16] : memory[addr_idx][23:16];
memory[addr_idx][15: 8] = b_en[1] ? wdata[15: 8] : memory[addr_idx][15: 8];
memory[addr_idx][ 7: 0] = b_en[0] ? wdata[ 7: 0] : memory[addr_idx][ 7: 0];
end else if(resetn) begin
$display("ERROR: Requested write addr %h out of range.", addr);
error = 1'b1;
end
end
end
always @(posedge gclk, negedge resetn) begin
if(resetn == 1'b0) begin
rdata = {data_w{1'b0}};
end else if(|b_en == 1'b1) begin
rdata = n_output_data;
end
end
initial begin
n_output_data = 32'b0;
for(i = 0; i < size; i = i + 1) begin
memory[i] = {data_w{1'bx}};
end
end
always @(posedge resetn) begin
if(memfile != "") begin
$display("In Reset -> Loading memory file: %s", memfile);
$readmemh(memfile, memory, 0, size-1);
end else begin
$display("No memory file specified: Memory will be blank.");
end
end
endmodule | 3 |
3,323 | data/full_repos/permissive/104053853/digitron.v | 104,053,853 | digitron.v | v | 226 | 57 | [] | [] | [] | [(1, 20), (22, 65), (67, 103), (105, 207), (209, 225)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n ^~~~~~~~~~~\n : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 1,071 | module | module frequency_divider (input clock,
output reg new_clock);
reg [14:0] counter;
initial
begin
counter = 0;
new_clock = 0;
end
always @ (posedge clock)
begin
counter <= counter + 1;
if (counter == 16383)
begin
counter <= 0;
new_clock <= ~new_clock;
end
end
endmodule | module frequency_divider (input clock,
output reg new_clock); |
reg [14:0] counter;
initial
begin
counter = 0;
new_clock = 0;
end
always @ (posedge clock)
begin
counter <= counter + 1;
if (counter == 16383)
begin
counter <= 0;
new_clock <= ~new_clock;
end
end
endmodule | 1 |
3,324 | data/full_repos/permissive/104053853/digitron.v | 104,053,853 | digitron.v | v | 226 | 57 | [] | [] | [] | [(1, 20), (22, 65), (67, 103), (105, 207), (209, 225)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n ^~~~~~~~~~~\n : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 1,071 | module | module hello_printer (input switch,
input clock,
output reg [7:0] seq,
output reg [7:0] an);
parameter character_h = 8'b10010001,
character_e = 8'b01100001,
character_l = 8'b11100011,
character_o = 8'b00000011;
parameter A0 = 8'b11111110,
A1 = 8'b11111101,
A2 = 8'b11111011,
A3 = 8'b11110111,
A4 = 8'b11101111;
reg [2:0] count;
initial
begin
count = 0;
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= character_h; an <= A0; end
1: begin seq <= character_e; an <= A1; end
2: begin seq <= character_l; an <= A2; end
3: begin seq <= character_l; an <= A3; end
4: begin seq <= character_o; an <= A4; end
default: begin seq <= character_h; an <= A0; end
endcase
if (count == 5) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | module hello_printer (input switch,
input clock,
output reg [7:0] seq,
output reg [7:0] an); |
parameter character_h = 8'b10010001,
character_e = 8'b01100001,
character_l = 8'b11100011,
character_o = 8'b00000011;
parameter A0 = 8'b11111110,
A1 = 8'b11111101,
A2 = 8'b11111011,
A3 = 8'b11110111,
A4 = 8'b11101111;
reg [2:0] count;
initial
begin
count = 0;
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= character_h; an <= A0; end
1: begin seq <= character_e; an <= A1; end
2: begin seq <= character_l; an <= A2; end
3: begin seq <= character_l; an <= A3; end
4: begin seq <= character_o; an <= A4; end
default: begin seq <= character_h; an <= A0; end
endcase
if (count == 5) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | 1 |
3,325 | data/full_repos/permissive/104053853/digitron.v | 104,053,853 | digitron.v | v | 226 | 57 | [] | [] | [] | [(1, 20), (22, 65), (67, 103), (105, 207), (209, 225)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n ^~~~~~~~~~~\n : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 1,071 | module | module fin_printer (input switch,
input clock,
output reg [7:0] seq,
output reg [7:0] an);
parameter character_f = 8'b01110001,
character_i = 8'b11011111,
character_n = 8'b11010101;
parameter A5 = 8'b11011111,
A6 = 8'b10111111,
A7 = 8'b01111111;
reg [2:0] count;
initial
begin
count = 0;
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= character_f; an <= A5; end
1: begin seq <= character_i; an <= A6; end
2: begin seq <= character_n; an <= A7; end
default: begin seq <= character_f; an <= A5; end
endcase
if (count == 3) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | module fin_printer (input switch,
input clock,
output reg [7:0] seq,
output reg [7:0] an); |
parameter character_f = 8'b01110001,
character_i = 8'b11011111,
character_n = 8'b11010101;
parameter A5 = 8'b11011111,
A6 = 8'b10111111,
A7 = 8'b01111111;
reg [2:0] count;
initial
begin
count = 0;
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= character_f; an <= A5; end
1: begin seq <= character_i; an <= A6; end
2: begin seq <= character_n; an <= A7; end
default: begin seq <= character_f; an <= A5; end
endcase
if (count == 3) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | 1 |
3,326 | data/full_repos/permissive/104053853/digitron.v | 104,053,853 | digitron.v | v | 226 | 57 | [] | [] | [] | [(1, 20), (22, 65), (67, 103), (105, 207), (209, 225)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n ^~~~~~~~~~~\n : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 1,071 | module | module digit_printer (input switch,
input clock,
input [4:0] val,
output reg [7:0] seq,
output reg [7:0] an);
parameter digit_0 = 8'b00000011,
digit_1 = 8'b10011111,
digit_2 = 8'b00100101,
digit_3 = 8'b00001101,
digit_4 = 8'b10011001,
digit_5 = 8'b01001001,
digit_6 = 8'b01000001,
digit_7 = 8'b00011111,
digit_8 = 8'b00000001,
digit_9 = 8'b00001001,
non_digit = 8'b11111111;
parameter A5 = 8'b11011111,
A6 = 8'b10111111,
A7 = 8'b01111111;
reg [2:0] count;
reg half;
reg [3:0] low_bit;
reg [3:0] high_bit;
reg [7:0] small_digit;
reg [7:0] low_digit;
reg [7:0] high_digit;
initial
begin
count = 0;
end
always @ (val)
begin
low_bit = val[3:0] % 10;
high_bit = val[3:0] / 10;
half = val[4:4];
end
always @ (high_bit)
begin
case (high_bit)
0: high_digit = non_digit;
1: high_digit = digit_1;
2: high_digit = digit_2;
3: high_digit = digit_3;
4: high_digit = digit_4;
5: high_digit = digit_5;
6: high_digit = digit_6;
7: high_digit = digit_7;
8: high_digit = digit_8;
9: high_digit = digit_9;
default: high_digit = non_digit;
endcase
end
always @ (low_bit)
begin
case (low_bit)
0: low_digit = digit_0;
1: low_digit = digit_1;
2: low_digit = digit_2;
3: low_digit = digit_3;
4: low_digit = digit_4;
5: low_digit = digit_5;
6: low_digit = digit_6;
7: low_digit = digit_7;
8: low_digit = digit_8;
9: low_digit = digit_9;
default: low_digit = non_digit;
endcase
low_digit = low_digit & 8'b11111110;
end
always @ (half)
begin
case (half)
0: small_digit <= digit_0;
1: small_digit <= digit_5;
endcase
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= high_digit; an <= A5; end
1: begin seq <= low_digit; an <= A6; end
2: begin seq <= small_digit; an <= A7; end
default: begin seq <= high_digit; an <= A5; end
endcase
if (count == 3) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | module digit_printer (input switch,
input clock,
input [4:0] val,
output reg [7:0] seq,
output reg [7:0] an); |
parameter digit_0 = 8'b00000011,
digit_1 = 8'b10011111,
digit_2 = 8'b00100101,
digit_3 = 8'b00001101,
digit_4 = 8'b10011001,
digit_5 = 8'b01001001,
digit_6 = 8'b01000001,
digit_7 = 8'b00011111,
digit_8 = 8'b00000001,
digit_9 = 8'b00001001,
non_digit = 8'b11111111;
parameter A5 = 8'b11011111,
A6 = 8'b10111111,
A7 = 8'b01111111;
reg [2:0] count;
reg half;
reg [3:0] low_bit;
reg [3:0] high_bit;
reg [7:0] small_digit;
reg [7:0] low_digit;
reg [7:0] high_digit;
initial
begin
count = 0;
end
always @ (val)
begin
low_bit = val[3:0] % 10;
high_bit = val[3:0] / 10;
half = val[4:4];
end
always @ (high_bit)
begin
case (high_bit)
0: high_digit = non_digit;
1: high_digit = digit_1;
2: high_digit = digit_2;
3: high_digit = digit_3;
4: high_digit = digit_4;
5: high_digit = digit_5;
6: high_digit = digit_6;
7: high_digit = digit_7;
8: high_digit = digit_8;
9: high_digit = digit_9;
default: high_digit = non_digit;
endcase
end
always @ (low_bit)
begin
case (low_bit)
0: low_digit = digit_0;
1: low_digit = digit_1;
2: low_digit = digit_2;
3: low_digit = digit_3;
4: low_digit = digit_4;
5: low_digit = digit_5;
6: low_digit = digit_6;
7: low_digit = digit_7;
8: low_digit = digit_8;
9: low_digit = digit_9;
default: low_digit = non_digit;
endcase
low_digit = low_digit & 8'b11111110;
end
always @ (half)
begin
case (half)
0: small_digit <= digit_0;
1: small_digit <= digit_5;
endcase
end
always @ (posedge clock)
begin
if (switch)
begin
case (count)
0: begin seq <= high_digit; an <= A5; end
1: begin seq <= low_digit; an <= A6; end
2: begin seq <= small_digit; an <= A7; end
default: begin seq <= high_digit; an <= A5; end
endcase
if (count == 3) count <= 0; else count <= count + 1;
end
else
begin
seq <= 8'b11111111;
an <= 8'b11111111;
end
end
endmodule | 1 |
3,327 | data/full_repos/permissive/104053853/digitron.v | 104,053,853 | digitron.v | v | 226 | 57 | [] | [] | [] | [(1, 20), (22, 65), (67, 103), (105, 207), (209, 225)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n ^~~~~~~~~~~\n : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n ^~~~~~~~~~~~~\n : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 1,071 | module | module bi_printer (input [7:0] seq1,
input [7:0] an1,
input [7:0] seq2,
input [7:0] an2,
input clock,
output reg [7:0] seq,
output reg [7:0] an);
reg [4:0] count;
always @ (posedge clock)
begin
if (count < 9) begin seq <= seq1; an <= an1; end
else if (count < 18) begin seq <= seq2; an <= an2; end
if (count == 18) count <= 0; else count <= count + 1;
end
endmodule | module bi_printer (input [7:0] seq1,
input [7:0] an1,
input [7:0] seq2,
input [7:0] an2,
input clock,
output reg [7:0] seq,
output reg [7:0] an); |
reg [4:0] count;
always @ (posedge clock)
begin
if (count < 9) begin seq <= seq1; an <= an1; end
else if (count < 18) begin seq <= seq2; an <= an2; end
if (count == 18) count <= 0; else count <= count + 1;
end
endmodule | 1 |
3,328 | data/full_repos/permissive/104053853/vending.v | 104,053,853 | vending.v | v | 275 | 189 | [] | [] | [] | [(1, 64), (66, 91), (93, 103), (105, 239), (241, 274)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104053853/vending.v:164: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance top_module.controller\n if (coin_val != 4\'b0000)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104053853/vending.v:40: Cannot find file containing module: \'frequency_divider\'\nfrequency_divider devider(clock, new_clock);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.v\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/104053853/vending.v:44: Cannot find file containing module: \'hello_printer\'\nhello_printer hello((~hold_ind & reset), new_clock, seq1, an1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:45: Cannot find file containing module: \'digit_printer\'\ndigit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:46: Cannot find file containing module: \'bi_printer\'\nbi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:47: Cannot find file containing module: \'digit_printer\'\ndigit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:48: Cannot find file containing module: \'digit_printer\'\ndigit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:49: Cannot find file containing module: \'fin_printer\'\nfin_printer fin(drinktk_ind, new_clock, seq5, an5);\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 1,072 | module | module top_module (input clock,
input reset,
input op_start,
input goods_mark,
input val_mark,
input coin_confirm,
input cancel_flag,
output reset_led,
output hold_led,
output coin_led,
output drinktk_led,
output charge_led,
output reg [7:0] seq,
output reg [7:0] an);
wire [4:0] coin_val;
wire [4:0] goods_val;
wire [4:0] goods_val_now;
wire hold_ind;
wire coin_ind;
wire drinktk_ind;
wire charge_ind;
wire [4:0] charge_val;
wire new_clock;
wire [7:0] seq1;
wire [7:0] seq2;
wire [7:0] seq3;
wire [7:0] seq4;
wire [7:0] seq5;
wire [7:0] seq2_3;
wire [7:0] an1;
wire [7:0] an2;
wire [7:0] an2_3;
wire [7:0] an3;
wire [7:0] an4;
wire [7:0] an5;
wire drinktk_signal;
wire charge_signal;
frequency_divider devider(clock, new_clock);
main_controller controller(reset, clock, op_start, coin_val, goods_val, cancel_flag, drinktk_signal, charge_signal, hold_ind, coin_ind, drinktk_ind, charge_ind, goods_val_now, charge_val);
coin_inserter inserter(hold_ind, (hold_ind | coin_ind) & (~drinktk_ind) & (~charge_ind) , coin_confirm, val_mark, coin_val);
goods_picker picker(goods_mark, goods_val);
hello_printer hello((~hold_ind & reset), new_clock, seq1, an1);
digit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);
bi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);
digit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);
digit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);
fin_printer fin(drinktk_ind, new_clock, seq5, an5);
delay_timer drinktk_timer(drinktk_ind, clock, drinktk_signal);
delay_timer charge_timer(charge_ind, clock, charge_signal);
assign reset_led = reset;
assign hold_led = hold_ind;
assign coin_led = coin_ind;
assign drinktk_led = drinktk_ind;
assign charge_led = charge_ind;
always @ (*)
begin
seq = ~((~seq1) | (~seq2_3) | (~seq4) | (~seq5));
an = ~((~an1) | (~an2_3) | (~an4) | (~an5));
end
endmodule | module top_module (input clock,
input reset,
input op_start,
input goods_mark,
input val_mark,
input coin_confirm,
input cancel_flag,
output reset_led,
output hold_led,
output coin_led,
output drinktk_led,
output charge_led,
output reg [7:0] seq,
output reg [7:0] an); |
wire [4:0] coin_val;
wire [4:0] goods_val;
wire [4:0] goods_val_now;
wire hold_ind;
wire coin_ind;
wire drinktk_ind;
wire charge_ind;
wire [4:0] charge_val;
wire new_clock;
wire [7:0] seq1;
wire [7:0] seq2;
wire [7:0] seq3;
wire [7:0] seq4;
wire [7:0] seq5;
wire [7:0] seq2_3;
wire [7:0] an1;
wire [7:0] an2;
wire [7:0] an2_3;
wire [7:0] an3;
wire [7:0] an4;
wire [7:0] an5;
wire drinktk_signal;
wire charge_signal;
frequency_divider devider(clock, new_clock);
main_controller controller(reset, clock, op_start, coin_val, goods_val, cancel_flag, drinktk_signal, charge_signal, hold_ind, coin_ind, drinktk_ind, charge_ind, goods_val_now, charge_val);
coin_inserter inserter(hold_ind, (hold_ind | coin_ind) & (~drinktk_ind) & (~charge_ind) , coin_confirm, val_mark, coin_val);
goods_picker picker(goods_mark, goods_val);
hello_printer hello((~hold_ind & reset), new_clock, seq1, an1);
digit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);
bi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);
digit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);
digit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);
fin_printer fin(drinktk_ind, new_clock, seq5, an5);
delay_timer drinktk_timer(drinktk_ind, clock, drinktk_signal);
delay_timer charge_timer(charge_ind, clock, charge_signal);
assign reset_led = reset;
assign hold_led = hold_ind;
assign coin_led = coin_ind;
assign drinktk_led = drinktk_ind;
assign charge_led = charge_ind;
always @ (*)
begin
seq = ~((~seq1) | (~seq2_3) | (~seq4) | (~seq5));
an = ~((~an1) | (~an2_3) | (~an4) | (~an5));
end
endmodule | 1 |
3,329 | data/full_repos/permissive/104053853/vending.v | 104,053,853 | vending.v | v | 275 | 189 | [] | [] | [] | [(1, 64), (66, 91), (93, 103), (105, 239), (241, 274)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104053853/vending.v:164: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance top_module.controller\n if (coin_val != 4\'b0000)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104053853/vending.v:40: Cannot find file containing module: \'frequency_divider\'\nfrequency_divider devider(clock, new_clock);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.v\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/104053853/vending.v:44: Cannot find file containing module: \'hello_printer\'\nhello_printer hello((~hold_ind & reset), new_clock, seq1, an1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:45: Cannot find file containing module: \'digit_printer\'\ndigit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:46: Cannot find file containing module: \'bi_printer\'\nbi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:47: Cannot find file containing module: \'digit_printer\'\ndigit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:48: Cannot find file containing module: \'digit_printer\'\ndigit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:49: Cannot find file containing module: \'fin_printer\'\nfin_printer fin(drinktk_ind, new_clock, seq5, an5);\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 1,072 | module | module coin_inserter (input reset,
input switch,
input coin_confirm,
input val_mark,
output reg [4:0] coin_val);
initial
begin
coin_val = 0;
end
always @ (negedge reset or posedge coin_confirm)
begin
if (!reset) coin_val <= 0;
else
begin
if (switch == 1)
begin
if (val_mark == 0)
coin_val <= coin_val + 1;
else
coin_val <= coin_val + 10;
end
end
end
endmodule | module coin_inserter (input reset,
input switch,
input coin_confirm,
input val_mark,
output reg [4:0] coin_val); |
initial
begin
coin_val = 0;
end
always @ (negedge reset or posedge coin_confirm)
begin
if (!reset) coin_val <= 0;
else
begin
if (switch == 1)
begin
if (val_mark == 0)
coin_val <= coin_val + 1;
else
coin_val <= coin_val + 10;
end
end
end
endmodule | 1 |
3,330 | data/full_repos/permissive/104053853/vending.v | 104,053,853 | vending.v | v | 275 | 189 | [] | [] | [] | [(1, 64), (66, 91), (93, 103), (105, 239), (241, 274)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104053853/vending.v:164: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance top_module.controller\n if (coin_val != 4\'b0000)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104053853/vending.v:40: Cannot find file containing module: \'frequency_divider\'\nfrequency_divider devider(clock, new_clock);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.v\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/104053853/vending.v:44: Cannot find file containing module: \'hello_printer\'\nhello_printer hello((~hold_ind & reset), new_clock, seq1, an1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:45: Cannot find file containing module: \'digit_printer\'\ndigit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:46: Cannot find file containing module: \'bi_printer\'\nbi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:47: Cannot find file containing module: \'digit_printer\'\ndigit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:48: Cannot find file containing module: \'digit_printer\'\ndigit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:49: Cannot find file containing module: \'fin_printer\'\nfin_printer fin(drinktk_ind, new_clock, seq5, an5);\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 1,072 | module | module goods_picker (input goods_mark,
output reg [4:0] goods_val);
always @ (goods_mark)
begin
if (goods_mark == 0)
goods_val = 18;
else
goods_val = 5;
end
endmodule | module goods_picker (input goods_mark,
output reg [4:0] goods_val); |
always @ (goods_mark)
begin
if (goods_mark == 0)
goods_val = 18;
else
goods_val = 5;
end
endmodule | 1 |
3,331 | data/full_repos/permissive/104053853/vending.v | 104,053,853 | vending.v | v | 275 | 189 | [] | [] | [] | [(1, 64), (66, 91), (93, 103), (105, 239), (241, 274)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104053853/vending.v:164: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance top_module.controller\n if (coin_val != 4\'b0000)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104053853/vending.v:40: Cannot find file containing module: \'frequency_divider\'\nfrequency_divider devider(clock, new_clock);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.v\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/104053853/vending.v:44: Cannot find file containing module: \'hello_printer\'\nhello_printer hello((~hold_ind & reset), new_clock, seq1, an1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:45: Cannot find file containing module: \'digit_printer\'\ndigit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:46: Cannot find file containing module: \'bi_printer\'\nbi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:47: Cannot find file containing module: \'digit_printer\'\ndigit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:48: Cannot find file containing module: \'digit_printer\'\ndigit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:49: Cannot find file containing module: \'fin_printer\'\nfin_printer fin(drinktk_ind, new_clock, seq5, an5);\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 1,072 | module | module main_controller (input reset,
input clock,
input op_start,
input [4:0] coin_val,
input [4:0] goods_val,
input cancel_flag,
input drinktk_signal,
input charge_signal,
output reg hold_ind,
output reg coin_ind,
output reg drinktk_ind,
output reg charge_ind,
output reg [4:0] goods_val_now,
output reg [4:0] charge_val);
reg [4:0] current_state, next_state;
reg [31:0] count;
wire delay_signal;
initial
begin
goods_val_now = 0;
count = 0;
end
parameter S0 = 5'b00000,
S1 = 5'b10000,
S2 = 5'b01000,
S3 = 5'b00100,
S4 = 5'b00010,
S5 = 5'b00001;
always @ (posedge clock or negedge reset)
begin
if (!reset)
current_state <= S0;
else
current_state <= next_state;
end
always @ (*)
begin
next_state = S0;
case (current_state)
S0: begin
if (reset == 1)
next_state = S1;
end
S1: begin
if (op_start == 1)
begin
next_state = S2;
goods_val_now = goods_val;
end
else
next_state = S1;
end
S2: begin
if (coin_val != 4'b0000)
next_state = S3;
else if (cancel_flag == 1)
next_state = S5;
else
next_state = S2;
end
S3: begin
if (cancel_flag == 1)
next_state = S5;
else if ((coin_val[3:0] > goods_val_now[3:0]) || ((coin_val[3:0] == goods_val_now[3:0] && (goods_val_now[4:4] == 0))))
next_state = S4;
else
next_state = S3;
end
S4: begin
if (drinktk_signal)
begin
if ((coin_val[3:0] - goods_val_now[3:0] == 4'b0000) && (goods_val_now[4:4] != 1))
next_state = S1;
else
next_state = S5;
end
else
next_state = S4;
end
S5: begin
if (charge_signal)
next_state = S1;
else
next_state = S5;
end
default: begin
next_state = S0;
end
endcase
end
always @ (posedge clock or negedge reset)
begin
if (!reset) begin
hold_ind <= 0;
coin_ind <= 0;
drinktk_ind <= 0;
charge_ind <= 0;
charge_val <= 0;
end
else begin
case (next_state)
S2: begin hold_ind <= 1; end
S3: coin_ind <= 1;
S4: begin drinktk_ind <= 1; coin_ind <= 0; end
S5: begin
drinktk_ind <= 0;
coin_ind <= 0;
charge_ind <= 1;
if (coin_val[3:0] > goods_val_now[3:0])
if (goods_val_now[4:4] == 1)
charge_val = (coin_val[3:0] - goods_val_now[3:0] - 1) | 5'b10000;
else
charge_val = coin_val - goods_val_now;
else
charge_val <= coin_val;
end
default: begin
hold_ind <= 0;
coin_ind <= 0;
drinktk_ind <= 0;
charge_ind <= 0;
charge_val <= 0;
end
endcase
end
end
endmodule | module main_controller (input reset,
input clock,
input op_start,
input [4:0] coin_val,
input [4:0] goods_val,
input cancel_flag,
input drinktk_signal,
input charge_signal,
output reg hold_ind,
output reg coin_ind,
output reg drinktk_ind,
output reg charge_ind,
output reg [4:0] goods_val_now,
output reg [4:0] charge_val); |
reg [4:0] current_state, next_state;
reg [31:0] count;
wire delay_signal;
initial
begin
goods_val_now = 0;
count = 0;
end
parameter S0 = 5'b00000,
S1 = 5'b10000,
S2 = 5'b01000,
S3 = 5'b00100,
S4 = 5'b00010,
S5 = 5'b00001;
always @ (posedge clock or negedge reset)
begin
if (!reset)
current_state <= S0;
else
current_state <= next_state;
end
always @ (*)
begin
next_state = S0;
case (current_state)
S0: begin
if (reset == 1)
next_state = S1;
end
S1: begin
if (op_start == 1)
begin
next_state = S2;
goods_val_now = goods_val;
end
else
next_state = S1;
end
S2: begin
if (coin_val != 4'b0000)
next_state = S3;
else if (cancel_flag == 1)
next_state = S5;
else
next_state = S2;
end
S3: begin
if (cancel_flag == 1)
next_state = S5;
else if ((coin_val[3:0] > goods_val_now[3:0]) || ((coin_val[3:0] == goods_val_now[3:0] && (goods_val_now[4:4] == 0))))
next_state = S4;
else
next_state = S3;
end
S4: begin
if (drinktk_signal)
begin
if ((coin_val[3:0] - goods_val_now[3:0] == 4'b0000) && (goods_val_now[4:4] != 1))
next_state = S1;
else
next_state = S5;
end
else
next_state = S4;
end
S5: begin
if (charge_signal)
next_state = S1;
else
next_state = S5;
end
default: begin
next_state = S0;
end
endcase
end
always @ (posedge clock or negedge reset)
begin
if (!reset) begin
hold_ind <= 0;
coin_ind <= 0;
drinktk_ind <= 0;
charge_ind <= 0;
charge_val <= 0;
end
else begin
case (next_state)
S2: begin hold_ind <= 1; end
S3: coin_ind <= 1;
S4: begin drinktk_ind <= 1; coin_ind <= 0; end
S5: begin
drinktk_ind <= 0;
coin_ind <= 0;
charge_ind <= 1;
if (coin_val[3:0] > goods_val_now[3:0])
if (goods_val_now[4:4] == 1)
charge_val = (coin_val[3:0] - goods_val_now[3:0] - 1) | 5'b10000;
else
charge_val = coin_val - goods_val_now;
else
charge_val <= coin_val;
end
default: begin
hold_ind <= 0;
coin_ind <= 0;
drinktk_ind <= 0;
charge_ind <= 0;
charge_val <= 0;
end
endcase
end
end
endmodule | 1 |
3,332 | data/full_repos/permissive/104053853/vending.v | 104,053,853 | vending.v | v | 275 | 189 | [] | [] | [] | [(1, 64), (66, 91), (93, 103), (105, 239), (241, 274)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104053853/vending.v:164: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance top_module.controller\n if (coin_val != 4\'b0000)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104053853/vending.v:40: Cannot find file containing module: \'frequency_divider\'\nfrequency_divider devider(clock, new_clock);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.v\n data/full_repos/permissive/104053853,data/full_repos/permissive/104053853/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/104053853/vending.v:44: Cannot find file containing module: \'hello_printer\'\nhello_printer hello((~hold_ind & reset), new_clock, seq1, an1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:45: Cannot find file containing module: \'digit_printer\'\ndigit_printer goods(((hold_ind | coin_ind) & (~charge_ind) & (~drinktk_ind)), new_clock, goods_val_now, seq2, an2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:46: Cannot find file containing module: \'bi_printer\'\nbi_printer goods_coin(seq2, (~((~an2) >> 5)), seq3, an3, new_clock, seq2_3, an2_3);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:47: Cannot find file containing module: \'digit_printer\'\ndigit_printer coin(coin_ind, new_clock, coin_val, seq3, an3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:48: Cannot find file containing module: \'digit_printer\'\ndigit_printer charge(charge_ind, new_clock, charge_val, seq4, an4);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104053853/vending.v:49: Cannot find file containing module: \'fin_printer\'\nfin_printer fin(drinktk_ind, new_clock, seq5, an5);\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 1,072 | module | module delay_timer (input start,
input clock,
output reg signal);
reg [31:0] count;
reg wake;
initial
begin
signal = 0;
end
always @ (start)
begin
if (start == 1)
wake = 1;
else
wake = 0;
end
always @ (posedge clock)
begin
if (wake == 1)
begin
signal <= 0;
count <= count + 1;
end
if (count >= 400000000)
begin
signal <= 1;
count <= 0;
end
end
endmodule | module delay_timer (input start,
input clock,
output reg signal); |
reg [31:0] count;
reg wake;
initial
begin
signal = 0;
end
always @ (start)
begin
if (start == 1)
wake = 1;
else
wake = 0;
end
always @ (posedge clock)
begin
if (wake == 1)
begin
signal <= 0;
count <= count + 1;
end
if (count >= 400000000)
begin
signal <= 1;
count <= 0;
end
end
endmodule | 1 |
3,333 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module player
(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
wire [7:0] x;
wire [6:0] y;
wire [2:0] color;
wire clock_out;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
XCounter right(
.clock(KEY[0]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b1),
.x_out(x)
);
XCounter left(
.clock(KEY[3]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b0),
.x_out(x)
);
YCounter down(
.clock(KEY[2]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b1),
.y_out(y)
);
YCounter up(
.clock(KEY[1]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b0),
.y_out(y)
);
playerx sizex(
.clock(CLOCK_50),
.move_enable(KEY[3:0]),
.x_out(x)
);
playery sizey(
.clock(CLOCK_50),
.move_enable(KEY[3:0]),
.y_out(y)
);
bullet b(
.clock(CLOCK_50),
.shoot(SW[9]),
.y_out(y),
.clock_out(clock_out)
);
eraser e1(
.clock(CLOCK_50),
.colour_erase_enable(KEY[3:0]),
.colour(color),
.clock_out(clock_out)
);
vga_adapter VGA(
.resetn(SW[4]),
.clock(CLOCK_50),
.colour(color),
.x(x),
.y(y),
.plot(1'b1),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
endmodule | module player
(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
wire [7:0] x;
wire [6:0] y;
wire [2:0] color;
wire clock_out;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
XCounter right(
.clock(KEY[0]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b1),
.x_out(x)
);
XCounter left(
.clock(KEY[3]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b0),
.x_out(x)
);
YCounter down(
.clock(KEY[2]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b1),
.y_out(y)
);
YCounter up(
.clock(KEY[1]),
.resetn(SW[0]),
.enable(SW[1]),
.increase(1'b0),
.y_out(y)
);
playerx sizex(
.clock(CLOCK_50),
.move_enable(KEY[3:0]),
.x_out(x)
);
playery sizey(
.clock(CLOCK_50),
.move_enable(KEY[3:0]),
.y_out(y)
);
bullet b(
.clock(CLOCK_50),
.shoot(SW[9]),
.y_out(y),
.clock_out(clock_out)
);
eraser e1(
.clock(CLOCK_50),
.colour_erase_enable(KEY[3:0]),
.colour(color),
.clock_out(clock_out)
);
vga_adapter VGA(
.resetn(SW[4]),
.clock(CLOCK_50),
.colour(color),
.x(x),
.y(y),
.plot(1'b1),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
endmodule | 0 |
3,334 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module XCounter (clock, resetn, enable, increase, x_out);
input clock;
input resetn;
input enable;
input increase;
output [7:0] x_out;
reg [7:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 0;
else if (enable == 1'b1)
begin
if (increase == 1'b1)
m <= m + 1'b1;
else
m <= m - 1'b1;
end
end
assign x_out = m;
endmodule | module XCounter (clock, resetn, enable, increase, x_out); |
input clock;
input resetn;
input enable;
input increase;
output [7:0] x_out;
reg [7:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 0;
else if (enable == 1'b1)
begin
if (increase == 1'b1)
m <= m + 1'b1;
else
m <= m - 1'b1;
end
end
assign x_out = m;
endmodule | 0 |
3,335 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module YCounter (clock, resetn, enable, increase, y_out);
input clock;
input resetn;
input enable;
input increase;
output [6:0] y_out;
reg [6:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 7'd60;
else if (enable == 1'b1)
begin
if (increase == 1'b1)
m <= m + 1'b1;
else
m <= m - 1'b1;
end
end
assign y_out = m;
endmodule | module YCounter (clock, resetn, enable, increase, y_out); |
input clock;
input resetn;
input enable;
input increase;
output [6:0] y_out;
reg [6:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 7'd60;
else if (enable == 1'b1)
begin
if (increase == 1'b1)
m <= m + 1'b1;
else
m <= m - 1'b1;
end
end
assign y_out = m;
endmodule | 0 |
3,336 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module playerx (clock, move_enable, x_out);
input clock;
input [3:0] move_enable;
output [7:0] x_out;
reg [7:0] m;
reg [7:0] temp;
always @(posedge clock)
begin
if (move_enable[0] & move_enable[1] & move_enable[2] & move_enable[3])
begin
if (temp == m)
m <= m + 1;
else if (temp == m - 1'b1)
m <= m - 2'b10;
else if(temp == m + 1'b1)
m <= m + 1;
else
m <= temp;
end
else
temp <= m;
end
assign x_out = m;
endmodule | module playerx (clock, move_enable, x_out); |
input clock;
input [3:0] move_enable;
output [7:0] x_out;
reg [7:0] m;
reg [7:0] temp;
always @(posedge clock)
begin
if (move_enable[0] & move_enable[1] & move_enable[2] & move_enable[3])
begin
if (temp == m)
m <= m + 1;
else if (temp == m - 1'b1)
m <= m - 2'b10;
else if(temp == m + 1'b1)
m <= m + 1;
else
m <= temp;
end
else
temp <= m;
end
assign x_out = m;
endmodule | 0 |
3,337 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module playery (clock, move_enable, y_out);
input clock;
input [3:0] move_enable;
output [6:0] y_out;
reg [6:0] m;
reg [6:0] temp;
always @(posedge clock)
begin
if (move_enable[0] & move_enable[1] & move_enable[2] & move_enable[3])
begin
if (temp == m)
m <= m + 1;
else if(temp == m - 1'b1)
m <= m - 1'b1;
else
m <= temp;
end
else
temp <= m;
end
assign y_out = m;
endmodule | module playery (clock, move_enable, y_out); |
input clock;
input [3:0] move_enable;
output [6:0] y_out;
reg [6:0] m;
reg [6:0] temp;
always @(posedge clock)
begin
if (move_enable[0] & move_enable[1] & move_enable[2] & move_enable[3])
begin
if (temp == m)
m <= m + 1;
else if(temp == m - 1'b1)
m <= m - 1'b1;
else
m <= temp;
end
else
temp <= m;
end
assign y_out = m;
endmodule | 0 |
3,338 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module bullet (clock, shoot, y_out, clock_out);
input clock;
input shoot;
output reg clock_out;
output [6:0] y_out;
reg[23:0] counter;
reg [6:0] m;
always @(posedge clock)
begin
if(!shoot)
begin
clock_out <= 1'b0;
counter<=24'd0;
end
else
begin
if(counter==24'd10000000)
begin
counter<=24'd0;
m <= m + 1'b1;
clock_out <= ~clock_out;
end
else
counter<=counter+1'b1;
end
end
assign y_out = m;
endmodule | module bullet (clock, shoot, y_out, clock_out); |
input clock;
input shoot;
output reg clock_out;
output [6:0] y_out;
reg[23:0] counter;
reg [6:0] m;
always @(posedge clock)
begin
if(!shoot)
begin
clock_out <= 1'b0;
counter<=24'd0;
end
else
begin
if(counter==24'd10000000)
begin
counter<=24'd0;
m <= m + 1'b1;
clock_out <= ~clock_out;
end
else
counter<=counter+1'b1;
end
end
assign y_out = m;
endmodule | 0 |
3,339 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module DelayCounter (clock, resetn, enable, delay_out);
input clock;
input resetn;
input enable;
output [19:0] delay_out;
reg [19:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 0;
else if (enable == 1'b1)
begin
if (m == 20'd833400)
m <= 0;
else
m <= m + 1'b1;
end
end
assign delay_out = m;
endmodule | module DelayCounter (clock, resetn, enable, delay_out); |
input clock;
input resetn;
input enable;
output [19:0] delay_out;
reg [19:0] m;
always @(posedge clock)
begin
if (resetn == 1'b0)
m <= 0;
else if (enable == 1'b1)
begin
if (m == 20'd833400)
m <= 0;
else
m <= m + 1'b1;
end
end
assign delay_out = m;
endmodule | 0 |
3,340 | data/full_repos/permissive/104147155/player.v | 104,147,155 | player.v | v | 287 | 104 | [] | [] | [] | null | line:110: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'player\'\nmodule player\n ^~~~~~\n : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance player.sizex\n m <= m - 2\'b10;\n ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,073 | module | module eraser(clock,colour_erase_enable, colour, clock_out);
input clock;
input clock_out;
input [3:0] colour_erase_enable;
output reg [2:0] colour;
always @(posedge clock)
begin
if (colour_erase_enable[0] & colour_erase_enable[1] & colour_erase_enable[2] & colour_erase_enable[3])
colour = 3'b011;
else
colour = 3'b000;
end
endmodule | module eraser(clock,colour_erase_enable, colour, clock_out); |
input clock;
input clock_out;
input [3:0] colour_erase_enable;
output reg [2:0] colour;
always @(posedge clock)
begin
if (colour_erase_enable[0] & colour_erase_enable[1] & colour_erase_enable[2] & colour_erase_enable[3])
colour = 3'b011;
else
colour = 3'b000;
end
endmodule | 0 |
3,341 | data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v | 104,147,155 | vga_address_translator.v | v | 36 | 107 | [] | [] | [] | [(4, 35)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:25: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 15 bits.\n : ... In instance vga_address_translator\n wire [16:0] res_320x240 = ({1\'b0, y, 8\'d0} + {1\'b0, y, 6\'d0} + {1\'b0, x});\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:25: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 10 bits.\n : ... In instance vga_address_translator\n wire [16:0] res_320x240 = ({1\'b0, y, 8\'d0} + {1\'b0, y, 6\'d0} + {1\'b0, x});\n ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:26: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n : ... In instance vga_address_translator\n wire [15:0] res_160x120 = ({1\'b0, y, 7\'d0} + {1\'b0, y, 5\'d0} + {1\'b0, x});\n ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:26: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 10 bits.\n : ... In instance vga_address_translator\n wire [15:0] res_160x120 = ({1\'b0, y, 7\'d0} + {1\'b0, y, 5\'d0} + {1\'b0, x});\n ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:33: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n : ... In instance vga_address_translator\n mem_address = res_160x120[14:0];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 1,075 | module | module vga_address_translator(x, y, mem_address);
parameter RESOLUTION = "320x240";
input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address;
wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x});
wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x});
always @(*)
begin
if (RESOLUTION == "320x240")
mem_address = res_320x240;
else
mem_address = res_160x120[14:0];
end
endmodule | module vga_address_translator(x, y, mem_address); |
parameter RESOLUTION = "320x240";
input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address;
wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x});
wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x});
always @(*)
begin
if (RESOLUTION == "320x240")
mem_address = res_320x240;
else
mem_address = res_160x120[14:0];
end
endmodule | 0 |
3,342 | data/full_repos/permissive/104147155/vga_adapter/vga_controller.v | 104,147,155 | vga_controller.v | v | 199 | 107 | [] | [] | [] | null | line:135: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_controller.v:127: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance vga_controller\n x = xCounter[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_controller.v:128: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n : ... In instance vga_controller\n y = yCounter[8:2];\n ^\n%Error: data/full_repos/permissive/104147155/vga_adapter/vga_controller.v:133: Cannot find file containing module: \'vga_address_translator\'\n vga_address_translator controller_translator(\n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104147155/vga_adapter,data/full_repos/permissive/104147155/vga_address_translator\n data/full_repos/permissive/104147155/vga_adapter,data/full_repos/permissive/104147155/vga_address_translator.v\n data/full_repos/permissive/104147155/vga_adapter,data/full_repos/permissive/104147155/vga_address_translator.sv\n vga_address_translator\n vga_address_translator.v\n vga_address_translator.sv\n obj_dir/vga_address_translator\n obj_dir/vga_address_translator.v\n obj_dir/vga_address_translator.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,076 | module | module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK);
parameter BITS_PER_COLOUR_CHANNEL = 1;
parameter MONOCHROME = "FALSE";
parameter RESOLUTION = "320x240";
parameter C_VERT_NUM_PIXELS = 10'd480;
parameter C_VERT_SYNC_START = 10'd493;
parameter C_VERT_SYNC_END = 10'd494;
parameter C_VERT_TOTAL_COUNT = 10'd525;
parameter C_HORZ_NUM_PIXELS = 10'd640;
parameter C_HORZ_SYNC_START = 10'd659;
parameter C_HORZ_SYNC_END = 10'd754;
parameter C_HORZ_TOTAL_COUNT = 10'd800;
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
assign vcc =1'b1;
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear)
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
always @(posedge vga_clock)
begin
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
assign VGA_SYNC = vcc;
assign VGA_CLK = vga_clock;
integer index;
integer sub_index;
always @(pixel_colour)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= pixel_colour[0:0];
VGA_G[index] <= pixel_colour[0:0];
VGA_B[index] <= pixel_colour[0:0];
end
end
end
endmodule | module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK); |
parameter BITS_PER_COLOUR_CHANNEL = 1;
parameter MONOCHROME = "FALSE";
parameter RESOLUTION = "320x240";
parameter C_VERT_NUM_PIXELS = 10'd480;
parameter C_VERT_SYNC_START = 10'd493;
parameter C_VERT_SYNC_END = 10'd494;
parameter C_VERT_TOTAL_COUNT = 10'd525;
parameter C_HORZ_NUM_PIXELS = 10'd640;
parameter C_HORZ_SYNC_START = 10'd659;
parameter C_HORZ_SYNC_END = 10'd754;
parameter C_HORZ_TOTAL_COUNT = 10'd800;
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
assign vcc =1'b1;
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear)
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
always @(posedge vga_clock)
begin
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
assign VGA_SYNC = vcc;
assign VGA_CLK = vga_clock;
integer index;
integer sub_index;
always @(pixel_colour)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= pixel_colour[0:0];
VGA_G[index] <= pixel_colour[0:0];
VGA_B[index] <= pixel_colour[0:0];
end
end
end
endmodule | 0 |
3,343 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module ALU_ctrl(input [63:0] A,
input [63:0] B,
input [3:0] cmd,
output [31:0] psw,
output reg [63:0] Data_out);
wire [63:0] Data_out6;
wire [63:0] Data_out7;
wire [63:0] Data_out8;
shift_L_register alu7(.data_in(A), .shamt(B), .data_out(Data_out6));
shift_R_register alu8(.data_in(A), .shamt(B), .data_out(Data_out7));
shift_RA_register alu9(.data_in(A), .shamt(B), .data_out(Data_out8));
always @ (*)
begin
case (cmd)
`ADD:
Data_out = A + B;
`SUB:
Data_out = A - B;
`AND:
Data_out = A & B;
`OR:
Data_out = A | B;
`NOT:
Data_out = ~A;
`SHIFT_L:
Data_out = Data_out6;
`SHIFT_R:
Data_out = Data_out7;
`SHIFT_RA:
Data_out = Data_out8;
default:
Data_out = 64'h0;
endcase
end
endmodule | module ALU_ctrl(input [63:0] A,
input [63:0] B,
input [3:0] cmd,
output [31:0] psw,
output reg [63:0] Data_out); |
wire [63:0] Data_out6;
wire [63:0] Data_out7;
wire [63:0] Data_out8;
shift_L_register alu7(.data_in(A), .shamt(B), .data_out(Data_out6));
shift_R_register alu8(.data_in(A), .shamt(B), .data_out(Data_out7));
shift_RA_register alu9(.data_in(A), .shamt(B), .data_out(Data_out8));
always @ (*)
begin
case (cmd)
`ADD:
Data_out = A + B;
`SUB:
Data_out = A - B;
`AND:
Data_out = A & B;
`OR:
Data_out = A | B;
`NOT:
Data_out = ~A;
`SHIFT_L:
Data_out = Data_out6;
`SHIFT_R:
Data_out = Data_out7;
`SHIFT_RA:
Data_out = Data_out8;
default:
Data_out = 64'h0;
endcase
end
endmodule | 0 |
3,344 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module one_bit_add_Sub (input A,
input B,
input Cin,
input b_invert,
output Cout,
output Sum);
wire Bin;
assign Bin = b_invert ^ B;
xor(Sum, A, Cin, Bin);
and(w1, A, Bin);
and(w2, A, Cin);
and(w3, Bin, Cin);
or(Cout, w1, w2, w3);
endmodule | module one_bit_add_Sub (input A,
input B,
input Cin,
input b_invert,
output Cout,
output Sum); |
wire Bin;
assign Bin = b_invert ^ B;
xor(Sum, A, Cin, Bin);
and(w1, A, Bin);
and(w2, A, Cin);
and(w3, Bin, Cin);
or(Cout, w1, w2, w3);
endmodule | 0 |
3,345 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module add_sub_64bit(input [63:0] A,
input [63:0] B,
input Cin,
input add_sub,
output Cout,
output [63:0] Sum);
wire [62:0] carry_prop;
wire carry_out;
wire carry;
assign carry = add_sub ? 1 : Cin;
one_bit_add_Sub A0( .A(A[0]), .B(B[0]), .Cin(carry), .b_invert(add_sub), .Cout(carry_prop[0]), .Sum(Sum[0]));
genvar i;
generate
for (i=1; i<=62; i=i+1)
begin: adder
one_bit_add_Sub A1( .A(A[i]), .B(B[i]), .Cin(carry_prop[i-1]), .b_invert(add_sub), .Cout(carry_prop[i]), .Sum(Sum[i]));
end
endgenerate
one_bit_add_Sub A2( .A(A[63]), .B(B[63]), .Cin(carry_prop[62]), .b_invert(add_sub), .Cout(carry_out), .Sum(Sum[63]));
assign Cout = add_sub ? ~carry_out : carry_out;
endmodule | module add_sub_64bit(input [63:0] A,
input [63:0] B,
input Cin,
input add_sub,
output Cout,
output [63:0] Sum); |
wire [62:0] carry_prop;
wire carry_out;
wire carry;
assign carry = add_sub ? 1 : Cin;
one_bit_add_Sub A0( .A(A[0]), .B(B[0]), .Cin(carry), .b_invert(add_sub), .Cout(carry_prop[0]), .Sum(Sum[0]));
genvar i;
generate
for (i=1; i<=62; i=i+1)
begin: adder
one_bit_add_Sub A1( .A(A[i]), .B(B[i]), .Cin(carry_prop[i-1]), .b_invert(add_sub), .Cout(carry_prop[i]), .Sum(Sum[i]));
end
endgenerate
one_bit_add_Sub A2( .A(A[63]), .B(B[63]), .Cin(carry_prop[62]), .b_invert(add_sub), .Cout(carry_out), .Sum(Sum[63]));
assign Cout = add_sub ? ~carry_out : carry_out;
endmodule | 0 |
3,346 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module shift_L_register (data_in,shamt,data_out);
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {data_in[WIDTH-2:0],1'h0};
'h2: data_out = {data_in[WIDTH-3:0],2'h0};
'h3: data_out = {data_in[WIDTH-4:0],3'h0};
'h4: data_out = {data_in[WIDTH-5:0],4'h0};
'h5: data_out = {data_in[WIDTH-6:0],5'h0};
'h6: data_out = {data_in[WIDTH-7:0],6'h0};
'h7: data_out = {data_in[WIDTH-8:0],7'h0};
'h8: data_out = {data_in[WIDTH-9:0],8'h0};
'h9: data_out = {data_in[WIDTH-10:0],9'h0};
'hA: data_out = {data_in[WIDTH-11:0],10'h0};
'hB: data_out = {data_in[WIDTH-12:0],11'h0};
'hC: data_out = {data_in[WIDTH-13:0],12'h0};
'hD: data_out = {data_in[WIDTH-14:0],13'h0};
'hE: data_out = {data_in[WIDTH-15:0],14'h0};
'hF: data_out = {data_in[WIDTH-16:0],15'h0};
'h10: data_out = {data_in[WIDTH-17:0],16'h0};
'h11: data_out = {data_in[WIDTH-18:0],17'h0};
'h12: data_out = {data_in[WIDTH-19:0],18'h0};
'h13: data_out = {data_in[WIDTH-20:0],19'h0};
'h14: data_out = {data_in[WIDTH-21:0],20'h0};
'h15: data_out = {data_in[WIDTH-22:0],21'h0};
'h16: data_out = {data_in[WIDTH-23:0],22'h0};
'h17: data_out = {data_in[WIDTH-24:0],23'h0};
'h18: data_out = {data_in[WIDTH-25:0],24'h0};
'h19: data_out = {data_in[WIDTH-26:0],25'h0};
'h1A: data_out = {data_in[WIDTH-27:0],26'h0};
'h1B: data_out = {data_in[WIDTH-28:0],27'h0};
'h1C: data_out = {data_in[WIDTH-29:0],28'h0};
'h1D: data_out = {data_in[WIDTH-30:0],29'h0};
'h1E: data_out = {data_in[WIDTH-31:0],30'h0};
'h1F: data_out = {data_in[WIDTH-32:0],31'h0};
'h20: data_out = {data_in[WIDTH-33:0],32'h0};
'h21: data_out = {data_in[WIDTH-34:0],33'h0};
'h22: data_out = {data_in[WIDTH-35:0],34'h0};
'h23: data_out = {data_in[WIDTH-17:0],35'h0};
'h24: data_out = {data_in[WIDTH-18:0],36'h0};
'h25: data_out = {data_in[WIDTH-19:0],37'h0};
'h26: data_out = {data_in[WIDTH-20:0],38'h0};
'h27: data_out = {data_in[WIDTH-21:0],39'h0};
'h28: data_out = {data_in[WIDTH-22:0],40'h0};
'h29: data_out = {data_in[WIDTH-23:0],41'h0};
'h2A: data_out = {data_in[WIDTH-24:0],42'h0};
'h2B: data_out = {data_in[WIDTH-25:0],43'h0};
'h2C: data_out = {data_in[WIDTH-26:0],44'h0};
'h2D: data_out = {data_in[WIDTH-27:0],45'h0};
'h2E: data_out = {data_in[WIDTH-28:0],46'h0};
'h2F: data_out = {data_in[WIDTH-29:0],47'h0};
'h30: data_out = {data_in[WIDTH-30:0],48'h0};
default: data_out = data_in;
endcase
end
endmodule | module shift_L_register (data_in,shamt,data_out); |
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {data_in[WIDTH-2:0],1'h0};
'h2: data_out = {data_in[WIDTH-3:0],2'h0};
'h3: data_out = {data_in[WIDTH-4:0],3'h0};
'h4: data_out = {data_in[WIDTH-5:0],4'h0};
'h5: data_out = {data_in[WIDTH-6:0],5'h0};
'h6: data_out = {data_in[WIDTH-7:0],6'h0};
'h7: data_out = {data_in[WIDTH-8:0],7'h0};
'h8: data_out = {data_in[WIDTH-9:0],8'h0};
'h9: data_out = {data_in[WIDTH-10:0],9'h0};
'hA: data_out = {data_in[WIDTH-11:0],10'h0};
'hB: data_out = {data_in[WIDTH-12:0],11'h0};
'hC: data_out = {data_in[WIDTH-13:0],12'h0};
'hD: data_out = {data_in[WIDTH-14:0],13'h0};
'hE: data_out = {data_in[WIDTH-15:0],14'h0};
'hF: data_out = {data_in[WIDTH-16:0],15'h0};
'h10: data_out = {data_in[WIDTH-17:0],16'h0};
'h11: data_out = {data_in[WIDTH-18:0],17'h0};
'h12: data_out = {data_in[WIDTH-19:0],18'h0};
'h13: data_out = {data_in[WIDTH-20:0],19'h0};
'h14: data_out = {data_in[WIDTH-21:0],20'h0};
'h15: data_out = {data_in[WIDTH-22:0],21'h0};
'h16: data_out = {data_in[WIDTH-23:0],22'h0};
'h17: data_out = {data_in[WIDTH-24:0],23'h0};
'h18: data_out = {data_in[WIDTH-25:0],24'h0};
'h19: data_out = {data_in[WIDTH-26:0],25'h0};
'h1A: data_out = {data_in[WIDTH-27:0],26'h0};
'h1B: data_out = {data_in[WIDTH-28:0],27'h0};
'h1C: data_out = {data_in[WIDTH-29:0],28'h0};
'h1D: data_out = {data_in[WIDTH-30:0],29'h0};
'h1E: data_out = {data_in[WIDTH-31:0],30'h0};
'h1F: data_out = {data_in[WIDTH-32:0],31'h0};
'h20: data_out = {data_in[WIDTH-33:0],32'h0};
'h21: data_out = {data_in[WIDTH-34:0],33'h0};
'h22: data_out = {data_in[WIDTH-35:0],34'h0};
'h23: data_out = {data_in[WIDTH-17:0],35'h0};
'h24: data_out = {data_in[WIDTH-18:0],36'h0};
'h25: data_out = {data_in[WIDTH-19:0],37'h0};
'h26: data_out = {data_in[WIDTH-20:0],38'h0};
'h27: data_out = {data_in[WIDTH-21:0],39'h0};
'h28: data_out = {data_in[WIDTH-22:0],40'h0};
'h29: data_out = {data_in[WIDTH-23:0],41'h0};
'h2A: data_out = {data_in[WIDTH-24:0],42'h0};
'h2B: data_out = {data_in[WIDTH-25:0],43'h0};
'h2C: data_out = {data_in[WIDTH-26:0],44'h0};
'h2D: data_out = {data_in[WIDTH-27:0],45'h0};
'h2E: data_out = {data_in[WIDTH-28:0],46'h0};
'h2F: data_out = {data_in[WIDTH-29:0],47'h0};
'h30: data_out = {data_in[WIDTH-30:0],48'h0};
default: data_out = data_in;
endcase
end
endmodule | 0 |
3,347 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module shift_R_register (data_in,shamt,data_out);
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {1'h0,data_in[WIDTH-1:1]};
'h2: data_out = {2'h0,data_in[WIDTH-1:2]};
'h3: data_out = {3'h0,data_in[WIDTH-1:3]};
'h4: data_out = {4'h0,data_in[WIDTH-1:4]};
'h5: data_out = {5'h0,data_in[WIDTH-1:5]};
'h6: data_out = {6'h0,data_in[WIDTH-1:6]};
'h7: data_out = {7'h0,data_in[WIDTH-1:7]};
'h8: data_out = {8'h0,data_in[WIDTH-1:8]};
'h9: data_out = {9'h0,data_in[WIDTH-1:9]};
'hA: data_out = {10'h0,data_in[WIDTH-1:10]};
'hB: data_out = {11'h0,data_in[WIDTH-1:11]};
'hC: data_out = {12'h0,data_in[WIDTH-1:12]};
'hD: data_out = {13'h0,data_in[WIDTH-1:13]};
'hE: data_out = {14'h0,data_in[WIDTH-1:14]};
'hF: data_out = {15'h0,data_in[WIDTH-1:15]};
'h10: data_out = {16'h0,data_in[WIDTH-1:16]};
'h11: data_out = {17'h0,data_in[WIDTH-1:17]};
'h12: data_out = {18'h0,data_in[WIDTH-1:18]};
'h13: data_out = {19'h0,data_in[WIDTH-1:19]};
'h14: data_out = {20'h0,data_in[WIDTH-1:20]};
'h15: data_out = {21'h0,data_in[WIDTH-1:21]};
'h16: data_out = {22'h0,data_in[WIDTH-1:22]};
'h17: data_out = {23'h0,data_in[WIDTH-1:23]};
'h18: data_out = {24'h0,data_in[WIDTH-1:24]};
'h19: data_out = {25'h0,data_in[WIDTH-1:25]};
'h1A: data_out = {26'h0,data_in[WIDTH-1:26]};
'h1B: data_out = {27'h0,data_in[WIDTH-1:27]};
'h1C: data_out = {28'h0,data_in[WIDTH-1:28]};
'h1D: data_out = {29'h0,data_in[WIDTH-1:29]};
'h1E: data_out = {30'h0,data_in[WIDTH-1:30]};
'h1F: data_out = {31'h0,data_in[WIDTH-1:31]};
'h20: data_out = {32'h0,data_in[WIDTH-1:32]};
'h21: data_out = {33'h0,data_in[WIDTH-1:33]};
'h22: data_out = {34'h0,data_in[WIDTH-1:34]};
'h23: data_out = {35'h0,data_in[WIDTH-1:35]};
'h24: data_out = {36'h0,data_in[WIDTH-1:36]};
'h25: data_out = {37'h0,data_in[WIDTH-1:37]};
'h26: data_out = {38'h0,data_in[WIDTH-1:38]};
'h27: data_out = {39'h0,data_in[WIDTH-1:39]};
'h28: data_out = {40'h0,data_in[WIDTH-1:40]};
'h29: data_out = {41'h0,data_in[WIDTH-1:41]};
'h2A: data_out = {42'h0,data_in[WIDTH-1:42]};
'h2B: data_out = {43'h0,data_in[WIDTH-1:43]};
'h2C: data_out = {44'h0,data_in[WIDTH-1:44]};
'h2D: data_out = {45'h0,data_in[WIDTH-1:45]};
'h2E: data_out = {46'h0,data_in[WIDTH-1:46]};
'h2F: data_out = {47'h0,data_in[WIDTH-1:47]};
'h30: data_out = {48'h0,data_in[WIDTH-1:48]};
default: data_out = data_in;
endcase
end
endmodule | module shift_R_register (data_in,shamt,data_out); |
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {1'h0,data_in[WIDTH-1:1]};
'h2: data_out = {2'h0,data_in[WIDTH-1:2]};
'h3: data_out = {3'h0,data_in[WIDTH-1:3]};
'h4: data_out = {4'h0,data_in[WIDTH-1:4]};
'h5: data_out = {5'h0,data_in[WIDTH-1:5]};
'h6: data_out = {6'h0,data_in[WIDTH-1:6]};
'h7: data_out = {7'h0,data_in[WIDTH-1:7]};
'h8: data_out = {8'h0,data_in[WIDTH-1:8]};
'h9: data_out = {9'h0,data_in[WIDTH-1:9]};
'hA: data_out = {10'h0,data_in[WIDTH-1:10]};
'hB: data_out = {11'h0,data_in[WIDTH-1:11]};
'hC: data_out = {12'h0,data_in[WIDTH-1:12]};
'hD: data_out = {13'h0,data_in[WIDTH-1:13]};
'hE: data_out = {14'h0,data_in[WIDTH-1:14]};
'hF: data_out = {15'h0,data_in[WIDTH-1:15]};
'h10: data_out = {16'h0,data_in[WIDTH-1:16]};
'h11: data_out = {17'h0,data_in[WIDTH-1:17]};
'h12: data_out = {18'h0,data_in[WIDTH-1:18]};
'h13: data_out = {19'h0,data_in[WIDTH-1:19]};
'h14: data_out = {20'h0,data_in[WIDTH-1:20]};
'h15: data_out = {21'h0,data_in[WIDTH-1:21]};
'h16: data_out = {22'h0,data_in[WIDTH-1:22]};
'h17: data_out = {23'h0,data_in[WIDTH-1:23]};
'h18: data_out = {24'h0,data_in[WIDTH-1:24]};
'h19: data_out = {25'h0,data_in[WIDTH-1:25]};
'h1A: data_out = {26'h0,data_in[WIDTH-1:26]};
'h1B: data_out = {27'h0,data_in[WIDTH-1:27]};
'h1C: data_out = {28'h0,data_in[WIDTH-1:28]};
'h1D: data_out = {29'h0,data_in[WIDTH-1:29]};
'h1E: data_out = {30'h0,data_in[WIDTH-1:30]};
'h1F: data_out = {31'h0,data_in[WIDTH-1:31]};
'h20: data_out = {32'h0,data_in[WIDTH-1:32]};
'h21: data_out = {33'h0,data_in[WIDTH-1:33]};
'h22: data_out = {34'h0,data_in[WIDTH-1:34]};
'h23: data_out = {35'h0,data_in[WIDTH-1:35]};
'h24: data_out = {36'h0,data_in[WIDTH-1:36]};
'h25: data_out = {37'h0,data_in[WIDTH-1:37]};
'h26: data_out = {38'h0,data_in[WIDTH-1:38]};
'h27: data_out = {39'h0,data_in[WIDTH-1:39]};
'h28: data_out = {40'h0,data_in[WIDTH-1:40]};
'h29: data_out = {41'h0,data_in[WIDTH-1:41]};
'h2A: data_out = {42'h0,data_in[WIDTH-1:42]};
'h2B: data_out = {43'h0,data_in[WIDTH-1:43]};
'h2C: data_out = {44'h0,data_in[WIDTH-1:44]};
'h2D: data_out = {45'h0,data_in[WIDTH-1:45]};
'h2E: data_out = {46'h0,data_in[WIDTH-1:46]};
'h2F: data_out = {47'h0,data_in[WIDTH-1:47]};
'h30: data_out = {48'h0,data_in[WIDTH-1:48]};
default: data_out = data_in;
endcase
end
endmodule | 0 |
3,348 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module shift_RA_register (data_in,shamt,data_out);
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {{data_in[WIDTH-1]},data_in[WIDTH-1:1]};
'h2: data_out = {{2{data_in[WIDTH-1]}},data_in[WIDTH-1:2]};
'h3: data_out = {{3{data_in[WIDTH-1]}},data_in[WIDTH-1:3]};
'h4: data_out = {{4{data_in[WIDTH-1]}},data_in[WIDTH-1:4]};
'h5: data_out = {{5{data_in[WIDTH-1]}},data_in[WIDTH-1:5]};
'h6: data_out = {{6{data_in[WIDTH-1]}},data_in[WIDTH-1:6]};
'h7: data_out = {{7{data_in[WIDTH-1]}},data_in[WIDTH-1:7]};
'h8: data_out = {{8{data_in[WIDTH-1]}},data_in[WIDTH-1:8]};
'h9: data_out = {{9{data_in[WIDTH-1]}},data_in[WIDTH-1:9]};
'hA: data_out = {{10{data_in[WIDTH-1]}},data_in[WIDTH-1:10]};
'hB: data_out = {{11{data_in[WIDTH-1]}},data_in[WIDTH-1:11]};
'hC: data_out = {{12{data_in[WIDTH-1]}},data_in[WIDTH-1:12]};
'hD: data_out = {{13{data_in[WIDTH-1]}},data_in[WIDTH-1:13]};
'hE: data_out = {{14{data_in[WIDTH-1]}},data_in[WIDTH-1:14]};
'hF: data_out = {{15{data_in[WIDTH-1]}},data_in[WIDTH-1:15]};
'h10: data_out = {{16{data_in[WIDTH-1]}},data_in[WIDTH-1:16]};
'h11: data_out = {{17{data_in[WIDTH-1]}},data_in[WIDTH-1:17]};
'h12: data_out = {{18{data_in[WIDTH-1]}},data_in[WIDTH-1:18]};
'h13: data_out = {{19{data_in[WIDTH-1]}},data_in[WIDTH-1:19]};
'h14: data_out = {{20{data_in[WIDTH-1]}},data_in[WIDTH-1:20]};
'h15: data_out = {{21{data_in[WIDTH-1]}},data_in[WIDTH-1:21]};
'h16: data_out = {{22{data_in[WIDTH-1]}},data_in[WIDTH-1:22]};
'h17: data_out = {{23{data_in[WIDTH-1]}},data_in[WIDTH-1:23]};
'h18: data_out = {{24{data_in[WIDTH-1]}},data_in[WIDTH-1:24]};
'h19: data_out = {{25{data_in[WIDTH-1]}},data_in[WIDTH-1:25]};
'h1A: data_out = {{26{data_in[WIDTH-1]}},data_in[WIDTH-1:26]};
'h1B: data_out = {{27{data_in[WIDTH-1]}},data_in[WIDTH-1:27]};
'h1C: data_out = {{28{data_in[WIDTH-1]}},data_in[WIDTH-1:28]};
'h1D: data_out = {{29{data_in[WIDTH-1]}},data_in[WIDTH-1:29]};
'h1E: data_out = {{30{data_in[WIDTH-1]}},data_in[WIDTH-1:30]};
'h1F: data_out = {{31{data_in[WIDTH-1]}},data_in[WIDTH-1:31]};
'h20: data_out = {{32{data_in[WIDTH-1]}},data_in[WIDTH-1:32]};
'h21: data_out = {{33{data_in[WIDTH-1]}},data_in[WIDTH-1:33]};
'h22: data_out = {{34{data_in[WIDTH-1]}},data_in[WIDTH-1:34]};
'h23: data_out = {{35{data_in[WIDTH-1]}},data_in[WIDTH-1:35]};
'h24: data_out = {{36{data_in[WIDTH-1]}},data_in[WIDTH-1:36]};
'h25: data_out = {{37{data_in[WIDTH-1]}},data_in[WIDTH-1:37]};
'h26: data_out = {{38{data_in[WIDTH-1]}},data_in[WIDTH-1:38]};
'h27: data_out = {{39{data_in[WIDTH-1]}},data_in[WIDTH-1:39]};
'h28: data_out = {{40{data_in[WIDTH-1]}},data_in[WIDTH-1:40]};
'h29: data_out = {{41{data_in[WIDTH-1]}},data_in[WIDTH-1:41]};
'h2A: data_out = {{42{data_in[WIDTH-1]}},data_in[WIDTH-1:42]};
'h2B: data_out = {{43{data_in[WIDTH-1]}},data_in[WIDTH-1:43]};
'h2C: data_out = {{44{data_in[WIDTH-1]}},data_in[WIDTH-1:44]};
'h2D: data_out = {{45{data_in[WIDTH-1]}},data_in[WIDTH-1:45]};
'h2E: data_out = {{46{data_in[WIDTH-1]}},data_in[WIDTH-1:46]};
'h2F: data_out = {{47{data_in[WIDTH-1]}},data_in[WIDTH-1:47]};
'h30: data_out = {{48{data_in[WIDTH-1]}},data_in[WIDTH-1:48]};
default: data_out = data_in;
endcase
end
endmodule | module shift_RA_register (data_in,shamt,data_out); |
parameter WIDTH = 64;
input [WIDTH-1:0] data_in;
input [WIDTH-1:0] shamt;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ *
begin
case(shamt[5:0])
'h0: data_out = {data_in};
'h1: data_out = {{data_in[WIDTH-1]},data_in[WIDTH-1:1]};
'h2: data_out = {{2{data_in[WIDTH-1]}},data_in[WIDTH-1:2]};
'h3: data_out = {{3{data_in[WIDTH-1]}},data_in[WIDTH-1:3]};
'h4: data_out = {{4{data_in[WIDTH-1]}},data_in[WIDTH-1:4]};
'h5: data_out = {{5{data_in[WIDTH-1]}},data_in[WIDTH-1:5]};
'h6: data_out = {{6{data_in[WIDTH-1]}},data_in[WIDTH-1:6]};
'h7: data_out = {{7{data_in[WIDTH-1]}},data_in[WIDTH-1:7]};
'h8: data_out = {{8{data_in[WIDTH-1]}},data_in[WIDTH-1:8]};
'h9: data_out = {{9{data_in[WIDTH-1]}},data_in[WIDTH-1:9]};
'hA: data_out = {{10{data_in[WIDTH-1]}},data_in[WIDTH-1:10]};
'hB: data_out = {{11{data_in[WIDTH-1]}},data_in[WIDTH-1:11]};
'hC: data_out = {{12{data_in[WIDTH-1]}},data_in[WIDTH-1:12]};
'hD: data_out = {{13{data_in[WIDTH-1]}},data_in[WIDTH-1:13]};
'hE: data_out = {{14{data_in[WIDTH-1]}},data_in[WIDTH-1:14]};
'hF: data_out = {{15{data_in[WIDTH-1]}},data_in[WIDTH-1:15]};
'h10: data_out = {{16{data_in[WIDTH-1]}},data_in[WIDTH-1:16]};
'h11: data_out = {{17{data_in[WIDTH-1]}},data_in[WIDTH-1:17]};
'h12: data_out = {{18{data_in[WIDTH-1]}},data_in[WIDTH-1:18]};
'h13: data_out = {{19{data_in[WIDTH-1]}},data_in[WIDTH-1:19]};
'h14: data_out = {{20{data_in[WIDTH-1]}},data_in[WIDTH-1:20]};
'h15: data_out = {{21{data_in[WIDTH-1]}},data_in[WIDTH-1:21]};
'h16: data_out = {{22{data_in[WIDTH-1]}},data_in[WIDTH-1:22]};
'h17: data_out = {{23{data_in[WIDTH-1]}},data_in[WIDTH-1:23]};
'h18: data_out = {{24{data_in[WIDTH-1]}},data_in[WIDTH-1:24]};
'h19: data_out = {{25{data_in[WIDTH-1]}},data_in[WIDTH-1:25]};
'h1A: data_out = {{26{data_in[WIDTH-1]}},data_in[WIDTH-1:26]};
'h1B: data_out = {{27{data_in[WIDTH-1]}},data_in[WIDTH-1:27]};
'h1C: data_out = {{28{data_in[WIDTH-1]}},data_in[WIDTH-1:28]};
'h1D: data_out = {{29{data_in[WIDTH-1]}},data_in[WIDTH-1:29]};
'h1E: data_out = {{30{data_in[WIDTH-1]}},data_in[WIDTH-1:30]};
'h1F: data_out = {{31{data_in[WIDTH-1]}},data_in[WIDTH-1:31]};
'h20: data_out = {{32{data_in[WIDTH-1]}},data_in[WIDTH-1:32]};
'h21: data_out = {{33{data_in[WIDTH-1]}},data_in[WIDTH-1:33]};
'h22: data_out = {{34{data_in[WIDTH-1]}},data_in[WIDTH-1:34]};
'h23: data_out = {{35{data_in[WIDTH-1]}},data_in[WIDTH-1:35]};
'h24: data_out = {{36{data_in[WIDTH-1]}},data_in[WIDTH-1:36]};
'h25: data_out = {{37{data_in[WIDTH-1]}},data_in[WIDTH-1:37]};
'h26: data_out = {{38{data_in[WIDTH-1]}},data_in[WIDTH-1:38]};
'h27: data_out = {{39{data_in[WIDTH-1]}},data_in[WIDTH-1:39]};
'h28: data_out = {{40{data_in[WIDTH-1]}},data_in[WIDTH-1:40]};
'h29: data_out = {{41{data_in[WIDTH-1]}},data_in[WIDTH-1:41]};
'h2A: data_out = {{42{data_in[WIDTH-1]}},data_in[WIDTH-1:42]};
'h2B: data_out = {{43{data_in[WIDTH-1]}},data_in[WIDTH-1:43]};
'h2C: data_out = {{44{data_in[WIDTH-1]}},data_in[WIDTH-1:44]};
'h2D: data_out = {{45{data_in[WIDTH-1]}},data_in[WIDTH-1:45]};
'h2E: data_out = {{46{data_in[WIDTH-1]}},data_in[WIDTH-1:46]};
'h2F: data_out = {{47{data_in[WIDTH-1]}},data_in[WIDTH-1:47]};
'h30: data_out = {{48{data_in[WIDTH-1]}},data_in[WIDTH-1:48]};
default: data_out = data_in;
endcase
end
endmodule | 0 |
3,349 | data/full_repos/permissive/104269513/ALU_final_smaller.v | 104,269,513 | ALU_final_smaller.v | v | 451 | 121 | [] | [] | [] | [(20, 83), (89, 114), (120, 144), (150, 220), (225, 308), (313, 396), (399, 451)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,078 | module | module ALU_ctrl_tb();
reg [63:0] A;
reg [63:0] B;
reg [3:0] cmd;
reg clk;
reg rst;
wire [31:0] psw;
wire [63:0] Data_out;
ALU_ctrl ALU_ctrl(.A(A), .B(B), .cmd(cmd), .psw(psw), .Data_out(Data_out));
initial
begin
clk=0;
rst=1;
forever #10 clk=~clk;
end
initial
begin
#99
rst=0;
A='hFFFF_FFFF_FFFF_FFFF;
B='h0000_0000_0000_0030;
cmd=0;
#20
cmd=1;
#20
cmd=2;
#20
cmd=3;
#20
cmd=4;
#20
cmd=6;
#20
cmd=7;
#20
cmd=8;
end
endmodule | module ALU_ctrl_tb(); |
reg [63:0] A;
reg [63:0] B;
reg [3:0] cmd;
reg clk;
reg rst;
wire [31:0] psw;
wire [63:0] Data_out;
ALU_ctrl ALU_ctrl(.A(A), .B(B), .cmd(cmd), .psw(psw), .Data_out(Data_out));
initial
begin
clk=0;
rst=1;
forever #10 clk=~clk;
end
initial
begin
#99
rst=0;
A='hFFFF_FFFF_FFFF_FFFF;
B='h0000_0000_0000_0030;
cmd=0;
#20
cmd=1;
#20
cmd=2;
#20
cmd=3;
#20
cmd=4;
#20
cmd=6;
#20
cmd=7;
#20
cmd=8;
end
endmodule | 0 |
3,350 | data/full_repos/permissive/104269513/control_logic.v | 104,269,513 | control_logic.v | v | 299 | 220 | [] | [] | [] | [(21, 207), (213, 299)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/control_logic.v:238: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'PL_done\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n ^~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'FW_ld\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/104269513/control_logic.v:238: Infinite loop (condition always true)\n : ... In instance control_tb\nforever #10 clk = ~clk;\n^~~~~~~\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,079 | module | module control (
input [31:0] instruction,
output reg RegWrite,
output reg ALUSrc,
output reg MemWrite,
output reg MemtoReg,
output reg Jump,
output reg ble,
output reg imme,
output reg PL_done,
output reg FW_ld,
output reg [3:0] ALUop,
output reg [2:0] Master_reg,
output reg mem_sel);
wire [6:0]opcode;
wire [2:0]func3;
wire [6:0]func7;
assign opcode = instruction[6:0];
assign func3 = instruction[14:12];
assign func7 = instruction[31:25];
always @(*)
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
case (opcode)
`ADDIW:
begin
RegWrite = 'b1;
ALUSrc = 'b1;
MemtoReg = 'b1;
imme = 'b1;
PL_done = 0;
end
`IMMEDIATE:
begin
RegWrite = 'b1;
ALUSrc = 'b1;
MemtoReg = 'b1;
imme = 'b1;
PL_done = 0;
if (func3 == 'b000)
ALUop = 'd0;
else if(func3 == 'b001)
ALUop='d6;
else if(func3 == 'b100)
ALUop='d4;
else if(func3 == 'b101)
if ((func7 == 'b0000000) || (func7 == 'b0000001))
ALUop = 'd7;
else if((func7 == 'b0100000) || (func7 == 'b0100001))
ALUop = 'd8;
else
ALUop='d0;
end
`ADD_SUB_AND_OR:
begin
RegWrite = 'b1;
MemtoReg = 'b1;
PL_done = 0;
if (func7 == 'b0000000)
if(func3 == 'b000)
ALUop = 'd0;
else if(func3 == 'b110)
ALUop = 'd3;
else if(func3 == 'b111)
ALUop = 'd2;
else if(func7 == 'b0100000)
ALUop = 'd1;
else
ALUop = 'd0;
end
`SD:
begin
if(func3 == 'b111)
mem_sel = 'b1;
else
mem_sel = 'b0;
ALUSrc = 'b1;
MemWrite = 'b1;
PL_done = 0;
end
`BLE: begin
ble = 'b1;
PL_done = 0;
end
`LD:
begin
if(func3 == 'b111)
mem_sel = 'b1;
else
mem_sel = 'b0;
RegWrite = 'b1;
ALUSrc = 'b1;
imme = 'b1;
PL_done = 0;
end
`J:
begin
RegWrite = 'b1;
Jump = 'b1;
PL_done = 0;
end
`FIFO:
begin
FW_ld = 0;
PL_done = 0;
if (func3 == 'b000)
begin
FW_ld = 1;
RegWrite = 'b1;
end
else if(func3 == 'b001)
PL_done = 1;
else
begin
FW_ld = 0;
PL_done = 0;
end
end
`Master_Control:
begin
if (func3 == 'b000)
Master_reg = 'b000;
if (func3 == 'b001)
Master_reg = 'b001;
if (func3 == 'b010)
Master_reg = 'b010;
if (func3 == 'b011)
Master_reg = 'b011;
if (func3 == 'b100)
Master_reg = 'b100;
if (func3 == 'b101)
Master_reg = 'b101;
if (func3 == 'b110)
Master_reg = 'b110;
end
default:
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
end
endcase
end
endmodule | module control (
input [31:0] instruction,
output reg RegWrite,
output reg ALUSrc,
output reg MemWrite,
output reg MemtoReg,
output reg Jump,
output reg ble,
output reg imme,
output reg PL_done,
output reg FW_ld,
output reg [3:0] ALUop,
output reg [2:0] Master_reg,
output reg mem_sel); |
wire [6:0]opcode;
wire [2:0]func3;
wire [6:0]func7;
assign opcode = instruction[6:0];
assign func3 = instruction[14:12];
assign func7 = instruction[31:25];
always @(*)
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
case (opcode)
`ADDIW:
begin
RegWrite = 'b1;
ALUSrc = 'b1;
MemtoReg = 'b1;
imme = 'b1;
PL_done = 0;
end
`IMMEDIATE:
begin
RegWrite = 'b1;
ALUSrc = 'b1;
MemtoReg = 'b1;
imme = 'b1;
PL_done = 0;
if (func3 == 'b000)
ALUop = 'd0;
else if(func3 == 'b001)
ALUop='d6;
else if(func3 == 'b100)
ALUop='d4;
else if(func3 == 'b101)
if ((func7 == 'b0000000) || (func7 == 'b0000001))
ALUop = 'd7;
else if((func7 == 'b0100000) || (func7 == 'b0100001))
ALUop = 'd8;
else
ALUop='d0;
end
`ADD_SUB_AND_OR:
begin
RegWrite = 'b1;
MemtoReg = 'b1;
PL_done = 0;
if (func7 == 'b0000000)
if(func3 == 'b000)
ALUop = 'd0;
else if(func3 == 'b110)
ALUop = 'd3;
else if(func3 == 'b111)
ALUop = 'd2;
else if(func7 == 'b0100000)
ALUop = 'd1;
else
ALUop = 'd0;
end
`SD:
begin
if(func3 == 'b111)
mem_sel = 'b1;
else
mem_sel = 'b0;
ALUSrc = 'b1;
MemWrite = 'b1;
PL_done = 0;
end
`BLE: begin
ble = 'b1;
PL_done = 0;
end
`LD:
begin
if(func3 == 'b111)
mem_sel = 'b1;
else
mem_sel = 'b0;
RegWrite = 'b1;
ALUSrc = 'b1;
imme = 'b1;
PL_done = 0;
end
`J:
begin
RegWrite = 'b1;
Jump = 'b1;
PL_done = 0;
end
`FIFO:
begin
FW_ld = 0;
PL_done = 0;
if (func3 == 'b000)
begin
FW_ld = 1;
RegWrite = 'b1;
end
else if(func3 == 'b001)
PL_done = 1;
else
begin
FW_ld = 0;
PL_done = 0;
end
end
`Master_Control:
begin
if (func3 == 'b000)
Master_reg = 'b000;
if (func3 == 'b001)
Master_reg = 'b001;
if (func3 == 'b010)
Master_reg = 'b010;
if (func3 == 'b011)
Master_reg = 'b011;
if (func3 == 'b100)
Master_reg = 'b100;
if (func3 == 'b101)
Master_reg = 'b101;
if (func3 == 'b110)
Master_reg = 'b110;
end
default:
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
end
endcase
end
endmodule | 0 |
3,351 | data/full_repos/permissive/104269513/control_logic.v | 104,269,513 | control_logic.v | v | 299 | 220 | [] | [] | [] | [(21, 207), (213, 299)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/control_logic.v:238: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'PL_done\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n ^~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'FW_ld\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/104269513/control_logic.v:238: Infinite loop (condition always true)\n : ... In instance control_tb\nforever #10 clk = ~clk;\n^~~~~~~\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,079 | module | module control_tb;
reg clk;
reg [31:0]instruction;
wire RegWrite;
wire ALUSrc;
wire MemWrite;
wire MemtoReg;
wire Jump;
wire ble;
wire imme;
wire [3:0] ALUop;
wire [2:0]Master_reg;
wire mem_sel;
integer count;
control control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));
initial
begin
instruction = 'h00000000;
clk = 0;
count = 0;
forever #10 clk = ~clk;
end
always @(posedge clk)
begin
count <= count + 1;
if (count == 1)
begin
instruction <= 'h0000001e;
end
if (count == 2)
begin
instruction <= 'h0000101e;
end
if (count == 3)
begin
instruction <= 'h0000201e;
end
if (count == 4)
begin
instruction <= 'h0000301e;
end
if (count == 5)
begin
instruction <= 'h0000401e;
end
if (count == 6)
begin
instruction <= 'h0000501e;
end
if (count == 7)
begin
instruction <= 'h0000601e;
end
if (count == 8)
begin
instruction <= 'hfe047623;
end
end
endmodule | module control_tb; |
reg clk;
reg [31:0]instruction;
wire RegWrite;
wire ALUSrc;
wire MemWrite;
wire MemtoReg;
wire Jump;
wire ble;
wire imme;
wire [3:0] ALUop;
wire [2:0]Master_reg;
wire mem_sel;
integer count;
control control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));
initial
begin
instruction = 'h00000000;
clk = 0;
count = 0;
forever #10 clk = ~clk;
end
always @(posedge clk)
begin
count <= count + 1;
if (count == 1)
begin
instruction <= 'h0000001e;
end
if (count == 2)
begin
instruction <= 'h0000101e;
end
if (count == 3)
begin
instruction <= 'h0000201e;
end
if (count == 4)
begin
instruction <= 'h0000301e;
end
if (count == 5)
begin
instruction <= 'h0000401e;
end
if (count == 6)
begin
instruction <= 'h0000501e;
end
if (count == 7)
begin
instruction <= 'h0000601e;
end
if (count == 8)
begin
instruction <= 'hfe047623;
end
end
endmodule | 0 |
3,352 | data/full_repos/permissive/104269513/Fifo_mem.v | 104,269,513 | Fifo_mem.v | v | 179 | 72 | [] | [] | [] | [(6, 76), (83, 178)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:125: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:128: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk; \n ^\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:137: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n in_fifo <= \'hff_9999_1010_0101_1010;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:141: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n in_fifo <= \'h00_0101_1010_0101_1010; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:146: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:150: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:156: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n in_fifo <= \'hff_9999_1010_0101_1010;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:160: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n in_fifo <= \'h00_0101_1010_0101_1010; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:163: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:166: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:172: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,081 | module | module fifomem #(
parameter ADR_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8 ,
parameter WIDTH = 72,
parameter PROG_FULL_THRESHOLD = 2**ADR_WIDTH - 1
)
(
input fiforead,
input fifowrite,
output full,
output nearly_full,
output nearly_empty,
output empty,
input [WIDTH-1:0] in_fifo,
output reg [WIDTH-1:0] out_fifo,
input clk,
input rst);
parameter MAX_DEPTH = 2 ** ADR_WIDTH;
reg [ADR_WIDTH-1:0] WA;
reg [ADR_WIDTH-1:0] RA;
reg [WIDTH-1:0] queue [MAX_DEPTH-1:0];
reg [ADR_WIDTH:0] depth;
assign full = depth == MAX_DEPTH;
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
assign nearly_empty = depth == 'h1;
assign in_rdy = (!full | !nearly_full) & fifowrite;
always @(posedge clk, posedge rst)
begin
if (rst)
begin
WA <= 'h0;
RA <= 'h0;
depth <= 'h0;
end
else begin
if (fifowrite & ~full) WA <= WA + 'h1;
if (fiforead & ~(empty)) RA <= RA + 'h1;
if ((fifowrite & ~full) & ~(fiforead & ~empty)) depth <=
depth + 'h1;
else if (~(fifowrite & ~full) & (fiforead & ~empty)) depth <=
depth - 'h1;
end
end
always @(posedge clk)
begin
out_fifo <= queue[RA];
if (fifowrite & ~full) queue[WA] <= in_fifo;
end
endmodule | module fifomem #(
parameter ADR_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8 ,
parameter WIDTH = 72,
parameter PROG_FULL_THRESHOLD = 2**ADR_WIDTH - 1
)
(
input fiforead,
input fifowrite,
output full,
output nearly_full,
output nearly_empty,
output empty,
input [WIDTH-1:0] in_fifo,
output reg [WIDTH-1:0] out_fifo,
input clk,
input rst); |
parameter MAX_DEPTH = 2 ** ADR_WIDTH;
reg [ADR_WIDTH-1:0] WA;
reg [ADR_WIDTH-1:0] RA;
reg [WIDTH-1:0] queue [MAX_DEPTH-1:0];
reg [ADR_WIDTH:0] depth;
assign full = depth == MAX_DEPTH;
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
assign nearly_empty = depth == 'h1;
assign in_rdy = (!full | !nearly_full) & fifowrite;
always @(posedge clk, posedge rst)
begin
if (rst)
begin
WA <= 'h0;
RA <= 'h0;
depth <= 'h0;
end
else begin
if (fifowrite & ~full) WA <= WA + 'h1;
if (fiforead & ~(empty)) RA <= RA + 'h1;
if ((fifowrite & ~full) & ~(fiforead & ~empty)) depth <=
depth + 'h1;
else if (~(fifowrite & ~full) & (fiforead & ~empty)) depth <=
depth - 'h1;
end
end
always @(posedge clk)
begin
out_fifo <= queue[RA];
if (fifowrite & ~full) queue[WA] <= in_fifo;
end
endmodule | 0 |
3,353 | data/full_repos/permissive/104269513/Fifo_mem.v | 104,269,513 | Fifo_mem.v | v | 179 | 72 | [] | [] | [] | [(6, 76), (83, 178)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:125: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:128: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk; \n ^\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:137: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n in_fifo <= \'hff_9999_1010_0101_1010;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:141: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n in_fifo <= \'h00_0101_1010_0101_1010; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:146: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:150: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:156: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n in_fifo <= \'hff_9999_1010_0101_1010;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:160: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n in_fifo <= \'h00_0101_1010_0101_1010; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:163: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:166: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:172: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n in_fifo <= \'hff_0101_1010_0101_9999;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,081 | module | module fifomem_tb();
reg clk, rst;
integer count;
reg fiforead, fifowrite;
reg [71:0] in_fifo;
wire [71:0] out_fifo;
wire full;
wire nearly_full;
wire nearly_empty;
wire empty;
fifomem UUT (
.fiforead(fiforead),
.fifowrite(fifowrite),
.full(full),
.nearly_full(nearly_full),
.nearly_empty(nearly_empty),
.empty(empty),
.in_fifo(in_fifo),
.out_fifo(out_fifo),
.clk(clk),
.rst(rst)
);
initial begin
fiforead = 'h0;
fifowrite = 'h0;
in_fifo = 'h0;
count = 0;
clk = 0;
rst = 1;
#10
rst = 0;
forever #10 clk = ~clk;
end
always @(posedge clk)
begin
if (count < 1)
begin
fiforead = 'h1;
fifowrite = 'h1;
in_fifo <= 'hff_9999_1010_0101_1010;
end
else if (count < 2)
begin
in_fifo <= 'h00_0101_1010_0101_1010;
end
else if (count < 4)
begin
fiforead <= 'h0;
in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;
end
else if (count < 6)
begin
in_fifo <= 'hff_0101_1010_0101_9999;
end
else if (count < 11)
begin
fiforead <= 'h1;
fifowrite <= 'h0;
in_fifo <= 'hff_9999_1010_0101_1010;
end
else if (count < 12)
begin
in_fifo <= 'h00_0101_1010_0101_1010;
end
else if (count < 13)
in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;
else if (count < 14)
begin
in_fifo <= 'hff_0101_1010_0101_9999;
end
else if (count < 15)
begin
fiforead <= 'h0;
fifowrite <= 'h1;
in_fifo <= 'hff_0101_1010_0101_9999;
end
count <= count + 1;
end
endmodule | module fifomem_tb(); |
reg clk, rst;
integer count;
reg fiforead, fifowrite;
reg [71:0] in_fifo;
wire [71:0] out_fifo;
wire full;
wire nearly_full;
wire nearly_empty;
wire empty;
fifomem UUT (
.fiforead(fiforead),
.fifowrite(fifowrite),
.full(full),
.nearly_full(nearly_full),
.nearly_empty(nearly_empty),
.empty(empty),
.in_fifo(in_fifo),
.out_fifo(out_fifo),
.clk(clk),
.rst(rst)
);
initial begin
fiforead = 'h0;
fifowrite = 'h0;
in_fifo = 'h0;
count = 0;
clk = 0;
rst = 1;
#10
rst = 0;
forever #10 clk = ~clk;
end
always @(posedge clk)
begin
if (count < 1)
begin
fiforead = 'h1;
fifowrite = 'h1;
in_fifo <= 'hff_9999_1010_0101_1010;
end
else if (count < 2)
begin
in_fifo <= 'h00_0101_1010_0101_1010;
end
else if (count < 4)
begin
fiforead <= 'h0;
in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;
end
else if (count < 6)
begin
in_fifo <= 'hff_0101_1010_0101_9999;
end
else if (count < 11)
begin
fiforead <= 'h1;
fifowrite <= 'h0;
in_fifo <= 'hff_9999_1010_0101_1010;
end
else if (count < 12)
begin
in_fifo <= 'h00_0101_1010_0101_1010;
end
else if (count < 13)
in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;
else if (count < 14)
begin
in_fifo <= 'hff_0101_1010_0101_9999;
end
else if (count < 15)
begin
fiforead <= 'h0;
fifowrite <= 'h1;
in_fifo <= 'hff_0101_1010_0101_9999;
end
count <= count + 1;
end
endmodule | 0 |
3,354 | data/full_repos/permissive/104269513/generic_cntr_regs.v | 104,269,513 | generic_cntr_regs.v | v | 310 | 121 | [] | [] | [] | null | line:86: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Signal definition not found, creating implicitly: \'addr_good\'\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:180: Signal definition not found, creating implicitly: \'tag_hit\'\n assign tag_hit = tag_addr == TAG;\n ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:181: Signal definition not found, creating implicitly: \'reg_rd_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good_d1\'\n assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:182: Signal definition not found, creating implicitly: \'reg_wr_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good\'\n assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:185: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign delta = deltas[reg_cnt_d1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:225: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n reg_file[reg_file_wr_addr] <= reg_file_in;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:229: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign reg_file_out = reg_file[reg_file_rd_addr_ram];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:295: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'reg_cnt_d1\' generates 5 bits.\n : ... In instance generic_cntr_regs\n if ((i==reg_cnt_d1) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Comparison is constant due to unsigned arithmetic\n : ... In instance generic_cntr_regs\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 1,082 | module | module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_REGS_USED = 8,
parameter REG_START_ADDR = 0,
parameter INPUT_WIDTH = 1,
parameter MIN_UPDATE_INTERVAL = 8,
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter RESET_ON_READ = 0,
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH,
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
`define CEILDIV_FUNC
function integer ceildiv;
input integer num;
input integer divisor;
begin
if (num <= divisor)
ceildiv = 1;
else begin
ceildiv = num / divisor;
if (ceildiv * divisor < num)
ceildiv = ceildiv + 1;
end
end
endfunction
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
always @(posedge clk) begin
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
if ((i==reg_cnt_d1)
&& !reg_wr_req_good_d1
&& !(reg_rd_req_good_d1 && RESET_ON_READ)
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end
end
end
end
endmodule | module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_REGS_USED = 8,
parameter REG_START_ADDR = 0,
parameter INPUT_WIDTH = 1,
parameter MIN_UPDATE_INTERVAL = 8,
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter RESET_ON_READ = 0,
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH,
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement,
input clk,
input reset
); |
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
`define CEILDIV_FUNC
function integer ceildiv;
input integer num;
input integer divisor;
begin
if (num <= divisor)
ceildiv = 1;
else begin
ceildiv = num / divisor;
if (ceildiv * divisor < num)
ceildiv = ceildiv + 1;
end
end
endfunction
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
always @(posedge clk) begin
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
if ((i==reg_cnt_d1)
&& !reg_wr_req_good_d1
&& !(reg_rd_req_good_d1 && RESET_ON_READ)
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end
end
end
end
endmodule | 0 |
3,355 | data/full_repos/permissive/104269513/generic_cntr_regs.v | 104,269,513 | generic_cntr_regs.v | v | 310 | 121 | [] | [] | [] | null | line:86: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Signal definition not found, creating implicitly: \'addr_good\'\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:180: Signal definition not found, creating implicitly: \'tag_hit\'\n assign tag_hit = tag_addr == TAG;\n ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:181: Signal definition not found, creating implicitly: \'reg_rd_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good_d1\'\n assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:182: Signal definition not found, creating implicitly: \'reg_wr_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good\'\n assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:185: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign delta = deltas[reg_cnt_d1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:225: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n reg_file[reg_file_wr_addr] <= reg_file_in;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:229: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign reg_file_out = reg_file[reg_file_rd_addr_ram];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:295: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'reg_cnt_d1\' generates 5 bits.\n : ... In instance generic_cntr_regs\n if ((i==reg_cnt_d1) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Comparison is constant due to unsigned arithmetic\n : ... In instance generic_cntr_regs\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 1,082 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 0 |
3,356 | data/full_repos/permissive/104269513/generic_cntr_regs.v | 104,269,513 | generic_cntr_regs.v | v | 310 | 121 | [] | [] | [] | null | line:86: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Signal definition not found, creating implicitly: \'addr_good\'\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:180: Signal definition not found, creating implicitly: \'tag_hit\'\n assign tag_hit = tag_addr == TAG;\n ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:181: Signal definition not found, creating implicitly: \'reg_rd_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good_d1\'\n assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_cntr_regs.v:182: Signal definition not found, creating implicitly: \'reg_wr_req_good\'\n : ... Suggested alternative: \'reg_rd_req_good\'\n assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);\n ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:185: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign delta = deltas[reg_cnt_d1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:225: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n reg_file[reg_file_wr_addr] <= reg_file_in;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:229: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_cntr_regs\n assign reg_file_out = reg_file[reg_file_rd_addr_ram];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_cntr_regs.v:295: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'reg_cnt_d1\' generates 5 bits.\n : ... In instance generic_cntr_regs\n if ((i==reg_cnt_d1) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/104269513/generic_cntr_regs.v:179: Comparison is constant due to unsigned arithmetic\n : ... In instance generic_cntr_regs\n assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 1,082 | function | function integer ceildiv;
input integer num;
input integer divisor;
begin
if (num <= divisor)
ceildiv = 1;
else begin
ceildiv = num / divisor;
if (ceildiv * divisor < num)
ceildiv = ceildiv + 1;
end
end
endfunction | function integer ceildiv; |
input integer num;
input integer divisor;
begin
if (num <= divisor)
ceildiv = 1;
else begin
ceildiv = num / divisor;
if (ceildiv * divisor < num)
ceildiv = ceildiv + 1;
end
end
endfunction | 0 |
3,357 | data/full_repos/permissive/104269513/generic_regs.v | 104,269,513 | generic_regs.v | v | 478 | 161 | [] | [] | [] | null | line:162: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_regs.v:291: Signal definition not found, creating implicitly: \'sofware_regs\'\n : ... Suggested alternative: \'software_regs\'\n assign sofware_regs = \'h0;\n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104269513/generic_regs.v:211: Cannot find file containing module: \'generic_cntr_regs\'\n generic_cntr_regs\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs.sv\n generic_cntr_regs\n generic_cntr_regs.v\n generic_cntr_regs.sv\n obj_dir/generic_cntr_regs\n obj_dir/generic_cntr_regs.v\n obj_dir/generic_cntr_regs.sv\n%Error: data/full_repos/permissive/104269513/generic_regs.v:256: Cannot find file containing module: \'generic_sw_regs\'\n generic_sw_regs\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/generic_regs.v:297: Cannot find file containing module: \'generic_hw_regs\'\n generic_hw_regs\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 1,084 | module | module generic_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_COUNTERS = 8,
parameter NUM_SOFTWARE_REGS = 8,
parameter NUM_HARDWARE_REGS = 8,
parameter NUM_INSTANCES = 1,
parameter COUNTER_INPUT_WIDTH = 1,
parameter MIN_UPDATE_INTERVAL = 8,
parameter COUNTER_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter RESET_ON_READ = 0,
parameter REG_START_ADDR = 0,
parameter ACK_UNFOUND_ADDRESSES = 1,
parameter REVERSE_WORD_ORDER = 0,
parameter INSTANCES =
NUM_INSTANCES > 1 ? 2 ** log2(NUM_INSTANCES) : 1,
parameter INST_WIDTH =
NUM_INSTANCES > 1 ? log2(NUM_INSTANCES) : 0,
parameter COUNTER_UPDATE_WIDTH =
NUM_COUNTERS > 0 ? NUM_COUNTERS * COUNTER_INPUT_WIDTH * INSTANCES : INSTANCES,
parameter COUNTER_DECREMENT_WIDTH =
NUM_COUNTERS > 0 ? NUM_COUNTERS * INSTANCES : INSTANCES,
parameter SOFTWARE_REGS_WIDTH =
NUM_SOFTWARE_REGS > 0 ? NUM_SOFTWARE_REGS * `CPCI_NF2_DATA_WIDTH * INSTANCES : INSTANCES,
parameter HARDWARE_REGS_WIDTH =
NUM_HARDWARE_REGS > 0 ? NUM_HARDWARE_REGS * `CPCI_NF2_DATA_WIDTH * INSTANCES : INSTANCES
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates,
input [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement,
output [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs,
input [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
wire cntr_reg_req_out;
wire cntr_reg_ack_out;
wire cntr_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] cntr_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] cntr_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] cntr_reg_src_out;
wire sw_reg_req_out;
wire sw_reg_ack_out;
wire sw_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] sw_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] sw_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] sw_reg_src_out;
wire hw_reg_req_out;
wire hw_reg_ack_out;
wire hw_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] hw_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] hw_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] hw_reg_src_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_swapped;
wire [`UDP_REG_ADDR_WIDTH-1:0] hw_reg_addr_out_swapped;
wire [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates_ordered;
wire [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement_ordered;
wire [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs_ordered;
wire [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs_ordered;
wire [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates_expanded;
wire [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement_expanded;
wire [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs_expanded;
wire [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs_expanded;
generate
if (NUM_COUNTERS > 0) begin
generic_cntr_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_COUNTERS * INSTANCES),
.REG_WIDTH (COUNTER_WIDTH),
.MIN_UPDATE_INTERVAL (MIN_UPDATE_INTERVAL),
.RESET_ON_READ (RESET_ON_READ),
.INPUT_WIDTH (COUNTER_INPUT_WIDTH),
.REG_START_ADDR (REG_START_ADDR))
generic_cntr_regs
(
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in_swapped),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (cntr_reg_req_out),
.reg_ack_out (cntr_reg_ack_out),
.reg_rd_wr_L_out (cntr_reg_rd_wr_L_out),
.reg_addr_out (cntr_reg_addr_out),
.reg_data_out (cntr_reg_data_out),
.reg_src_out (cntr_reg_src_out),
.updates (counter_updates_expanded),
.decrement (counter_decrement_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign cntr_reg_req_out = reg_req_in;
assign cntr_reg_ack_out = reg_ack_in;
assign cntr_reg_rd_wr_L_out = reg_rd_wr_L_in;
assign cntr_reg_addr_out = reg_addr_in_swapped;
assign cntr_reg_data_out = reg_data_in;
assign cntr_reg_src_out = reg_src_in;
end
endgenerate
generate
if (NUM_SOFTWARE_REGS > 0) begin
generic_sw_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_SOFTWARE_REGS * INSTANCES),
.REG_START_ADDR (REG_START_ADDR + NUM_COUNTERS * INSTANCES))
generic_sw_regs
(
.reg_req_in (cntr_reg_req_out),
.reg_ack_in (cntr_reg_ack_out),
.reg_rd_wr_L_in (cntr_reg_rd_wr_L_out),
.reg_addr_in (cntr_reg_addr_out),
.reg_data_in (cntr_reg_data_out),
.reg_src_in (cntr_reg_src_out),
.reg_req_out (sw_reg_req_out),
.reg_ack_out (sw_reg_ack_out),
.reg_rd_wr_L_out (sw_reg_rd_wr_L_out),
.reg_addr_out (sw_reg_addr_out),
.reg_data_out (sw_reg_data_out),
.reg_src_out (sw_reg_src_out),
.software_regs (software_regs_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign sw_reg_req_out = cntr_reg_req_out;
assign sw_reg_ack_out = cntr_reg_ack_out;
assign sw_reg_rd_wr_L_out = cntr_reg_rd_wr_L_out;
assign sw_reg_addr_out = cntr_reg_addr_out;
assign sw_reg_data_out = cntr_reg_data_out;
assign sw_reg_src_out = cntr_reg_src_out;
assign sofware_regs = 'h0;
end
endgenerate
generate
if (NUM_HARDWARE_REGS > 0) begin
generic_hw_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_HARDWARE_REGS * INSTANCES),
.REG_START_ADDR (REG_START_ADDR + (NUM_COUNTERS+NUM_SOFTWARE_REGS) * INSTANCES))
generic_hw_regs
(
.reg_req_in (sw_reg_req_out),
.reg_ack_in (sw_reg_ack_out),
.reg_rd_wr_L_in (sw_reg_rd_wr_L_out),
.reg_addr_in (sw_reg_addr_out),
.reg_data_in (sw_reg_data_out),
.reg_src_in (sw_reg_src_out),
.reg_req_out (hw_reg_req_out),
.reg_ack_out (hw_reg_ack_out),
.reg_rd_wr_L_out (hw_reg_rd_wr_L_out),
.reg_addr_out (hw_reg_addr_out_swapped),
.reg_data_out (hw_reg_data_out),
.reg_src_out (hw_reg_src_out),
.hardware_regs (hardware_regs_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign hw_reg_req_out = sw_reg_req_out;
assign hw_reg_ack_out = sw_reg_ack_out;
assign hw_reg_rd_wr_L_out = sw_reg_rd_wr_L_out;
assign hw_reg_addr_out_swapped = sw_reg_addr_out;
assign hw_reg_data_out = sw_reg_data_out;
assign hw_reg_src_out = sw_reg_src_out;
end
endgenerate
always @(posedge clk) begin
if (reset) begin
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_data_out <= 0;
reg_src_out <= 0;
end
else begin
if (ACK_UNFOUND_ADDRESSES
&& hw_reg_req_out
&& !hw_reg_ack_out
) begin
reg_ack_out <= 1'b1;
reg_data_out <= hw_reg_rd_wr_L_out ? 32'hDEADBEEF : hw_reg_data_out;
end
else begin
reg_ack_out <= hw_reg_ack_out;
reg_data_out <= hw_reg_data_out;
end
reg_req_out <= hw_reg_req_out;
reg_rd_wr_L_out <= hw_reg_rd_wr_L_out;
reg_addr_out <= hw_reg_addr_out;
reg_src_out <= hw_reg_src_out;
end
end
generate
genvar i;
if(NUM_COUNTERS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_COUNTERS; i=i+1) begin:gen_ordered_cntrs
assign counter_updates_ordered[(i+1)*COUNTER_INPUT_WIDTH - 1: i*COUNTER_INPUT_WIDTH]
= counter_updates[(NUM_COUNTERS-i)*COUNTER_INPUT_WIDTH - 1:(NUM_COUNTERS-i-1)*COUNTER_INPUT_WIDTH];
assign counter_decrement_ordered[i] = counter_decrement[NUM_COUNTERS-i-1];
end
end
else begin
assign counter_updates_ordered = counter_updates;
assign counter_decrement_ordered = counter_decrement;
end
if(NUM_SOFTWARE_REGS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_SOFTWARE_REGS; i=i+1) begin:gen_ordered_sw_regs
assign software_regs[(i+1)*`CPCI_NF2_DATA_WIDTH - 1: i*`CPCI_NF2_DATA_WIDTH]
= software_regs_ordered[(NUM_SOFTWARE_REGS-i)*`CPCI_NF2_DATA_WIDTH - 1:(NUM_SOFTWARE_REGS-i-1)*`CPCI_NF2_DATA_WIDTH];
end
end
else begin
assign software_regs = software_regs_ordered;
end
if(NUM_HARDWARE_REGS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_HARDWARE_REGS; i=i+1) begin:gen_ordered_hw_regs
assign hardware_regs_ordered[(i+1)*`CPCI_NF2_DATA_WIDTH - 1: i*`CPCI_NF2_DATA_WIDTH]
= hardware_regs[(NUM_HARDWARE_REGS-i)*`CPCI_NF2_DATA_WIDTH - 1:(NUM_HARDWARE_REGS-i-1)*`CPCI_NF2_DATA_WIDTH];
end
end
else begin
assign hardware_regs_ordered = hardware_regs;
end
endgenerate
generate
genvar j;
if(INSTANCES != 1 && INSTANCES != NUM_INSTANCES) begin
if (NUM_COUNTERS>0) begin
for(j=0; j<NUM_COUNTERS; j=j+1) begin:gen_expanded_cntrs
assign counter_updates_expanded[j*COUNTER_INPUT_WIDTH*INSTANCES +
NUM_INSTANCES*COUNTER_INPUT_WIDTH - 1 :
j*COUNTER_INPUT_WIDTH*INSTANCES] =
counter_updates_ordered[(j+1)*COUNTER_INPUT_WIDTH*NUM_INSTANCES +
j*COUNTER_INPUT_WIDTH*NUM_INSTANCES];
assign counter_updates_expanded[(j+1)*COUNTER_INPUT_WIDTH*INSTANCES - 1 :
j*COUNTER_INPUT_WIDTH*INSTANCES +
NUM_INSTANCES*COUNTER_INPUT_WIDTH] = 0;
assign counter_decrement_expanded[j*INSTANCES + NUM_INSTANCES - 1 : j*INSTANCES] =
counter_decrement_ordered[(j+1)*NUM_INSTANCES + j*NUM_INSTANCES];
assign counter_decrement_expanded[(j+1)*INSTANCES - 1 : j*INSTANCES + NUM_INSTANCES] = 0;
end
end
if (NUM_SOFTWARE_REGS>0) begin
for(j=0; j<NUM_SOFTWARE_REGS; j=j+1) begin:gen_ordered_sw_regs
assign software_regs_ordered[(j+1)*`CPCI_NF2_DATA_WIDTH - 1: j*`CPCI_NF2_DATA_WIDTH] =
software_regs_expanded[j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH - 1:
j*`CPCI_NF2_DATA_WIDTH];
end
end
if (NUM_HARDWARE_REGS>0) begin
for(j=0; j<NUM_HARDWARE_REGS; j=j+1) begin:gen_ordered_hw_regs
assign hardware_regs_expanded[j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH - 1 :
j*`CPCI_NF2_DATA_WIDTH*INSTANCES] =
hardware_regs_ordered[(j+1)*`CPCI_NF2_DATA_WIDTH*NUM_INSTANCES:
j*`CPCI_NF2_DATA_WIDTH*NUM_INSTANCES];
assign hardware_regs_expanded[(j+1)*`CPCI_NF2_DATA_WIDTH*INSTANCES - 1 :
j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH] = 0;
end
end
end
else begin
assign counter_updates_expanded = counter_updates_ordered;
assign counter_decrement_expanded = counter_decrement_ordered;
assign software_regs_ordered = software_regs_expanded;
assign hardware_regs_expanded = hardware_regs_ordered;
end
endgenerate
generate
if (NUM_INSTANCES > 1) begin
assign reg_addr_in_swapped = {reg_addr_in[`UDP_REG_ADDR_WIDTH-1:REG_ADDR_WIDTH],
reg_addr_in[REG_ADDR_WIDTH-INST_WIDTH-1:0],
reg_addr_in[REG_ADDR_WIDTH-1:REG_ADDR_WIDTH-INST_WIDTH]};
assign hw_reg_addr_out = {hw_reg_addr_out_swapped[`UDP_REG_ADDR_WIDTH-1:REG_ADDR_WIDTH],
hw_reg_addr_out_swapped[INST_WIDTH-1:0],
hw_reg_addr_out_swapped[REG_ADDR_WIDTH-1:INST_WIDTH]};
end
else begin
assign reg_addr_in_swapped = reg_addr_in;
assign hw_reg_addr_out = hw_reg_addr_out_swapped;
end
endgenerate
endmodule | module generic_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_COUNTERS = 8,
parameter NUM_SOFTWARE_REGS = 8,
parameter NUM_HARDWARE_REGS = 8,
parameter NUM_INSTANCES = 1,
parameter COUNTER_INPUT_WIDTH = 1,
parameter MIN_UPDATE_INTERVAL = 8,
parameter COUNTER_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter RESET_ON_READ = 0,
parameter REG_START_ADDR = 0,
parameter ACK_UNFOUND_ADDRESSES = 1,
parameter REVERSE_WORD_ORDER = 0,
parameter INSTANCES =
NUM_INSTANCES > 1 ? 2 ** log2(NUM_INSTANCES) : 1,
parameter INST_WIDTH =
NUM_INSTANCES > 1 ? log2(NUM_INSTANCES) : 0,
parameter COUNTER_UPDATE_WIDTH =
NUM_COUNTERS > 0 ? NUM_COUNTERS * COUNTER_INPUT_WIDTH * INSTANCES : INSTANCES,
parameter COUNTER_DECREMENT_WIDTH =
NUM_COUNTERS > 0 ? NUM_COUNTERS * INSTANCES : INSTANCES,
parameter SOFTWARE_REGS_WIDTH =
NUM_SOFTWARE_REGS > 0 ? NUM_SOFTWARE_REGS * `CPCI_NF2_DATA_WIDTH * INSTANCES : INSTANCES,
parameter HARDWARE_REGS_WIDTH =
NUM_HARDWARE_REGS > 0 ? NUM_HARDWARE_REGS * `CPCI_NF2_DATA_WIDTH * INSTANCES : INSTANCES
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates,
input [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement,
output [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs,
input [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs,
input clk,
input reset
); |
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
wire cntr_reg_req_out;
wire cntr_reg_ack_out;
wire cntr_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] cntr_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] cntr_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] cntr_reg_src_out;
wire sw_reg_req_out;
wire sw_reg_ack_out;
wire sw_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] sw_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] sw_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] sw_reg_src_out;
wire hw_reg_req_out;
wire hw_reg_ack_out;
wire hw_reg_rd_wr_L_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] hw_reg_addr_out;
wire [`CPCI_NF2_DATA_WIDTH-1:0] hw_reg_data_out;
wire [UDP_REG_SRC_WIDTH-1:0] hw_reg_src_out;
wire [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_swapped;
wire [`UDP_REG_ADDR_WIDTH-1:0] hw_reg_addr_out_swapped;
wire [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates_ordered;
wire [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement_ordered;
wire [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs_ordered;
wire [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs_ordered;
wire [COUNTER_UPDATE_WIDTH - 1 :0] counter_updates_expanded;
wire [COUNTER_DECREMENT_WIDTH - 1:0] counter_decrement_expanded;
wire [SOFTWARE_REGS_WIDTH - 1 : 0] software_regs_expanded;
wire [HARDWARE_REGS_WIDTH - 1 : 0] hardware_regs_expanded;
generate
if (NUM_COUNTERS > 0) begin
generic_cntr_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_COUNTERS * INSTANCES),
.REG_WIDTH (COUNTER_WIDTH),
.MIN_UPDATE_INTERVAL (MIN_UPDATE_INTERVAL),
.RESET_ON_READ (RESET_ON_READ),
.INPUT_WIDTH (COUNTER_INPUT_WIDTH),
.REG_START_ADDR (REG_START_ADDR))
generic_cntr_regs
(
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in_swapped),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (cntr_reg_req_out),
.reg_ack_out (cntr_reg_ack_out),
.reg_rd_wr_L_out (cntr_reg_rd_wr_L_out),
.reg_addr_out (cntr_reg_addr_out),
.reg_data_out (cntr_reg_data_out),
.reg_src_out (cntr_reg_src_out),
.updates (counter_updates_expanded),
.decrement (counter_decrement_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign cntr_reg_req_out = reg_req_in;
assign cntr_reg_ack_out = reg_ack_in;
assign cntr_reg_rd_wr_L_out = reg_rd_wr_L_in;
assign cntr_reg_addr_out = reg_addr_in_swapped;
assign cntr_reg_data_out = reg_data_in;
assign cntr_reg_src_out = reg_src_in;
end
endgenerate
generate
if (NUM_SOFTWARE_REGS > 0) begin
generic_sw_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_SOFTWARE_REGS * INSTANCES),
.REG_START_ADDR (REG_START_ADDR + NUM_COUNTERS * INSTANCES))
generic_sw_regs
(
.reg_req_in (cntr_reg_req_out),
.reg_ack_in (cntr_reg_ack_out),
.reg_rd_wr_L_in (cntr_reg_rd_wr_L_out),
.reg_addr_in (cntr_reg_addr_out),
.reg_data_in (cntr_reg_data_out),
.reg_src_in (cntr_reg_src_out),
.reg_req_out (sw_reg_req_out),
.reg_ack_out (sw_reg_ack_out),
.reg_rd_wr_L_out (sw_reg_rd_wr_L_out),
.reg_addr_out (sw_reg_addr_out),
.reg_data_out (sw_reg_data_out),
.reg_src_out (sw_reg_src_out),
.software_regs (software_regs_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign sw_reg_req_out = cntr_reg_req_out;
assign sw_reg_ack_out = cntr_reg_ack_out;
assign sw_reg_rd_wr_L_out = cntr_reg_rd_wr_L_out;
assign sw_reg_addr_out = cntr_reg_addr_out;
assign sw_reg_data_out = cntr_reg_data_out;
assign sw_reg_src_out = cntr_reg_src_out;
assign sofware_regs = 'h0;
end
endgenerate
generate
if (NUM_HARDWARE_REGS > 0) begin
generic_hw_regs
#(.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (TAG),
.REG_ADDR_WIDTH (REG_ADDR_WIDTH),
.NUM_REGS_USED (NUM_HARDWARE_REGS * INSTANCES),
.REG_START_ADDR (REG_START_ADDR + (NUM_COUNTERS+NUM_SOFTWARE_REGS) * INSTANCES))
generic_hw_regs
(
.reg_req_in (sw_reg_req_out),
.reg_ack_in (sw_reg_ack_out),
.reg_rd_wr_L_in (sw_reg_rd_wr_L_out),
.reg_addr_in (sw_reg_addr_out),
.reg_data_in (sw_reg_data_out),
.reg_src_in (sw_reg_src_out),
.reg_req_out (hw_reg_req_out),
.reg_ack_out (hw_reg_ack_out),
.reg_rd_wr_L_out (hw_reg_rd_wr_L_out),
.reg_addr_out (hw_reg_addr_out_swapped),
.reg_data_out (hw_reg_data_out),
.reg_src_out (hw_reg_src_out),
.hardware_regs (hardware_regs_expanded),
.clk (clk),
.reset (reset));
end
else begin
assign hw_reg_req_out = sw_reg_req_out;
assign hw_reg_ack_out = sw_reg_ack_out;
assign hw_reg_rd_wr_L_out = sw_reg_rd_wr_L_out;
assign hw_reg_addr_out_swapped = sw_reg_addr_out;
assign hw_reg_data_out = sw_reg_data_out;
assign hw_reg_src_out = sw_reg_src_out;
end
endgenerate
always @(posedge clk) begin
if (reset) begin
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_data_out <= 0;
reg_src_out <= 0;
end
else begin
if (ACK_UNFOUND_ADDRESSES
&& hw_reg_req_out
&& !hw_reg_ack_out
) begin
reg_ack_out <= 1'b1;
reg_data_out <= hw_reg_rd_wr_L_out ? 32'hDEADBEEF : hw_reg_data_out;
end
else begin
reg_ack_out <= hw_reg_ack_out;
reg_data_out <= hw_reg_data_out;
end
reg_req_out <= hw_reg_req_out;
reg_rd_wr_L_out <= hw_reg_rd_wr_L_out;
reg_addr_out <= hw_reg_addr_out;
reg_src_out <= hw_reg_src_out;
end
end
generate
genvar i;
if(NUM_COUNTERS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_COUNTERS; i=i+1) begin:gen_ordered_cntrs
assign counter_updates_ordered[(i+1)*COUNTER_INPUT_WIDTH - 1: i*COUNTER_INPUT_WIDTH]
= counter_updates[(NUM_COUNTERS-i)*COUNTER_INPUT_WIDTH - 1:(NUM_COUNTERS-i-1)*COUNTER_INPUT_WIDTH];
assign counter_decrement_ordered[i] = counter_decrement[NUM_COUNTERS-i-1];
end
end
else begin
assign counter_updates_ordered = counter_updates;
assign counter_decrement_ordered = counter_decrement;
end
if(NUM_SOFTWARE_REGS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_SOFTWARE_REGS; i=i+1) begin:gen_ordered_sw_regs
assign software_regs[(i+1)*`CPCI_NF2_DATA_WIDTH - 1: i*`CPCI_NF2_DATA_WIDTH]
= software_regs_ordered[(NUM_SOFTWARE_REGS-i)*`CPCI_NF2_DATA_WIDTH - 1:(NUM_SOFTWARE_REGS-i-1)*`CPCI_NF2_DATA_WIDTH];
end
end
else begin
assign software_regs = software_regs_ordered;
end
if(NUM_HARDWARE_REGS>1 && REVERSE_WORD_ORDER) begin
for(i=0; i<NUM_HARDWARE_REGS; i=i+1) begin:gen_ordered_hw_regs
assign hardware_regs_ordered[(i+1)*`CPCI_NF2_DATA_WIDTH - 1: i*`CPCI_NF2_DATA_WIDTH]
= hardware_regs[(NUM_HARDWARE_REGS-i)*`CPCI_NF2_DATA_WIDTH - 1:(NUM_HARDWARE_REGS-i-1)*`CPCI_NF2_DATA_WIDTH];
end
end
else begin
assign hardware_regs_ordered = hardware_regs;
end
endgenerate
generate
genvar j;
if(INSTANCES != 1 && INSTANCES != NUM_INSTANCES) begin
if (NUM_COUNTERS>0) begin
for(j=0; j<NUM_COUNTERS; j=j+1) begin:gen_expanded_cntrs
assign counter_updates_expanded[j*COUNTER_INPUT_WIDTH*INSTANCES +
NUM_INSTANCES*COUNTER_INPUT_WIDTH - 1 :
j*COUNTER_INPUT_WIDTH*INSTANCES] =
counter_updates_ordered[(j+1)*COUNTER_INPUT_WIDTH*NUM_INSTANCES +
j*COUNTER_INPUT_WIDTH*NUM_INSTANCES];
assign counter_updates_expanded[(j+1)*COUNTER_INPUT_WIDTH*INSTANCES - 1 :
j*COUNTER_INPUT_WIDTH*INSTANCES +
NUM_INSTANCES*COUNTER_INPUT_WIDTH] = 0;
assign counter_decrement_expanded[j*INSTANCES + NUM_INSTANCES - 1 : j*INSTANCES] =
counter_decrement_ordered[(j+1)*NUM_INSTANCES + j*NUM_INSTANCES];
assign counter_decrement_expanded[(j+1)*INSTANCES - 1 : j*INSTANCES + NUM_INSTANCES] = 0;
end
end
if (NUM_SOFTWARE_REGS>0) begin
for(j=0; j<NUM_SOFTWARE_REGS; j=j+1) begin:gen_ordered_sw_regs
assign software_regs_ordered[(j+1)*`CPCI_NF2_DATA_WIDTH - 1: j*`CPCI_NF2_DATA_WIDTH] =
software_regs_expanded[j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH - 1:
j*`CPCI_NF2_DATA_WIDTH];
end
end
if (NUM_HARDWARE_REGS>0) begin
for(j=0; j<NUM_HARDWARE_REGS; j=j+1) begin:gen_ordered_hw_regs
assign hardware_regs_expanded[j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH - 1 :
j*`CPCI_NF2_DATA_WIDTH*INSTANCES] =
hardware_regs_ordered[(j+1)*`CPCI_NF2_DATA_WIDTH*NUM_INSTANCES:
j*`CPCI_NF2_DATA_WIDTH*NUM_INSTANCES];
assign hardware_regs_expanded[(j+1)*`CPCI_NF2_DATA_WIDTH*INSTANCES - 1 :
j*`CPCI_NF2_DATA_WIDTH*INSTANCES +
NUM_INSTANCES*`CPCI_NF2_DATA_WIDTH] = 0;
end
end
end
else begin
assign counter_updates_expanded = counter_updates_ordered;
assign counter_decrement_expanded = counter_decrement_ordered;
assign software_regs_ordered = software_regs_expanded;
assign hardware_regs_expanded = hardware_regs_ordered;
end
endgenerate
generate
if (NUM_INSTANCES > 1) begin
assign reg_addr_in_swapped = {reg_addr_in[`UDP_REG_ADDR_WIDTH-1:REG_ADDR_WIDTH],
reg_addr_in[REG_ADDR_WIDTH-INST_WIDTH-1:0],
reg_addr_in[REG_ADDR_WIDTH-1:REG_ADDR_WIDTH-INST_WIDTH]};
assign hw_reg_addr_out = {hw_reg_addr_out_swapped[`UDP_REG_ADDR_WIDTH-1:REG_ADDR_WIDTH],
hw_reg_addr_out_swapped[INST_WIDTH-1:0],
hw_reg_addr_out_swapped[REG_ADDR_WIDTH-1:INST_WIDTH]};
end
else begin
assign reg_addr_in_swapped = reg_addr_in;
assign hw_reg_addr_out = hw_reg_addr_out_swapped;
end
endgenerate
endmodule | 0 |
3,358 | data/full_repos/permissive/104269513/generic_regs.v | 104,269,513 | generic_regs.v | v | 478 | 161 | [] | [] | [] | null | line:162: before: "integer" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104269513/generic_regs.v:291: Signal definition not found, creating implicitly: \'sofware_regs\'\n : ... Suggested alternative: \'software_regs\'\n assign sofware_regs = \'h0;\n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104269513/generic_regs.v:211: Cannot find file containing module: \'generic_cntr_regs\'\n generic_cntr_regs\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/generic_cntr_regs.sv\n generic_cntr_regs\n generic_cntr_regs.v\n generic_cntr_regs.sv\n obj_dir/generic_cntr_regs\n obj_dir/generic_cntr_regs.v\n obj_dir/generic_cntr_regs.sv\n%Error: data/full_repos/permissive/104269513/generic_regs.v:256: Cannot find file containing module: \'generic_sw_regs\'\n generic_sw_regs\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/generic_regs.v:297: Cannot find file containing module: \'generic_hw_regs\'\n generic_hw_regs\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 1,084 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 0 |
3,359 | data/full_repos/permissive/104269513/generic_sw_regs.v | 104,269,513 | generic_sw_regs.v | v | 137 | 115 | [] | [] | [] | [(19, 129)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/104269513/generic_sw_regs.v:64: Little bit endian vector: MSB < LSB of bit range: -2:0\n wire [4-REG_ADDR_WIDTH-1:0] tag_addr;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:74: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_addr_in\' generates 4 bits.\n : ... In instance generic_sw_regs\n assign addr = reg_addr_in;\n ^\n%Error: data/full_repos/permissive/104269513/generic_sw_regs.v:75: [3:5] Range extract has backward bit ordering, perhaps you wanted [5:3]\n : ... In instance generic_sw_regs\n assign tag_addr = reg_addr_in[4 - 1:REG_ADDR_WIDTH];\n ^\n%Warning-SELRANGE: data/full_repos/permissive/104269513/generic_sw_regs.v:75: Selection index out of range: 7:5 outside 3:0\n : ... In instance generic_sw_regs\n assign tag_addr = reg_addr_in[4 - 1:REG_ADDR_WIDTH];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:110: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_sw_regs\n reg_data_out <= reg_file[addr];\n ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:115: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n : ... In instance generic_sw_regs\n reg_file[addr] <= reg_data_in;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 1,085 | module | module generic_sw_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_REGS_USED = 8,
parameter REG_START_ADDR = 0,
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
parameter INPUT_START = REG_START_ADDR * `CPCI_NF2_DATA_WIDTH,
parameter INPUT_END = REG_END_ADDR * `CPCI_NF2_DATA_WIDTH
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
output [INPUT_END - 1 : INPUT_START] software_regs,
input clk,
input reset
);
wire [REG_ADDR_WIDTH-1:0] addr;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
wire addr_good;
wire tag_hit;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_file[REG_START_ADDR:REG_END_ADDR - 1];
integer ii;
assign addr = reg_addr_in;
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
generate
genvar i;
for (i=REG_START_ADDR; i<REG_END_ADDR; i=i+1) begin:reg_file_assigns
assign software_regs[`CPCI_NF2_DATA_WIDTH*(i+1)-1:`CPCI_NF2_DATA_WIDTH*i]
= reg_file[i];
end
endgenerate
always @(posedge clk) begin
if(reset) begin
for(ii=REG_START_ADDR; ii<REG_END_ADDR; ii=ii+1) begin
reg_file[ii] <= 0;
end
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_src_out <= 0;
reg_data_out <= 0;
end
else begin
if(addr_good && tag_hit && reg_req_in) begin
reg_req_out <= reg_req_in;
reg_ack_out <= 1'b1;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
if(reg_rd_wr_L_in) begin
reg_data_out <= reg_file[addr];
end
else begin
reg_data_out <= reg_data_in;
reg_file[addr] <= reg_data_in;
end
end
else begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
reg_data_out <= reg_data_in;
end
end
end
endmodule | module generic_sw_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0,
parameter REG_ADDR_WIDTH = 5,
parameter NUM_REGS_USED = 8,
parameter REG_START_ADDR = 0,
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
parameter INPUT_START = REG_START_ADDR * `CPCI_NF2_DATA_WIDTH,
parameter INPUT_END = REG_END_ADDR * `CPCI_NF2_DATA_WIDTH
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
output [INPUT_END - 1 : INPUT_START] software_regs,
input clk,
input reset
); |
wire [REG_ADDR_WIDTH-1:0] addr;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
wire addr_good;
wire tag_hit;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_file[REG_START_ADDR:REG_END_ADDR - 1];
integer ii;
assign addr = reg_addr_in;
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
generate
genvar i;
for (i=REG_START_ADDR; i<REG_END_ADDR; i=i+1) begin:reg_file_assigns
assign software_regs[`CPCI_NF2_DATA_WIDTH*(i+1)-1:`CPCI_NF2_DATA_WIDTH*i]
= reg_file[i];
end
endgenerate
always @(posedge clk) begin
if(reset) begin
for(ii=REG_START_ADDR; ii<REG_END_ADDR; ii=ii+1) begin
reg_file[ii] <= 0;
end
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_src_out <= 0;
reg_data_out <= 0;
end
else begin
if(addr_good && tag_hit && reg_req_in) begin
reg_req_out <= reg_req_in;
reg_ack_out <= 1'b1;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
if(reg_rd_wr_L_in) begin
reg_data_out <= reg_file[addr];
end
else begin
reg_data_out <= reg_data_in;
reg_file[addr] <= reg_data_in;
end
end
else begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
reg_data_out <= reg_data_in;
end
end
end
endmodule | 0 |
3,360 | data/full_repos/permissive/104269513/master_control.v | 104,269,513 | master_control.v | v | 518 | 228 | [] | [] | [] | null | line:94: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/104269513/master_control.v:107: Cannot find file containing module: \'spring_fifo\'\n spring_fifo fifo( \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo.sv\n spring_fifo\n spring_fifo.v\n spring_fifo.sv\n obj_dir/spring_fifo\n obj_dir/spring_fifo.v\n obj_dir/spring_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/104269513/master_control.v:411: Operator LT expects 32 or 17 bits on the LHS, but LHS\'s VARREF \'counter\' generates 16 bits.\n : ... In instance master_ctrl\n if (counter < \'h10000)\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,086 | module | module master_ctrl #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 5
)
(
input [log2(Number_of_FIFO)-1:0] ip_fifo_sel,
input ip_PL_done,
output reg in_rdy,
input in_wr,
input out_rdy,
output reg out_wr,
output reg [log2(Number_of_FIFO)-1:0] pckt_count,
output reg [1:0] state,
output reg full,
output reg nearly_full,
output reg nearly_empty,
output reg empty,
output reg pckt_rd_wr,
input [DATA_WIDTH-1:0] fifo_data_in,
output reg [DATA_WIDTH-1:0] fifo_data_out,
input [CTRL_WIDTH-1:0] fifo_ctrl_in,
output reg [CTRL_WIDTH-1:0] fifo_ctrl_out,
input clk,
input rst
);
reg [Number_of_FIFO-1:0] sf_rd_req;
reg [Number_of_FIFO-1:0] sf_wr_req;
wire [Number_of_FIFO-1:0] sf_rd_ack;
wire [Number_of_FIFO-1:0] sf_wr_ack;
wire [Number_of_FIFO-1:0] sf_rd_done;
wire [Number_of_FIFO-1:0] sf_wr_done;
wire [Number_of_FIFO-1:0] sf_out_wr;
wire [Number_of_FIFO-1:0] sf_in_rdy;
reg [Number_of_FIFO-1:0] sf_in_wr;
reg [Number_of_FIFO-1:0] sf_out_rdy;
wire [Number_of_FIFO-1:0] sf_full;
wire [Number_of_FIFO-1:0] sf_nearly_full;
wire [Number_of_FIFO-1:0] sf_nearly_empty;
wire [Number_of_FIFO-1:0] sf_empty;
wire [Number_of_FIFO-1:0] sf_pckt_rd_wr;
wire [DATA_WIDTH-1:0] sf_data_out[Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] sf_ctrl_out[Number_of_FIFO-1:0];
reg [log2(Number_of_FIFO)-1:0] fifo_sel;
reg [log2(Number_of_FIFO)-1:0] op_fifo_sel;
reg rd_req;
reg wr_req;
reg rd_ack;
reg wr_ack;
reg rd_done;
reg wr_done;
reg [15:0] counter,counter_next;
reg [log2(Number_of_FIFO)-1:0] prev_pckt_count, prev_pckt_count_next;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
genvar i;
generate
for (i=0 ; i<Number_of_FIFO ; i = i+1)
begin:SF
spring_fifo fifo(
.rd_req(sf_rd_req[i]),
.wr_req(sf_wr_req[i]),
.out_rdy(sf_out_rdy[i]),
.in_wr(sf_in_wr[i]),
.ip_rd_count(2'b1),
.out_wr(sf_out_wr[i]),
.pckt_rd_wr(sf_pckt_rd_wr[i]),
.rd_ack(sf_rd_ack[i]),
.wr_ack(sf_wr_ack[i]),
.rd_done(sf_rd_done[i]),
.wr_done(sf_wr_done[i]),
.in_rdy(sf_in_rdy[i]),
.full(sf_full[i]),
.empty(sf_empty[i]),
.nearly_full(sf_nearly_full[i]),
.nearly_empty(sf_nearly_empty[i]),
.packet_count(),
.first_word(),
.last_word(),
.fifo_busy(),
.fifo_data_in(fifo_data_in),
.fifo_data_out(sf_data_out[i]),
.fifo_ctrl_in(fifo_ctrl_in),
.fifo_ctrl_out(sf_ctrl_out[i]),
.DEPTH(),
.wr_state(),
.state(),
.fifo_wa(),
.fifo_ra(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
end
endgenerate
always @ (*)
begin
sf_rd_req [0] = 'h0;
sf_wr_req [0] = 'h0;
sf_rd_req [1] = 'h0;
sf_wr_req [1] = 'h0;
sf_rd_req [2] = 'h0;
sf_wr_req [2] = 'h0;
sf_rd_req [3] = 'h0;
sf_wr_req [3] = 'h0;
sf_rd_req [4] = 'h0;
sf_wr_req [4] = 'h0;
sf_in_wr [0] = 'h0;
sf_out_rdy [0] = 'h0;
sf_in_wr [1] = 'h0;
sf_out_rdy [1] = 'h0;
sf_in_wr [2] = 'h0;
sf_out_rdy [2] = 'h0;
sf_in_wr [3] = 'h0;
sf_out_rdy [3] = 'h0;
sf_in_wr [4] = 'h0;
sf_out_rdy [4] = 'h0;
case (fifo_sel)
'h0:begin
rd_ack = sf_rd_ack [0];
wr_ack = sf_wr_ack [0];
rd_done = sf_rd_done [0];
wr_done = sf_wr_done [0];
sf_rd_req [0] = rd_req;
sf_wr_req [0] = wr_req;
in_rdy = sf_in_rdy [0];
out_wr = sf_out_wr [0];
sf_in_wr [0] = in_wr;
sf_out_rdy [0] = out_rdy;
full = sf_full [0];
nearly_full = sf_nearly_full [0];
nearly_empty = sf_nearly_empty [0];
empty = sf_empty [0];
pckt_rd_wr = sf_pckt_rd_wr[0];
end
'h1:begin
rd_ack = sf_rd_ack [1];
wr_ack = sf_wr_ack [1];
rd_done = sf_rd_done [1];
wr_done = sf_wr_done [1];
sf_rd_req [1] = rd_req;
sf_wr_req [1] = wr_req;
in_rdy = sf_in_rdy [1];
out_wr = sf_out_wr [1];
sf_in_wr [1] = in_wr;
sf_out_rdy [1] = out_rdy;
full = sf_full [1];
nearly_full = sf_nearly_full [1];
nearly_empty = sf_nearly_empty [1];
empty = sf_empty [1];
pckt_rd_wr = sf_pckt_rd_wr[1];
end
'h2:begin
rd_ack = sf_rd_ack [2];
wr_ack = sf_wr_ack [2];
rd_done = sf_rd_done [2];
wr_done = sf_wr_done [2];
sf_rd_req [2] = rd_req;
sf_wr_req [2] = wr_req;
in_rdy = sf_in_rdy [2];
out_wr = sf_out_wr [2];
sf_in_wr [2] = in_wr;
sf_out_rdy [2] = out_rdy;
full = sf_full [2];
nearly_full = sf_nearly_full [2];
nearly_empty = sf_nearly_empty [2];
empty = sf_empty [2];
pckt_rd_wr = sf_pckt_rd_wr[2];
end
'h3:begin
rd_ack = sf_rd_ack [3];
wr_ack = sf_wr_ack [3];
rd_done = sf_rd_done [3];
wr_done = sf_wr_done [3];
sf_rd_req [3] = rd_req;
sf_wr_req [3] = wr_req;
in_rdy = sf_in_rdy [3];
out_wr = sf_out_wr [3];
sf_in_wr [3] = in_wr;
sf_out_rdy [3] = out_rdy;
full = sf_full [3];
nearly_full = sf_nearly_full [3];
nearly_empty = sf_nearly_empty [3];
empty = sf_empty [3];
pckt_rd_wr = sf_pckt_rd_wr[3];
end
'h4:begin
rd_ack = sf_rd_ack [4];
wr_ack = sf_wr_ack [4];
rd_done = sf_rd_done [4];
wr_done = sf_wr_done [4];
sf_rd_req [4] = rd_req;
sf_wr_req [4] = wr_req;
in_rdy = sf_in_rdy [4];
out_wr = sf_out_wr [4];
sf_in_wr [4] = in_wr;
sf_out_rdy [4] = out_rdy;
full = sf_full [4];
nearly_full = sf_nearly_full [4];
nearly_empty = sf_nearly_empty [4];
empty = sf_empty [4];
pckt_rd_wr = sf_pckt_rd_wr[4];
end
default: begin
rd_ack = sf_rd_ack [0];
wr_ack = sf_wr_ack [0];
rd_done = sf_rd_done [0];
wr_done = sf_wr_done [0];
sf_rd_req [0] = rd_req;
sf_wr_req [0] = wr_req;
in_rdy = sf_in_rdy [0];
out_wr = sf_out_wr [0];
sf_in_wr [0] = in_wr;
sf_out_rdy [0] = out_rdy;
full = sf_full [0];
nearly_full = sf_nearly_full [0];
nearly_empty = sf_nearly_empty [0];
empty = sf_empty [0];
pckt_rd_wr = sf_pckt_rd_wr[0];
end
endcase
end
always @ (fifo_sel, sf_data_out[0],sf_data_out[1],sf_data_out[2],sf_data_out[3],sf_data_out[4],sf_ctrl_out[0],sf_ctrl_out[1],sf_ctrl_out[2],sf_ctrl_out[3],sf_ctrl_out[4])
begin
case (fifo_sel)
'h0:begin
fifo_data_out = sf_data_out[0];
fifo_ctrl_out = sf_ctrl_out[0];
end
'h1:begin
fifo_data_out = sf_data_out[1];
fifo_ctrl_out = sf_ctrl_out[1];
end
'h2:begin
fifo_data_out = sf_data_out[2];
fifo_ctrl_out = sf_ctrl_out[2];
end
'h3:begin
fifo_data_out = sf_data_out[3];
fifo_ctrl_out = sf_ctrl_out[3];
end
'h4:begin
fifo_data_out = sf_data_out[4];
fifo_ctrl_out = sf_ctrl_out[4];
end
default: begin
fifo_data_out = sf_data_out[0];
fifo_ctrl_out = sf_ctrl_out[0];
end
endcase
end
always @ *
begin
prev_pckt_count_next = pckt_count;
counter_next = counter + 1;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
state <= 'h0;
rd_req <= 'h0;
wr_req <= 'h0;
fifo_sel <= 'h0;
op_fifo_sel <= 'h0;
pckt_count <= 'h0;
prev_pckt_count <= 'h0;
counter <= 'h0;
end
else
begin
prev_pckt_count <= prev_pckt_count_next;
counter <= counter_next;
if (fifo_sel == 'h0)
op_fifo_sel <= fifo_sel;
else if (pckt_count == 'h4)
op_fifo_sel <='h1;
else if (pckt_count == 'h3)
op_fifo_sel <='h2;
else if (pckt_count == 'h2)
op_fifo_sel <='h3;
else if (pckt_count == 'h1)
op_fifo_sel <='h4;
if (counter < 'h10000)
begin
case (state)
'h0: begin
if (ip_PL_done)
begin
fifo_sel <= ip_fifo_sel;
if (pckt_rd_wr)
wr_req <= 1;
if (wr_ack)
begin
wr_req <= 0;
state <= 'h1;
end
end
end
'h1: begin
if (!pckt_rd_wr)
begin
if (prev_pckt_count != pckt_count)
begin
if ((pckt_count == 'h4) | (fifo_sel == 'h0))
state <= 'h2;
else
state <= 'h0;
end
else
pckt_count <= pckt_count + 1;
end
end
'h2: begin
fifo_sel <= op_fifo_sel;
rd_req <= 1;
if (rd_ack)
begin
rd_req <= 0;
state <= 'h3;
end
end
'h3: begin
if (pckt_rd_wr)
begin
if (prev_pckt_count != pckt_count)
begin
if ((pckt_count == 'h0) | (op_fifo_sel == 'h0))
begin
state <= 'h0;
counter_next <= 'h0;
end
else
state <= 'h2;
end
else
pckt_count <= pckt_count - 1;
end
end
default:begin
state <= 'h0;
rd_req <= 'h0;
wr_req <= 'h0;
fifo_sel <= 'h0;
op_fifo_sel <= 'h0;
pckt_count <= 'h0;
end
endcase
end
else
begin
if(!sf_pckt_rd_wr[1])
begin
fifo_sel <= 'h1;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[2])
begin
fifo_sel <= 'h2;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[3])
begin
fifo_sel <= 'h3;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[4])
begin
fifo_sel <= 'h4;
wr_req <= 'h0;
rd_req <= 'h1;
counter_next <= 'h0;
end
end
end
end
endmodule | module master_ctrl #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 5
)
(
input [log2(Number_of_FIFO)-1:0] ip_fifo_sel,
input ip_PL_done,
output reg in_rdy,
input in_wr,
input out_rdy,
output reg out_wr,
output reg [log2(Number_of_FIFO)-1:0] pckt_count,
output reg [1:0] state,
output reg full,
output reg nearly_full,
output reg nearly_empty,
output reg empty,
output reg pckt_rd_wr,
input [DATA_WIDTH-1:0] fifo_data_in,
output reg [DATA_WIDTH-1:0] fifo_data_out,
input [CTRL_WIDTH-1:0] fifo_ctrl_in,
output reg [CTRL_WIDTH-1:0] fifo_ctrl_out,
input clk,
input rst
); |
reg [Number_of_FIFO-1:0] sf_rd_req;
reg [Number_of_FIFO-1:0] sf_wr_req;
wire [Number_of_FIFO-1:0] sf_rd_ack;
wire [Number_of_FIFO-1:0] sf_wr_ack;
wire [Number_of_FIFO-1:0] sf_rd_done;
wire [Number_of_FIFO-1:0] sf_wr_done;
wire [Number_of_FIFO-1:0] sf_out_wr;
wire [Number_of_FIFO-1:0] sf_in_rdy;
reg [Number_of_FIFO-1:0] sf_in_wr;
reg [Number_of_FIFO-1:0] sf_out_rdy;
wire [Number_of_FIFO-1:0] sf_full;
wire [Number_of_FIFO-1:0] sf_nearly_full;
wire [Number_of_FIFO-1:0] sf_nearly_empty;
wire [Number_of_FIFO-1:0] sf_empty;
wire [Number_of_FIFO-1:0] sf_pckt_rd_wr;
wire [DATA_WIDTH-1:0] sf_data_out[Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] sf_ctrl_out[Number_of_FIFO-1:0];
reg [log2(Number_of_FIFO)-1:0] fifo_sel;
reg [log2(Number_of_FIFO)-1:0] op_fifo_sel;
reg rd_req;
reg wr_req;
reg rd_ack;
reg wr_ack;
reg rd_done;
reg wr_done;
reg [15:0] counter,counter_next;
reg [log2(Number_of_FIFO)-1:0] prev_pckt_count, prev_pckt_count_next;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
genvar i;
generate
for (i=0 ; i<Number_of_FIFO ; i = i+1)
begin:SF
spring_fifo fifo(
.rd_req(sf_rd_req[i]),
.wr_req(sf_wr_req[i]),
.out_rdy(sf_out_rdy[i]),
.in_wr(sf_in_wr[i]),
.ip_rd_count(2'b1),
.out_wr(sf_out_wr[i]),
.pckt_rd_wr(sf_pckt_rd_wr[i]),
.rd_ack(sf_rd_ack[i]),
.wr_ack(sf_wr_ack[i]),
.rd_done(sf_rd_done[i]),
.wr_done(sf_wr_done[i]),
.in_rdy(sf_in_rdy[i]),
.full(sf_full[i]),
.empty(sf_empty[i]),
.nearly_full(sf_nearly_full[i]),
.nearly_empty(sf_nearly_empty[i]),
.packet_count(),
.first_word(),
.last_word(),
.fifo_busy(),
.fifo_data_in(fifo_data_in),
.fifo_data_out(sf_data_out[i]),
.fifo_ctrl_in(fifo_ctrl_in),
.fifo_ctrl_out(sf_ctrl_out[i]),
.DEPTH(),
.wr_state(),
.state(),
.fifo_wa(),
.fifo_ra(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
end
endgenerate
always @ (*)
begin
sf_rd_req [0] = 'h0;
sf_wr_req [0] = 'h0;
sf_rd_req [1] = 'h0;
sf_wr_req [1] = 'h0;
sf_rd_req [2] = 'h0;
sf_wr_req [2] = 'h0;
sf_rd_req [3] = 'h0;
sf_wr_req [3] = 'h0;
sf_rd_req [4] = 'h0;
sf_wr_req [4] = 'h0;
sf_in_wr [0] = 'h0;
sf_out_rdy [0] = 'h0;
sf_in_wr [1] = 'h0;
sf_out_rdy [1] = 'h0;
sf_in_wr [2] = 'h0;
sf_out_rdy [2] = 'h0;
sf_in_wr [3] = 'h0;
sf_out_rdy [3] = 'h0;
sf_in_wr [4] = 'h0;
sf_out_rdy [4] = 'h0;
case (fifo_sel)
'h0:begin
rd_ack = sf_rd_ack [0];
wr_ack = sf_wr_ack [0];
rd_done = sf_rd_done [0];
wr_done = sf_wr_done [0];
sf_rd_req [0] = rd_req;
sf_wr_req [0] = wr_req;
in_rdy = sf_in_rdy [0];
out_wr = sf_out_wr [0];
sf_in_wr [0] = in_wr;
sf_out_rdy [0] = out_rdy;
full = sf_full [0];
nearly_full = sf_nearly_full [0];
nearly_empty = sf_nearly_empty [0];
empty = sf_empty [0];
pckt_rd_wr = sf_pckt_rd_wr[0];
end
'h1:begin
rd_ack = sf_rd_ack [1];
wr_ack = sf_wr_ack [1];
rd_done = sf_rd_done [1];
wr_done = sf_wr_done [1];
sf_rd_req [1] = rd_req;
sf_wr_req [1] = wr_req;
in_rdy = sf_in_rdy [1];
out_wr = sf_out_wr [1];
sf_in_wr [1] = in_wr;
sf_out_rdy [1] = out_rdy;
full = sf_full [1];
nearly_full = sf_nearly_full [1];
nearly_empty = sf_nearly_empty [1];
empty = sf_empty [1];
pckt_rd_wr = sf_pckt_rd_wr[1];
end
'h2:begin
rd_ack = sf_rd_ack [2];
wr_ack = sf_wr_ack [2];
rd_done = sf_rd_done [2];
wr_done = sf_wr_done [2];
sf_rd_req [2] = rd_req;
sf_wr_req [2] = wr_req;
in_rdy = sf_in_rdy [2];
out_wr = sf_out_wr [2];
sf_in_wr [2] = in_wr;
sf_out_rdy [2] = out_rdy;
full = sf_full [2];
nearly_full = sf_nearly_full [2];
nearly_empty = sf_nearly_empty [2];
empty = sf_empty [2];
pckt_rd_wr = sf_pckt_rd_wr[2];
end
'h3:begin
rd_ack = sf_rd_ack [3];
wr_ack = sf_wr_ack [3];
rd_done = sf_rd_done [3];
wr_done = sf_wr_done [3];
sf_rd_req [3] = rd_req;
sf_wr_req [3] = wr_req;
in_rdy = sf_in_rdy [3];
out_wr = sf_out_wr [3];
sf_in_wr [3] = in_wr;
sf_out_rdy [3] = out_rdy;
full = sf_full [3];
nearly_full = sf_nearly_full [3];
nearly_empty = sf_nearly_empty [3];
empty = sf_empty [3];
pckt_rd_wr = sf_pckt_rd_wr[3];
end
'h4:begin
rd_ack = sf_rd_ack [4];
wr_ack = sf_wr_ack [4];
rd_done = sf_rd_done [4];
wr_done = sf_wr_done [4];
sf_rd_req [4] = rd_req;
sf_wr_req [4] = wr_req;
in_rdy = sf_in_rdy [4];
out_wr = sf_out_wr [4];
sf_in_wr [4] = in_wr;
sf_out_rdy [4] = out_rdy;
full = sf_full [4];
nearly_full = sf_nearly_full [4];
nearly_empty = sf_nearly_empty [4];
empty = sf_empty [4];
pckt_rd_wr = sf_pckt_rd_wr[4];
end
default: begin
rd_ack = sf_rd_ack [0];
wr_ack = sf_wr_ack [0];
rd_done = sf_rd_done [0];
wr_done = sf_wr_done [0];
sf_rd_req [0] = rd_req;
sf_wr_req [0] = wr_req;
in_rdy = sf_in_rdy [0];
out_wr = sf_out_wr [0];
sf_in_wr [0] = in_wr;
sf_out_rdy [0] = out_rdy;
full = sf_full [0];
nearly_full = sf_nearly_full [0];
nearly_empty = sf_nearly_empty [0];
empty = sf_empty [0];
pckt_rd_wr = sf_pckt_rd_wr[0];
end
endcase
end
always @ (fifo_sel, sf_data_out[0],sf_data_out[1],sf_data_out[2],sf_data_out[3],sf_data_out[4],sf_ctrl_out[0],sf_ctrl_out[1],sf_ctrl_out[2],sf_ctrl_out[3],sf_ctrl_out[4])
begin
case (fifo_sel)
'h0:begin
fifo_data_out = sf_data_out[0];
fifo_ctrl_out = sf_ctrl_out[0];
end
'h1:begin
fifo_data_out = sf_data_out[1];
fifo_ctrl_out = sf_ctrl_out[1];
end
'h2:begin
fifo_data_out = sf_data_out[2];
fifo_ctrl_out = sf_ctrl_out[2];
end
'h3:begin
fifo_data_out = sf_data_out[3];
fifo_ctrl_out = sf_ctrl_out[3];
end
'h4:begin
fifo_data_out = sf_data_out[4];
fifo_ctrl_out = sf_ctrl_out[4];
end
default: begin
fifo_data_out = sf_data_out[0];
fifo_ctrl_out = sf_ctrl_out[0];
end
endcase
end
always @ *
begin
prev_pckt_count_next = pckt_count;
counter_next = counter + 1;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
state <= 'h0;
rd_req <= 'h0;
wr_req <= 'h0;
fifo_sel <= 'h0;
op_fifo_sel <= 'h0;
pckt_count <= 'h0;
prev_pckt_count <= 'h0;
counter <= 'h0;
end
else
begin
prev_pckt_count <= prev_pckt_count_next;
counter <= counter_next;
if (fifo_sel == 'h0)
op_fifo_sel <= fifo_sel;
else if (pckt_count == 'h4)
op_fifo_sel <='h1;
else if (pckt_count == 'h3)
op_fifo_sel <='h2;
else if (pckt_count == 'h2)
op_fifo_sel <='h3;
else if (pckt_count == 'h1)
op_fifo_sel <='h4;
if (counter < 'h10000)
begin
case (state)
'h0: begin
if (ip_PL_done)
begin
fifo_sel <= ip_fifo_sel;
if (pckt_rd_wr)
wr_req <= 1;
if (wr_ack)
begin
wr_req <= 0;
state <= 'h1;
end
end
end
'h1: begin
if (!pckt_rd_wr)
begin
if (prev_pckt_count != pckt_count)
begin
if ((pckt_count == 'h4) | (fifo_sel == 'h0))
state <= 'h2;
else
state <= 'h0;
end
else
pckt_count <= pckt_count + 1;
end
end
'h2: begin
fifo_sel <= op_fifo_sel;
rd_req <= 1;
if (rd_ack)
begin
rd_req <= 0;
state <= 'h3;
end
end
'h3: begin
if (pckt_rd_wr)
begin
if (prev_pckt_count != pckt_count)
begin
if ((pckt_count == 'h0) | (op_fifo_sel == 'h0))
begin
state <= 'h0;
counter_next <= 'h0;
end
else
state <= 'h2;
end
else
pckt_count <= pckt_count - 1;
end
end
default:begin
state <= 'h0;
rd_req <= 'h0;
wr_req <= 'h0;
fifo_sel <= 'h0;
op_fifo_sel <= 'h0;
pckt_count <= 'h0;
end
endcase
end
else
begin
if(!sf_pckt_rd_wr[1])
begin
fifo_sel <= 'h1;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[2])
begin
fifo_sel <= 'h2;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[3])
begin
fifo_sel <= 'h3;
wr_req <= 'h0;
rd_req <= 'h1;
end
else if(!sf_pckt_rd_wr[4])
begin
fifo_sel <= 'h4;
wr_req <= 'h0;
rd_req <= 'h1;
counter_next <= 'h0;
end
end
end
end
endmodule | 0 |
3,361 | data/full_repos/permissive/104269513/master_control.v | 104,269,513 | master_control.v | v | 518 | 228 | [] | [] | [] | null | line:94: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/104269513/master_control.v:107: Cannot find file containing module: \'spring_fifo\'\n spring_fifo fifo( \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo.sv\n spring_fifo\n spring_fifo.v\n spring_fifo.sv\n obj_dir/spring_fifo\n obj_dir/spring_fifo.v\n obj_dir/spring_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/104269513/master_control.v:411: Operator LT expects 32 or 17 bits on the LHS, but LHS\'s VARREF \'counter\' generates 16 bits.\n : ... In instance master_ctrl\n if (counter < \'h10000)\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,086 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 0 |
3,362 | data/full_repos/permissive/104269513/mem_mod_master2_32bit - FinalFSM - final project_combined.v | 104,269,513 | mem_mod_master2_32bit - FinalFSM - final project_combined.v | v | 888 | 452 | [] | ['netfpga'] | [] | null | line:310: before: ")" | null | 1: b'%Error: Invalid Option: -\n' | 1,087 | module | module mem_mod_mast
#( parameter UDP_REG_SRC_WIDTH = 2,
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output in_rdy,
output out_wr,
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input clk,
input rst
);
wire [31:0] cmd;
wire IorD;
wire [8:0] Addr_in;
wire [DATA_WIDTH-1:0] Data_In;
wire [DATA_WIDTH-1:0] Data_out_DM;
wire full,empty;
wire nearly_full,nearly_empty;
wire [7:0] FIFO_RD_addr;
wire [7:0] FIFO_WR_addr;
wire [1:0] fifo_state;
wire [8:0] DEPTH;
wire PL_EN, SW_CTRL;
wire [1:0] fifo_rd_en, fifo_wr_en;
wire [1:0] packet_count;
wire PL1_done;
wire [2:0] ip_fifo_sel;
wire [DATA_WIDTH-1:0] in_data_MC, in_data_PLDCF;
wire [CTRL_WIDTH-1:0] in_ctrl_MC, in_ctrl_PLDCF;
wire in_rdy_MC, in_rdy_PLDCF;
wire in_wr_MC, in_wr_PLDCF;
generic_regs
#(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (`MEM_BLOCK_ADDR),
.REG_ADDR_WIDTH (`MEM_REG_ADDR_WIDTH),
.NUM_COUNTERS (0),
.NUM_SOFTWARE_REGS (3),
.NUM_HARDWARE_REGS (4)
) module_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
.counter_updates (),
.counter_decrement(),
.software_regs ({cmd,Data_In}),
.hardware_regs ({26'h0,packet_count,PL_EN,SW_CTRL,fifo_state,fifo_rd_en,fifo_wr_en,FIFO_WR_addr,FIFO_RD_addr, full, empty, out_rdy, DEPTH, Data_out_DM}),
.clk (clk),
.reset (rst)
);
pipeline #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO(`Number_of_FIFO)
)
PL1
(
.in_data(in_data),
.in_ctrl(in_ctrl),
.out_data(in_data_MC),
.out_ctrl(in_ctrl_MC),
.out_rdy(in_rdy_MC),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(in_wr_MC),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.op_fifo_sel(ip_fifo_sel),
.PL_done(PL1_done),
.clk(clk),
.rst(rst)
);
master_ctrl #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO(`Number_of_FIFO)
)
UUT
(
.ip_fifo_sel(ip_fifo_sel),
.ip_PL_done(PL1_done),
.in_rdy(in_rdy_MC),
.in_wr(in_wr_MC),
.out_rdy(in_rdy_PLDCF),
.out_wr(in_wr_PLDCF),
.pckt_count(),
.state(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.pckt_rd_wr(),
.fifo_data_in(in_data_MC),
.fifo_data_out(in_data_PLDCF),
.fifo_ctrl_in(in_ctrl_MC),
.fifo_ctrl_out(in_ctrl_PLDCF),
.clk(clk),
.rst(rst)
);
pipeline_dualCF #(
.MAX_DEPTH(MAX_DEPTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO()
)
PL2
(
.in_data(in_data_PLDCF),
.in_ctrl(in_ctrl_PLDCF),
.out_data(out_data),
.out_ctrl(out_ctrl),
.out_rdy(out_rdy),
.in_wr(in_wr_PLDCF),
.in_rdy(in_rdy_PLDCF),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.Master_reg(),
.clk(clk),
.rst(rst)
);
assign MOD = {cmd[31],cmd[27]};
assign IorD = cmd[29];
assign Addr_in = cmd[8:0];
endmodule | module mem_mod_mast
#( parameter UDP_REG_SRC_WIDTH = 2,
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output in_rdy,
output out_wr,
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input clk,
input rst
); |
wire [31:0] cmd;
wire IorD;
wire [8:0] Addr_in;
wire [DATA_WIDTH-1:0] Data_In;
wire [DATA_WIDTH-1:0] Data_out_DM;
wire full,empty;
wire nearly_full,nearly_empty;
wire [7:0] FIFO_RD_addr;
wire [7:0] FIFO_WR_addr;
wire [1:0] fifo_state;
wire [8:0] DEPTH;
wire PL_EN, SW_CTRL;
wire [1:0] fifo_rd_en, fifo_wr_en;
wire [1:0] packet_count;
wire PL1_done;
wire [2:0] ip_fifo_sel;
wire [DATA_WIDTH-1:0] in_data_MC, in_data_PLDCF;
wire [CTRL_WIDTH-1:0] in_ctrl_MC, in_ctrl_PLDCF;
wire in_rdy_MC, in_rdy_PLDCF;
wire in_wr_MC, in_wr_PLDCF;
generic_regs
#(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (`MEM_BLOCK_ADDR),
.REG_ADDR_WIDTH (`MEM_REG_ADDR_WIDTH),
.NUM_COUNTERS (0),
.NUM_SOFTWARE_REGS (3),
.NUM_HARDWARE_REGS (4)
) module_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
.counter_updates (),
.counter_decrement(),
.software_regs ({cmd,Data_In}),
.hardware_regs ({26'h0,packet_count,PL_EN,SW_CTRL,fifo_state,fifo_rd_en,fifo_wr_en,FIFO_WR_addr,FIFO_RD_addr, full, empty, out_rdy, DEPTH, Data_out_DM}),
.clk (clk),
.reset (rst)
);
pipeline #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO(`Number_of_FIFO)
)
PL1
(
.in_data(in_data),
.in_ctrl(in_ctrl),
.out_data(in_data_MC),
.out_ctrl(in_ctrl_MC),
.out_rdy(in_rdy_MC),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(in_wr_MC),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.op_fifo_sel(ip_fifo_sel),
.PL_done(PL1_done),
.clk(clk),
.rst(rst)
);
master_ctrl #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO(`Number_of_FIFO)
)
UUT
(
.ip_fifo_sel(ip_fifo_sel),
.ip_PL_done(PL1_done),
.in_rdy(in_rdy_MC),
.in_wr(in_wr_MC),
.out_rdy(in_rdy_PLDCF),
.out_wr(in_wr_PLDCF),
.pckt_count(),
.state(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.pckt_rd_wr(),
.fifo_data_in(in_data_MC),
.fifo_data_out(in_data_PLDCF),
.fifo_ctrl_in(in_ctrl_MC),
.fifo_ctrl_out(in_ctrl_PLDCF),
.clk(clk),
.rst(rst)
);
pipeline_dualCF #(
.MAX_DEPTH(MAX_DEPTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.Number_of_FIFO()
)
PL2
(
.in_data(in_data_PLDCF),
.in_ctrl(in_ctrl_PLDCF),
.out_data(out_data),
.out_ctrl(out_ctrl),
.out_rdy(out_rdy),
.in_wr(in_wr_PLDCF),
.in_rdy(in_rdy_PLDCF),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.Master_reg(),
.clk(clk),
.rst(rst)
);
assign MOD = {cmd[31],cmd[27]};
assign IorD = cmd[29];
assign Addr_in = cmd[8:0];
endmodule | 0 |
3,363 | data/full_repos/permissive/104269513/mem_mod_master2_32bit - FinalFSM - final project_combined.v | 104,269,513 | mem_mod_master2_32bit - FinalFSM - final project_combined.v | v | 888 | 452 | [] | ['netfpga'] | [] | null | line:310: before: ")" | null | 1: b'%Error: Invalid Option: -\n' | 1,087 | module | module mem_mod_mast_tb();
reg [31:0] Data_In_hi,Data_In_lo;
reg [8:0] LD_A;
reg [17:0] DUMMY;
reg [31:0] reg_addr_data_out;
reg HW_RDY_in, I_D, R_W;
reg [1:0] MOD;
reg [31:0] Data_out_hi_DM, Data_out_lo_DM, Data_out_IM;
wire [31:0] reg_addr_data_in;
reg [12:0] dummy;
reg HW_RDY_out;
reg [8:0] A_IM, A_DM;
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
reg reg_req_out;
reg reg_ack_out;
reg reg_rd_wr_L_out;
reg [`UDP_REG_SRC_WIDTH-1:0] reg_src_out;
reg[`UDP_REG_ADDR_WIDTH-1:0] addr_out;
wire reg_req_in;
wire reg_ack_in;
wire reg_rd_wr_L_in;
wire[`UDP_REG_SRC_WIDTH-1:0] reg_src_in;
wire[`UDP_REG_ADDR_WIDTH-1:0] addr_in;
mem_mod_mast UUT (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.reg_req_in(reg_req_out),
.reg_ack_in(reg_ack_out),
.reg_rd_wr_L_in(reg_rd_wr_L_out),
.reg_addr_in(addr_out),
.reg_data_in(reg_addr_data_out),
.reg_src_in(reg_src_out),
.reg_req_out(reg_req_in),
.reg_ack_out(reg_ack_in),
.reg_rd_wr_L_out(reg_rd_wr_L_in),
.reg_addr_out(addr_in),
.reg_data_out(reg_addr_data_in),
.reg_src_out(reg_src_in),
.clk(clk),
.rst(rst)
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
LD_A = 'h0001;
Data_In_hi = 'h BAAB;
Data_In_lo = 'h ABBA;
reg_addr_data_out = 'h BEEF;
DUMMY = 'h 0;
dummy = 'h 0;
count = 0;
MOD = 'h0;
HW_RDY_in = 1;
I_D = 1;
R_W = 0;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
counter_restart = 25;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
fq = $fopen ("mem_mod_mast_tb_op.txt", "w");
if (!fq) $display ("Failed genrating output file");
end
always @ (posedge clk)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 0;
count <= count + 1;
if (count < 2)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h0 ;
reg_addr_data_out <= Data_In_lo;
end
else if (count < 3)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h1;
reg_addr_data_out <= Data_In_hi;
end
else if (count < 4)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h2;
reg_addr_data_out <= {MOD[1],HW_RDY_in,I_D,R_W,MOD[0],DUMMY,LD_A};
end
else if (count < 8)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h6;
end
else if (count < 9)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h5;
end
else if (count < 10)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h4;
end
else if (count < 11)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h3;
end
else if (count == 50 )
begin
out_rdy <= 0;
in_wr <= 0;
end
else if (count == 100)
out_rdy <= 1;
if (addr_in == 'h6) {dummy,HW_RDY_out,A_IM,A_DM} <= reg_addr_data_in;
if (addr_in == 'h5) Data_out_IM <= reg_addr_data_in;
if (addr_in == 'h4) Data_out_hi_DM <= reg_addr_data_in;
if (addr_in == 'h3) Data_out_lo_DM <= reg_addr_data_in;
if (count > 13)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
if (reg_req_in & reg_ack_in & reg_src_in == 0)
begin
$fdisplay (fq,"%d Success!! %h %h\t\t %h_%h",count,A_IM,A_DM, Data_out_hi_DM, Data_out_lo_DM);
end
else if (reg_req_in & !reg_ack_in & reg_src_in == 0)
begin
$fdisplay (fq,"Failed:( Ja mar ja");
end
else if (!reg_req_in)
begin
$fdisplay (fq,"Ab to Doob ke mar ja");
end
if (count == 40) $fclose(fq);
end
endmodule | module mem_mod_mast_tb(); |
reg [31:0] Data_In_hi,Data_In_lo;
reg [8:0] LD_A;
reg [17:0] DUMMY;
reg [31:0] reg_addr_data_out;
reg HW_RDY_in, I_D, R_W;
reg [1:0] MOD;
reg [31:0] Data_out_hi_DM, Data_out_lo_DM, Data_out_IM;
wire [31:0] reg_addr_data_in;
reg [12:0] dummy;
reg HW_RDY_out;
reg [8:0] A_IM, A_DM;
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
reg reg_req_out;
reg reg_ack_out;
reg reg_rd_wr_L_out;
reg [`UDP_REG_SRC_WIDTH-1:0] reg_src_out;
reg[`UDP_REG_ADDR_WIDTH-1:0] addr_out;
wire reg_req_in;
wire reg_ack_in;
wire reg_rd_wr_L_in;
wire[`UDP_REG_SRC_WIDTH-1:0] reg_src_in;
wire[`UDP_REG_ADDR_WIDTH-1:0] addr_in;
mem_mod_mast UUT (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.reg_req_in(reg_req_out),
.reg_ack_in(reg_ack_out),
.reg_rd_wr_L_in(reg_rd_wr_L_out),
.reg_addr_in(addr_out),
.reg_data_in(reg_addr_data_out),
.reg_src_in(reg_src_out),
.reg_req_out(reg_req_in),
.reg_ack_out(reg_ack_in),
.reg_rd_wr_L_out(reg_rd_wr_L_in),
.reg_addr_out(addr_in),
.reg_data_out(reg_addr_data_in),
.reg_src_out(reg_src_in),
.clk(clk),
.rst(rst)
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
LD_A = 'h0001;
Data_In_hi = 'h BAAB;
Data_In_lo = 'h ABBA;
reg_addr_data_out = 'h BEEF;
DUMMY = 'h 0;
dummy = 'h 0;
count = 0;
MOD = 'h0;
HW_RDY_in = 1;
I_D = 1;
R_W = 0;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
counter_restart = 25;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
fq = $fopen ("mem_mod_mast_tb_op.txt", "w");
if (!fq) $display ("Failed genrating output file");
end
always @ (posedge clk)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 0;
count <= count + 1;
if (count < 2)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h0 ;
reg_addr_data_out <= Data_In_lo;
end
else if (count < 3)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h1;
reg_addr_data_out <= Data_In_hi;
end
else if (count < 4)
begin
reg_rd_wr_L_out <= 0;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h2;
reg_addr_data_out <= {MOD[1],HW_RDY_in,I_D,R_W,MOD[0],DUMMY,LD_A};
end
else if (count < 8)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h6;
end
else if (count < 9)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h5;
end
else if (count < 10)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h4;
end
else if (count < 11)
begin
reg_rd_wr_L_out <= 1;
reg_req_out <= 1;
reg_ack_out <= 0;
reg_src_out <= 2'b00;
addr_out <= 'h3;
end
else if (count == 50 )
begin
out_rdy <= 0;
in_wr <= 0;
end
else if (count == 100)
out_rdy <= 1;
if (addr_in == 'h6) {dummy,HW_RDY_out,A_IM,A_DM} <= reg_addr_data_in;
if (addr_in == 'h5) Data_out_IM <= reg_addr_data_in;
if (addr_in == 'h4) Data_out_hi_DM <= reg_addr_data_in;
if (addr_in == 'h3) Data_out_lo_DM <= reg_addr_data_in;
if (count > 13)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
if (reg_req_in & reg_ack_in & reg_src_in == 0)
begin
$fdisplay (fq,"%d Success!! %h %h\t\t %h_%h",count,A_IM,A_DM, Data_out_hi_DM, Data_out_lo_DM);
end
else if (reg_req_in & !reg_ack_in & reg_src_in == 0)
begin
$fdisplay (fq,"Failed:( Ja mar ja");
end
else if (!reg_req_in)
begin
$fdisplay (fq,"Ab to Doob ke mar ja");
end
if (count == 40) $fclose(fq);
end
endmodule | 0 |
3,364 | data/full_repos/permissive/104269513/pipeline.v | 104,269,513 | pipeline.v | v | 481 | 452 | [] | [] | [] | null | line:135: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:410: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:415: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'op_fifo_sel\'\npipeline PL (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'PL_done\'\npipeline PL (\n ^~\n%Error: data/full_repos/permissive/104269513/pipeline.v:145: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline.v:191: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:199: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:215: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:393: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,088 | module | module pipeline #(
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 5
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output in_rdy,
output out_wr,
input IorD,
input [8:0] Addr_in,
input [DATA_WIDTH-1:0] Data_In,
output [8:0] Addr_DM,
output [8:0] Addr_IM,
output [31:0] Data_out_IM,
output [DATA_WIDTH-1:0] Data_out_DM,
output full,
output empty,
output fifo_busy,
output [1:0] packet_count,
output [ADDR_WIDTH-1:0] FIFO_RD_addr,
output [ADDR_WIDTH-1:0] FIFO_WR_addr,
output [1:0] fifo_state,
output [ADDR_WIDTH:0] DEPTH,
output reg PL_EN,
output reg SW_CTRL,
output reg fifo_rd_en,
output reg fifo_wr_en,
output [log2(Number_of_FIFO)-1:0] op_fifo_sel,
output reg PL_done,
input clk,
input rst
);
reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina, PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;
reg PL_done_next;
wire PL_done_raw;
wire [63:0] EX_ALU_in1,EX_ALU_in2;
wire [63:0] EX_ALU_out;
wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg fifo_rd_en_next;
reg fifo_wr_en_next;
wire [ADDR_WIDTH-1:0] first_word;
wire pckt_rd_wr_next;
reg pckt_rd_wr;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
datapath dp (
.clk(clk),
.rst(rst),
.pipeline_en(PL_EN),
.sw_ctrl(SW_CTRL),
.IorD(IorD),
.WorR(R_W_EN),
.MEM_PL_done(PL_done_raw),
.Addr_in(Addr_in),
.Data_in(Data_In),
.IM_Addr_out(Addr_IM),
.DM_Addr_out(Addr_DM),
.IM_Data_out(Data_out_IM),
.DM_Data_out(Data_out_DM),
.Data_mem_wea (DM_wea),
.Data_mem_dina (PL_Data_mem_dina),
.Data_mem_addr (PL_Addr_DM),
.MEM_Dout(PL_MEM_dout),
.first_word(first_word),
.EX_ALU_in1(EX_ALU_in1),
.EX_ALU_in2(EX_ALU_in2),
.EX_ALU_out(EX_ALU_out),
.EX_ALUop(EX_ALUop),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.ALUop(ALUop),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld)
);
ALU_ctrl EX_ALU (
.A(EX_ALU_in1),
.B(EX_ALU_in2),
.cmd(EX_ALUop),
.psw(),
.Data_out(EX_ALU_out)
);
control ctrl (
.instruction(Data_out_IM),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld),
.ALUop(ALUop),
.Master_reg(op_fifo_sel),
.mem_sel()
);
convert_fifo fifo_dm (
.fifo_rd_en(fifo_rd_en),
.fifo_wr_en(fifo_wr_en),
.out_rdy(out_rdy),
.in_wr(in_wr),
.out_wr(out_wr),
.pckt_rd_wr(pckt_rd_wr_next),
.in_rdy(in_rdy),
.full(full),
.empty(empty),
.nearly_full(),
.nearly_empty(),
.packet_count(packet_count),
.first_word(first_word),
.last_word(),
.fifo_busy(fifo_busy),
.fifo_data_in(in_data),
.fifo_data_out(out_data),
.fifo_ctrl_in(in_ctrl),
.fifo_ctrl_out(out_ctrl),
.PL_A_DM(PL_Addr_DM),
.PL_Data_mem_dina(PL_Data_mem_dina),
.DM_wea(DM_wea),
.PL_MEM_dout(PL_MEM_dout),
.addrb(FIFO_RD_addr),
.addra(FIFO_WR_addr),
.state (fifo_state),
.DEPTH (DEPTH),
.clk(clk),
.rst(rst)
);
always @ *
begin
PL_EN_next = 'b0;
SW_CTRL_next = 'b0;
R_W_EN_next = 'b1;
fifo_rd_en_next = 'b0;
fifo_wr_en_next = 'b0;
PL_done_next = PL_done;
if (PL_done_raw & !pckt_rd_wr_next)
PL_done_next = 1;
if (PL_done_raw & !pckt_rd_wr_next)
PL_done_next = 0;
if (PL_done & pckt_rd_wr)
begin
fifo_wr_en_next = 'b1;
PL_done_next = pckt_rd_wr_next;
end
if (!PL_done & !pckt_rd_wr)
begin
PL_EN_next = 'b1;
PL_done_next = PL_done_raw;
end
if (PL_done & !pckt_rd_wr)
begin
fifo_rd_en_next = 'b1;
end
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
PL_EN <= 0;
SW_CTRL <= 0;
R_W_EN <= 1;
fifo_rd_en <= 0;
fifo_wr_en <= 0;
PL_done <= 'h1;
pckt_rd_wr <= 'h1;
end
else
begin
PL_EN <= PL_EN_next;
SW_CTRL <= SW_CTRL_next;
R_W_EN <= R_W_EN_next;
fifo_rd_en <= fifo_rd_en_next;
fifo_wr_en <= fifo_wr_en_next;
PL_done <= PL_done_next;
pckt_rd_wr <= pckt_rd_wr_next;
end
end
endmodule | module pipeline #(
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 5
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output in_rdy,
output out_wr,
input IorD,
input [8:0] Addr_in,
input [DATA_WIDTH-1:0] Data_In,
output [8:0] Addr_DM,
output [8:0] Addr_IM,
output [31:0] Data_out_IM,
output [DATA_WIDTH-1:0] Data_out_DM,
output full,
output empty,
output fifo_busy,
output [1:0] packet_count,
output [ADDR_WIDTH-1:0] FIFO_RD_addr,
output [ADDR_WIDTH-1:0] FIFO_WR_addr,
output [1:0] fifo_state,
output [ADDR_WIDTH:0] DEPTH,
output reg PL_EN,
output reg SW_CTRL,
output reg fifo_rd_en,
output reg fifo_wr_en,
output [log2(Number_of_FIFO)-1:0] op_fifo_sel,
output reg PL_done,
input clk,
input rst
); |
reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina, PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;
reg PL_done_next;
wire PL_done_raw;
wire [63:0] EX_ALU_in1,EX_ALU_in2;
wire [63:0] EX_ALU_out;
wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg fifo_rd_en_next;
reg fifo_wr_en_next;
wire [ADDR_WIDTH-1:0] first_word;
wire pckt_rd_wr_next;
reg pckt_rd_wr;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
datapath dp (
.clk(clk),
.rst(rst),
.pipeline_en(PL_EN),
.sw_ctrl(SW_CTRL),
.IorD(IorD),
.WorR(R_W_EN),
.MEM_PL_done(PL_done_raw),
.Addr_in(Addr_in),
.Data_in(Data_In),
.IM_Addr_out(Addr_IM),
.DM_Addr_out(Addr_DM),
.IM_Data_out(Data_out_IM),
.DM_Data_out(Data_out_DM),
.Data_mem_wea (DM_wea),
.Data_mem_dina (PL_Data_mem_dina),
.Data_mem_addr (PL_Addr_DM),
.MEM_Dout(PL_MEM_dout),
.first_word(first_word),
.EX_ALU_in1(EX_ALU_in1),
.EX_ALU_in2(EX_ALU_in2),
.EX_ALU_out(EX_ALU_out),
.EX_ALUop(EX_ALUop),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.ALUop(ALUop),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld)
);
ALU_ctrl EX_ALU (
.A(EX_ALU_in1),
.B(EX_ALU_in2),
.cmd(EX_ALUop),
.psw(),
.Data_out(EX_ALU_out)
);
control ctrl (
.instruction(Data_out_IM),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld),
.ALUop(ALUop),
.Master_reg(op_fifo_sel),
.mem_sel()
);
convert_fifo fifo_dm (
.fifo_rd_en(fifo_rd_en),
.fifo_wr_en(fifo_wr_en),
.out_rdy(out_rdy),
.in_wr(in_wr),
.out_wr(out_wr),
.pckt_rd_wr(pckt_rd_wr_next),
.in_rdy(in_rdy),
.full(full),
.empty(empty),
.nearly_full(),
.nearly_empty(),
.packet_count(packet_count),
.first_word(first_word),
.last_word(),
.fifo_busy(fifo_busy),
.fifo_data_in(in_data),
.fifo_data_out(out_data),
.fifo_ctrl_in(in_ctrl),
.fifo_ctrl_out(out_ctrl),
.PL_A_DM(PL_Addr_DM),
.PL_Data_mem_dina(PL_Data_mem_dina),
.DM_wea(DM_wea),
.PL_MEM_dout(PL_MEM_dout),
.addrb(FIFO_RD_addr),
.addra(FIFO_WR_addr),
.state (fifo_state),
.DEPTH (DEPTH),
.clk(clk),
.rst(rst)
);
always @ *
begin
PL_EN_next = 'b0;
SW_CTRL_next = 'b0;
R_W_EN_next = 'b1;
fifo_rd_en_next = 'b0;
fifo_wr_en_next = 'b0;
PL_done_next = PL_done;
if (PL_done_raw & !pckt_rd_wr_next)
PL_done_next = 1;
if (PL_done_raw & !pckt_rd_wr_next)
PL_done_next = 0;
if (PL_done & pckt_rd_wr)
begin
fifo_wr_en_next = 'b1;
PL_done_next = pckt_rd_wr_next;
end
if (!PL_done & !pckt_rd_wr)
begin
PL_EN_next = 'b1;
PL_done_next = PL_done_raw;
end
if (PL_done & !pckt_rd_wr)
begin
fifo_rd_en_next = 'b1;
end
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
PL_EN <= 0;
SW_CTRL <= 0;
R_W_EN <= 1;
fifo_rd_en <= 0;
fifo_wr_en <= 0;
PL_done <= 'h1;
pckt_rd_wr <= 'h1;
end
else
begin
PL_EN <= PL_EN_next;
SW_CTRL <= SW_CTRL_next;
R_W_EN <= R_W_EN_next;
fifo_rd_en <= fifo_rd_en_next;
fifo_wr_en <= fifo_wr_en_next;
PL_done <= PL_done_next;
pckt_rd_wr <= pckt_rd_wr_next;
end
end
endmodule | 0 |
3,365 | data/full_repos/permissive/104269513/pipeline.v | 104,269,513 | pipeline.v | v | 481 | 452 | [] | [] | [] | null | line:135: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:410: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:415: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'op_fifo_sel\'\npipeline PL (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'PL_done\'\npipeline PL (\n ^~\n%Error: data/full_repos/permissive/104269513/pipeline.v:145: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline.v:191: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:199: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:215: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:393: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,088 | module | module pipeline_tb();
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
pipeline PL (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
count = 0;
out_rdy = 1;
in_wr = 0;
counter_restart = 25;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end
always @ (posedge clk)
begin
count <= count + 1;
if (count > 2)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
else if (count == 200 )
begin
out_rdy <= 0;
in_wr <= 0;
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
end
endmodule | module pipeline_tb(); |
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
pipeline PL (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
count = 0;
out_rdy = 1;
in_wr = 0;
counter_restart = 25;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end
always @ (posedge clk)
begin
count <= count + 1;
if (count > 2)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
else if (count == 200 )
begin
out_rdy <= 0;
in_wr <= 0;
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
end
endmodule | 0 |
3,366 | data/full_repos/permissive/104269513/pipeline.v | 104,269,513 | pipeline.v | v | 481 | 452 | [] | [] | [] | null | line:135: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:410: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:415: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'op_fifo_sel\'\npipeline PL (\n ^~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'PL_done\'\npipeline PL (\n ^~\n%Error: data/full_repos/permissive/104269513/pipeline.v:145: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline.v:191: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:199: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:215: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:393: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,088 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 0 |
3,367 | data/full_repos/permissive/104269513/pipeline_dualCF.v | 104,269,513 | pipeline_dualCF.v | v | 762 | 452 | [] | [] | [] | null | line:168: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:691: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:696: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:177: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:223: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:231: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:294: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:674: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,089 | module | module pipeline_dualCF #(
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 2
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output reg in_rdy,
output reg out_wr,
input IorD,
input [8:0] Addr_in,
input [DATA_WIDTH-1:0] Data_In,
output [8:0] Addr_DM,
output [8:0] Addr_IM,
output [31:0] Data_out_IM,
output [DATA_WIDTH-1:0] Data_out_DM,
output reg full,
output reg nearly_full,
output reg nearly_empty,
output reg empty,
output reg fifo_busy,
output reg [1:0] packet_count,
output reg [ADDR_WIDTH-1:0] FIFO_RD_addr,
output reg [ADDR_WIDTH-1:0] FIFO_WR_addr,
output reg [1:0] fifo_state,
output reg [ADDR_WIDTH:0] DEPTH,
output reg PL_EN,
output reg SW_CTRL,
output reg [Number_of_FIFO-1:0] fifo_rd_en,
output reg [Number_of_FIFO-1:0] fifo_wr_en,
output reg [Number_of_FIFO-1:0] Master_reg,
input clk,
input rst
);
reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
reg [15:0] counter,counter_next;
wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina;
reg [DATA_WIDTH-1:0] PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;
reg PL_done_next;
wire PL_done_raw;
reg PL_done;
wire [DATA_WIDTH-1:0] EX_ALU_in1,EX_ALU_in2;
wire [DATA_WIDTH-1:0] EX_ALU_out;
wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg [log2(Number_of_FIFO)-1:0] fifo_mem_sel;
reg [log2(Number_of_FIFO)-1:0] fifo_sel, fifo_sel_next;
wire [log2(Number_of_FIFO)-1:0] mem_sel;
reg [Number_of_FIFO-1:0] fifo_rd_en_next;
reg [Number_of_FIFO-1:0] fifo_wr_en_next;
reg [ADDR_WIDTH-1:0] first_word;
wire [Number_of_FIFO-1:0] pckt_rd_wr_next;
reg [Number_of_FIFO-1:0] pckt_rd_wr;
wire [DATA_WIDTH-1:0] cf_out_data [Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] cf_out_ctrl [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_out_rdy;
reg [Number_of_FIFO-1:0] cf_in_wr;
wire [Number_of_FIFO-1:0] cf_in_rdy;
wire [Number_of_FIFO-1:0] cf_out_wr;
wire [Number_of_FIFO-1:0] cf_full;
wire [Number_of_FIFO-1:0] cf_nearly_full;
wire [Number_of_FIFO-1:0] cf_nearly_empty;
wire [Number_of_FIFO-1:0] cf_empty;
wire [Number_of_FIFO-1:0] cf_fifo_busy;
wire [1:0] cf_packet_count [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_RD_addr [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_WR_addr [Number_of_FIFO-1:0];
wire [1:0] cf_fifo_state [Number_of_FIFO-1:0];
wire [ADDR_WIDTH:0] cf_DEPTH [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_first_word [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_DM_wea;
wire [DATA_WIDTH-1:0] cf_PL_MEM_dout [Number_of_FIFO-1:0];
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
datapath dp (
.clk(clk),
.rst(rst),
.pipeline_en(PL_EN),
.sw_ctrl(SW_CTRL),
.IorD(IorD),
.WorR(R_W_EN),
.MEM_PL_done(PL_done_raw),
.Addr_in(Addr_in),
.Data_in(Data_In),
.IM_Addr_out(Addr_IM),
.DM_Addr_out(Addr_DM),
.IM_Data_out(Data_out_IM),
.DM_Data_out(Data_out_DM),
.Data_mem_wea (DM_wea),
.Data_mem_dina (PL_Data_mem_dina),
.Data_mem_addr (PL_Addr_DM),
.MEM_Dout(PL_MEM_dout),
.first_word(first_word),
.EX_ALU_in1(EX_ALU_in1),
.EX_ALU_in2(EX_ALU_in2),
.EX_ALU_out(EX_ALU_out),
.EX_ALUop(EX_ALUop),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.ALUop(ALUop),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld)
);
ALU_ctrl EX_ALU (
.A(EX_ALU_in1),
.B(EX_ALU_in2),
.cmd(EX_ALUop),
.psw(),
.Data_out(EX_ALU_out)
);
control ctrl (
.instruction(Data_out_IM),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld),
.ALUop(ALUop),
.Master_reg(),
.mem_sel(mem_sel)
);
genvar i;
generate
for (i=0 ; i<Number_of_FIFO ; i = i+1)
begin: CF
convert_fifo fifo_dm (
.fifo_rd_en(fifo_rd_en[i]),
.fifo_wr_en(fifo_wr_en[i]),
.out_rdy(cf_out_rdy[i]),
.in_wr(cf_in_wr[i]),
.out_wr(cf_out_wr[i]),
.pckt_rd_wr(pckt_rd_wr_next[i]),
.in_rdy(cf_in_rdy[i]),
.full(cf_full[i]),
.empty(cf_empty[i]),
.nearly_full(cf_nearly_full[i]),
.nearly_empty(cf_nearly_empty[i]),
.packet_count(cf_packet_count[i]),
.first_word(cf_first_word[i]),
.last_word(),
.fifo_busy(cf_fifo_busy[i]),
.fifo_data_in(in_data),
.fifo_data_out(cf_out_data[i]),
.fifo_ctrl_in(in_ctrl),
.fifo_ctrl_out(cf_out_ctrl[i]),
.PL_A_DM(PL_Addr_DM),
.PL_Data_mem_dina(PL_Data_mem_dina),
.DM_wea(cf_DM_wea[i]),
.PL_MEM_dout(cf_PL_MEM_dout[i]),
.addrb(cf_FIFO_RD_addr[i]),
.addra(cf_FIFO_WR_addr[i]),
.state (cf_fifo_state[i]),
.DEPTH (cf_DEPTH[i]),
.clk(clk),
.rst(rst)
);
end
endgenerate
always @ *
begin
cf_out_rdy[0] = 'b0;
cf_in_wr[0] = 'b0;
cf_DM_wea[0] = 'b0;
cf_out_rdy[1] = 'b0;
cf_in_wr[1] = 'b0;
cf_DM_wea[1] = 'b0;
out_wr = cf_out_wr[0];
case(fifo_mem_sel)
'h0:begin
cf_out_rdy[0] = out_rdy;
cf_in_wr[0] = in_wr;
in_rdy = cf_in_rdy[0];
full = cf_full[0];
nearly_full = cf_nearly_full[0];
nearly_empty = cf_nearly_empty[0];
empty = cf_empty[0];
fifo_busy = cf_fifo_busy[0];
cf_DM_wea[0] = DM_wea;
end
'h1:begin
cf_out_rdy[1] = out_rdy;
cf_in_wr[1] = in_wr;
in_rdy = cf_in_rdy[1];
full = cf_full[1];
nearly_full = cf_nearly_full[1];
nearly_empty = cf_nearly_empty[1];
empty = cf_empty[1];
fifo_busy = cf_fifo_busy[1];
cf_DM_wea[1] = DM_wea;
end
default:begin
cf_out_rdy[0] = out_rdy;
cf_in_wr[0] = in_wr;
in_rdy = cf_in_rdy[0];
out_wr = cf_out_wr[0];
full = cf_full[0];
nearly_full = cf_nearly_full[0];
nearly_empty = cf_nearly_empty[0];
empty = cf_empty[0];
fifo_busy = cf_fifo_busy[0];
cf_DM_wea[0] = DM_wea;
end
endcase
end
always @ (fifo_mem_sel,cf_out_data [0], cf_out_ctrl [0], cf_packet_count[0], cf_FIFO_RD_addr[0], cf_FIFO_WR_addr[0],cf_fifo_state[0], cf_DEPTH[0],cf_first_word [0], cf_PL_MEM_dout [0],cf_out_data [1], cf_out_ctrl [1], cf_packet_count[1], cf_FIFO_RD_addr[1], cf_FIFO_WR_addr[1],cf_fifo_state[1], cf_DEPTH[1],cf_first_word [1], cf_PL_MEM_dout [1])
begin
out_data = cf_out_data [0];
out_ctrl = cf_out_ctrl [0];
case(fifo_mem_sel)
'h0:begin
packet_count = cf_packet_count[0];
FIFO_RD_addr = cf_FIFO_RD_addr[0];
FIFO_WR_addr = cf_FIFO_WR_addr[0];
fifo_state = cf_fifo_state[0];
DEPTH = cf_DEPTH[0];
first_word = cf_first_word [0];
PL_MEM_dout = cf_PL_MEM_dout [0];
end
'h1:begin
packet_count = cf_packet_count[1];
FIFO_RD_addr = cf_FIFO_RD_addr[1];
FIFO_WR_addr = cf_FIFO_WR_addr[1];
fifo_state = cf_fifo_state[1];
DEPTH = cf_DEPTH[1];
first_word = cf_first_word [1];
PL_MEM_dout = cf_PL_MEM_dout [1];
end
default:begin
out_data = cf_out_data [0];
out_ctrl = cf_out_ctrl [0];
packet_count = cf_packet_count[0];
FIFO_RD_addr = cf_FIFO_RD_addr[0];
FIFO_WR_addr = cf_FIFO_WR_addr[0];
fifo_state = cf_fifo_state[0];
DEPTH = cf_DEPTH[0];
first_word = cf_first_word [0];
PL_MEM_dout = cf_PL_MEM_dout [0];
end
endcase
end
always @ *
begin
PL_EN_next = 'b0;
SW_CTRL_next = 'b0;
R_W_EN_next = 'b1;
fifo_rd_en_next[0] = 'b0;
fifo_rd_en_next[1] = 'b0;
fifo_wr_en_next[0] = 'b0;
fifo_wr_en_next[1] = 'b0;
PL_done_next = PL_done;
fifo_sel_next = 'h0;
counter_next = counter + 1;
if(counter < 'h4000)
begin
if (PL_done & pckt_rd_wr[0] & pckt_rd_wr[1])
begin
fifo_wr_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
if (PL_done & !pckt_rd_wr[0] & pckt_rd_wr[1])
begin
fifo_wr_en_next[1] = 'b1;
PL_done_next = pckt_rd_wr_next[1];
fifo_sel_next = 'h1;
end
if (!PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
PL_EN_next = 'b1;
PL_done_next = PL_done_raw;
end
if (PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
fifo_rd_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
if (PL_done & pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
fifo_rd_en_next[1] = 'b1;
fifo_sel_next = 'h1;
counter_next = 'h0;
end
end
else
begin
if (!pckt_rd_wr[0])
begin
fifo_rd_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
else if (!pckt_rd_wr[1])
begin
fifo_rd_en_next[1] = 'b1;
fifo_sel_next = 'h1;
end
else counter_next = 'h0;
end
if (PL_EN)
fifo_mem_sel = mem_sel;
else
fifo_mem_sel = fifo_sel;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
counter <= 'h0;
PL_EN <= 0;
SW_CTRL <= 0;
R_W_EN <= 1;
fifo_rd_en[0] <= 0;
fifo_rd_en[1] <= 0;
fifo_wr_en[0] <= 0;
fifo_wr_en[1] <= 0;
PL_done <= 'h1;
pckt_rd_wr[0] <= 'h1;
pckt_rd_wr[1] <= 'h1;
fifo_sel <= 'h0;
end
else
begin
counter <= counter_next;
PL_EN <= PL_EN_next;
SW_CTRL <= SW_CTRL_next;
R_W_EN <= R_W_EN_next;
fifo_rd_en[0] <= fifo_rd_en_next[0];
fifo_rd_en[1] <= fifo_rd_en_next[1];
fifo_wr_en[0] <= fifo_wr_en_next[0];
fifo_wr_en[1] <= fifo_wr_en_next[1];
PL_done <= PL_done_next;
pckt_rd_wr[0] <= pckt_rd_wr_next[0];
pckt_rd_wr[1] <= pckt_rd_wr_next[1];
fifo_sel <= fifo_sel_next;
end
end
endmodule | module pipeline_dualCF #(
parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter Number_of_FIFO = 2
)
(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
input out_rdy,
input in_wr,
output reg in_rdy,
output reg out_wr,
input IorD,
input [8:0] Addr_in,
input [DATA_WIDTH-1:0] Data_In,
output [8:0] Addr_DM,
output [8:0] Addr_IM,
output [31:0] Data_out_IM,
output [DATA_WIDTH-1:0] Data_out_DM,
output reg full,
output reg nearly_full,
output reg nearly_empty,
output reg empty,
output reg fifo_busy,
output reg [1:0] packet_count,
output reg [ADDR_WIDTH-1:0] FIFO_RD_addr,
output reg [ADDR_WIDTH-1:0] FIFO_WR_addr,
output reg [1:0] fifo_state,
output reg [ADDR_WIDTH:0] DEPTH,
output reg PL_EN,
output reg SW_CTRL,
output reg [Number_of_FIFO-1:0] fifo_rd_en,
output reg [Number_of_FIFO-1:0] fifo_wr_en,
output reg [Number_of_FIFO-1:0] Master_reg,
input clk,
input rst
); |
reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
reg [15:0] counter,counter_next;
wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina;
reg [DATA_WIDTH-1:0] PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;
reg PL_done_next;
wire PL_done_raw;
reg PL_done;
wire [DATA_WIDTH-1:0] EX_ALU_in1,EX_ALU_in2;
wire [DATA_WIDTH-1:0] EX_ALU_out;
wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg [log2(Number_of_FIFO)-1:0] fifo_mem_sel;
reg [log2(Number_of_FIFO)-1:0] fifo_sel, fifo_sel_next;
wire [log2(Number_of_FIFO)-1:0] mem_sel;
reg [Number_of_FIFO-1:0] fifo_rd_en_next;
reg [Number_of_FIFO-1:0] fifo_wr_en_next;
reg [ADDR_WIDTH-1:0] first_word;
wire [Number_of_FIFO-1:0] pckt_rd_wr_next;
reg [Number_of_FIFO-1:0] pckt_rd_wr;
wire [DATA_WIDTH-1:0] cf_out_data [Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] cf_out_ctrl [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_out_rdy;
reg [Number_of_FIFO-1:0] cf_in_wr;
wire [Number_of_FIFO-1:0] cf_in_rdy;
wire [Number_of_FIFO-1:0] cf_out_wr;
wire [Number_of_FIFO-1:0] cf_full;
wire [Number_of_FIFO-1:0] cf_nearly_full;
wire [Number_of_FIFO-1:0] cf_nearly_empty;
wire [Number_of_FIFO-1:0] cf_empty;
wire [Number_of_FIFO-1:0] cf_fifo_busy;
wire [1:0] cf_packet_count [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_RD_addr [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_WR_addr [Number_of_FIFO-1:0];
wire [1:0] cf_fifo_state [Number_of_FIFO-1:0];
wire [ADDR_WIDTH:0] cf_DEPTH [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_first_word [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_DM_wea;
wire [DATA_WIDTH-1:0] cf_PL_MEM_dout [Number_of_FIFO-1:0];
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
datapath dp (
.clk(clk),
.rst(rst),
.pipeline_en(PL_EN),
.sw_ctrl(SW_CTRL),
.IorD(IorD),
.WorR(R_W_EN),
.MEM_PL_done(PL_done_raw),
.Addr_in(Addr_in),
.Data_in(Data_In),
.IM_Addr_out(Addr_IM),
.DM_Addr_out(Addr_DM),
.IM_Data_out(Data_out_IM),
.DM_Data_out(Data_out_DM),
.Data_mem_wea (DM_wea),
.Data_mem_dina (PL_Data_mem_dina),
.Data_mem_addr (PL_Addr_DM),
.MEM_Dout(PL_MEM_dout),
.first_word(first_word),
.EX_ALU_in1(EX_ALU_in1),
.EX_ALU_in2(EX_ALU_in2),
.EX_ALU_out(EX_ALU_out),
.EX_ALUop(EX_ALUop),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.ALUop(ALUop),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld)
);
ALU_ctrl EX_ALU (
.A(EX_ALU_in1),
.B(EX_ALU_in2),
.cmd(EX_ALUop),
.psw(),
.Data_out(EX_ALU_out)
);
control ctrl (
.instruction(Data_out_IM),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.ble(ble),
.imme(imme),
.PL_done(PL_done_ctrl),
.FW_ld (FW_ld),
.ALUop(ALUop),
.Master_reg(),
.mem_sel(mem_sel)
);
genvar i;
generate
for (i=0 ; i<Number_of_FIFO ; i = i+1)
begin: CF
convert_fifo fifo_dm (
.fifo_rd_en(fifo_rd_en[i]),
.fifo_wr_en(fifo_wr_en[i]),
.out_rdy(cf_out_rdy[i]),
.in_wr(cf_in_wr[i]),
.out_wr(cf_out_wr[i]),
.pckt_rd_wr(pckt_rd_wr_next[i]),
.in_rdy(cf_in_rdy[i]),
.full(cf_full[i]),
.empty(cf_empty[i]),
.nearly_full(cf_nearly_full[i]),
.nearly_empty(cf_nearly_empty[i]),
.packet_count(cf_packet_count[i]),
.first_word(cf_first_word[i]),
.last_word(),
.fifo_busy(cf_fifo_busy[i]),
.fifo_data_in(in_data),
.fifo_data_out(cf_out_data[i]),
.fifo_ctrl_in(in_ctrl),
.fifo_ctrl_out(cf_out_ctrl[i]),
.PL_A_DM(PL_Addr_DM),
.PL_Data_mem_dina(PL_Data_mem_dina),
.DM_wea(cf_DM_wea[i]),
.PL_MEM_dout(cf_PL_MEM_dout[i]),
.addrb(cf_FIFO_RD_addr[i]),
.addra(cf_FIFO_WR_addr[i]),
.state (cf_fifo_state[i]),
.DEPTH (cf_DEPTH[i]),
.clk(clk),
.rst(rst)
);
end
endgenerate
always @ *
begin
cf_out_rdy[0] = 'b0;
cf_in_wr[0] = 'b0;
cf_DM_wea[0] = 'b0;
cf_out_rdy[1] = 'b0;
cf_in_wr[1] = 'b0;
cf_DM_wea[1] = 'b0;
out_wr = cf_out_wr[0];
case(fifo_mem_sel)
'h0:begin
cf_out_rdy[0] = out_rdy;
cf_in_wr[0] = in_wr;
in_rdy = cf_in_rdy[0];
full = cf_full[0];
nearly_full = cf_nearly_full[0];
nearly_empty = cf_nearly_empty[0];
empty = cf_empty[0];
fifo_busy = cf_fifo_busy[0];
cf_DM_wea[0] = DM_wea;
end
'h1:begin
cf_out_rdy[1] = out_rdy;
cf_in_wr[1] = in_wr;
in_rdy = cf_in_rdy[1];
full = cf_full[1];
nearly_full = cf_nearly_full[1];
nearly_empty = cf_nearly_empty[1];
empty = cf_empty[1];
fifo_busy = cf_fifo_busy[1];
cf_DM_wea[1] = DM_wea;
end
default:begin
cf_out_rdy[0] = out_rdy;
cf_in_wr[0] = in_wr;
in_rdy = cf_in_rdy[0];
out_wr = cf_out_wr[0];
full = cf_full[0];
nearly_full = cf_nearly_full[0];
nearly_empty = cf_nearly_empty[0];
empty = cf_empty[0];
fifo_busy = cf_fifo_busy[0];
cf_DM_wea[0] = DM_wea;
end
endcase
end
always @ (fifo_mem_sel,cf_out_data [0], cf_out_ctrl [0], cf_packet_count[0], cf_FIFO_RD_addr[0], cf_FIFO_WR_addr[0],cf_fifo_state[0], cf_DEPTH[0],cf_first_word [0], cf_PL_MEM_dout [0],cf_out_data [1], cf_out_ctrl [1], cf_packet_count[1], cf_FIFO_RD_addr[1], cf_FIFO_WR_addr[1],cf_fifo_state[1], cf_DEPTH[1],cf_first_word [1], cf_PL_MEM_dout [1])
begin
out_data = cf_out_data [0];
out_ctrl = cf_out_ctrl [0];
case(fifo_mem_sel)
'h0:begin
packet_count = cf_packet_count[0];
FIFO_RD_addr = cf_FIFO_RD_addr[0];
FIFO_WR_addr = cf_FIFO_WR_addr[0];
fifo_state = cf_fifo_state[0];
DEPTH = cf_DEPTH[0];
first_word = cf_first_word [0];
PL_MEM_dout = cf_PL_MEM_dout [0];
end
'h1:begin
packet_count = cf_packet_count[1];
FIFO_RD_addr = cf_FIFO_RD_addr[1];
FIFO_WR_addr = cf_FIFO_WR_addr[1];
fifo_state = cf_fifo_state[1];
DEPTH = cf_DEPTH[1];
first_word = cf_first_word [1];
PL_MEM_dout = cf_PL_MEM_dout [1];
end
default:begin
out_data = cf_out_data [0];
out_ctrl = cf_out_ctrl [0];
packet_count = cf_packet_count[0];
FIFO_RD_addr = cf_FIFO_RD_addr[0];
FIFO_WR_addr = cf_FIFO_WR_addr[0];
fifo_state = cf_fifo_state[0];
DEPTH = cf_DEPTH[0];
first_word = cf_first_word [0];
PL_MEM_dout = cf_PL_MEM_dout [0];
end
endcase
end
always @ *
begin
PL_EN_next = 'b0;
SW_CTRL_next = 'b0;
R_W_EN_next = 'b1;
fifo_rd_en_next[0] = 'b0;
fifo_rd_en_next[1] = 'b0;
fifo_wr_en_next[0] = 'b0;
fifo_wr_en_next[1] = 'b0;
PL_done_next = PL_done;
fifo_sel_next = 'h0;
counter_next = counter + 1;
if(counter < 'h4000)
begin
if (PL_done & pckt_rd_wr[0] & pckt_rd_wr[1])
begin
fifo_wr_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
if (PL_done & !pckt_rd_wr[0] & pckt_rd_wr[1])
begin
fifo_wr_en_next[1] = 'b1;
PL_done_next = pckt_rd_wr_next[1];
fifo_sel_next = 'h1;
end
if (!PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
PL_EN_next = 'b1;
PL_done_next = PL_done_raw;
end
if (PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
fifo_rd_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
if (PL_done & pckt_rd_wr[0] & !pckt_rd_wr[1])
begin
fifo_rd_en_next[1] = 'b1;
fifo_sel_next = 'h1;
counter_next = 'h0;
end
end
else
begin
if (!pckt_rd_wr[0])
begin
fifo_rd_en_next[0] = 'b1;
fifo_sel_next = 'h0;
end
else if (!pckt_rd_wr[1])
begin
fifo_rd_en_next[1] = 'b1;
fifo_sel_next = 'h1;
end
else counter_next = 'h0;
end
if (PL_EN)
fifo_mem_sel = mem_sel;
else
fifo_mem_sel = fifo_sel;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
counter <= 'h0;
PL_EN <= 0;
SW_CTRL <= 0;
R_W_EN <= 1;
fifo_rd_en[0] <= 0;
fifo_rd_en[1] <= 0;
fifo_wr_en[0] <= 0;
fifo_wr_en[1] <= 0;
PL_done <= 'h1;
pckt_rd_wr[0] <= 'h1;
pckt_rd_wr[1] <= 'h1;
fifo_sel <= 'h0;
end
else
begin
counter <= counter_next;
PL_EN <= PL_EN_next;
SW_CTRL <= SW_CTRL_next;
R_W_EN <= R_W_EN_next;
fifo_rd_en[0] <= fifo_rd_en_next[0];
fifo_rd_en[1] <= fifo_rd_en_next[1];
fifo_wr_en[0] <= fifo_wr_en_next[0];
fifo_wr_en[1] <= fifo_wr_en_next[1];
PL_done <= PL_done_next;
pckt_rd_wr[0] <= pckt_rd_wr_next[0];
pckt_rd_wr[1] <= pckt_rd_wr_next[1];
fifo_sel <= fifo_sel_next;
end
end
endmodule | 0 |
3,368 | data/full_repos/permissive/104269513/pipeline_dualCF.v | 104,269,513 | pipeline_dualCF.v | v | 762 | 452 | [] | [] | [] | null | line:168: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:691: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:696: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:177: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:223: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:231: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:294: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:674: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,089 | module | module pipeline_dualCF_tb();
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
pipeline_dualCF PL_2CF (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.Master_reg(),
.clk(clk),
.rst(rst)
);
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
count = 0;
out_rdy = 1;
in_wr = 0;
counter_restart = 25;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end
always @ (posedge clk)
begin
count <= count + 1;
if (count > 2)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
else if (count == 200 )
begin
out_rdy <= 0;
in_wr <= 0;
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
end
endmodule | module pipeline_dualCF_tb(); |
reg clk, rst;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
reg out_rdy, in_wr;
wire in_rdy, out_wr;
integer count,fq;
integer i, counter_restart;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
pipeline_dualCF PL_2CF (
.in_data(fifo_data_in),
.in_ctrl(fifo_ctrl_in),
.out_data(fifo_data_out),
.out_ctrl(fifo_ctrl_out),
.out_rdy(out_rdy),
.in_wr(in_wr),
.in_rdy(in_rdy),
.out_wr(out_wr),
.IorD(),
.Addr_in(),
.Data_In(),
.Addr_DM(),
.Addr_IM(),
.Data_out_IM(),
.Data_out_DM(),
.full(),
.nearly_full(),
.nearly_empty(),
.empty(),
.fifo_busy(),
.packet_count(),
.FIFO_RD_addr(),
.FIFO_WR_addr(),
.fifo_state(),
.DEPTH(),
.PL_EN(),
.SW_CTRL(),
.fifo_rd_en(),
.fifo_wr_en(),
.Master_reg(),
.clk(clk),
.rst(rst)
);
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
count = 0;
out_rdy = 1;
in_wr = 0;
counter_restart = 25;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end
always @ (posedge clk)
begin
count <= count + 1;
if (count > 2)
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
else if (count == 200 )
begin
out_rdy <= 0;
in_wr <= 0;
end
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
end
endmodule | 0 |
3,369 | data/full_repos/permissive/104269513/pipeline_dualCF.v | 104,269,513 | pipeline_dualCF.v | v | 762 | 452 | [] | [] | [] | null | line:168: before: "integer" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:691: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:696: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:177: Cannot find file containing module: \'datapath\'\ndatapath dp ( \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n datapath\n datapath.v\n datapath.sv\n obj_dir/datapath\n obj_dir/datapath.v\n obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:223: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:231: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:294: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:674: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,089 | function | function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | function integer log2; |
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction | 0 |
3,370 | data/full_repos/permissive/104269513/regfile_32x64.v | 104,269,513 | regfile_32x64.v | v | 88 | 36 | [] | [] | [] | [(3, 86)] | null | data/verilator_xmls/89a19dd9-9722-4013-9607-b8e390d0b10e.xml | null | 1,090 | module | module regfile (clk,
rst,
r0addr,
r1addr,
waddr,
wdata,
wena,
r0data,
r1data
);
input clk;
input rst;
input [4:0] r0addr;
input [4:0] r1addr;
input [4:0] waddr;
input [63:0] wdata;
input wena;
output [63:0] r0data;
output [63:0] r1data;
reg [63:0] reg_file [31:0];
reg [4:0] addr0,addr1,addr2;
reg [63:0] r0data,r1data;
always @ *
begin
addr0 = r0addr;
addr1 = r1addr;
addr2 = waddr;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
reg_file[0] <= 'h0;
reg_file[1] <= 'h0;
reg_file[2] <= 'h0;
reg_file[3] <= 'h0;
reg_file[4] <= 'h0;
reg_file[5] <= 'h0;
reg_file[6] <= 'h0;
reg_file[7] <= 'h0;
reg_file[8] <= 'h0;
reg_file[9] <= 'h0;
reg_file[10] <= 'h0;
reg_file[11] <= 'h0;
reg_file[12] <= 'h0;
reg_file[13] <= 'h0;
reg_file[14] <= 'h0;
reg_file[15] <= 'h0;
reg_file[16] <= 'h0;
reg_file[17] <= 'h0;
reg_file[18] <= 'h0;
reg_file[19] <= 'h0;
reg_file[20] <= 'h0;
reg_file[21] <= 'h0;
reg_file[22] <= 'h0;
reg_file[23] <= 'h0;
reg_file[24] <= 'h0;
reg_file[25] <= 'h0;
reg_file[26] <= 'h0;
reg_file[27] <= 'h0;
reg_file[28] <= 'h0;
reg_file[29] <= 'h0;
reg_file[20] <= 'h0;
reg_file[31] <= 'h0;
end
else
begin
r0data <= reg_file [addr0];
r1data <= reg_file [addr1];
if (wena)
reg_file[addr2] <= wdata;
end
end
endmodule | module regfile (clk,
rst,
r0addr,
r1addr,
waddr,
wdata,
wena,
r0data,
r1data
); |
input clk;
input rst;
input [4:0] r0addr;
input [4:0] r1addr;
input [4:0] waddr;
input [63:0] wdata;
input wena;
output [63:0] r0data;
output [63:0] r1data;
reg [63:0] reg_file [31:0];
reg [4:0] addr0,addr1,addr2;
reg [63:0] r0data,r1data;
always @ *
begin
addr0 = r0addr;
addr1 = r1addr;
addr2 = waddr;
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
reg_file[0] <= 'h0;
reg_file[1] <= 'h0;
reg_file[2] <= 'h0;
reg_file[3] <= 'h0;
reg_file[4] <= 'h0;
reg_file[5] <= 'h0;
reg_file[6] <= 'h0;
reg_file[7] <= 'h0;
reg_file[8] <= 'h0;
reg_file[9] <= 'h0;
reg_file[10] <= 'h0;
reg_file[11] <= 'h0;
reg_file[12] <= 'h0;
reg_file[13] <= 'h0;
reg_file[14] <= 'h0;
reg_file[15] <= 'h0;
reg_file[16] <= 'h0;
reg_file[17] <= 'h0;
reg_file[18] <= 'h0;
reg_file[19] <= 'h0;
reg_file[20] <= 'h0;
reg_file[21] <= 'h0;
reg_file[22] <= 'h0;
reg_file[23] <= 'h0;
reg_file[24] <= 'h0;
reg_file[25] <= 'h0;
reg_file[26] <= 'h0;
reg_file[27] <= 'h0;
reg_file[28] <= 'h0;
reg_file[29] <= 'h0;
reg_file[20] <= 'h0;
reg_file[31] <= 'h0;
end
else
begin
r0data <= reg_file [addr0];
r1data <= reg_file [addr1];
if (wena)
reg_file[addr2] <= wdata;
end
end
endmodule | 0 |
3,371 | data/full_repos/permissive/104269513/spring_fifo_v2.v | 104,269,513 | spring_fifo_v2.v | v | 561 | 361 | [] | [] | [] | [(27, 339), (349, 558)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:447: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 0;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:451: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:453: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:103: Cannot find file containing module: \'spring_fifo_mem\'\nspring_fifo_mem mem2(\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.sv\n spring_fifo_mem\n spring_fifo_mem.v\n spring_fifo_mem.sv\n obj_dir/spring_fifo_mem\n obj_dir/spring_fifo_mem.v\n obj_dir/spring_fifo_mem.sv\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:432: Cannot find file containing module: \'regfile\'\nregfile op_reg( \n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/spring_fifo_v2.v:462: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n : ... In instance spring_fifo_tb\nip_rd_count = 4 ;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,092 | module | module spring_fifo #( parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
input rd_req,
input wr_req,
input out_rdy,
input in_wr,
input [1:0] ip_rd_count,
output reg out_wr,
output reg pckt_rd_wr,
output reg rd_ack,
output reg wr_ack,
output reg rd_done,
output reg wr_done,
output in_rdy,
output full,
output empty,
output nearly_full,
output nearly_empty,
output reg [1:0] packet_count,
output reg [ADDR_WIDTH-1:0] first_word,
output reg [ADDR_WIDTH-1:0] last_word,
output fifo_busy,
input [DATA_WIDTH-1:0] fifo_data_in,
output [DATA_WIDTH-1:0] fifo_data_out,
input [CTRL_WIDTH-1:0] fifo_ctrl_in,
output [CTRL_WIDTH-1:0] fifo_ctrl_out,
output reg [ADDR_WIDTH:0] DEPTH,
output reg [1:0] wr_state,
output reg [1:0] state,
output reg [ADDR_WIDTH-1:0] fifo_wa,
output reg [ADDR_WIDTH-1:0] fifo_ra,
output reg fifo_rd_en,
output reg fifo_wr_en,
input clk,
input rst
);
reg [1:0] rd_count, rd_count_next, rd_count_prev;
reg [1:0] pckt_rd_out_count;
reg [1:0]wr_state_next;
reg [ADDR_WIDTH-1:0] first_word_next, last_word_next;
reg [1:0] packet_count_next;
reg [ADDR_WIDTH-1:0] packet_size, packet_size_next;
reg [ADDR_WIDTH-1:0]fifo_wa_next;
reg [ADDR_WIDTH-1:0]fifo_ra_next, fifo_ra_prev;
wire fifo_read, fifo_write;
reg [ADDR_WIDTH:0] DEPTH_next;
reg [ADDR_WIDTH:0] DEPTH_prev, DEPTH_prev_next;
reg out_wr_next;
reg pckt_rd_wr_next;
spring_fifo_mem mem2(
.clka(clk),
.dina({fifo_ctrl_in,fifo_data_in}),
.addra(fifo_wa),
.wea(fifo_write),
.clkb(clk),
.addrb(fifo_ra),
.doutb({fifo_ctrl_out,fifo_data_out})
);
assign empty = (DEPTH == 'h0) ? 1'b1 : 1'b0;
assign nearly_empty = (DEPTH == 'h1) ? 1'b1 : 1'b0;
assign full = (DEPTH == MAX_DEPTH) ? 1'b1 : 1'b0;
assign nearly_full = (DEPTH == MAX_DEPTH - 1) ? 1'b1 : 1'b0;
assign in_rdy = (!(nearly_full | full)) & fifo_wr_en;
assign fifo_read = (fifo_rd_en & out_rdy & !empty);
assign fifo_write = (fifo_wr_en & in_wr & !full);
assign fifo_busy = (fifo_read | fifo_write);
always @ *
begin
fifo_ra_next = fifo_ra;
fifo_wa_next = fifo_wa;
DEPTH_next = DEPTH;
DEPTH_prev_next = DEPTH_prev;
first_word_next = first_word;
last_word_next = last_word;
packet_size_next = packet_size;
pckt_rd_wr_next = pckt_rd_wr;
packet_count_next = packet_count;
wr_state_next = wr_state;
out_wr_next = out_wr;
rd_count_next = rd_count;
if (fifo_read)
begin
if (rd_count != rd_count_prev)
begin
fifo_ra_next = first_word;
DEPTH_next = DEPTH_prev;
pckt_rd_wr_next = 1'b0;
end
else if (fifo_ra != last_word)
begin
if (fifo_ra == first_word)
begin
out_wr_next = 1'b1;
DEPTH_prev_next = DEPTH;
end
fifo_ra_next = fifo_ra + 1;
DEPTH_next = DEPTH_next -1;
end
else if ((fifo_ctrl_out != 0) & out_wr)
begin
packet_count_next = packet_count - 1;
out_wr_next = 1'b0;
rd_count_next = rd_count - 1;
if (rd_count_next == 0)
pckt_rd_wr_next = 1'b1;
end
end
else out_wr_next = 1'b0;
if ((fifo_ra == fifo_ra_prev) & (out_wr))
begin
out_wr_next = 1'b0;
end
if (fifo_write)
begin
case (wr_state)
2'h0: begin
if(fifo_ctrl_in != 'h0)
begin
wr_state_next = 2'h1;
first_word_next = fifo_wa;
packet_size_next = 'h1;
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
end
end
2'h1: begin
if(fifo_ctrl_in == 'h0)
begin
packet_size_next = packet_size + 1;
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
if (packet_size == 'h5)
wr_state_next = 2'h2;
end
end
2'h2: begin
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
packet_size_next = packet_size + 1;
if(fifo_ctrl_in != 'h0)
begin
wr_state_next = 2'h0;
last_word_next = fifo_wa;
pckt_rd_wr_next = 1'b0;
packet_count_next = packet_count + 1;
end
end
default: begin
wr_state_next = wr_state;
packet_count_next = packet_count;
pckt_rd_wr_next = pckt_rd_wr;
packet_size_next = packet_size;
first_word_next = first_word;
last_word_next = last_word;
end
endcase
end
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
fifo_wa <= 'h0;
fifo_ra <= 'h0;
DEPTH <= 'h0;
DEPTH_prev <= 'h0;
state <= 'h0;
wr_state <= 'h0;
packet_size <= 'h0;
packet_count <= 'h0;
first_word <= 'h0;
last_word <= 'h0;
out_wr <= 'h0;
pckt_rd_wr <= 'h1;
fifo_rd_en <= 'h0;
fifo_wr_en <= 'h0;
rd_count <= 'h0;
rd_ack <= 0;
wr_ack <= 0;
rd_done <= 1;
wr_done <= 0;
pckt_rd_out_count <= 'h0;
end
else
begin
fifo_wa <= fifo_wa_next;
fifo_ra_prev <= fifo_ra;
fifo_ra <= fifo_ra_next;
DEPTH <= DEPTH_next;
DEPTH_prev <= DEPTH_prev_next;
wr_state <= wr_state_next;
packet_size <= packet_size_next;
packet_count <= packet_count_next;
first_word <= first_word_next;
last_word <= last_word_next;
out_wr <= out_wr_next;
pckt_rd_wr <= pckt_rd_wr_next;
rd_count <= rd_count_next;
rd_count_prev <= rd_count;
case (state)
'h0:begin
rd_done <= 'h0;
state <= 'h1;
if(rd_req)
begin
fifo_rd_en <= 'b1;
rd_ack <= 'b1;
state <= 'h2;
if (pckt_rd_out_count == 'h0)
begin
rd_count <= 'h1;
rd_count_prev <= 'h1;
end
else
begin
rd_count <= 'h1;
rd_count_prev <= 'h0;
end
end
end
'h1:begin
wr_done <= 'h0;
state <= 'h0;
if(wr_req)
begin
fifo_wr_en <= 'b1;
wr_ack <= 'b1;
state <= 'h3;
end
end
'h2:begin
rd_ack <= 'b0;
if(pckt_rd_wr_next)
begin
fifo_rd_en <= 'b0;
state <= 'h0;
rd_done <= 'h1;
pckt_rd_out_count <= pckt_rd_out_count + 1;
end
end
'h3:begin
wr_ack <= 'b0;
if(!pckt_rd_wr_next)
begin
fifo_wr_en <= 'b0;
state <= 'h0;
wr_done <= 'h1;
pckt_rd_out_count <= 'h0;
end
end
default: begin
fifo_wr_en <= 0;
fifo_rd_en <= 0;
rd_ack <= 0;
wr_ack <= 0;
rd_done <= 0;
wr_done <= 0;
state <= 'h0;
end
endcase
end
end
endmodule | module spring_fifo #( parameter MAX_DEPTH = 256,
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
input rd_req,
input wr_req,
input out_rdy,
input in_wr,
input [1:0] ip_rd_count,
output reg out_wr,
output reg pckt_rd_wr,
output reg rd_ack,
output reg wr_ack,
output reg rd_done,
output reg wr_done,
output in_rdy,
output full,
output empty,
output nearly_full,
output nearly_empty,
output reg [1:0] packet_count,
output reg [ADDR_WIDTH-1:0] first_word,
output reg [ADDR_WIDTH-1:0] last_word,
output fifo_busy,
input [DATA_WIDTH-1:0] fifo_data_in,
output [DATA_WIDTH-1:0] fifo_data_out,
input [CTRL_WIDTH-1:0] fifo_ctrl_in,
output [CTRL_WIDTH-1:0] fifo_ctrl_out,
output reg [ADDR_WIDTH:0] DEPTH,
output reg [1:0] wr_state,
output reg [1:0] state,
output reg [ADDR_WIDTH-1:0] fifo_wa,
output reg [ADDR_WIDTH-1:0] fifo_ra,
output reg fifo_rd_en,
output reg fifo_wr_en,
input clk,
input rst
); |
reg [1:0] rd_count, rd_count_next, rd_count_prev;
reg [1:0] pckt_rd_out_count;
reg [1:0]wr_state_next;
reg [ADDR_WIDTH-1:0] first_word_next, last_word_next;
reg [1:0] packet_count_next;
reg [ADDR_WIDTH-1:0] packet_size, packet_size_next;
reg [ADDR_WIDTH-1:0]fifo_wa_next;
reg [ADDR_WIDTH-1:0]fifo_ra_next, fifo_ra_prev;
wire fifo_read, fifo_write;
reg [ADDR_WIDTH:0] DEPTH_next;
reg [ADDR_WIDTH:0] DEPTH_prev, DEPTH_prev_next;
reg out_wr_next;
reg pckt_rd_wr_next;
spring_fifo_mem mem2(
.clka(clk),
.dina({fifo_ctrl_in,fifo_data_in}),
.addra(fifo_wa),
.wea(fifo_write),
.clkb(clk),
.addrb(fifo_ra),
.doutb({fifo_ctrl_out,fifo_data_out})
);
assign empty = (DEPTH == 'h0) ? 1'b1 : 1'b0;
assign nearly_empty = (DEPTH == 'h1) ? 1'b1 : 1'b0;
assign full = (DEPTH == MAX_DEPTH) ? 1'b1 : 1'b0;
assign nearly_full = (DEPTH == MAX_DEPTH - 1) ? 1'b1 : 1'b0;
assign in_rdy = (!(nearly_full | full)) & fifo_wr_en;
assign fifo_read = (fifo_rd_en & out_rdy & !empty);
assign fifo_write = (fifo_wr_en & in_wr & !full);
assign fifo_busy = (fifo_read | fifo_write);
always @ *
begin
fifo_ra_next = fifo_ra;
fifo_wa_next = fifo_wa;
DEPTH_next = DEPTH;
DEPTH_prev_next = DEPTH_prev;
first_word_next = first_word;
last_word_next = last_word;
packet_size_next = packet_size;
pckt_rd_wr_next = pckt_rd_wr;
packet_count_next = packet_count;
wr_state_next = wr_state;
out_wr_next = out_wr;
rd_count_next = rd_count;
if (fifo_read)
begin
if (rd_count != rd_count_prev)
begin
fifo_ra_next = first_word;
DEPTH_next = DEPTH_prev;
pckt_rd_wr_next = 1'b0;
end
else if (fifo_ra != last_word)
begin
if (fifo_ra == first_word)
begin
out_wr_next = 1'b1;
DEPTH_prev_next = DEPTH;
end
fifo_ra_next = fifo_ra + 1;
DEPTH_next = DEPTH_next -1;
end
else if ((fifo_ctrl_out != 0) & out_wr)
begin
packet_count_next = packet_count - 1;
out_wr_next = 1'b0;
rd_count_next = rd_count - 1;
if (rd_count_next == 0)
pckt_rd_wr_next = 1'b1;
end
end
else out_wr_next = 1'b0;
if ((fifo_ra == fifo_ra_prev) & (out_wr))
begin
out_wr_next = 1'b0;
end
if (fifo_write)
begin
case (wr_state)
2'h0: begin
if(fifo_ctrl_in != 'h0)
begin
wr_state_next = 2'h1;
first_word_next = fifo_wa;
packet_size_next = 'h1;
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
end
end
2'h1: begin
if(fifo_ctrl_in == 'h0)
begin
packet_size_next = packet_size + 1;
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
if (packet_size == 'h5)
wr_state_next = 2'h2;
end
end
2'h2: begin
fifo_wa_next = fifo_wa + 1;
DEPTH_next = DEPTH_next +1;
packet_size_next = packet_size + 1;
if(fifo_ctrl_in != 'h0)
begin
wr_state_next = 2'h0;
last_word_next = fifo_wa;
pckt_rd_wr_next = 1'b0;
packet_count_next = packet_count + 1;
end
end
default: begin
wr_state_next = wr_state;
packet_count_next = packet_count;
pckt_rd_wr_next = pckt_rd_wr;
packet_size_next = packet_size;
first_word_next = first_word;
last_word_next = last_word;
end
endcase
end
end
always @ (posedge clk, posedge rst)
begin
if (rst)
begin
fifo_wa <= 'h0;
fifo_ra <= 'h0;
DEPTH <= 'h0;
DEPTH_prev <= 'h0;
state <= 'h0;
wr_state <= 'h0;
packet_size <= 'h0;
packet_count <= 'h0;
first_word <= 'h0;
last_word <= 'h0;
out_wr <= 'h0;
pckt_rd_wr <= 'h1;
fifo_rd_en <= 'h0;
fifo_wr_en <= 'h0;
rd_count <= 'h0;
rd_ack <= 0;
wr_ack <= 0;
rd_done <= 1;
wr_done <= 0;
pckt_rd_out_count <= 'h0;
end
else
begin
fifo_wa <= fifo_wa_next;
fifo_ra_prev <= fifo_ra;
fifo_ra <= fifo_ra_next;
DEPTH <= DEPTH_next;
DEPTH_prev <= DEPTH_prev_next;
wr_state <= wr_state_next;
packet_size <= packet_size_next;
packet_count <= packet_count_next;
first_word <= first_word_next;
last_word <= last_word_next;
out_wr <= out_wr_next;
pckt_rd_wr <= pckt_rd_wr_next;
rd_count <= rd_count_next;
rd_count_prev <= rd_count;
case (state)
'h0:begin
rd_done <= 'h0;
state <= 'h1;
if(rd_req)
begin
fifo_rd_en <= 'b1;
rd_ack <= 'b1;
state <= 'h2;
if (pckt_rd_out_count == 'h0)
begin
rd_count <= 'h1;
rd_count_prev <= 'h1;
end
else
begin
rd_count <= 'h1;
rd_count_prev <= 'h0;
end
end
end
'h1:begin
wr_done <= 'h0;
state <= 'h0;
if(wr_req)
begin
fifo_wr_en <= 'b1;
wr_ack <= 'b1;
state <= 'h3;
end
end
'h2:begin
rd_ack <= 'b0;
if(pckt_rd_wr_next)
begin
fifo_rd_en <= 'b0;
state <= 'h0;
rd_done <= 'h1;
pckt_rd_out_count <= pckt_rd_out_count + 1;
end
end
'h3:begin
wr_ack <= 'b0;
if(!pckt_rd_wr_next)
begin
fifo_wr_en <= 'b0;
state <= 'h0;
wr_done <= 'h1;
pckt_rd_out_count <= 'h0;
end
end
default: begin
fifo_wr_en <= 0;
fifo_rd_en <= 0;
rd_ack <= 0;
wr_ack <= 0;
rd_done <= 0;
wr_done <= 0;
state <= 'h0;
end
endcase
end
end
endmodule | 0 |
3,372 | data/full_repos/permissive/104269513/spring_fifo_v2.v | 104,269,513 | spring_fifo_v2.v | v | 561 | 361 | [] | [] | [] | [(27, 339), (349, 558)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:447: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 0;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:451: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:453: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:103: Cannot find file containing module: \'spring_fifo_mem\'\nspring_fifo_mem mem2(\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.v\n data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.sv\n spring_fifo_mem\n spring_fifo_mem.v\n spring_fifo_mem.sv\n obj_dir/spring_fifo_mem\n obj_dir/spring_fifo_mem.v\n obj_dir/spring_fifo_mem.sv\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:432: Cannot find file containing module: \'regfile\'\nregfile op_reg( \n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/spring_fifo_v2.v:462: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n : ... In instance spring_fifo_tb\nip_rd_count = 4 ;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,092 | module | module spring_fifo_tb ();
reg clk, rst;
integer count;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
reg rd_req,wr_req;
reg [1:0] ip_rd_count;
reg out_rdy, in_wr;
wire out_wr;
wire rd_ack, wr_ack;
wire rd_done, wr_done;
reg rd_done_next;
wire [1:0] packet_count;
wire in_rdy;
wire [7:0] first_word, last_word;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
spring_fifo UUT(
.rd_req(rd_req),
.wr_req(wr_req),
.out_rdy(out_rdy),
.in_wr(in_wr),
.ip_rd_count(ip_rd_count),
.out_wr(out_wr),
.pckt_rd_wr(),
.rd_ack(rd_ack),
.wr_ack(wr_ack),
.rd_done(rd_done),
.wr_done(wr_done),
.in_rdy(in_rdy),
.full(),
.empty(),
.nearly_full(),
.nearly_empty(),
.packet_count(packet_count),
.first_word(first_word),
.last_word(last_word),
.fifo_busy(),
.fifo_data_in(fifo_data_in),
.fifo_data_out(fifo_data_out),
.fifo_ctrl_in(fifo_ctrl_in),
.fifo_ctrl_out(fifo_ctrl_out),
.DEPTH(),
.wr_state(),
.state(),
.fifo_wa(),
.fifo_ra(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
#100
clk = 0;
forever #10 clk = ~clk;
end
initial begin
count = 0;
rd_req = 0;
wr_req = 1;
ip_rd_count = 4 ;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
end
always @ (posedge clk)
begin
if (count < 2) wr_req <= 1;
else if (wr_ack) wr_req <= 0;
if (count > 5 )
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
if (wr_done) rd_req <= 1;
if (rd_ack) rd_req <= 0;
if (count == 'h24 | count == 'h36) rd_req <= 1;
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
count <= count + 1;
end
endmodule | module spring_fifo_tb (); |
reg clk, rst;
integer count;
reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;
reg[4:0] reg_wa;
reg rd_req,wr_req;
reg [1:0] ip_rd_count;
reg out_rdy, in_wr;
wire out_wr;
wire rd_ack, wr_ack;
wire rd_done, wr_done;
reg rd_done_next;
wire [1:0] packet_count;
wire in_rdy;
wire [7:0] first_word, last_word;
wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;
wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;
spring_fifo UUT(
.rd_req(rd_req),
.wr_req(wr_req),
.out_rdy(out_rdy),
.in_wr(in_wr),
.ip_rd_count(ip_rd_count),
.out_wr(out_wr),
.pckt_rd_wr(),
.rd_ack(rd_ack),
.wr_ack(wr_ack),
.rd_done(rd_done),
.wr_done(wr_done),
.in_rdy(in_rdy),
.full(),
.empty(),
.nearly_full(),
.nearly_empty(),
.packet_count(packet_count),
.first_word(first_word),
.last_word(last_word),
.fifo_busy(),
.fifo_data_in(fifo_data_in),
.fifo_data_out(fifo_data_out),
.fifo_ctrl_in(fifo_ctrl_in),
.fifo_ctrl_out(fifo_ctrl_out),
.DEPTH(),
.wr_state(),
.state(),
.fifo_wa(),
.fifo_ra(),
.fifo_rd_en(),
.fifo_wr_en(),
.clk(clk),
.rst(rst)
);
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];
regfile op_reg(
.clk(clk),
.rst(rst),
.r0addr(),
.r1addr(),
.waddr(reg_wa),
.wdata(fifo_data_out),
.wena(out_wr),
.r0data(),
.r1data()
);
initial begin
rst = 1;
#30 rst = 0;
end
initial begin
#100
clk = 0;
forever #10 clk = ~clk;
end
initial begin
count = 0;
rd_req = 0;
wr_req = 1;
ip_rd_count = 4 ;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
end
always @ (posedge clk)
begin
if (count < 2) wr_req <= 1;
else if (wr_ack) wr_req <= 0;
if (count > 5 )
begin
if (in_rdy && fifo_ctrl_in != 'hab)
begin
in_wr <= 1;
if (in_wr)
reg_ra <= reg_ra + 1;
end
else
begin
reg_ra <= reg_ra;
in_wr <= 0;
end
end
if (wr_done) rd_req <= 1;
if (rd_ack) rd_req <= 0;
if (count == 'h24 | count == 'h36) rd_req <= 1;
if(out_wr)
reg_wa <= reg_wa +1;
else
reg_wa <= reg_wa;
count <= count + 1;
end
endmodule | 0 |
3,373 | data/full_repos/permissive/104305228/code/cpu.v | 104,305,228 | cpu.v | v | 176 | 104 | [] | [] | [] | [(143, 316)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/cpu.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/cpu.v:93: syntax error, unexpected iff\n iff iff(\n ^~~\n%Error: data/full_repos/permissive/104305228/code/cpu.v:113: syntax error, unexpected type\n .op(id_op), .type(id_type), .reg1(id_reg1), .reg2(id_reg2),\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/cpu.v:138: syntax error, unexpected type\n .op_i(ex_op_i), .op_o(ex_op_o), .type(ex_type),\n ^~~~\n%Error: Exiting due to 4 error(s)\n' | 1,094 | module | module cpu(
input clk,
input rst,
input [31:0] rom_read_instr,
input [31:0] ram_read_instr,
output [31:0] rom_read_addr,
output ram_re,
output [31:0] ram_read_addr,
output ram_we,
output [31:0] ram_write_addr,
output [3:0] ram_write,
output [31:0] ram_write_instr
);
wire [5:0] ctrl_stall;
wire re1;
wire [4:0] read_addr1;
wire [31:0] read_instr1;
wire re2;
wire [4:0] read_addr2;
wire [31:0] read_instr2;
wire we;
wire [4:0] write_addr;
wire [31:0] write_instr;
wire [31:0] if_pc_read_instr;
wire [31:0] if_instr;
wire [31:0] id_instr_i;
wire [31:0] id_instr_o;
wire id_pc_we;
wire [31:0] id_pc_write_instr;
wire [31:0] id_pc_read_instr;
wire id_re1;
wire [4:0] id_read_addr1;
wire [31:0] id_read_instr1;
wire id_re2;
wire [4:0] id_read_addr2;
wire [31:0] id_read_instr2;
wire [7:0] id_op;
wire [2:0] id_type;
wire [31:0] id_reg1;
wire [31:0] id_reg2;
wire id_we;
wire [4:0] id_write_addr;
wire [31:0] id_write_instr;
wire id_stallsignal;
wire [31:0] ex_instr_i;
wire [31:0] ex_instr_o;
wire [7:0] ex_op_i;
wire [7:0] ex_op_o;
wire [2:0] ex_type;
wire [31:0] ex_reg1_i;
wire [31:0] ex_reg1_o;
wire [31:0] ex_reg2_i;
wire [31:0] ex_reg2_o;
wire ex_we_i;
wire ex_we_o;
wire [4:0] ex_write_addr_i;
wire [4:0] ex_write_addr_o;
wire [31:0] ex_write_instr_i;
wire [31:0] ex_write_instr_o;
wire ex_stallsignal;
wire [31:0] mem_instr;
wire [7:0] mem_op;
wire [31:0] mem_reg1;
wire [31:0] mem_reg2;
wire mem_we_i;
wire mem_we_o;
wire [4:0] mem_write_addr_i;
wire [4:0] mem_write_addr_o;
wire [31:0] mem_write_instr_i;
wire [31:0] mem_write_instr_o;
wire wb_we;
wire [4:0] wb_write_addr;
wire [31:0] wb_write_instr;
ctrl ctrl(
.rst(rst),
.id_stallsignal(id_stallsignal),
.ex_stallsignal(ex_stallsignal),
.stall(ctrl_stall)
);
register register(
.clk(clk), .rst(rst),
.re1(re1), .read_addr1(read_addr1), .read_instr1(read_instr1),
.re2(re2), .read_addr2(read_addr2), .read_instr2(read_instr2),
.we(we), .write_addr(write_addr), .write_instr(write_instr)
);
iff iff(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.pc_we(id_pc_we), .pc_write_instr(id_pc_write_instr),
.pc_read_instr(if_pc_read_instr)
);
assign rom_read_addr = if_pc_read_instr;
assign if_instr = rom_read_instr;
if_id if_id(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.if_pc(if_pc_read_instr), .if_instr(if_instr),
.id_pc(id_pc_read_instr), .id_instr(id_instr_i)
);
id id(
.rst(rst), .instr_i(id_instr_i), .instr_o(id_instr_o),
.pc_we(id_pc_we), .pc_write_instr(id_pc_write_instr), .pc_i(id_pc_read_instr),
.reg1_re(id_re1), .reg1_read_addr(id_read_addr1), .reg1_read_instr(id_read_instr1),
.reg2_re(id_re2), .reg2_read_addr(id_read_addr2), .reg2_read_instr(id_read_instr2),
.op(id_op), .type(id_type), .reg1(id_reg1), .reg2(id_reg2),
.we(id_we), .write_addr(id_write_addr), .write_instr(id_write_instr),
.ex_op(ex_op_o), .ex_we(ex_we_o), .ex_write_addr(ex_write_addr_o), .ex_write_instr(ex_write_instr_o),
.mem_we(mem_we_o), .mem_write_addr(mem_write_addr_o), .mem_write_instr(mem_write_instr_o),
.stallsignal(id_stallsignal)
);
assign re1 = id_re1;
assign read_addr1 = id_read_addr1;
assign id_read_instr1 = read_instr1;
assign re2 = id_re2;
assign read_addr2 = id_read_addr2;
assign id_read_instr2 = read_instr2;
id_ex id_ex(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.id_instr(id_instr_o), .id_op(id_op), .id_type(id_type),
.id_reg1(id_reg1), .id_reg2(id_reg2), .id_we(id_we), .id_write_addr(id_write_addr),
.id_write_instr(id_write_instr),
.ex_instr(ex_instr_i), .ex_op(ex_op_i), .ex_type(ex_type),
.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_we(ex_we_i),
.ex_write_addr(ex_write_addr_i), .ex_write_instr(ex_write_instr_i)
);
ex ex(
.rst(rst), .instr_i(ex_instr_i), .instr_o(ex_instr_o),
.op_i(ex_op_i), .op_o(ex_op_o), .type(ex_type),
.reg1_i(ex_reg1_i), .reg1_o(ex_reg1_o), .reg2_i(ex_reg2_i), .reg2_o(ex_reg2_o),
.we_i(ex_we_i), .we_o(ex_we_o), .write_addr_i(ex_write_addr_i), .write_addr_o(ex_write_addr_o),
.write_instr_i(ex_write_instr_i), .write_instr_o(ex_write_instr_o),
.stallsignal(ex_stallsignal)
);
ex_mem ex_mem(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.ex_instr(ex_instr_o), .ex_op(ex_op_o), .ex_reg1(ex_reg1_o), .ex_reg2(ex_reg2_o),
.ex_we(ex_we_o), .ex_write_addr(ex_write_addr_o), .ex_write_instr(ex_write_instr_o),
.mem_instr(mem_instr), .mem_op(mem_op), .mem_reg1(mem_reg1), .mem_reg2(mem_reg2),
.mem_we(mem_we_i), .mem_write_addr(mem_write_addr_i), .mem_write_instr(mem_write_instr_i)
);
mem mem(
.rst(rst), .instr(mem_instr), .op(mem_op), .reg1(mem_reg1), .reg2(mem_reg2),
.mem_re(ram_re), .mem_read_addr(ram_read_addr), .mem_i(ram_read_instr),
.mem_we(ram_we), .mem_write_addr(ram_write_addr), .mem_write(ram_write),
.mem_write_instr(ram_write_instr),
.we_i(mem_we_i), .we_o(mem_we_o), .write_addr_i(mem_write_addr_i), .write_addr_o(mem_write_addr_o),
.write_instr_i(mem_write_instr_i), .write_instr_o(mem_write_instr_o)
);
mem_wb mem_wb(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.mem_we(mem_we_o), .mem_write_addr(mem_write_addr_o), .mem_write_instr(mem_write_instr_o),
.wb_we(wb_we), .wb_write_addr(wb_write_addr), .wb_write_instr(wb_write_instr)
);
assign we = wb_we;
assign write_addr = wb_write_addr;
assign write_instr = wb_write_instr;
wb wb(
.clk(clk), .rst(rst)
);
endmodule | module cpu(
input clk,
input rst,
input [31:0] rom_read_instr,
input [31:0] ram_read_instr,
output [31:0] rom_read_addr,
output ram_re,
output [31:0] ram_read_addr,
output ram_we,
output [31:0] ram_write_addr,
output [3:0] ram_write,
output [31:0] ram_write_instr
); |
wire [5:0] ctrl_stall;
wire re1;
wire [4:0] read_addr1;
wire [31:0] read_instr1;
wire re2;
wire [4:0] read_addr2;
wire [31:0] read_instr2;
wire we;
wire [4:0] write_addr;
wire [31:0] write_instr;
wire [31:0] if_pc_read_instr;
wire [31:0] if_instr;
wire [31:0] id_instr_i;
wire [31:0] id_instr_o;
wire id_pc_we;
wire [31:0] id_pc_write_instr;
wire [31:0] id_pc_read_instr;
wire id_re1;
wire [4:0] id_read_addr1;
wire [31:0] id_read_instr1;
wire id_re2;
wire [4:0] id_read_addr2;
wire [31:0] id_read_instr2;
wire [7:0] id_op;
wire [2:0] id_type;
wire [31:0] id_reg1;
wire [31:0] id_reg2;
wire id_we;
wire [4:0] id_write_addr;
wire [31:0] id_write_instr;
wire id_stallsignal;
wire [31:0] ex_instr_i;
wire [31:0] ex_instr_o;
wire [7:0] ex_op_i;
wire [7:0] ex_op_o;
wire [2:0] ex_type;
wire [31:0] ex_reg1_i;
wire [31:0] ex_reg1_o;
wire [31:0] ex_reg2_i;
wire [31:0] ex_reg2_o;
wire ex_we_i;
wire ex_we_o;
wire [4:0] ex_write_addr_i;
wire [4:0] ex_write_addr_o;
wire [31:0] ex_write_instr_i;
wire [31:0] ex_write_instr_o;
wire ex_stallsignal;
wire [31:0] mem_instr;
wire [7:0] mem_op;
wire [31:0] mem_reg1;
wire [31:0] mem_reg2;
wire mem_we_i;
wire mem_we_o;
wire [4:0] mem_write_addr_i;
wire [4:0] mem_write_addr_o;
wire [31:0] mem_write_instr_i;
wire [31:0] mem_write_instr_o;
wire wb_we;
wire [4:0] wb_write_addr;
wire [31:0] wb_write_instr;
ctrl ctrl(
.rst(rst),
.id_stallsignal(id_stallsignal),
.ex_stallsignal(ex_stallsignal),
.stall(ctrl_stall)
);
register register(
.clk(clk), .rst(rst),
.re1(re1), .read_addr1(read_addr1), .read_instr1(read_instr1),
.re2(re2), .read_addr2(read_addr2), .read_instr2(read_instr2),
.we(we), .write_addr(write_addr), .write_instr(write_instr)
);
iff iff(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.pc_we(id_pc_we), .pc_write_instr(id_pc_write_instr),
.pc_read_instr(if_pc_read_instr)
);
assign rom_read_addr = if_pc_read_instr;
assign if_instr = rom_read_instr;
if_id if_id(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.if_pc(if_pc_read_instr), .if_instr(if_instr),
.id_pc(id_pc_read_instr), .id_instr(id_instr_i)
);
id id(
.rst(rst), .instr_i(id_instr_i), .instr_o(id_instr_o),
.pc_we(id_pc_we), .pc_write_instr(id_pc_write_instr), .pc_i(id_pc_read_instr),
.reg1_re(id_re1), .reg1_read_addr(id_read_addr1), .reg1_read_instr(id_read_instr1),
.reg2_re(id_re2), .reg2_read_addr(id_read_addr2), .reg2_read_instr(id_read_instr2),
.op(id_op), .type(id_type), .reg1(id_reg1), .reg2(id_reg2),
.we(id_we), .write_addr(id_write_addr), .write_instr(id_write_instr),
.ex_op(ex_op_o), .ex_we(ex_we_o), .ex_write_addr(ex_write_addr_o), .ex_write_instr(ex_write_instr_o),
.mem_we(mem_we_o), .mem_write_addr(mem_write_addr_o), .mem_write_instr(mem_write_instr_o),
.stallsignal(id_stallsignal)
);
assign re1 = id_re1;
assign read_addr1 = id_read_addr1;
assign id_read_instr1 = read_instr1;
assign re2 = id_re2;
assign read_addr2 = id_read_addr2;
assign id_read_instr2 = read_instr2;
id_ex id_ex(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.id_instr(id_instr_o), .id_op(id_op), .id_type(id_type),
.id_reg1(id_reg1), .id_reg2(id_reg2), .id_we(id_we), .id_write_addr(id_write_addr),
.id_write_instr(id_write_instr),
.ex_instr(ex_instr_i), .ex_op(ex_op_i), .ex_type(ex_type),
.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_we(ex_we_i),
.ex_write_addr(ex_write_addr_i), .ex_write_instr(ex_write_instr_i)
);
ex ex(
.rst(rst), .instr_i(ex_instr_i), .instr_o(ex_instr_o),
.op_i(ex_op_i), .op_o(ex_op_o), .type(ex_type),
.reg1_i(ex_reg1_i), .reg1_o(ex_reg1_o), .reg2_i(ex_reg2_i), .reg2_o(ex_reg2_o),
.we_i(ex_we_i), .we_o(ex_we_o), .write_addr_i(ex_write_addr_i), .write_addr_o(ex_write_addr_o),
.write_instr_i(ex_write_instr_i), .write_instr_o(ex_write_instr_o),
.stallsignal(ex_stallsignal)
);
ex_mem ex_mem(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.ex_instr(ex_instr_o), .ex_op(ex_op_o), .ex_reg1(ex_reg1_o), .ex_reg2(ex_reg2_o),
.ex_we(ex_we_o), .ex_write_addr(ex_write_addr_o), .ex_write_instr(ex_write_instr_o),
.mem_instr(mem_instr), .mem_op(mem_op), .mem_reg1(mem_reg1), .mem_reg2(mem_reg2),
.mem_we(mem_we_i), .mem_write_addr(mem_write_addr_i), .mem_write_instr(mem_write_instr_i)
);
mem mem(
.rst(rst), .instr(mem_instr), .op(mem_op), .reg1(mem_reg1), .reg2(mem_reg2),
.mem_re(ram_re), .mem_read_addr(ram_read_addr), .mem_i(ram_read_instr),
.mem_we(ram_we), .mem_write_addr(ram_write_addr), .mem_write(ram_write),
.mem_write_instr(ram_write_instr),
.we_i(mem_we_i), .we_o(mem_we_o), .write_addr_i(mem_write_addr_i), .write_addr_o(mem_write_addr_o),
.write_instr_i(mem_write_instr_i), .write_instr_o(mem_write_instr_o)
);
mem_wb mem_wb(
.clk(clk), .rst(rst), .stall(ctrl_stall),
.mem_we(mem_we_o), .mem_write_addr(mem_write_addr_o), .mem_write_instr(mem_write_instr_o),
.wb_we(wb_we), .wb_write_addr(wb_write_addr), .wb_write_instr(wb_write_instr)
);
assign we = wb_we;
assign write_addr = wb_write_addr;
assign write_instr = wb_write_instr;
wb wb(
.clk(clk), .rst(rst)
);
endmodule | 0 |
3,374 | data/full_repos/permissive/104305228/code/ctrl.v | 104,305,228 | ctrl.v | v | 25 | 50 | [] | [] | [] | [(143, 165)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/ctrl.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:9: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:13: Define or directive not defined: \'`StallEnable\'\n if (ex_stallsignal == `StallEnable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:16: Define or directive not defined: \'`StallEnable\'\n else if (id_stallsignal == `StallEnable) begin\n ^~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,095 | module | module ctrl(
input rst,
input id_stallsignal,
input ex_stallsignal,
output reg[5:0] stall
);
always @ (*) begin
if (rst == `RstEnable) begin
stall <= 6'b000000;
end
else begin
if (ex_stallsignal == `StallEnable) begin
stall <= 6'b001111;
end
else if (id_stallsignal == `StallEnable) begin
stall <= 6'b000111;
end
else begin
stall <= 6'b000000;
end
end
end
endmodule | module ctrl(
input rst,
input id_stallsignal,
input ex_stallsignal,
output reg[5:0] stall
); |
always @ (*) begin
if (rst == `RstEnable) begin
stall <= 6'b000000;
end
else begin
if (ex_stallsignal == `StallEnable) begin
stall <= 6'b001111;
end
else if (id_stallsignal == `StallEnable) begin
stall <= 6'b000111;
end
else begin
stall <= 6'b000000;
end
end
end
endmodule | 0 |
3,375 | data/full_repos/permissive/104305228/code/ex.v | 104,305,228 | ex.v | v | 125 | 115 | [] | [] | [] | [(143, 265)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/ex.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ex.v:8: syntax error, unexpected type, expecting IDENTIFIER or \'[\' or do or final\n input [2:0] type,\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:15: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input [4:0] write_addr_i,\n ^~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input [31:0] write_instr_i,\n ^~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:19: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg stallsignal\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_sub\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n ^~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_subu\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_slt\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:31: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:32: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:37: Define or directive not defined: \'`op_and\'\n `op_and : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:40: Define or directive not defined: \'`op_or\'\n `op_or : begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:43: Define or directive not defined: \'`op_xor\'\n `op_xor : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:46: Define or directive not defined: \'`op_nor\'\n `op_nor : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:56: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:57: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:62: Define or directive not defined: \'`op_slt\'\n `op_slt : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:65: Define or directive not defined: \'`op_sltu\'\n `op_sltu : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_add\'\n `op_add, `op_addu, `op_sub, `op_subu : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_addu\'\n `op_add, `op_addu, `op_sub, `op_subu : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_sub\'\n `op_add, `op_addu, `op_sub, `op_subu : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_subu\'\n `op_add, `op_addu, `op_sub, `op_subu : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:78: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:79: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:88: Define or directive not defined: \'`op_add\'\n `op_add : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:90: Define or directive not defined: \'`WriteDisable\'\n we_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:96: Define or directive not defined: \'`op_sub\'\n `op_sub : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:98: Define or directive not defined: \'`WriteDisable\'\n we_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:110: Define or directive not defined: \'`type_logic\'\n `type_logic : begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:113: Define or directive not defined: \'`type_arith\'\n `type_arith : begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:116: Define or directive not defined: \'`type_jmp\'\n `type_jmp : begin\n ^~~~~~~~~\n%Error: Exiting due to 32 error(s)\n' | 1,097 | module | module ex(
input rst,
input [31:0] instr_i,
output [31:0] instr_o,
input [7:0] op_i,
output [7:0] op_o,
input [2:0] type,
input [31:0] reg1_i,
output [31:0] reg1_o,
input [31:0] reg2_i,
output [31:0] reg2_o,
input we_i,
output reg we_o,
input [4:0] write_addr_i,
output reg[4:0] write_addr_o,
input [31:0] write_instr_i,
output reg[31:0] write_instr_o,
output reg stallsignal
);
wire [31:0] reg1_comp = ~reg1_i + 1;
wire [31:0] reg2_comp = ~reg2_i + 1;
wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);
assign instr_o = instr_i;
assign op_o = op_i;
assign reg1_o = reg1_i;
assign reg2_o = reg2_i;
reg [31:0] res_logic;
always @ (*) begin
if (rst == `RstEnable) begin
res_logic <= 32'b0;
end
else begin
case (op_i)
`op_and : begin
res_logic <= reg1_i & reg2_i;
end
`op_or : begin
res_logic <= reg1_i | reg2_i;
end
`op_xor : begin
res_logic <= reg1_i ^ reg2_i;
end
`op_nor : begin
res_logic <= ~(reg1_i | reg2_i);
end
default : begin
res_logic <= 32'b0;
end
endcase
end
end
reg[63:0] res_arith;
always @ (*) begin
if (rst == `RstEnable) begin
res_arith <= 32'b0;
end
else begin
case (op_i)
`op_slt : begin
res_arith <= (reg1_i[31] == 1'b1 && reg2_i[31] == 1'b0) || (reg1_i[31] == reg2_i[31] && reg_sum[31] == 1'b1);
end
`op_sltu : begin
res_arith <= reg1_i < reg2_i;
end
`op_add, `op_addu, `op_sub, `op_subu : begin
res_arith <= reg_sum;
end
default : begin
res_arith <= 32'b0;
end
endcase
end
end
reg[31:0] res_jmp;
always @ (*) begin
if (rst == `RstEnable) begin
res_jmp <= 32'b0;
end
else begin
res_jmp <= write_instr_i;
end
end
always @ (*) begin
case (op_i)
`op_add : begin
if (reg1_i[31] == reg2_i[31] && reg_sum[31] != reg1_i[31]) begin
we_o <= `WriteDisable;
end
else begin
we_o <= we_i;
end
end
`op_sub : begin
if (reg1_i[31] == reg2_comp[31] && reg1_i != reg_sum[31]) begin
we_o <= `WriteDisable;
end
else begin
we_o <= we_i;
end
end
default : begin
we_o <= we_i;
end
endcase
write_addr_o <= write_addr_i;
case (type)
`type_logic : begin
write_instr_o <= res_logic;
end
`type_arith : begin
write_instr_o <= res_arith[31:0];
end
`type_jmp : begin
write_instr_o <= res_jmp;
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
endmodule | module ex(
input rst,
input [31:0] instr_i,
output [31:0] instr_o,
input [7:0] op_i,
output [7:0] op_o,
input [2:0] type,
input [31:0] reg1_i,
output [31:0] reg1_o,
input [31:0] reg2_i,
output [31:0] reg2_o,
input we_i,
output reg we_o,
input [4:0] write_addr_i,
output reg[4:0] write_addr_o,
input [31:0] write_instr_i,
output reg[31:0] write_instr_o,
output reg stallsignal
); |
wire [31:0] reg1_comp = ~reg1_i + 1;
wire [31:0] reg2_comp = ~reg2_i + 1;
wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);
assign instr_o = instr_i;
assign op_o = op_i;
assign reg1_o = reg1_i;
assign reg2_o = reg2_i;
reg [31:0] res_logic;
always @ (*) begin
if (rst == `RstEnable) begin
res_logic <= 32'b0;
end
else begin
case (op_i)
`op_and : begin
res_logic <= reg1_i & reg2_i;
end
`op_or : begin
res_logic <= reg1_i | reg2_i;
end
`op_xor : begin
res_logic <= reg1_i ^ reg2_i;
end
`op_nor : begin
res_logic <= ~(reg1_i | reg2_i);
end
default : begin
res_logic <= 32'b0;
end
endcase
end
end
reg[63:0] res_arith;
always @ (*) begin
if (rst == `RstEnable) begin
res_arith <= 32'b0;
end
else begin
case (op_i)
`op_slt : begin
res_arith <= (reg1_i[31] == 1'b1 && reg2_i[31] == 1'b0) || (reg1_i[31] == reg2_i[31] && reg_sum[31] == 1'b1);
end
`op_sltu : begin
res_arith <= reg1_i < reg2_i;
end
`op_add, `op_addu, `op_sub, `op_subu : begin
res_arith <= reg_sum;
end
default : begin
res_arith <= 32'b0;
end
endcase
end
end
reg[31:0] res_jmp;
always @ (*) begin
if (rst == `RstEnable) begin
res_jmp <= 32'b0;
end
else begin
res_jmp <= write_instr_i;
end
end
always @ (*) begin
case (op_i)
`op_add : begin
if (reg1_i[31] == reg2_i[31] && reg_sum[31] != reg1_i[31]) begin
we_o <= `WriteDisable;
end
else begin
we_o <= we_i;
end
end
`op_sub : begin
if (reg1_i[31] == reg2_comp[31] && reg1_i != reg_sum[31]) begin
we_o <= `WriteDisable;
end
else begin
we_o <= we_i;
end
end
default : begin
we_o <= we_i;
end
endcase
write_addr_o <= write_addr_i;
case (type)
`type_logic : begin
write_instr_o <= res_logic;
end
`type_arith : begin
write_instr_o <= res_arith[31:0];
end
`type_jmp : begin
write_instr_o <= res_jmp;
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
endmodule | 0 |
3,376 | data/full_repos/permissive/104305228/code/ex_mem.v | 104,305,228 | ex_mem.v | v | 41 | 90 | [] | [] | [] | [(143, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/ex_mem.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`StallEnable\'\n if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`StallDisable\'\n if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:24: Define or directive not defined: \'`op_null\'\n mem_op <= `op_null;\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_op <= `op_null;\n ^\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:27: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_we <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:31: syntax error, unexpected else\n else if (stall[3] == `StallDisable) begin\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:31: Define or directive not defined: \'`StallDisable\'\n else if (stall[3] == `StallDisable) begin\n ^~~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,098 | module | module ex_mem(
input clk,
input rst,
input [5:0] stall,
input [31:0] ex_instr,
input [7:0] ex_op,
input [31:0] ex_reg1,
input [31:0] ex_reg2,
input ex_we,
input [4:0] ex_write_addr,
input [31:0] ex_write_instr,
output reg[31:0] mem_instr,
output reg[7:0] mem_op,
output reg[31:0] mem_reg1,
output reg[31:0] mem_reg2,
output reg mem_we,
output reg[4:0] mem_write_addr,
output reg[31:0] mem_write_instr
);
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin
mem_instr <= 32'b0;
mem_op <= `op_null;
mem_reg1 <= 32'b0;
mem_reg2 <= 32'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write_instr <= 32'b0;
end
else if (stall[3] == `StallDisable) begin
mem_instr <= ex_instr;
mem_op <= ex_op;
mem_reg1 <= ex_reg1;
mem_reg2 <= ex_reg2;
mem_we <= ex_we;
mem_write_addr <= ex_write_addr;
mem_write_instr <= ex_write_instr;
end
end
endmodule | module ex_mem(
input clk,
input rst,
input [5:0] stall,
input [31:0] ex_instr,
input [7:0] ex_op,
input [31:0] ex_reg1,
input [31:0] ex_reg2,
input ex_we,
input [4:0] ex_write_addr,
input [31:0] ex_write_instr,
output reg[31:0] mem_instr,
output reg[7:0] mem_op,
output reg[31:0] mem_reg1,
output reg[31:0] mem_reg2,
output reg mem_we,
output reg[4:0] mem_write_addr,
output reg[31:0] mem_write_instr
); |
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin
mem_instr <= 32'b0;
mem_op <= `op_null;
mem_reg1 <= 32'b0;
mem_reg2 <= 32'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write_instr <= 32'b0;
end
else if (stall[3] == `StallDisable) begin
mem_instr <= ex_instr;
mem_op <= ex_op;
mem_reg1 <= ex_reg1;
mem_reg2 <= ex_reg2;
mem_we <= ex_we;
mem_write_addr <= ex_write_addr;
mem_write_instr <= ex_write_instr;
end
end
endmodule | 0 |
3,377 | data/full_repos/permissive/104305228/code/id.v | 104,305,228 | id.v | v | 635 | 163 | [] | [] | [] | [(143, 776)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/id.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/id.v:18: syntax error, unexpected type, expecting IDENTIFIER or do or final\n output reg[2:0] type,\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[31:0] reg2,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg1_re,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[4:0] reg1_read_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_re,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[4:0] reg2_read_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg we,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[4:0] write_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[31:0] write_instr,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg pc_we,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[31:0] pc_write_instr,\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg stallsignal\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lb\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lbu\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lh\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lhu\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lw\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lwl\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:35: Define or directive not defined: \'`op_lwr\'\n wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:38: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:39: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:40: Define or directive not defined: \'`op_null\'\n op <= `op_null;\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:41: Define or directive not defined: \'`type_null\'\n type <= `type_null;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:42: Define or directive not defined: \'`ReadDisable\'\n reg1_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:44: Define or directive not defined: \'`ReadDisable\'\n reg2_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:46: Define or directive not defined: \'`WriteDisable\'\n we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:49: Define or directive not defined: \'`WriteDisable\'\n pc_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:54: Define or directive not defined: \'`op_null\'\n op <= `op_null;\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:55: Define or directive not defined: \'`type_null\'\n type <= `type_null;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:56: Define or directive not defined: \'`ReadDisable\'\n reg1_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:58: Define or directive not defined: \'`ReadDisable\'\n reg2_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:60: Define or directive not defined: \'`WriteDisable\'\n we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:63: Define or directive not defined: \'`WriteDisable\'\n pc_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:72: Define or directive not defined: \'`opc_and\'\n `opc_and : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:73: Define or directive not defined: \'`op_and\'\n op <= `op_and;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:74: Define or directive not defined: \'`type_logic\'\n type <= `type_logic;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:75: Define or directive not defined: \'`ReadEnable\'\n reg1_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:76: Define or directive not defined: \'`ReadEnable\'\n reg2_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:77: Define or directive not defined: \'`WriteEnable\'\n we <= `WriteEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:79: Define or directive not defined: \'`opc_or\'\n `opc_or : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:80: Define or directive not defined: \'`op_or\'\n op <= `op_or;\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:81: Define or directive not defined: \'`type_logic\'\n type <= `type_logic;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:82: Define or directive not defined: \'`ReadEnable\'\n reg1_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:83: Define or directive not defined: \'`ReadEnable\'\n reg2_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:84: Define or directive not defined: \'`WriteEnable\'\n we <= `WriteEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:86: Define or directive not defined: \'`opc_xor\'\n `opc_xor : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:87: Define or directive not defined: \'`op_xor\'\n op <= `op_xor;\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id.v:88: Define or directive not defined: \'`type_logic\'\n type <= `type_logic;\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,099 | module | module id(
input rst,
input [31:0] instr_i,
input [31:0] reg1_read_instr,
input [31:0] reg2_read_instr,
input [31:0] pc_i,
input [7:0] ex_op,
input ex_we,
input [4:0] ex_write_addr,
input [31:0] ex_write_instr,
input mem_we,
input [4:0] mem_write_addr,
input [31:0] mem_write_instr,
output [31:0] instr_o,
output reg[7:0] op,
output reg[2:0] type,
output reg[31:0] reg1,
output reg[31:0] reg2,
output reg reg1_re,
output reg[4:0] reg1_read_addr,
output reg reg2_re,
output reg[4:0] reg2_read_addr,
output reg we,
output reg[4:0] write_addr,
output reg[31:0] write_instr,
output reg pc_we,
output reg[31:0] pc_write_instr,
output reg stallsignal
);
wire [31:0] pc_nxt = pc_i + 32'd4;
wire [31:0] pc_jmp = {pc_nxt[31:28], instr_i[25:0], 2'b0};
wire [31:0] pc_branch = pc_nxt + {{14{instr_i[15]}}, instr_i[15:0], 2'b00};
wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;
assign instr_o = instr_i;
reg[31:0] immediatevalue;
always @ (*) begin
if (rst == `RstEnable) begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg1_read_addr <= 5'b0;
reg2_re <= `ReadDisable;
reg2_read_addr <= 5'b0;
we <= `WriteDisable;
write_addr <= 5'b0;
write_instr <= 32'b0;
pc_we <= `WriteDisable;
pc_write_instr <= 32'b0;
immediatevalue <= 32'b0;
end
else begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg1_read_addr <= instr_i[25:21];
reg2_re <= `ReadDisable;
reg2_read_addr <= instr_i[20:16];
we <= `WriteDisable;
write_addr <= instr_i[15:11];
write_instr <= 32'b0;
pc_we <= `WriteDisable;
pc_write_instr <= 32'b0;
immediatevalue <= 32'b0;
case (instr_i[31:26])
6'b000000 : begin
case (instr_i[10:6])
5'b00000 : begin
case (instr_i[5:0])
`opc_and : begin
op <= `op_and;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_or : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_xor : begin
op <= `op_xor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_nor : begin
op <= `op_nor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sll : begin
op <= `op_sll;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_srl : begin
op <= `op_srl;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sra : begin
op <= `op_sra;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_null : begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_mfhi : begin
op <= `op_mfhi;
type <= `type_move;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mfho : begin
op <= `op_mfho;
type <= `type_move;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mthi : begin
op <= `op_mthi;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
end
`opc_mtho : begin
op <= `op_mtho;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
end
`opc_movn : begin
op <= `op_movn;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= (reg2 == 32'b0) ? `WriteDisable : `WriteEnable;
end
`opc_movz : begin
op <= `op_movz;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= (reg2 == 32'b0) ? `WriteDisable : `WriteEnable;
end
`opc_slt : begin
op <= `op_slt;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sltu : begin
op <= `op_sltu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_add : begin
op <= `op_add;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_addu : begin
op <= `op_addu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sub : begin
op <= `op_sub;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_subu : begin
op <= `op_subu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_mult : begin
op <= `op_mult;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_multu : begin
op <= `op_multu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_jr : begin
op <= `op_jr;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= `WriteEnable;
pc_write_instr <= reg1;
end
`opc_jalr : begin
op <= `op_jalr;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= `WriteEnable;
pc_write_instr <= reg1;
write_addr <= instr_i[15:11];
write_instr <= pc_i + 32'd8;
end
endcase
end
endcase
end
6'b000001 : begin
case (instr_i[20:16])
`opc_bgez : begin
op <= `op_bgez;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bgezal : begin
op <= `op_bgezal;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= (reg1[31] == 1'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
`opc_bltz : begin
op <= `op_bltz;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b1) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bltzal : begin
op <= `op_bltzal;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= (reg1[31] == 1'b1) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
endcase
end
6'b011100 : begin
case (instr_i[5:0])
`opc_clz : begin
op <= `op_clz;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_clo : begin
op <= `op_clo;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mul : begin
op <= `op_mul;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
endcase
end
`opc_andi : begin
op <= `op_and;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_ori : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_xori : begin
op <= `op_xor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_lui : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {instr_i[15:0], 16'b0};
end
`opc_pref : begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_slti : begin
op <= `op_slt;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_sltiu : begin
op <= `op_sltu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_addi : begin
op <= `op_add;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_addiu : begin
op <= `op_addu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_lb : begin
op <= `op_lb;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lbu : begin
op <= `op_lbu;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lh : begin
op <= `op_lh;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lhu : begin
op <= `op_lhu;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lw : begin
op <= `op_lw;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lwl : begin
op <= `op_lwl;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lwr : begin
op <= `op_lwr;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_sb : begin
op <= `op_sb;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_sh : begin
op <= `op_sh;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_sw : begin
op <= `op_sw;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_swl : begin
op <= `op_swl;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_swr : begin
op <= `op_swr;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_j : begin
op <= `op_j;
type <= `type_jmp;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= `WriteEnable;
pc_write_instr <= pc_jmp;
end
`opc_jal : begin
op <= `op_jal;
type <= `type_jmp;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= `WriteEnable;
pc_write_instr <= pc_jmp;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
`opc_beq : begin
op <= `op_beq;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
pc_we <= (reg1 == reg2) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bne : begin
op <= `op_bne;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
pc_we <= (reg1 != reg2) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bgtz : begin
op <= `op_bgtz;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b0 && reg1 != 32'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_blez : begin
op <= `op_blez;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b1 || reg1 == 32'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
endcase
if (instr_i[31:21] == 11'b0) begin
case (instr_i[5:0])
`opc_sll : begin
op <= `op_sll;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
`opc_srl : begin
op <= `op_srl;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
`opc_sra : begin
op <= `op_sra;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
endcase
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
stallsignal <= `StallDisable;
end
else begin
if (reg1_re == `ReadEnable && ex_op_status == 1'b1 && ex_write_addr == reg1_read_addr) begin
stallsignal <= `StallEnable;
end
else if (reg2_re == `ReadEnable && ex_op_status == 1'b1 && ex_write_addr == reg2_read_addr) begin
stallsignal <= `StallEnable;
end
else begin
stallsignal <= `StallDisable;
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
reg1 <= 32'b0;
end
else if (reg1_re == `ReadEnable && ex_we == `WriteEnable && ex_write_addr == reg1_read_addr) begin
reg1 <= ex_write_instr;
end
else if (reg1_re == `ReadEnable && mem_we == `WriteEnable && mem_write_addr == reg1_read_addr) begin
reg1 <= mem_write_instr;
end
else if (reg1_re == `ReadEnable) begin
reg1 <= reg1_read_instr;
end
else if (reg1_re == `ReadDisable) begin
reg1 <= immediatevalue;
end
else begin
reg1 <= 32'b0;
end
end
always @ (*) begin
if (rst == `RstEnable) begin
reg2 <= 32'b0;
end
else if (reg2_re == `ReadEnable && ex_we == `WriteEnable && ex_write_addr == reg2_read_addr) begin
reg2 <= ex_write_instr;
end
else if (reg2_re == `ReadEnable && mem_we == `WriteEnable && mem_write_addr == reg2_read_addr) begin
reg2 <= mem_write_instr;
end
else if (reg2_re == `ReadEnable) begin
reg2 <= reg2_read_instr;
end
else if (reg2_re == `ReadDisable) begin
reg2 <= immediatevalue;
end
else begin
reg2 <= 32'b0;
end
end
endmodule | module id(
input rst,
input [31:0] instr_i,
input [31:0] reg1_read_instr,
input [31:0] reg2_read_instr,
input [31:0] pc_i,
input [7:0] ex_op,
input ex_we,
input [4:0] ex_write_addr,
input [31:0] ex_write_instr,
input mem_we,
input [4:0] mem_write_addr,
input [31:0] mem_write_instr,
output [31:0] instr_o,
output reg[7:0] op,
output reg[2:0] type,
output reg[31:0] reg1,
output reg[31:0] reg2,
output reg reg1_re,
output reg[4:0] reg1_read_addr,
output reg reg2_re,
output reg[4:0] reg2_read_addr,
output reg we,
output reg[4:0] write_addr,
output reg[31:0] write_instr,
output reg pc_we,
output reg[31:0] pc_write_instr,
output reg stallsignal
); |
wire [31:0] pc_nxt = pc_i + 32'd4;
wire [31:0] pc_jmp = {pc_nxt[31:28], instr_i[25:0], 2'b0};
wire [31:0] pc_branch = pc_nxt + {{14{instr_i[15]}}, instr_i[15:0], 2'b00};
wire [31:0] ex_op_status = ex_op == `op_lb || ex_op == `op_lbu || ex_op == `op_lh || ex_op == `op_lhu || ex_op == `op_lw || ex_op == `op_lwl || ex_op == `op_lwr;
assign instr_o = instr_i;
reg[31:0] immediatevalue;
always @ (*) begin
if (rst == `RstEnable) begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg1_read_addr <= 5'b0;
reg2_re <= `ReadDisable;
reg2_read_addr <= 5'b0;
we <= `WriteDisable;
write_addr <= 5'b0;
write_instr <= 32'b0;
pc_we <= `WriteDisable;
pc_write_instr <= 32'b0;
immediatevalue <= 32'b0;
end
else begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg1_read_addr <= instr_i[25:21];
reg2_re <= `ReadDisable;
reg2_read_addr <= instr_i[20:16];
we <= `WriteDisable;
write_addr <= instr_i[15:11];
write_instr <= 32'b0;
pc_we <= `WriteDisable;
pc_write_instr <= 32'b0;
immediatevalue <= 32'b0;
case (instr_i[31:26])
6'b000000 : begin
case (instr_i[10:6])
5'b00000 : begin
case (instr_i[5:0])
`opc_and : begin
op <= `op_and;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_or : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_xor : begin
op <= `op_xor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_nor : begin
op <= `op_nor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sll : begin
op <= `op_sll;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_srl : begin
op <= `op_srl;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sra : begin
op <= `op_sra;
type <= `type_shift;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_null : begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_mfhi : begin
op <= `op_mfhi;
type <= `type_move;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mfho : begin
op <= `op_mfho;
type <= `type_move;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mthi : begin
op <= `op_mthi;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
end
`opc_mtho : begin
op <= `op_mtho;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
end
`opc_movn : begin
op <= `op_movn;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= (reg2 == 32'b0) ? `WriteDisable : `WriteEnable;
end
`opc_movz : begin
op <= `op_movz;
type <= `type_move;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= (reg2 == 32'b0) ? `WriteDisable : `WriteEnable;
end
`opc_slt : begin
op <= `op_slt;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sltu : begin
op <= `op_sltu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_add : begin
op <= `op_add;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_addu : begin
op <= `op_addu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_sub : begin
op <= `op_sub;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_subu : begin
op <= `op_subu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
`opc_mult : begin
op <= `op_mult;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_multu : begin
op <= `op_multu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_jr : begin
op <= `op_jr;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= `WriteEnable;
pc_write_instr <= reg1;
end
`opc_jalr : begin
op <= `op_jalr;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= `WriteEnable;
pc_write_instr <= reg1;
write_addr <= instr_i[15:11];
write_instr <= pc_i + 32'd8;
end
endcase
end
endcase
end
6'b000001 : begin
case (instr_i[20:16])
`opc_bgez : begin
op <= `op_bgez;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bgezal : begin
op <= `op_bgezal;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= (reg1[31] == 1'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
`opc_bltz : begin
op <= `op_bltz;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b1) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bltzal : begin
op <= `op_bltzal;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= (reg1[31] == 1'b1) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
endcase
end
6'b011100 : begin
case (instr_i[5:0])
`opc_clz : begin
op <= `op_clz;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_clo : begin
op <= `op_clo;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
end
`opc_mul : begin
op <= `op_mul;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
end
endcase
end
`opc_andi : begin
op <= `op_and;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_ori : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_xori : begin
op <= `op_xor;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {16'b0, instr_i[15:0]};
end
`opc_lui : begin
op <= `op_or;
type <= `type_logic;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {instr_i[15:0], 16'b0};
end
`opc_pref : begin
op <= `op_null;
type <= `type_null;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_slti : begin
op <= `op_slt;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_sltiu : begin
op <= `op_sltu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_addi : begin
op <= `op_add;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_addiu : begin
op <= `op_addu;
type <= `type_arith;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
immediatevalue <= {{16{instr_i[15]}}, instr_i[15:0]};
end
`opc_lb : begin
op <= `op_lb;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lbu : begin
op <= `op_lbu;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lh : begin
op <= `op_lh;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lhu : begin
op <= `op_lhu;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lw : begin
op <= `op_lw;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lwl : begin
op <= `op_lwl;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_lwr : begin
op <= `op_lwr;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[20:16];
end
`opc_sb : begin
op <= `op_sb;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_sh : begin
op <= `op_sh;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_sw : begin
op <= `op_sw;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_swl : begin
op <= `op_swl;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_swr : begin
op <= `op_swr;
type <= `type_memory;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
end
`opc_j : begin
op <= `op_j;
type <= `type_jmp;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= `WriteEnable;
pc_write_instr <= pc_jmp;
end
`opc_jal : begin
op <= `op_jal;
type <= `type_jmp;
reg1_re <= `ReadDisable;
reg2_re <= `ReadDisable;
we <= `WriteEnable;
pc_we <= `WriteEnable;
pc_write_instr <= pc_jmp;
write_addr <= 5'b11111;
write_instr <= pc_i + 32'd8;
end
`opc_beq : begin
op <= `op_beq;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
pc_we <= (reg1 == reg2) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bne : begin
op <= `op_bne;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadEnable;
we <= `WriteDisable;
pc_we <= (reg1 != reg2) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_bgtz : begin
op <= `op_bgtz;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b0 && reg1 != 32'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
`opc_blez : begin
op <= `op_blez;
type <= `type_jmp;
reg1_re <= `ReadEnable;
reg2_re <= `ReadDisable;
we <= `WriteDisable;
pc_we <= (reg1[31] == 1'b1 || reg1 == 32'b0) ? `WriteEnable : `WriteDisable;
pc_write_instr <= pc_branch;
end
endcase
if (instr_i[31:21] == 11'b0) begin
case (instr_i[5:0])
`opc_sll : begin
op <= `op_sll;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
`opc_srl : begin
op <= `op_srl;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
`opc_sra : begin
op <= `op_sra;
type <= `type_shift;
reg1_re <= `ReadDisable;
reg2_re <= `ReadEnable;
we <= `WriteEnable;
write_addr <= instr_i[15:11];
immediatevalue[4:0] <= instr_i[10:6];
end
endcase
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
stallsignal <= `StallDisable;
end
else begin
if (reg1_re == `ReadEnable && ex_op_status == 1'b1 && ex_write_addr == reg1_read_addr) begin
stallsignal <= `StallEnable;
end
else if (reg2_re == `ReadEnable && ex_op_status == 1'b1 && ex_write_addr == reg2_read_addr) begin
stallsignal <= `StallEnable;
end
else begin
stallsignal <= `StallDisable;
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
reg1 <= 32'b0;
end
else if (reg1_re == `ReadEnable && ex_we == `WriteEnable && ex_write_addr == reg1_read_addr) begin
reg1 <= ex_write_instr;
end
else if (reg1_re == `ReadEnable && mem_we == `WriteEnable && mem_write_addr == reg1_read_addr) begin
reg1 <= mem_write_instr;
end
else if (reg1_re == `ReadEnable) begin
reg1 <= reg1_read_instr;
end
else if (reg1_re == `ReadDisable) begin
reg1 <= immediatevalue;
end
else begin
reg1 <= 32'b0;
end
end
always @ (*) begin
if (rst == `RstEnable) begin
reg2 <= 32'b0;
end
else if (reg2_re == `ReadEnable && ex_we == `WriteEnable && ex_write_addr == reg2_read_addr) begin
reg2 <= ex_write_instr;
end
else if (reg2_re == `ReadEnable && mem_we == `WriteEnable && mem_write_addr == reg2_read_addr) begin
reg2 <= mem_write_instr;
end
else if (reg2_re == `ReadEnable) begin
reg2 <= reg2_read_instr;
end
else if (reg2_re == `ReadDisable) begin
reg2 <= immediatevalue;
end
else begin
reg2 <= 32'b0;
end
end
endmodule | 0 |
3,378 | data/full_repos/permissive/104305228/code/id_ex.v | 104,305,228 | id_ex.v | v | 46 | 90 | [] | [] | [] | [(143, 187)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/id_ex.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`StallEnable\'\n if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`StallDisable\'\n if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:27: Define or directive not defined: \'`op_null\'\n ex_op <= `op_null;\n ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_op <= `op_null;\n ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:28: Define or directive not defined: \'`type_null\'\n ex_type <= `type_null;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_type <= `type_null;\n ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:31: Define or directive not defined: \'`WriteDisable\'\n ex_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_we <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:35: syntax error, unexpected else\n else if (stall[2] == `StallDisable) begin\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:35: Define or directive not defined: \'`StallDisable\'\n else if (stall[2] == `StallDisable) begin\n ^~~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,100 | module | module id_ex(
input clk,
input rst,
input [5:0] stall,
input [31:0] id_instr,
input [7:0] id_op,
input [2:0] id_type,
input [31:0] id_reg1,
input [31:0] id_reg2,
input id_we,
input [4:0] id_write_addr,
input [31:0] id_write_instr,
output reg[31:0] ex_instr,
output reg[7:0] ex_op,
output reg[2:0] ex_type,
output reg[31:0] ex_reg1,
output reg[31:0] ex_reg2,
output reg ex_we,
output reg[4:0] ex_write_addr,
output reg[31:0] ex_write_instr
);
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin
ex_instr <= 32'b0;
ex_op <= `op_null;
ex_type <= `type_null;
ex_reg1 <= 32'b0;
ex_reg2 <= 32'b0;
ex_we <= `WriteDisable;
ex_write_addr <= 32'b0;
ex_write_instr <= 32'b0;
end
else if (stall[2] == `StallDisable) begin
ex_instr <= id_instr;
ex_op <= id_op;
ex_type <= id_type;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_we <= id_we;
ex_write_addr <= id_write_addr;
ex_write_instr <= id_write_instr;
end
end
endmodule | module id_ex(
input clk,
input rst,
input [5:0] stall,
input [31:0] id_instr,
input [7:0] id_op,
input [2:0] id_type,
input [31:0] id_reg1,
input [31:0] id_reg2,
input id_we,
input [4:0] id_write_addr,
input [31:0] id_write_instr,
output reg[31:0] ex_instr,
output reg[7:0] ex_op,
output reg[2:0] ex_type,
output reg[31:0] ex_reg1,
output reg[31:0] ex_reg2,
output reg ex_we,
output reg[4:0] ex_write_addr,
output reg[31:0] ex_write_instr
); |
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin
ex_instr <= 32'b0;
ex_op <= `op_null;
ex_type <= `type_null;
ex_reg1 <= 32'b0;
ex_reg2 <= 32'b0;
ex_we <= `WriteDisable;
ex_write_addr <= 32'b0;
ex_write_instr <= 32'b0;
end
else if (stall[2] == `StallDisable) begin
ex_instr <= id_instr;
ex_op <= id_op;
ex_type <= id_type;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_we <= id_we;
ex_write_addr <= id_write_addr;
ex_write_instr <= id_write_instr;
end
end
endmodule | 0 |
3,379 | data/full_repos/permissive/104305228/code/if.v | 104,305,228 | if.v | v | 22 | 45 | [] | [] | [] | null | line:10 column:15: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/104305228/code/if.v:1: syntax error, unexpected iff, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule iff(\n ^~~\n%Error: data/full_repos/permissive/104305228/code/if.v:8: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: Exiting due to 2 error(s)\n" | 1,101 | module | module iff(
input clk,
input rst,
input [5:0] stall,
input pc_we,
input pc_write_instr,
output reg[31:0] pc_read_instr
);
always @ (posedge clk) begin
if (rst == 'RstEnable) begin
pc_read_instr <= 32'b0;
else
else if (stall[0] == 'StallDisable) begin
if (pc_we == 'WriteEnable) begin
pc_read_instr <= pc_write_instr;
end
else begin
pc_read_instr <= pc_write_instr + 32'd4;
end
end
end
endmodule | module iff(
input clk,
input rst,
input [5:0] stall,
input pc_we,
input pc_write_instr,
output reg[31:0] pc_read_instr
); |
always @ (posedge clk) begin
if (rst == 'RstEnable) begin
pc_read_instr <= 32'b0;
else
else if (stall[0] == 'StallDisable) begin
if (pc_we == 'WriteEnable) begin
pc_read_instr <= pc_write_instr;
end
else begin
pc_read_instr <= pc_write_instr + 32'd4;
end
end
end
endmodule | 0 |
3,380 | data/full_repos/permissive/104305228/code/if_id.v | 104,305,228 | if_id.v | v | 22 | 90 | [] | [] | [] | [(143, 163)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/if_id.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/if_id.v:13: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/if_id.v:13: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/if_id.v:13: Define or directive not defined: \'`StallEnable\'\n if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/if_id.v:13: Define or directive not defined: \'`StallDisable\'\n if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/if_id.v:17: syntax error, unexpected else\n else if (stall[1] == `StallDisable) begin\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/if_id.v:17: Define or directive not defined: \'`StallDisable\'\n else if (stall[1] == `StallDisable) begin\n ^~~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,103 | module | module if_id(
input clk,
input rst,
input [5:0] stall,
input [31:0] if_pc,
input [31:0] if_instr,
output reg[31:0] id_pc,
output reg[31:0] id_instr
);
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin
id_pc <= 32'b0;
id_instr <= 32'b0;
end
else if (stall[1] == `StallDisable) begin
id_pc <= if_pc;
id_instr <= if_instr;
end
end
endmodule | module if_id(
input clk,
input rst,
input [5:0] stall,
input [31:0] if_pc,
input [31:0] if_instr,
output reg[31:0] id_pc,
output reg[31:0] id_instr
); |
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[1] == `StallEnable && stall[2] == `StallDisable)) begin
id_pc <= 32'b0;
id_instr <= 32'b0;
end
else if (stall[1] == `StallDisable) begin
id_pc <= if_pc;
id_instr <= if_instr;
end
end
endmodule | 0 |
3,381 | data/full_repos/permissive/104305228/code/mem.v | 104,305,228 | mem.v | v | 173 | 59 | [] | [] | [] | [(143, 313)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/mem.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/mem.v:25: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:25: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:26: Define or directive not defined: \'`ReadDisable\'\n mem_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:28: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_we <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:32: Define or directive not defined: \'`WriteDisable\'\n we_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n we_o <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:36: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:37: Define or directive not defined: \'`ReadDisable\'\n mem_re <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:39: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:47: Define or directive not defined: \'`op_lb\'\n `op_lb : begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:47: syntax error, unexpected \':\', expecting endcase\n `op_lb : begin\n ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:48: Define or directive not defined: \'`ReadEnable\'\n mem_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:50: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:53: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:56: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:59: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:62: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:65: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= 32\'b0;\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:68: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:69: Define or directive not defined: \'`op_lbu\'\n `op_lbu : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:70: Define or directive not defined: \'`ReadEnable\'\n mem_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:72: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:75: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {24\'b0, mem_i[31:24]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:78: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {24\'b0, mem_i[23:16]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:81: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {24\'b0, mem_i[15:8]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:84: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {24\'b0, mem_i[7:0]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:87: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= 32\'b0;\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:90: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:91: Define or directive not defined: \'`op_lh\'\n `op_lh : begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:92: Define or directive not defined: \'`ReadEnable\'\n mem_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:94: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:97: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:100: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= 32\'b0;\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:106: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:107: Define or directive not defined: \'`op_lhu\'\n `op_lhu : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:108: Define or directive not defined: \'`ReadEnable\'\n mem_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:110: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:113: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {16\'b0, mem_i[31:16]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:116: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= {16\'b0, mem_i[15:0]};\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:119: syntax error, unexpected <=, expecting IDENTIFIER\n write_instr_o <= 32\'b0;\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:122: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:123: Define or directive not defined: \'`op_lw\'\n `op_lw : begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:124: Define or directive not defined: \'`ReadEnable\'\n mem_re <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:126: Define or directive not defined: \'`WriteDisable\'\n mem_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:129: Define or directive not defined: \'`op_lwr\'\n `op_lwr : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:131: Define or directive not defined: \'`op_lwl\'\n `op_lwl : begin\n ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:133: Define or directive not defined: \'`op_sb\'\n `op_sb : begin\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,104 | module | module mem(
input rst,
input [31:0] instr,
input [7:0] op,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] mem_i,
input we_i,
input [4:0] write_addr_i,
input [31:0] write_instr_i,
output reg mem_re,
output reg[31:0] mem_read_addr,
output reg mem_we,
output reg[31:0] mem_write_addr,
output reg[3:0] mem_write,
output reg[31:0] mem_write_instr,
output reg we_o,
output reg[4:0] write_addr_o,
output reg[31:0] write_instr_o
);
wire [31:0] addr = reg1 + {{16{instr[15]}}, instr[15:0]};
always @ (*) begin
if (rst == `RstEnable) begin
mem_re <= `ReadDisable;
mem_read_addr <= 5'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write <= 4'b0;
mem_write_instr <= 32'b0;
we_o <= `WriteDisable;
write_addr_o <= 5'b0;
write_instr_o <= 32'b0;
end
else begin
mem_re <= `ReadDisable;
mem_read_addr <= 5'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write <= 4'b0;
mem_write_instr <= 32'b0;
we_o <= we_i;
write_addr_o <= write_addr_i;
write_instr_o <= write_instr_i;
case (op)
`op_lb : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};
end
2'b01 : begin
write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};
end
2'b10 : begin
write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};
end
2'b11 : begin
write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lbu : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {24'b0, mem_i[31:24]};
end
2'b01 : begin
write_instr_o <= {24'b0, mem_i[23:16]};
end
2'b10 : begin
write_instr_o <= {24'b0, mem_i[15:8]};
end
2'b11 : begin
write_instr_o <= {24'b0, mem_i[7:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lh : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};
end
2'b10 : begin
write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lhu : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {16'b0, mem_i[31:16]};
end
2'b10 : begin
write_instr_o <= {16'b0, mem_i[15:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lw : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
write_instr_o <= mem_i;
end
`op_lwr : begin
end
`op_lwl : begin
end
`op_sb : begin
mem_re <= `ReadDisable;
mem_write_addr <= addr;
mem_we <= `WriteEnable;
mem_write_instr <= {4{reg2[7:0]}};
case (addr[1:0])
2'b00 : begin
mem_write <= 4'b1000;
end
2'b01 : begin
mem_write <= 4'b0100;
end
2'b10 : begin
mem_write <= 4'b0010;
end
2'b11 : begin
mem_write <= 4'b0001;
end
default : begin
mem_write <= 4'b0000;
end
endcase
end
`op_sh : begin
end
`op_sw : begin
mem_re <= `ReadDisable;
mem_write_addr <= addr;
mem_we <= `WriteEnable;
mem_write_instr <= reg2;
mem_write <= 4'b1111;
end
`op_swl : begin
end
`op_swr : begin
end
endcase
end
end
endmodule | module mem(
input rst,
input [31:0] instr,
input [7:0] op,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] mem_i,
input we_i,
input [4:0] write_addr_i,
input [31:0] write_instr_i,
output reg mem_re,
output reg[31:0] mem_read_addr,
output reg mem_we,
output reg[31:0] mem_write_addr,
output reg[3:0] mem_write,
output reg[31:0] mem_write_instr,
output reg we_o,
output reg[4:0] write_addr_o,
output reg[31:0] write_instr_o
); |
wire [31:0] addr = reg1 + {{16{instr[15]}}, instr[15:0]};
always @ (*) begin
if (rst == `RstEnable) begin
mem_re <= `ReadDisable;
mem_read_addr <= 5'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write <= 4'b0;
mem_write_instr <= 32'b0;
we_o <= `WriteDisable;
write_addr_o <= 5'b0;
write_instr_o <= 32'b0;
end
else begin
mem_re <= `ReadDisable;
mem_read_addr <= 5'b0;
mem_we <= `WriteDisable;
mem_write_addr <= 5'b0;
mem_write <= 4'b0;
mem_write_instr <= 32'b0;
we_o <= we_i;
write_addr_o <= write_addr_i;
write_instr_o <= write_instr_i;
case (op)
`op_lb : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};
end
2'b01 : begin
write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};
end
2'b10 : begin
write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};
end
2'b11 : begin
write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lbu : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {24'b0, mem_i[31:24]};
end
2'b01 : begin
write_instr_o <= {24'b0, mem_i[23:16]};
end
2'b10 : begin
write_instr_o <= {24'b0, mem_i[15:8]};
end
2'b11 : begin
write_instr_o <= {24'b0, mem_i[7:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lh : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};
end
2'b10 : begin
write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lhu : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
case (addr[1:0])
2'b00 : begin
write_instr_o <= {16'b0, mem_i[31:16]};
end
2'b10 : begin
write_instr_o <= {16'b0, mem_i[15:0]};
end
default : begin
write_instr_o <= 32'b0;
end
endcase
end
`op_lw : begin
mem_re <= `ReadEnable;
mem_read_addr <= addr;
mem_we <= `WriteDisable;
write_instr_o <= mem_i;
end
`op_lwr : begin
end
`op_lwl : begin
end
`op_sb : begin
mem_re <= `ReadDisable;
mem_write_addr <= addr;
mem_we <= `WriteEnable;
mem_write_instr <= {4{reg2[7:0]}};
case (addr[1:0])
2'b00 : begin
mem_write <= 4'b1000;
end
2'b01 : begin
mem_write <= 4'b0100;
end
2'b10 : begin
mem_write <= 4'b0010;
end
2'b11 : begin
mem_write <= 4'b0001;
end
default : begin
mem_write <= 4'b0000;
end
endcase
end
`op_sh : begin
end
`op_sw : begin
mem_re <= `ReadDisable;
mem_write_addr <= addr;
mem_we <= `WriteEnable;
mem_write_instr <= reg2;
mem_write <= 4'b1111;
end
`op_swl : begin
end
`op_swr : begin
end
endcase
end
end
endmodule | 0 |
3,382 | data/full_repos/permissive/104305228/code/mem_wb.v | 104,305,228 | mem_wb.v | v | 26 | 90 | [] | [] | [] | [(143, 167)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/mem_wb.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`StallEnable\'\n if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`StallDisable\'\n if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:16: Define or directive not defined: \'`WriteDisable\'\n wb_we <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:20: syntax error, unexpected else\n else if (stall[4] == `StallDisable) begin\n ^~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:20: Define or directive not defined: \'`StallDisable\'\n else if (stall[4] == `StallDisable) begin\n ^~~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,105 | module | module mem_wb(
input clk,
input rst,
input [5:0] stall,
input mem_we,
input [4:0] mem_write_addr,
input [31:0] mem_write_instr,
output reg wb_we,
output reg[4:0] wb_write_addr,
output reg[31:0] wb_write_instr
);
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin
wb_we <= `WriteDisable;
wb_write_addr <= 5'b0;
wb_write_instr <= 32'b0;
end
else if (stall[4] == `StallDisable) begin
wb_we <= mem_we;
wb_write_addr <= mem_write_addr;
wb_write_instr <= mem_write_instr;
end
end
endmodule | module mem_wb(
input clk,
input rst,
input [5:0] stall,
input mem_we,
input [4:0] mem_write_addr,
input [31:0] mem_write_instr,
output reg wb_we,
output reg[4:0] wb_write_addr,
output reg[31:0] wb_write_instr
); |
always @ (posedge clk) begin
if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin
wb_we <= `WriteDisable;
wb_write_addr <= 5'b0;
wb_write_instr <= 32'b0;
end
else if (stall[4] == `StallDisable) begin
wb_we <= mem_we;
wb_write_addr <= mem_write_addr;
wb_write_instr <= mem_write_instr;
end
end
endmodule | 0 |
3,383 | data/full_repos/permissive/104305228/code/ram.v | 104,305,228 | ram.v | v | 39 | 62 | [] | [] | [] | [(143, 180)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/ram.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: Define or directive not defined: \'`ChipEnable\'\n if (ce == `ChipEnable && re == `ReadEnable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (ce == `ChipEnable && re == `ReadEnable) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: Define or directive not defined: \'`ReadEnable\'\n if (ce == `ChipEnable && re == `ReadEnable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:24: Define or directive not defined: \'`ChipEnable\'\n if (ce == `ChipEnable && we == `WriteEnable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:24: Define or directive not defined: \'`WriteEnable\'\n if (ce == `ChipEnable && we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,106 | module | module ram(
input clk,
input ce,
input re,
input we,
input [31:0] read_addr,
output reg[31:0] read_instr,
input [31:0] write_addr,
input [31:0] write_instr,
input [3:0] write
);
reg [31:0] instr_mem[0:1023];
always @ (*) begin
if (ce == `ChipEnable && re == `ReadEnable) begin
read_instr <= instr_mem[read_addr[18:2]];
end
else begin
read_instr <= 32'b0;
end
end
always @ (negedge clk) begin
if (ce == `ChipEnable && we == `WriteEnable) begin
if (write[3] == 1'b1) begin
instr_mem[write_addr[18:2]][31:24] <= write_instr[31:24];
end
if (write[2] == 1'b1) begin
instr_mem[write_addr[18:2]][23:16] <= write_instr[23:16];
end
if (write[1] == 1'b1) begin
instr_mem[write_addr[18:2]][15:8] <= write_instr[15:8];
end
if (write[0] == 1'b1) begin
instr_mem[write_addr[18:2]][7:0] <= write_instr[7:0];
end
end
end
endmodule | module ram(
input clk,
input ce,
input re,
input we,
input [31:0] read_addr,
output reg[31:0] read_instr,
input [31:0] write_addr,
input [31:0] write_instr,
input [3:0] write
); |
reg [31:0] instr_mem[0:1023];
always @ (*) begin
if (ce == `ChipEnable && re == `ReadEnable) begin
read_instr <= instr_mem[read_addr[18:2]];
end
else begin
read_instr <= 32'b0;
end
end
always @ (negedge clk) begin
if (ce == `ChipEnable && we == `WriteEnable) begin
if (write[3] == 1'b1) begin
instr_mem[write_addr[18:2]][31:24] <= write_instr[31:24];
end
if (write[2] == 1'b1) begin
instr_mem[write_addr[18:2]][23:16] <= write_instr[23:16];
end
if (write[1] == 1'b1) begin
instr_mem[write_addr[18:2]][15:8] <= write_instr[15:8];
end
if (write[0] == 1'b1) begin
instr_mem[write_addr[18:2]][7:0] <= write_instr[7:0];
end
end
end
endmodule | 0 |
3,384 | data/full_repos/permissive/104305228/code/register.v | 104,305,228 | register.v | v | 41 | 76 | [] | [] | [] | [(143, 181)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/register.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/register.v:18: Define or directive not defined: \'`RstDisable\'\n if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:18: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n ^~\n%Error: data/full_repos/permissive/104305228/code/register.v:18: Define or directive not defined: \'`ReadEnable\'\n if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:27: Define or directive not defined: \'`RstDisable\'\n if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5\'b0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:27: Define or directive not defined: \'`ReadEnable\'\n if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5\'b0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:36: Define or directive not defined: \'`RstDisable\'\n if (rst == `RstDisable && we == `WriteEnable && write_addr != 5\'b0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:36: Define or directive not defined: \'`WriteEnable\'\n if (rst == `RstDisable && we == `WriteEnable && write_addr != 5\'b0) begin\n ^~~~~~~~~~~~\n%Error: Cannot continue\n' | 1,107 | module | module register(
input clk,
input rst,
input re1,
input [4:0] read_addr1,
input re2,
input [4:0] read_addr2,
input we,
input [4:0] write_addr,
input [31:0] write_instr,
output reg[31:0] read_instr1,
output reg[31:0] read_instr2
);
reg[31:0] instr[31:0];
always @ (*) begin
if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5'b0) begin
read_instr1 <= instr[read_addr1];
end
else begin
read_instr1 <= 32'b0;
end
end
always @ (*) begin
if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5'b0) begin
read_instr2 <= instr[read_addr2];
end
else begin
read_instr2 <= 32'b0;
end
end
always @ (negedge clk) begin
if (rst == `RstDisable && we == `WriteEnable && write_addr != 5'b0) begin
instr[write_addr] <= write_instr;
end
end
endmodule | module register(
input clk,
input rst,
input re1,
input [4:0] read_addr1,
input re2,
input [4:0] read_addr2,
input we,
input [4:0] write_addr,
input [31:0] write_instr,
output reg[31:0] read_instr1,
output reg[31:0] read_instr2
); |
reg[31:0] instr[31:0];
always @ (*) begin
if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5'b0) begin
read_instr1 <= instr[read_addr1];
end
else begin
read_instr1 <= 32'b0;
end
end
always @ (*) begin
if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5'b0) begin
read_instr2 <= instr[read_addr2];
end
else begin
read_instr2 <= 32'b0;
end
end
always @ (negedge clk) begin
if (rst == `RstDisable && we == `WriteEnable && write_addr != 5'b0) begin
instr[write_addr] <= write_instr;
end
end
endmodule | 0 |
3,385 | data/full_repos/permissive/104305228/code/rom.v | 104,305,228 | rom.v | v | 17 | 48 | [] | [] | [] | [(143, 158)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/rom.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/rom.v:10: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/rom.v:10: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (ce == `ChipDisable) begin\n ^\n%Error: Cannot continue\n' | 1,108 | module | module rom(
input ce,
input [31:0] instr_addr,
output reg[31:0] instr
);
reg [31:0] instr_mem[0:1023];
initial $readmemh("inst_rom.data", instr_mem);
always @ (*) begin
if (ce == `ChipDisable) begin
instr <= 32'b0;
end
else begin
instr <= instr_mem[instr_addr[18:2]];
end
end
endmodule | module rom(
input ce,
input [31:0] instr_addr,
output reg[31:0] instr
); |
reg [31:0] instr_mem[0:1023];
initial $readmemh("inst_rom.data", instr_mem);
always @ (*) begin
if (ce == `ChipDisable) begin
instr <= 32'b0;
end
else begin
instr <= instr_mem[instr_addr[18:2]];
end
end
endmodule | 0 |
3,386 | data/full_repos/permissive/104305228/code/sopc.v | 104,305,228 | sopc.v | v | 38 | 70 | [] | [] | [] | [(143, 179)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/sopc.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/sopc.v:27: Define or directive not defined: \'`RstEnable\'\n assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/sopc.v:27: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^\n%Error: data/full_repos/permissive/104305228/code/sopc.v:27: Define or directive not defined: \'`ChipDisable\'\n assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/sopc.v:27: Define or directive not defined: \'`ChipEnable\'\n assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/sopc.v:28: Define or directive not defined: \'`RstEnable\'\n assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/sopc.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^\n%Error: data/full_repos/permissive/104305228/code/sopc.v:28: Define or directive not defined: \'`ChipDisable\'\n assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/sopc.v:28: Define or directive not defined: \'`ChipEnable\'\n assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;\n ^~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 1,109 | module | module sopc(
input clk,
input rst
);
wire [31:0] rom_instr_addr;
wire rom_ce;
wire [31:0] rom_instr;
wire ram_ce;
wire ram_we;
wire ram_re;
wire [31:0] ram_read_addr;
wire [31:0] ram_read_instr;
wire [31:0] ram_write_addr;
wire [31:0] ram_write_instr;
wire [3:0] ram_write;
cpu cpu(
.clk(clk), .rst(rst),
.rom_read_addr(rom_instr_addr), .rom_read_instr(rom_instr),
.ram_we(ram_we), .ram_re(ram_re),
.ram_read_addr(ram_read_addr), .ram_read_instr(ram_read_instr),
.ram_write_addr(ram_write_addr), .ram_write_instr(ram_write_instr),
.ram_write(ram_write)
);
assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;
assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;
rom rom(
.ce(rom_ce), .instr_addr(rom_instr_addr), .instr(rom_instr)
);
ram ram(
.clk(clk), .ce(ram.ce), .re(ram.re), .we(ram.we),
.read_addr(ram_read_addr), .read_instr(ram_read_instr),
.write_addr(ram_write_addr), .write_instr(ram_write_instr),
.write(ram_write)
);
endmodule | module sopc(
input clk,
input rst
); |
wire [31:0] rom_instr_addr;
wire rom_ce;
wire [31:0] rom_instr;
wire ram_ce;
wire ram_we;
wire ram_re;
wire [31:0] ram_read_addr;
wire [31:0] ram_read_instr;
wire [31:0] ram_write_addr;
wire [31:0] ram_write_instr;
wire [3:0] ram_write;
cpu cpu(
.clk(clk), .rst(rst),
.rom_read_addr(rom_instr_addr), .rom_read_instr(rom_instr),
.ram_we(ram_we), .ram_re(ram_re),
.ram_read_addr(ram_read_addr), .ram_read_instr(ram_read_instr),
.ram_write_addr(ram_write_addr), .ram_write_instr(ram_write_instr),
.ram_write(ram_write)
);
assign rom_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;
assign ram_ce = (rst == `RstEnable) ? `ChipDisable : `ChipEnable;
rom rom(
.ce(rom_ce), .instr_addr(rom_instr_addr), .instr(rom_instr)
);
ram ram(
.clk(clk), .ce(ram.ce), .re(ram.re), .we(ram.we),
.read_addr(ram_read_addr), .read_instr(ram_read_instr),
.write_addr(ram_write_addr), .write_instr(ram_write_instr),
.write(ram_write)
);
endmodule | 0 |
3,387 | data/full_repos/permissive/104305228/code/tb.v | 104,305,228 | tb.v | v | 23 | 36 | [] | [] | [] | null | line:157: before: "$" | null | 1: b'%Error: data/full_repos/permissive/104305228/code/tb.v:2: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104305228/code/tb.v:14: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/tb.v:14: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/104305228/code/tb.v:15: Define or directive not defined: \'`RstDisable\'\n #195 rst = `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1000 $stop;\n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 1,110 | module | module tb();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#1000 $stop;
end
sopc sopc(
.clk(CLOCK_50), .rst(rst)
);
endmodule | module tb(); |
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#1000 $stop;
end
sopc sopc(
.clk(CLOCK_50), .rst(rst)
);
endmodule | 0 |
3,388 | data/full_repos/permissive/104305228/code/wb.v | 104,305,228 | wb.v | v | 13 | 30 | [] | [] | [] | [(143, 153)] | null | null | 1: b'%Error: data/full_repos/permissive/104305228/code/wb.v:1: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,111 | module | module wb(
input clk,
input rst
);
always @ (posedge clk) begin
end
always @ (posedge clk) begin
end
endmodule | module wb(
input clk,
input rst
); |
always @ (posedge clk) begin
end
always @ (posedge clk) begin
end
endmodule | 0 |
3,389 | data/full_repos/permissive/104443190/axis_fifo_v1_0.v | 104,443,190 | axis_fifo_v1_0.v | v | 268 | 90 | [] | [] | [] | null | line:72: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104443190/axis_fifo_v1_0.v:117: Operator ASSIGNW expects 34 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n : ... In instance axis_fifo_v1_0\nassign mem_write_data = {s00_axis_tlast, s00_axis_tdata};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104443190/axis_fifo_v1_0.v:118: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'m00_data_reg\' generates 34 bits.\n : ... In instance axis_fifo_v1_0\nassign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,112 | module | module axis_fifo_v1_0 #
(
parameter ADDR_WIDTH = 12,
parameter C_AXIS_TDATA_WIDTH = 32
)
(
input wire s00_axis_aclk,
input wire s00_axis_aresetn,
input wire [C_AXIS_TDATA_WIDTH-1:0] s00_axis_tdata,
input wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb,
input wire s00_axis_tvalid,
output wire s00_axis_tready,
input wire s00_axis_tlast,
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire [C_AXIS_TDATA_WIDTH-1:0] m00_axis_tdata,
output wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
output wire m00_axis_tvalid,
input wire m00_axis_tready,
output wire m00_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg s00_rst_sync1_reg = 1'b1;
reg s00_rst_sync2_reg = 1'b1;
reg s00_rst_sync3_reg = 1'b1;
reg m00_rst_sync1_reg = 1'b1;
reg m00_rst_sync2_reg = 1'b1;
reg m00_rst_sync3_reg = 1'b1;
reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [C_AXIS_TDATA_WIDTH+2-1:0] mem_write_data;
reg [C_AXIS_TDATA_WIDTH+2-1:0] m00_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
reg m00_axis_tvalid_reg = 1'b0, m00_axis_tvalid_next;
wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
reg write;
reg read;
reg store_output;
assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
assign m00_axis_tvalid = m00_axis_tvalid_reg;
assign mem_write_data = {s00_axis_tlast, s00_axis_tdata};
assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
always @(posedge s00_axis_aclk) begin
if (!s00_axis_aresetn) begin
s00_rst_sync1_reg <= 1'b1;
s00_rst_sync2_reg <= 1'b1;
s00_rst_sync3_reg <= 1'b1;
end else begin
s00_rst_sync1_reg <= 1'b0;
s00_rst_sync2_reg <= s00_rst_sync1_reg | m00_rst_sync1_reg;
s00_rst_sync3_reg <= s00_rst_sync2_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (!m00_axis_aresetn) begin
m00_rst_sync1_reg <= 1'b1;
m00_rst_sync2_reg <= 1'b1;
m00_rst_sync3_reg <= 1'b1;
end else begin
m00_rst_sync1_reg <= 1'b0;
m00_rst_sync2_reg <= s00_rst_sync1_reg | m00_rst_sync1_reg;
m00_rst_sync3_reg <= m00_rst_sync2_reg;
end
end
always @* begin
write = 1'b0;
wr_ptr_next = wr_ptr_reg;
wr_ptr_gray_next = wr_ptr_gray_reg;
if (s00_axis_tvalid) begin
if (~full) begin
write = 1'b1;
wr_ptr_next = wr_ptr_reg + 1;
wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
always @(posedge s00_axis_aclk) begin
if (s00_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_gray_reg <= wr_ptr_gray_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
always @(posedge s00_axis_aclk) begin
if (s00_rst_sync3_reg) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
end
end
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
rd_ptr_gray_next = rd_ptr_gray_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
if (~empty) begin
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
end else begin
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
rd_ptr_gray_reg <= rd_ptr_gray_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
always @* begin
store_output = 1'b0;
m00_axis_tvalid_next = m00_axis_tvalid_reg;
if (m00_axis_tready | ~m00_axis_tvalid) begin
store_output = 1'b1;
m00_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
m00_axis_tvalid_reg <= 1'b0;
end else begin
m00_axis_tvalid_reg <= m00_axis_tvalid_next;
end
if (store_output) begin
m00_data_reg <= mem_read_data_reg;
end
end
endmodule | module axis_fifo_v1_0 #
(
parameter ADDR_WIDTH = 12,
parameter C_AXIS_TDATA_WIDTH = 32
)
(
input wire s00_axis_aclk,
input wire s00_axis_aresetn,
input wire [C_AXIS_TDATA_WIDTH-1:0] s00_axis_tdata,
input wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb,
input wire s00_axis_tvalid,
output wire s00_axis_tready,
input wire s00_axis_tlast,
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire [C_AXIS_TDATA_WIDTH-1:0] m00_axis_tdata,
output wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
output wire m00_axis_tvalid,
input wire m00_axis_tready,
output wire m00_axis_tlast
); |
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg s00_rst_sync1_reg = 1'b1;
reg s00_rst_sync2_reg = 1'b1;
reg s00_rst_sync3_reg = 1'b1;
reg m00_rst_sync1_reg = 1'b1;
reg m00_rst_sync2_reg = 1'b1;
reg m00_rst_sync3_reg = 1'b1;
reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [C_AXIS_TDATA_WIDTH+2-1:0] mem_write_data;
reg [C_AXIS_TDATA_WIDTH+2-1:0] m00_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
reg m00_axis_tvalid_reg = 1'b0, m00_axis_tvalid_next;
wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
reg write;
reg read;
reg store_output;
assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
assign m00_axis_tvalid = m00_axis_tvalid_reg;
assign mem_write_data = {s00_axis_tlast, s00_axis_tdata};
assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
always @(posedge s00_axis_aclk) begin
if (!s00_axis_aresetn) begin
s00_rst_sync1_reg <= 1'b1;
s00_rst_sync2_reg <= 1'b1;
s00_rst_sync3_reg <= 1'b1;
end else begin
s00_rst_sync1_reg <= 1'b0;
s00_rst_sync2_reg <= s00_rst_sync1_reg | m00_rst_sync1_reg;
s00_rst_sync3_reg <= s00_rst_sync2_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (!m00_axis_aresetn) begin
m00_rst_sync1_reg <= 1'b1;
m00_rst_sync2_reg <= 1'b1;
m00_rst_sync3_reg <= 1'b1;
end else begin
m00_rst_sync1_reg <= 1'b0;
m00_rst_sync2_reg <= s00_rst_sync1_reg | m00_rst_sync1_reg;
m00_rst_sync3_reg <= m00_rst_sync2_reg;
end
end
always @* begin
write = 1'b0;
wr_ptr_next = wr_ptr_reg;
wr_ptr_gray_next = wr_ptr_gray_reg;
if (s00_axis_tvalid) begin
if (~full) begin
write = 1'b1;
wr_ptr_next = wr_ptr_reg + 1;
wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
always @(posedge s00_axis_aclk) begin
if (s00_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_gray_reg <= wr_ptr_gray_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
always @(posedge s00_axis_aclk) begin
if (s00_rst_sync3_reg) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
end
end
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
rd_ptr_gray_next = rd_ptr_gray_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
if (~empty) begin
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
end else begin
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
rd_ptr_gray_reg <= rd_ptr_gray_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
always @* begin
store_output = 1'b0;
m00_axis_tvalid_next = m00_axis_tvalid_reg;
if (m00_axis_tready | ~m00_axis_tvalid) begin
store_output = 1'b1;
m00_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge m00_axis_aclk) begin
if (m00_rst_sync3_reg) begin
m00_axis_tvalid_reg <= 1'b0;
end else begin
m00_axis_tvalid_reg <= m00_axis_tvalid_next;
end
if (store_output) begin
m00_data_reg <= mem_read_data_reg;
end
end
endmodule | 2 |
3,390 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | module | module chen_div_tb;
reg clk=0,rst=0;
initial #30 rst=1;
always#10 clk=~clk;
reg divide_en=0;
reg [31:0] dividend=0,divisor=0;
integer i=0;
always@(posedge clk)
begin
i <= i + 1;
if(i==7)
begin
divide_en=1; dividend={16'd10,16'd0};divisor={16'd0,16'd3};
end
else if(i==8)
begin
divide_en=1; dividend=10;divisor=2;
end
else
begin
divide_en=0; dividend=0;divisor=0;
end
end
wire divide_error;
wire divide_done;
wire [31:0] quotient;
wire [31:0] remainde;
chen_unsigned_div chen_unsigned_div(
.clk(clk),
.rst_n(rst),
.divide_en(divide_en),
.dividend(dividend),
.divisor(divisor),
.divide_error(divide_error),
.divide_done(divide_done),
.quotient(quotient),
.remainde(remainde)
);
reg divide_en_signed=0;
reg [15:0] dividend_signed=0,divisor_signed=0;
integer j=0;
always@(posedge clk)
begin
j <= j + 1;
if(j==7)
begin
divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd3;
end
else if(j==8)
begin
divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd0;
end
else
begin
divide_en_signed=0; dividend_signed=0;divisor_signed=0;
end
end
wire divide_error_signed;
wire divide_done_signed;
wire [31:0] quotient_signed;
chen_signed_div chen_signed_div(
.clk(clk),
.rst_n(rst),
.divide_en(divide_en_signed),
.dividend(dividend_signed),
.divisor(divisor_signed),
.divide_error(divide_error_signed),
.divide_done(divide_done_signed),
.quotient(quotient_signed)
);
endmodule | module chen_div_tb; |
reg clk=0,rst=0;
initial #30 rst=1;
always#10 clk=~clk;
reg divide_en=0;
reg [31:0] dividend=0,divisor=0;
integer i=0;
always@(posedge clk)
begin
i <= i + 1;
if(i==7)
begin
divide_en=1; dividend={16'd10,16'd0};divisor={16'd0,16'd3};
end
else if(i==8)
begin
divide_en=1; dividend=10;divisor=2;
end
else
begin
divide_en=0; dividend=0;divisor=0;
end
end
wire divide_error;
wire divide_done;
wire [31:0] quotient;
wire [31:0] remainde;
chen_unsigned_div chen_unsigned_div(
.clk(clk),
.rst_n(rst),
.divide_en(divide_en),
.dividend(dividend),
.divisor(divisor),
.divide_error(divide_error),
.divide_done(divide_done),
.quotient(quotient),
.remainde(remainde)
);
reg divide_en_signed=0;
reg [15:0] dividend_signed=0,divisor_signed=0;
integer j=0;
always@(posedge clk)
begin
j <= j + 1;
if(j==7)
begin
divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd3;
end
else if(j==8)
begin
divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd0;
end
else
begin
divide_en_signed=0; dividend_signed=0;divisor_signed=0;
end
end
wire divide_error_signed;
wire divide_done_signed;
wire [31:0] quotient_signed;
chen_signed_div chen_signed_div(
.clk(clk),
.rst_n(rst),
.divide_en(divide_en_signed),
.dividend(dividend_signed),
.divisor(divisor_signed),
.divide_error(divide_error_signed),
.divide_done(divide_done_signed),
.quotient(quotient_signed)
);
endmodule | 2 |
3,391 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | module | module chen_signed_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient );
parameter width = 16;
input clk;
input rst_n;
input divide_en;
input[15:0] dividend;
input[15:0] divisor;
output reg divide_error;
output reg divide_done;
output reg [31:0] quotient;
reg divide_en_temp;
reg divide_sign_temp;
reg [31:0] divide_dividend_temp;
reg [31:0]divide_divisor_temp;
reg [33:0] divide_sign_temp_shift_reg;
wire divide_error_temp;
wire divide_done_temp;
wire [31:0] quotient_temp;
always@(posedge clk)
if(~rst_n)
begin
divide_en_temp <= 0;
divide_sign_temp <= 0;
divide_dividend_temp <= 0;
divide_divisor_temp <= 0;
divide_sign_temp_shift_reg <= 0;
divide_done <= 0;
divide_error <= 0;
quotient <= 0;
end
else
begin
divide_en_temp <= divide_en;
divide_sign_temp <= dividend[15]^divisor[15];
divide_dividend_temp <= { abs(dividend),16'sb0 };
divide_divisor_temp <= { 16'sb0,abs(divisor) };
divide_sign_temp_shift_reg <= {divide_sign_temp_shift_reg[32:0],divide_sign_temp};
divide_done <= divide_done_temp;
divide_error <= divide_error_temp;
quotient <= divide_done_temp?unsignedtosigned(quotient_temp,divide_sign_temp_shift_reg[33]):0;
end
chen_unsigned_div#(
.width (32)
) inst_chen_unsigned_div(
.clk(clk),
.rst_n(rst_n),
.divide_en(divide_en_temp),
.dividend(divide_dividend_temp),
.divisor(divide_divisor_temp),
.divide_error(divide_error_temp),
.divide_done(divide_done_temp),
.quotient(quotient_temp),
.remainde()
);
function [15:0] abs;
input [15:0] x;
begin
abs = x[15]?~x+1'b1:x;
end
endfunction
function [31:0] unsignedtosigned;
input [31:0] x;
input sign;
begin
unsignedtosigned = sign?~x+1'b1:x;
end
endfunction
endmodule | module chen_signed_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient ); |
parameter width = 16;
input clk;
input rst_n;
input divide_en;
input[15:0] dividend;
input[15:0] divisor;
output reg divide_error;
output reg divide_done;
output reg [31:0] quotient;
reg divide_en_temp;
reg divide_sign_temp;
reg [31:0] divide_dividend_temp;
reg [31:0]divide_divisor_temp;
reg [33:0] divide_sign_temp_shift_reg;
wire divide_error_temp;
wire divide_done_temp;
wire [31:0] quotient_temp;
always@(posedge clk)
if(~rst_n)
begin
divide_en_temp <= 0;
divide_sign_temp <= 0;
divide_dividend_temp <= 0;
divide_divisor_temp <= 0;
divide_sign_temp_shift_reg <= 0;
divide_done <= 0;
divide_error <= 0;
quotient <= 0;
end
else
begin
divide_en_temp <= divide_en;
divide_sign_temp <= dividend[15]^divisor[15];
divide_dividend_temp <= { abs(dividend),16'sb0 };
divide_divisor_temp <= { 16'sb0,abs(divisor) };
divide_sign_temp_shift_reg <= {divide_sign_temp_shift_reg[32:0],divide_sign_temp};
divide_done <= divide_done_temp;
divide_error <= divide_error_temp;
quotient <= divide_done_temp?unsignedtosigned(quotient_temp,divide_sign_temp_shift_reg[33]):0;
end
chen_unsigned_div#(
.width (32)
) inst_chen_unsigned_div(
.clk(clk),
.rst_n(rst_n),
.divide_en(divide_en_temp),
.dividend(divide_dividend_temp),
.divisor(divide_divisor_temp),
.divide_error(divide_error_temp),
.divide_done(divide_done_temp),
.quotient(quotient_temp),
.remainde()
);
function [15:0] abs;
input [15:0] x;
begin
abs = x[15]?~x+1'b1:x;
end
endfunction
function [31:0] unsignedtosigned;
input [31:0] x;
input sign;
begin
unsignedtosigned = sign?~x+1'b1:x;
end
endfunction
endmodule | 2 |
3,392 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | module | module chen_unsigned_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient,remainde );
parameter width = 32;
input clk;
input rst_n;
input divide_en;
input[width-1:0] dividend;
input[width-1:0] divisor;
output divide_error;
output divide_done;
output [width-1:0] quotient;
output [width-1:0] remainde;
reg temp_en;
reg[width*2-1:0] temp_a;
reg[width*2-1:0] temp_b;
reg divide_error_temp;
always@(posedge clk)
if(~rst_n)
begin
divide_error_temp <= 0;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
else if(divide_en)
begin
if( divisor==0 )
begin
divide_error_temp <= 1;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
else
begin
divide_error_temp <= 0;
temp_en <= 1;
temp_a <= {dividend>>width,dividend};
temp_b <= {divisor,divisor>>width};
end
end
else
begin
divide_error_temp <= 0;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
wire [width*2-1:0] a_reg[0:width];
wire [width*2-1:0] b_reg[0:width];
assign a_reg[0] = temp_a;
assign b_reg[0] = temp_b;
generate
genvar i;
for (i = 0; i < width; i = i + 1)
begin:shift_compute
shift_compute#(
.width(width*2)
) inst_shift_compute (
.clk(clk),
.a_i(a_reg[i]),
.b_i(b_reg[i]),
.a_o(a_reg[i+1]),
.b_o(b_reg[i+1])
);
end
endgenerate
reg [width:0] divide_en_shift_reg;
reg [width-1:0] divide_error_temp_shift_reg;
reg divide_error;
reg divide_done;
reg [width-1:0] quotient;
reg [width-1:0] remainde;
always@(posedge clk)
if(~rst_n)
begin
divide_en_shift_reg <= 0;
divide_error_temp_shift_reg <= 0;
divide_error <= 0;
divide_done <= 0;
quotient <= 0;
remainde <= 0;
end
else
begin
divide_en_shift_reg <= {divide_en_shift_reg[width-1:0],divide_en};
divide_error_temp_shift_reg <= {divide_error_temp_shift_reg[width-2:0],divide_error_temp};
divide_error <= divide_error_temp_shift_reg[width-1];
divide_done <= divide_en_shift_reg[width];
quotient <= divide_en_shift_reg[width]?a_reg[width][width-1:0]:0;
remainde <= divide_en_shift_reg[width]?a_reg[width][width*2-1:width]:0;
end
endmodule | module chen_unsigned_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient,remainde ); |
parameter width = 32;
input clk;
input rst_n;
input divide_en;
input[width-1:0] dividend;
input[width-1:0] divisor;
output divide_error;
output divide_done;
output [width-1:0] quotient;
output [width-1:0] remainde;
reg temp_en;
reg[width*2-1:0] temp_a;
reg[width*2-1:0] temp_b;
reg divide_error_temp;
always@(posedge clk)
if(~rst_n)
begin
divide_error_temp <= 0;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
else if(divide_en)
begin
if( divisor==0 )
begin
divide_error_temp <= 1;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
else
begin
divide_error_temp <= 0;
temp_en <= 1;
temp_a <= {dividend>>width,dividend};
temp_b <= {divisor,divisor>>width};
end
end
else
begin
divide_error_temp <= 0;
temp_en <= 0;
temp_a <= 0;
temp_b <= 0;
end
wire [width*2-1:0] a_reg[0:width];
wire [width*2-1:0] b_reg[0:width];
assign a_reg[0] = temp_a;
assign b_reg[0] = temp_b;
generate
genvar i;
for (i = 0; i < width; i = i + 1)
begin:shift_compute
shift_compute#(
.width(width*2)
) inst_shift_compute (
.clk(clk),
.a_i(a_reg[i]),
.b_i(b_reg[i]),
.a_o(a_reg[i+1]),
.b_o(b_reg[i+1])
);
end
endgenerate
reg [width:0] divide_en_shift_reg;
reg [width-1:0] divide_error_temp_shift_reg;
reg divide_error;
reg divide_done;
reg [width-1:0] quotient;
reg [width-1:0] remainde;
always@(posedge clk)
if(~rst_n)
begin
divide_en_shift_reg <= 0;
divide_error_temp_shift_reg <= 0;
divide_error <= 0;
divide_done <= 0;
quotient <= 0;
remainde <= 0;
end
else
begin
divide_en_shift_reg <= {divide_en_shift_reg[width-1:0],divide_en};
divide_error_temp_shift_reg <= {divide_error_temp_shift_reg[width-2:0],divide_error_temp};
divide_error <= divide_error_temp_shift_reg[width-1];
divide_done <= divide_en_shift_reg[width];
quotient <= divide_en_shift_reg[width]?a_reg[width][width-1:0]:0;
remainde <= divide_en_shift_reg[width]?a_reg[width][width*2-1:width]:0;
end
endmodule | 2 |
3,393 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | module | module shift_compute#( parameter width=64 )( clk,a_i,b_i,a_o,b_o );
input clk;
input [width-1:0] a_i,b_i;
output reg [width-1:0] a_o,b_o;
wire [width-1:0] temp_a,temp_b;
assign temp_a = {a_i[width-2:0],1'b0};
assign temp_b = b_i;
always@(posedge clk)
begin
if(temp_a[width-1:width/2] >= temp_b[width-1:width/2])
a_o <= temp_a - temp_b + 1'b1;
else
a_o <= temp_a;
b_o <= temp_b;
end
endmodule | module shift_compute#( parameter width=64 )( clk,a_i,b_i,a_o,b_o ); |
input clk;
input [width-1:0] a_i,b_i;
output reg [width-1:0] a_o,b_o;
wire [width-1:0] temp_a,temp_b;
assign temp_a = {a_i[width-2:0],1'b0};
assign temp_b = b_i;
always@(posedge clk)
begin
if(temp_a[width-1:width/2] >= temp_b[width-1:width/2])
a_o <= temp_a - temp_b + 1'b1;
else
a_o <= temp_a;
b_o <= temp_b;
end
endmodule | 2 |
3,394 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | function | function [15:0] abs;
input [15:0] x;
begin
abs = x[15]?~x+1'b1:x;
end
endfunction | function [15:0] abs; |
input [15:0] x;
begin
abs = x[15]?~x+1'b1:x;
end
endfunction | 2 |
3,395 | data/full_repos/permissive/104443190/chen_div.v | 104,443,190 | chen_div.v | v | 345 | 138 | [] | [] | [] | null | line:13: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,113 | function | function [31:0] unsignedtosigned;
input [31:0] x;
input sign;
begin
unsignedtosigned = sign?~x+1'b1:x;
end
endfunction | function [31:0] unsignedtosigned; |
input [31:0] x;
input sign;
begin
unsignedtosigned = sign?~x+1'b1:x;
end
endfunction | 2 |
3,400 | data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v | 104,443,190 | tb_Booth_Multiplier.v | v | 101 | 90 | [] | [] | [] | null | line:84: before: "#" | null | 1: b'%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:55: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dut.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:56: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:72: Unsupported: Ignoring delay on this delayed statement.\n #101 Rst = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:84: syntax error, unexpected \'@\'\n @(posedge Clk) #1 Ld = 1; M = 4\'b0110; R = 4\'b0101;\n ^\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:85: syntax error, unexpected \'@\'\n @(posedge Clk) #1 Ld = 0; M=0; R=0;\n ^\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:86: syntax error, unexpected \'@\'\n @(posedge Valid);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:96: Unsupported: Ignoring delay on this delayed statement.\nalways #5 Clk = ~Clk;\n ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,118 | module | module tb_Booth_Multiplier;
parameter N = 2;
reg Rst;
reg Clk;
reg Ld;
reg [(2**N - 1):0] M;
reg [(2**N - 1):0] R;
wire Valid;
wire [(2**(N+1) - 1):0] P;
reg [2**(N+1):0] i;
Booth_Multiplier #(
.pN(N)
)chen_dut(
.Rst_n(~Rst),
.Clk(Clk),
.En(Ld),
.M(M),
.Q(R),
.Valid(Valid),
.Product(P)
);
`ifdef tb_iverilog
initial
begin
$dumpfile("dut.vcd");
$dumpvars;
end
`endif
initial begin
Rst = 1;
Clk = 1;
Ld = 0;
M = 0;
R = 0;
i = 0;
#101 Rst = 0;
@(posedge Clk) #1 Ld = 1; M = 4'b0110; R = 4'b0101;
@(posedge Clk) #1 Ld = 0; M=0; R=0;
@(posedge Valid);
@(posedge Clk);
@(posedge Clk);
$finish;
end
always #5 Clk = ~Clk;
endmodule | module tb_Booth_Multiplier; |
parameter N = 2;
reg Rst;
reg Clk;
reg Ld;
reg [(2**N - 1):0] M;
reg [(2**N - 1):0] R;
wire Valid;
wire [(2**(N+1) - 1):0] P;
reg [2**(N+1):0] i;
Booth_Multiplier #(
.pN(N)
)chen_dut(
.Rst_n(~Rst),
.Clk(Clk),
.En(Ld),
.M(M),
.Q(R),
.Valid(Valid),
.Product(P)
);
`ifdef tb_iverilog
initial
begin
$dumpfile("dut.vcd");
$dumpvars;
end
`endif
initial begin
Rst = 1;
Clk = 1;
Ld = 0;
M = 0;
R = 0;
i = 0;
#101 Rst = 0;
@(posedge Clk) #1 Ld = 1; M = 4'b0110; R = 4'b0101;
@(posedge Clk) #1 Ld = 0; M=0; R=0;
@(posedge Valid);
@(posedge Clk);
@(posedge Clk);
$finish;
end
always #5 Clk = ~Clk;
endmodule | 2 |
3,401 | data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v | 104,443,190 | chen_cordic_radian.v | v | 281 | 143 | [] | [] | [] | null | line:129: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:186: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h6488\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0000: angle = 18\'d25736 ; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:187: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h3b58\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0001: angle = 18\'d15192; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:188: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1f5b\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0010: angle = 18\'d8027; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:189: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'hfeb\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0011: angle = 18\'d4075; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:190: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h7fd\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0100: angle = 18\'d2045; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:191: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h400\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0101: angle = 18\'d1024; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:192: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h200\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0110: angle = 18\'d512; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:193: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h100\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0111: angle = 18\'d256; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:194: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h80\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1000: angle = 18\'d128; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:195: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h40\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1001: angle = 18\'d64; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:196: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1010: angle = 18\'d32; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:197: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h10\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1011: angle = 18\'d16; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:198: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h8\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1100: angle = 18\'d8; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:199: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h4\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1101: angle = 18\'d4; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:200: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h2\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1110: angle = 18\'d2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:201: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1111: angle = 18\'d1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h6488\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[0].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h3b58\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[1].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1f5b\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[2].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'hfeb\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[3].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h7fd\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[4].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h400\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[5].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h200\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[6].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h100\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[7].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h80\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[8].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h40\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[9].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h20\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[10].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h10\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[11].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h8\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[12].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h4\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[13].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h2\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[14].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[15].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Error: Exiting due to 32 warning(s)\n' | 1,119 | module | module chen_cordic #(
parameter ROTATE_TYPE = "ROTATE",
parameter DATABITS = 17,
parameter ITERATIONS = 16
)(
input clk,
input rst_n,
input Validin,
input signed [DATABITS-1:0] Xin,
input signed [DATABITS-1:0] Yin,
input signed [17:0] Ain,
output reg Validout,
output reg signed [DATABITS-1:0] Xout,
output reg signed [DATABITS-1:0] Yout,
output reg signed [17:0] Aout
);
localparam pi = 18'sd102943;
localparam half_pi = 18'sd51471;
localparam K = 16'sb0100110110111010;
reg signed [DATABITS-1:0] xtemp,ytemp;
reg signed [17:0] atemp;
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
always@(posedge clk)
if(!rst_n)
{xtemp,ytemp,atemp} <= 0;
else if( Ain <= half_pi && Ain >= -half_pi)
begin
xtemp <= Xin;
ytemp <= Yin;
atemp <= Ain;
end
else if( Ain > half_pi )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= Ain - pi;
end
else if( Ain < -half_pi )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= Ain + pi;
end
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
always@(posedge clk)
if(!rst_n)
{xtemp,ytemp,atemp} <= 0;
else if(Xin>=0)
begin
xtemp <= Xin;
ytemp <= Yin;
atemp <= 0;
end
else if( Xin < 0 && Yin >= 0 )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= +pi;
end
else if( Xin < 0 && Yin < 0 )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= -pi;
end
end
endgenerate
wire [DATABITS-1:0] x[ITERATIONS:0];
wire [DATABITS-1:0] y[ITERATIONS:0];
wire [17:0] a[ITERATIONS:0];
assign { x[0],y[0],a[0] } = {xtemp,ytemp,atemp};
genvar i;
generate for(i=0;i<=ITERATIONS-1;i=i+1) begin
rotator inst_rotator (clk,rst_n,x[i],y[i],a[i],x[i+1],y[i+1],a[i+1]);
defparam inst_rotator.ROTATE_TYPE = ROTATE_TYPE;
defparam inst_rotator.ITERATE_INDEX = i;
defparam inst_rotator.DATABITS = DATABITS;
defparam inst_rotator.angle = angle(i);
end
endgenerate
reg [ITERATIONS:0] valid_temp;
always@(posedge clk)
if(~rst_n)
valid_temp <= 0;
else
valid_temp <= {valid_temp[ITERATIONS-1:0],Validin};
reg Validout_reg;
reg signed [DATABITS+16-1:0] Xout_reg,Yout_reg;
reg signed [17:0] Aout_reg;
always@(posedge clk)
if(!rst_n)
begin
{ Validout_reg,Xout_reg,Yout_reg,Aout_reg } <= 0;
{ Validout,Xout,Yout,Aout } <= 0;
end
else
begin
Validout_reg <= valid_temp[ITERATIONS];
Xout_reg <= K*$signed(x[ITERATIONS]);
Yout_reg <= K*$signed(y[ITERATIONS]);
Aout_reg <= a[ITERATIONS];
if(Validout_reg)
begin
Validout <= Validout_reg;
Xout <= Xout_reg[DATABITS+14:15];
Yout <= Yout_reg[DATABITS+14:15];
Aout <= Aout_reg;
end
else
{ Validout,Xout,Yout,Aout } <= 0;
end
function signed [18:0] angle;
input [3:0] i;
begin
case (i)
4'b0000: angle = 18'd25736 ;
4'b0001: angle = 18'd15192;
4'b0010: angle = 18'd8027;
4'b0011: angle = 18'd4075;
4'b0100: angle = 18'd2045;
4'b0101: angle = 18'd1024;
4'b0110: angle = 18'd512;
4'b0111: angle = 18'd256;
4'b1000: angle = 18'd128;
4'b1001: angle = 18'd64;
4'b1010: angle = 18'd32;
4'b1011: angle = 18'd16;
4'b1100: angle = 18'd8;
4'b1101: angle = 18'd4;
4'b1110: angle = 18'd2;
4'b1111: angle = 18'd1;
endcase
end
endfunction
endmodule | module chen_cordic #(
parameter ROTATE_TYPE = "ROTATE",
parameter DATABITS = 17,
parameter ITERATIONS = 16
)(
input clk,
input rst_n,
input Validin,
input signed [DATABITS-1:0] Xin,
input signed [DATABITS-1:0] Yin,
input signed [17:0] Ain,
output reg Validout,
output reg signed [DATABITS-1:0] Xout,
output reg signed [DATABITS-1:0] Yout,
output reg signed [17:0] Aout
); |
localparam pi = 18'sd102943;
localparam half_pi = 18'sd51471;
localparam K = 16'sb0100110110111010;
reg signed [DATABITS-1:0] xtemp,ytemp;
reg signed [17:0] atemp;
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
always@(posedge clk)
if(!rst_n)
{xtemp,ytemp,atemp} <= 0;
else if( Ain <= half_pi && Ain >= -half_pi)
begin
xtemp <= Xin;
ytemp <= Yin;
atemp <= Ain;
end
else if( Ain > half_pi )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= Ain - pi;
end
else if( Ain < -half_pi )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= Ain + pi;
end
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
always@(posedge clk)
if(!rst_n)
{xtemp,ytemp,atemp} <= 0;
else if(Xin>=0)
begin
xtemp <= Xin;
ytemp <= Yin;
atemp <= 0;
end
else if( Xin < 0 && Yin >= 0 )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= +pi;
end
else if( Xin < 0 && Yin < 0 )
begin
xtemp <= -Xin;
ytemp <= -Yin;
atemp <= -pi;
end
end
endgenerate
wire [DATABITS-1:0] x[ITERATIONS:0];
wire [DATABITS-1:0] y[ITERATIONS:0];
wire [17:0] a[ITERATIONS:0];
assign { x[0],y[0],a[0] } = {xtemp,ytemp,atemp};
genvar i;
generate for(i=0;i<=ITERATIONS-1;i=i+1) begin
rotator inst_rotator (clk,rst_n,x[i],y[i],a[i],x[i+1],y[i+1],a[i+1]);
defparam inst_rotator.ROTATE_TYPE = ROTATE_TYPE;
defparam inst_rotator.ITERATE_INDEX = i;
defparam inst_rotator.DATABITS = DATABITS;
defparam inst_rotator.angle = angle(i);
end
endgenerate
reg [ITERATIONS:0] valid_temp;
always@(posedge clk)
if(~rst_n)
valid_temp <= 0;
else
valid_temp <= {valid_temp[ITERATIONS-1:0],Validin};
reg Validout_reg;
reg signed [DATABITS+16-1:0] Xout_reg,Yout_reg;
reg signed [17:0] Aout_reg;
always@(posedge clk)
if(!rst_n)
begin
{ Validout_reg,Xout_reg,Yout_reg,Aout_reg } <= 0;
{ Validout,Xout,Yout,Aout } <= 0;
end
else
begin
Validout_reg <= valid_temp[ITERATIONS];
Xout_reg <= K*$signed(x[ITERATIONS]);
Yout_reg <= K*$signed(y[ITERATIONS]);
Aout_reg <= a[ITERATIONS];
if(Validout_reg)
begin
Validout <= Validout_reg;
Xout <= Xout_reg[DATABITS+14:15];
Yout <= Yout_reg[DATABITS+14:15];
Aout <= Aout_reg;
end
else
{ Validout,Xout,Yout,Aout } <= 0;
end
function signed [18:0] angle;
input [3:0] i;
begin
case (i)
4'b0000: angle = 18'd25736 ;
4'b0001: angle = 18'd15192;
4'b0010: angle = 18'd8027;
4'b0011: angle = 18'd4075;
4'b0100: angle = 18'd2045;
4'b0101: angle = 18'd1024;
4'b0110: angle = 18'd512;
4'b0111: angle = 18'd256;
4'b1000: angle = 18'd128;
4'b1001: angle = 18'd64;
4'b1010: angle = 18'd32;
4'b1011: angle = 18'd16;
4'b1100: angle = 18'd8;
4'b1101: angle = 18'd4;
4'b1110: angle = 18'd2;
4'b1111: angle = 18'd1;
endcase
end
endfunction
endmodule | 2 |
3,402 | data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v | 104,443,190 | chen_cordic_radian.v | v | 281 | 143 | [] | [] | [] | null | line:129: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:186: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h6488\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0000: angle = 18\'d25736 ; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:187: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h3b58\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0001: angle = 18\'d15192; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:188: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1f5b\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0010: angle = 18\'d8027; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:189: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'hfeb\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0011: angle = 18\'d4075; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:190: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h7fd\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0100: angle = 18\'d2045; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:191: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h400\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0101: angle = 18\'d1024; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:192: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h200\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0110: angle = 18\'d512; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:193: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h100\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0111: angle = 18\'d256; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:194: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h80\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1000: angle = 18\'d128; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:195: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h40\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1001: angle = 18\'d64; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:196: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1010: angle = 18\'d32; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:197: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h10\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1011: angle = 18\'d16; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:198: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h8\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1100: angle = 18\'d8; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:199: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h4\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1101: angle = 18\'d4; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:200: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h2\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1110: angle = 18\'d2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:201: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1111: angle = 18\'d1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h6488\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[0].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h3b58\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[1].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1f5b\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[2].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'hfeb\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[3].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h7fd\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[4].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h400\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[5].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h200\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[6].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h100\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[7].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h80\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[8].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h40\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[9].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h20\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[10].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h10\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[11].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h8\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[12].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h4\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[13].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h2\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[14].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[15].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Error: Exiting due to 32 warning(s)\n' | 1,119 | module | module rotator(clk,rst_n,xin,yin,ain,xout,yout,aout);
parameter ROTATE_TYPE = "ROTATE";
parameter ITERATE_INDEX = 0;
parameter DATABITS = 17;
parameter signed [17:0] angle=0;
input clk;
input rst_n;
input signed [DATABITS-1:0] xin,yin;
input signed [17:0] ain;
output reg signed [DATABITS-1:0] xout,yout;
output reg signed [17:0] aout;
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
always@(posedge clk)
if(!rst_n)
{xout,yout,aout} <= 0;
else if(ain < 0)
begin
xout <= xin + (yin>>>ITERATE_INDEX);
yout <= yin - (xin>>>ITERATE_INDEX);
aout <= ain + angle;
end
else
begin
xout <= xin - (yin>>>ITERATE_INDEX);
yout <= yin + (xin>>>ITERATE_INDEX);
aout <= ain - angle;
end
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
always@(posedge clk)
if(!rst_n)
{xout,yout,aout} <= 0;
else if(yin > 0)
begin
xout <= xin + (yin>>>ITERATE_INDEX);
yout <= yin - (xin>>>ITERATE_INDEX);
aout <= ain + angle;
end
else
begin
xout <= xin - (yin>>>ITERATE_INDEX);
yout <= yin + (xin>>>ITERATE_INDEX);
aout <= ain - angle;
end
end
endgenerate
endmodule | module rotator(clk,rst_n,xin,yin,ain,xout,yout,aout); |
parameter ROTATE_TYPE = "ROTATE";
parameter ITERATE_INDEX = 0;
parameter DATABITS = 17;
parameter signed [17:0] angle=0;
input clk;
input rst_n;
input signed [DATABITS-1:0] xin,yin;
input signed [17:0] ain;
output reg signed [DATABITS-1:0] xout,yout;
output reg signed [17:0] aout;
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
always@(posedge clk)
if(!rst_n)
{xout,yout,aout} <= 0;
else if(ain < 0)
begin
xout <= xin + (yin>>>ITERATE_INDEX);
yout <= yin - (xin>>>ITERATE_INDEX);
aout <= ain + angle;
end
else
begin
xout <= xin - (yin>>>ITERATE_INDEX);
yout <= yin + (xin>>>ITERATE_INDEX);
aout <= ain - angle;
end
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
always@(posedge clk)
if(!rst_n)
{xout,yout,aout} <= 0;
else if(yin > 0)
begin
xout <= xin + (yin>>>ITERATE_INDEX);
yout <= yin - (xin>>>ITERATE_INDEX);
aout <= ain + angle;
end
else
begin
xout <= xin - (yin>>>ITERATE_INDEX);
yout <= yin + (xin>>>ITERATE_INDEX);
aout <= ain - angle;
end
end
endgenerate
endmodule | 2 |
3,403 | data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v | 104,443,190 | chen_cordic_radian.v | v | 281 | 143 | [] | [] | [] | null | line:129: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:186: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h6488\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0000: angle = 18\'d25736 ; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:187: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h3b58\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0001: angle = 18\'d15192; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:188: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1f5b\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0010: angle = 18\'d8027; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:189: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'hfeb\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0011: angle = 18\'d4075; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:190: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h7fd\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0100: angle = 18\'d2045; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:191: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h400\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0101: angle = 18\'d1024; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:192: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h200\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0110: angle = 18\'d512; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:193: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h100\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b0111: angle = 18\'d256; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:194: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h80\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1000: angle = 18\'d128; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:195: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h40\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1001: angle = 18\'d64; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:196: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1010: angle = 18\'d32; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:197: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h10\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1011: angle = 18\'d16; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:198: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h8\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1100: angle = 18\'d8; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:199: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h4\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1101: angle = 18\'d4; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:200: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h2\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1110: angle = 18\'d2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:201: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1\' generates 18 bits.\n : ... In instance chen_cordic\n 4\'b1111: angle = 18\'d1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h6488\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[0].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h3b58\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[1].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1f5b\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[2].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'hfeb\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[3].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h7fd\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[4].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h400\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[5].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h200\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[6].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h100\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[7].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h80\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[8].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h40\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[9].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h20\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[10].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h10\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[11].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h8\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[12].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h4\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[13].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h2\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[14].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1\' generates 19 bits.\n : ... In instance chen_cordic.genblk2[15].inst_rotator\n parameter signed [17:0] angle=0;\n ^~~~~\n%Error: Exiting due to 32 warning(s)\n' | 1,119 | function | function signed [18:0] angle;
input [3:0] i;
begin
case (i)
4'b0000: angle = 18'd25736 ;
4'b0001: angle = 18'd15192;
4'b0010: angle = 18'd8027;
4'b0011: angle = 18'd4075;
4'b0100: angle = 18'd2045;
4'b0101: angle = 18'd1024;
4'b0110: angle = 18'd512;
4'b0111: angle = 18'd256;
4'b1000: angle = 18'd128;
4'b1001: angle = 18'd64;
4'b1010: angle = 18'd32;
4'b1011: angle = 18'd16;
4'b1100: angle = 18'd8;
4'b1101: angle = 18'd4;
4'b1110: angle = 18'd2;
4'b1111: angle = 18'd1;
endcase
end
endfunction | function signed [18:0] angle; |
input [3:0] i;
begin
case (i)
4'b0000: angle = 18'd25736 ;
4'b0001: angle = 18'd15192;
4'b0010: angle = 18'd8027;
4'b0011: angle = 18'd4075;
4'b0100: angle = 18'd2045;
4'b0101: angle = 18'd1024;
4'b0110: angle = 18'd512;
4'b0111: angle = 18'd256;
4'b1000: angle = 18'd128;
4'b1001: angle = 18'd64;
4'b1010: angle = 18'd32;
4'b1011: angle = 18'd16;
4'b1100: angle = 18'd8;
4'b1101: angle = 18'd4;
4'b1110: angle = 18'd2;
4'b1111: angle = 18'd1;
endcase
end
endfunction | 2 |
3,410 | data/full_repos/permissive/104443190/complex_mult/complex_mult_dsp_impl.v | 104,443,190 | complex_mult_dsp_impl.v | v | 118 | 154 | [] | [] | [] | [(22, 117)] | null | data/verilator_xmls/ea7b64bc-3ed7-4cca-bd96-15b10910ba4d.xml | null | 1,122 | module | module complex_mult_dsp_impl
#(
parameter WIDTH=16
)(
clk,
ab_valid,
ar,ai,
br,bi,
p_valid,
pr,pi
);
input clk;
input ab_valid;
input signed [WIDTH-1:0] ar, ai;
input signed [WIDTH-1:0] br, bi;
output p_valid;
output signed [WIDTH+WIDTH:0] pr, pi;
reg signed [WIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd;
reg signed [WIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
reg signed [WIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
reg signed [WIDTH:0] addcommon;
reg signed [WIDTH:0] addr, addi;
reg signed [WIDTH+WIDTH:0] mult0, multr, multi, pr_int, pi_int;
reg signed [WIDTH+WIDTH:0] common, commonr1, commonr2;
reg [5:0] data_valid_reg;
always@(posedge clk)
begin
data_valid_reg[0] <= ab_valid;
data_valid_reg[5:1] <= data_valid_reg[4:0];
end
assign p_valid = data_valid_reg[5];
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
end
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1;
end
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule | module complex_mult_dsp_impl
#(
parameter WIDTH=16
)(
clk,
ab_valid,
ar,ai,
br,bi,
p_valid,
pr,pi
); |
input clk;
input ab_valid;
input signed [WIDTH-1:0] ar, ai;
input signed [WIDTH-1:0] br, bi;
output p_valid;
output signed [WIDTH+WIDTH:0] pr, pi;
reg signed [WIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd;
reg signed [WIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
reg signed [WIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
reg signed [WIDTH:0] addcommon;
reg signed [WIDTH:0] addr, addi;
reg signed [WIDTH+WIDTH:0] mult0, multr, multi, pr_int, pi_int;
reg signed [WIDTH+WIDTH:0] common, commonr1, commonr2;
reg [5:0] data_valid_reg;
always@(posedge clk)
begin
data_valid_reg[0] <= ab_valid;
data_valid_reg[5:1] <= data_valid_reg[4:0];
end
assign p_valid = data_valid_reg[5];
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
end
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1;
end
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule | 2 |
3,411 | data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v | 104,443,190 | tb_complex_mult.v | v | 108 | 80 | [] | [] | [] | null | line:58: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:51: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:57: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:65: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:69: syntax error, unexpected \'@\'\n @(negedge p_valid)\n ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:80: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:103: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,123 | module | module tb_complex_mult;
parameter N = 2;
reg clk;
reg ab_valid;
reg signed [N-1:0] ar,ai,br,bi;
wire p_valid;
wire signed [N+N:0] pr,pi;
reg [4*N-1:0] i,j;
reg signed [N-1:0] exp_ar,exp_ai,exp_br,exp_bi;
reg signed [N+N:0] real_part_dsp,imag_part_dsp;
complex_mult
#(
.WIDTH(N),
.INPUT_BUF("ON"),
.OUTPUT_BUF("ON")
)UUT(
.clk(clk),
.ab_valid(ab_valid),
.ar(ar), .ai(ai),
.br(br), .bi(bi),
.p_valid(p_valid),
.pr(pr), .pi(pi)
);
initial begin
clk = 0;
i = 0;
j = 0;
ab_valid = 0;
ar = 0; ai = 0; br = 0; bi = 0;
#200;
$display("Simulation begin!");
for(i = 0; i < 2**(4*N)-1; i = i + 1) begin
@(posedge clk)
#1;
ab_valid = 1;
ar = i[N-1:0];
ai = i[2*N-1:N];
br = i[3*N-1:2*N];
bi = i[4*N-1:3*N];
end
@(posedge clk)
ab_valid = 0;
ar = 0; ai = 0; br = 0; bi = 0;
@(negedge p_valid)
#100;
$display("All tests are passed!");
$finish;
end
initial begin
while(1)begin
@(posedge clk);
if(p_valid)begin
exp_ar = j[N-1:0];
exp_ai = j[2*N-1:N];
exp_br = j[3*N-1:2*N];
exp_bi = j[4*N-1:3*N];
real_part_dsp = exp_ar*exp_br - exp_ai*exp_bi;
imag_part_dsp = exp_ai*exp_br + exp_ar*exp_bi;
if( (pr != real_part_dsp)&&(pi != imag_part_dsp) ) begin
$display(" Fail - Module output does not equal expected value\n");
$display("%d,%d,%d,%d",pr,pi,real_part_dsp,imag_part_dsp);
$stop;
end
j = j + 1;
end
end
end
always #10 clk = ~clk;
endmodule | module tb_complex_mult; |
parameter N = 2;
reg clk;
reg ab_valid;
reg signed [N-1:0] ar,ai,br,bi;
wire p_valid;
wire signed [N+N:0] pr,pi;
reg [4*N-1:0] i,j;
reg signed [N-1:0] exp_ar,exp_ai,exp_br,exp_bi;
reg signed [N+N:0] real_part_dsp,imag_part_dsp;
complex_mult
#(
.WIDTH(N),
.INPUT_BUF("ON"),
.OUTPUT_BUF("ON")
)UUT(
.clk(clk),
.ab_valid(ab_valid),
.ar(ar), .ai(ai),
.br(br), .bi(bi),
.p_valid(p_valid),
.pr(pr), .pi(pi)
);
initial begin
clk = 0;
i = 0;
j = 0;
ab_valid = 0;
ar = 0; ai = 0; br = 0; bi = 0;
#200;
$display("Simulation begin!");
for(i = 0; i < 2**(4*N)-1; i = i + 1) begin
@(posedge clk)
#1;
ab_valid = 1;
ar = i[N-1:0];
ai = i[2*N-1:N];
br = i[3*N-1:2*N];
bi = i[4*N-1:3*N];
end
@(posedge clk)
ab_valid = 0;
ar = 0; ai = 0; br = 0; bi = 0;
@(negedge p_valid)
#100;
$display("All tests are passed!");
$finish;
end
initial begin
while(1)begin
@(posedge clk);
if(p_valid)begin
exp_ar = j[N-1:0];
exp_ai = j[2*N-1:N];
exp_br = j[3*N-1:2*N];
exp_bi = j[4*N-1:3*N];
real_part_dsp = exp_ar*exp_br - exp_ai*exp_bi;
imag_part_dsp = exp_ai*exp_br + exp_ar*exp_bi;
if( (pr != real_part_dsp)&&(pi != imag_part_dsp) ) begin
$display(" Fail - Module output does not equal expected value\n");
$display("%d,%d,%d,%d",pr,pi,real_part_dsp,imag_part_dsp);
$stop;
end
j = j + 1;
end
end
end
always #10 clk = ~clk;
endmodule | 2 |
3,412 | data/full_repos/permissive/104504209/PGM8755/src/buffer.v | 104,504,209 | buffer.v | v | 31 | 103 | [] | [] | [] | [(12, 30)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104504209/PGM8755/src/buffer.v:22: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3f0\' generates 10 bits.\n : ... In instance buffer\n if(rst) address_i <= 10\'hFF0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,124 | module | module buffer(input rst, clk, dir, input[7:0] data_in, input[10:0] address, output reg[7:0] data_out);
reg[7:0] blockram [2047:0];
reg[10:0] address_i;
always@(posedge clk) begin
if(rst) address_i <= 10'hFF0;
if(dir) data_out <= blockram[address];
else begin
blockram[address_i] <= data_in;
address_i <= address_i - 1'b1;
end
end
endmodule | module buffer(input rst, clk, dir, input[7:0] data_in, input[10:0] address, output reg[7:0] data_out); |
reg[7:0] blockram [2047:0];
reg[10:0] address_i;
always@(posedge clk) begin
if(rst) address_i <= 10'hFF0;
if(dir) data_out <= blockram[address];
else begin
blockram[address_i] <= data_in;
address_i <= address_i - 1'b1;
end
end
endmodule | 0 |
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