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3,532 | data/full_repos/permissive/105546923/infra/hdl/fifo.v | 105,546,923 | fifo.v | v | 285 | 71 | [] | [] | [] | null | line:176: before: "," | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/fifo.v:179: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Warning-SELRANGE: data/full_repos/permissive/105546923/infra/hdl/fifo.v:119: Selection index out of range: 1:1 outside 0:0\n : ... In instance fifo\n assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1\'b0;\n ^\n ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,320 | module | module fifo_(
input w_clk,
input r_clk,
input we,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
output [RAM_DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
function [ADDR_WIDTH :0] bin_to_gray;
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction
parameter MODE = 0;
parameter ADDR_WIDTH = 0;
parameter ASYNC = 0;
localparam RAM_ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
reg [ADDR_WIDTH - 1 : 0] raddr = 0, waddr = 0;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(_raddr),
.RCLK(r_clk),
.RCLKE(1'b1),
.RE(re),
.WADDR(_waddr),
.WCLK(w_clk),
.WCLKE(1'b1),
.WDATA(d),
.WE(we),
.MASK(mask)
);
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
always @ (posedge w_clk)
begin
if (we & ~full)
begin
waddr <= waddr + 1;
end
end
always @ (posedge r_clk)
begin
if (re & ~empty)
begin
raddr <= raddr + 1;
end
end
generate
if (ASYNC)
begin : async_ctrs
reg _full = 0, _empty = 1;
reg [ADDR_WIDTH : 0] wptr = 0, rptr = 0;
reg [ADDR_WIDTH : 0] rq1_wptr = 0, rq2_wptr = 0;
reg [ADDR_WIDTH : 0] wq1_rptr = 0, wq2_rptr = 0;
wire [ADDR_WIDTH : 0] _wptr, _rptr;
assign _wptr = bin_to_gray(waddr + (we & ~full));
assign _rptr = bin_to_gray(raddr + (re & ~empty));
assign full = _full;
assign empty = _empty;
always @ (posedge w_clk)
begin
wptr <= _wptr;
_full <= (_wptr ==
{~wq2_rptr[ADDR_WIDTH:ADDR_WIDTH-1], wq2_rptr[ADDR_WIDTH-2:0]});
end
always @ (posedge r_clk)
begin
_empty <= (_rptr == rq2_wptr);
rptr <= _rptr;
end
always @ (posedge w_clk)
begin
wq1_rptr <= rptr;
wq2_rptr <= wq1_rptr;
end
always @ (posedge r_clk)
begin
rq1_wptr <= wptr;
rq2_wptr <= rq1_wptr;
end
end
else
begin : sync_ctrs
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
assign full = &ctr;
assign empty = ~&ctr;
always @ (posedge w_clk)
begin
if (we & ~re & ~full)
begin
ctr <= ctr + 1;
end
else if(re & ~we & ~empty)
begin
ctr <= ctr - 1;
end
end
end
endgenerate
endmodule | module fifo_(
input w_clk,
input r_clk,
input we,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
output [RAM_DATA_WIDTH - 1 : 0] q,
output empty,
output full
); |
function [ADDR_WIDTH :0] bin_to_gray;
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction
parameter MODE = 0;
parameter ADDR_WIDTH = 0;
parameter ASYNC = 0;
localparam RAM_ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
reg [ADDR_WIDTH - 1 : 0] raddr = 0, waddr = 0;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(_raddr),
.RCLK(r_clk),
.RCLKE(1'b1),
.RE(re),
.WADDR(_waddr),
.WCLK(w_clk),
.WCLKE(1'b1),
.WDATA(d),
.WE(we),
.MASK(mask)
);
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
always @ (posedge w_clk)
begin
if (we & ~full)
begin
waddr <= waddr + 1;
end
end
always @ (posedge r_clk)
begin
if (re & ~empty)
begin
raddr <= raddr + 1;
end
end
generate
if (ASYNC)
begin : async_ctrs
reg _full = 0, _empty = 1;
reg [ADDR_WIDTH : 0] wptr = 0, rptr = 0;
reg [ADDR_WIDTH : 0] rq1_wptr = 0, rq2_wptr = 0;
reg [ADDR_WIDTH : 0] wq1_rptr = 0, wq2_rptr = 0;
wire [ADDR_WIDTH : 0] _wptr, _rptr;
assign _wptr = bin_to_gray(waddr + (we & ~full));
assign _rptr = bin_to_gray(raddr + (re & ~empty));
assign full = _full;
assign empty = _empty;
always @ (posedge w_clk)
begin
wptr <= _wptr;
_full <= (_wptr ==
{~wq2_rptr[ADDR_WIDTH:ADDR_WIDTH-1], wq2_rptr[ADDR_WIDTH-2:0]});
end
always @ (posedge r_clk)
begin
_empty <= (_rptr == rq2_wptr);
rptr <= _rptr;
end
always @ (posedge w_clk)
begin
wq1_rptr <= rptr;
wq2_rptr <= wq1_rptr;
end
always @ (posedge r_clk)
begin
rq1_wptr <= wptr;
rq2_wptr <= rq1_wptr;
end
end
else
begin : sync_ctrs
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
assign full = &ctr;
assign empty = ~&ctr;
always @ (posedge w_clk)
begin
if (we & ~re & ~full)
begin
ctr <= ctr + 1;
end
else if(re & ~we & ~empty)
begin
ctr <= ctr - 1;
end
end
end
endgenerate
endmodule | 0 |
3,533 | data/full_repos/permissive/105546923/infra/hdl/fifo.v | 105,546,923 | fifo.v | v | 285 | 71 | [] | [] | [] | null | line:176: before: "," | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/fifo.v:179: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Warning-SELRANGE: data/full_repos/permissive/105546923/infra/hdl/fifo.v:119: Selection index out of range: 1:1 outside 0:0\n : ... In instance fifo\n assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1\'b0;\n ^\n ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,320 | function | function [ADDR_WIDTH :0] bin_to_gray;
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction | function [ADDR_WIDTH :0] bin_to_gray; |
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction | 0 |
3,534 | data/full_repos/permissive/105546923/infra/hdl/infra.v | 105,546,923 | infra.v | v | 70 | 52 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n uart.vh\n uart.vh.v\n uart.vh.sv\n obj_dir/uart.vh\n obj_dir/uart.vh.v\n obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:10: Define or directive not defined: \'`UART_DATA_LENGTH\'\n output [`UART_DATA_LENGTH - 1 : 0] rx_o,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:12: Define or directive not defined: \'`UART_DATA_LENGTH\'\n input [`UART_DATA_LENGTH - 1 : 0] tx_i,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:27: Define or directive not defined: \'`UART_CLK_RX_FREQ\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:27: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:27: Define or directive not defined: \'`UART_RX_SAMPLE_RATE\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:36: Define or directive not defined: \'`UART_CLK_TX_FREQ\'\n .T(`UART_CLK_TX_FREQ / 2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/infra.v:36: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n .T(`UART_CLK_TX_FREQ / 2)\n ^\n%Error: Exiting due to 8 error(s)\n' | 1,321 | module | module infra(
input clk_i,
output clk_o_uart_rx,
output clk_o_uart_tx,
input rst_i,
output [7:0] led_o,
input rx_i,
output [`UART_DATA_LENGTH - 1 : 0] rx_o,
output rx_o_v,
input [`UART_DATA_LENGTH - 1 : 0] tx_i,
input tx_i_v,
output tx_o,
output tx_o_v
);
wire clk_led;
wire clk_uart_rx, clk_uart_tx;
assign clk_o_uart_rx = clk_uart_rx;
assign clk_o_uart_tx = clk_uart_tx;
clks #(
.PLL_EN(0),
.GBUFF_EN(1),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(1),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(6000000)
)led_clk(
.clk_i (clk_i),
.clk_o (clk_led)
);
uart_ctrl uart_ctrl(
.clk_rx_i (clk_uart_rx),
.clk_tx_i (clk_uart_tx),
.rx_i (rx_i),
.rx_o (rx_o),
.rx_o_v(rx_o_v),
.tx_i(tx_i),
.tx_i_v(tx_i_v),
.tx_o (tx_o),
.tx_o_v (tx_o_v)
);
assign led_o[0] = clk_led;
assign led_o[1] = rst_i;
assign led_o[7:2] = 0;
endmodule | module infra(
input clk_i,
output clk_o_uart_rx,
output clk_o_uart_tx,
input rst_i,
output [7:0] led_o,
input rx_i,
output [`UART_DATA_LENGTH - 1 : 0] rx_o,
output rx_o_v,
input [`UART_DATA_LENGTH - 1 : 0] tx_i,
input tx_i_v,
output tx_o,
output tx_o_v
); |
wire clk_led;
wire clk_uart_rx, clk_uart_tx;
assign clk_o_uart_rx = clk_uart_rx;
assign clk_o_uart_tx = clk_uart_tx;
clks #(
.PLL_EN(0),
.GBUFF_EN(1),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(1),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(6000000)
)led_clk(
.clk_i (clk_i),
.clk_o (clk_led)
);
uart_ctrl uart_ctrl(
.clk_rx_i (clk_uart_rx),
.clk_tx_i (clk_uart_tx),
.rx_i (rx_i),
.rx_o (rx_o),
.rx_o_v(rx_o_v),
.tx_i(tx_i),
.tx_i_v(tx_i_v),
.tx_o (tx_o),
.tx_o_v (tx_o_v)
);
assign led_o[0] = clk_led;
assign led_o[1] = rst_i;
assign led_o[7:2] = 0;
endmodule | 0 |
3,535 | data/full_repos/permissive/105546923/infra/hdl/multiplier.v | 105,546,923 | multiplier.v | v | 115 | 110 | [] | [] | [] | null | line:102: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance multiplier.mult\n P[0] <= { {(P_WIDTH){1\'b0}}, {a} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:28: Output port connection \'c\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'_c\' generates 4 bits.\n : ... In instance multiplier\n .c(_c)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,322 | module | module multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
wire [WIDTH : 0] _a;
wire [WIDTH : 0] _b;
wire [2 * WIDTH - 1 : 0] _c;
assign _a = { {a[WIDTH - 1]}, {a[WIDTH - 1 : 0]} };
assign _b = { {b[WIDTH - 1]}, {b[WIDTH - 1 : 0]} };
assign c = _c;
_multiplier#(
.WIDTH(WIDTH + 1)
) mult(
.clk(clk),
.a(_a),
.b(_b),
.c(_c)
);
endmodule | module multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
); |
parameter WIDTH = 2;
wire [WIDTH : 0] _a;
wire [WIDTH : 0] _b;
wire [2 * WIDTH - 1 : 0] _c;
assign _a = { {a[WIDTH - 1]}, {a[WIDTH - 1 : 0]} };
assign _b = { {b[WIDTH - 1]}, {b[WIDTH - 1 : 0]} };
assign c = _c;
_multiplier#(
.WIDTH(WIDTH + 1)
) mult(
.clk(clk),
.a(_a),
.b(_b),
.c(_c)
);
endmodule | 0 |
3,536 | data/full_repos/permissive/105546923/infra/hdl/multiplier.v | 105,546,923 | multiplier.v | v | 115 | 110 | [] | [] | [] | null | line:102: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance multiplier.mult\n P[0] <= { {(P_WIDTH){1\'b0}}, {a} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:28: Output port connection \'c\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'_c\' generates 4 bits.\n : ... In instance multiplier\n .c(_c)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,322 | module | module _multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
localparam M_WIDTH = WIDTH;
localparam P_WIDTH = 2 * M_WIDTH;
reg [P_WIDTH - 1 : 0] P [M_WIDTH : 0];
reg signed [M_WIDTH - 1 : 0] M [M_WIDTH : 0];
reg [M_WIDTH - 1 : 0] Q;
assign c = P[M_WIDTH];
always @(a, b)
begin
P[0] <= { {(P_WIDTH){1'b0}}, {a} };
M[0] <= b;
end
always @(posedge clk)
begin
if (P[0][0])
begin
P[1] <= sub_shift_right(P[0], M[0]);
end
else
begin
P[1] <= shift_right(P[0]);
end
Q[0] <= P[0][0];
M[1] <= M[0];
end
genvar i;
generate
for (i = 1; i < M_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
Q[i] <= P[i][0];
M[i + 1] <= M[i];
case( { P[i][0], Q[i - 1] } )
2'b01:
P[i + 1] <= add_shift_right(P[i], M[i]);
2'b10:
P[i + 1] <= sub_shift_right(P[i], M[i]);
default:
P[i + 1] <= shift_right(P[i]);
endcase
end
end
endgenerate
function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x);
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction
function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction
function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction
endmodule | module _multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
); |
parameter WIDTH = 2;
localparam M_WIDTH = WIDTH;
localparam P_WIDTH = 2 * M_WIDTH;
reg [P_WIDTH - 1 : 0] P [M_WIDTH : 0];
reg signed [M_WIDTH - 1 : 0] M [M_WIDTH : 0];
reg [M_WIDTH - 1 : 0] Q;
assign c = P[M_WIDTH];
always @(a, b)
begin
P[0] <= { {(P_WIDTH){1'b0}}, {a} };
M[0] <= b;
end
always @(posedge clk)
begin
if (P[0][0])
begin
P[1] <= sub_shift_right(P[0], M[0]);
end
else
begin
P[1] <= shift_right(P[0]);
end
Q[0] <= P[0][0];
M[1] <= M[0];
end
genvar i;
generate
for (i = 1; i < M_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
Q[i] <= P[i][0];
M[i + 1] <= M[i];
case( { P[i][0], Q[i - 1] } )
2'b01:
P[i + 1] <= add_shift_right(P[i], M[i]);
2'b10:
P[i + 1] <= sub_shift_right(P[i], M[i]);
default:
P[i + 1] <= shift_right(P[i]);
endcase
end
end
endgenerate
function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x);
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction
function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction
function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction
endmodule | 0 |
3,537 | data/full_repos/permissive/105546923/infra/hdl/multiplier.v | 105,546,923 | multiplier.v | v | 115 | 110 | [] | [] | [] | null | line:102: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance multiplier.mult\n P[0] <= { {(P_WIDTH){1\'b0}}, {a} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:28: Output port connection \'c\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'_c\' generates 4 bits.\n : ... In instance multiplier\n .c(_c)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,322 | function | function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x);
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction | function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x); |
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction | 0 |
3,538 | data/full_repos/permissive/105546923/infra/hdl/multiplier.v | 105,546,923 | multiplier.v | v | 115 | 110 | [] | [] | [] | null | line:102: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance multiplier.mult\n P[0] <= { {(P_WIDTH){1\'b0}}, {a} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:28: Output port connection \'c\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'_c\' generates 4 bits.\n : ... In instance multiplier\n .c(_c)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,322 | function | function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction | function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y); |
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction | 0 |
3,539 | data/full_repos/permissive/105546923/infra/hdl/multiplier.v | 105,546,923 | multiplier.v | v | 115 | 110 | [] | [] | [] | null | line:102: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n : ... In instance multiplier.mult\n P[0] <= { {(P_WIDTH){1\'b0}}, {a} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/infra/hdl/multiplier.v:28: Output port connection \'c\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'_c\' generates 4 bits.\n : ... In instance multiplier\n .c(_c)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,322 | function | function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction | function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y); |
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction | 0 |
3,540 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module ram(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end
endmodule | module ram(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end
endmodule | 0 |
3,541 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module dram_256x16(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [DATA_WIDTH - 1 :0] mask,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 16;
localparam ADDR_WIDTH = 8;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
assign _d = d;
assign q = _q;
dram_#(
.MODE(0)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | module dram_256x16(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [DATA_WIDTH - 1 :0] mask,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
localparam DATA_WIDTH = 16;
localparam ADDR_WIDTH = 8;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
assign _d = d;
assign q = _q;
dram_#(
.MODE(0)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | 0 |
3,542 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module dram_512x8(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 9;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = d[i];
assign q[i] = _q[i * 2];
end
endgenerate
dram_#(
.MODE(1)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | module dram_512x8(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 9;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = d[i];
assign q[i] = _q[i * 2];
end
endgenerate
dram_#(
.MODE(1)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | 0 |
3,543 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module dram_1024x4(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 4;
localparam ADDR_WIDTH = 10;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = d[i];
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
assign q[i] = _q[i * 4 + 1];
end
endgenerate
dram_#(
.MODE(2)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | module dram_1024x4(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
localparam DATA_WIDTH = 4;
localparam ADDR_WIDTH = 10;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = d[i];
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
assign q[i] = _q[i * 4 + 1];
end
endgenerate
dram_#(
.MODE(2)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | 0 |
3,544 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module dram_2048x2(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 2;
localparam ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = waddr;
assign _raddr = raddr;
genvar i;
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = d[i];
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
assign q[i] = _q[i * 8 + 3];
end
dram_#(
.MODE(3)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | module dram_2048x2(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
localparam DATA_WIDTH = 2;
localparam ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = waddr;
assign _raddr = raddr;
genvar i;
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = d[i];
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
assign q[i] = _q[i * 8 + 3];
end
dram_#(
.MODE(3)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule | 0 |
3,545 | data/full_repos/permissive/105546923/infra/hdl/ram.v | 105,546,923 | ram.v | v | 284 | 71 | [] | [] | [] | null | line:221: before: "for" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ram\'\nmodule ram(\n ^~~\n : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n ^~~~~~~~~~~\n : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n ^~~~~~~~~~\n : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n ^~~~~~~~~~~\n : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,323 | module | module dram_(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [RAM_ADDR_WIDTH - 1 : 0] waddr,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
input [RAM_ADDR_WIDTH - 1 : 0] raddr,
output [RAM_DATA_WIDTH - 1 : 0] q
);
parameter MODE = -1;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(raddr),
.RCLK(r_clk),
.RCLKE(r_clk_en),
.RE(re),
.WADDR(waddr),
.WCLK(w_clk),
.WCLKE(w_clk_en),
.WDATA(d),
.WE(we),
.MASK(mask)
);
endmodule | module dram_(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [RAM_ADDR_WIDTH - 1 : 0] waddr,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
input [RAM_ADDR_WIDTH - 1 : 0] raddr,
output [RAM_DATA_WIDTH - 1 : 0] q
); |
parameter MODE = -1;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(raddr),
.RCLK(r_clk),
.RCLKE(r_clk_en),
.RE(re),
.WADDR(waddr),
.WCLK(w_clk),
.WCLKE(w_clk_en),
.WDATA(d),
.WE(we),
.MASK(mask)
);
endmodule | 0 |
3,546 | data/full_repos/permissive/105546923/infra/hdl/rom.v | 105,546,923 | rom.v | v | 36 | 60 | [] | [] | [] | [(1, 35)] | null | data/verilator_xmls/a23d4634-b64f-485a-93ac-37cbfffb455c.xml | null | 1,324 | module | module rom(
input clk,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8;
parameter INIT = 0;
parameter FILE_NAME = "";
parameter FILE_START = 0;
parameter FILE_STOP = 1 << ADDR_WIDTH;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
initial
begin
if(INIT)
begin
$readmemh(FILE_NAME, mem, FILE_START, FILE_STOP - 1);
end
end
assign q = _q;
always @ (posedge clk)
begin
_q <= mem[raddr];
end
endmodule | module rom(
input clk,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8;
parameter INIT = 0;
parameter FILE_NAME = "";
parameter FILE_START = 0;
parameter FILE_STOP = 1 << ADDR_WIDTH;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
initial
begin
if(INIT)
begin
$readmemh(FILE_NAME, mem, FILE_START, FILE_STOP - 1);
end
end
assign q = _q;
always @ (posedge clk)
begin
_q <= mem[raddr];
end
endmodule | 0 |
3,547 | data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v | 105,546,923 | uart_ctrl.v | v | 31 | 44 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n uart.vh\n uart.vh.v\n uart.vh.sv\n obj_dir/uart.vh\n obj_dir/uart.vh.v\n obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:7: Define or directive not defined: \'`UART_DATA_LENGTH\'\n output [`UART_DATA_LENGTH - 1 : 0] rx_o,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:9: Define or directive not defined: \'`UART_DATA_LENGTH\'\n input [`UART_DATA_LENGTH - 1 : 0] tx_i,\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 1,325 | module | module uart_ctrl(
input clk_rx_i,
input clk_tx_i,
input rx_i,
output [`UART_DATA_LENGTH - 1 : 0] rx_o,
output rx_o_v,
input [`UART_DATA_LENGTH - 1 : 0] tx_i,
input tx_i_v,
output tx_o,
output tx_o_v
);
uart_rx uart_rx(
.clk_i(clk_rx_i),
.rx_i(rx_i),
.tx_o(rx_o),
.tx_o_v(rx_o_v)
);
uart_tx uart_tx(
.clk_i (clk_tx_i),
.rx_i (tx_i),
.rx_i_v (tx_i_v),
.tx_o (tx_o),
.tx_o_v (tx_o_v)
);
endmodule | module uart_ctrl(
input clk_rx_i,
input clk_tx_i,
input rx_i,
output [`UART_DATA_LENGTH - 1 : 0] rx_o,
output rx_o_v,
input [`UART_DATA_LENGTH - 1 : 0] tx_i,
input tx_i_v,
output tx_o,
output tx_o_v
); |
uart_rx uart_rx(
.clk_i(clk_rx_i),
.rx_i(rx_i),
.tx_o(rx_o),
.tx_o_v(rx_o_v)
);
uart_tx uart_tx(
.clk_i (clk_tx_i),
.rx_i (tx_i),
.rx_i_v (tx_i_v),
.tx_o (tx_o),
.tx_o_v (tx_o_v)
);
endmodule | 0 |
3,548 | data/full_repos/permissive/105546923/infra/hdl/uart_rx.v | 105,546,923 | uart_rx.v | v | 121 | 76 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n uart.vh\n uart.vh.v\n uart.vh.sv\n obj_dir/uart.vh\n obj_dir/uart.vh.v\n obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:10: Define or directive not defined: \'`UART_RX_SAMPLE_RATE\'\n localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:11: Define or directive not defined: \'`UART_RX_SAMPLE_UPPER\'\n localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:12: Define or directive not defined: \'`UART_RX_SAMPLE_MID\'\n localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:12: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:13: Define or directive not defined: \'`UART_RX_SAMPLE_LOWER\'\n localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:13: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:17: Define or directive not defined: \'`UART_PACKET_LENGTH\'\n localparam PACKET_LENGTH = `UART_PACKET_LENGTH;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam PACKET_LENGTH = `UART_PACKET_LENGTH;\n ^\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:19: Define or directive not defined: \'`UART_DATA_LENGTH\'\n localparam DATA_LENGTH = `UART_DATA_LENGTH;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_rx.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam DATA_LENGTH = `UART_DATA_LENGTH;\n ^\n%Error: Exiting due to 13 error(s)\n' | 1,326 | module | module uart_rx(
input clk_i,
input rx_i,
output [DATA_LENGTH - 1 : 0] tx_o,
output tx_o_v
);
localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;
localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;
localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;
localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;
localparam SAMPLE_WIDTH = $clog2(SAMPLE_RATE);
localparam PACKET_LENGTH = `UART_PACKET_LENGTH;
localparam PACKET_WIDTH = $clog2(PACKET_LENGTH);
localparam DATA_LENGTH = `UART_DATA_LENGTH;
localparam DATA_WIDTH = $clog2(DATA_LENGTH);
localparam ST_IDLE = 2'd0;
localparam ST_START = 2'd1;
localparam ST_DATA = 2'd2;
localparam ST_STOP = 2'd3;
reg [2 : 0] state = ST_IDLE;
reg rx_i_d = 0;
reg [PACKET_WIDTH - 1 : 0] ctr_bit = 0;
reg [SAMPLE_WIDTH - 1 : 0] ctr_sample = 0;
reg [SAMPLE_RATE - 1 : 0] rx_i_shift = 0;
reg rx_vote = 0;
reg [DATA_LENGTH - 1 : 0] s_tx_o = 0;
assign tx_o = s_tx_o;
assign tx_o_v = state == ST_STOP & rx_vote & ctr_sample == SAMPLE_UPPER;
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE | state == ST_IDLE)
begin
ctr_sample <= 0;
end
else
begin
ctr_sample <= ctr_sample + 1;
end
end
always @ (posedge clk_i)
begin
if (state == ST_IDLE)
begin
ctr_bit <= 0;
end
else if (ctr_sample == SAMPLE_RATE - 1)
begin
ctr_bit <= ctr_bit + 1;
end
end
always @ (posedge clk_i)
begin
rx_i_shift <= { {rx_i_shift[SAMPLE_RATE - 2 : 0]} , {rx_i} };
end
always @ (posedge clk_i)
begin
rx_vote <= (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_MID])
| (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_LOWER])
| (rx_i_shift[SAMPLE_MID] & rx_i_shift[SAMPLE_LOWER]);
end
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE - 1)
begin
s_tx_o <= { {rx_vote}, {s_tx_o[DATA_LENGTH - 1 : 1]} };
end
end
always @ (posedge clk_i)
begin
rx_i_d <= rx_i;
end
always @ (posedge clk_i)
begin
case (state)
ST_IDLE:
if (~rx_i & rx_i_d)
begin
state <= ST_START;
end
ST_START:
if (ctr_sample == SAMPLE_RATE - 1)
begin
state <= ST_DATA;
end
ST_DATA:
if (ctr_bit == DATA_LENGTH & ctr_sample == SAMPLE_RATE - 1 )
begin
state <= ST_STOP;
end
ST_STOP:
if (ctr_bit == PACKET_LENGTH - 1 & ctr_sample == SAMPLE_UPPER)
begin
state <= ST_IDLE;
end
endcase
end
endmodule | module uart_rx(
input clk_i,
input rx_i,
output [DATA_LENGTH - 1 : 0] tx_o,
output tx_o_v
); |
localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;
localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;
localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;
localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;
localparam SAMPLE_WIDTH = $clog2(SAMPLE_RATE);
localparam PACKET_LENGTH = `UART_PACKET_LENGTH;
localparam PACKET_WIDTH = $clog2(PACKET_LENGTH);
localparam DATA_LENGTH = `UART_DATA_LENGTH;
localparam DATA_WIDTH = $clog2(DATA_LENGTH);
localparam ST_IDLE = 2'd0;
localparam ST_START = 2'd1;
localparam ST_DATA = 2'd2;
localparam ST_STOP = 2'd3;
reg [2 : 0] state = ST_IDLE;
reg rx_i_d = 0;
reg [PACKET_WIDTH - 1 : 0] ctr_bit = 0;
reg [SAMPLE_WIDTH - 1 : 0] ctr_sample = 0;
reg [SAMPLE_RATE - 1 : 0] rx_i_shift = 0;
reg rx_vote = 0;
reg [DATA_LENGTH - 1 : 0] s_tx_o = 0;
assign tx_o = s_tx_o;
assign tx_o_v = state == ST_STOP & rx_vote & ctr_sample == SAMPLE_UPPER;
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE | state == ST_IDLE)
begin
ctr_sample <= 0;
end
else
begin
ctr_sample <= ctr_sample + 1;
end
end
always @ (posedge clk_i)
begin
if (state == ST_IDLE)
begin
ctr_bit <= 0;
end
else if (ctr_sample == SAMPLE_RATE - 1)
begin
ctr_bit <= ctr_bit + 1;
end
end
always @ (posedge clk_i)
begin
rx_i_shift <= { {rx_i_shift[SAMPLE_RATE - 2 : 0]} , {rx_i} };
end
always @ (posedge clk_i)
begin
rx_vote <= (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_MID])
| (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_LOWER])
| (rx_i_shift[SAMPLE_MID] & rx_i_shift[SAMPLE_LOWER]);
end
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE - 1)
begin
s_tx_o <= { {rx_vote}, {s_tx_o[DATA_LENGTH - 1 : 1]} };
end
end
always @ (posedge clk_i)
begin
rx_i_d <= rx_i;
end
always @ (posedge clk_i)
begin
case (state)
ST_IDLE:
if (~rx_i & rx_i_d)
begin
state <= ST_START;
end
ST_START:
if (ctr_sample == SAMPLE_RATE - 1)
begin
state <= ST_DATA;
end
ST_DATA:
if (ctr_bit == DATA_LENGTH & ctr_sample == SAMPLE_RATE - 1 )
begin
state <= ST_STOP;
end
ST_STOP:
if (ctr_bit == PACKET_LENGTH - 1 & ctr_sample == SAMPLE_UPPER)
begin
state <= ST_IDLE;
end
endcase
end
endmodule | 0 |
3,549 | data/full_repos/permissive/105546923/infra/hdl/uart_tx.v | 105,546,923 | uart_tx.v | v | 94 | 49 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/uart_tx.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n uart.vh\n uart.vh.v\n uart.vh.sv\n obj_dir/uart.vh\n obj_dir/uart.vh.v\n obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_tx.v:5: Define or directive not defined: \'`UART_DATA_LENGTH\'\n input [`UART_DATA_LENGTH - 1 : 0] rx_i,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_tx.v:19: Define or directive not defined: \'`UART_DATA_LENGTH\'\n reg [`UART_DATA_LENGTH - 1 : 0] s_rx = 0;\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 1,327 | module | module uart_tx(
input clk_i,
input [`UART_DATA_LENGTH - 1 : 0] rx_i,
input rx_i_v,
output tx_o,
output tx_o_v
);
localparam ST_IDLE = 3'd0;
localparam ST_START = 3'd1;
localparam ST_DATA = 3'd2;
localparam ST_STOP = 3'd3;
reg [2:0] state = ST_IDLE;
reg [2:0] tx_ctr = 0;
reg [`UART_DATA_LENGTH - 1 : 0] s_rx = 0;
reg s_tx = 1;
always @ (posedge clk_i)
begin
case (state)
ST_IDLE :
if (rx_i_v)
begin
state <= ST_START;
end
ST_START :
state <= ST_DATA;
ST_DATA :
if (tx_ctr == 7)
begin
state <= ST_STOP;
end
ST_STOP :
state <= ST_IDLE;
endcase
end
always @ (posedge clk_i)
begin
if (state == ST_DATA)
begin
tx_ctr <= tx_ctr + 1;
end
else
begin
tx_ctr <= 0;
end
end
always @ (posedge clk_i)
begin
if (state == ST_START)
begin
s_rx <= rx_i;
end
else if (state == ST_DATA)
begin
s_rx <= s_rx >> 1;
end
end
assign tx_o_v = (state == ST_IDLE) ? 0 : 1;
always @ *
begin
if (state == ST_START)
begin
s_tx = 0;
end
else if (state == ST_DATA)
begin
s_tx = s_rx[0];
end
else if (state == ST_STOP)
begin
s_tx = 1;
end
end
assign tx_o = s_tx;
endmodule | module uart_tx(
input clk_i,
input [`UART_DATA_LENGTH - 1 : 0] rx_i,
input rx_i_v,
output tx_o,
output tx_o_v
); |
localparam ST_IDLE = 3'd0;
localparam ST_START = 3'd1;
localparam ST_DATA = 3'd2;
localparam ST_STOP = 3'd3;
reg [2:0] state = ST_IDLE;
reg [2:0] tx_ctr = 0;
reg [`UART_DATA_LENGTH - 1 : 0] s_rx = 0;
reg s_tx = 1;
always @ (posedge clk_i)
begin
case (state)
ST_IDLE :
if (rx_i_v)
begin
state <= ST_START;
end
ST_START :
state <= ST_DATA;
ST_DATA :
if (tx_ctr == 7)
begin
state <= ST_STOP;
end
ST_STOP :
state <= ST_IDLE;
endcase
end
always @ (posedge clk_i)
begin
if (state == ST_DATA)
begin
tx_ctr <= tx_ctr + 1;
end
else
begin
tx_ctr <= 0;
end
end
always @ (posedge clk_i)
begin
if (state == ST_START)
begin
s_rx <= rx_i;
end
else if (state == ST_DATA)
begin
s_rx <= s_rx >> 1;
end
end
assign tx_o_v = (state == ST_IDLE) ? 0 : 1;
always @ *
begin
if (state == ST_START)
begin
s_tx = 0;
end
else if (state == ST_DATA)
begin
s_tx = s_rx[0];
end
else if (state == ST_STOP)
begin
s_tx = 1;
end
end
assign tx_o = s_tx;
endmodule | 0 |
3,550 | data/full_repos/permissive/105546923/infra/hdl/vga.v | 105,546,923 | vga.v | v | 63 | 100 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/0881349b-12f0-4adc-875c-c8057176b5ac.xml | null | 1,328 | module | module vga(
input clk,
output vs_o,
output vs_valid,
output hs_o,
output hs_valid
);
parameter H_PIX = 640;
parameter H_SYNC_PULSE = 96;
parameter H_FP = 16;
parameter H_BP = 48;
parameter H_SYNC = H_PIX + H_SYNC_PULSE + H_FP + H_BP;
parameter V_PIX = 480;
parameter V_SYNC_PULSE = 2;
parameter V_FP = 10;
parameter V_BP = 33;
parameter V_SYNC = V_PIX + V_SYNC_PULSE + V_FP + V_BP;
localparam H_SYNC_WIDTH = $clog2(H_SYNC);
localparam V_SYNC_WIDTH = $clog2(V_SYNC);
reg [H_SYNC_WIDTH - 1 : 0] ctr_h = 0;
reg [V_SYNC_WIDTH - 1 : 0] ctr_v = 0;
always @ (posedge clk)
begin
if (ctr_h == H_SYNC - 1)
begin
ctr_h <= 0;
end
else
begin
ctr_h <= ctr_h + 1;
end
end
always @ (posedge clk)
begin
if (ctr_h == H_SYNC - 1)
begin
if (ctr_v == V_SYNC - 1)
begin
ctr_v <= 0;
end
else
begin
ctr_v <= ctr_v + 1;
end
end
end
assign hs_o = (ctr_h > H_SYNC_PULSE - 1);
assign vs_o = (ctr_v > V_SYNC_PULSE - 1);
assign hs_valid = (ctr_h > H_SYNC_PULSE + H_BP - 1) & (ctr_h < H_SYNC_PULSE + H_BP + H_PIX - 1);
assign vs_valid = (ctr_v > V_SYNC_PULSE + V_BP - 1) & (ctr_v < V_SYNC_PULSE + V_BP + V_PIX - 1);
endmodule | module vga(
input clk,
output vs_o,
output vs_valid,
output hs_o,
output hs_valid
); |
parameter H_PIX = 640;
parameter H_SYNC_PULSE = 96;
parameter H_FP = 16;
parameter H_BP = 48;
parameter H_SYNC = H_PIX + H_SYNC_PULSE + H_FP + H_BP;
parameter V_PIX = 480;
parameter V_SYNC_PULSE = 2;
parameter V_FP = 10;
parameter V_BP = 33;
parameter V_SYNC = V_PIX + V_SYNC_PULSE + V_FP + V_BP;
localparam H_SYNC_WIDTH = $clog2(H_SYNC);
localparam V_SYNC_WIDTH = $clog2(V_SYNC);
reg [H_SYNC_WIDTH - 1 : 0] ctr_h = 0;
reg [V_SYNC_WIDTH - 1 : 0] ctr_v = 0;
always @ (posedge clk)
begin
if (ctr_h == H_SYNC - 1)
begin
ctr_h <= 0;
end
else
begin
ctr_h <= ctr_h + 1;
end
end
always @ (posedge clk)
begin
if (ctr_h == H_SYNC - 1)
begin
if (ctr_v == V_SYNC - 1)
begin
ctr_v <= 0;
end
else
begin
ctr_v <= ctr_v + 1;
end
end
end
assign hs_o = (ctr_h > H_SYNC_PULSE - 1);
assign vs_o = (ctr_v > V_SYNC_PULSE - 1);
assign hs_valid = (ctr_h > H_SYNC_PULSE + H_BP - 1) & (ctr_h < H_SYNC_PULSE + H_BP + H_PIX - 1);
assign vs_valid = (ctr_v > V_SYNC_PULSE + V_BP - 1) & (ctr_v < V_SYNC_PULSE + V_BP + V_PIX - 1);
endmodule | 0 |
3,551 | data/full_repos/permissive/105546923/projects/blink/hdl/top.v | 105,546,923 | top.v | v | 27 | 40 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/86cb1451-5f2a-431d-92c0-9d0c5b44826f.xml | null | 1,330 | module | module top(
input ice_clk_i,
output [7:0] led_o
);
reg [31:0] ctr;
always @(posedge ice_clk_i)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
endmodule | module top(
input ice_clk_i,
output [7:0] led_o
); |
reg [31:0] ctr;
always @(posedge ice_clk_i)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
endmodule | 0 |
3,552 | data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v | 105,546,923 | top_tb.v | v | 32 | 42 | [] | [] | [] | null | line:12: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/blink.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n # 500 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_i = ~clk_i;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,331 | module | module top_tb;
reg clk_i = 0;
wire [7:0] led_o;
initial
begin
$dumpfile("./build/iverilog/blink.vcd");
$dumpvars(0,top_tb);
# 500 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o)
);
endmodule | module top_tb; |
reg clk_i = 0;
wire [7:0] led_o;
initial
begin
$dumpfile("./build/iverilog/blink.vcd");
$dumpvars(0,top_tb);
# 500 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o)
);
endmodule | 0 |
3,553 | data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v | 105,546,923 | draw.v | v | 355 | 79 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v:277: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'I\' generates 16 bits.\n : ... In instance draw\n _mem_raddr <= I;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v:275: Operator EQ expects 2 bits on the RHS, but RHS\'s VARREF \'en\' generates 1 bits.\n : ... In instance draw\n if (state == en)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v:299: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'draw_cls\' generates 1 bits.\n : ... In instance draw\n ctr_vram <= ctr_vram + draw_cls;\n ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v:331: Cannot find file containing module: \'dram_2048x2\'\n dram_2048x2 vram (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/dram_2048x2\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/dram_2048x2.v\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/dram_2048x2.sv\n dram_2048x2\n dram_2048x2.v\n dram_2048x2.sv\n obj_dir/dram_2048x2\n obj_dir/dram_2048x2.v\n obj_dir/dram_2048x2.sv\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/draw.v:344: Cannot find file containing module: \'draw_screen\'\n draw_screen draw_screen(\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 1,332 | module | module draw(
input clk,
input en,
input cls_en,
input [15 : 0] I,
input [10 : 0] start_pix,
input [3 : 0] start_nibbles,
output [ADDR_WIDTH - 1 : 0] mem_raddr,
input [DATA_WIDTH - 1 : 0] mem_d,
output busy,
output draw_out,
output col,
output hs_o,
output vs_o
);
localparam ST_IDLE = 0;
localparam ST_DRAW_SCREEN = 1;
localparam ST_DRAW_VRAM = 2;
localparam ST_DRAW_CLS = 3;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 12;
localparam VRAM_DATA_WIDTH = 2;
localparam VRAM_ADDR_WIDTH = 11;
localparam PIPE_LENGTH = 4;
reg [1 : 0] state_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr_pipe [PIPE_LENGTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] mem_d_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] q_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] d_pipe [PIPE_LENGTH - 1 : 0];
reg [PIPE_LENGTH - 1 : 0] we_pipe;
reg [2 : 0] ctr_pix_pipe [PIPE_LENGTH - 1 : 0];
reg [1 : 0] state = ST_IDLE;
reg [ADDR_WIDTH - 1 : 0] _mem_raddr = 0;
reg we = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr = 0;
wire [VRAM_DATA_WIDTH - 1 : 0] q;
reg [VRAM_DATA_WIDTH - 1 : 0] d = 0;
wire [VRAM_ADDR_WIDTH - 1 : 0] raddr, draw_vram_raddr, draw_screen_raddr;
reg [3 : 0] ctr_nib = 0;
reg [3 : 0] nibbles = 0;
reg [2 : 0] ctr_pix = 0;
reg [4 : 0] y = 0;
reg [5 : 0] x = 0, x0 = 0;
wire [4 : 0] y_screen;
wire [5 : 0] x_screen;
wire vs, hs;
wire hs_valid, vs_valid;
reg _col;
reg draw_vram = 0, draw_cls = 0;
reg _draw_out;
reg [PIPE_LENGTH - 1 : 0] pipe_vs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_vs = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] ctr_vram = 0;
assign draw_out = _draw_out;
assign vs_o = pipe_vs[3];
assign hs_o = pipe_hs[3];
assign col = _col;
assign raddr = state == ST_DRAW_VRAM ? draw_vram_raddr : draw_screen_raddr;
assign draw_vram_raddr = { {y} , {x} };
assign draw_screen_raddr = { {y_screen} , {x_screen} };
assign mem_raddr = _mem_raddr;
assign busy = vs | draw_vram
| (state_pipe[1] == ST_DRAW_VRAM);
always @ (posedge clk)
begin
if (pipe_vs_valid[2] & pipe_hs_valid[2])
begin
_draw_out <= q[0];
end
else
begin
_draw_out <= 0;
end
end
always @ (vs_valid, hs_valid, hs, vs)
begin
pipe_vs_valid[0] <= vs_valid;
pipe_hs_valid[0] <= hs_valid;
pipe_vs[0] <= vs;
pipe_hs[0] <= hs;
end
always @ (posedge clk)
begin
pipe_vs_valid[PIPE_LENGTH - 1 : 1] <= pipe_vs_valid[PIPE_LENGTH - 2 : 0];
pipe_hs_valid[PIPE_LENGTH - 1 : 1] <= pipe_hs_valid[PIPE_LENGTH - 2 : 0];
pipe_vs[PIPE_LENGTH - 1 : 1] <= pipe_vs[PIPE_LENGTH - 2 : 0];
pipe_hs[PIPE_LENGTH - 1 : 1] <= pipe_hs[PIPE_LENGTH - 2 : 0];
we_pipe[PIPE_LENGTH - 1 : 1] <= we_pipe[PIPE_LENGTH - 2 : 0];
end
always @ (mem_d, state, we, waddr, q, d, ctr_pix)
begin
mem_d_pipe[0] <= mem_d;
state_pipe[0] <= state;
we_pipe[0] <= we;
waddr_pipe[0] <= waddr;
q_pipe[0] <= q;
d_pipe[0] <= d;
ctr_pix_pipe[0] <= ctr_pix;
end
genvar i;
generate
for (i = 1; i < PIPE_LENGTH; i = i + 1)
begin
always @ (posedge clk)
begin
mem_d_pipe[i] <= mem_d_pipe[i - 1];
state_pipe[i] <= state_pipe[i - 1];
waddr_pipe[i] <= waddr_pipe[i - 1];
q_pipe[i] <= q_pipe[i - 1];
d_pipe[i] <= d_pipe[i - 1];
ctr_pix_pipe[i] <= ctr_pix_pipe[i - 1];
end
end
endgenerate
always @ (posedge clk)
begin
case (state)
ST_IDLE:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (cls_en)
begin
state <= ST_DRAW_CLS;
end
else if (en)
begin
state <= ST_DRAW_VRAM;
end
end
ST_DRAW_VRAM:
begin
if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
state <= ST_IDLE;
end
else if (vs)
begin
state <= ST_DRAW_SCREEN;
end
end
ST_DRAW_SCREEN:
begin
if (~vs)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
ST_DRAW_CLS:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (~draw_cls)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
endcase
end
always @ (posedge clk)
begin
if (en)
begin
y <= start_pix[10 : 6];
x0 <= start_pix[5 : 0];
x <= start_pix[5 : 0];
nibbles <= start_nibbles;
end
else if (state == ST_DRAW_VRAM)
begin
if (ctr_pix == 0)
begin
y <= y + 1;
x <= x0;
end
else
begin
x <= x + 1;
end
end
end
always @ (posedge clk)
begin
if (state == ST_IDLE)
begin
ctr_pix <= 7;
end
else if (state == ST_DRAW_VRAM)
begin
ctr_pix <= ctr_pix - 1;
end
end
always @ (posedge clk)
begin
if (state == ST_DRAW_VRAM)
begin
waddr <= draw_vram_raddr;
end
else
begin
waddr <= ctr_vram;
end
end
always @ (posedge clk)
begin
if (draw_cls)
begin
d <= 0;
end
else if (state_pipe[1] == ST_DRAW_VRAM)
begin
d[0] <= mem_d_pipe[1][ctr_pix_pipe[1]] ^ q[0];
end
end
always @ (posedge clk)
begin
if ( (state_pipe[2] == ST_IDLE) | draw_cls )
begin
_col <= 0;
end
else if (state_pipe[2] == ST_DRAW_VRAM)
begin
if (q_pipe[1][0] == 1 & d[0] == 0)
begin
_col <= 1;
end
end
end
always @ (posedge clk)
begin
if (state == en)
begin
_mem_raddr <= I;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 1)
begin
_mem_raddr <= _mem_raddr + 1;
end
end
always @ (posedge clk)
begin
if (en)
begin
draw_vram <= 1;
end
else if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
draw_vram <= 0;
end
end
always @ (posedge clk)
begin
ctr_vram <= ctr_vram + draw_cls;
end
always @ (posedge clk)
begin
if (cls_en)
begin
draw_cls <= 1;
end
else if (ctr_vram == ((1 << VRAM_ADDR_WIDTH) - 2))
begin
draw_cls <= 0;
end
end
always @ (posedge clk)
begin
if (en)
begin
ctr_nib <= 0;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 0)
begin
ctr_nib <= ctr_nib + 1;
end
end
always @ (posedge clk)
begin
we <= (state == ST_DRAW_VRAM) | (draw_cls);
end
dram_2048x2 vram (
.w_clk(clk),
.r_clk(clk),
.w_clk_en(1'b1),
.r_clk_en(1'b1),
.we(we_pipe[1]),
.waddr(waddr_pipe[1]),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
draw_screen draw_screen(
.clk(clk),
.x(x_screen),
.y(y_screen),
.vs(vs),
.vs_valid(vs_valid),
.hs(hs),
.hs_valid(hs_valid)
);
endmodule | module draw(
input clk,
input en,
input cls_en,
input [15 : 0] I,
input [10 : 0] start_pix,
input [3 : 0] start_nibbles,
output [ADDR_WIDTH - 1 : 0] mem_raddr,
input [DATA_WIDTH - 1 : 0] mem_d,
output busy,
output draw_out,
output col,
output hs_o,
output vs_o
); |
localparam ST_IDLE = 0;
localparam ST_DRAW_SCREEN = 1;
localparam ST_DRAW_VRAM = 2;
localparam ST_DRAW_CLS = 3;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 12;
localparam VRAM_DATA_WIDTH = 2;
localparam VRAM_ADDR_WIDTH = 11;
localparam PIPE_LENGTH = 4;
reg [1 : 0] state_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr_pipe [PIPE_LENGTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] mem_d_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] q_pipe [PIPE_LENGTH - 1 : 0];
reg [VRAM_DATA_WIDTH - 1 : 0] d_pipe [PIPE_LENGTH - 1 : 0];
reg [PIPE_LENGTH - 1 : 0] we_pipe;
reg [2 : 0] ctr_pix_pipe [PIPE_LENGTH - 1 : 0];
reg [1 : 0] state = ST_IDLE;
reg [ADDR_WIDTH - 1 : 0] _mem_raddr = 0;
reg we = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] waddr = 0;
wire [VRAM_DATA_WIDTH - 1 : 0] q;
reg [VRAM_DATA_WIDTH - 1 : 0] d = 0;
wire [VRAM_ADDR_WIDTH - 1 : 0] raddr, draw_vram_raddr, draw_screen_raddr;
reg [3 : 0] ctr_nib = 0;
reg [3 : 0] nibbles = 0;
reg [2 : 0] ctr_pix = 0;
reg [4 : 0] y = 0;
reg [5 : 0] x = 0, x0 = 0;
wire [4 : 0] y_screen;
wire [5 : 0] x_screen;
wire vs, hs;
wire hs_valid, vs_valid;
reg _col;
reg draw_vram = 0, draw_cls = 0;
reg _draw_out;
reg [PIPE_LENGTH - 1 : 0] pipe_vs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs_valid = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_vs = 0;
reg [PIPE_LENGTH - 1 : 0] pipe_hs = 0;
reg [VRAM_ADDR_WIDTH - 1 : 0] ctr_vram = 0;
assign draw_out = _draw_out;
assign vs_o = pipe_vs[3];
assign hs_o = pipe_hs[3];
assign col = _col;
assign raddr = state == ST_DRAW_VRAM ? draw_vram_raddr : draw_screen_raddr;
assign draw_vram_raddr = { {y} , {x} };
assign draw_screen_raddr = { {y_screen} , {x_screen} };
assign mem_raddr = _mem_raddr;
assign busy = vs | draw_vram
| (state_pipe[1] == ST_DRAW_VRAM);
always @ (posedge clk)
begin
if (pipe_vs_valid[2] & pipe_hs_valid[2])
begin
_draw_out <= q[0];
end
else
begin
_draw_out <= 0;
end
end
always @ (vs_valid, hs_valid, hs, vs)
begin
pipe_vs_valid[0] <= vs_valid;
pipe_hs_valid[0] <= hs_valid;
pipe_vs[0] <= vs;
pipe_hs[0] <= hs;
end
always @ (posedge clk)
begin
pipe_vs_valid[PIPE_LENGTH - 1 : 1] <= pipe_vs_valid[PIPE_LENGTH - 2 : 0];
pipe_hs_valid[PIPE_LENGTH - 1 : 1] <= pipe_hs_valid[PIPE_LENGTH - 2 : 0];
pipe_vs[PIPE_LENGTH - 1 : 1] <= pipe_vs[PIPE_LENGTH - 2 : 0];
pipe_hs[PIPE_LENGTH - 1 : 1] <= pipe_hs[PIPE_LENGTH - 2 : 0];
we_pipe[PIPE_LENGTH - 1 : 1] <= we_pipe[PIPE_LENGTH - 2 : 0];
end
always @ (mem_d, state, we, waddr, q, d, ctr_pix)
begin
mem_d_pipe[0] <= mem_d;
state_pipe[0] <= state;
we_pipe[0] <= we;
waddr_pipe[0] <= waddr;
q_pipe[0] <= q;
d_pipe[0] <= d;
ctr_pix_pipe[0] <= ctr_pix;
end
genvar i;
generate
for (i = 1; i < PIPE_LENGTH; i = i + 1)
begin
always @ (posedge clk)
begin
mem_d_pipe[i] <= mem_d_pipe[i - 1];
state_pipe[i] <= state_pipe[i - 1];
waddr_pipe[i] <= waddr_pipe[i - 1];
q_pipe[i] <= q_pipe[i - 1];
d_pipe[i] <= d_pipe[i - 1];
ctr_pix_pipe[i] <= ctr_pix_pipe[i - 1];
end
end
endgenerate
always @ (posedge clk)
begin
case (state)
ST_IDLE:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (cls_en)
begin
state <= ST_DRAW_CLS;
end
else if (en)
begin
state <= ST_DRAW_VRAM;
end
end
ST_DRAW_VRAM:
begin
if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
state <= ST_IDLE;
end
else if (vs)
begin
state <= ST_DRAW_SCREEN;
end
end
ST_DRAW_SCREEN:
begin
if (~vs)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
ST_DRAW_CLS:
begin
if (vs)
begin
state <= ST_DRAW_SCREEN;
end
else if (~draw_cls)
begin
state <= draw_vram ? ST_DRAW_VRAM : ST_IDLE;
end
end
endcase
end
always @ (posedge clk)
begin
if (en)
begin
y <= start_pix[10 : 6];
x0 <= start_pix[5 : 0];
x <= start_pix[5 : 0];
nibbles <= start_nibbles;
end
else if (state == ST_DRAW_VRAM)
begin
if (ctr_pix == 0)
begin
y <= y + 1;
x <= x0;
end
else
begin
x <= x + 1;
end
end
end
always @ (posedge clk)
begin
if (state == ST_IDLE)
begin
ctr_pix <= 7;
end
else if (state == ST_DRAW_VRAM)
begin
ctr_pix <= ctr_pix - 1;
end
end
always @ (posedge clk)
begin
if (state == ST_DRAW_VRAM)
begin
waddr <= draw_vram_raddr;
end
else
begin
waddr <= ctr_vram;
end
end
always @ (posedge clk)
begin
if (draw_cls)
begin
d <= 0;
end
else if (state_pipe[1] == ST_DRAW_VRAM)
begin
d[0] <= mem_d_pipe[1][ctr_pix_pipe[1]] ^ q[0];
end
end
always @ (posedge clk)
begin
if ( (state_pipe[2] == ST_IDLE) | draw_cls )
begin
_col <= 0;
end
else if (state_pipe[2] == ST_DRAW_VRAM)
begin
if (q_pipe[1][0] == 1 & d[0] == 0)
begin
_col <= 1;
end
end
end
always @ (posedge clk)
begin
if (state == en)
begin
_mem_raddr <= I;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 1)
begin
_mem_raddr <= _mem_raddr + 1;
end
end
always @ (posedge clk)
begin
if (en)
begin
draw_vram <= 1;
end
else if (ctr_nib == (nibbles - 1) & (ctr_pix == 0) )
begin
draw_vram <= 0;
end
end
always @ (posedge clk)
begin
ctr_vram <= ctr_vram + draw_cls;
end
always @ (posedge clk)
begin
if (cls_en)
begin
draw_cls <= 1;
end
else if (ctr_vram == ((1 << VRAM_ADDR_WIDTH) - 2))
begin
draw_cls <= 0;
end
end
always @ (posedge clk)
begin
if (en)
begin
ctr_nib <= 0;
end
else if (state == ST_DRAW_VRAM & ctr_pix == 0)
begin
ctr_nib <= ctr_nib + 1;
end
end
always @ (posedge clk)
begin
we <= (state == ST_DRAW_VRAM) | (draw_cls);
end
dram_2048x2 vram (
.w_clk(clk),
.r_clk(clk),
.w_clk_en(1'b1),
.r_clk_en(1'b1),
.we(we_pipe[1]),
.waddr(waddr_pipe[1]),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
draw_screen draw_screen(
.clk(clk),
.x(x_screen),
.y(y_screen),
.vs(vs),
.vs_valid(vs_valid),
.hs(hs),
.hs_valid(hs_valid)
);
endmodule | 0 |
3,554 | data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v | 105,546,923 | draw_screen.v | v | 107 | 85 | [] | [] | [] | [(1, 106)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:40: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n if (x_div_ctr == X_DIV - 1)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:63: Operator EQ expects 32 or 7 bits on the LHS, but LHS\'s VARREF \'_x\' generates 6 bits.\n : ... In instance draw_screen\n else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:63: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:59: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'y_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:59: Operator EQ expects 32 or 7 bits on the LHS, but LHS\'s VARREF \'_x\' generates 6 bits.\n : ... In instance draw_screen\n if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:59: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:80: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n else if (x_div_ctr == X_DIV - 1)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:76: Operator EQ expects 32 or 7 bits on the LHS, but LHS\'s VARREF \'_x\' generates 6 bits.\n : ... In instance draw_screen\n if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:76: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:92: Operator EQ expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'x_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:92: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'y_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:92: Operator EQ expects 32 or 7 bits on the LHS, but LHS\'s VARREF \'_x\' generates 6 bits.\n : ... In instance draw_screen\n else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:88: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'_y\' generates 5 bits.\n : ... In instance draw_screen\n if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:88: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'y_div_ctr\' generates 4 bits.\n : ... In instance draw_screen\n if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))\n ^~\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/draw_screen.v:98: Cannot find file containing module: \'vga\'\n vga vga(\n ^~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/vga\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/vga.v\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/vga.sv\n vga\n vga.v\n vga.sv\n obj_dir/vga\n obj_dir/vga.v\n obj_dir/vga.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n' | 1,333 | module | module draw_screen(
input clk,
output [X_ADDR_WIDTH - 1 : 0] x,
output [Y_ADDR_WIDTH - 1 : 0] y,
output vs,
output vs_valid,
output hs,
output hs_valid
);
localparam X_MAX = 64;
localparam Y_MAX = 32;
localparam X_ADDR_WIDTH = $clog2(X_MAX);
localparam Y_ADDR_WIDTH = $clog2(Y_MAX);
localparam X_PIX = 640;
localparam Y_PIX = 480;
localparam X_DIV = X_PIX / X_MAX;
localparam Y_DIV = Y_PIX / Y_MAX;
localparam X_DIV_WIDTH = $clog2(X_DIV);
localparam Y_DIV_WIDTH = $clog2(Y_DIV);
reg [X_DIV_WIDTH - 1 : 0] x_div_ctr = 0;
reg [Y_DIV_WIDTH - 1 : 0] y_div_ctr = 0;
reg [X_ADDR_WIDTH - 1 : 0] _x = 0;
reg [Y_ADDR_WIDTH - 1 : 0] _y = 0;
wire _hs_valid, _vs_valid;
assign vs_valid = _vs_valid;
assign hs_valid = _hs_valid;
assign x = _x;
assign y = _y;
always @ (posedge clk)
begin
if (_hs_valid)
begin
if (x_div_ctr == X_DIV - 1)
begin
x_div_ctr <= 0;
end
else
begin
x_div_ctr <= x_div_ctr + 1;
end
end
else
begin
x_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if (_vs_valid)
begin
if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= 0;
end
else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= y_div_ctr + 1;
end
end
else
begin
y_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
_x <= 0;
end
else if (x_div_ctr == X_DIV - 1)
begin
_x <= x + 1;
end
end
always @ (posedge clk)
begin
if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))
begin
_y <= 0;
end
else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))
begin
_y <= _y + 1;
end
end
vga vga(
.clk(clk),
.vs_o(vs),
.vs_valid(_vs_valid),
.hs_o(hs),
.hs_valid(_hs_valid)
);
endmodule | module draw_screen(
input clk,
output [X_ADDR_WIDTH - 1 : 0] x,
output [Y_ADDR_WIDTH - 1 : 0] y,
output vs,
output vs_valid,
output hs,
output hs_valid
); |
localparam X_MAX = 64;
localparam Y_MAX = 32;
localparam X_ADDR_WIDTH = $clog2(X_MAX);
localparam Y_ADDR_WIDTH = $clog2(Y_MAX);
localparam X_PIX = 640;
localparam Y_PIX = 480;
localparam X_DIV = X_PIX / X_MAX;
localparam Y_DIV = Y_PIX / Y_MAX;
localparam X_DIV_WIDTH = $clog2(X_DIV);
localparam Y_DIV_WIDTH = $clog2(Y_DIV);
reg [X_DIV_WIDTH - 1 : 0] x_div_ctr = 0;
reg [Y_DIV_WIDTH - 1 : 0] y_div_ctr = 0;
reg [X_ADDR_WIDTH - 1 : 0] _x = 0;
reg [Y_ADDR_WIDTH - 1 : 0] _y = 0;
wire _hs_valid, _vs_valid;
assign vs_valid = _vs_valid;
assign hs_valid = _hs_valid;
assign x = _x;
assign y = _y;
always @ (posedge clk)
begin
if (_hs_valid)
begin
if (x_div_ctr == X_DIV - 1)
begin
x_div_ctr <= 0;
end
else
begin
x_div_ctr <= x_div_ctr + 1;
end
end
else
begin
x_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if (_vs_valid)
begin
if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= 0;
end
else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= y_div_ctr + 1;
end
end
else
begin
y_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
_x <= 0;
end
else if (x_div_ctr == X_DIV - 1)
begin
_x <= x + 1;
end
end
always @ (posedge clk)
begin
if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))
begin
_y <= 0;
end
else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))
begin
_y <= _y + 1;
end
end
vga vga(
.clk(clk),
.vs_o(vs),
.vs_valid(_vs_valid),
.hs_o(hs),
.hs_valid(_hs_valid)
);
endmodule | 0 |
3,555 | data/full_repos/permissive/105546923/projects/chip8/hdl/interpreter.v | 105,546,923 | interpreter.v | v | 1,220 | 79 | [] | [] | [] | null | line:148 column:263: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/interpreter.v:1: Cannot find include file: chip8.vh\n`include "chip8.vh" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/chip8.vh\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/chip8.vh.v\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/chip8.vh.sv\n chip8.vh\n chip8.vh.v\n chip8.vh.sv\n obj_dir/chip8.vh\n obj_dir/chip8.vh.v\n obj_dir/chip8.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 1,334 | module | module interpreter(
input clk,
input [7 : 0] rx_i,
input rx_i_v,
output vs,
output hs,
output draw_o
);
localparam ST_IDLE = 0;
localparam ST_RD_L = 1;
localparam ST_RD_U = 2;
localparam ST_OP = 3;
localparam ST_DRAW = 4;
localparam OP_SYS = 0;
localparam OP_JP_ADDR = 1;
localparam OP_CALL_ADDR = 2;
localparam OP_SE_VX_BYTE = 3;
localparam OP_SNE_VX_BYTE = 4;
localparam OP_SE_VX_VY = 5;
localparam OP_LD_VX_BYTE = 6;
localparam OP_ADD_VX_BYTE = 7;
localparam OP_VX_VY = 8;
localparam OP_SNE_VX_VY = 9;
localparam OP_LD_I_ADDR = 10;
localparam OP_JP_V0_ADDR = 11;
localparam OP_RND_VX_BYTE = 12;
localparam OP_DRW_VX_VY_NIB = 13;
localparam OP_SKP_VX = 14;
localparam OP_LD_VX = 15;
localparam ST_OP_IDLE = 0;
localparam ST_OP_LD_VX_VY = 1;
localparam ST_OP_OR_VX_VY = 2;
localparam ST_OP_AND_VX_VY = 3;
localparam ST_OP_XOR_VX_VY = 4;
localparam ST_OP_ADD_VX_VY = 5;
localparam ST_OP_SUB_VX_VY = 6;
localparam ST_OP_SHR_VX_VY = 7;
localparam ST_OP_SUBN_VX_VY = 8;
localparam ST_OP_SHL_VX_VY = 9;
localparam ST_OP_LD_VX_DT = 10;
localparam ST_OP_LD_VX_K = 11;
localparam ST_OP_LD_DT_VX = 12;
localparam ST_OP_LD_ST_VX = 13;
localparam ST_OP_ADD_I_VX = 14;
localparam ST_OP_LD_F_VX = 15;
localparam ST_OP_LD_B_VX = 16;
localparam ST_OP_LD_I_VX = 17;
localparam ST_OP_LD_VX_I = 18;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 12;
reg [3 : 0] state = ST_IDLE;
reg [4 : 0] opcode = OP_SYS;
reg [4 : 0] state_op = ST_OP_IDLE;
reg [PIPE_LENGTH - 1 : 0] op_en_pipe;
reg [15 : 0] I = 0;
wire [DATA_WIDTH - 1 : 0] mem_q;
reg [DATA_WIDTH - 1 : 0] mem_d = 0;
reg [ADDR_WIDTH - 1 : 0] mem_raddr;
reg [ADDR_WIDTH - 1 : 0] waddr = 0;
wire re;
reg we = 0;
reg [ADDR_WIDTH - 1 : 0] pc = 512;
localparam PIPE_LENGTH = 5;
reg [DATA_WIDTH - 1 : 0] mem_q_pipe [PIPE_LENGTH - 1 : 0];
reg [3 : 0] state_pipe [PIPE_LENGTH - 1 : 0];
reg [3 : 0] opcode_pipe [PIPE_LENGTH - 1 : 0];
reg [V_DATA_WIDTH - 1 : 0] v_q_pipe [PIPE_LENGTH - 1 : 0];
reg [15 : 0] I_pipe [PIPE_LENGTH - 1 : 0];
reg [15 : 0] dec_to_bcd_q_pipe [PIPE_LENGTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] pc_pipe [PIPE_LENGTH - 1 : 0];
localparam V_ADDR_WIDTH = 4;
localparam V_DATA_WIDTH = 8;
reg v_we = 0, v_re = 0;
reg [V_ADDR_WIDTH - 1 : 0] v_waddr = 0, v_raddr = 0;
reg [V_DATA_WIDTH - 1 : 0] v_d = 0, v_q = 0;
wire _v_we, _v_re;
wire [V_ADDR_WIDTH - 1 : 0] _v_waddr, _v_raddr;
wire [V_DATA_WIDTH - 1 : 0] _v_d, _v_q;
wire [ADDR_WIDTH - 1 : 0] draw_raddr;
wire draw_busy;
wire [10 : 0] vram_start_pix;
wire [3 : 0] vram_nibbles;
reg draw_en = 0, cls_en = 0;
wire draw_col;
localparam SP_ADDR_WIDTH = 4;
localparam SP_DATA_WIDTH = ADDR_WIDTH;
reg sp_we = 0;
reg [SP_DATA_WIDTH - 1 : 0] sp_d = 0;
wire [SP_DATA_WIDTH - 1 : 0] sp_q;
reg [SP_ADDR_WIDTH - 1 : 0] sp_waddr = 0, sp_raddr;
reg [7 : 0] dt = 0;
reg [3 : 0] ctr_op = 0;
reg [7 : 0] dec_to_bcd_raddr;
wire [11 : 0] dec_to_bcd_q;
reg [ADDR_WIDTH - 1 : 0] dump_raddr = 0;
wire [7 : 0] sprite_location_q;
reg [8 : 0] carry = 0;
reg ack_k = 0;
reg [7 : 0] rx_i_d = 0;
always @ (posedge clk)
begin
if (rx_i_v)
begin
case (rx_i)
8'h61:
rx_i_d <= 8'h0A;
8'h62:
rx_i_d <= 8'h0B;
8'h63:
rx_i_d <= 8'h0C;
8'h64:
rx_i_d <= 8'h0D;
8'h65:
rx_i_d <= 8'h0E;
8'h66:
rx_i_d <= 8'h0F;
default:
rx_i_d <= rx_i;
endcase;
end
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_SKP_VX)
begin
if ( (mem_q_pipe[0][7 : 0] == 8'h9E) | (mem_q_pipe[0][7 : 0] == 8'hA1) )
begin
ack_k <= 0;
end
end
end
else if ( (state_op == ST_OP_LD_VX_K) & (ctr_op == 0) )
begin
ack_k <= 0;
end
else if (rx_i_v)
begin
ack_k <= 1;
end
end
always @ (state, state_op, draw_raddr, pc, dump_raddr)
begin
if (state == ST_DRAW)
begin
mem_raddr <= draw_raddr;
end
else if (state_op == ST_OP_LD_VX_I)
begin
mem_raddr <= dump_raddr;
end
else
begin
mem_raddr <= pc;
end
end
always @(mem_q, state, opcode, v_q, I, dec_to_bcd_q, pc)
begin
mem_q_pipe[0] <= mem_q;
state_pipe[0] <= state;
opcode_pipe[0] <= opcode;
v_q_pipe[0] <= v_q;
I_pipe[0] <= I;
dec_to_bcd_q_pipe[0] <= dec_to_bcd_q;
pc_pipe[0] <= pc;
op_en_pipe[0] <= (state == ST_RD_L);
end
genvar i;
generate
for (i = 1; i < PIPE_LENGTH; i = i + 1)
begin
always @ (posedge clk)
begin
mem_q_pipe[i] <= mem_q_pipe[i - 1];
state_pipe[i] <= state_pipe[i - 1];
opcode_pipe[i] <= opcode_pipe[i - 1];
v_q_pipe[i] <= v_q_pipe[i - 1];
I_pipe[i] <= I_pipe[i - 1];
dec_to_bcd_q_pipe[i] <= dec_to_bcd_q_pipe[i - 1];
pc_pipe[i] <= pc_pipe[i - 1];
op_en_pipe[i] <= op_en_pipe[i - 1];
end
end
endgenerate
always @ (posedge clk)
begin
case (state)
ST_IDLE:
begin
state <= ST_RD_L;
end
ST_RD_L:
begin
state <= ST_RD_U;
end
ST_RD_U:
begin
if (opcode_pipe[0] == OP_DRW_VX_VY_NIB)
begin
state <= ST_DRAW;
end
else
begin
state <= ST_OP;
end
end
ST_OP:
begin
if (ctr_op == 0)
begin
state <= ST_RD_L;
end
end
ST_DRAW:
begin
if ( ~draw_busy & (ctr_op == 0) )
begin
state <= ST_OP;
end
end
endcase
end
always @ (posedge clk)
begin
if (state_pipe[0] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
ctr_op <= 0;
OP_ADD_VX_BYTE:
ctr_op <= 0;
OP_RND_VX_BYTE:
ctr_op <= 0;
OP_SE_VX_VY:
ctr_op <= 2;
OP_SKP_VX:
ctr_op <= 2;
default:
ctr_op <= 1;
endcase
end
else if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_LD_VX)
begin
case(mem_q_pipe[0])
8'h07:
ctr_op <= 0;
8'h15:
ctr_op <= 0;
8'h1E:
ctr_op <= 0;
8'h33:
ctr_op <= 5;
8'h55:
ctr_op <= mem_q_pipe[2][3 : 0] + 1;
8'h65:
ctr_op <= mem_q_pipe[2][3 : 0] + 2;
default:
ctr_op <= 1;
endcase
end
else if (opcode_pipe[1] == OP_VX_VY)
begin
case(mem_q_pipe[0][3: 0])
4'h0:
ctr_op <= 1;
4'h1:
ctr_op <= 1;
4'h2:
ctr_op <= 1;
4'h3:
ctr_op <= 1;
4'h4:
ctr_op <= 2;
4'h5:
ctr_op <= 2;
4'h6:
ctr_op <= 2;
4'h7:
ctr_op <= 2;
4'hE:
ctr_op <= 2;
endcase
end
else if (opcode_pipe[1] == OP_DRW_VX_VY_NIB)
begin
ctr_op <= 2;
end
end
else if (state_op == ST_OP_LD_VX_K)
begin
ctr_op <= (ack_k) ? 0 : 1;
end
else if (ctr_op > 0)
begin
ctr_op <= ctr_op - 1;
end
end
always @ (posedge clk)
begin
if ( ( state_pipe[0] == ST_RD_L | (state_pipe[0] == ST_RD_U)) )
begin
pc <= pc + 1;
end
else if (state_pipe[1] == ST_RD_U)
begin
case (opcode_pipe[1])
OP_SYS:
begin
if (mem_q_pipe[0] == 8'hEE)
begin
pc <= sp_q;
end
end
OP_JP_ADDR:
begin
pc[11 : 8] <= mem_q_pipe[1][3 : 0];
pc[7 : 0] <= mem_q_pipe[0];
end
OP_CALL_ADDR:
begin
pc[11 : 8] <= mem_q_pipe[1][3 : 0];
pc[7 : 0] <= mem_q_pipe[0];
end
OP_SE_VX_BYTE:
begin
if (v_q_pipe[0] == mem_q_pipe[0][7 : 0])
begin
pc <= pc + 2;
end
end
OP_SNE_VX_BYTE:
begin
if (v_q_pipe[0] != mem_q_pipe[0][7 : 0])
begin
pc <= pc + 2;
end
end
OP_JP_V0_ADDR:
begin
pc <= { {mem_q_pipe[1][3 : 0]} , {mem_q_pipe[0][7 : 0]} } + v_q_pipe[0];
end
OP_SKP_VX:
begin
case(mem_q_pipe[0][7 : 0])
8'h9E:
if ( ack_k & (v_q_pipe[0] == rx_i_d) )
begin
pc <= pc + 2;
end
8'hA1:
if ( (v_q_pipe[0] != rx_i_d) | ( (v_q_pipe[0] == rx_i_d) & ~ack_k) )
begin
pc <= pc + 2;
end
endcase
end
endcase
end
else if (state_pipe[3] == ST_RD_U)
begin
case (opcode_pipe[3])
OP_SE_VX_VY:
begin
if(v_q_pipe[0] == v_q_pipe[1])
begin
pc <= pc + 2;
end
end
endcase
end
end
assign _v_we = v_we;
always @ (mem_q_pipe[0])
begin
case(mem_q_pipe[0][7 : 4])
4'h0:
opcode <= OP_SYS;
4'h1:
opcode <= OP_JP_ADDR;
4'h2:
opcode <= OP_CALL_ADDR;
4'h3:
opcode <= OP_SE_VX_BYTE;
4'h4:
opcode <= OP_SNE_VX_BYTE;
4'h5:
opcode <= OP_SE_VX_VY;
4'h6:
opcode <= OP_LD_VX_BYTE;
4'h7:
opcode <= OP_ADD_VX_BYTE;
4'h8:
opcode <= OP_VX_VY;
4'h9:
opcode <= OP_SNE_VX_VY;
4'hA:
opcode <= OP_LD_I_ADDR;
4'hB:
opcode <= OP_JP_V0_ADDR;
4'hC:
opcode <= OP_RND_VX_BYTE;
4'hD:
opcode <= OP_DRW_VX_VY_NIB;
4'hE:
opcode <= OP_SKP_VX;
4'hF:
opcode <= OP_LD_VX;
endcase
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_DRAW)
begin
v_waddr <= 4'hF;
v_d <= draw_col;
end
else if (state_pipe[1] == ST_RD_L)
begin
v_raddr <= mem_q_pipe[0][3 : 0];
end
else if (state_pipe[1] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
begin
v_waddr <= mem_q_pipe[1][3 : 0];
v_d <= mem_q_pipe[0];
end
OP_ADD_VX_BYTE:
v_waddr <= mem_q_pipe[0][3 : 0];
OP_SE_VX_VY:
begin
v_raddr <= v_raddr + 1;
end
OP_VX_VY:
v_raddr <= mem_q_pipe[0][7 : 4];
OP_RND_VX_BYTE:
begin
v_waddr <= mem_q_pipe[1][3 : 0];
v_d <= ctr_rnd & mem_q_pipe[0];
end
OP_DRW_VX_VY_NIB:
v_raddr <= mem_q_pipe[0][7 : 4];
OP_LD_I_ADDR:
I[11 : 0] <= { {mem_q_pipe[1][3 : 0]}, mem_q_pipe[0][7 : 0] };
OP_LD_VX:
begin
case(mem_q_pipe[0])
8'h07:
begin
v_d <= dt;
v_waddr <= mem_q_pipe[1][3 : 0];
end
8'h1E:
I <= (I + v_q_pipe[0]);
8'h33:
waddr <= I[11 : 0];
8'h55:
v_raddr <= 0;
8'h65:
begin
v_waddr <= 0;
dump_raddr <= I[ADDR_WIDTH - 1 : 0];
end
endcase
end
OP_JP_V0_ADDR:
v_raddr <= 0;
endcase
end
else if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_ADD_VX_BYTE) )
begin
v_d <= v_q_pipe[0] + mem_q_pipe[1];
end
else
begin
case(state_op)
ST_OP_LD_VX_VY:
begin
v_d <= v_q_pipe[0];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_OR_VX_VY:
begin
v_d <= v_q_pipe[0] | v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_AND_VX_VY:
begin
v_d <= v_q_pipe[0] & v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_XOR_VX_VY:
begin
v_d <= v_q_pipe[0] ^ v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_ADD_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[0] + v_q_pipe[1];
carry <= v_q_pipe[0] + v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SUB_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] - v_q_pipe[0];
carry <= v_q_pipe[1] > v_q_pipe[0];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SHR_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] >> 1;
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= v_q_pipe[2][0];
end
endcase
end
ST_OP_SUBN_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[0] - v_q_pipe[1];
carry <= v_q_pipe[0] > v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SHL_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] << 1;
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= v_q_pipe[2][7];
end
endcase
end
ST_OP_LD_B_VX:
begin
if (ctr_op < 3)
begin
waddr <= waddr + 1;
end
case(ctr_op)
3:
mem_d <= dec_to_bcd_q[3 : 0];
2:
mem_d <= dec_to_bcd_q[7 : 4];
1:
mem_d <= dec_to_bcd_q[11 : 8];
endcase
end
ST_OP_LD_F_VX:
begin
I <= sprite_location_q;
end
ST_OP_LD_VX_K:
begin
v_d <= rx_i_d;
if (state_pipe[2] == ST_RD_U)
begin
v_waddr <= mem_q_pipe[2][3 : 0];
end
end
ST_OP_LD_I_VX:
begin
v_raddr <= v_raddr + 1;
mem_d <= v_q_pipe[0];
if ( (state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
waddr <= I;
end
else
begin
waddr <= waddr + 1;
end
end
ST_OP_LD_VX_I:
begin
if ( (state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
v_waddr <= 0;
end
else
begin
v_waddr <= v_waddr + 1;
end
v_d <= mem_q_pipe[0];
dump_raddr <= dump_raddr + 1;
end
endcase
end
end
always @ (posedge clk)
begin
case(state_op)
ST_OP_LD_I_VX:
begin
if ( ~(state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
we <= 1;
end
end
ST_OP_LD_B_VX:
begin
if (ctr_op < 4)
begin
we <= 1;
end
end
default:
we <= 0;
endcase
end
always @ (posedge clk)
begin
case(state_op)
ST_OP_IDLE:
begin
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_VX_VY))
begin
case(mem_q_pipe[0][3 : 0])
4'h0:
state_op <= ST_OP_LD_VX_VY;
4'h1:
state_op <= ST_OP_OR_VX_VY;
4'h2:
state_op <= ST_OP_AND_VX_VY;
4'h3:
state_op <= ST_OP_XOR_VX_VY;
4'h4:
state_op <= ST_OP_ADD_VX_VY;
4'h5:
state_op <= ST_OP_SUB_VX_VY;
4'h6:
state_op <= ST_OP_SHR_VX_VY;
4'h7:
state_op <= ST_OP_SUBN_VX_VY;
4'hE:
state_op <= ST_OP_SHL_VX_VY;
endcase
end
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_LD_VX))
begin
case(mem_q_pipe[0])
8'h07:
state_op <= ST_OP_LD_VX_DT;
8'h0A:
state_op <= ST_OP_LD_VX_K;
8'h15:
state_op <= ST_OP_LD_DT_VX;
8'h18:
state_op <= ST_OP_LD_ST_VX;
8'h1E:
state_op <= ST_OP_ADD_I_VX;
8'h29:
state_op <= ST_OP_LD_F_VX;
8'h33:
state_op <= ST_OP_LD_B_VX;
8'h55:
state_op <= ST_OP_LD_I_VX;
8'h65:
state_op <= ST_OP_LD_VX_I;
endcase
end
end
ST_OP_LD_B_VX:
begin
if (ctr_op == 1)
begin
state_op <= ST_OP_IDLE;
end
end
ST_OP_LD_VX_I:
begin
if (ctr_op == 1)
begin
state_op <= ST_OP_IDLE;
end
end
default:
if (ctr_op == 0)
begin
state_op <= ST_OP_IDLE;
end
endcase
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
v_we <= 1;
OP_RND_VX_BYTE:
v_we <= 1;
default:
v_we <= 0;
endcase
end
else if (state_pipe[1] == ST_DRAW)
begin
v_we <= 1;
end
else if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_ADD_VX_BYTE ) )
begin
v_we <= 1;
end
else
case(state_op)
ST_OP_IDLE:
v_we <= 0;
ST_OP_ADD_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SUB_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SHR_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SUBN_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SHL_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_LD_DT_VX:
v_we <= 0;
ST_OP_LD_ST_VX:
v_we <= 0;
ST_OP_ADD_I_VX:
v_we <= 0;
ST_OP_LD_F_VX:
v_we <= 0;
ST_OP_LD_B_VX:
v_we <= 0;
ST_OP_LD_I_VX:
v_we <= 0;
ST_OP_LD_ST_VX:
v_we <= 0;
ST_OP_LD_VX_K:
v_we <= ack_k & ~v_we;
ST_OP_LD_VX_I:
v_we <= 1;
default:
v_we <= ctr_op == 0;
endcase
end
always @ (posedge clk)
begin
if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_DRW_VX_VY_NIB))
begin
draw_en <= 1;
end
else
begin
draw_en <= 0;
end
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_SYS) )
begin
cls_en <= 1;
end
else
begin
cls_en <= 0;
end
end
assign vram_start_pix[5 : 0] = v_q_pipe[1][5 : 0];
assign vram_start_pix[10 : 6] = v_q_pipe[0][4 : 0];
assign vram_nibbles[3 : 0] = mem_q_pipe[2][3 : 0];
mem#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.INIT(1),
.SPRITE_FILE_NAME("projects/chip8/cfg/sprite.hex"),
.SPRITE_FILE_WIDTH(80),
.PROGRAM_FILE_NAME("projects/chip8/cfg/test.hex"),
.PROGRAM_FILE_WIDTH(18)
) mem (
.clk(clk),
.we(we),
.waddr(waddr),
.d(mem_d),
.re(1'b1),
.raddr(mem_raddr),
.q(mem_q)
);
ram#(
.ADDR_WIDTH(V_ADDR_WIDTH),
.DATA_WIDTH(V_DATA_WIDTH)
) vx (
.clk(clk),
.we(_v_we),
.waddr(v_waddr),
.d(v_d),
.re(1'b1),
.raddr(v_raddr),
.q(_v_q)
);
always @ (posedge clk)
begin
sp_d <= pc;
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_CALL_ADDR)
begin
sp_we <= 1;
end
end
else
begin
sp_we <= 0;
end
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_SYS)
begin
if (mem_q_pipe[0] == 8'hEE)
begin
sp_waddr <= sp_waddr - 1;
end
end
end
else if (state_pipe[2] == ST_RD_U)
begin
if (opcode_pipe[2] == OP_CALL_ADDR)
begin
sp_waddr <= sp_waddr + 1;
end
end
end
always @ (posedge clk)
begin
sp_raddr <= sp_waddr - 1;
end
ram#(
.ADDR_WIDTH(SP_ADDR_WIDTH),
.DATA_WIDTH(SP_DATA_WIDTH)
) stack_addr (
.clk(clk),
.we(sp_we),
.waddr(sp_waddr),
.d(sp_d),
.re(1'b1),
.raddr(sp_raddr),
.q(sp_q)
);
always @ (_v_q)
begin
v_q <= _v_q;
end
always @ (posedge clk)
begin
dec_to_bcd_raddr <= v_q_pipe[0];
end
rom#(
.ADDR_WIDTH(8),
.DATA_WIDTH(12),
.INIT(1),
.FILE_NAME("projects/chip8/cfg/dec_to_bcd.hex")
) dec_to_bcd (
.clk(clk),
.raddr(dec_to_bcd_raddr),
.q(dec_to_bcd_q)
);
rom#(
.ADDR_WIDTH(4),
.DATA_WIDTH(8),
.INIT(1),
.FILE_NAME("projects/chip8/cfg/sprite_location.hex")
) sprite_location (
.clk(clk),
.raddr(v_q_pipe[0][3 : 0]),
.q(sprite_location_q)
);
draw draw(
.clk(clk),
.en(draw_en),
.cls_en(cls_en),
.I(I),
.start_pix(vram_start_pix),
.start_nibbles(vram_nibbles),
.mem_raddr(draw_raddr),
.mem_d(mem_q_pipe[0]),
.busy(draw_busy),
.col(draw_col),
.draw_out(draw_o),
.hs_o(hs),
.vs_o(vs)
);
wire clk_dt;
reg dt_pulse = 0, dt_pulse_d = 0;
always @ (posedge clk_dt)
begin
dt_pulse <= ~dt_pulse;
end
clks#(
.T(418750 / 2)
)
dt_clks(
.clk_i(clk),
.clk_o(clk_dt)
);
always @ (posedge clk)
begin
dt_pulse_d <= dt_pulse;
if (state_op == ST_OP_LD_DT_VX)
begin
dt <= v_q_pipe[0];
end
else if ( dt > 0 )
begin
dt <= dt - (dt_pulse ^ dt_pulse_d);
end
end
reg [7 : 0] ctr_rnd = 0;
always @ (posedge clk)
begin
ctr_rnd <= ctr_rnd + 1;
end
endmodule | module interpreter(
input clk,
input [7 : 0] rx_i,
input rx_i_v,
output vs,
output hs,
output draw_o
); |
localparam ST_IDLE = 0;
localparam ST_RD_L = 1;
localparam ST_RD_U = 2;
localparam ST_OP = 3;
localparam ST_DRAW = 4;
localparam OP_SYS = 0;
localparam OP_JP_ADDR = 1;
localparam OP_CALL_ADDR = 2;
localparam OP_SE_VX_BYTE = 3;
localparam OP_SNE_VX_BYTE = 4;
localparam OP_SE_VX_VY = 5;
localparam OP_LD_VX_BYTE = 6;
localparam OP_ADD_VX_BYTE = 7;
localparam OP_VX_VY = 8;
localparam OP_SNE_VX_VY = 9;
localparam OP_LD_I_ADDR = 10;
localparam OP_JP_V0_ADDR = 11;
localparam OP_RND_VX_BYTE = 12;
localparam OP_DRW_VX_VY_NIB = 13;
localparam OP_SKP_VX = 14;
localparam OP_LD_VX = 15;
localparam ST_OP_IDLE = 0;
localparam ST_OP_LD_VX_VY = 1;
localparam ST_OP_OR_VX_VY = 2;
localparam ST_OP_AND_VX_VY = 3;
localparam ST_OP_XOR_VX_VY = 4;
localparam ST_OP_ADD_VX_VY = 5;
localparam ST_OP_SUB_VX_VY = 6;
localparam ST_OP_SHR_VX_VY = 7;
localparam ST_OP_SUBN_VX_VY = 8;
localparam ST_OP_SHL_VX_VY = 9;
localparam ST_OP_LD_VX_DT = 10;
localparam ST_OP_LD_VX_K = 11;
localparam ST_OP_LD_DT_VX = 12;
localparam ST_OP_LD_ST_VX = 13;
localparam ST_OP_ADD_I_VX = 14;
localparam ST_OP_LD_F_VX = 15;
localparam ST_OP_LD_B_VX = 16;
localparam ST_OP_LD_I_VX = 17;
localparam ST_OP_LD_VX_I = 18;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 12;
reg [3 : 0] state = ST_IDLE;
reg [4 : 0] opcode = OP_SYS;
reg [4 : 0] state_op = ST_OP_IDLE;
reg [PIPE_LENGTH - 1 : 0] op_en_pipe;
reg [15 : 0] I = 0;
wire [DATA_WIDTH - 1 : 0] mem_q;
reg [DATA_WIDTH - 1 : 0] mem_d = 0;
reg [ADDR_WIDTH - 1 : 0] mem_raddr;
reg [ADDR_WIDTH - 1 : 0] waddr = 0;
wire re;
reg we = 0;
reg [ADDR_WIDTH - 1 : 0] pc = 512;
localparam PIPE_LENGTH = 5;
reg [DATA_WIDTH - 1 : 0] mem_q_pipe [PIPE_LENGTH - 1 : 0];
reg [3 : 0] state_pipe [PIPE_LENGTH - 1 : 0];
reg [3 : 0] opcode_pipe [PIPE_LENGTH - 1 : 0];
reg [V_DATA_WIDTH - 1 : 0] v_q_pipe [PIPE_LENGTH - 1 : 0];
reg [15 : 0] I_pipe [PIPE_LENGTH - 1 : 0];
reg [15 : 0] dec_to_bcd_q_pipe [PIPE_LENGTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] pc_pipe [PIPE_LENGTH - 1 : 0];
localparam V_ADDR_WIDTH = 4;
localparam V_DATA_WIDTH = 8;
reg v_we = 0, v_re = 0;
reg [V_ADDR_WIDTH - 1 : 0] v_waddr = 0, v_raddr = 0;
reg [V_DATA_WIDTH - 1 : 0] v_d = 0, v_q = 0;
wire _v_we, _v_re;
wire [V_ADDR_WIDTH - 1 : 0] _v_waddr, _v_raddr;
wire [V_DATA_WIDTH - 1 : 0] _v_d, _v_q;
wire [ADDR_WIDTH - 1 : 0] draw_raddr;
wire draw_busy;
wire [10 : 0] vram_start_pix;
wire [3 : 0] vram_nibbles;
reg draw_en = 0, cls_en = 0;
wire draw_col;
localparam SP_ADDR_WIDTH = 4;
localparam SP_DATA_WIDTH = ADDR_WIDTH;
reg sp_we = 0;
reg [SP_DATA_WIDTH - 1 : 0] sp_d = 0;
wire [SP_DATA_WIDTH - 1 : 0] sp_q;
reg [SP_ADDR_WIDTH - 1 : 0] sp_waddr = 0, sp_raddr;
reg [7 : 0] dt = 0;
reg [3 : 0] ctr_op = 0;
reg [7 : 0] dec_to_bcd_raddr;
wire [11 : 0] dec_to_bcd_q;
reg [ADDR_WIDTH - 1 : 0] dump_raddr = 0;
wire [7 : 0] sprite_location_q;
reg [8 : 0] carry = 0;
reg ack_k = 0;
reg [7 : 0] rx_i_d = 0;
always @ (posedge clk)
begin
if (rx_i_v)
begin
case (rx_i)
8'h61:
rx_i_d <= 8'h0A;
8'h62:
rx_i_d <= 8'h0B;
8'h63:
rx_i_d <= 8'h0C;
8'h64:
rx_i_d <= 8'h0D;
8'h65:
rx_i_d <= 8'h0E;
8'h66:
rx_i_d <= 8'h0F;
default:
rx_i_d <= rx_i;
endcase;
end
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_SKP_VX)
begin
if ( (mem_q_pipe[0][7 : 0] == 8'h9E) | (mem_q_pipe[0][7 : 0] == 8'hA1) )
begin
ack_k <= 0;
end
end
end
else if ( (state_op == ST_OP_LD_VX_K) & (ctr_op == 0) )
begin
ack_k <= 0;
end
else if (rx_i_v)
begin
ack_k <= 1;
end
end
always @ (state, state_op, draw_raddr, pc, dump_raddr)
begin
if (state == ST_DRAW)
begin
mem_raddr <= draw_raddr;
end
else if (state_op == ST_OP_LD_VX_I)
begin
mem_raddr <= dump_raddr;
end
else
begin
mem_raddr <= pc;
end
end
always @(mem_q, state, opcode, v_q, I, dec_to_bcd_q, pc)
begin
mem_q_pipe[0] <= mem_q;
state_pipe[0] <= state;
opcode_pipe[0] <= opcode;
v_q_pipe[0] <= v_q;
I_pipe[0] <= I;
dec_to_bcd_q_pipe[0] <= dec_to_bcd_q;
pc_pipe[0] <= pc;
op_en_pipe[0] <= (state == ST_RD_L);
end
genvar i;
generate
for (i = 1; i < PIPE_LENGTH; i = i + 1)
begin
always @ (posedge clk)
begin
mem_q_pipe[i] <= mem_q_pipe[i - 1];
state_pipe[i] <= state_pipe[i - 1];
opcode_pipe[i] <= opcode_pipe[i - 1];
v_q_pipe[i] <= v_q_pipe[i - 1];
I_pipe[i] <= I_pipe[i - 1];
dec_to_bcd_q_pipe[i] <= dec_to_bcd_q_pipe[i - 1];
pc_pipe[i] <= pc_pipe[i - 1];
op_en_pipe[i] <= op_en_pipe[i - 1];
end
end
endgenerate
always @ (posedge clk)
begin
case (state)
ST_IDLE:
begin
state <= ST_RD_L;
end
ST_RD_L:
begin
state <= ST_RD_U;
end
ST_RD_U:
begin
if (opcode_pipe[0] == OP_DRW_VX_VY_NIB)
begin
state <= ST_DRAW;
end
else
begin
state <= ST_OP;
end
end
ST_OP:
begin
if (ctr_op == 0)
begin
state <= ST_RD_L;
end
end
ST_DRAW:
begin
if ( ~draw_busy & (ctr_op == 0) )
begin
state <= ST_OP;
end
end
endcase
end
always @ (posedge clk)
begin
if (state_pipe[0] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
ctr_op <= 0;
OP_ADD_VX_BYTE:
ctr_op <= 0;
OP_RND_VX_BYTE:
ctr_op <= 0;
OP_SE_VX_VY:
ctr_op <= 2;
OP_SKP_VX:
ctr_op <= 2;
default:
ctr_op <= 1;
endcase
end
else if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_LD_VX)
begin
case(mem_q_pipe[0])
8'h07:
ctr_op <= 0;
8'h15:
ctr_op <= 0;
8'h1E:
ctr_op <= 0;
8'h33:
ctr_op <= 5;
8'h55:
ctr_op <= mem_q_pipe[2][3 : 0] + 1;
8'h65:
ctr_op <= mem_q_pipe[2][3 : 0] + 2;
default:
ctr_op <= 1;
endcase
end
else if (opcode_pipe[1] == OP_VX_VY)
begin
case(mem_q_pipe[0][3: 0])
4'h0:
ctr_op <= 1;
4'h1:
ctr_op <= 1;
4'h2:
ctr_op <= 1;
4'h3:
ctr_op <= 1;
4'h4:
ctr_op <= 2;
4'h5:
ctr_op <= 2;
4'h6:
ctr_op <= 2;
4'h7:
ctr_op <= 2;
4'hE:
ctr_op <= 2;
endcase
end
else if (opcode_pipe[1] == OP_DRW_VX_VY_NIB)
begin
ctr_op <= 2;
end
end
else if (state_op == ST_OP_LD_VX_K)
begin
ctr_op <= (ack_k) ? 0 : 1;
end
else if (ctr_op > 0)
begin
ctr_op <= ctr_op - 1;
end
end
always @ (posedge clk)
begin
if ( ( state_pipe[0] == ST_RD_L | (state_pipe[0] == ST_RD_U)) )
begin
pc <= pc + 1;
end
else if (state_pipe[1] == ST_RD_U)
begin
case (opcode_pipe[1])
OP_SYS:
begin
if (mem_q_pipe[0] == 8'hEE)
begin
pc <= sp_q;
end
end
OP_JP_ADDR:
begin
pc[11 : 8] <= mem_q_pipe[1][3 : 0];
pc[7 : 0] <= mem_q_pipe[0];
end
OP_CALL_ADDR:
begin
pc[11 : 8] <= mem_q_pipe[1][3 : 0];
pc[7 : 0] <= mem_q_pipe[0];
end
OP_SE_VX_BYTE:
begin
if (v_q_pipe[0] == mem_q_pipe[0][7 : 0])
begin
pc <= pc + 2;
end
end
OP_SNE_VX_BYTE:
begin
if (v_q_pipe[0] != mem_q_pipe[0][7 : 0])
begin
pc <= pc + 2;
end
end
OP_JP_V0_ADDR:
begin
pc <= { {mem_q_pipe[1][3 : 0]} , {mem_q_pipe[0][7 : 0]} } + v_q_pipe[0];
end
OP_SKP_VX:
begin
case(mem_q_pipe[0][7 : 0])
8'h9E:
if ( ack_k & (v_q_pipe[0] == rx_i_d) )
begin
pc <= pc + 2;
end
8'hA1:
if ( (v_q_pipe[0] != rx_i_d) | ( (v_q_pipe[0] == rx_i_d) & ~ack_k) )
begin
pc <= pc + 2;
end
endcase
end
endcase
end
else if (state_pipe[3] == ST_RD_U)
begin
case (opcode_pipe[3])
OP_SE_VX_VY:
begin
if(v_q_pipe[0] == v_q_pipe[1])
begin
pc <= pc + 2;
end
end
endcase
end
end
assign _v_we = v_we;
always @ (mem_q_pipe[0])
begin
case(mem_q_pipe[0][7 : 4])
4'h0:
opcode <= OP_SYS;
4'h1:
opcode <= OP_JP_ADDR;
4'h2:
opcode <= OP_CALL_ADDR;
4'h3:
opcode <= OP_SE_VX_BYTE;
4'h4:
opcode <= OP_SNE_VX_BYTE;
4'h5:
opcode <= OP_SE_VX_VY;
4'h6:
opcode <= OP_LD_VX_BYTE;
4'h7:
opcode <= OP_ADD_VX_BYTE;
4'h8:
opcode <= OP_VX_VY;
4'h9:
opcode <= OP_SNE_VX_VY;
4'hA:
opcode <= OP_LD_I_ADDR;
4'hB:
opcode <= OP_JP_V0_ADDR;
4'hC:
opcode <= OP_RND_VX_BYTE;
4'hD:
opcode <= OP_DRW_VX_VY_NIB;
4'hE:
opcode <= OP_SKP_VX;
4'hF:
opcode <= OP_LD_VX;
endcase
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_DRAW)
begin
v_waddr <= 4'hF;
v_d <= draw_col;
end
else if (state_pipe[1] == ST_RD_L)
begin
v_raddr <= mem_q_pipe[0][3 : 0];
end
else if (state_pipe[1] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
begin
v_waddr <= mem_q_pipe[1][3 : 0];
v_d <= mem_q_pipe[0];
end
OP_ADD_VX_BYTE:
v_waddr <= mem_q_pipe[0][3 : 0];
OP_SE_VX_VY:
begin
v_raddr <= v_raddr + 1;
end
OP_VX_VY:
v_raddr <= mem_q_pipe[0][7 : 4];
OP_RND_VX_BYTE:
begin
v_waddr <= mem_q_pipe[1][3 : 0];
v_d <= ctr_rnd & mem_q_pipe[0];
end
OP_DRW_VX_VY_NIB:
v_raddr <= mem_q_pipe[0][7 : 4];
OP_LD_I_ADDR:
I[11 : 0] <= { {mem_q_pipe[1][3 : 0]}, mem_q_pipe[0][7 : 0] };
OP_LD_VX:
begin
case(mem_q_pipe[0])
8'h07:
begin
v_d <= dt;
v_waddr <= mem_q_pipe[1][3 : 0];
end
8'h1E:
I <= (I + v_q_pipe[0]);
8'h33:
waddr <= I[11 : 0];
8'h55:
v_raddr <= 0;
8'h65:
begin
v_waddr <= 0;
dump_raddr <= I[ADDR_WIDTH - 1 : 0];
end
endcase
end
OP_JP_V0_ADDR:
v_raddr <= 0;
endcase
end
else if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_ADD_VX_BYTE) )
begin
v_d <= v_q_pipe[0] + mem_q_pipe[1];
end
else
begin
case(state_op)
ST_OP_LD_VX_VY:
begin
v_d <= v_q_pipe[0];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_OR_VX_VY:
begin
v_d <= v_q_pipe[0] | v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_AND_VX_VY:
begin
v_d <= v_q_pipe[0] & v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_XOR_VX_VY:
begin
v_d <= v_q_pipe[0] ^ v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
ST_OP_ADD_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[0] + v_q_pipe[1];
carry <= v_q_pipe[0] + v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SUB_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] - v_q_pipe[0];
carry <= v_q_pipe[1] > v_q_pipe[0];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SHR_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] >> 1;
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= v_q_pipe[2][0];
end
endcase
end
ST_OP_SUBN_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[0] - v_q_pipe[1];
carry <= v_q_pipe[0] > v_q_pipe[1];
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= carry[8];
end
endcase
end
ST_OP_SHL_VX_VY:
begin
case(ctr_op)
1:
begin
v_d <= v_q_pipe[1] << 1;
v_waddr <= mem_q_pipe[3][3 : 0];
end
0:
begin
v_waddr <= 4'hF;
v_d <= v_q_pipe[2][7];
end
endcase
end
ST_OP_LD_B_VX:
begin
if (ctr_op < 3)
begin
waddr <= waddr + 1;
end
case(ctr_op)
3:
mem_d <= dec_to_bcd_q[3 : 0];
2:
mem_d <= dec_to_bcd_q[7 : 4];
1:
mem_d <= dec_to_bcd_q[11 : 8];
endcase
end
ST_OP_LD_F_VX:
begin
I <= sprite_location_q;
end
ST_OP_LD_VX_K:
begin
v_d <= rx_i_d;
if (state_pipe[2] == ST_RD_U)
begin
v_waddr <= mem_q_pipe[2][3 : 0];
end
end
ST_OP_LD_I_VX:
begin
v_raddr <= v_raddr + 1;
mem_d <= v_q_pipe[0];
if ( (state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
waddr <= I;
end
else
begin
waddr <= waddr + 1;
end
end
ST_OP_LD_VX_I:
begin
if ( (state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
v_waddr <= 0;
end
else
begin
v_waddr <= v_waddr + 1;
end
v_d <= mem_q_pipe[0];
dump_raddr <= dump_raddr + 1;
end
endcase
end
end
always @ (posedge clk)
begin
case(state_op)
ST_OP_LD_I_VX:
begin
if ( ~(state_pipe[2] == ST_RD_U) | (state_pipe[3] == ST_RD_U) )
begin
we <= 1;
end
end
ST_OP_LD_B_VX:
begin
if (ctr_op < 4)
begin
we <= 1;
end
end
default:
we <= 0;
endcase
end
always @ (posedge clk)
begin
case(state_op)
ST_OP_IDLE:
begin
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_VX_VY))
begin
case(mem_q_pipe[0][3 : 0])
4'h0:
state_op <= ST_OP_LD_VX_VY;
4'h1:
state_op <= ST_OP_OR_VX_VY;
4'h2:
state_op <= ST_OP_AND_VX_VY;
4'h3:
state_op <= ST_OP_XOR_VX_VY;
4'h4:
state_op <= ST_OP_ADD_VX_VY;
4'h5:
state_op <= ST_OP_SUB_VX_VY;
4'h6:
state_op <= ST_OP_SHR_VX_VY;
4'h7:
state_op <= ST_OP_SUBN_VX_VY;
4'hE:
state_op <= ST_OP_SHL_VX_VY;
endcase
end
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_LD_VX))
begin
case(mem_q_pipe[0])
8'h07:
state_op <= ST_OP_LD_VX_DT;
8'h0A:
state_op <= ST_OP_LD_VX_K;
8'h15:
state_op <= ST_OP_LD_DT_VX;
8'h18:
state_op <= ST_OP_LD_ST_VX;
8'h1E:
state_op <= ST_OP_ADD_I_VX;
8'h29:
state_op <= ST_OP_LD_F_VX;
8'h33:
state_op <= ST_OP_LD_B_VX;
8'h55:
state_op <= ST_OP_LD_I_VX;
8'h65:
state_op <= ST_OP_LD_VX_I;
endcase
end
end
ST_OP_LD_B_VX:
begin
if (ctr_op == 1)
begin
state_op <= ST_OP_IDLE;
end
end
ST_OP_LD_VX_I:
begin
if (ctr_op == 1)
begin
state_op <= ST_OP_IDLE;
end
end
default:
if (ctr_op == 0)
begin
state_op <= ST_OP_IDLE;
end
endcase
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_RD_U)
begin
case(opcode_pipe[1])
OP_LD_VX_BYTE:
v_we <= 1;
OP_RND_VX_BYTE:
v_we <= 1;
default:
v_we <= 0;
endcase
end
else if (state_pipe[1] == ST_DRAW)
begin
v_we <= 1;
end
else if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_ADD_VX_BYTE ) )
begin
v_we <= 1;
end
else
case(state_op)
ST_OP_IDLE:
v_we <= 0;
ST_OP_ADD_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SUB_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SHR_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SUBN_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_SHL_VX_VY:
v_we <= (ctr_op < 2);
ST_OP_LD_DT_VX:
v_we <= 0;
ST_OP_LD_ST_VX:
v_we <= 0;
ST_OP_ADD_I_VX:
v_we <= 0;
ST_OP_LD_F_VX:
v_we <= 0;
ST_OP_LD_B_VX:
v_we <= 0;
ST_OP_LD_I_VX:
v_we <= 0;
ST_OP_LD_ST_VX:
v_we <= 0;
ST_OP_LD_VX_K:
v_we <= ack_k & ~v_we;
ST_OP_LD_VX_I:
v_we <= 1;
default:
v_we <= ctr_op == 0;
endcase
end
always @ (posedge clk)
begin
if ( (state_pipe[2] == ST_RD_U) & (opcode_pipe[2] == OP_DRW_VX_VY_NIB))
begin
draw_en <= 1;
end
else
begin
draw_en <= 0;
end
if ( (state_pipe[1] == ST_RD_U) & (opcode_pipe[1] == OP_SYS) )
begin
cls_en <= 1;
end
else
begin
cls_en <= 0;
end
end
assign vram_start_pix[5 : 0] = v_q_pipe[1][5 : 0];
assign vram_start_pix[10 : 6] = v_q_pipe[0][4 : 0];
assign vram_nibbles[3 : 0] = mem_q_pipe[2][3 : 0];
mem#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.INIT(1),
.SPRITE_FILE_NAME("projects/chip8/cfg/sprite.hex"),
.SPRITE_FILE_WIDTH(80),
.PROGRAM_FILE_NAME("projects/chip8/cfg/test.hex"),
.PROGRAM_FILE_WIDTH(18)
) mem (
.clk(clk),
.we(we),
.waddr(waddr),
.d(mem_d),
.re(1'b1),
.raddr(mem_raddr),
.q(mem_q)
);
ram#(
.ADDR_WIDTH(V_ADDR_WIDTH),
.DATA_WIDTH(V_DATA_WIDTH)
) vx (
.clk(clk),
.we(_v_we),
.waddr(v_waddr),
.d(v_d),
.re(1'b1),
.raddr(v_raddr),
.q(_v_q)
);
always @ (posedge clk)
begin
sp_d <= pc;
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_CALL_ADDR)
begin
sp_we <= 1;
end
end
else
begin
sp_we <= 0;
end
end
always @ (posedge clk)
begin
if (state_pipe[1] == ST_RD_U)
begin
if (opcode_pipe[1] == OP_SYS)
begin
if (mem_q_pipe[0] == 8'hEE)
begin
sp_waddr <= sp_waddr - 1;
end
end
end
else if (state_pipe[2] == ST_RD_U)
begin
if (opcode_pipe[2] == OP_CALL_ADDR)
begin
sp_waddr <= sp_waddr + 1;
end
end
end
always @ (posedge clk)
begin
sp_raddr <= sp_waddr - 1;
end
ram#(
.ADDR_WIDTH(SP_ADDR_WIDTH),
.DATA_WIDTH(SP_DATA_WIDTH)
) stack_addr (
.clk(clk),
.we(sp_we),
.waddr(sp_waddr),
.d(sp_d),
.re(1'b1),
.raddr(sp_raddr),
.q(sp_q)
);
always @ (_v_q)
begin
v_q <= _v_q;
end
always @ (posedge clk)
begin
dec_to_bcd_raddr <= v_q_pipe[0];
end
rom#(
.ADDR_WIDTH(8),
.DATA_WIDTH(12),
.INIT(1),
.FILE_NAME("projects/chip8/cfg/dec_to_bcd.hex")
) dec_to_bcd (
.clk(clk),
.raddr(dec_to_bcd_raddr),
.q(dec_to_bcd_q)
);
rom#(
.ADDR_WIDTH(4),
.DATA_WIDTH(8),
.INIT(1),
.FILE_NAME("projects/chip8/cfg/sprite_location.hex")
) sprite_location (
.clk(clk),
.raddr(v_q_pipe[0][3 : 0]),
.q(sprite_location_q)
);
draw draw(
.clk(clk),
.en(draw_en),
.cls_en(cls_en),
.I(I),
.start_pix(vram_start_pix),
.start_nibbles(vram_nibbles),
.mem_raddr(draw_raddr),
.mem_d(mem_q_pipe[0]),
.busy(draw_busy),
.col(draw_col),
.draw_out(draw_o),
.hs_o(hs),
.vs_o(vs)
);
wire clk_dt;
reg dt_pulse = 0, dt_pulse_d = 0;
always @ (posedge clk_dt)
begin
dt_pulse <= ~dt_pulse;
end
clks#(
.T(418750 / 2)
)
dt_clks(
.clk_i(clk),
.clk_o(clk_dt)
);
always @ (posedge clk)
begin
dt_pulse_d <= dt_pulse;
if (state_op == ST_OP_LD_DT_VX)
begin
dt <= v_q_pipe[0];
end
else if ( dt > 0 )
begin
dt <= dt - (dt_pulse ^ dt_pulse_d);
end
end
reg [7 : 0] ctr_rnd = 0;
always @ (posedge clk)
begin
ctr_rnd <= ctr_rnd + 1;
end
endmodule | 0 |
3,556 | data/full_repos/permissive/105546923/projects/chip8/hdl/mem.v | 105,546,923 | mem.v | v | 53 | 75 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/2dbfb2b1-3798-4e73-8790-e91200a25ead.xml | null | 1,335 | module | module mem(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
parameter INIT = 0;
parameter SPRITE_FILE_NAME = "";
parameter SPRITE_FILE_WIDTH = 80;
parameter PROGRAM_FILE_NAME = "";
parameter PROGRAM_FILE_WIDTH = 256;
localparam PROGRAM_FILE_START = 512;
initial
begin
if (INIT)
begin
$readmemh(SPRITE_FILE_NAME, mem, 0, SPRITE_FILE_WIDTH - 1);
$readmemh(PROGRAM_FILE_NAME, mem,
PROGRAM_FILE_START, PROGRAM_FILE_START + PROGRAM_FILE_WIDTH - 1);
end
end
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end
endmodule | module mem(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
); |
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
parameter INIT = 0;
parameter SPRITE_FILE_NAME = "";
parameter SPRITE_FILE_WIDTH = 80;
parameter PROGRAM_FILE_NAME = "";
parameter PROGRAM_FILE_WIDTH = 256;
localparam PROGRAM_FILE_START = 512;
initial
begin
if (INIT)
begin
$readmemh(SPRITE_FILE_NAME, mem, 0, SPRITE_FILE_WIDTH - 1);
$readmemh(PROGRAM_FILE_NAME, mem,
PROGRAM_FILE_START, PROGRAM_FILE_START + PROGRAM_FILE_WIDTH - 1);
end
end
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end
endmodule | 0 |
3,557 | data/full_repos/permissive/105546923/projects/chip8/hdl/top.v | 105,546,923 | top.v | v | 95 | 52 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/projects/chip8/hdl,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:2: Cannot find include file: chip8.vh\n`include "chip8.vh" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:3: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:59: Define or directive not defined: \'`UART_CLK_RX_FREQ\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:59: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/hdl/top.v:59: Define or directive not defined: \'`UART_RX_SAMPLE_RATE\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n' | 1,336 | module | module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
wire clk_uart_rx, clk_led, clk_25;
reg [7 : 0] rx_i = 0;
reg rx_i_v = 0, rx_i_v_d = 0, tx_o_v_d = 0;
wire [7 : 0] tx_o;
wire tx_o_v;
wire [7 : 0] _rx_i;
wire _rx_i_v;
wire draw_o;
assign led_o[0] = 1;
assign led_o[1] = clk_led;
assign _rx_i = rx_i;
assign _rx_i_v = rx_i_v;
assign red_o = draw_o ? 4'b1111 : 0;
assign blue_o = draw_o ? 4'b1111 : 0;
assign green_o = draw_o ? 4'b1111 : 0;
always @ (posedge clk_25)
begin
rx_i_v <= tx_o_v & ~rx_i_v_d;
rx_i_v_d <= tx_o_v;
rx_i <= tx_o;
end
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(6000000)
)led_clk(
.clk_i (ice_clk_i),
.clk_o (clk_led)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
) clk_uart_rx_gen(
.clk_i (ice_clk_i),
.clk_o (clk_uart_rx)
);
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
uart_rx uart_rx(
.clk_i(clk_uart_rx),
.rx_i(rs232_rx_i),
.tx_o(tx_o),
.tx_o_v(tx_o_v)
);
interpreter interpreter(
.clk(clk_25),
.rx_i(rx_i),
.rx_i_v(rx_i_v),
.hs(hs_o),
.vs(vs_o),
.draw_o(draw_o)
);
endmodule | module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
); |
wire clk_uart_rx, clk_led, clk_25;
reg [7 : 0] rx_i = 0;
reg rx_i_v = 0, rx_i_v_d = 0, tx_o_v_d = 0;
wire [7 : 0] tx_o;
wire tx_o_v;
wire [7 : 0] _rx_i;
wire _rx_i_v;
wire draw_o;
assign led_o[0] = 1;
assign led_o[1] = clk_led;
assign _rx_i = rx_i;
assign _rx_i_v = rx_i_v;
assign red_o = draw_o ? 4'b1111 : 0;
assign blue_o = draw_o ? 4'b1111 : 0;
assign green_o = draw_o ? 4'b1111 : 0;
always @ (posedge clk_25)
begin
rx_i_v <= tx_o_v & ~rx_i_v_d;
rx_i_v_d <= tx_o_v;
rx_i <= tx_o;
end
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(6000000)
)led_clk(
.clk_i (ice_clk_i),
.clk_o (clk_led)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
) clk_uart_rx_gen(
.clk_i (ice_clk_i),
.clk_o (clk_uart_rx)
);
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
uart_rx uart_rx(
.clk_i(clk_uart_rx),
.rx_i(rs232_rx_i),
.tx_o(tx_o),
.tx_o_v(tx_o_v)
);
interpreter interpreter(
.clk(clk_25),
.rx_i(rx_i),
.rx_i_v(rx_i_v),
.hs(hs_o),
.vs(vs_o),
.draw_o(draw_o)
);
endmodule | 0 |
3,558 | data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v | 105,546,923 | top_tb.v | v | 76 | 52 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:2: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/chip8.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_i = ~clk_i;\n ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: Define or directive not defined: \'`UART_CLK_RX_FREQ\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: Define or directive not defined: \'`UART_RX_SAMPLE_RATE\'\n .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:49: Define or directive not defined: \'`UART_CLK_TX_FREQ\'\n .T(`UART_CLK_TX_FREQ / 2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:49: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n .T(`UART_CLK_TX_FREQ / 2)\n ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n' | 1,340 | module | module top_tb;
reg clk_i = 0;
reg rst_i = 1;
reg [4:0] rx_i_ctr = 0;
reg [19:0] rx_tmp = 20'b10100011101010010000;
reg tmp_rx_bit = 1;
wire [7:0] led_o;
wire clk_uart_tx;
wire clk_uart_rx, rs232_rx_i;
initial
begin
$dumpfile("./build/iverilog/chip8.vcd");
$dumpvars(0,top_tb);
rst_i <= 0;
# 1000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.rstn_i(rst_i),
.rs232_rx_i(rs232_rx_i),
.led_o (led_o)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
assign rs232_rx_i =tmp_rx_bit;
always @ (posedge (clk_uart_tx))
begin
tmp_rx_bit <= rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
end
always @ (posedge clk_uart_tx)
begin
if (rx_i_ctr == 19 | rst_i)
begin
rx_i_ctr <= 0;
end
else
begin
rx_i_ctr <= rx_i_ctr + 1;
end
end
endmodule | module top_tb; |
reg clk_i = 0;
reg rst_i = 1;
reg [4:0] rx_i_ctr = 0;
reg [19:0] rx_tmp = 20'b10100011101010010000;
reg tmp_rx_bit = 1;
wire [7:0] led_o;
wire clk_uart_tx;
wire clk_uart_rx, rs232_rx_i;
initial
begin
$dumpfile("./build/iverilog/chip8.vcd");
$dumpvars(0,top_tb);
rst_i <= 0;
# 1000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.rstn_i(rst_i),
.rs232_rx_i(rs232_rx_i),
.led_o (led_o)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
assign rs232_rx_i =tmp_rx_bit;
always @ (posedge (clk_uart_tx))
begin
tmp_rx_bit <= rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
end
always @ (posedge clk_uart_tx)
begin
if (rx_i_ctr == 19 | rst_i)
begin
rx_i_ctr <= 0;
end
else
begin
rx_i_ctr <= rx_i_ctr + 1;
end
end
endmodule | 0 |
3,559 | data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v | 105,546,923 | mandlebrot.v | v | 171 | 85 | [] | [] | [] | [(1, 170)] | null | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:156: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/mandlebrot.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:159: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, re_pipe[k]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:160: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, im_pipe[k]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:161: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, im_c_pipe[k]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:162: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, re_c_pipe[k]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:164: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, im_c_pipe[10]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot.v:165: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, re_c_pipe[10]);\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,341 | module | module mandlebrot(
input clk,
input [WIDTH - 1 : 0] re_i,
input [WIDTH - 1 : 0] im_i,
input [WIDTH - 1 : 0] re_c,
input [WIDTH - 1 : 0] im_c,
output [WIDTH - 1 : 0] re_o,
output [WIDTH - 1 : 0] im_o,
output escaped,
input valid_i,
output valid_o
);
parameter WIDTH = 8;
parameter DIVERGENCE = 1 << 2 * WIDTH;
localparam MAX_SQUARE = 1 << WIDTH;
localparam VALID_DELAY = 2 * WIDTH + 4;
reg [VALID_DELAY - 1 : 0] valid_pipe = 0;
reg signed [WIDTH - 1 : 0] re_c_pipe [WIDTH + 1 : 0];
reg signed [WIDTH - 1 : 0] im_c_pipe [WIDTH + 1: 0];
always @(*)
begin
valid_pipe[0] <= valid_i;
end
always @(posedge clk)
begin
valid_pipe[VALID_DELAY - 1 : 1] <= valid_pipe[VALID_DELAY - 2 : 0];
end
assign valid_o = valid_pipe[VALID_DELAY - 1];
wire signed [WIDTH : 0] x_signed;
wire signed [WIDTH : 0] y_signed;
assign x_signed = {re_i[WIDTH - 1], re_i};
assign y_signed = {im_i[WIDTH - 1], im_i};
reg signed [WIDTH : 0] x_p_y;
reg signed [WIDTH : 0] x_m_y;
reg signed [WIDTH : 0] double_x;
reg signed [WIDTH : 0] y_d;
wire signed [(WIDTH + 1) * 2 - 1 : 0] re;
wire signed [(WIDTH + 1) * 2 - 1 : 0] im;
always @(posedge clk)
begin
x_p_y <= x_signed + y_signed;
x_m_y <= x_signed - y_signed;
double_x <= re_i << 1;
y_d <= y_signed;
end
multiplier#(
.WIDTH(WIDTH + 1)
) mult_1(
.clk(clk),
.a(x_p_y),
.b(x_m_y),
.c(re)
);
multiplier#(
.WIDTH(WIDTH + 1)
) mult_2(
.clk(clk),
.a(double_x),
.b(y_d),
.c(im)
);
reg [WIDTH - 1 : 0] im_pipe [WIDTH : 0];
reg [WIDTH - 1 : 0] re_pipe [WIDTH : 0];
reg [WIDTH : 0] escaped_i;
wire [WIDTH * 2 - 1 : 0] im_squared;
wire [WIDTH * 2 - 1 : 0] re_squared;
wire [WIDTH - 1 : 0] im_d;
wire [WIDTH - 1 : 0] re_d;
always @(posedge clk)
begin
re_c_pipe[0] <= re_c;
im_c_pipe[0] <= im_c;
re_pipe[0] <= re[WIDTH - 1 : 0] + re_c_pipe[WIDTH + 1];
im_pipe[0] <= im[WIDTH - 1 : 0] + im_c_pipe[WIDTH + 1];
escaped_i[0] <= ((im + im_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((im + im_c_pipe[WIDTH + 1]) < -MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) < -MAX_SQUARE);
escaped_i[WIDTH : 1] <= escaped_i[WIDTH - 1 : 0];
end
genvar i;
generate
for (i = 1; i < WIDTH + 1; i = i + 1)
begin
always @(posedge clk)
begin
re_pipe[i] <= re_pipe[i - 1];
im_pipe[i] <= im_pipe[i - 1];
re_c_pipe[i] <= re_c_pipe[i - 1];
im_c_pipe[i] <= im_c_pipe[i - 1];
end
end
endgenerate
always @(posedge clk)
begin
re_c_pipe[WIDTH + 1] <= re_c_pipe[WIDTH];
im_c_pipe[WIDTH + 1] <= im_c_pipe[WIDTH];
end
assign re_d = re_pipe[0];
assign im_d = im_pipe[0];
assign re_o = re_pipe[WIDTH];
assign im_o = im_pipe[WIDTH];
multiplier#(
.WIDTH(WIDTH)
) square_im(
.clk(clk),
.a(im_d),
.b(im_d),
.c(im_squared)
);
multiplier#(
.WIDTH(WIDTH)
) square_re(
.clk(clk),
.a(re_d),
.b(re_d),
.c(re_squared)
);
assign escaped = ( (re_squared + im_squared) > DIVERGENCE ) || escaped_i[WIDTH];
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < WIDTH + 1; k = k + 1)
begin
$dumpvars(0, re_pipe[k]);
$dumpvars(0, im_pipe[k]);
$dumpvars(0, im_c_pipe[k]);
$dumpvars(0, re_c_pipe[k]);
end
$dumpvars(0, im_c_pipe[10]);
$dumpvars(0, re_c_pipe[10]);
end
endmodule | module mandlebrot(
input clk,
input [WIDTH - 1 : 0] re_i,
input [WIDTH - 1 : 0] im_i,
input [WIDTH - 1 : 0] re_c,
input [WIDTH - 1 : 0] im_c,
output [WIDTH - 1 : 0] re_o,
output [WIDTH - 1 : 0] im_o,
output escaped,
input valid_i,
output valid_o
); |
parameter WIDTH = 8;
parameter DIVERGENCE = 1 << 2 * WIDTH;
localparam MAX_SQUARE = 1 << WIDTH;
localparam VALID_DELAY = 2 * WIDTH + 4;
reg [VALID_DELAY - 1 : 0] valid_pipe = 0;
reg signed [WIDTH - 1 : 0] re_c_pipe [WIDTH + 1 : 0];
reg signed [WIDTH - 1 : 0] im_c_pipe [WIDTH + 1: 0];
always @(*)
begin
valid_pipe[0] <= valid_i;
end
always @(posedge clk)
begin
valid_pipe[VALID_DELAY - 1 : 1] <= valid_pipe[VALID_DELAY - 2 : 0];
end
assign valid_o = valid_pipe[VALID_DELAY - 1];
wire signed [WIDTH : 0] x_signed;
wire signed [WIDTH : 0] y_signed;
assign x_signed = {re_i[WIDTH - 1], re_i};
assign y_signed = {im_i[WIDTH - 1], im_i};
reg signed [WIDTH : 0] x_p_y;
reg signed [WIDTH : 0] x_m_y;
reg signed [WIDTH : 0] double_x;
reg signed [WIDTH : 0] y_d;
wire signed [(WIDTH + 1) * 2 - 1 : 0] re;
wire signed [(WIDTH + 1) * 2 - 1 : 0] im;
always @(posedge clk)
begin
x_p_y <= x_signed + y_signed;
x_m_y <= x_signed - y_signed;
double_x <= re_i << 1;
y_d <= y_signed;
end
multiplier#(
.WIDTH(WIDTH + 1)
) mult_1(
.clk(clk),
.a(x_p_y),
.b(x_m_y),
.c(re)
);
multiplier#(
.WIDTH(WIDTH + 1)
) mult_2(
.clk(clk),
.a(double_x),
.b(y_d),
.c(im)
);
reg [WIDTH - 1 : 0] im_pipe [WIDTH : 0];
reg [WIDTH - 1 : 0] re_pipe [WIDTH : 0];
reg [WIDTH : 0] escaped_i;
wire [WIDTH * 2 - 1 : 0] im_squared;
wire [WIDTH * 2 - 1 : 0] re_squared;
wire [WIDTH - 1 : 0] im_d;
wire [WIDTH - 1 : 0] re_d;
always @(posedge clk)
begin
re_c_pipe[0] <= re_c;
im_c_pipe[0] <= im_c;
re_pipe[0] <= re[WIDTH - 1 : 0] + re_c_pipe[WIDTH + 1];
im_pipe[0] <= im[WIDTH - 1 : 0] + im_c_pipe[WIDTH + 1];
escaped_i[0] <= ((im + im_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((im + im_c_pipe[WIDTH + 1]) < -MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) < -MAX_SQUARE);
escaped_i[WIDTH : 1] <= escaped_i[WIDTH - 1 : 0];
end
genvar i;
generate
for (i = 1; i < WIDTH + 1; i = i + 1)
begin
always @(posedge clk)
begin
re_pipe[i] <= re_pipe[i - 1];
im_pipe[i] <= im_pipe[i - 1];
re_c_pipe[i] <= re_c_pipe[i - 1];
im_c_pipe[i] <= im_c_pipe[i - 1];
end
end
endgenerate
always @(posedge clk)
begin
re_c_pipe[WIDTH + 1] <= re_c_pipe[WIDTH];
im_c_pipe[WIDTH + 1] <= im_c_pipe[WIDTH];
end
assign re_d = re_pipe[0];
assign im_d = im_pipe[0];
assign re_o = re_pipe[WIDTH];
assign im_o = im_pipe[WIDTH];
multiplier#(
.WIDTH(WIDTH)
) square_im(
.clk(clk),
.a(im_d),
.b(im_d),
.c(im_squared)
);
multiplier#(
.WIDTH(WIDTH)
) square_re(
.clk(clk),
.a(re_d),
.b(re_d),
.c(re_squared)
);
assign escaped = ( (re_squared + im_squared) > DIVERGENCE ) || escaped_i[WIDTH];
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < WIDTH + 1; k = k + 1)
begin
$dumpvars(0, re_pipe[k]);
$dumpvars(0, im_pipe[k]);
$dumpvars(0, im_c_pipe[k]);
$dumpvars(0, re_c_pipe[k]);
end
$dumpvars(0, im_c_pipe[10]);
$dumpvars(0, re_c_pipe[10]);
end
endmodule | 0 |
3,560 | data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot_factory.v | 105,546,923 | mandlebrot_factory.v | v | 156 | 89 | [] | [] | [] | [(1, 155)] | null | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot_factory.v:146: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/mandlebrot.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot_factory.v:149: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, iteration_pipe[k]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/mandlebrot_factory.v:150: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, waddr_pipe[k]);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,342 | module | module mandlebrot_factory(
input clk,
input [ADDR_WIDTH - 1 : 0]raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
parameter PIPE_WIDTH = 2 * DATA_WIDTH + 7;
localparam MAX_N_IT = 5;
reg we = 0;
reg [DATA_WIDTH - 1 : 0] iteration_pipe[PIPE_WIDTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
reg [ADDR_WIDTH - 1 : 0] waddr_pipe[PIPE_WIDTH - 1 : 0];
wire escaped;
wire en;
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 1] > MAX_N_IT) )
begin
ctr <= ctr + 1;
end
end
always @(posedge clk)
begin
if ( escaped || (iteration_pipe[PIPE_WIDTH - 2] > (MAX_N_IT - 1)) )
begin
we <= 1;
iteration_pipe[0] <= 0;
end
else
begin
we <= 0;
iteration_pipe[0] <= en ? iteration_pipe[PIPE_WIDTH - 2] + 1 : 0;
end
end
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 2] > MAX_N_IT - 1) )
begin
waddr_pipe[0] <= ctr;
end
else
begin
waddr_pipe[0] <= waddr_pipe[PIPE_WIDTH - 2];
end
end
genvar i;
generate
for (i = 1; i < PIPE_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
waddr_pipe[i] <= waddr_pipe[i - 1];
if (i == PIPE_WIDTH - 1)
begin
iteration_pipe[i] <= escaped ? iteration_pipe[i - 1] : iteration_pipe[i - 1] + 1;
end
else
begin
iteration_pipe[i] <= iteration_pipe[i - 1];
end
end
end
endgenerate
wire [DATA_WIDTH - 1 : 0] d;
wire [ADDR_WIDTH - 1 : 0] waddr;
assign d = iteration_pipe[PIPE_WIDTH - 1];
assign waddr = waddr_pipe[PIPE_WIDTH - 1];
dram_512x8#(
) memory (
.w_clk(clk),
.r_clk(clk),
.we(we),
.waddr(waddr),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
reg [ADDR_WIDTH - 1 : 0] re_i, re_c;
wire [ADDR_WIDTH - 1 : 0] re_o;
reg [ADDR_WIDTH - 1 : 0] im_i, im_c;
wire [ADDR_WIDTH - 1 : 0] im_o;
reg valid_i;
always @(*)
begin
if (~en ||~escaped)
begin
re_i <= 0;
im_i <= 0;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
else
begin
re_i <= re_o;
im_i <= im_o;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
end
always @(posedge clk)
begin
valid_i <= 1'b1;
end
mandlebrot#(
.WIDTH(ADDR_WIDTH)
) mandle(
.clk(clk),
.re_i(re_i),
.im_i(im_i),
.re_c(re_c),
.im_c(im_c),
.re_o(re_o),
.im_o(im_o),
.escaped(escaped),
.valid_i(valid_i),
.valid_o(en)
);
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < PIPE_WIDTH; k = k + 1)
begin
$dumpvars(0, iteration_pipe[k]);
$dumpvars(0, waddr_pipe[k]);
end
end
endmodule | module mandlebrot_factory(
input clk,
input [ADDR_WIDTH - 1 : 0]raddr,
output [DATA_WIDTH - 1 : 0] q
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
parameter PIPE_WIDTH = 2 * DATA_WIDTH + 7;
localparam MAX_N_IT = 5;
reg we = 0;
reg [DATA_WIDTH - 1 : 0] iteration_pipe[PIPE_WIDTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
reg [ADDR_WIDTH - 1 : 0] waddr_pipe[PIPE_WIDTH - 1 : 0];
wire escaped;
wire en;
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 1] > MAX_N_IT) )
begin
ctr <= ctr + 1;
end
end
always @(posedge clk)
begin
if ( escaped || (iteration_pipe[PIPE_WIDTH - 2] > (MAX_N_IT - 1)) )
begin
we <= 1;
iteration_pipe[0] <= 0;
end
else
begin
we <= 0;
iteration_pipe[0] <= en ? iteration_pipe[PIPE_WIDTH - 2] + 1 : 0;
end
end
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 2] > MAX_N_IT - 1) )
begin
waddr_pipe[0] <= ctr;
end
else
begin
waddr_pipe[0] <= waddr_pipe[PIPE_WIDTH - 2];
end
end
genvar i;
generate
for (i = 1; i < PIPE_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
waddr_pipe[i] <= waddr_pipe[i - 1];
if (i == PIPE_WIDTH - 1)
begin
iteration_pipe[i] <= escaped ? iteration_pipe[i - 1] : iteration_pipe[i - 1] + 1;
end
else
begin
iteration_pipe[i] <= iteration_pipe[i - 1];
end
end
end
endgenerate
wire [DATA_WIDTH - 1 : 0] d;
wire [ADDR_WIDTH - 1 : 0] waddr;
assign d = iteration_pipe[PIPE_WIDTH - 1];
assign waddr = waddr_pipe[PIPE_WIDTH - 1];
dram_512x8#(
) memory (
.w_clk(clk),
.r_clk(clk),
.we(we),
.waddr(waddr),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
reg [ADDR_WIDTH - 1 : 0] re_i, re_c;
wire [ADDR_WIDTH - 1 : 0] re_o;
reg [ADDR_WIDTH - 1 : 0] im_i, im_c;
wire [ADDR_WIDTH - 1 : 0] im_o;
reg valid_i;
always @(*)
begin
if (~en ||~escaped)
begin
re_i <= 0;
im_i <= 0;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
else
begin
re_i <= re_o;
im_i <= im_o;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
end
always @(posedge clk)
begin
valid_i <= 1'b1;
end
mandlebrot#(
.WIDTH(ADDR_WIDTH)
) mandle(
.clk(clk),
.re_i(re_i),
.im_i(im_i),
.re_c(re_c),
.im_c(im_c),
.re_o(re_o),
.im_o(im_o),
.escaped(escaped),
.valid_i(valid_i),
.valid_o(en)
);
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < PIPE_WIDTH; k = k + 1)
begin
$dumpvars(0, iteration_pipe[k]);
$dumpvars(0, waddr_pipe[k]);
end
end
endmodule | 0 |
3,561 | data/full_repos/permissive/105546923/projects/mandlebrot/hdl/top.v | 105,546,923 | top.v | v | 63 | 57 | [] | [] | [] | [(1, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/top.v:35: Cannot find file containing module: 'clks'\n clks#(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/mandlebrot/hdl,data/full_repos/permissive/105546923/clks\n data/full_repos/permissive/105546923/projects/mandlebrot/hdl,data/full_repos/permissive/105546923/clks.v\n data/full_repos/permissive/105546923/projects/mandlebrot/hdl,data/full_repos/permissive/105546923/clks.sv\n clks\n clks.v\n clks.sv\n obj_dir/clks\n obj_dir/clks.v\n obj_dir/clks.sv\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/top.v:46: Cannot find file containing module: 'vga'\n vga vga(\n ^~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/hdl/top.v:56: Cannot find file containing module: 'mandlebrot_factory'\n mandlebrot_factory mandle(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 1,343 | module | module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
parameter WIDTH = 8;
wire clk_25;
reg [8 : 0] ctr = 3;
wire vs_valid;
wire hs_valid;
assign red_o = hs_valid & vs_valid ? pix[7 : 4] : 0;
assign blue_o = hs_valid & vs_valid ? pix[3 : 0] : 0;
assign green_o = hs_valid & vs_valid? 4'b1111 : 0;
always @(posedge clk_25)
begin
ctr <= ctr + 1;
end
genvar i;
generate
for (i = 0; i < 8; i = i + 1)
begin
end
endgenerate
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
vga vga(
.clk(clk_25),
.vs_o(vs_o),
.vs_valid(vs_valid),
.hs_o(hs_o),
.hs_valid(hs_valid)
);
wire [7 : 0] pix;
mandlebrot_factory mandle(
.clk(clk_25),
.raddr(ctr),
.q(pix)
);
endmodule | module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
); |
parameter WIDTH = 8;
wire clk_25;
reg [8 : 0] ctr = 3;
wire vs_valid;
wire hs_valid;
assign red_o = hs_valid & vs_valid ? pix[7 : 4] : 0;
assign blue_o = hs_valid & vs_valid ? pix[3 : 0] : 0;
assign green_o = hs_valid & vs_valid? 4'b1111 : 0;
always @(posedge clk_25)
begin
ctr <= ctr + 1;
end
genvar i;
generate
for (i = 0; i < 8; i = i + 1)
begin
end
endgenerate
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
vga vga(
.clk(clk_25),
.vs_o(vs_o),
.vs_valid(vs_valid),
.hs_o(hs_o),
.hs_valid(hs_valid)
);
wire [7 : 0] pix;
mandlebrot_factory mandle(
.clk(clk_25),
.raddr(ctr),
.q(pix)
);
endmodule | 0 |
3,562 | data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v | 105,546,923 | top_tb.v | v | 38 | 47 | [] | [] | [] | null | line:28: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/mandlebrot.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_i = ~clk_i;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 1,346 | module | module top_tb;
reg clk_i = 0;
wire [7:0] led_o;
wire vs;
wire hs;
wire [3 : 0] red;
wire [3 : 0] blue;
wire [3 : 0] green;
integer j = 0;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
$dumpvars(0,top_tb);
# 1000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o),
.vs_o(vs),
.hs_o(hs),
.red_o(red),
.blue_o(blue),
.green_o(green)
);
endmodule | module top_tb; |
reg clk_i = 0;
wire [7:0] led_o;
wire vs;
wire hs;
wire [3 : 0] red;
wire [3 : 0] blue;
wire [3 : 0] green;
integer j = 0;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
$dumpvars(0,top_tb);
# 1000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o),
.vs_o(vs),
.hs_o(hs),
.red_o(red),
.blue_o(blue),
.green_o(green)
);
endmodule | 0 |
3,563 | data/full_repos/permissive/105546923/projects/uart_echo/hdl/top.v | 105,546,923 | top.v | v | 64 | 69 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/uart_echo/hdl/top.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/uart_echo/hdl,data/full_repos/permissive/105546923/uart.vh\n data/full_repos/permissive/105546923/projects/uart_echo/hdl,data/full_repos/permissive/105546923/uart.vh.v\n data/full_repos/permissive/105546923/projects/uart_echo/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n uart.vh\n uart.vh.v\n uart.vh.sv\n obj_dir/uart.vh\n obj_dir/uart.vh.v\n obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/uart_echo/hdl/top.v:12: Define or directive not defined: \'`UART_DATA_LENGTH\'\n reg [`UART_DATA_LENGTH - 1 : 0] fifo_d = 0, tx_i = 0;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/uart_echo/hdl/top.v:16: Define or directive not defined: \'`UART_DATA_LENGTH\'\n wire [`UART_DATA_LENGTH - 1 : 0] fifo_q, rx_o;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/uart_echo/hdl/top.v:34: Define or directive not defined: \'`UART_DATA_LENGTH\'\n .DATA_WIDTH(`UART_DATA_LENGTH),\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 1,347 | module | module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output rs232_tx_o
);
reg tx_i_v = 0, fifo_re = 0, fifo_re_d = 0, fifo_we = 0;
reg [`UART_DATA_LENGTH - 1 : 0] fifo_d = 0, tx_i = 0;
wire clk_uart_rx, clk_uart_tx;
wire fifo_empty, rx_o_v, tx_o_v;
wire [`UART_DATA_LENGTH - 1 : 0] fifo_q, rx_o;
infra infra (
.clk_i (ice_clk_i),
.clk_o_uart_rx(clk_uart_rx),
.clk_o_uart_tx(clk_uart_tx),
.rst_i(rstn_i),
.led_o (led_o),
.rx_i(rs232_rx_i),
.rx_o(rx_o),
.rx_o_v(rx_o_v),
.tx_i(tx_i),
.tx_i_v(tx_i_v),
.tx_o(rs232_tx_o),
.tx_o_v(tx_o_v)
);
fifo#(
.DATA_WIDTH(`UART_DATA_LENGTH),
.ASYNC(1)
) fifo(
.w_clk(clk_uart_rx),
.r_clk(clk_uart_tx),
.we(fifo_we),
.d(fifo_d),
.re(fifo_re),
.q(fifo_q),
.empty(fifo_empty),
.mask(16'b0)
);
always @ (posedge clk_uart_rx)
begin
fifo_we <= rx_o_v;
fifo_d <= rx_o;
end
always @ (posedge clk_uart_tx)
begin
fifo_re <= ~fifo_empty & ~tx_o_v & ~tx_i_v & ~fifo_re & ~fifo_re_d;
fifo_re_d <= fifo_re;
tx_i <= fifo_q;
tx_i_v <= fifo_re_d;
end
endmodule | module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output rs232_tx_o
); |
reg tx_i_v = 0, fifo_re = 0, fifo_re_d = 0, fifo_we = 0;
reg [`UART_DATA_LENGTH - 1 : 0] fifo_d = 0, tx_i = 0;
wire clk_uart_rx, clk_uart_tx;
wire fifo_empty, rx_o_v, tx_o_v;
wire [`UART_DATA_LENGTH - 1 : 0] fifo_q, rx_o;
infra infra (
.clk_i (ice_clk_i),
.clk_o_uart_rx(clk_uart_rx),
.clk_o_uart_tx(clk_uart_tx),
.rst_i(rstn_i),
.led_o (led_o),
.rx_i(rs232_rx_i),
.rx_o(rx_o),
.rx_o_v(rx_o_v),
.tx_i(tx_i),
.tx_i_v(tx_i_v),
.tx_o(rs232_tx_o),
.tx_o_v(tx_o_v)
);
fifo#(
.DATA_WIDTH(`UART_DATA_LENGTH),
.ASYNC(1)
) fifo(
.w_clk(clk_uart_rx),
.r_clk(clk_uart_tx),
.we(fifo_we),
.d(fifo_d),
.re(fifo_re),
.q(fifo_q),
.empty(fifo_empty),
.mask(16'b0)
);
always @ (posedge clk_uart_rx)
begin
fifo_we <= rx_o_v;
fifo_d <= rx_o;
end
always @ (posedge clk_uart_tx)
begin
fifo_re <= ~fifo_empty & ~tx_o_v & ~tx_i_v & ~fifo_re & ~fifo_re_d;
fifo_re_d <= fifo_re;
tx_i <= fifo_q;
tx_i_v <= fifo_re_d;
end
endmodule | 0 |
3,564 | data/full_repos/permissive/105546923/projects/vga/hdl/top.v | 105,546,923 | top.v | v | 139 | 78 | [] | [] | [] | null | line:18: before: "@" | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/vga/hdl/top.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/vga/hdl,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/projects/vga/hdl,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/projects/vga/hdl,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 1,350 | module | module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
reg [31:0] ctr;
reg vs = 0, hs = 0;
reg [9 : 0] ctr_x = 0;
reg [8 : 0] ctr_y = 0;
wire clk_vga;
wire locked;
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b100)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_vga)
);
always @(posedge clk_vga)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
wire pix_clk;
reg pcount = 0;
wire en = (pcount == 0);
always @ (posedge clk_vga) pcount <= ~pcount;
assign pix_clk = en;
reg hsync = 0,vsync = 0,hblank = 0,vblank = 0;
reg [9:0] hcount = 0;
reg [9:0] vcount = 0;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = en & (hcount == 639);
assign hsyncon = en & (hcount == 652-4);
assign hsyncoff = en & (hcount == 746-4);
assign hreset = en & (hcount == 793-4);
wire blank = (vblank | (hblank & ~hreset));
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == 479);
assign vsyncon = hreset & (vcount == 492-4);
assign vsyncoff = hreset & (vcount == 494-4);
assign vreset = hreset & (vcount == 527-4);
always @(posedge clk_vga) begin
hcount <= en ? (hreset ? 0 : hcount + 1) : hcount;
hblank <= hreset ? 0 : hblankon ? 1 : hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync;
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= vreset ? 0 : vblankon ? 1 : vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync;
end
assign hs_o = hsync;
assign vs_o = vsync;
reg [9 : 0] h_bx_ctr = 0;
reg [9 : 0] v_bx_ctr = 0;
wire draw;
wire h_bx, v_vx;
always @ (posedge pix_clk)
begin
if (draw)
begin
h_bx_ctr <= h_bx_ctr + 1;
end
else
begin
h_bx_ctr <= 0;
end
end
always @ (posedge pix_clk)
begin
if (vblankon)
begin
v_bx_ctr <= v_bx_ctr + 1;
end
else if(v_bx_ctr == 479)
begin
v_bx_ctr <= 0;
end
end
assign draw = (hsync & ~hblank) & (vsync & ~vblank);
assign h_bx = (h_bx_ctr > 310) & (h_bx_ctr < 330);
assign v_bx = 1;
assign red_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign blue_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign green_o = draw & h_bx & v_bx ? 4'b1111 : 0;
endmodule | module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
); |
reg [31:0] ctr;
reg vs = 0, hs = 0;
reg [9 : 0] ctr_x = 0;
reg [8 : 0] ctr_y = 0;
wire clk_vga;
wire locked;
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b100)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_vga)
);
always @(posedge clk_vga)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
wire pix_clk;
reg pcount = 0;
wire en = (pcount == 0);
always @ (posedge clk_vga) pcount <= ~pcount;
assign pix_clk = en;
reg hsync = 0,vsync = 0,hblank = 0,vblank = 0;
reg [9:0] hcount = 0;
reg [9:0] vcount = 0;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = en & (hcount == 639);
assign hsyncon = en & (hcount == 652-4);
assign hsyncoff = en & (hcount == 746-4);
assign hreset = en & (hcount == 793-4);
wire blank = (vblank | (hblank & ~hreset));
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == 479);
assign vsyncon = hreset & (vcount == 492-4);
assign vsyncoff = hreset & (vcount == 494-4);
assign vreset = hreset & (vcount == 527-4);
always @(posedge clk_vga) begin
hcount <= en ? (hreset ? 0 : hcount + 1) : hcount;
hblank <= hreset ? 0 : hblankon ? 1 : hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync;
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= vreset ? 0 : vblankon ? 1 : vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync;
end
assign hs_o = hsync;
assign vs_o = vsync;
reg [9 : 0] h_bx_ctr = 0;
reg [9 : 0] v_bx_ctr = 0;
wire draw;
wire h_bx, v_vx;
always @ (posedge pix_clk)
begin
if (draw)
begin
h_bx_ctr <= h_bx_ctr + 1;
end
else
begin
h_bx_ctr <= 0;
end
end
always @ (posedge pix_clk)
begin
if (vblankon)
begin
v_bx_ctr <= v_bx_ctr + 1;
end
else if(v_bx_ctr == 479)
begin
v_bx_ctr <= 0;
end
end
assign draw = (hsync & ~hblank) & (vsync & ~vblank);
assign h_bx = (h_bx_ctr > 310) & (h_bx_ctr < 330);
assign v_bx = 1;
assign red_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign blue_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign green_o = draw & h_bx & v_bx ? 4'b1111 : 0;
endmodule | 0 |
3,565 | data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v | 105,546,923 | top_tb.v | v | 39 | 40 | [] | [] | [] | null | line:24: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/projects/vga/sim,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/projects/vga/sim,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/projects/vga/sim,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/vga.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n # 1000000 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/vga/sim/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_i = ~clk_i;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 1,354 | module | module top_tb;
reg clk_i = 0;
wire [7:0] led_o;
wire vs_o, hs_o;
wire [3 : 0] green_o, red_o, blue_o;
initial
begin
$dumpfile("./build/iverilog/vga.vcd");
$dumpvars(0,top_tb);
# 1000000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o),
.vs_o(vs_o),
.hs_o(hs_o),
.red_o(red_o),
.blue_o(blue_o),
.green_o(green_o)
);
endmodule | module top_tb; |
reg clk_i = 0;
wire [7:0] led_o;
wire vs_o, hs_o;
wire [3 : 0] green_o, red_o, blue_o;
initial
begin
$dumpfile("./build/iverilog/vga.vcd");
$dumpvars(0,top_tb);
# 1000000 $finish;
end
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.led_o (led_o),
.vs_o(vs_o),
.hs_o(hs_o),
.red_o(red_o),
.blue_o(blue_o),
.green_o(green_o)
);
endmodule | 0 |
3,566 | data/full_repos/permissive/105681119/src/alu.v | 105,681,119 | alu.v | v | 58 | 82 | [] | ['mit license'] | [] | [(86, 108)] | null | null | 1: b'%Error: data/full_repos/permissive/105681119/src/alu.v:34: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/alu.v:38: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n input [`DATA_INDEX_LIMIT:0] OP1, OP2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`DATA_INDEX_LIMIT:0] OP1, OP2;\n ^\n%Error: data/full_repos/permissive/105681119/src/alu.v:39: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n input [`ALU_FUNCT_INDEX_LIMIT:0] FUNCT;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:39: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`ALU_FUNCT_INDEX_LIMIT:0] FUNCT;\n ^\n%Error: data/full_repos/permissive/105681119/src/alu.v:42: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n output reg [`DATA_INDEX_LIMIT:0] RESULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:42: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output reg [`DATA_INDEX_LIMIT:0] RESULT;\n ^\n%Error: data/full_repos/permissive/105681119/src/alu.v:46: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h20 : RESULT = OP1 + OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:47: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h22 : RESULT = OP1 - OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:48: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h2c : RESULT = OP1 * OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:49: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h01 : RESULT = OP1 << OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:50: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h02 : RESULT = OP1 >> OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:51: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h24 : RESULT = OP1 & OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:52: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h25 : RESULT = OP1 | OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:53: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h27 : RESULT = ~(OP1 | OP2); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:54: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n `ALU_FUNCT_WIDTH\'h2a : RESULT = OP1 < OP2; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/alu.v:55: Define or directive not defined: \'`DATA_WIDTH\'\n default: RESULT = `DATA_WIDTH\'hx; \n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n' | 1,355 | module | module ALU(OP1, OP2, FUNCT, RESULT);
input [`DATA_INDEX_LIMIT:0] OP1, OP2;
input [`ALU_FUNCT_INDEX_LIMIT:0] FUNCT;
output reg [`DATA_INDEX_LIMIT:0] RESULT;
always @ (OP1 or OP2 or FUNCT) begin
case (FUNCT)
`ALU_FUNCT_WIDTH'h20 : RESULT = OP1 + OP2;
`ALU_FUNCT_WIDTH'h22 : RESULT = OP1 - OP2;
`ALU_FUNCT_WIDTH'h2c : RESULT = OP1 * OP2;
`ALU_FUNCT_WIDTH'h01 : RESULT = OP1 << OP2;
`ALU_FUNCT_WIDTH'h02 : RESULT = OP1 >> OP2;
`ALU_FUNCT_WIDTH'h24 : RESULT = OP1 & OP2;
`ALU_FUNCT_WIDTH'h25 : RESULT = OP1 | OP2;
`ALU_FUNCT_WIDTH'h27 : RESULT = ~(OP1 | OP2);
`ALU_FUNCT_WIDTH'h2a : RESULT = OP1 < OP2;
default: RESULT = `DATA_WIDTH'hx;
endcase
end
endmodule | module ALU(OP1, OP2, FUNCT, RESULT); |
input [`DATA_INDEX_LIMIT:0] OP1, OP2;
input [`ALU_FUNCT_INDEX_LIMIT:0] FUNCT;
output reg [`DATA_INDEX_LIMIT:0] RESULT;
always @ (OP1 or OP2 or FUNCT) begin
case (FUNCT)
`ALU_FUNCT_WIDTH'h20 : RESULT = OP1 + OP2;
`ALU_FUNCT_WIDTH'h22 : RESULT = OP1 - OP2;
`ALU_FUNCT_WIDTH'h2c : RESULT = OP1 * OP2;
`ALU_FUNCT_WIDTH'h01 : RESULT = OP1 << OP2;
`ALU_FUNCT_WIDTH'h02 : RESULT = OP1 >> OP2;
`ALU_FUNCT_WIDTH'h24 : RESULT = OP1 & OP2;
`ALU_FUNCT_WIDTH'h25 : RESULT = OP1 | OP2;
`ALU_FUNCT_WIDTH'h27 : RESULT = ~(OP1 | OP2);
`ALU_FUNCT_WIDTH'h2a : RESULT = OP1 < OP2;
default: RESULT = `DATA_WIDTH'hx;
endcase
end
endmodule | 0 |
3,567 | data/full_repos/permissive/105681119/src/clk_gen.v | 105,681,119 | clk_gen.v | v | 46 | 82 | [] | ['mit license'] | [] | [(84, 96)] | null | null | 1: b'%Error: data/full_repos/permissive/105681119/src/clk_gen.v:32: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/clk_gen.v:44: Define or directive not defined: \'`SYS_CLK_HALF_PERIOD\'\n #`SYS_CLK_HALF_PERIOD CLK = ~CLK;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/clk_gen.v:44: syntax error, unexpected \'=\'\n #`SYS_CLK_HALF_PERIOD CLK = ~CLK;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105681119/src/clk_gen.v:44: Unsupported: Ignoring delay on this delayed statement.\n #`SYS_CLK_HALF_PERIOD CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 1,356 | module | module CLK_GENERATOR(CLK);
output reg CLK;
initial begin
CLK = 1'b1;
end
always begin
#`SYS_CLK_HALF_PERIOD CLK = ~CLK;
end
endmodule | module CLK_GENERATOR(CLK); |
output reg CLK;
initial begin
CLK = 1'b1;
end
always begin
#`SYS_CLK_HALF_PERIOD CLK = ~CLK;
end
endmodule | 0 |
3,568 | data/full_repos/permissive/105681119/src/control_unit.v | 105,681,119 | control_unit.v | v | 98 | 82 | [] | ['mit license'] | [] | [(94, 148)] | null | null | 1: b'%Error: data/full_repos/permissive/105681119/src/control_unit.v:42: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:47: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n input [`ALU_FUNCT_INDEX_LIMIT:0] OPCODE, FUNCT;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:47: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`ALU_FUNCT_INDEX_LIMIT:0] OPCODE, FUNCT;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:49: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n input [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:49: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:53: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n output reg [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:53: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output reg [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:54: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n output reg [`ALU_FUNCT_INDEX_LIMIT:0] ALU_CODE;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:54: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output reg [`ALU_FUNCT_INDEX_LIMIT:0] ALU_CODE;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:61: Define or directive not defined: \'`STATE_IDLE\'\n state = `STATE_IDLE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n state = `STATE_IDLE;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:67: Define or directive not defined: \'`STATE_FETCH\'\n state = `STATE_FETCH;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n state = `STATE_FETCH;\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:72: Define or directive not defined: \'`STATE_FETCH\'\n `STATE_FETCH: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:72: syntax error, unexpected \':\', expecting endcase\n `STATE_FETCH: begin\n ^\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:73: Define or directive not defined: \'`NOP\'\n if (OPCODE !== `NOP) begin \n ^~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:74: Define or directive not defined: \'`STATE_DECODE\'\n state = `STATE_DECODE;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:80: Define or directive not defined: \'`STATE_DECODE\'\n `STATE_DECODE: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:80: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `STATE_DECODE: begin\n ^~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:81: Define or directive not defined: \'`STATE_EXECUTE\'\n state = `STATE_EXECUTE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:83: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n ALU_OP2 = ((FUNCT === `ALU_FUNCT_WIDTH\'h01) || \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:84: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n (FUNCT === `ALU_FUNCT_WIDTH\'h02)) ? SHAMT : DATA_R2;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:88: Define or directive not defined: \'`STATE_EXECUTE\'\n `STATE_EXECUTE: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:88: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `STATE_EXECUTE: begin\n ^~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:89: Define or directive not defined: \'`STATE_IDLE\'\n state = `STATE_IDLE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/control_unit.v:94: syntax error, unexpected \':\', expecting clocking\n default: ; \n ^\n%Error: Cannot continue\n' | 1,357 | module | module CONTROL_UNIT(OPCODE, FUNCT, SHAMT, DATA_R1, DATA_R2, CLK, RST,
ALU_OP1, ALU_OP2, ALU_CODE, RF_READ, RF_WRITE);
input [`ALU_FUNCT_INDEX_LIMIT:0] OPCODE, FUNCT;
input [4:0] SHAMT;
input [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;
input CLK, RST;
output reg [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;
output reg [`ALU_FUNCT_INDEX_LIMIT:0] ALU_CODE;
output reg RF_READ, RF_WRITE;
reg [1:0] state;
initial begin
state = `STATE_IDLE;
end
always @ (negedge RST or posedge CLK) begin
if (RST === 1'b0) begin
state = `STATE_FETCH;
end
else begin
case (state)
`STATE_FETCH: begin
if (OPCODE !== `NOP) begin
state = `STATE_DECODE;
RF_READ = 1'b1;
RF_WRITE = 1'b0;
end
end
`STATE_DECODE: begin
state = `STATE_EXECUTE;
ALU_OP1 = DATA_R1;
ALU_OP2 = ((FUNCT === `ALU_FUNCT_WIDTH'h01) ||
(FUNCT === `ALU_FUNCT_WIDTH'h02)) ? SHAMT : DATA_R2;
ALU_CODE = FUNCT;
end
`STATE_EXECUTE: begin
state = `STATE_IDLE;
RF_READ = 1'b0;
RF_WRITE = 1'b1;
end
default: ;
endcase
end
end
endmodule | module CONTROL_UNIT(OPCODE, FUNCT, SHAMT, DATA_R1, DATA_R2, CLK, RST,
ALU_OP1, ALU_OP2, ALU_CODE, RF_READ, RF_WRITE); |
input [`ALU_FUNCT_INDEX_LIMIT:0] OPCODE, FUNCT;
input [4:0] SHAMT;
input [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;
input CLK, RST;
output reg [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;
output reg [`ALU_FUNCT_INDEX_LIMIT:0] ALU_CODE;
output reg RF_READ, RF_WRITE;
reg [1:0] state;
initial begin
state = `STATE_IDLE;
end
always @ (negedge RST or posedge CLK) begin
if (RST === 1'b0) begin
state = `STATE_FETCH;
end
else begin
case (state)
`STATE_FETCH: begin
if (OPCODE !== `NOP) begin
state = `STATE_DECODE;
RF_READ = 1'b1;
RF_WRITE = 1'b0;
end
end
`STATE_DECODE: begin
state = `STATE_EXECUTE;
ALU_OP1 = DATA_R1;
ALU_OP2 = ((FUNCT === `ALU_FUNCT_WIDTH'h01) ||
(FUNCT === `ALU_FUNCT_WIDTH'h02)) ? SHAMT : DATA_R2;
ALU_CODE = FUNCT;
end
`STATE_EXECUTE: begin
state = `STATE_IDLE;
RF_READ = 1'b0;
RF_WRITE = 1'b1;
end
default: ;
endcase
end
end
endmodule | 0 |
3,569 | data/full_repos/permissive/105681119/src/miniproc_tb.v | 105,681,119 | miniproc_tb.v | v | 310 | 151 | [] | ['mit license'] | [] | null | line:129: before: ")" | null | 1: b'%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:32: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:36: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:36: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:38: Define or directive not defined: \'`REG_ADDR_INDEX_LIMIT\'\n reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:42: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:42: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:45: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:45: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:46: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:46: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:47: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:47: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:69: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("miniproc_dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:70: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:75: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:75: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:79: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("---------------------------------------------------------------",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:80: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("| if (EXPECTED === ACTUAL) pass; else fail. |",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:81: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("---------------------------------------------------------------",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:89: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h20;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:90: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:90: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:96: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:96: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:105: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h22;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:106: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:106: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:112: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:112: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:121: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h2c;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:122: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:122: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:128: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:128: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:137: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h01;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:138: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:138: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:144: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:144: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:153: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h02;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:154: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:154: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:160: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:160: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:169: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h24;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:170: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:170: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:176: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:176: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,359 | module | module MINIPROC_TB;
reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;
reg [4:0] CU_SHAMT;
reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;
reg CU_RST, RF_RST;
wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;
wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;
wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;
wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;
wire SYS_CLK, rf_read, rf_write;
CLK_GENERATOR cg_inst(.CLK(SYS_CLK));
CONTROL_UNIT cu_inst(.OPCODE(CU_OPCODE), .FUNCT(CU_FUNCT), .SHAMT(CU_SHAMT), .DATA_R1(rf_data_r1), .DATA_R2(rf_data_r2), .CLK(SYS_CLK), .RST(CU_RST),
.ALU_OP1(alu_op1), .ALU_OP2(alu_op2), .ALU_CODE(alu_code), .RF_READ(rf_read), .RF_WRITE(rf_write));
REGISTER_FILE_32x32 rf_inst(.ADDR_R1(RF_ADDR_R1), .ADDR_R2(RF_ADDR_R2), .ADDR_W(RF_ADDR_W), .DATA_W(ALU_RESULT), .READ(rf_read), .WRITE(rf_write),
.CLK(SYS_CLK), .RST(RF_RST), .DATA_R1(rf_data_r1), .DATA_R2(rf_data_r2));
ALU alu_inst(.OP1(alu_op1), .OP2(alu_op2), .FUNCT(alu_code), .RESULT(ALU_RESULT));
integer test = 0, pass = 0, status;
initial begin
$dumpfile("miniproc_dump.vcd");
$dumpvars(0);
CU_RST = 1'b0;
RF_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
RF_RST = 1'b1;
$display("---------------------------------------------------------------",);
$display("| if (EXPECTED === ACTUAL) pass; else fail. |",);
$display("---------------------------------------------------------------",);
CU_OPCODE = 0;
RF_ADDR_W = 31;
RF_ADDR_R1 = 18;
RF_ADDR_R2 = 3;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h20;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 30;
RF_ADDR_R1 = 15;
RF_ADDR_R2 = 5;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h22;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 29;
RF_ADDR_R1 = 12;
RF_ADDR_R2 = 7;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2c;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 28;
RF_ADDR_R1 = 9;
RF_ADDR_R2 = 0;
CU_SHAMT = 2;
CU_FUNCT = `ALU_FUNCT_WIDTH'h01;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 27;
RF_ADDR_R1 = 29;
RF_ADDR_R2 = 0;
CU_SHAMT = 1;
CU_FUNCT = `ALU_FUNCT_WIDTH'h02;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 26;
RF_ADDR_R1 = 31;
RF_ADDR_R2 = 6;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h24;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 25;
RF_ADDR_R1 = 30;
RF_ADDR_R2 = 4;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h25;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 24;
RF_ADDR_R1 = 28;
RF_ADDR_R2 = 27;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h27;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 23;
RF_ADDR_R1 = 26;
RF_ADDR_R2 = 25;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2a;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 22;
RF_ADDR_R1 = 24;
RF_ADDR_R2 = 8;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2a;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
$display("---------------------------------------------------------------",);
$display("| [RESULT] %2d out of %2d. |", pass, test);
$display("---------------------------------------------------------------",);
$finish;
end
task test_counter;
inout test, pass, status;
integer test, pass;
begin
test = test + 1;
if (status) begin
pass = pass + 1;
end
end
endtask
function test_result;
input [`DATA_INDEX_LIMIT:0] op1, op2;
input [`ALU_FUNCT_INDEX_LIMIT:0] funct;
input [`DATA_INDEX_LIMIT:0] actual;
reg [`DATA_INDEX_LIMIT:0] exp;
reg [2*8:0] opr;
begin
case (funct)
`ALU_FUNCT_WIDTH'h20 : begin opr = "+"; exp = op1 + op2; end
`ALU_FUNCT_WIDTH'h22 : begin opr = "-"; exp = op1 - op2; end
`ALU_FUNCT_WIDTH'h2c : begin opr = "*"; exp = op1 * op2; end
`ALU_FUNCT_WIDTH'h01 : begin opr = "<<"; exp = op1 << op2; end
`ALU_FUNCT_WIDTH'h02 : begin opr = ">>"; exp = op1 >> op2; end
`ALU_FUNCT_WIDTH'h24 : begin opr = "&"; exp = op1 & op2; end
`ALU_FUNCT_WIDTH'h25 : begin opr = "|"; exp = op1 | op2; end
`ALU_FUNCT_WIDTH'h27 : begin opr = "~|"; exp = ~(op1 | op2); end
`ALU_FUNCT_WIDTH'h2a : begin opr = "<"; exp = op1 < op2; end
default: begin opr = "?"; exp = `DATA_WIDTH'hx; end
endcase
if (exp === actual) begin
$write(" [PASS] ");
test_result = 1'b1;
end
else begin
$write(" [FAIL] ");
test_result = 1'b0;
end
$display("%d %2s %-d EXPECTED = %2d, ACTUAL = %2d", op1, opr, op2, exp, actual);
end
endfunction
endmodule | module MINIPROC_TB; |
reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;
reg [4:0] CU_SHAMT;
reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;
reg CU_RST, RF_RST;
wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;
wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;
wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;
wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;
wire SYS_CLK, rf_read, rf_write;
CLK_GENERATOR cg_inst(.CLK(SYS_CLK));
CONTROL_UNIT cu_inst(.OPCODE(CU_OPCODE), .FUNCT(CU_FUNCT), .SHAMT(CU_SHAMT), .DATA_R1(rf_data_r1), .DATA_R2(rf_data_r2), .CLK(SYS_CLK), .RST(CU_RST),
.ALU_OP1(alu_op1), .ALU_OP2(alu_op2), .ALU_CODE(alu_code), .RF_READ(rf_read), .RF_WRITE(rf_write));
REGISTER_FILE_32x32 rf_inst(.ADDR_R1(RF_ADDR_R1), .ADDR_R2(RF_ADDR_R2), .ADDR_W(RF_ADDR_W), .DATA_W(ALU_RESULT), .READ(rf_read), .WRITE(rf_write),
.CLK(SYS_CLK), .RST(RF_RST), .DATA_R1(rf_data_r1), .DATA_R2(rf_data_r2));
ALU alu_inst(.OP1(alu_op1), .OP2(alu_op2), .FUNCT(alu_code), .RESULT(ALU_RESULT));
integer test = 0, pass = 0, status;
initial begin
$dumpfile("miniproc_dump.vcd");
$dumpvars(0);
CU_RST = 1'b0;
RF_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
RF_RST = 1'b1;
$display("---------------------------------------------------------------",);
$display("| if (EXPECTED === ACTUAL) pass; else fail. |",);
$display("---------------------------------------------------------------",);
CU_OPCODE = 0;
RF_ADDR_W = 31;
RF_ADDR_R1 = 18;
RF_ADDR_R2 = 3;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h20;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 30;
RF_ADDR_R1 = 15;
RF_ADDR_R2 = 5;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h22;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 29;
RF_ADDR_R1 = 12;
RF_ADDR_R2 = 7;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2c;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 28;
RF_ADDR_R1 = 9;
RF_ADDR_R2 = 0;
CU_SHAMT = 2;
CU_FUNCT = `ALU_FUNCT_WIDTH'h01;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 27;
RF_ADDR_R1 = 29;
RF_ADDR_R2 = 0;
CU_SHAMT = 1;
CU_FUNCT = `ALU_FUNCT_WIDTH'h02;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 26;
RF_ADDR_R1 = 31;
RF_ADDR_R2 = 6;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h24;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 25;
RF_ADDR_R1 = 30;
RF_ADDR_R2 = 4;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h25;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 24;
RF_ADDR_R1 = 28;
RF_ADDR_R2 = 27;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h27;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 23;
RF_ADDR_R1 = 26;
RF_ADDR_R2 = 25;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2a;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
CU_RST = 1'b0;
#`SYS_CLK_PERIOD;
CU_RST = 1'b1;
CU_OPCODE = 0;
RF_ADDR_W = 22;
RF_ADDR_R1 = 24;
RF_ADDR_R2 = 8;
CU_SHAMT = 0;
CU_FUNCT = `ALU_FUNCT_WIDTH'h2a;
#`CU_CLK_PERIOD;
status = test_result(alu_op1, alu_op2, alu_code, ALU_RESULT);
test_counter(test, pass, status);
$display("---------------------------------------------------------------",);
$display("| [RESULT] %2d out of %2d. |", pass, test);
$display("---------------------------------------------------------------",);
$finish;
end
task test_counter;
inout test, pass, status;
integer test, pass;
begin
test = test + 1;
if (status) begin
pass = pass + 1;
end
end
endtask
function test_result;
input [`DATA_INDEX_LIMIT:0] op1, op2;
input [`ALU_FUNCT_INDEX_LIMIT:0] funct;
input [`DATA_INDEX_LIMIT:0] actual;
reg [`DATA_INDEX_LIMIT:0] exp;
reg [2*8:0] opr;
begin
case (funct)
`ALU_FUNCT_WIDTH'h20 : begin opr = "+"; exp = op1 + op2; end
`ALU_FUNCT_WIDTH'h22 : begin opr = "-"; exp = op1 - op2; end
`ALU_FUNCT_WIDTH'h2c : begin opr = "*"; exp = op1 * op2; end
`ALU_FUNCT_WIDTH'h01 : begin opr = "<<"; exp = op1 << op2; end
`ALU_FUNCT_WIDTH'h02 : begin opr = ">>"; exp = op1 >> op2; end
`ALU_FUNCT_WIDTH'h24 : begin opr = "&"; exp = op1 & op2; end
`ALU_FUNCT_WIDTH'h25 : begin opr = "|"; exp = op1 | op2; end
`ALU_FUNCT_WIDTH'h27 : begin opr = "~|"; exp = ~(op1 | op2); end
`ALU_FUNCT_WIDTH'h2a : begin opr = "<"; exp = op1 < op2; end
default: begin opr = "?"; exp = `DATA_WIDTH'hx; end
endcase
if (exp === actual) begin
$write(" [PASS] ");
test_result = 1'b1;
end
else begin
$write(" [FAIL] ");
test_result = 1'b0;
end
$display("%d %2s %-d EXPECTED = %2d, ACTUAL = %2d", op1, opr, op2, exp, actual);
end
endfunction
endmodule | 0 |
3,570 | data/full_repos/permissive/105681119/src/miniproc_tb.v | 105,681,119 | miniproc_tb.v | v | 310 | 151 | [] | ['mit license'] | [] | null | line:129: before: ")" | null | 1: b'%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:32: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:36: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:36: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`ALU_FUNCT_INDEX_LIMIT:0] CU_OPCODE, CU_FUNCT;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:38: Define or directive not defined: \'`REG_ADDR_INDEX_LIMIT\'\n reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`REG_ADDR_INDEX_LIMIT:0] RF_ADDR_R1, RF_ADDR_R2, RF_ADDR_W;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:42: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:42: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] ALU_RESULT;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:45: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:45: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] alu_op1, alu_op2;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:46: Define or directive not defined: \'`ALU_FUNCT_INDEX_LIMIT\'\n wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:46: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`ALU_FUNCT_INDEX_LIMIT:0] alu_code;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:47: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:47: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`DATA_INDEX_LIMIT:0] rf_data_r1, rf_data_r2;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:69: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("miniproc_dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:70: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:75: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:75: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:79: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("---------------------------------------------------------------",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:80: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("| if (EXPECTED === ACTUAL) pass; else fail. |",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:81: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("---------------------------------------------------------------",);\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:89: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h20;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:90: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:90: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:96: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:96: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:105: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h22;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:106: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:106: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:112: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:112: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:121: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h2c;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:122: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:122: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:128: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:128: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:137: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h01;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:138: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:138: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:144: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:144: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:153: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h02;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:154: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:154: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:160: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:160: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:169: Define or directive not defined: \'`ALU_FUNCT_WIDTH\'\n CU_FUNCT = `ALU_FUNCT_WIDTH\'h24;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:170: Define or directive not defined: \'`CU_CLK_PERIOD\'\n #`CU_CLK_PERIOD; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:170: syntax error, unexpected \';\', expecting IDENTIFIER\n #`CU_CLK_PERIOD; \n ^\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:176: Define or directive not defined: \'`SYS_CLK_PERIOD\'\n #`SYS_CLK_PERIOD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/miniproc_tb.v:176: syntax error, unexpected \';\', expecting IDENTIFIER\n #`SYS_CLK_PERIOD;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,359 | function | function test_result;
input [`DATA_INDEX_LIMIT:0] op1, op2;
input [`ALU_FUNCT_INDEX_LIMIT:0] funct;
input [`DATA_INDEX_LIMIT:0] actual;
reg [`DATA_INDEX_LIMIT:0] exp;
reg [2*8:0] opr;
begin
case (funct)
`ALU_FUNCT_WIDTH'h20 : begin opr = "+"; exp = op1 + op2; end
`ALU_FUNCT_WIDTH'h22 : begin opr = "-"; exp = op1 - op2; end
`ALU_FUNCT_WIDTH'h2c : begin opr = "*"; exp = op1 * op2; end
`ALU_FUNCT_WIDTH'h01 : begin opr = "<<"; exp = op1 << op2; end
`ALU_FUNCT_WIDTH'h02 : begin opr = ">>"; exp = op1 >> op2; end
`ALU_FUNCT_WIDTH'h24 : begin opr = "&"; exp = op1 & op2; end
`ALU_FUNCT_WIDTH'h25 : begin opr = "|"; exp = op1 | op2; end
`ALU_FUNCT_WIDTH'h27 : begin opr = "~|"; exp = ~(op1 | op2); end
`ALU_FUNCT_WIDTH'h2a : begin opr = "<"; exp = op1 < op2; end
default: begin opr = "?"; exp = `DATA_WIDTH'hx; end
endcase
if (exp === actual) begin
$write(" [PASS] ");
test_result = 1'b1;
end
else begin
$write(" [FAIL] ");
test_result = 1'b0;
end
$display("%d %2s %-d EXPECTED = %2d, ACTUAL = %2d", op1, opr, op2, exp, actual);
end
endfunction | function test_result; |
input [`DATA_INDEX_LIMIT:0] op1, op2;
input [`ALU_FUNCT_INDEX_LIMIT:0] funct;
input [`DATA_INDEX_LIMIT:0] actual;
reg [`DATA_INDEX_LIMIT:0] exp;
reg [2*8:0] opr;
begin
case (funct)
`ALU_FUNCT_WIDTH'h20 : begin opr = "+"; exp = op1 + op2; end
`ALU_FUNCT_WIDTH'h22 : begin opr = "-"; exp = op1 - op2; end
`ALU_FUNCT_WIDTH'h2c : begin opr = "*"; exp = op1 * op2; end
`ALU_FUNCT_WIDTH'h01 : begin opr = "<<"; exp = op1 << op2; end
`ALU_FUNCT_WIDTH'h02 : begin opr = ">>"; exp = op1 >> op2; end
`ALU_FUNCT_WIDTH'h24 : begin opr = "&"; exp = op1 & op2; end
`ALU_FUNCT_WIDTH'h25 : begin opr = "|"; exp = op1 | op2; end
`ALU_FUNCT_WIDTH'h27 : begin opr = "~|"; exp = ~(op1 | op2); end
`ALU_FUNCT_WIDTH'h2a : begin opr = "<"; exp = op1 < op2; end
default: begin opr = "?"; exp = `DATA_WIDTH'hx; end
endcase
if (exp === actual) begin
$write(" [PASS] ");
test_result = 1'b1;
end
else begin
$write(" [FAIL] ");
test_result = 1'b0;
end
$display("%d %2s %-d EXPECTED = %2d, ACTUAL = %2d", op1, opr, op2, exp, actual);
end
endfunction | 0 |
3,571 | data/full_repos/permissive/105681119/src/register_file.v | 105,681,119 | register_file.v | v | 85 | 100 | [] | ['mit license'] | [] | [(97, 135)] | null | null | 1: b'%Error: data/full_repos/permissive/105681119/src/register_file.v:45: Cannot find include file: definition.v\n`include "definition.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n definition.v\n definition.v.v\n definition.v.sv\n obj_dir/definition.v\n obj_dir/definition.v.v\n obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/register_file.v:50: Define or directive not defined: \'`REG_ADDR_INDEX_LIMIT\'\n input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:50: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:51: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n input [`DATA_INDEX_LIMIT:0] DATA_W;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:51: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`DATA_INDEX_LIMIT:0] DATA_W;\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:55: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:55: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: Define or directive not defined: \'`REG_INDEX_LIMIT\'\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: Define or directive not defined: \'`NUM_OF_REG\'\n for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:68: syntax error, unexpected else\n else begin \n ^~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:80: Define or directive not defined: \'`DATA_WIDTH\'\n DATA_R1 = { `DATA_WIDTH{1\'bx} };\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:81: Define or directive not defined: \'`DATA_WIDTH\'\n DATA_R2 = { `DATA_WIDTH{1\'bx} };\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 1,360 | module | module REGISTER_FILE_32x32(ADDR_R1, ADDR_R2, ADDR_W, DATA_W, READ, WRITE,
CLK, RST, DATA_R1, DATA_R2);
input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
input [`DATA_INDEX_LIMIT:0] DATA_W;
input READ, WRITE, CLK, RST;
output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;
reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];
integer i;
always @ (negedge RST or posedge CLK) begin
if (RST === 1'b0) begin
for (i = 0; i < `NUM_OF_REG; i = i + 1) begin
reg32x32[i] = i;
end
end
else begin
if ((READ === 1'b0) && (WRITE === 1'b1)) begin
reg32x32[ADDR_W] = DATA_W;
end
else if ((READ === 1'b1) && (WRITE === 1'b0)) begin
DATA_R1 = reg32x32[ADDR_R1];
DATA_R2 = reg32x32[ADDR_R2];
end
else begin
DATA_R1 = { `DATA_WIDTH{1'bx} };
DATA_R2 = { `DATA_WIDTH{1'bx} };
end
end
end
endmodule | module REGISTER_FILE_32x32(ADDR_R1, ADDR_R2, ADDR_W, DATA_W, READ, WRITE,
CLK, RST, DATA_R1, DATA_R2); |
input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
input [`DATA_INDEX_LIMIT:0] DATA_W;
input READ, WRITE, CLK, RST;
output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;
reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];
integer i;
always @ (negedge RST or posedge CLK) begin
if (RST === 1'b0) begin
for (i = 0; i < `NUM_OF_REG; i = i + 1) begin
reg32x32[i] = i;
end
end
else begin
if ((READ === 1'b0) && (WRITE === 1'b1)) begin
reg32x32[ADDR_W] = DATA_W;
end
else if ((READ === 1'b1) && (WRITE === 1'b0)) begin
DATA_R1 = reg32x32[ADDR_R1];
DATA_R2 = reg32x32[ADDR_R2];
end
else begin
DATA_R1 = { `DATA_WIDTH{1'bx} };
DATA_R2 = { `DATA_WIDTH{1'bx} };
end
end
end
endmodule | 0 |
3,572 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module lab7(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
input [1:0] KEY,
output reg [9:0] LEDR,
input [9:0] SW
);
wire [31:0] value;
wire rst, sample, start;
wire [1:0] debug;
wire [7:0] is_prime, done;
wire [7:0] write_data_orig, write_data_prime, read_data_orig, read_data_prime;
wire write_enable_orig, write_enable_prime;
wire [1:0] write_addr_orig, write_addr_prime, read_addr_orig, read_addr_prime, read_addr;
wire c0_sig, c1_sig, clk;
reg [31:0] count, count_c;
reg [31:0] orig_val, orig_val_c;
reg [31:0] prime_val, prime_val_c;
reg [2:0] state, state_c;
reg LED_prime, LED_prime_c;
reg LED_done, LED_done_c;
reg startTest;
wire [7:0] count_prime;
wire reset_prime_tester;
wire dividend = count;
wire data_sel;
wire key1_start;
parameter WAIT = 3'b000;
parameter CLK_WAIT_1 = 3'b001;
parameter TEST_ORIGINAL = 3'b010;
parameter CHECK_ORIGINAL = 3'b011;
parameter CLK_WAIT_2 = 3'b100;
parameter CLK_WAIT_3 = 3'b101;
parameter TEST_NEXT = 3'b110;
parameter CHECK_NEXT = 3'b111;
pll pll_inst (
.inclk0 ( MAX10_CLK1_50 ),
.c0 ( clk ),
.c1 ( c1_sig )
);
synchronizer s1(.clk(clk), .in(SW[9]), .out(rst));
synchronizer s2(.clk(clk), .in(KEY[1]), .out(key1_start));
synchronizer s3(.clk(clk), .in(KEY[0]), .out(sample));
synchronizer s4(.clk(clk), .in(SW[4]), .out(data_sel));
synchronizer s5(.clk(clk), .in(SW[3]), .out(read_addr[1]));
synchronizer s6(.clk(clk), .in(SW[2]), .out(read_addr[0]));
synchronizer s7(.clk(clk), .in(SW[1]), .out(debug[1]));
synchronizer s8(.clk(clk), .in(SW[0]), .out(debug[0]));
number_generator gen(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
prime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32'd2), .end_val((count >> 4)));
prime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2'd2));
prime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2'd2), .end_val((count >> 4) * 2'd3));
prime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2'd3), .end_val((count >> 4) * 3'd4));
prime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3'd4), .end_val((count >> 4) * 3'd5));
prime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3'd5), .end_val((count >> 4) * 3'd6));
prime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3'd6), .end_val((count >> 4) * 3'd7));
prime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3'd7), .end_val((count >> 1) + 1'b1));
edge_detector_falling state_detector_falling(.clk(clk), .input_signal(key1_start), .falling_transition(start));
always @(*) begin
count_c = count;
state_c = state;
LED_prime_c = LED_prime;
LED_done_c = LED_done;
orig_val_c = orig_val;
prime_val_c = prime_val;
LEDR[1] = LED_done;
LEDR[0] = LED_prime;
LEDR[9:2] = done;
case (state)
WAIT: begin
startTest = 1'b1;
if (start == 1'b1) begin
state_c = CLK_WAIT_1;
count_c = value;
LED_done_c = 1'b0;
LED_prime_c = 1'b0;
startTest = 1'b0;
orig_val_c = value;
prime_val_c = 32'd0;
end
end
CLK_WAIT_1: begin
startTest = 1'b0;
state_c = TEST_ORIGINAL;
orig_val_c = value;
end
TEST_ORIGINAL: begin
startTest = 1'b1;
if (done == 8'b11111111) begin
state_c = CHECK_ORIGINAL;
end
end
CHECK_ORIGINAL: begin
startTest = 1'b1;
if (is_prime == 8'b11111111) begin
state_c = WAIT;
LED_done_c = 1'b1;
LED_prime_c = 1'b1;
prime_val_c = value;
orig_val_c = value;
end
else begin
count_c = count + 32'b1;
state_c = CLK_WAIT_2;
orig_val_c = value;
end
end
CLK_WAIT_2: begin
startTest = 1'b0;
state_c = CLK_WAIT_3;
end
CLK_WAIT_3: begin
startTest = 1'b0;
state_c = TEST_NEXT;
end
TEST_NEXT: begin
state_c = TEST_NEXT;
startTest = 1'b1;
if(done == 8'b11111111) begin
state_c = CHECK_NEXT;
end
end
CHECK_NEXT: begin
startTest = 1'b1;
if (is_prime == 8'b11111111) begin
state_c = WAIT;
LED_done_c = 1'b1;
prime_val_c = count;
end
else begin
state_c = CLK_WAIT_2;
count_c = count + 32'b1;
startTest = 1'b0;
end
end
endcase
if (rst == 1'b1) begin
count_c = 32'b0;
state_c = WAIT;
LED_prime_c = 1'b0;
LED_done_c = 1'b0;
orig_val_c = 32'b0;
prime_val_c = 32'b0;
end
end
always @(posedge clk) begin
state <= #1 state_c;
count <= #1 count_c;
LED_done <= #1 LED_done_c;
LED_prime <= #1 LED_prime_c;
prime_val <= #1 prime_val_c;
orig_val <= #1 orig_val_c;
end
serializer ser_orig(.clk(clk), .rst(rst), .save(LED_done), .data_in(orig_val), .write_data(write_data_orig), .write_enable(write_enable_orig), .write_addr(write_addr_orig));
serializer ser_prime(.clk(clk), .rst(rst), .save(LED_done), .data_in(prime_val), .write_data(write_data_prime), .write_enable(write_enable_prime), .write_addr(write_addr_prime));
output_ram ram_orig(.clk(clk), .write_data(write_data_orig), .write_enable(write_enable_orig), .write_addr(write_addr_orig), .read_addr(read_addr_orig), .read_data(read_data_orig));
output_ram ram_prime(.clk(clk), .write_data(write_data_prime), .write_enable(write_enable_prime), .write_addr(write_addr_prime), .read_addr(read_addr_prime), .read_data(read_data_prime));
assign read_addr_orig = read_addr;
assign read_addr_prime = read_addr;
byte2_7seg b_orig(.data_sel(data_sel), .in_orig(read_data_orig), .in_prime(read_data_prime), .hex0out(HEX0), .hex1out(HEX1));
assign HEX2 = 8'b11111111;
assign HEX3 = 8'b11111111;
assign HEX4 = 8'b11111111;
assign HEX5 = 8'b11111111;
endmodule | module lab7(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
input [1:0] KEY,
output reg [9:0] LEDR,
input [9:0] SW
); |
wire [31:0] value;
wire rst, sample, start;
wire [1:0] debug;
wire [7:0] is_prime, done;
wire [7:0] write_data_orig, write_data_prime, read_data_orig, read_data_prime;
wire write_enable_orig, write_enable_prime;
wire [1:0] write_addr_orig, write_addr_prime, read_addr_orig, read_addr_prime, read_addr;
wire c0_sig, c1_sig, clk;
reg [31:0] count, count_c;
reg [31:0] orig_val, orig_val_c;
reg [31:0] prime_val, prime_val_c;
reg [2:0] state, state_c;
reg LED_prime, LED_prime_c;
reg LED_done, LED_done_c;
reg startTest;
wire [7:0] count_prime;
wire reset_prime_tester;
wire dividend = count;
wire data_sel;
wire key1_start;
parameter WAIT = 3'b000;
parameter CLK_WAIT_1 = 3'b001;
parameter TEST_ORIGINAL = 3'b010;
parameter CHECK_ORIGINAL = 3'b011;
parameter CLK_WAIT_2 = 3'b100;
parameter CLK_WAIT_3 = 3'b101;
parameter TEST_NEXT = 3'b110;
parameter CHECK_NEXT = 3'b111;
pll pll_inst (
.inclk0 ( MAX10_CLK1_50 ),
.c0 ( clk ),
.c1 ( c1_sig )
);
synchronizer s1(.clk(clk), .in(SW[9]), .out(rst));
synchronizer s2(.clk(clk), .in(KEY[1]), .out(key1_start));
synchronizer s3(.clk(clk), .in(KEY[0]), .out(sample));
synchronizer s4(.clk(clk), .in(SW[4]), .out(data_sel));
synchronizer s5(.clk(clk), .in(SW[3]), .out(read_addr[1]));
synchronizer s6(.clk(clk), .in(SW[2]), .out(read_addr[0]));
synchronizer s7(.clk(clk), .in(SW[1]), .out(debug[1]));
synchronizer s8(.clk(clk), .in(SW[0]), .out(debug[0]));
number_generator gen(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
prime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32'd2), .end_val((count >> 4)));
prime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2'd2));
prime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2'd2), .end_val((count >> 4) * 2'd3));
prime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2'd3), .end_val((count >> 4) * 3'd4));
prime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3'd4), .end_val((count >> 4) * 3'd5));
prime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3'd5), .end_val((count >> 4) * 3'd6));
prime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3'd6), .end_val((count >> 4) * 3'd7));
prime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3'd7), .end_val((count >> 1) + 1'b1));
edge_detector_falling state_detector_falling(.clk(clk), .input_signal(key1_start), .falling_transition(start));
always @(*) begin
count_c = count;
state_c = state;
LED_prime_c = LED_prime;
LED_done_c = LED_done;
orig_val_c = orig_val;
prime_val_c = prime_val;
LEDR[1] = LED_done;
LEDR[0] = LED_prime;
LEDR[9:2] = done;
case (state)
WAIT: begin
startTest = 1'b1;
if (start == 1'b1) begin
state_c = CLK_WAIT_1;
count_c = value;
LED_done_c = 1'b0;
LED_prime_c = 1'b0;
startTest = 1'b0;
orig_val_c = value;
prime_val_c = 32'd0;
end
end
CLK_WAIT_1: begin
startTest = 1'b0;
state_c = TEST_ORIGINAL;
orig_val_c = value;
end
TEST_ORIGINAL: begin
startTest = 1'b1;
if (done == 8'b11111111) begin
state_c = CHECK_ORIGINAL;
end
end
CHECK_ORIGINAL: begin
startTest = 1'b1;
if (is_prime == 8'b11111111) begin
state_c = WAIT;
LED_done_c = 1'b1;
LED_prime_c = 1'b1;
prime_val_c = value;
orig_val_c = value;
end
else begin
count_c = count + 32'b1;
state_c = CLK_WAIT_2;
orig_val_c = value;
end
end
CLK_WAIT_2: begin
startTest = 1'b0;
state_c = CLK_WAIT_3;
end
CLK_WAIT_3: begin
startTest = 1'b0;
state_c = TEST_NEXT;
end
TEST_NEXT: begin
state_c = TEST_NEXT;
startTest = 1'b1;
if(done == 8'b11111111) begin
state_c = CHECK_NEXT;
end
end
CHECK_NEXT: begin
startTest = 1'b1;
if (is_prime == 8'b11111111) begin
state_c = WAIT;
LED_done_c = 1'b1;
prime_val_c = count;
end
else begin
state_c = CLK_WAIT_2;
count_c = count + 32'b1;
startTest = 1'b0;
end
end
endcase
if (rst == 1'b1) begin
count_c = 32'b0;
state_c = WAIT;
LED_prime_c = 1'b0;
LED_done_c = 1'b0;
orig_val_c = 32'b0;
prime_val_c = 32'b0;
end
end
always @(posedge clk) begin
state <= #1 state_c;
count <= #1 count_c;
LED_done <= #1 LED_done_c;
LED_prime <= #1 LED_prime_c;
prime_val <= #1 prime_val_c;
orig_val <= #1 orig_val_c;
end
serializer ser_orig(.clk(clk), .rst(rst), .save(LED_done), .data_in(orig_val), .write_data(write_data_orig), .write_enable(write_enable_orig), .write_addr(write_addr_orig));
serializer ser_prime(.clk(clk), .rst(rst), .save(LED_done), .data_in(prime_val), .write_data(write_data_prime), .write_enable(write_enable_prime), .write_addr(write_addr_prime));
output_ram ram_orig(.clk(clk), .write_data(write_data_orig), .write_enable(write_enable_orig), .write_addr(write_addr_orig), .read_addr(read_addr_orig), .read_data(read_data_orig));
output_ram ram_prime(.clk(clk), .write_data(write_data_prime), .write_enable(write_enable_prime), .write_addr(write_addr_prime), .read_addr(read_addr_prime), .read_data(read_data_prime));
assign read_addr_orig = read_addr;
assign read_addr_prime = read_addr;
byte2_7seg b_orig(.data_sel(data_sel), .in_orig(read_data_orig), .in_prime(read_data_prime), .hex0out(HEX0), .hex1out(HEX1));
assign HEX2 = 8'b11111111;
assign HEX3 = 8'b11111111;
assign HEX4 = 8'b11111111;
assign HEX5 = 8'b11111111;
endmodule | 0 |
3,573 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module byte2_7seg(data_sel, in_orig, in_prime, hex0out, hex1out);
input [7:0] in_orig, in_prime;
output [7:0] hex0out, hex1out;
wire [7:0] display;
input data_sel;
assign display = data_sel ? in_prime : in_orig;
hex_2_7_seg m1(.in(display[7:4]), .out(hex1out));
hex_2_7_seg m2(.in(display[3:0]), .out(hex0out));
endmodule | module byte2_7seg(data_sel, in_orig, in_prime, hex0out, hex1out); |
input [7:0] in_orig, in_prime;
output [7:0] hex0out, hex1out;
wire [7:0] display;
input data_sel;
assign display = data_sel ? in_prime : in_orig;
hex_2_7_seg m1(.in(display[7:4]), .out(hex1out));
hex_2_7_seg m2(.in(display[3:0]), .out(hex0out));
endmodule | 0 |
3,574 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module hex_2_7_seg(in, out);
input [3:0] in;
output reg [7:0] out;
parameter ZERO = 8'b1100_0000;
parameter ONE = 8'b1111_1001;
parameter TWO = 8'b1010_0100;
parameter THREE = 8'b1011_0000;
parameter FOUR = 8'b1001_1001;
parameter FIVE = 8'b1001_0010;
parameter SIX = 8'b1000_0010;
parameter SEVEN = 8'b1111_1000;
parameter EIGHT = 8'b1000_0000;
parameter NINE = 8'b1001_1000;
parameter A = 8'b1000_1000;
parameter B = 8'b1000_0011;
parameter C = 8'b1100_0110;
parameter D = 8'b1010_0001;
parameter E = 8'b1000_0110;
parameter F = 8'b1000_1110;
always @(*) begin
case (in)
0: out = ZERO;
1: out = ONE;
2: out = TWO;
3: out = THREE;
4: out = FOUR;
5: out = FIVE;
6: out = SIX;
7: out = SEVEN;
8: out = EIGHT;
9: out = NINE;
10: out = A;
11: out = B;
12: out = C;
13: out = D;
14: out = E;
15: out = F;
endcase
end
endmodule | module hex_2_7_seg(in, out); |
input [3:0] in;
output reg [7:0] out;
parameter ZERO = 8'b1100_0000;
parameter ONE = 8'b1111_1001;
parameter TWO = 8'b1010_0100;
parameter THREE = 8'b1011_0000;
parameter FOUR = 8'b1001_1001;
parameter FIVE = 8'b1001_0010;
parameter SIX = 8'b1000_0010;
parameter SEVEN = 8'b1111_1000;
parameter EIGHT = 8'b1000_0000;
parameter NINE = 8'b1001_1000;
parameter A = 8'b1000_1000;
parameter B = 8'b1000_0011;
parameter C = 8'b1100_0110;
parameter D = 8'b1010_0001;
parameter E = 8'b1000_0110;
parameter F = 8'b1000_1110;
always @(*) begin
case (in)
0: out = ZERO;
1: out = ONE;
2: out = TWO;
3: out = THREE;
4: out = FOUR;
5: out = FIVE;
6: out = SIX;
7: out = SEVEN;
8: out = EIGHT;
9: out = NINE;
10: out = A;
11: out = B;
12: out = C;
13: out = D;
14: out = E;
15: out = F;
endcase
end
endmodule | 0 |
3,575 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module output_ram(clk, write_data, write_enable, write_addr, read_addr, read_data);
input [7:0] write_data;
input write_enable, clk;
input [1:0] write_addr;
input [1:0] read_addr;
output [7:0] read_data;
reg [7:0] Mem [0:3];
always @(posedge clk) begin
if (write_enable == 1'b1) begin
Mem[write_addr] <= #1 write_data;
end
end
assign read_data = Mem[read_addr];
endmodule | module output_ram(clk, write_data, write_enable, write_addr, read_addr, read_data); |
input [7:0] write_data;
input write_enable, clk;
input [1:0] write_addr;
input [1:0] read_addr;
output [7:0] read_data;
reg [7:0] Mem [0:3];
always @(posedge clk) begin
if (write_enable == 1'b1) begin
Mem[write_addr] <= #1 write_data;
end
end
assign read_data = Mem[read_addr];
endmodule | 0 |
3,576 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module serializer(clk, rst, save, data_in, write_data, write_enable, write_addr);
input save, clk, rst;
input [31:0] data_in;
output reg [7:0] write_data;
output reg write_enable;
output reg [1:0] write_addr;
wire rising_transition;
parameter WAIT = 3'b000;
parameter ADDR1 = 3'b001;
parameter ADDR2 = 3'b010;
parameter ADDR3 = 3'b011;
parameter ADDR4 = 3'b100;
reg [2:0] state, state_c;
edge_detector_rising test(.clk(clk), .input_signal(save), .rising_transition(rising_transition));
always @(*) begin
state_c = state;
case (state)
WAIT: begin
write_enable = 1'b0;
if (rising_transition == 1'b1) begin
state_c = ADDR1;
end
end
ADDR1: begin
write_enable = 1'b1;
write_addr = 2'b00;
write_data = data_in[7:0];
state_c = ADDR2;
end
ADDR2: begin
write_enable = 1'b1;
write_addr = 2'b01;
write_data = data_in[15:8];
state_c = ADDR3;
end
ADDR3: begin
write_enable = 1'b1;
write_addr = 2'b10;
write_data = data_in[23:16];
state_c = ADDR4;
end
ADDR4: begin
write_enable = 1'b1;
write_addr = 2'b11;
write_data = data_in[31:24];
state_c = WAIT;
end
endcase
if (rst == 1'b1) begin
state_c = WAIT;
end
end
always @(posedge clk) begin
state <= #1 state_c;
end
endmodule | module serializer(clk, rst, save, data_in, write_data, write_enable, write_addr); |
input save, clk, rst;
input [31:0] data_in;
output reg [7:0] write_data;
output reg write_enable;
output reg [1:0] write_addr;
wire rising_transition;
parameter WAIT = 3'b000;
parameter ADDR1 = 3'b001;
parameter ADDR2 = 3'b010;
parameter ADDR3 = 3'b011;
parameter ADDR4 = 3'b100;
reg [2:0] state, state_c;
edge_detector_rising test(.clk(clk), .input_signal(save), .rising_transition(rising_transition));
always @(*) begin
state_c = state;
case (state)
WAIT: begin
write_enable = 1'b0;
if (rising_transition == 1'b1) begin
state_c = ADDR1;
end
end
ADDR1: begin
write_enable = 1'b1;
write_addr = 2'b00;
write_data = data_in[7:0];
state_c = ADDR2;
end
ADDR2: begin
write_enable = 1'b1;
write_addr = 2'b01;
write_data = data_in[15:8];
state_c = ADDR3;
end
ADDR3: begin
write_enable = 1'b1;
write_addr = 2'b10;
write_data = data_in[23:16];
state_c = ADDR4;
end
ADDR4: begin
write_enable = 1'b1;
write_addr = 2'b11;
write_data = data_in[31:24];
state_c = WAIT;
end
endcase
if (rst == 1'b1) begin
state_c = WAIT;
end
end
always @(posedge clk) begin
state <= #1 state_c;
end
endmodule | 0 |
3,577 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module synchronizer(clk, in, out);
input clk, in;
output reg out;
reg ff1, ff1_c, ff2, ff2_c, ff3, ff3_c;
always @(*) begin
ff1_c = in;
ff2_c = ff1;
ff3_c = ff2;
out = ff3;
end
always @(posedge clk) begin
ff1 <= #1 ff1_c;
ff2 <= #1 ff2_c;
ff3 <= #1 ff3_c;
end
endmodule | module synchronizer(clk, in, out); |
input clk, in;
output reg out;
reg ff1, ff1_c, ff2, ff2_c, ff3, ff3_c;
always @(*) begin
ff1_c = in;
ff2_c = ff1;
ff3_c = ff2;
out = ff3;
end
always @(posedge clk) begin
ff1 <= #1 ff1_c;
ff2 <= #1 ff2_c;
ff3 <= #1 ff3_c;
end
endmodule | 0 |
3,578 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module prime_tester(clk, rst, dividend, start, done, is_prime, count, start_val, end_val, rem0);
input [31:0] dividend;
input start, clk, rst;
input [31:0] start_val, end_val;
output reg done, is_prime;
reg done_c, is_prime_c;
output reg [32:0] count;
reg [32:0] count_c;
wire [32:0] endValConcat = {1'b0, end_val};
wire [32:0] startValConcat = {1'b0, start_val};
wire falling_transition;
reg run, run_c;
reg clear;
edge_detector_falling edge_detector_falling2(.clk(clk), .input_signal(start), .falling_transition(falling_transition));
wire [23:0] remainder_done;
wire [31:0] rem;
reg [31:0] remainder;
wire [31:0] remainder_c;
output [23:0] rem0;
remainder_test test0(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0]), .done(remainder_done[0]), .rem0(rem0[0]));
remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd2), .done(remainder_done[1]), .rem0(rem0[1]));
remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd4), .done(remainder_done[2]), .rem0(rem0[2]));
remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd6), .done(remainder_done[3]), .rem0(rem0[3]));
remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd8), .done(remainder_done[4]), .rem0(rem0[4]));
remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd10), .done(remainder_done[5]), .rem0(rem0[5]));
remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd12), .done(remainder_done[6]), .rem0(rem0[6]));
remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd14), .done(remainder_done[7]), .rem0(rem0[7]));
remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd16), .done(remainder_done[8]), .rem0(rem0[8]));
remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd18), .done(remainder_done[9]), .rem0(rem0[9]));
remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd20), .done(remainder_done[10]), .rem0(rem0[10]));
remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd22), .done(remainder_done[11]), .rem0(rem0[11]));
remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd24), .done(remainder_done[12]), .rem0(rem0[12]));
remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd26), .done(remainder_done[13]), .rem0(rem0[13]));
remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd28), .done(remainder_done[14]), .rem0(rem0[14]));
remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd30), .done(remainder_done[15]), .rem0(rem0[15]));
remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd32), .done(remainder_done[16]), .rem0(rem0[16]));
remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd34), .done(remainder_done[17]), .rem0(rem0[17]));
remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd36), .done(remainder_done[18]), .rem0(rem0[18]));
remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd38), .done(remainder_done[19]), .rem0(rem0[19]));
remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd40), .done(remainder_done[20]), .rem0(rem0[20]));
remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd42), .done(remainder_done[21]), .rem0(rem0[21]));
remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd44), .done(remainder_done[22]), .rem0(rem0[22]));
remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd46), .done(remainder_done[23]), .rem0(rem0[23]));
reg [3:0] state;
reg [3:0] state_c;
parameter INITIAL = 2'b00;
parameter PROCESS = 2'b01;
parameter DONE = 2'b10;
always @(*) begin
count_c = count;
is_prime_c = is_prime;
done_c = done;
state_c = state;
remainder = remainder_c;
case (state)
INITIAL: begin
state_c = INITIAL;
if (falling_transition == 1'b1) begin
count_c = startValConcat;
done_c = 1'b0;
is_prime_c = 1'b1;
state_c = PROCESS;
if (count_c[0] == 33'b0) begin
count_c = count_c + 33'b1;
end
end
clear = 1'b1;
end
PROCESS: begin
clear = 1'b0;
if (dividend == 32'b0 | dividend == 32'b1) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
if (dividend[0] == 1'b0 & (dividend != 32'd2)) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
if (remainder_done == 24'b111111111111111111111111) begin
if (rem0 != 24'b000000000000000000000000) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
count_c = count + 33'd48;
state_c = PROCESS;
if ((count) > (endValConcat)) begin
done_c = 1'b1;
state_c = INITIAL;
end
end
end
DONE: begin
end
endcase
if(rst == 1'b1) begin
state_c = INITIAL;
count_c = startValConcat;
done_c = 1'b0;
is_prime_c = 1'b1;
end
end
always @(posedge clk) begin
count <= #1 count_c;
is_prime <= #1 is_prime_c;
done <= #1 done_c;
state <= #1 state_c;
end
endmodule | module prime_tester(clk, rst, dividend, start, done, is_prime, count, start_val, end_val, rem0); |
input [31:0] dividend;
input start, clk, rst;
input [31:0] start_val, end_val;
output reg done, is_prime;
reg done_c, is_prime_c;
output reg [32:0] count;
reg [32:0] count_c;
wire [32:0] endValConcat = {1'b0, end_val};
wire [32:0] startValConcat = {1'b0, start_val};
wire falling_transition;
reg run, run_c;
reg clear;
edge_detector_falling edge_detector_falling2(.clk(clk), .input_signal(start), .falling_transition(falling_transition));
wire [23:0] remainder_done;
wire [31:0] rem;
reg [31:0] remainder;
wire [31:0] remainder_c;
output [23:0] rem0;
remainder_test test0(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0]), .done(remainder_done[0]), .rem0(rem0[0]));
remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd2), .done(remainder_done[1]), .rem0(rem0[1]));
remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd4), .done(remainder_done[2]), .rem0(rem0[2]));
remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd6), .done(remainder_done[3]), .rem0(rem0[3]));
remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd8), .done(remainder_done[4]), .rem0(rem0[4]));
remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd10), .done(remainder_done[5]), .rem0(rem0[5]));
remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd12), .done(remainder_done[6]), .rem0(rem0[6]));
remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd14), .done(remainder_done[7]), .rem0(rem0[7]));
remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd16), .done(remainder_done[8]), .rem0(rem0[8]));
remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd18), .done(remainder_done[9]), .rem0(rem0[9]));
remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd20), .done(remainder_done[10]), .rem0(rem0[10]));
remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd22), .done(remainder_done[11]), .rem0(rem0[11]));
remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd24), .done(remainder_done[12]), .rem0(rem0[12]));
remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd26), .done(remainder_done[13]), .rem0(rem0[13]));
remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd28), .done(remainder_done[14]), .rem0(rem0[14]));
remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd30), .done(remainder_done[15]), .rem0(rem0[15]));
remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd32), .done(remainder_done[16]), .rem0(rem0[16]));
remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd34), .done(remainder_done[17]), .rem0(rem0[17]));
remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd36), .done(remainder_done[18]), .rem0(rem0[18]));
remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd38), .done(remainder_done[19]), .rem0(rem0[19]));
remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd40), .done(remainder_done[20]), .rem0(rem0[20]));
remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd42), .done(remainder_done[21]), .rem0(rem0[21]));
remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd44), .done(remainder_done[22]), .rem0(rem0[22]));
remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6'd46), .done(remainder_done[23]), .rem0(rem0[23]));
reg [3:0] state;
reg [3:0] state_c;
parameter INITIAL = 2'b00;
parameter PROCESS = 2'b01;
parameter DONE = 2'b10;
always @(*) begin
count_c = count;
is_prime_c = is_prime;
done_c = done;
state_c = state;
remainder = remainder_c;
case (state)
INITIAL: begin
state_c = INITIAL;
if (falling_transition == 1'b1) begin
count_c = startValConcat;
done_c = 1'b0;
is_prime_c = 1'b1;
state_c = PROCESS;
if (count_c[0] == 33'b0) begin
count_c = count_c + 33'b1;
end
end
clear = 1'b1;
end
PROCESS: begin
clear = 1'b0;
if (dividend == 32'b0 | dividend == 32'b1) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
if (dividend[0] == 1'b0 & (dividend != 32'd2)) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
if (remainder_done == 24'b111111111111111111111111) begin
if (rem0 != 24'b000000000000000000000000) begin
is_prime_c = 1'b0;
done_c = 1'b1;
state_c = INITIAL;
end
count_c = count + 33'd48;
state_c = PROCESS;
if ((count) > (endValConcat)) begin
done_c = 1'b1;
state_c = INITIAL;
end
end
end
DONE: begin
end
endcase
if(rst == 1'b1) begin
state_c = INITIAL;
count_c = startValConcat;
done_c = 1'b0;
is_prime_c = 1'b1;
end
end
always @(posedge clk) begin
count <= #1 count_c;
is_prime <= #1 is_prime_c;
done <= #1 done_c;
state <= #1 state_c;
end
endmodule | 0 |
3,579 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module remainder_test(clk, rst, numerator, denominator, done, rem0);
input clk, rst;
input [31:0] numerator, denominator;
reg [31:0] remainder;
output reg done, rem0;
reg done_c, rem0_c;
reg [4:0] i;
reg [4:0] i_c;
reg [31:0] remainder_c;
reg [31:0] Ni;
always @(*) begin
done_c = done;
rem0_c = rem0;
i_c = i - 5'b00001;
remainder_c = remainder << 1'b1;
Ni = numerator << (5'b11111 - i);
remainder_c[0] = Ni[31];
if (remainder_c >= denominator) begin
remainder_c = remainder_c - denominator;
end
if(numerator[0] == 1'b1 & denominator[0] == 1'b0) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (numerator <= denominator) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (denominator == 32'b0 | denominator == 32'b1) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (i == 5'b00000) begin
done_c = 1'b1;
if(remainder_c == 32'b0) begin
rem0_c = 1'b1;
end
end
else begin
done_c = 1'b0;
end
if (rst == 1'b1 | done == 1'b1) begin
i_c = 5'b11111;
remainder_c = 32'b00000000000000000000000000000000;
done_c = 1'b0;
rem0_c = 1'b0;
end
end
always @(posedge clk) begin
i <= #1 i_c;
remainder <= #1 remainder_c;
done <= #1 done_c;
rem0 <= #1 rem0_c;
end
endmodule | module remainder_test(clk, rst, numerator, denominator, done, rem0); |
input clk, rst;
input [31:0] numerator, denominator;
reg [31:0] remainder;
output reg done, rem0;
reg done_c, rem0_c;
reg [4:0] i;
reg [4:0] i_c;
reg [31:0] remainder_c;
reg [31:0] Ni;
always @(*) begin
done_c = done;
rem0_c = rem0;
i_c = i - 5'b00001;
remainder_c = remainder << 1'b1;
Ni = numerator << (5'b11111 - i);
remainder_c[0] = Ni[31];
if (remainder_c >= denominator) begin
remainder_c = remainder_c - denominator;
end
if(numerator[0] == 1'b1 & denominator[0] == 1'b0) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (numerator <= denominator) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (denominator == 32'b0 | denominator == 32'b1) begin
done_c = 1'b1;
remainder_c = 32'b11;
rem0_c = 1'b0;
end
if (i == 5'b00000) begin
done_c = 1'b1;
if(remainder_c == 32'b0) begin
rem0_c = 1'b1;
end
end
else begin
done_c = 1'b0;
end
if (rst == 1'b1 | done == 1'b1) begin
i_c = 5'b11111;
remainder_c = 32'b00000000000000000000000000000000;
done_c = 1'b0;
rem0_c = 1'b0;
end
end
always @(posedge clk) begin
i <= #1 i_c;
remainder <= #1 remainder_c;
done <= #1 done_c;
rem0 <= #1 rem0_c;
end
endmodule | 0 |
3,580 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module number_generator(clk, rst, sample, debug, value);
input clk, rst, sample;
input [1:0] debug;
output reg [31:0] value;
reg [15:0] count, count_c;
reg [31:0] value_c;
wire rising_transition, falling_transition;
edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(sample), .rising_transition(rising_transition));
edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(sample), .falling_transition(falling_transition));
always @(*) begin
count_c = count + 16'b0000000000000001;
value_c = value;
case (debug)
2'b00: begin
if (falling_transition == 1'b1) begin
value_c = {value[31:16], count};
end
if(rising_transition == 1'b1) begin
value_c = {count, value[15:0]};
end
end
2'b01: begin
value_c = 32'b01111111111111111111111111111001;
end
2'b10: begin
value_c = 32'd130680497;
end
2'b11: begin
value_c = 32'd2147483647;
end
endcase
if (rst == 1'b1) begin
count_c = 16'b0000000000000000;
value_c = 32'b00000000000000000000000000000000;
end
end
always @(*) begin
count <= #1 count_c;
value <= #1 value_c;
end
endmodule | module number_generator(clk, rst, sample, debug, value); |
input clk, rst, sample;
input [1:0] debug;
output reg [31:0] value;
reg [15:0] count, count_c;
reg [31:0] value_c;
wire rising_transition, falling_transition;
edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(sample), .rising_transition(rising_transition));
edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(sample), .falling_transition(falling_transition));
always @(*) begin
count_c = count + 16'b0000000000000001;
value_c = value;
case (debug)
2'b00: begin
if (falling_transition == 1'b1) begin
value_c = {value[31:16], count};
end
if(rising_transition == 1'b1) begin
value_c = {count, value[15:0]};
end
end
2'b01: begin
value_c = 32'b01111111111111111111111111111001;
end
2'b10: begin
value_c = 32'd130680497;
end
2'b11: begin
value_c = 32'd2147483647;
end
endcase
if (rst == 1'b1) begin
count_c = 16'b0000000000000000;
value_c = 32'b00000000000000000000000000000000;
end
end
always @(*) begin
count <= #1 count_c;
value <= #1 value_c;
end
endmodule | 0 |
3,581 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module edge_detector_rising(clk, input_signal, rising_transition);
input clk, input_signal;
output reg rising_transition;
reg n;
wire rising_transition_c;
assign rising_transition_c = ~n & input_signal;
always @(posedge clk) begin
n <= #1 input_signal;
rising_transition <= rising_transition_c;
end
endmodule | module edge_detector_rising(clk, input_signal, rising_transition); |
input clk, input_signal;
output reg rising_transition;
reg n;
wire rising_transition_c;
assign rising_transition_c = ~n & input_signal;
always @(posedge clk) begin
n <= #1 input_signal;
rising_transition <= rising_transition_c;
end
endmodule | 0 |
3,582 | data/full_repos/permissive/105729015/Next_prime_finder.v | 105,729,015 | Next_prime_finder.v | v | 765 | 218 | [] | [] | [] | [(6, 248), (251, 262), (265, 307), (310, 328), (331, 397), (400, 420), (423, 589), (592, 671), (674, 728), (731, 746), (749, 764)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance lab7.prime7\n if (count_c[0] == 33\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = PROCESS;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n : ... In instance lab7.prime7\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n : ... In instance lab7.prime7\n state_c = INITIAL;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n : ... In instance lab7\nwire dividend = count;\n ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4))); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1)); \n ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n' | 1,361 | module | module edge_detector_falling(clk, input_signal, falling_transition);
input clk, input_signal;
output reg falling_transition;
reg n;
wire falling_transition_c;
assign falling_transition_c = n & ~input_signal;
always @(posedge clk) begin
n <= #1 input_signal;
falling_transition <= falling_transition_c;
end
endmodule | module edge_detector_falling(clk, input_signal, falling_transition); |
input clk, input_signal;
output reg falling_transition;
reg n;
wire falling_transition_c;
assign falling_transition_c = n & ~input_signal;
always @(posedge clk) begin
n <= #1 input_signal;
falling_transition <= falling_transition_c;
end
endmodule | 0 |
3,583 | data/full_repos/permissive/105729015/Prime_finder_32_bit.v | 105,729,015 | Prime_finder_32_bit.v | v | 300 | 271 | [] | [] | [] | null | line:72: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:61: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:68: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:74: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:82: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:90: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:96: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:101: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:106: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:115: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:120: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:123: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:128: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:131: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:138: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:144: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:150: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:155: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:170: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:175: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:194: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:197: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:200: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:211: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:214: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:222: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:225: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:227: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:231: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:234: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:236: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:238: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:240: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:245: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:247: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:258: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:265: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:272: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:278: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:290: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:292: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:201: Signal definition not found, creating implicitly: \'rem0\'\n : ... Suggested alternative: \'rem00\'\n $display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);\n ^~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:34: Cannot find file containing module: \'edge_detector_rising\'\n edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising.sv\n edge_detector_rising\n edge_detector_rising.v\n edge_detector_rising.sv\n obj_dir/edge_detector_rising\n obj_dir/edge_detector_rising.v\n obj_dir/edge_detector_rising.sv\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:35: Cannot find file containing module: \'edge_detector_falling\'\n edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:36: Cannot find file containing module: \'number_generator\'\n number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:37: Cannot find file containing module: \'remainder_test\'\n remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:40: Cannot find file containing module: \'prime_tester\'\n prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32\'d2), .end_val((dividend >> 2)), .rem0(rem00)); \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:41: Cannot find file containing module: \'prime_tester\'\n prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01)); \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:42: Cannot find file containing module: \'prime_tester\'\n prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02)); \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:43: Cannot find file containing module: \'prime_tester\'\n prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1\'b1), .rem0(rem03)); \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:52: Cannot find file containing module: \'serializer\'\n serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:57: Cannot find file containing module: \'output_ram\'\n output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:248: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'inc\' generates 32 bits.\n : ... In instance lab7_tb\n inc = inc + 64\'b1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:248: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 64 bits.\n : ... In instance lab7_tb\n inc = inc + 64\'b1;\n ^\n%Error: Exiting due to 10 error(s), 45 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,363 | module | module lab7_tb();
reg clk, rst;
reg input_signal;
reg sample;
reg [1:0] debug;
reg [31:0] numerator, denominator;
wire rising_transition, falling_transition;
wire [31:0] value;
wire done;
wire [31:0] remainder;
integer i, j;
reg [31:0] inc;
reg [31:0] dividend;
reg start;
wire [3:0] done_prime, is_prime;
wire [32:0] count_0, count_1, count_2, count_3;
wire prime_falling_transition;
wire [31:0] remainder_prime;
wire [23:0] remainder_prime_done;
reg run;
wire [23:0] rem00, rem01, rem02, rem03;
edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));
edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));
number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));
prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32'd2), .end_val((dividend >> 2)), .rem0(rem00));
prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01));
prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02));
prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1'b1), .rem0(rem03));
reg save;
reg [31:0] data_in;
wire [7:0] write_data;
wire write_enable;
wire [1:0] write_addr;
serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));
reg [1:0] read_addr;
wire [7:0] read_data;
output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));
initial begin
#3;
$display("Test Edge Detector");
input_signal = 1'b0;
clk = 1'b0;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
input_signal = 1'b1;
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
input_signal = 1'b0;
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
$display("Random Number Generator");
#1;
debug = 2'b00;
clk = 1'b0;
rst = 1'b1;
run = 1'b1;
#3;
rst = 1'b0;
repeat(20) begin
#1;
clk = ~clk;
end
debug = 2'b01;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b10;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b11;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b00;
sample = 1'b1;
repeat(2000) begin
#1;
clk = ~clk;
end
sample = 1'b0;
repeat(4000) begin
#1;
clk = ~clk;
end
sample = 1'b1;
repeat(6000) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
$display("Remainder Test");
numerator = 5;
denominator = 6;
clk = 1'b0;
rst = 1'b0;
#1;
rst = 1'b1;
repeat(2) begin
#1;
clk = ~clk;
$display("Num: %d, Den: %d, Rem: %d, Done: %d", numerator, denominator, remainder, done);
end
rst = 1'b0;
#1;
for (i = 1; i < 10; i = i + 1) begin
for (j = 1; j < 10; j = j + 1) begin
numerator = i;
denominator = j;
#1;
while (done == 1'b0) begin
#1;
clk = ~clk;
end
#1;
$display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);
end
end
$display("Test Prime Number");
clk = 1'b0;
rst = 1'b0;
#3;
clk = 1'b1;
rst = 1'b1;
#3;
rst = 1'b0;
inc = 32'd2;
repeat (100) begin
clk = 1'b0;
rst = 1'b0;
#3;
clk = 1'b1;
rst = 1'b1;
#3;
rst = 1'b0;
#3;
start = 1'b1;
repeat(3) begin
#3;
clk = ~clk;
end
#3;
start = 1'b0;
#3;
dividend = inc;
#3;
while (done_prime != 4'b1111) begin
#3;
clk = ~clk;
end
#3;
$display("inc: %d, isPrime: %b, done: %b", inc, &is_prime, done_prime);
#3;
inc = inc + 64'b1;
end
$display("Test Serializer, Output RAM");
clk = 1'b0;
save = 1'b0;
rst = 1'b0;
data_in = 32'b11111111111111101111110011111000;
repeat(6) begin
#3;
clk = ~clk;
end
rst = 1'b1;
repeat(6) begin
#3;
clk = ~clk;
end
rst = 1'b0;
repeat(6) begin
#3;
clk = ~clk;
end
save = 1'b1;
repeat(20) begin
#3;
clk = ~clk;
if (clk == 1'b1) begin
$display("write_data: %b, write_enable: %b, write_addr: %b", write_data, write_enable, write_addr);
end
end
$display("Test Output RAM");
read_addr = 2'b00;
repeat(4) begin
#3;
clk = ~clk;
#3;
$display("read_addr: %b, read_data: %b", read_addr, read_data);
read_addr = read_addr + 1'b1;
end
end
endmodule | module lab7_tb(); |
reg clk, rst;
reg input_signal;
reg sample;
reg [1:0] debug;
reg [31:0] numerator, denominator;
wire rising_transition, falling_transition;
wire [31:0] value;
wire done;
wire [31:0] remainder;
integer i, j;
reg [31:0] inc;
reg [31:0] dividend;
reg start;
wire [3:0] done_prime, is_prime;
wire [32:0] count_0, count_1, count_2, count_3;
wire prime_falling_transition;
wire [31:0] remainder_prime;
wire [23:0] remainder_prime_done;
reg run;
wire [23:0] rem00, rem01, rem02, rem03;
edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));
edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));
number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));
prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32'd2), .end_val((dividend >> 2)), .rem0(rem00));
prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01));
prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02));
prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1'b1), .rem0(rem03));
reg save;
reg [31:0] data_in;
wire [7:0] write_data;
wire write_enable;
wire [1:0] write_addr;
serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));
reg [1:0] read_addr;
wire [7:0] read_data;
output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));
initial begin
#3;
$display("Test Edge Detector");
input_signal = 1'b0;
clk = 1'b0;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
input_signal = 1'b1;
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
input_signal = 1'b0;
repeat(5) begin
clk = ~clk;
#3;
$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
end
$display("Random Number Generator");
#1;
debug = 2'b00;
clk = 1'b0;
rst = 1'b1;
run = 1'b1;
#3;
rst = 1'b0;
repeat(20) begin
#1;
clk = ~clk;
end
debug = 2'b01;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b10;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b11;
repeat(20) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
debug = 2'b00;
sample = 1'b1;
repeat(2000) begin
#1;
clk = ~clk;
end
sample = 1'b0;
repeat(4000) begin
#1;
clk = ~clk;
end
sample = 1'b1;
repeat(6000) begin
#1;
clk = ~clk;
end
#1;
$display("Debug: %b, value: %d", debug, value);
$display("Remainder Test");
numerator = 5;
denominator = 6;
clk = 1'b0;
rst = 1'b0;
#1;
rst = 1'b1;
repeat(2) begin
#1;
clk = ~clk;
$display("Num: %d, Den: %d, Rem: %d, Done: %d", numerator, denominator, remainder, done);
end
rst = 1'b0;
#1;
for (i = 1; i < 10; i = i + 1) begin
for (j = 1; j < 10; j = j + 1) begin
numerator = i;
denominator = j;
#1;
while (done == 1'b0) begin
#1;
clk = ~clk;
end
#1;
$display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);
end
end
$display("Test Prime Number");
clk = 1'b0;
rst = 1'b0;
#3;
clk = 1'b1;
rst = 1'b1;
#3;
rst = 1'b0;
inc = 32'd2;
repeat (100) begin
clk = 1'b0;
rst = 1'b0;
#3;
clk = 1'b1;
rst = 1'b1;
#3;
rst = 1'b0;
#3;
start = 1'b1;
repeat(3) begin
#3;
clk = ~clk;
end
#3;
start = 1'b0;
#3;
dividend = inc;
#3;
while (done_prime != 4'b1111) begin
#3;
clk = ~clk;
end
#3;
$display("inc: %d, isPrime: %b, done: %b", inc, &is_prime, done_prime);
#3;
inc = inc + 64'b1;
end
$display("Test Serializer, Output RAM");
clk = 1'b0;
save = 1'b0;
rst = 1'b0;
data_in = 32'b11111111111111101111110011111000;
repeat(6) begin
#3;
clk = ~clk;
end
rst = 1'b1;
repeat(6) begin
#3;
clk = ~clk;
end
rst = 1'b0;
repeat(6) begin
#3;
clk = ~clk;
end
save = 1'b1;
repeat(20) begin
#3;
clk = ~clk;
if (clk == 1'b1) begin
$display("write_data: %b, write_enable: %b, write_addr: %b", write_data, write_enable, write_addr);
end
end
$display("Test Output RAM");
read_addr = 2'b00;
repeat(4) begin
#3;
clk = ~clk;
#3;
$display("read_addr: %b, read_data: %b", read_addr, read_data);
read_addr = read_addr + 1'b1;
end
end
endmodule | 0 |
3,584 | data/full_repos/permissive/105729015/Testbench_2.v | 105,729,015 | Testbench_2.v | v | 149 | 221 | [] | [] | [] | null | line:56: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:57: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:59: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:65: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:67: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:74: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:76: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:83: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:85: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:91: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:93: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:109: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:111: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:120: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:122: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:126: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:129: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:131: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:137: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:139: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/105729015/Testbench_2.v:20: Cannot find file containing module: \'lab7_multi\'\n lab7_multi UUT(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi.v\n data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi.sv\n lab7_multi\n lab7_multi.v\n lab7_multi.sv\n obj_dir/lab7_multi\n obj_dir/lab7_multi.v\n obj_dir/lab7_multi.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,367 | module | module lab7_tb2();
reg ADC_CLK_10;
wire MAX10_CLK1_50, MAX10_CLK2_50;
wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
reg [1:0] KEY;
wire [9:0] LEDR;
reg [9:0] SW;
wire [31:0] count, orig_val, prime_val;
reg [31:0] test_number;
wire [2:0] state;
wire LED_done, LED_prime;
reg clk, rst;
wire [7:0] done;
wire [7:0] is_prime;
integer i;
lab7_multi UUT(
.ADC_CLK_10(ADC_CLK_10),
.MAX10_CLK1_50(MAX10_CLK1_50),
.MAX10_CLK2_50(MAX10_CLK2_50),
.HEX0(HEX0),
.HEX1(HEX1),
.HEX2(HEX2),
.HEX3(HEX3),
.HEX4(HEX4),
.HEX5(HEX5),
.KEY(KEY),
.LEDR(LEDR),
.SW(SW),
.count(count),
.orig_val(orig_val),
.prime_val(prime_val),
.test_number(test_number),
.state(state),
.LED_done(LED_done),
.LED_prime(LED_prime),
.done(done),
.is_prime(is_prime)
);
assign MAX10_CLK1_50 = clk;
initial begin
test_number = 32'd1000;
clk = 1'b0;
SW[9:0] = 10'b0000000000;
KEY[1:0] = 2'b11;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
SW[9] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
SW[9] = 1'b0;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
KEY[1] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
KEY[1] = 1'b0;
while(LED_done != 1'b1) begin
#3;
clk = ~clk;
#3;
if (clk == 1'b1) begin
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
end
end
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
repeat (100) begin
#3;
clk = ~clk;
#3;
end
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
KEY[1] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
test_number = 32'd1164;
KEY[1] = 1'b0;
#3;
repeat (10) begin
#3;
clk = ~clk;
#3;
end
$display("Here");
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
while (LED_done != 1'b1) begin
#3;
clk = ~clk;
#3;
if(clk == 1'b1) begin
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
end
end
$display("Here2");
end
endmodule | module lab7_tb2(); |
reg ADC_CLK_10;
wire MAX10_CLK1_50, MAX10_CLK2_50;
wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
reg [1:0] KEY;
wire [9:0] LEDR;
reg [9:0] SW;
wire [31:0] count, orig_val, prime_val;
reg [31:0] test_number;
wire [2:0] state;
wire LED_done, LED_prime;
reg clk, rst;
wire [7:0] done;
wire [7:0] is_prime;
integer i;
lab7_multi UUT(
.ADC_CLK_10(ADC_CLK_10),
.MAX10_CLK1_50(MAX10_CLK1_50),
.MAX10_CLK2_50(MAX10_CLK2_50),
.HEX0(HEX0),
.HEX1(HEX1),
.HEX2(HEX2),
.HEX3(HEX3),
.HEX4(HEX4),
.HEX5(HEX5),
.KEY(KEY),
.LEDR(LEDR),
.SW(SW),
.count(count),
.orig_val(orig_val),
.prime_val(prime_val),
.test_number(test_number),
.state(state),
.LED_done(LED_done),
.LED_prime(LED_prime),
.done(done),
.is_prime(is_prime)
);
assign MAX10_CLK1_50 = clk;
initial begin
test_number = 32'd1000;
clk = 1'b0;
SW[9:0] = 10'b0000000000;
KEY[1:0] = 2'b11;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
SW[9] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
SW[9] = 1'b0;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
KEY[1] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
KEY[1] = 1'b0;
while(LED_done != 1'b1) begin
#3;
clk = ~clk;
#3;
if (clk == 1'b1) begin
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
end
end
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
repeat (100) begin
#3;
clk = ~clk;
#3;
end
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
KEY[1] = 1'b1;
repeat (100) begin
#3;
clk = ~clk;
#3;
end
test_number = 32'd1164;
KEY[1] = 1'b0;
#3;
repeat (10) begin
#3;
clk = ~clk;
#3;
end
$display("Here");
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
while (LED_done != 1'b1) begin
#3;
clk = ~clk;
#3;
if(clk == 1'b1) begin
$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
end
end
$display("Here2");
end
endmodule | 0 |
3,585 | data/full_repos/permissive/105729488/state_machine.v | 105,729,488 | state_machine.v | v | 341 | 106 | [] | [] | [] | [(1, 341)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:91: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LA_RUE_YELLOW_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = LA_RUE_YELLOW_st;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:96: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LA_RUE_YELLOW_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = LA_RUE_YELLOW_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:95: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h6\' generates 4 bits.\n : ... In instance state_machine\n else if (count > 4\'b0110) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:90: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance state_machine\n if ((count >= 4\'b0011) & (count <= 4\'b0110) & la_rue_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:90: Operator LTE expects 28 bits on the RHS, but RHS\'s CONST \'4\'h6\' generates 4 bits.\n : ... In instance state_machine\n if ((count >= 4\'b0011) & (count <= 4\'b0110) & la_rue_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:119: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'PED_WALK_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = PED_WALK_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:124: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_GREEN_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:129: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LA_RUE_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = LA_RUE_GREEN_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:117: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance state_machine\n if (count > 4\'b0011) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:152: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_YELLOW_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_YELLOW_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:151: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance state_machine\n if (count >= 4\'b0011 & orchard_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:160: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_YELLOW_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_YELLOW_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:166: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_YELLOW_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_YELLOW_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:165: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h6\' generates 4 bits.\n : ... In instance state_machine\n else if (count > 4\'b0110) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:159: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance state_machine\n if (count >= 4\'b0001 & count <= 4\'b0110 & orchard_sensor_ff == 1\'b0) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:159: Operator LTE expects 28 bits on the RHS, but RHS\'s CONST \'4\'h6\' generates 4 bits.\n : ... In instance state_machine\n if (count >= 4\'b0001 & count <= 4\'b0110 & orchard_sensor_ff == 1\'b0) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:188: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LA_RUE_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = LA_RUE_GREEN_st; \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:191: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'PED_WALK_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = PED_WALK_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:194: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_GREEN_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:186: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance state_machine\n if (count > 4\'b0011) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:218: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'PED_DONT_WALK_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = PED_DONT_WALK_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:219: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 4 bits.\n : ... In instance state_machine\n flash_count_c = flash_count + 4\'b0001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:217: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance state_machine\n if (count > 4\'b1000) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:243: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'PED_OFF_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = PED_OFF_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:244: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 4 bits.\n : ... In instance state_machine\n flash_count_c = flash_count + 4\'b0001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:242: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance state_machine\n if (count > 4\'b0001) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:269: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 4 bits.\n : ... In instance state_machine\n flash_count_c = flash_count + 4\'b0001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:270: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'PED_DONT_WALK_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = PED_DONT_WALK_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:281: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LA_RUE_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = LA_RUE_GREEN_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:284: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance state_machine\n flash_count_c = 4\'b0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:288: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ORCHARD_GREEN_st\' generates 4 bits.\n : ... In instance state_machine\n state_c = ORCHARD_GREEN_st;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:291: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance state_machine\n flash_count_c = 4\'b0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:278: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance state_machine\n else if (count > 4\'b0001 & flash_count >= 4\'b0101) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:278: Operator GTE expects 4 bits on the LHS, but LHS\'s VARREF \'flash_count\' generates 3 bits.\n : ... In instance state_machine\n else if (count > 4\'b0001 & flash_count >= 4\'b0101) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:268: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance state_machine\n if (count > 4\'b0001 & flash_count < 4\'b0101) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:268: Operator LT expects 4 bits on the LHS, but LHS\'s VARREF \'flash_count\' generates 3 bits.\n : ... In instance state_machine\n if (count > 4\'b0001 & flash_count < 4\'b0101) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:74: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n : ... In instance state_machine\n case (state) \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:309: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance state_machine\n state_c = 4\'b0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine.v:315: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance state_machine\n flash_count_c = 4\'b0000;\n ^\n%Error: Exiting due to 39 warning(s)\n' | 1,369 | module | module state_machine(
clk, reset_n, la_rue_sensor, orchard_sensor, pedestrian_sensor,
la_rue_green, la_rue_yellow, la_rue_red,
orchard_green, orchard_yellow, orchard_red,
pedestrian_walk, pedestrian_stop, count, count_c, state, state_c, x, x_c
);
input reset_n;
input clk;
input la_rue_sensor, orchard_sensor, pedestrian_sensor;
output reg la_rue_green, la_rue_yellow, la_rue_red;
output reg orchard_green, orchard_yellow, orchard_red;
output reg pedestrian_walk, pedestrian_stop;
reg [2:0] flash_count, flash_count_c;
reg pedestrian_queue, pedestrian_queue_c;
reg la_rue_sensor_ff, orchard_sensor_ff, pedestrian_sensor_ff;
reg la_rue_sensor_ff_c, orchard_sensor_ff_c, pedestrian_sensor_ff_c;
output reg [2:0] state;
output reg [2:0] state_c;
output reg [27:0] count;
output reg [27:0] count_c;
output reg [27:0] x;
output reg [27:0] x_c;
parameter LA_RUE_GREEN_st = 4'b0000;
parameter LA_RUE_YELLOW_st = 4'b0001;
parameter PED_WALK_st = 4'b0010;
parameter PED_DONT_WALK_st = 4'b0011;
parameter PED_OFF_st = 4'b0100;
parameter ORCHARD_GREEN_st = 4'b0101;
parameter ORCHARD_YELLOW_st = 4'b0110;
always @(*) begin
state_c = state;
flash_count_c = flash_count;
la_rue_sensor_ff_c = la_rue_sensor;
orchard_sensor_ff_c = orchard_sensor;
pedestrian_sensor_ff_c = pedestrian_sensor_ff;
x_c = x + 28'b1;
if (x == 28'd24999999) begin
x_c = 28'd0;
count_c = count + 28'b1;
end
if (pedestrian_sensor == 0) begin
pedestrian_sensor_ff_c = 1'b1;
end
case (state)
LA_RUE_GREEN_st: begin
la_rue_green = 1'b1;
la_rue_yellow = 1'b0;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (orchard_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if ((count >= 4'b0011) & (count <= 4'b0110) & la_rue_sensor_ff == 1'b0) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0110) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
LA_RUE_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b1;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0011) begin
if (pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (pedestrian_sensor_ff == 1'b0 & orchard_sensor_ff == 1'b1) begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
else begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_GREEN_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b1;
orchard_yellow = 1'b0;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b0) begin
if (count >= 4'b0011 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
else if (la_rue_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if (count >= 4'b0001 & count <= 4'b0110 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0110) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b1;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0011) begin
state_c = LA_RUE_GREEN_st;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
end
else if (orchard_sensor_ff == 1'b1 & pedestrian_sensor_ff == 1'b0 & la_rue_sensor_ff == 1'b0) begin
state_c = ORCHARD_GREEN_st;
end
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b1;
pedestrian_stop = 1'b0;
if (count > 4'b1000) begin
state_c = PED_DONT_WALK_st;
flash_count_c = flash_count + 4'b0001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_DONT_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0001) begin
state_c = PED_OFF_st;
flash_count_c = flash_count + 4'b0001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_OFF_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b0;
if (count > 4'b0001 & flash_count < 4'b0101) begin
flash_count_c = flash_count + 4'b0001;
state_c = PED_DONT_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0001 & flash_count >= 4'b0101) begin
if (orchard_sensor_ff == 1'b0) begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 4'b0000;
pedestrian_sensor_ff_c = 1'b0;
end
else begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 4'b0000;
pedestrian_sensor_ff_c = 1'b0;
end
end
end
endcase
if (reset_n == 0) begin
state_c = 4'b0000;
x_c = 28'd0;
count_c = 28'd0;
flash_count_c = 4'b0000;
orchard_sensor_ff_c = 1'b0;
la_rue_sensor_ff_c = 1'b0;
pedestrian_sensor_ff_c = 1'b0;
end
end
always @(posedge clk) begin
state <= #1 state_c;
count <= #1 count_c;
x <= #1 x_c;
flash_count <= #1 flash_count_c;
orchard_sensor_ff <= #1 orchard_sensor_ff_c;
la_rue_sensor_ff <= #1 la_rue_sensor_ff_c;
pedestrian_sensor_ff <= #1 pedestrian_sensor_ff_c;
end
endmodule | module state_machine(
clk, reset_n, la_rue_sensor, orchard_sensor, pedestrian_sensor,
la_rue_green, la_rue_yellow, la_rue_red,
orchard_green, orchard_yellow, orchard_red,
pedestrian_walk, pedestrian_stop, count, count_c, state, state_c, x, x_c
); |
input reset_n;
input clk;
input la_rue_sensor, orchard_sensor, pedestrian_sensor;
output reg la_rue_green, la_rue_yellow, la_rue_red;
output reg orchard_green, orchard_yellow, orchard_red;
output reg pedestrian_walk, pedestrian_stop;
reg [2:0] flash_count, flash_count_c;
reg pedestrian_queue, pedestrian_queue_c;
reg la_rue_sensor_ff, orchard_sensor_ff, pedestrian_sensor_ff;
reg la_rue_sensor_ff_c, orchard_sensor_ff_c, pedestrian_sensor_ff_c;
output reg [2:0] state;
output reg [2:0] state_c;
output reg [27:0] count;
output reg [27:0] count_c;
output reg [27:0] x;
output reg [27:0] x_c;
parameter LA_RUE_GREEN_st = 4'b0000;
parameter LA_RUE_YELLOW_st = 4'b0001;
parameter PED_WALK_st = 4'b0010;
parameter PED_DONT_WALK_st = 4'b0011;
parameter PED_OFF_st = 4'b0100;
parameter ORCHARD_GREEN_st = 4'b0101;
parameter ORCHARD_YELLOW_st = 4'b0110;
always @(*) begin
state_c = state;
flash_count_c = flash_count;
la_rue_sensor_ff_c = la_rue_sensor;
orchard_sensor_ff_c = orchard_sensor;
pedestrian_sensor_ff_c = pedestrian_sensor_ff;
x_c = x + 28'b1;
if (x == 28'd24999999) begin
x_c = 28'd0;
count_c = count + 28'b1;
end
if (pedestrian_sensor == 0) begin
pedestrian_sensor_ff_c = 1'b1;
end
case (state)
LA_RUE_GREEN_st: begin
la_rue_green = 1'b1;
la_rue_yellow = 1'b0;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (orchard_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if ((count >= 4'b0011) & (count <= 4'b0110) & la_rue_sensor_ff == 1'b0) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0110) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
LA_RUE_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b1;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0011) begin
if (pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (pedestrian_sensor_ff == 1'b0 & orchard_sensor_ff == 1'b1) begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
else begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_GREEN_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b1;
orchard_yellow = 1'b0;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b0) begin
if (count >= 4'b0011 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
else if (la_rue_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if (count >= 4'b0001 & count <= 4'b0110 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0110) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b1;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0011) begin
state_c = LA_RUE_GREEN_st;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
end
else if (orchard_sensor_ff == 1'b1 & pedestrian_sensor_ff == 1'b0 & la_rue_sensor_ff == 1'b0) begin
state_c = ORCHARD_GREEN_st;
end
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b1;
pedestrian_stop = 1'b0;
if (count > 4'b1000) begin
state_c = PED_DONT_WALK_st;
flash_count_c = flash_count + 4'b0001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_DONT_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count > 4'b0001) begin
state_c = PED_OFF_st;
flash_count_c = flash_count + 4'b0001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_OFF_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b0;
if (count > 4'b0001 & flash_count < 4'b0101) begin
flash_count_c = flash_count + 4'b0001;
state_c = PED_DONT_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 4'b0001 & flash_count >= 4'b0101) begin
if (orchard_sensor_ff == 1'b0) begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 4'b0000;
pedestrian_sensor_ff_c = 1'b0;
end
else begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 4'b0000;
pedestrian_sensor_ff_c = 1'b0;
end
end
end
endcase
if (reset_n == 0) begin
state_c = 4'b0000;
x_c = 28'd0;
count_c = 28'd0;
flash_count_c = 4'b0000;
orchard_sensor_ff_c = 1'b0;
la_rue_sensor_ff_c = 1'b0;
pedestrian_sensor_ff_c = 1'b0;
end
end
always @(posedge clk) begin
state <= #1 state_c;
count <= #1 count_c;
x <= #1 x_c;
flash_count <= #1 flash_count_c;
orchard_sensor_ff <= #1 orchard_sensor_ff_c;
la_rue_sensor_ff <= #1 la_rue_sensor_ff_c;
pedestrian_sensor_ff <= #1 pedestrian_sensor_ff_c;
end
endmodule | 0 |
3,586 | data/full_repos/permissive/105729488/state_machine_tb.v | 105,729,488 | state_machine_tb.v | v | 104 | 108 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105729488/state_machine_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/105729488/state_machine_tb.v:16: Cannot find file containing module: \'state_machine\'\n state_machine UUT(.clk(clk), .reset_n(reset_n), .la_rue_sensor(la_rue_sensor),\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine.v\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine.sv\n state_machine\n state_machine.v\n state_machine.sv\n obj_dir/state_machine\n obj_dir/state_machine.v\n obj_dir/state_machine.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,370 | module | module state_machine_tb();
wire la_rue_green, la_rue_yellow, la_rue_red;
wire orchard_green, orchard_yellow, orchard_red;
wire pedestrian_walk, pedestrian_stop;
wire [27:0] count, count_c, x, x_c;
wire [3:0] state, state_c;
reg clk;
reg reset_n;
reg la_rue_sensor, orchard_sensor, pedestrian_sensor;
integer i, last_count;
state_machine UUT(.clk(clk), .reset_n(reset_n), .la_rue_sensor(la_rue_sensor),
.orchard_sensor(orchard_sensor), .pedestrian_sensor(pedestrian_sensor),
.la_rue_green(la_rue_green), .la_rue_yellow(la_rue_yellow), .la_rue_red(la_rue_red),
.orchard_green(orchard_green), .orchard_yellow(orchard_yellow), .orchard_red(orchard_red),
.pedestrian_walk(pedestrian_walk), .pedestrian_stop(pedestrian_stop),
.count(count), .count_c(count_c),
.state(state), .state_c(state_c), .x(x), .x_c(x_c));
initial begin
clk = 0;
reset_n = 0;
#10;
reset_n = 1;
#10;
la_rue_sensor = 1;
orchard_sensor = 0;
pedestrian_sensor = 1;
$display("Test 1");
for (i = 0; i < 50; i = i + 1) begin
#3;
clk = ~clk;
#3;
if (i == 1) begin
pedestrian_sensor = 0;
end
#3;
if (i == 3) begin
pedestrian_sensor = 1;
orchard_sensor = 1;
end
#3;
$display("Count: %d, Current State: %d", count, state);
end
$display("Test 2");
for (i = 0; i < 50; i = i + 1) begin
#3;
clk = ~clk;
#3;
if (i == 1) begin
la_rue_sensor = 0;
orchard_sensor = 1;
end
#3;
if (i == 20) begin
pedestrian_sensor = 0;
end
if (i == 25) begin
la_rue_sensor = 1;
orchard_sensor = 0;
end
#3;
$display("Count: %d, Current State: %d", count, state);
end
$display("End Tests");
end
endmodule | module state_machine_tb(); |
wire la_rue_green, la_rue_yellow, la_rue_red;
wire orchard_green, orchard_yellow, orchard_red;
wire pedestrian_walk, pedestrian_stop;
wire [27:0] count, count_c, x, x_c;
wire [3:0] state, state_c;
reg clk;
reg reset_n;
reg la_rue_sensor, orchard_sensor, pedestrian_sensor;
integer i, last_count;
state_machine UUT(.clk(clk), .reset_n(reset_n), .la_rue_sensor(la_rue_sensor),
.orchard_sensor(orchard_sensor), .pedestrian_sensor(pedestrian_sensor),
.la_rue_green(la_rue_green), .la_rue_yellow(la_rue_yellow), .la_rue_red(la_rue_red),
.orchard_green(orchard_green), .orchard_yellow(orchard_yellow), .orchard_red(orchard_red),
.pedestrian_walk(pedestrian_walk), .pedestrian_stop(pedestrian_stop),
.count(count), .count_c(count_c),
.state(state), .state_c(state_c), .x(x), .x_c(x_c));
initial begin
clk = 0;
reset_n = 0;
#10;
reset_n = 1;
#10;
la_rue_sensor = 1;
orchard_sensor = 0;
pedestrian_sensor = 1;
$display("Test 1");
for (i = 0; i < 50; i = i + 1) begin
#3;
clk = ~clk;
#3;
if (i == 1) begin
pedestrian_sensor = 0;
end
#3;
if (i == 3) begin
pedestrian_sensor = 1;
orchard_sensor = 1;
end
#3;
$display("Count: %d, Current State: %d", count, state);
end
$display("Test 2");
for (i = 0; i < 50; i = i + 1) begin
#3;
clk = ~clk;
#3;
if (i == 1) begin
la_rue_sensor = 0;
orchard_sensor = 1;
end
#3;
if (i == 20) begin
pedestrian_sensor = 0;
end
if (i == 25) begin
la_rue_sensor = 1;
orchard_sensor = 0;
end
#3;
$display("Count: %d, Current State: %d", count, state);
end
$display("End Tests");
end
endmodule | 0 |
3,587 | data/full_repos/permissive/105729488/state_machine_tbmod.v | 105,729,488 | state_machine_tbmod.v | v | 332 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:94: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance state_machine\n else if (count > 3\'b110) begin\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:89: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance state_machine\n if ((count >= 3\'b011) & (count <= 3\'b110) & la_rue_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:89: Operator LTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance state_machine\n if ((count >= 3\'b011) & (count <= 3\'b110) & la_rue_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:116: Operator EQ expects 28 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance state_machine\n if (count == 3\'b011) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:145: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance state_machine\n if (count >= 3\'b011 & orchard_sensor_ff == 1\'b0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:159: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance state_machine\n else if (count > 3\'b110) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:153: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance state_machine\n if (count >= 3\'b001 & count <= 3\'b110 & orchard_sensor_ff == 1\'b0) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:153: Operator LTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance state_machine\n if (count >= 3\'b001 & count <= 3\'b110 & orchard_sensor_ff == 1\'b0) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:180: Operator EQ expects 28 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n : ... In instance state_machine\n if (count == 3\'b011) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:208: Operator GT expects 28 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n : ... In instance state_machine\n if (count > 3\'b110) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:233: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance state_machine\n if (count >= 3\'b001) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:269: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance state_machine\n else if (count >= 3\'b001 & flash_count >= 3\'b101) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/105729488/state_machine_tbmod.v:259: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n : ... In instance state_machine\n if (count >= 3\'b001 & flash_count < 3\'b101) begin\n ^~\n%Error: Exiting due to 13 warning(s)\n' | 1,371 | module | module state_machine(
clk, reset_n, la_rue_sensor, orchard_sensor, pedestrian_sensor,
la_rue_green, la_rue_yellow, la_rue_red,
orchard_green, orchard_yellow, orchard_red,
pedestrian_walk, pedestrian_stop, count, count_c, state, state_c, x, x_c
);
input reset_n;
input clk;
input la_rue_sensor, orchard_sensor, pedestrian_sensor;
output reg la_rue_green, la_rue_yellow, la_rue_red;
output reg orchard_green, orchard_yellow, orchard_red;
output reg pedestrian_walk, pedestrian_stop;
reg [2:0] flash_count, flash_count_c;
reg pedestrian_queue, pedestrian_queue_c;
reg la_rue_sensor_ff, orchard_sensor_ff, pedestrian_sensor_ff;
reg la_rue_sensor_ff_c, orchard_sensor_ff_c, pedestrian_sensor_ff_c;
output reg [2:0] state;
output reg [2:0] state_c;
output reg [27:0] count;
output reg [27:0] count_c;
output reg [27:0] x;
output reg [27:0] x_c;
parameter LA_RUE_GREEN_st = 3'b000;
parameter LA_RUE_YELLOW_st = 3'b001;
parameter PED_WALK_st = 3'b010;
parameter PED_DONT_WALK_st = 3'b011;
parameter PED_OFF_st = 3'b100;
parameter ORCHARD_GREEN_st = 3'b101;
parameter ORCHARD_YELLOW_st = 3'b110;
always @(*) begin
state_c = state;
flash_count_c = flash_count;
la_rue_sensor_ff_c = la_rue_sensor;
orchard_sensor_ff_c = orchard_sensor;
pedestrian_sensor_ff_c = pedestrian_sensor_ff;
count_c = count + 1;
x_c = x + 1'b1;
if (pedestrian_sensor == 0) begin
pedestrian_sensor_ff_c = 1'b1;
end
case (state)
LA_RUE_GREEN_st: begin
la_rue_green = 1'b1;
la_rue_yellow = 1'b0;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (orchard_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if ((count >= 3'b011) & (count <= 3'b110) & la_rue_sensor_ff == 1'b0) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 3'b110) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
LA_RUE_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b1;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count == 3'b011) begin
if (pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (pedestrian_sensor_ff == 1'b0 & orchard_sensor_ff == 1'b1) begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_GREEN_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b1;
orchard_yellow = 1'b0;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b0) begin
if (count >= 3'b011 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
else if (la_rue_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if (count >= 3'b001 & count <= 3'b110 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 3'b110) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b1;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count == 3'b011) begin
state_c = LA_RUE_GREEN_st;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
end
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b1;
pedestrian_stop = 1'b0;
if (count > 3'b110) begin
state_c = PED_DONT_WALK_st;
flash_count_c = flash_count + 3'b001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_DONT_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count >= 3'b001) begin
state_c = PED_OFF_st;
flash_count_c = flash_count + 3'b001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_OFF_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b0;
if (count >= 3'b001 & flash_count < 3'b101) begin
flash_count_c = flash_count + 3'b001;
state_c = PED_DONT_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count >= 3'b001 & flash_count >= 3'b101) begin
if (orchard_sensor_ff == 1'b0) begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 3'b000;
pedestrian_sensor_ff_c = 1'b0;
end
else begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 3'b000;
pedestrian_sensor_ff_c = 1'b0;
end
end
end
endcase
if (reset_n == 0) begin
state_c = 3'b000;
x_c = 28'd0;
count_c = 28'd0;
flash_count_c = 3'b000;
orchard_sensor_ff_c = 1'b0;
la_rue_sensor_ff_c = 1'b0;
pedestrian_sensor_ff_c = 1'b0;
end
end
always @( clk) begin
state <= #1 state_c;
count <= #1 count_c;
x <= #1 x_c;
flash_count <= #1 flash_count_c;
orchard_sensor_ff <= #1 orchard_sensor_ff_c;
la_rue_sensor_ff <= #1 la_rue_sensor_ff_c;
pedestrian_sensor_ff <= #1 pedestrian_sensor_ff_c;
end
endmodule | module state_machine(
clk, reset_n, la_rue_sensor, orchard_sensor, pedestrian_sensor,
la_rue_green, la_rue_yellow, la_rue_red,
orchard_green, orchard_yellow, orchard_red,
pedestrian_walk, pedestrian_stop, count, count_c, state, state_c, x, x_c
); |
input reset_n;
input clk;
input la_rue_sensor, orchard_sensor, pedestrian_sensor;
output reg la_rue_green, la_rue_yellow, la_rue_red;
output reg orchard_green, orchard_yellow, orchard_red;
output reg pedestrian_walk, pedestrian_stop;
reg [2:0] flash_count, flash_count_c;
reg pedestrian_queue, pedestrian_queue_c;
reg la_rue_sensor_ff, orchard_sensor_ff, pedestrian_sensor_ff;
reg la_rue_sensor_ff_c, orchard_sensor_ff_c, pedestrian_sensor_ff_c;
output reg [2:0] state;
output reg [2:0] state_c;
output reg [27:0] count;
output reg [27:0] count_c;
output reg [27:0] x;
output reg [27:0] x_c;
parameter LA_RUE_GREEN_st = 3'b000;
parameter LA_RUE_YELLOW_st = 3'b001;
parameter PED_WALK_st = 3'b010;
parameter PED_DONT_WALK_st = 3'b011;
parameter PED_OFF_st = 3'b100;
parameter ORCHARD_GREEN_st = 3'b101;
parameter ORCHARD_YELLOW_st = 3'b110;
always @(*) begin
state_c = state;
flash_count_c = flash_count;
la_rue_sensor_ff_c = la_rue_sensor;
orchard_sensor_ff_c = orchard_sensor;
pedestrian_sensor_ff_c = pedestrian_sensor_ff;
count_c = count + 1;
x_c = x + 1'b1;
if (pedestrian_sensor == 0) begin
pedestrian_sensor_ff_c = 1'b1;
end
case (state)
LA_RUE_GREEN_st: begin
la_rue_green = 1'b1;
la_rue_yellow = 1'b0;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (orchard_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if ((count >= 3'b011) & (count <= 3'b110) & la_rue_sensor_ff == 1'b0) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 3'b110) begin
state_c = LA_RUE_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
LA_RUE_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b1;
la_rue_red = 1'b0;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count == 3'b011) begin
if (pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (pedestrian_sensor_ff == 1'b0 & orchard_sensor_ff == 1'b1) begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_GREEN_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b1;
orchard_yellow = 1'b0;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b0) begin
if (count >= 3'b011 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
else if (la_rue_sensor_ff == 1'b1 | pedestrian_sensor_ff == 1'b1) begin
if (count >= 3'b001 & count <= 3'b110 & orchard_sensor_ff == 1'b0) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count > 3'b110) begin
state_c = ORCHARD_YELLOW_st;
count_c = 28'b0;
x_c = 28'b0;
end
end
end
ORCHARD_YELLOW_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b1;
orchard_red = 1'b0;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count == 3'b011) begin
state_c = LA_RUE_GREEN_st;
if (la_rue_sensor_ff == 1'b0 & pedestrian_sensor_ff == 1'b1) begin
state_c = PED_WALK_st;
end
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b1;
pedestrian_stop = 1'b0;
if (count > 3'b110) begin
state_c = PED_DONT_WALK_st;
flash_count_c = flash_count + 3'b001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_DONT_WALK_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b1;
if (count >= 3'b001) begin
state_c = PED_OFF_st;
flash_count_c = flash_count + 3'b001;
count_c = 28'b0;
x_c = 28'b0;
end
end
PED_OFF_st: begin
la_rue_green = 1'b0;
la_rue_yellow = 1'b0;
la_rue_red = 1'b1;
orchard_green = 1'b0;
orchard_yellow = 1'b0;
orchard_red = 1'b1;
pedestrian_walk = 1'b0;
pedestrian_stop = 1'b0;
if (count >= 3'b001 & flash_count < 3'b101) begin
flash_count_c = flash_count + 3'b001;
state_c = PED_DONT_WALK_st;
count_c = 28'b0;
x_c = 28'b0;
end
else if (count >= 3'b001 & flash_count >= 3'b101) begin
if (orchard_sensor_ff == 1'b0) begin
state_c = LA_RUE_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 3'b000;
pedestrian_sensor_ff_c = 1'b0;
end
else begin
state_c = ORCHARD_GREEN_st;
count_c = 28'b0;
x_c = 28'b0;
flash_count_c = 3'b000;
pedestrian_sensor_ff_c = 1'b0;
end
end
end
endcase
if (reset_n == 0) begin
state_c = 3'b000;
x_c = 28'd0;
count_c = 28'd0;
flash_count_c = 3'b000;
orchard_sensor_ff_c = 1'b0;
la_rue_sensor_ff_c = 1'b0;
pedestrian_sensor_ff_c = 1'b0;
end
end
always @( clk) begin
state <= #1 state_c;
count <= #1 count_c;
x <= #1 x_c;
flash_count <= #1 flash_count_c;
orchard_sensor_ff <= #1 orchard_sensor_ff_c;
la_rue_sensor_ff <= #1 la_rue_sensor_ff_c;
pedestrian_sensor_ff <= #1 pedestrian_sensor_ff_c;
end
endmodule | 0 |
3,588 | data/full_repos/permissive/105729488/Traffic.v | 105,729,488 | Traffic.v | v | 139 | 78 | [] | [] | [] | null | line:32: before: "e" | null | 1: b"%Error: data/full_repos/permissive/105729488/Traffic.v:62: Cannot find file containing module: 'state_machine'\nstate_machine lab6(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine.v\n data/full_repos/permissive/105729488,data/full_repos/permissive/105729488/state_machine.sv\n state_machine\n state_machine.v\n state_machine.sv\n obj_dir/state_machine\n obj_dir/state_machine.v\n obj_dir/state_machine.sv\n%Error: data/full_repos/permissive/105729488/Traffic.v:88: Cannot find file containing module: 'draw'\ndraw drawer(\n^~~~\n%Error: data/full_repos/permissive/105729488/Traffic.v:107: Cannot find file containing module: 'vga_pll'\nvga_pll pll_inst (\n^~~~~~~\n%Error: data/full_repos/permissive/105729488/Traffic.v:113: Cannot find file containing module: 'vga_timing'\nvga_timing timing(\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,372 | module | module lab6(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [1:0] KEY,
output [9:0] LEDR,
input [9:0] SW,
output reg [3:0] VGA_B,
output reg [3:0] VGA_G,
output reg VGA_HS,
output reg [3:0] VGA_R,
output reg VGA_VS
);
localparam X_BITS = 10;
localparam Y_BITS = 9;
wire clk;
wire reset_n;
wire h_sync, v_sync;
wire disp_ena;
wire [11:0] rgb;
wire [X_BITS-1:0] x;
wire [Y_BITS-1:0] y;
wire la_rue_green, la_rue_yellow, la_rue_red;
wire orchard_green, orchard_yellow, orchard_red;
wire pedestrian_walk, pedestrian_stop;
wire state;
wire [2:0] test;
wire [27:0] count;
state_machine lab6(
.reset_n(reset_n),
.clk(clk),
.la_rue_green(la_rue_green),
.la_rue_yellow(la_rue_yellow),
.la_rue_red(la_rue_red),
.orchard_green(orchard_green),
.orchard_yellow(orchard_yellow),
.orchard_red(orchard_red),
.pedestrian_walk(pedestrian_walk),
.pedestrian_stop(pedestrian_stop),
.la_rue_sensor(SW[0]),
.orchard_sensor(SW[1]),
.pedestrian_sensor(KEY[1]),
.count(count)
);
assign reset_n = KEY[0];
assign LEDR[9:0] = count[9:0];
draw drawer(
.clk (clk),
.reset_n (reset_n),
.x (x),
.y (y),
.la_rue_green (la_rue_green),
.la_rue_yellow (la_rue_yellow),
.la_rue_red (la_rue_red),
.orchard_green (orchard_green),
.orchard_yellow (orchard_yellow),
.orchard_red (orchard_red),
.pedestrian_walk (pedestrian_walk),
.pedestrian_stop (pedestrian_stop),
.rgb_out (rgb)
);
vga_pll pll_inst (
.inclk0 ( MAX10_CLK1_50 ),
.c0 ( clk )
);
vga_timing timing(
.pixel_clk (clk),
.reset_n (reset_n),
.h_sync (h_sync),
.v_sync (v_sync),
.disp_ena (disp_ena),
.column (x),
.row (y)
);
always @(posedge clk) begin
if (disp_ena == 1'b1) begin
VGA_R <= rgb[11:8];
VGA_G <= rgb[7:4];
VGA_B <= rgb[3:0];
end else begin
VGA_R <= 4'd0;
VGA_B <= 4'd0;
VGA_G <= 4'd0;
end
VGA_HS <= h_sync;
VGA_VS <= v_sync;
end
endmodule | module lab6(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [1:0] KEY,
output [9:0] LEDR,
input [9:0] SW,
output reg [3:0] VGA_B,
output reg [3:0] VGA_G,
output reg VGA_HS,
output reg [3:0] VGA_R,
output reg VGA_VS
); |
localparam X_BITS = 10;
localparam Y_BITS = 9;
wire clk;
wire reset_n;
wire h_sync, v_sync;
wire disp_ena;
wire [11:0] rgb;
wire [X_BITS-1:0] x;
wire [Y_BITS-1:0] y;
wire la_rue_green, la_rue_yellow, la_rue_red;
wire orchard_green, orchard_yellow, orchard_red;
wire pedestrian_walk, pedestrian_stop;
wire state;
wire [2:0] test;
wire [27:0] count;
state_machine lab6(
.reset_n(reset_n),
.clk(clk),
.la_rue_green(la_rue_green),
.la_rue_yellow(la_rue_yellow),
.la_rue_red(la_rue_red),
.orchard_green(orchard_green),
.orchard_yellow(orchard_yellow),
.orchard_red(orchard_red),
.pedestrian_walk(pedestrian_walk),
.pedestrian_stop(pedestrian_stop),
.la_rue_sensor(SW[0]),
.orchard_sensor(SW[1]),
.pedestrian_sensor(KEY[1]),
.count(count)
);
assign reset_n = KEY[0];
assign LEDR[9:0] = count[9:0];
draw drawer(
.clk (clk),
.reset_n (reset_n),
.x (x),
.y (y),
.la_rue_green (la_rue_green),
.la_rue_yellow (la_rue_yellow),
.la_rue_red (la_rue_red),
.orchard_green (orchard_green),
.orchard_yellow (orchard_yellow),
.orchard_red (orchard_red),
.pedestrian_walk (pedestrian_walk),
.pedestrian_stop (pedestrian_stop),
.rgb_out (rgb)
);
vga_pll pll_inst (
.inclk0 ( MAX10_CLK1_50 ),
.c0 ( clk )
);
vga_timing timing(
.pixel_clk (clk),
.reset_n (reset_n),
.h_sync (h_sync),
.v_sync (v_sync),
.disp_ena (disp_ena),
.column (x),
.row (y)
);
always @(posedge clk) begin
if (disp_ena == 1'b1) begin
VGA_R <= rgb[11:8];
VGA_G <= rgb[7:4];
VGA_B <= rgb[3:0];
end else begin
VGA_R <= 4'd0;
VGA_B <= 4'd0;
VGA_G <= 4'd0;
end
VGA_HS <= h_sync;
VGA_VS <= v_sync;
end
endmodule | 0 |
3,589 | data/full_repos/permissive/105772342/hdl/conv_8to16.v | 105,772,342 | conv_8to16.v | v | 107 | 84 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/c6213eb2-def5-4465-96bc-0f46e973e722.xml | null | 1,373 | module | module CONV_8TO16(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [15:0] data16_out,
output reg valid16_out,
input wire ready16_in
);
parameter [0:0]
S_WAIT_MSB = 0,
S_WAIT_LSB = 1;
reg state = S_WAIT_MSB;
reg state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
always @(posedge clk_in) begin
if((reset_in == 1'b 1)) begin
state <= S_WAIT_MSB;
msb <= 8'b00;
end
else begin
state <= state_next;
msb <= msb_next;
end
end
always @(state or msb or data8_in or valid8_in or ready16_in) begin
state_next <= state;
msb_next <= msb;
valid16_out <= 1'b 0;
case(state)
S_WAIT_LSB : begin
ready8_out <= ready16_in;
data16_out <= {msb,data8_in};
if((valid8_in == 1'b 1 && ready16_in == 1'b 1)) begin
valid16_out <= 1'b 1;
state_next <= S_WAIT_MSB;
end
end
default : begin
ready8_out <= 1'b 1;
data16_out <= {16{1'bX}};
if((valid8_in == 1'b 1)) begin
msb_next <= data8_in;
state_next <= S_WAIT_LSB;
end
end
endcase
end
endmodule | module CONV_8TO16(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [15:0] data16_out,
output reg valid16_out,
input wire ready16_in
); |
parameter [0:0]
S_WAIT_MSB = 0,
S_WAIT_LSB = 1;
reg state = S_WAIT_MSB;
reg state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
always @(posedge clk_in) begin
if((reset_in == 1'b 1)) begin
state <= S_WAIT_MSB;
msb <= 8'b00;
end
else begin
state <= state_next;
msb <= msb_next;
end
end
always @(state or msb or data8_in or valid8_in or ready16_in) begin
state_next <= state;
msb_next <= msb;
valid16_out <= 1'b 0;
case(state)
S_WAIT_LSB : begin
ready8_out <= ready16_in;
data16_out <= {msb,data8_in};
if((valid8_in == 1'b 1 && ready16_in == 1'b 1)) begin
valid16_out <= 1'b 1;
state_next <= S_WAIT_MSB;
end
end
default : begin
ready8_out <= 1'b 1;
data16_out <= {16{1'bX}};
if((valid8_in == 1'b 1)) begin
msb_next <= data8_in;
state_next <= S_WAIT_LSB;
end
end
endcase
end
endmodule | 0 |
3,590 | data/full_repos/permissive/105772342/hdl/conv_8to24.v | 105,772,342 | conv_8to24.v | v | 127 | 84 | [] | ['general public license', 'free software foundation'] | [] | null | line:86: before: "<=" | data/verilator_xmls/da76061a-322b-4ef2-b584-b94bc8fdfa5f.xml | null | 1,374 | module | module CONV_8TO24(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [23:0] data24_out,
output reg valid24_out,
input wire ready24_in
);
parameter [1:0]
S_WAIT_MSB = 0,
S_WAIT_MID = 1,
S_WAIT_LSB = 2;
reg [1:0] state = S_WAIT_MSB;
reg [1:0] state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
reg [7:0] mid = 0;
reg [7:0] mid_next;
always @(posedge clk_in) begin
if((reset_in == 1'b 1)) begin
state <= S_WAIT_MSB;
msb <= {8{1'b0}};
mid <= {8{1'b0}};
end
else begin
state <= state_next;
msb <= msb_next;
mid <= mid_next;
end
end
always @(state or msb or mid or data8_in or valid8_in or ready24_in) begin
state_next <= state;
msb_next <= msb;
mid_next <= mid;
valid24_out <= 1'b 0;
case(state)
S_WAIT_LSB : begin
ready8_out <= ready24_in;
data24_out <= {msb,mid,data8_in};
if((valid8_in == 1'b 1 && ready24_in == 1'b 1)) begin
valid24_out <= 1'b 1;
state_next <= S_WAIT_MSB;
end
end
S_WAIT_MID : begin
ready8_out <= 1'b 1;
data24_out <= {24{1'bX}};
if((valid8_in == 1'b 1)) begin
mid_next <= data8_in;
state_next <= S_WAIT_LSB;
end
end
default : begin
ready8_out <= 1'b 1;
data24_out <= {24{1'bX}};
if((valid8_in == 1'b 1)) begin
msb_next <= data8_in;
state_next <= S_WAIT_MID;
end
end
endcase
end
endmodule | module CONV_8TO24(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [23:0] data24_out,
output reg valid24_out,
input wire ready24_in
); |
parameter [1:0]
S_WAIT_MSB = 0,
S_WAIT_MID = 1,
S_WAIT_LSB = 2;
reg [1:0] state = S_WAIT_MSB;
reg [1:0] state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
reg [7:0] mid = 0;
reg [7:0] mid_next;
always @(posedge clk_in) begin
if((reset_in == 1'b 1)) begin
state <= S_WAIT_MSB;
msb <= {8{1'b0}};
mid <= {8{1'b0}};
end
else begin
state <= state_next;
msb <= msb_next;
mid <= mid_next;
end
end
always @(state or msb or mid or data8_in or valid8_in or ready24_in) begin
state_next <= state;
msb_next <= msb;
mid_next <= mid;
valid24_out <= 1'b 0;
case(state)
S_WAIT_LSB : begin
ready8_out <= ready24_in;
data24_out <= {msb,mid,data8_in};
if((valid8_in == 1'b 1 && ready24_in == 1'b 1)) begin
valid24_out <= 1'b 1;
state_next <= S_WAIT_MSB;
end
end
S_WAIT_MID : begin
ready8_out <= 1'b 1;
data24_out <= {24{1'bX}};
if((valid8_in == 1'b 1)) begin
mid_next <= data8_in;
state_next <= S_WAIT_LSB;
end
end
default : begin
ready8_out <= 1'b 1;
data24_out <= {24{1'bX}};
if((valid8_in == 1'b 1)) begin
msb_next <= data8_in;
state_next <= S_WAIT_MID;
end
end
endcase
end
endmodule | 0 |
3,591 | data/full_repos/permissive/105772342/tb/tb_conv8to16.v | 105,772,342 | tb_conv8to16.v | v | 93 | 126 | [] | [] | [] | null | line:23: before: "(" | null | 1: b'%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:25: syntax error, unexpected \'@\'\n @(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_conv_8to16.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:34: syntax error, unexpected \'@\'\n @(posedge clk) reset = 0;\n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:37: syntax error, unexpected \'@\'\n @(negedge clk) \n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:38: syntax error, unexpected \'(\', expecting IDENTIFIER\n stimulate(8\'h34, 1, 1); \n ^~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 1,375 | module | module tb_conv_8to16();
reg clk = 0;
reg reset = 1;
reg [7:0] data8;
reg valid8;
wire ready8;
wire [15:0] data16;
wire valid16;
reg ready16;
task stimulate(input [7:0] _data8, input _valid8, input _ready16);
begin
@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;
end
endtask
always #10 clk = ~clk;
initial begin
$dumpfile("tb_conv_8to16.vcd");
$dumpvars;
@(posedge clk) reset = 0;
stimulate(8'h12, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(16'h1234, 1, 1);
stimulate(8'h56, 0, 0);
`expect(16'hXXXX, 0, 1);
stimulate(8'h56, 1, 0);
`expect(16'hXXXX, 0, 1);
stimulate(8'h78, 0, 0);
`expect(16'h5678, 0, 0);
stimulate(8'h78, 0, 1);
`expect(16'h5678, 0, 1);
stimulate(8'h78, 1, 0);
`expect(16'h5678, 0, 0);
stimulate(8'h78, 1, 1);
`expect(16'h5678, 1, 1);
stimulate(8'hAB, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hBC, 1, 1);
`expect(16'hABBC, 1, 1);
stimulate(8'hCD, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hDE, 1, 1);
`expect(16'hCDDE, 1, 1);
stimulate(8'hEF, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hF0, 1, 1);
`expect(16'hEFF0, 1, 1);
stimulate(8'h01, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'h12, 1, 1);
`expect(16'h0112, 1, 1);
$finish;
end
CONV_8TO16 conv_8to16(
.clk_in(clk),
.reset_in(reset),
.data8_in(data8),
.valid8_in(valid8),
.ready8_out(ready8),
.data16_out(data16),
.valid16_out(valid16),
.ready16_in(ready16));
endmodule | module tb_conv_8to16(); |
reg clk = 0;
reg reset = 1;
reg [7:0] data8;
reg valid8;
wire ready8;
wire [15:0] data16;
wire valid16;
reg ready16;
task stimulate(input [7:0] _data8, input _valid8, input _ready16);
begin
@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;
end
endtask
always #10 clk = ~clk;
initial begin
$dumpfile("tb_conv_8to16.vcd");
$dumpvars;
@(posedge clk) reset = 0;
stimulate(8'h12, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(16'h1234, 1, 1);
stimulate(8'h56, 0, 0);
`expect(16'hXXXX, 0, 1);
stimulate(8'h56, 1, 0);
`expect(16'hXXXX, 0, 1);
stimulate(8'h78, 0, 0);
`expect(16'h5678, 0, 0);
stimulate(8'h78, 0, 1);
`expect(16'h5678, 0, 1);
stimulate(8'h78, 1, 0);
`expect(16'h5678, 0, 0);
stimulate(8'h78, 1, 1);
`expect(16'h5678, 1, 1);
stimulate(8'hAB, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hBC, 1, 1);
`expect(16'hABBC, 1, 1);
stimulate(8'hCD, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hDE, 1, 1);
`expect(16'hCDDE, 1, 1);
stimulate(8'hEF, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'hF0, 1, 1);
`expect(16'hEFF0, 1, 1);
stimulate(8'h01, 1, 1);
`expect(16'hXXXX, 0, 1);
stimulate(8'h12, 1, 1);
`expect(16'h0112, 1, 1);
$finish;
end
CONV_8TO16 conv_8to16(
.clk_in(clk),
.reset_in(reset),
.data8_in(data8),
.valid8_in(valid8),
.ready8_out(ready8),
.data16_out(data16),
.valid16_out(valid16),
.ready16_in(ready16));
endmodule | 0 |
3,592 | data/full_repos/permissive/105772342/tb/tb_conv8to24.v | 105,772,342 | tb_conv8to24.v | v | 109 | 126 | [] | [] | [] | null | line:23: before: "(" | null | 1: b'%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:25: syntax error, unexpected \'@\'\n @(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_conv_8to24.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:34: syntax error, unexpected \'@\'\n @(posedge clk) reset = 0;\n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:37: syntax error, unexpected \'@\'\n @(negedge clk) \n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:38: syntax error, unexpected \'(\', expecting IDENTIFIER\n stimulate(8\'h34, 1, 1); \n ^~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n' | 1,376 | module | module tb_conv_8to24();
reg clk = 0;
reg reset = 1;
reg [7:0] data8;
reg valid8;
wire ready8;
wire [23:0] data24;
wire valid24;
reg ready24;
task stimulate(input [7:0] _data8, input _valid8, input _ready24);
begin
@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;
end
endtask
always #10 clk = ~clk;
initial begin
$dumpfile("tb_conv_8to24.vcd");
$dumpvars;
@(posedge clk) reset = 0;
stimulate(8'h12, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'h123456, 1, 1);
stimulate(8'h78, 0, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h78, 1, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 0, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 1, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hBC, 0, 0);
`expect(24'h789ABC, 0, 0);
stimulate(8'hBC, 0, 1);
`expect(24'h789ABC, 0, 1);
stimulate(8'hBC, 1, 0);
`expect(24'h789ABC, 0, 0);
stimulate(8'hBC, 1, 1);
`expect(24'h789ABC, 1, 1);
stimulate(8'h12, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'h123456, 1, 1);
stimulate(8'h78, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hBC, 1, 1);
`expect(24'h789ABC, 1, 1);
stimulate(8'hDE, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hF0, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h12, 1, 1);
`expect(24'hDEF012, 1, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h78, 1, 1);
`expect(24'h345678, 1, 1);
$finish;
end
CONV_8TO24 conv_8to24(
.clk_in(clk),
.reset_in(reset),
.data8_in(data8),
.valid8_in(valid8),
.ready8_out(ready8),
.data24_out(data24),
.valid24_out(valid24),
.ready24_in(ready24));
endmodule | module tb_conv_8to24(); |
reg clk = 0;
reg reset = 1;
reg [7:0] data8;
reg valid8;
wire ready8;
wire [23:0] data24;
wire valid24;
reg ready24;
task stimulate(input [7:0] _data8, input _valid8, input _ready24);
begin
@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;
end
endtask
always #10 clk = ~clk;
initial begin
$dumpfile("tb_conv_8to24.vcd");
$dumpvars;
@(posedge clk) reset = 0;
stimulate(8'h12, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'h123456, 1, 1);
stimulate(8'h78, 0, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h78, 1, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 0, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 1, 0);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hBC, 0, 0);
`expect(24'h789ABC, 0, 0);
stimulate(8'hBC, 0, 1);
`expect(24'h789ABC, 0, 1);
stimulate(8'hBC, 1, 0);
`expect(24'h789ABC, 0, 0);
stimulate(8'hBC, 1, 1);
`expect(24'h789ABC, 1, 1);
stimulate(8'h12, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'h123456, 1, 1);
stimulate(8'h78, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h9A, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hBC, 1, 1);
`expect(24'h789ABC, 1, 1);
stimulate(8'hDE, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'hF0, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h12, 1, 1);
`expect(24'hDEF012, 1, 1);
stimulate(8'h34, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h56, 1, 1);
`expect(24'hXXXXXX, 0, 1);
stimulate(8'h78, 1, 1);
`expect(24'h345678, 1, 1);
$finish;
end
CONV_8TO24 conv_8to24(
.clk_in(clk),
.reset_in(reset),
.data8_in(data8),
.valid8_in(valid8),
.ready8_out(ready8),
.data24_out(data24),
.valid24_out(valid24),
.ready24_in(ready24));
endmodule | 0 |
3,593 | data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v | 105,824,537 | DDS24_Core_v0_0.v | v | 326 | 142 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:29: Cannot find include file: cypress.v\n`include "cypress.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v\n data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v.v\n data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v.sv\n cypress.v\n cypress.v.v\n cypress.v.sv\n obj_dir/cypress.v\n obj_dir/cypress.v.v\n obj_dir/cypress.v.sv\n%Warning-WIDTH: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:70: Value too large for 2 bit number: 10\n localparam CTRL_BUS = 2\'d10; \n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:163: Define or directive not defined: \'`FALSE\'\n cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE)) \n ^~~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:176: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_force_order(`TRUE)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:269: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:273: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:277: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:282: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:289: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:294: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:299: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF)) \n ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:305: Define or directive not defined: \'`TRUE\'\n cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF)) \n ^~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n' | 1,378 | module | module DDS24_Core_v0_0( load, en, ctrl, phase, clock, out1, out2, rdy1, rdy2, rfd );
parameter out1_width = 8'd8;
parameter out2_width = 8'd8;
localparam Hi1 = out1_width-1;
localparam Hi2 = out2_width-1;
input wire load;
input wire en;
input wire [22:0] ctrl;
input wire [7:0] phase;
input wire clock;
output wire [Hi1:0] out1;
output wire [Hi2:0] out2;
output wire rdy1;
output wire rdy2;
output wire rfd;
parameter out2_enable = 1'b0;
parameter hw_load = 1'b0;
parameter tune_word_h = 23'd1;
parameter out2_phase_h = 8'd0;
localparam CTRL_API = 2'b00;
localparam CTRL_HARDC = 2'b01;
localparam CTRL_BUS = 2'd10;
parameter [1:0] ControlFreq = CTRL_API;
parameter [1:0] ControlPhase = CTRL_API;
localparam ENMODE_AUTO = 2'b00;
localparam ENMODE_CRONLY = 2'b01;
localparam ENMODE_HWONLY = 2'b10;
localparam ENMODE_CR_HW = 2'b11;
parameter [1:0] EnableMode = ENMODE_CRONLY;
wire [22:0] tune_word;
wire [7:0] controlD;
wire ClockOutFromEnBlock;
reg [23:0] Acc;
reg [23:16] Ac1;
reg [23:16] Ac2;
generate
if(out2_enable==1'b1)
begin
always @(posedge ClockOutFromEnBlock) begin
Acc <= Acc+tune_word;
Ac1 <= Acc[23:16];
Ac2 <= Acc[23:16]+controlD;
end
assign out1 = Ac1[23:(23-Hi1)];
assign out2 = Ac2[23:(23-Hi2)];
end
else begin
always @(posedge ClockOutFromEnBlock) begin
Acc <= Acc+tune_word;
end
assign out1 = Acc[23:(23-Hi1)];
end
endgenerate
reg [Hi1:0] out1_old;
reg [Hi2:0] out2_old;
generate
if(out2_enable==1'b1)
begin
always @(posedge ClockOutFromEnBlock)
begin
out1_old <= out1;
out2_old <= out2;
end
assign rdy1 = |(out1 ^ out1_old) & ~clock;
assign rdy2 = |(out2 ^ out2_old) & ~clock;
end
else begin
always @(posedge ClockOutFromEnBlock)
begin
out1_old <= out1;
end
assign rdy1 = |(out1 ^ out1_old) & ~clock;
end
endgenerate
wire clock_en;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
clock_enable_block (
.clock_out(ClockOutFromEnBlock),
.clock_in(clock),
.enable(clock_en)
);
localparam CLOCK_ENABLE_BIT = 1'd0;
wire [7:0] ctrl8;
generate
if( (EnableMode == ENMODE_CRONLY) || (EnableMode == ENMODE_CR_HW) ) begin : sCTRLReg
cy_psoc3_control #(.cy_force_order(`TRUE))
ctrlreg( .control(ctrl8) );
end
endgenerate
wire control_enable; assign control_enable = ctrl8[CLOCK_ENABLE_BIT];
assign clock_en = (EnableMode == ENMODE_AUTO)? 1'b1:
(EnableMode == ENMODE_CRONLY)? control_enable:
(EnableMode == ENMODE_CR_HW)? (control_enable & en):
en;
generate
if (hw_load==1'b1) begin
wire s_load;
cy_psoc3_sync HWLoadSync (
.clock (ClockOutFromEnBlock),
.sc_in (load),
.sc_out (s_load));
assign rfd = s_load;
end
endgenerate
wire [23:0] control_cr;
wire [7:0] controlD_cr;
generate
if (ControlFreq==CTRL_API) assign tune_word = control_cr[22:0]; else
if (ControlFreq==CTRL_HARDC) assign tune_word = tune_word_h; else
if (hw_load==1'd0)
assign tune_word = ctrl[22:0];
else begin
reg[22:0] r_ctrl; always @(posedge load) r_ctrl <= ctrl[22:0];
assign tune_word = r_ctrl;
end
endgenerate
generate
if (ControlPhase==CTRL_API) assign controlD = controlD_cr; else
if (ControlPhase==CTRL_HARDC) assign controlD = out2_phase_h; else
if (hw_load==1'd0)
assign controlD = phase;
else begin
reg[7:0] r_phase; always @(posedge load) r_phase <= phase;
assign controlD = r_phase;
end
endgenerate
generate
if (hw_load==1'b0) begin: sControl
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseA(
.control(control_cr[7:0]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseB(
.control(control_cr[15:8]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseC(
.control(control_cr[23:16]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseD(
.control(controlD_cr));
end
else begin: sControl
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseA(
.control(control_cr[7:0]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseB(
.control(control_cr[15:8]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseC(
.control(control_cr[23:16]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseD(
.control(controlD_cr),
.clock(load) );
end
endgenerate
endmodule | module DDS24_Core_v0_0( load, en, ctrl, phase, clock, out1, out2, rdy1, rdy2, rfd ); |
parameter out1_width = 8'd8;
parameter out2_width = 8'd8;
localparam Hi1 = out1_width-1;
localparam Hi2 = out2_width-1;
input wire load;
input wire en;
input wire [22:0] ctrl;
input wire [7:0] phase;
input wire clock;
output wire [Hi1:0] out1;
output wire [Hi2:0] out2;
output wire rdy1;
output wire rdy2;
output wire rfd;
parameter out2_enable = 1'b0;
parameter hw_load = 1'b0;
parameter tune_word_h = 23'd1;
parameter out2_phase_h = 8'd0;
localparam CTRL_API = 2'b00;
localparam CTRL_HARDC = 2'b01;
localparam CTRL_BUS = 2'd10;
parameter [1:0] ControlFreq = CTRL_API;
parameter [1:0] ControlPhase = CTRL_API;
localparam ENMODE_AUTO = 2'b00;
localparam ENMODE_CRONLY = 2'b01;
localparam ENMODE_HWONLY = 2'b10;
localparam ENMODE_CR_HW = 2'b11;
parameter [1:0] EnableMode = ENMODE_CRONLY;
wire [22:0] tune_word;
wire [7:0] controlD;
wire ClockOutFromEnBlock;
reg [23:0] Acc;
reg [23:16] Ac1;
reg [23:16] Ac2;
generate
if(out2_enable==1'b1)
begin
always @(posedge ClockOutFromEnBlock) begin
Acc <= Acc+tune_word;
Ac1 <= Acc[23:16];
Ac2 <= Acc[23:16]+controlD;
end
assign out1 = Ac1[23:(23-Hi1)];
assign out2 = Ac2[23:(23-Hi2)];
end
else begin
always @(posedge ClockOutFromEnBlock) begin
Acc <= Acc+tune_word;
end
assign out1 = Acc[23:(23-Hi1)];
end
endgenerate
reg [Hi1:0] out1_old;
reg [Hi2:0] out2_old;
generate
if(out2_enable==1'b1)
begin
always @(posedge ClockOutFromEnBlock)
begin
out1_old <= out1;
out2_old <= out2;
end
assign rdy1 = |(out1 ^ out1_old) & ~clock;
assign rdy2 = |(out2 ^ out2_old) & ~clock;
end
else begin
always @(posedge ClockOutFromEnBlock)
begin
out1_old <= out1;
end
assign rdy1 = |(out1 ^ out1_old) & ~clock;
end
endgenerate
wire clock_en;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
clock_enable_block (
.clock_out(ClockOutFromEnBlock),
.clock_in(clock),
.enable(clock_en)
);
localparam CLOCK_ENABLE_BIT = 1'd0;
wire [7:0] ctrl8;
generate
if( (EnableMode == ENMODE_CRONLY) || (EnableMode == ENMODE_CR_HW) ) begin : sCTRLReg
cy_psoc3_control #(.cy_force_order(`TRUE))
ctrlreg( .control(ctrl8) );
end
endgenerate
wire control_enable; assign control_enable = ctrl8[CLOCK_ENABLE_BIT];
assign clock_en = (EnableMode == ENMODE_AUTO)? 1'b1:
(EnableMode == ENMODE_CRONLY)? control_enable:
(EnableMode == ENMODE_CR_HW)? (control_enable & en):
en;
generate
if (hw_load==1'b1) begin
wire s_load;
cy_psoc3_sync HWLoadSync (
.clock (ClockOutFromEnBlock),
.sc_in (load),
.sc_out (s_load));
assign rfd = s_load;
end
endgenerate
wire [23:0] control_cr;
wire [7:0] controlD_cr;
generate
if (ControlFreq==CTRL_API) assign tune_word = control_cr[22:0]; else
if (ControlFreq==CTRL_HARDC) assign tune_word = tune_word_h; else
if (hw_load==1'd0)
assign tune_word = ctrl[22:0];
else begin
reg[22:0] r_ctrl; always @(posedge load) r_ctrl <= ctrl[22:0];
assign tune_word = r_ctrl;
end
endgenerate
generate
if (ControlPhase==CTRL_API) assign controlD = controlD_cr; else
if (ControlPhase==CTRL_HARDC) assign controlD = out2_phase_h; else
if (hw_load==1'd0)
assign controlD = phase;
else begin
reg[7:0] r_phase; always @(posedge load) r_phase <= phase;
assign controlD = r_phase;
end
endgenerate
generate
if (hw_load==1'b0) begin: sControl
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseA(
.control(control_cr[7:0]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseB(
.control(control_cr[15:8]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseC(
.control(control_cr[23:16]));
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
ControlPhaseD(
.control(controlD_cr));
end
else begin: sControl
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseA(
.control(control_cr[7:0]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseB(
.control(control_cr[15:8]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseC(
.control(control_cr[23:16]),
.clock(load) );
cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ControlPhaseD(
.control(controlD_cr),
.clock(load) );
end
endgenerate
endmodule | 0 |
3,594 | data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v | 105,824,869 | DDS32_v0_0.v | v | 353 | 82 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:30: Cannot find include file: cypress.v\n`include "cypress.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v\n data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v.v\n data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v.sv\n cypress.v\n cypress.v.v\n cypress.v.sv\n obj_dir/cypress.v\n obj_dir/cypress.v.v\n obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:102: Define or directive not defined: \'`TRUE\'\n cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync\n ^~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_ALU_OP__ADD\'\n `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n ^\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_SRCA_A0\'\n `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_SRCB_D0\'\n `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:124: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n `CS_CMP_SEL_CFGA, \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_SRCA_A0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_SRCB_D0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:128: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n `CS_CMP_SEL_CFGA, \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_SRCA_A0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_SRCB_D0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:132: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n `CS_CMP_SEL_CFGA, \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_SRCA_A0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_SRCB_D0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:136: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n `CS_CMP_SEL_CFGA, \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_SRCA_A0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_SRCB_D0\'\n `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:139: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,379 | module | module DDS32_v0_0 (
drq,
outp,
clk,
res
);
output drq;
output outp;
input clk;
input res;
parameter BusWidth = 8'd8;
wire nc1,nc2,nc3,nc4,nc5,nc6,nc7,nc8,nc9, nc10, nc11, nc12;
localparam [7:0] DDS_8_BIT = 8'd8;
localparam [7:0] DDS_16_BIT = 8'd16;
localparam [7:0] DDS_24_BIT = 8'd24;
localparam [7:0] DDS_32_BIT = 8'd32;
wire co_msb;
assign drq = co_msb;
wire cmsb;
assign outp = cmsb;
wire op_clk;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
);
localparam [2:0] ACC_CMD_SUM = 3'b0;
wire [2:0] cs_addr;
assign cs_addr = ACC_CMD_SUM;
parameter dpconfig0 =
{
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
8'hFF, 8'h00,
8'hFF, 8'hFF,
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI,
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN,
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL
};
parameter dpconfig1 =
{
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
8'hFF, 8'h00,
8'hFF, 8'hFF,
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI,
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN,
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL
};
generate
if(BusWidth == DDS_8_BIT) begin : sD8
cy_psoc3_dp8 #(.cy_dpconfig_a (dpconfig0))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb(co_msb),
.cmsb(cmsb),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_16_BIT) begin : sD16
cy_psoc3_dp16 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc1}),
.cmsb({cmsb,nc2}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_24_BIT) begin : sD24
cy_psoc3_dp24 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1),
.cy_dpconfig_c (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc3,nc4}),
.cmsb({cmsb,nc5,nc6}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_32_BIT) begin : sD32
cy_psoc3_dp32 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1),
.cy_dpconfig_c (dpconfig1), .cy_dpconfig_d (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc7,nc8,nc9}),
.cmsb({cmsb,nc10,nc11,nc12}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
endgenerate
endmodule | module DDS32_v0_0 (
drq,
outp,
clk,
res
); |
output drq;
output outp;
input clk;
input res;
parameter BusWidth = 8'd8;
wire nc1,nc2,nc3,nc4,nc5,nc6,nc7,nc8,nc9, nc10, nc11, nc12;
localparam [7:0] DDS_8_BIT = 8'd8;
localparam [7:0] DDS_16_BIT = 8'd16;
localparam [7:0] DDS_24_BIT = 8'd24;
localparam [7:0] DDS_32_BIT = 8'd32;
wire co_msb;
assign drq = co_msb;
wire cmsb;
assign outp = cmsb;
wire op_clk;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
);
localparam [2:0] ACC_CMD_SUM = 3'b0;
wire [2:0] cs_addr;
assign cs_addr = ACC_CMD_SUM;
parameter dpconfig0 =
{
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
8'hFF, 8'h00,
8'hFF, 8'hFF,
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI,
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN,
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL
};
parameter dpconfig1 =
{
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA,
8'hFF, 8'h00,
8'hFF, 8'hFF,
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI,
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN,
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL
};
generate
if(BusWidth == DDS_8_BIT) begin : sD8
cy_psoc3_dp8 #(.cy_dpconfig_a (dpconfig0))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb(co_msb),
.cmsb(cmsb),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_16_BIT) begin : sD16
cy_psoc3_dp16 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc1}),
.cmsb({cmsb,nc2}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_24_BIT) begin : sD24
cy_psoc3_dp24 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1),
.cy_dpconfig_c (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc3,nc4}),
.cmsb({cmsb,nc5,nc6}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
else if(BusWidth <= DDS_32_BIT) begin : sD32
cy_psoc3_dp32 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1),
.cy_dpconfig_c (dpconfig1), .cy_dpconfig_d (dpconfig1))
DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc7,nc8,nc9}),
.cmsb({cmsb,nc10,nc11,nc12}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
end
endgenerate
endmodule | 0 |
3,595 | data/full_repos/permissive/105847195/combine.v | 105,847,195 | combine.v | v | 224 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 assign consumer_iclk = ~consumer_iclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 assign producer_iclk = ~producer_iclk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 assign clk = ~clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:96: Unsupported: Ignoring delay on this delayed statement.\n #5 producer_iclk = ~(producer_iclk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:137: Unsupported: Ignoring delay on this delayed statement.\n #30for(j=0;j<10;j++)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:151: Unsupported: Ignoring delay on this delayed statement.\n #0 last = last +1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:167: Unsupported: Ignoring delay on this delayed statement.\n #0 start = start +1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:200: Unsupported: Ignoring delay on this delayed statement.\n #1 consumer_req = 0;\n ^\n%Error: data/full_repos/permissive/105847195/combine.v:209: Unsupported or unknown PLI call: $monitor\n $monitor("data consumed : %d at time = %t", consumer_data,$time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:217: Unsupported: Ignoring delay on this delayed statement.\n #10 consumer_iclk = ~consumer_iclk;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,380 | module | module top();
reg consumer_iclk;
reg producer_iclk;
wire cr;
wire [3:0] cd;
wire [3:0] pd;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
begin
#5000 $finish;
end
producer p1(
pd
);
fifo f1(
cd,
pd,
cr
);
consumer c1(
cr,
cd
);
endmodule | module top(); |
reg consumer_iclk;
reg producer_iclk;
wire cr;
wire [3:0] cd;
wire [3:0] pd;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
begin
#5000 $finish;
end
producer p1(
pd
);
fifo f1(
cd,
pd,
cr
);
consumer c1(
cr,
cd
);
endmodule | 0 |
3,596 | data/full_repos/permissive/105847195/combine.v | 105,847,195 | combine.v | v | 224 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 assign consumer_iclk = ~consumer_iclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 assign producer_iclk = ~producer_iclk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 assign clk = ~clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:96: Unsupported: Ignoring delay on this delayed statement.\n #5 producer_iclk = ~(producer_iclk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:137: Unsupported: Ignoring delay on this delayed statement.\n #30for(j=0;j<10;j++)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:151: Unsupported: Ignoring delay on this delayed statement.\n #0 last = last +1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:167: Unsupported: Ignoring delay on this delayed statement.\n #0 start = start +1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:200: Unsupported: Ignoring delay on this delayed statement.\n #1 consumer_req = 0;\n ^\n%Error: data/full_repos/permissive/105847195/combine.v:209: Unsupported or unknown PLI call: $monitor\n $monitor("data consumed : %d at time = %t", consumer_data,$time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:217: Unsupported: Ignoring delay on this delayed statement.\n #10 consumer_iclk = ~consumer_iclk;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,380 | module | module producer (producer_data);
output producer_data;
reg producer_iclk;
reg [3:0] producer_data;
reg [3:0] i = 4'b0000;
always @(producer_iclk)
begin
producer_data = producer_data + 1;
end
initial
begin
producer_data = 0;
producer_iclk = 0;
end
always
begin
#5 producer_iclk = ~(producer_iclk);
end
endmodule | module producer (producer_data); |
output producer_data;
reg producer_iclk;
reg [3:0] producer_data;
reg [3:0] i = 4'b0000;
always @(producer_iclk)
begin
producer_data = producer_data + 1;
end
initial
begin
producer_data = 0;
producer_iclk = 0;
end
always
begin
#5 producer_iclk = ~(producer_iclk);
end
endmodule | 0 |
3,597 | data/full_repos/permissive/105847195/combine.v | 105,847,195 | combine.v | v | 224 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 assign consumer_iclk = ~consumer_iclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 assign producer_iclk = ~producer_iclk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 assign clk = ~clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:96: Unsupported: Ignoring delay on this delayed statement.\n #5 producer_iclk = ~(producer_iclk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:137: Unsupported: Ignoring delay on this delayed statement.\n #30for(j=0;j<10;j++)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:151: Unsupported: Ignoring delay on this delayed statement.\n #0 last = last +1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:167: Unsupported: Ignoring delay on this delayed statement.\n #0 start = start +1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:200: Unsupported: Ignoring delay on this delayed statement.\n #1 consumer_req = 0;\n ^\n%Error: data/full_repos/permissive/105847195/combine.v:209: Unsupported or unknown PLI call: $monitor\n $monitor("data consumed : %d at time = %t", consumer_data,$time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:217: Unsupported: Ignoring delay on this delayed statement.\n #10 consumer_iclk = ~consumer_iclk;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,380 | module | module fifo(consumer_data,producer_data, consumer_req);
input consumer_req;
input producer_data;
output consumer_data;
reg [3:0] consumer_data;
reg [3:0] producer_data;
reg consumer_req;
int i;
int j;
int last;
int start;
int diff;
int last_s;
int start_s;
reg [3:0] queue [9:0];
initial
begin
assign last_s = last % 10;
assign start_s = start % 10;
assign diff = last - start;
#30for(j=0;j<10;j++)
begin
end
end
always @ (producer_data)
if((diff < 10))
begin
begin
queue[last_s] = producer_data;
#0 last = last +1;
end
end else begin
$finish;
end
always @(consumer_req)
begin
if(consumer_req == 1)
begin
if(diff != 0)
begin
consumer_data = queue[start_s];
#0 start = start +1;
end
end
end
endmodule | module fifo(consumer_data,producer_data, consumer_req); |
input consumer_req;
input producer_data;
output consumer_data;
reg [3:0] consumer_data;
reg [3:0] producer_data;
reg consumer_req;
int i;
int j;
int last;
int start;
int diff;
int last_s;
int start_s;
reg [3:0] queue [9:0];
initial
begin
assign last_s = last % 10;
assign start_s = start % 10;
assign diff = last - start;
#30for(j=0;j<10;j++)
begin
end
end
always @ (producer_data)
if((diff < 10))
begin
begin
queue[last_s] = producer_data;
#0 last = last +1;
end
end else begin
$finish;
end
always @(consumer_req)
begin
if(consumer_req == 1)
begin
if(diff != 0)
begin
consumer_data = queue[start_s];
#0 start = start +1;
end
end
end
endmodule | 0 |
3,598 | data/full_repos/permissive/105847195/combine.v | 105,847,195 | combine.v | v | 224 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 assign consumer_iclk = ~consumer_iclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 assign producer_iclk = ~producer_iclk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 assign clk = ~clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:96: Unsupported: Ignoring delay on this delayed statement.\n #5 producer_iclk = ~(producer_iclk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:137: Unsupported: Ignoring delay on this delayed statement.\n #30for(j=0;j<10;j++)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:151: Unsupported: Ignoring delay on this delayed statement.\n #0 last = last +1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:167: Unsupported: Ignoring delay on this delayed statement.\n #0 start = start +1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:200: Unsupported: Ignoring delay on this delayed statement.\n #1 consumer_req = 0;\n ^\n%Error: data/full_repos/permissive/105847195/combine.v:209: Unsupported or unknown PLI call: $monitor\n $monitor("data consumed : %d at time = %t", consumer_data,$time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:217: Unsupported: Ignoring delay on this delayed statement.\n #10 consumer_iclk = ~consumer_iclk;\n ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,380 | module | module consumer(consumer_req,consumer_data);
input consumer_data;
output consumer_req;
reg consumer_iclk;
reg [3:0] consumer_data;
reg consumer_req;
always @(consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
begin
consumer_req=0;
consumer_iclk =1;
$monitor("data consumed : %d at time = %t", consumer_data,$time);
end
always
begin
#10 consumer_iclk = ~consumer_iclk;
end
endmodule | module consumer(consumer_req,consumer_data); |
input consumer_data;
output consumer_req;
reg consumer_iclk;
reg [3:0] consumer_data;
reg consumer_req;
always @(consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
begin
consumer_req=0;
consumer_iclk =1;
$monitor("data consumed : %d at time = %t", consumer_data,$time);
end
always
begin
#10 consumer_iclk = ~consumer_iclk;
end
endmodule | 0 |
3,599 | data/full_repos/permissive/105847195/consumer.v | 105,847,195 | consumer.v | v | 25 | 59 | [] | [] | [] | [(1, 25)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/consumer.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1 consumer_req = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105847195/consumer.v:23: Unsupported or unknown PLI call: $monitor\n $monitor("data consumed : %b", consumer_data);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,381 | module | module consumer(consumer_iclk,consumer_req,consumer_data);
input consumer_iclk;
input consumer_data;
output consumer_req;
wire consumer_iclk;
wire [3:0] consumer_data;
reg consumer_req;
always @( consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
$monitor("data consumed : %b", consumer_data);
endmodule | module consumer(consumer_iclk,consumer_req,consumer_data); |
input consumer_iclk;
input consumer_data;
output consumer_req;
wire consumer_iclk;
wire [3:0] consumer_data;
reg consumer_req;
always @( consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
$monitor("data consumed : %b", consumer_data);
endmodule | 0 |
3,600 | data/full_repos/permissive/105847195/fifo.v | 105,847,195 | fifo.v | v | 88 | 97 | [] | [] | [] | null | line:380: before: "/" | null | 1: b'%Error: data/full_repos/permissive/105847195/fifo.v:72: syntax error, unexpected endtask\nendtask\n^~~~~~~\n%Error: Cannot continue\n' | 1,382 | module | module fifo( consumer_data, consumer_req, producer_data);
input consumer_req;
output consumer_data;
input producer_data;
wire [3:0] producer_data;
wire consumer_req;
reg consumer_data;
reg [3:0] stack [0:9];
int start = 0;
int last = 0;
int start_s;
int last_s;
initial
begin
last = 0;
start = 0;
assign last_s = (last%10);
assign start_s = (start%10);
end
task add_data;
begin
stack[last] = producer_data;
assign last = last +1 ;
end
endtask
task pop_data;
begin
start = start +1;
consumer_data = stack[start];
end
endtask
task check_empty;
begin
if((last - start)==1)
begin
consumer_data = 0;
end
else
begin
pop_data;
end
end
endtask
task check_full;
begin
if((last-start) == 9)
begin
$finish;
end else begin
add_data;
end
endtask
always @(consumer_req)
begin
check_empty;
end
always@(producer_data)
begin
check_full;
end
endmodule | module fifo( consumer_data, consumer_req, producer_data); |
input consumer_req;
output consumer_data;
input producer_data;
wire [3:0] producer_data;
wire consumer_req;
reg consumer_data;
reg [3:0] stack [0:9];
int start = 0;
int last = 0;
int start_s;
int last_s;
initial
begin
last = 0;
start = 0;
assign last_s = (last%10);
assign start_s = (start%10);
end
task add_data;
begin
stack[last] = producer_data;
assign last = last +1 ;
end
endtask
task pop_data;
begin
start = start +1;
consumer_data = stack[start];
end
endtask
task check_empty;
begin
if((last - start)==1)
begin
consumer_data = 0;
end
else
begin
pop_data;
end
end
endtask
task check_full;
begin
if((last-start) == 9)
begin
$finish;
end else begin
add_data;
end
endtask
always @(consumer_req)
begin
check_empty;
end
always@(producer_data)
begin
check_full;
end
endmodule | 0 |
3,601 | data/full_repos/permissive/105847195/producer.v | 105,847,195 | producer.v | v | 25 | 52 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Error: data/full_repos/permissive/105847195/producer.v:20: Unsupported or unknown PLI call: $monitor\n $monitor("data produced = %b",producer_data);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,383 | module | module producer (producer_iclk,producer_data);
input producer_iclk;
output producer_data;
wire producer_iclk;
reg [3:0] producer_data;
reg [3:0] i = 4'b0000;
always @ (producer_iclk)
begin
producer_data = i;
i = (i + 4'b0001);
end
initial
begin
$monitor("data produced = %b",producer_data);
end
endmodule | module producer (producer_iclk,producer_data); |
input producer_iclk;
output producer_data;
wire producer_iclk;
reg [3:0] producer_data;
reg [3:0] i = 4'b0000;
always @ (producer_iclk)
begin
producer_data = i;
i = (i + 4'b0001);
end
initial
begin
$monitor("data produced = %b",producer_data);
end
endmodule | 0 |
3,602 | data/full_repos/permissive/105847195/top.v | 105,847,195 | top.v | v | 33 | 49 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/105847195/top.v:1: Cannot find include file: producer\n`include "producer" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer\n data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer.v\n data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer.sv\n producer\n producer.v\n producer.sv\n obj_dir/producer\n obj_dir/producer.v\n obj_dir/producer.sv\n%Error: data/full_repos/permissive/105847195/top.v:2: Cannot find include file: fifo\n`include "fifo" \n ^~~~~~\n%Error: data/full_repos/permissive/105847195/top.v:3: Cannot find include file: consumer\n`include "consumer" \n ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 assign consumer_iclk = ~consumer_iclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 assign producer_iclk = ~producer_iclk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1 assign clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:31: Unsupported: Ignoring delay on this delayed statement.\n #50 $finish;\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 1,385 | module | module top();
reg consumer_iclk;
reg producer_iclk;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
#50 $finish;
endmodule | module top(); |
reg consumer_iclk;
reg producer_iclk;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
#50 $finish;
endmodule | 0 |
3,604 | data/full_repos/permissive/105869704/cpu.v | 105,869,704 | cpu.v | v | 280 | 88 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/105869704/cpu.v:17: Cannot find include file: alu.v\n`include "alu.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/alu.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/alu.v.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/alu.v.sv\n alu.v\n alu.v.v\n alu.v.sv\n obj_dir/alu.v\n obj_dir/alu.v.v\n obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/105869704/cpu.v:18: Cannot find include file: pcounter.v\n`include "pcounter.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105869704/cpu.v:19: Cannot find include file: ram.v\n`include "ram.v" \n ^~~~~~~\n%Error: data/full_repos/permissive/105869704/cpu.v:20: Cannot find include file: uart-tx.v\n`include "uart-tx.v" \n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 1,387 | module | module cpu(
input clk,
output uart_tx_wire);
localparam INSTR_SIZE = 4;
localparam WIDTH = 8;
localparam ADDRESS_WIDTH = WIDTH - INSTR_SIZE;
localparam NOP = 4'b0000;
localparam LDA = 4'b0001;
localparam ADD = 4'b0010;
localparam SUB = 4'b0011;
localparam STA = 4'b0100;
localparam OUT = 4'b0101;
localparam JMP = 4'b0110;
localparam LDI = 4'b0111;
localparam JC = 4'b1000;
localparam SHLA= 4'b1001;
localparam MULA= 4'b1010;
localparam HLT = 4'b1111;
localparam j = 0;
localparam co = 1;
localparam ce = 2;
localparam oi = 3;
localparam su = 4;
localparam ao = 5;
localparam io = 6;
localparam ro = 7;
localparam ri = 8;
localparam mi = 9;
localparam she = 10;
localparam mul = 11;
localparam SIG_COUNT = mul + 1;
localparam STAGE_T0 = 0;
localparam STAGE_T1 = 1;
localparam STAGE_T2 = 2;
localparam STAGE_T3 = 3;
localparam STAGE_T4 = 4;
localparam STAGE_COUNT = STAGE_T4 + 1;
localparam STAGE_WIDTH = $clog2(STAGE_COUNT);
localparam rst_size = 5;
localparam rst_max = (1 << 5) - 1;
reg [rst_size : 0] rst_cnt = 0;
reg rstn = 0;
reg [WIDTH-1 : 0] ir;
reg [SIG_COUNT-1 : 0] ctrl_reg;
reg [STAGE_WIDTH-1 : 0] stage_reg;
reg [WIDTH-1 : 0] reg_a;
reg [WIDTH-1 : 0] reg_b;
reg carry_status;
wire [WIDTH-1 : 0] alu_out;
wire alu_carry;
wire [ADDRESS_WIDTH-1 : 0] pc_in;
wire [ADDRESS_WIDTH-1 : 0] pc_out;
wire [WIDTH-1 : 0] mem_in;
wire [WIDTH-1 : 0] mem_out;
wire [WIDTH-1 : 0] mem_addr;
wire tx_idle;
pcounter #(.ADDRESS_WIDTH(ADDRESS_WIDTH)) pc(
.rst(!rstn),
.clk(clk),
.enable(ctrl_reg[ce]),
.jump(ctrl_reg[j]),
.out_enable(ctrl_reg[co]),
.bus_in(pc_in),
.bus_out(pc_out));
alu #(.WIDTH(WIDTH)) alu(
.a(reg_a),
.b(reg_b),
.mul_enable(ctrl_reg[mul]),
.sub_enable(ctrl_reg[su]),
.shift_enable(ctrl_reg[she]),
.shift_pos(ir[2 : 0]),
.result(alu_out),
.carry_out(alu_carry));
ram #(.WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) memory(
.clk(clk),
.enable(ctrl_reg[ro]),
.write_enable(ctrl_reg[ri]),
.addr(mem_addr),
.data_in(mem_in),
.data_out(mem_out));
uarttx uart(
.rst(!rstn),
.clk(clk),
.tx_start(ctrl_reg[oi]),
.tx_byte(reg_a),
.tx(uart_tx_wire),
.tx_ready(tx_idle));
assign pc_in = (ctrl_reg[j] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] : 0;
assign mem_addr = (ctrl_reg[mi] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] :
(ctrl_reg[mi] && ctrl_reg[co]) ? pc_out : 0;
assign mem_in = (ctrl_reg[ri] && ctrl_reg[ao]) ? reg_a : 0;
always @(posedge clk) begin
if (rst_cnt != rst_max) begin
rst_cnt <= rst_cnt + 1;
end else begin
rstn <= 1;
end
end
always @(posedge clk) begin
if (rstn) begin
case (stage_reg)
STAGE_T0: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << co);
stage_reg <= STAGE_T1;
end
STAGE_T1: begin
ctrl_reg <= 1 << ce;
ir <= mem_out;
stage_reg <= STAGE_T2;
end
STAGE_T2: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
ctrl_reg <= (1 << mul);
stage_reg <= STAGE_T3;
end
SHLA: begin
ctrl_reg <= (1 << she);
stage_reg <= STAGE_T3;
end
LDA: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
STA: begin
ctrl_reg <= (1 << ri) | (1 << ao) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
SUB: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
OUT: begin
ctrl_reg <= 1 << oi;
stage_reg <= STAGE_T3;
end
JMP: begin
ctrl_reg <= (1 << j) | (1 << io);
stage_reg <= STAGE_T0;
end
JC: begin
if (carry_status) begin
ctrl_reg <= (1 << j) | (1 << io);
end else begin
ctrl_reg <= 0;
end
stage_reg <= STAGE_T0;
end
LDI: begin
ctrl_reg <= 0;
reg_a <= {4'b0, ir[3 : 0]};
stage_reg <= STAGE_T0;
end
NOP: begin
ctrl_reg <= 0;
stage_reg <= STAGE_T0;
end
HLT: begin
ctrl_reg <= 0;
stage_reg <= STAGE_COUNT;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T3: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SHLA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
LDA: begin
reg_a <= mem_out;
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= 0;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
SUB: begin
ctrl_reg <= 1 << su;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
OUT: begin
ctrl_reg <= 0;
if (tx_idle) begin
stage_reg <= STAGE_T0;
end else begin
stage_reg <= STAGE_T3;
end
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T4: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
ADD: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SUB: begin
reg_a <= alu_out;
stage_reg <= STAGE_T0;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end else begin
ir <= 0;
carry_status <= 0;
ctrl_reg <= 0;
reg_a <= 0;
reg_b <= 0;
stage_reg <= STAGE_T0;
end
end
endmodule | module cpu(
input clk,
output uart_tx_wire); |
localparam INSTR_SIZE = 4;
localparam WIDTH = 8;
localparam ADDRESS_WIDTH = WIDTH - INSTR_SIZE;
localparam NOP = 4'b0000;
localparam LDA = 4'b0001;
localparam ADD = 4'b0010;
localparam SUB = 4'b0011;
localparam STA = 4'b0100;
localparam OUT = 4'b0101;
localparam JMP = 4'b0110;
localparam LDI = 4'b0111;
localparam JC = 4'b1000;
localparam SHLA= 4'b1001;
localparam MULA= 4'b1010;
localparam HLT = 4'b1111;
localparam j = 0;
localparam co = 1;
localparam ce = 2;
localparam oi = 3;
localparam su = 4;
localparam ao = 5;
localparam io = 6;
localparam ro = 7;
localparam ri = 8;
localparam mi = 9;
localparam she = 10;
localparam mul = 11;
localparam SIG_COUNT = mul + 1;
localparam STAGE_T0 = 0;
localparam STAGE_T1 = 1;
localparam STAGE_T2 = 2;
localparam STAGE_T3 = 3;
localparam STAGE_T4 = 4;
localparam STAGE_COUNT = STAGE_T4 + 1;
localparam STAGE_WIDTH = $clog2(STAGE_COUNT);
localparam rst_size = 5;
localparam rst_max = (1 << 5) - 1;
reg [rst_size : 0] rst_cnt = 0;
reg rstn = 0;
reg [WIDTH-1 : 0] ir;
reg [SIG_COUNT-1 : 0] ctrl_reg;
reg [STAGE_WIDTH-1 : 0] stage_reg;
reg [WIDTH-1 : 0] reg_a;
reg [WIDTH-1 : 0] reg_b;
reg carry_status;
wire [WIDTH-1 : 0] alu_out;
wire alu_carry;
wire [ADDRESS_WIDTH-1 : 0] pc_in;
wire [ADDRESS_WIDTH-1 : 0] pc_out;
wire [WIDTH-1 : 0] mem_in;
wire [WIDTH-1 : 0] mem_out;
wire [WIDTH-1 : 0] mem_addr;
wire tx_idle;
pcounter #(.ADDRESS_WIDTH(ADDRESS_WIDTH)) pc(
.rst(!rstn),
.clk(clk),
.enable(ctrl_reg[ce]),
.jump(ctrl_reg[j]),
.out_enable(ctrl_reg[co]),
.bus_in(pc_in),
.bus_out(pc_out));
alu #(.WIDTH(WIDTH)) alu(
.a(reg_a),
.b(reg_b),
.mul_enable(ctrl_reg[mul]),
.sub_enable(ctrl_reg[su]),
.shift_enable(ctrl_reg[she]),
.shift_pos(ir[2 : 0]),
.result(alu_out),
.carry_out(alu_carry));
ram #(.WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) memory(
.clk(clk),
.enable(ctrl_reg[ro]),
.write_enable(ctrl_reg[ri]),
.addr(mem_addr),
.data_in(mem_in),
.data_out(mem_out));
uarttx uart(
.rst(!rstn),
.clk(clk),
.tx_start(ctrl_reg[oi]),
.tx_byte(reg_a),
.tx(uart_tx_wire),
.tx_ready(tx_idle));
assign pc_in = (ctrl_reg[j] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] : 0;
assign mem_addr = (ctrl_reg[mi] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] :
(ctrl_reg[mi] && ctrl_reg[co]) ? pc_out : 0;
assign mem_in = (ctrl_reg[ri] && ctrl_reg[ao]) ? reg_a : 0;
always @(posedge clk) begin
if (rst_cnt != rst_max) begin
rst_cnt <= rst_cnt + 1;
end else begin
rstn <= 1;
end
end
always @(posedge clk) begin
if (rstn) begin
case (stage_reg)
STAGE_T0: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << co);
stage_reg <= STAGE_T1;
end
STAGE_T1: begin
ctrl_reg <= 1 << ce;
ir <= mem_out;
stage_reg <= STAGE_T2;
end
STAGE_T2: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
ctrl_reg <= (1 << mul);
stage_reg <= STAGE_T3;
end
SHLA: begin
ctrl_reg <= (1 << she);
stage_reg <= STAGE_T3;
end
LDA: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
STA: begin
ctrl_reg <= (1 << ri) | (1 << ao) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
SUB: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
OUT: begin
ctrl_reg <= 1 << oi;
stage_reg <= STAGE_T3;
end
JMP: begin
ctrl_reg <= (1 << j) | (1 << io);
stage_reg <= STAGE_T0;
end
JC: begin
if (carry_status) begin
ctrl_reg <= (1 << j) | (1 << io);
end else begin
ctrl_reg <= 0;
end
stage_reg <= STAGE_T0;
end
LDI: begin
ctrl_reg <= 0;
reg_a <= {4'b0, ir[3 : 0]};
stage_reg <= STAGE_T0;
end
NOP: begin
ctrl_reg <= 0;
stage_reg <= STAGE_T0;
end
HLT: begin
ctrl_reg <= 0;
stage_reg <= STAGE_COUNT;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T3: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SHLA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
LDA: begin
reg_a <= mem_out;
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= 0;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
SUB: begin
ctrl_reg <= 1 << su;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
OUT: begin
ctrl_reg <= 0;
if (tx_idle) begin
stage_reg <= STAGE_T0;
end else begin
stage_reg <= STAGE_T3;
end
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T4: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
ADD: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SUB: begin
reg_a <= alu_out;
stage_reg <= STAGE_T0;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end else begin
ir <= 0;
carry_status <= 0;
ctrl_reg <= 0;
reg_a <= 0;
reg_b <= 0;
stage_reg <= STAGE_T0;
end
end
endmodule | 13 |
3,605 | data/full_repos/permissive/105869704/fadder.v | 105,869,704 | fadder.v | v | 46 | 78 | [] | [] | [] | [(17, 45)] | null | data/verilator_xmls/0584d66b-f092-4531-8600-490385ec4b2c.xml | null | 1,388 | module | module fadder(
input [WIDTH-1 : 0] a,
input [WIDTH - 1 : 0] b,
input sub_enable,
input carry_in,
output [WIDTH - 1 : 0] res,
output carry_out);
parameter WIDTH = 8;
wire [WIDTH - 1 : 0] carry;
wire [WIDTH - 1 : 0] b_in;
assign carry_out = carry[WIDTH-1];
assign b_in = sub_enable ? ~(b) : b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry_in;
assign carry[i] = ((a[i] ^ b_in[i]) & carry_in) | (a[i] & b_in[i]);
end else begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry[i-1];
assign carry[i] = ((a[i] ^ b_in[i]) & carry[i-1]) | (a[i] & b_in[i]);
end
end
endgenerate
endmodule | module fadder(
input [WIDTH-1 : 0] a,
input [WIDTH - 1 : 0] b,
input sub_enable,
input carry_in,
output [WIDTH - 1 : 0] res,
output carry_out); |
parameter WIDTH = 8;
wire [WIDTH - 1 : 0] carry;
wire [WIDTH - 1 : 0] b_in;
assign carry_out = carry[WIDTH-1];
assign b_in = sub_enable ? ~(b) : b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry_in;
assign carry[i] = ((a[i] ^ b_in[i]) & carry_in) | (a[i] & b_in[i]);
end else begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry[i-1];
assign carry[i] = ((a[i] ^ b_in[i]) & carry[i-1]) | (a[i] & b_in[i]);
end
end
endgenerate
endmodule | 13 |
3,610 | data/full_repos/permissive/105869704/top.v | 105,869,704 | top.v | v | 28 | 76 | [] | [] | [] | [(81, 109), (126, 139), (141, 193), (195, 237), (254, 279), (296, 324), (341, 475), (477, 734), (736, 744)] | null | null | 1: b'%Error: data/full_repos/permissive/105869704/top.v:17: Cannot find include file: cpu.v\n`include "cpu.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/cpu.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/cpu.v.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/cpu.v.sv\n cpu.v\n cpu.v.v\n cpu.v.sv\n obj_dir/cpu.v\n obj_dir/cpu.v.v\n obj_dir/cpu.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,393 | module | module top(
input clk,
output uart_tx_line);
cpu node(
.clk(clk),
.uart_tx_wire(uart_tx_line));
endmodule | module top(
input clk,
output uart_tx_line); |
cpu node(
.clk(clk),
.uart_tx_wire(uart_tx_line));
endmodule | 13 |
3,611 | data/full_repos/permissive/105869704/top_test_fibonacci.v | 105,869,704 | top_test_fibonacci.v | v | 100 | 90 | [] | [] | [] | [(99, 127), (144, 157), (159, 211), (213, 255), (272, 297), (314, 342), (359, 493), (495, 752), (754, 762), (764, 842)] | null | null | 1: b'%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:19: Cannot find include file: top.v\n`include "top.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v.v\n data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v.sv\n top.v\n top.v.v\n top.v.sv\n obj_dir/top.v\n obj_dir/top.v.v\n obj_dir/top.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/105869704/top_test_fibonacci.v:50: Unsupported: Ignoring delay on this delayed statement.\n always #2 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105869704/top_test_fibonacci.v:51: Unsupported: Ignoring delay on this delayed statement.\n always #4 uart_clk = !uart_clk;\n ^\n%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("top_test_fibonacci.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 1,395 | module | module top_test_fibonacci;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test_fibonacci.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule | module top_test_fibonacci; |
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test_fibonacci.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule | 13 |
3,615 | data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v | 105,948,944 | CounterUp_TestBench.v | v | 77 | 84 | [] | [] | [] | [(22, 76)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:48: Unsupported: Ignoring delay on this delayed statement.\n #1000000\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1000000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1000000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:61: Unsupported: Ignoring delay on this delayed statement.\n #1000000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:66: Unsupported: Ignoring delay on this delayed statement.\n #1500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 clock = ~clock; \n ^\n%Error: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:36: Cannot find file containing module: \'counter_up\'\n counter_up U2(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up.v\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up.sv\n counter_up\n counter_up.v\n counter_up.sv\n obj_dir/counter_up\n obj_dir/counter_up.v\n obj_dir/counter_up.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,404 | module | module CounterUp_TestBench(
);
reg clock = 0;
reg reset = 0;
reg [27:0] counterPeriod = 0;
wire [27:0] countedUpTo;
parameter [27:0] PERIOD = 28'd1000000;
parameter [27:0] HALF_PERIOD = PERIOD >> 1;
parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
parameter [27:0] PERC75_PERIOD = HALF_PERIOD + QUARTER_PERIOD;
counter_up U2(
.clock(clock),
.reset(reset),
.counterPeriod(counterPeriod),
.countedUpTo(countedUpTo)
);
initial
begin
clock <=0;
counterPeriod <= 28'd0;
reset <= 0;
#1000000
counterPeriod <= PERIOD;
#1000000
reset = 1;
reset = 0;
counterPeriod = HALF_PERIOD;
#1000000
reset <= 1;
reset <= 0;
counterPeriod <= QUARTER_PERIOD;
#1000000
reset <= 1;
reset <= 0;
counterPeriod <= PERC75_PERIOD;
#1500000
reset = 1;
reset = 0;
counterPeriod = 0;
end
always
#1 clock = ~clock;
endmodule | module CounterUp_TestBench(
); |
reg clock = 0;
reg reset = 0;
reg [27:0] counterPeriod = 0;
wire [27:0] countedUpTo;
parameter [27:0] PERIOD = 28'd1000000;
parameter [27:0] HALF_PERIOD = PERIOD >> 1;
parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
parameter [27:0] PERC75_PERIOD = HALF_PERIOD + QUARTER_PERIOD;
counter_up U2(
.clock(clock),
.reset(reset),
.counterPeriod(counterPeriod),
.countedUpTo(countedUpTo)
);
initial
begin
clock <=0;
counterPeriod <= 28'd0;
reset <= 0;
#1000000
counterPeriod <= PERIOD;
#1000000
reset = 1;
reset = 0;
counterPeriod = HALF_PERIOD;
#1000000
reset <= 1;
reset <= 0;
counterPeriod <= QUARTER_PERIOD;
#1000000
reset <= 1;
reset <= 0;
counterPeriod <= PERC75_PERIOD;
#1500000
reset = 1;
reset = 0;
counterPeriod = 0;
end
always
#1 clock = ~clock;
endmodule | 1 |
3,616 | data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v | 105,948,944 | H_Bridge_v2_testBench.v | v | 140 | 84 | [] | [] | [] | [(29, 139)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:79: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:85: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:91: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:97: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:103: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:109: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:115: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:121: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:127: Unsupported: Ignoring delay on this delayed statement.\n #500000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:137: Unsupported: Ignoring delay on this delayed statement.\n #1 clock_Main_reg = ~clock_Main_reg;\n ^\n%Error: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:52: Cannot find file containing module: \'H_Bridge_v2\'\n H_Bridge_v2 H1(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2.v\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2.sv\n H_Bridge_v2\n H_Bridge_v2.v\n H_Bridge_v2.sv\n obj_dir/H_Bridge_v2\n obj_dir/H_Bridge_v2.v\n obj_dir/H_Bridge_v2.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,405 | module | module H_Bridge_testBench(
);
reg clock_Main_reg;
reg [3:0]movingDirection_reg;
reg [5:0]motorSpeed_reg, currentSensing_reg;
wire enA_wire, enB_wire, in1_wire, in2_wire, in3_wire, in4_wire;
parameter INTERTIAL_STOP = 4'b0000;
parameter HARD_STOP = 4'b1111;
parameter FORWARD = 4'b0110;
parameter REVERSE = 4'b1001;
parameter TURN_RIGHT = 4'b0101;
parameter TURN_LEFT = 4'b1010;
H_Bridge_v2 H1(
.clock(clock_Main_reg),
.movingDirection(movingDirection_reg),
.motorSpeed(motorSpeed_reg),
.currentSensing(currentSensing_reg),
.enA(enA_wire),
.enB(enB_wire),
.in1(in1_wire),
.in2(in2_wire),
.in3(in3_wire),
.in4(in4_wire)
);
initial
begin
clock_Main_reg <= 0;
movingDirection_reg <= INTERTIAL_STOP;
motorSpeed_reg[2:0] <= 3'b000;
motorSpeed_reg[5:3] <= 3'b000;
currentSensing_reg <= 0;
#10
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= REVERSE;
motorSpeed_reg[2:0] <= 3'b110;
motorSpeed_reg[5:3] <= 3'b110;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_RIGHT;
motorSpeed_reg[2:0] <= 3'b101;
motorSpeed_reg[5:3] <= 3'b101;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_LEFT;
motorSpeed_reg[2:0] <= 3'b100;
motorSpeed_reg[5:3] <= 3'b100;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_LEFT;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 1;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b011;
motorSpeed_reg[5:3] <= 3'b011;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b110;
motorSpeed_reg[5:3] <= 3'b110;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= INTERTIAL_STOP;
motorSpeed_reg[2:0] <= 3'b000;
motorSpeed_reg[5:3] <= 3'b000;
currentSensing_reg <= 0;
end
always
#1 clock_Main_reg = ~clock_Main_reg;
endmodule | module H_Bridge_testBench(
); |
reg clock_Main_reg;
reg [3:0]movingDirection_reg;
reg [5:0]motorSpeed_reg, currentSensing_reg;
wire enA_wire, enB_wire, in1_wire, in2_wire, in3_wire, in4_wire;
parameter INTERTIAL_STOP = 4'b0000;
parameter HARD_STOP = 4'b1111;
parameter FORWARD = 4'b0110;
parameter REVERSE = 4'b1001;
parameter TURN_RIGHT = 4'b0101;
parameter TURN_LEFT = 4'b1010;
H_Bridge_v2 H1(
.clock(clock_Main_reg),
.movingDirection(movingDirection_reg),
.motorSpeed(motorSpeed_reg),
.currentSensing(currentSensing_reg),
.enA(enA_wire),
.enB(enB_wire),
.in1(in1_wire),
.in2(in2_wire),
.in3(in3_wire),
.in4(in4_wire)
);
initial
begin
clock_Main_reg <= 0;
movingDirection_reg <= INTERTIAL_STOP;
motorSpeed_reg[2:0] <= 3'b000;
motorSpeed_reg[5:3] <= 3'b000;
currentSensing_reg <= 0;
#10
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= REVERSE;
motorSpeed_reg[2:0] <= 3'b110;
motorSpeed_reg[5:3] <= 3'b110;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_RIGHT;
motorSpeed_reg[2:0] <= 3'b101;
motorSpeed_reg[5:3] <= 3'b101;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_LEFT;
motorSpeed_reg[2:0] <= 3'b100;
motorSpeed_reg[5:3] <= 3'b100;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= TURN_LEFT;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 1;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b011;
motorSpeed_reg[5:3] <= 3'b011;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b110;
motorSpeed_reg[5:3] <= 3'b110;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= FORWARD;
motorSpeed_reg[2:0] <= 3'b111;
motorSpeed_reg[5:3] <= 3'b111;
currentSensing_reg <= 0;
#500000
movingDirection_reg <= INTERTIAL_STOP;
motorSpeed_reg[2:0] <= 3'b000;
motorSpeed_reg[5:3] <= 3'b000;
currentSensing_reg <= 0;
end
always
#1 clock_Main_reg = ~clock_Main_reg;
endmodule | 1 |
3,618 | data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v | 105,948,944 | movingReverse_testBench.v | v | 138 | 83 | [] | [] | [] | [(23, 137)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:56: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:59: Unsupported: Ignoring delay on this delayed statement.\n #200000 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:62: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:65: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:68: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:71: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:74: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:77: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:80: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:83: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:86: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:89: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:92: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:95: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:98: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:101: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:105: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:110: Unsupported: Ignoring delay on this delayed statement.\n #550000000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:119: Unsupported: Ignoring delay on this delayed statement.\n #200000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:135: Unsupported: Ignoring delay on this delayed statement.\n # 1 clock = ~clock;\n ^\n%Error: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:35: Cannot find file containing module: \'movingReverse\'\n movingReverse testU1(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse.v\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse.sv\n movingReverse\n movingReverse.v\n movingReverse.sv\n obj_dir/movingReverse\n obj_dir/movingReverse.v\n obj_dir/movingReverse.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,407 | module | module movingReverse_testBench(
);
reg clock;
reg canMove_reg;
reg isMoving_forward_reg;
reg sensorIR_back_reg;
reg [3:0] sensIP_back_reg;
reg [3:0] presentINs_Reg;
wire [3:0]sendToH_BridgeINs_wire;
wire isMoving_out_wire;
movingReverse testU1(
.clock(clock),
.canMove(canMove_reg),
.isMoving_forward(isMoving_forward_reg),
.sensorIR_back(sensorIR_back_reg),
.sensIP_back(sensIP_back_reg),
.presentINs(presentINs_Reg),
.sendToH_BridgeINs(sendToH_BridgeINs_wire),
.isMoving_out(isMoving_out_wire)
);
initial begin
clock <= 0;
canMove_reg <= 1'b1;
isMoving_forward_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
sensorIR_back_reg <= 1'b0;
presentINs_Reg <= 4'b0000;
#200000
sensIP_back_reg <= 4'b0000;
#200000
sensIP_back_reg <= 4'b0001;
#200000
sensIP_back_reg <= 4'b0010;
#200000
sensIP_back_reg <= 4'b0011;
#200000
sensIP_back_reg <= 4'b0100;
#200000
sensIP_back_reg <= 4'b0101;
#200000
sensIP_back_reg <= 4'b0110;
#200000
sensIP_back_reg <= 4'b0111;
#200000
sensIP_back_reg <= 4'b1000;
#200000
sensIP_back_reg <= 4'b1001;
#200000
sensIP_back_reg <= 4'b1010;
#200000
sensIP_back_reg <= 4'b1011;
#200000
sensIP_back_reg <= 4'b1100;
#200000
sensIP_back_reg <= 4'b1110;
#200000
sensIP_back_reg <= 4'b1111;
#200000
sensIP_back_reg <= 4'b0110;
sensorIR_back_reg <= 1'b1;
#200000
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
#550000000
isMoving_forward_reg <= 1'b0;
canMove_reg <= 1;
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b1001;
#200000
isMoving_forward_reg <= 1'b0;
canMove_reg <= 0;
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
end
always@(posedge clock) begin
if (~isMoving_out_wire)
canMove_reg <= 0;
else
canMove_reg <= canMove_reg;
end
always begin
# 1 clock = ~clock;
end
endmodule | module movingReverse_testBench(
); |
reg clock;
reg canMove_reg;
reg isMoving_forward_reg;
reg sensorIR_back_reg;
reg [3:0] sensIP_back_reg;
reg [3:0] presentINs_Reg;
wire [3:0]sendToH_BridgeINs_wire;
wire isMoving_out_wire;
movingReverse testU1(
.clock(clock),
.canMove(canMove_reg),
.isMoving_forward(isMoving_forward_reg),
.sensorIR_back(sensorIR_back_reg),
.sensIP_back(sensIP_back_reg),
.presentINs(presentINs_Reg),
.sendToH_BridgeINs(sendToH_BridgeINs_wire),
.isMoving_out(isMoving_out_wire)
);
initial begin
clock <= 0;
canMove_reg <= 1'b1;
isMoving_forward_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
sensorIR_back_reg <= 1'b0;
presentINs_Reg <= 4'b0000;
#200000
sensIP_back_reg <= 4'b0000;
#200000
sensIP_back_reg <= 4'b0001;
#200000
sensIP_back_reg <= 4'b0010;
#200000
sensIP_back_reg <= 4'b0011;
#200000
sensIP_back_reg <= 4'b0100;
#200000
sensIP_back_reg <= 4'b0101;
#200000
sensIP_back_reg <= 4'b0110;
#200000
sensIP_back_reg <= 4'b0111;
#200000
sensIP_back_reg <= 4'b1000;
#200000
sensIP_back_reg <= 4'b1001;
#200000
sensIP_back_reg <= 4'b1010;
#200000
sensIP_back_reg <= 4'b1011;
#200000
sensIP_back_reg <= 4'b1100;
#200000
sensIP_back_reg <= 4'b1110;
#200000
sensIP_back_reg <= 4'b1111;
#200000
sensIP_back_reg <= 4'b0110;
sensorIR_back_reg <= 1'b1;
#200000
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
#550000000
isMoving_forward_reg <= 1'b0;
canMove_reg <= 1;
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b1001;
#200000
isMoving_forward_reg <= 1'b0;
canMove_reg <= 0;
sensorIR_back_reg <= 1'b0;
sensIP_back_reg <= 4'b0000;
end
always@(posedge clock) begin
if (~isMoving_out_wire)
canMove_reg <= 0;
else
canMove_reg <= canMove_reg;
end
always begin
# 1 clock = ~clock;
end
endmodule | 1 |
3,619 | data/full_repos/permissive/105948944/simulations/PWM_testBench.v | 105,948,944 | PWM_testBench.v | v | 74 | 83 | [] | [] | [] | null | line:29: before: "." | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:61: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:70: Unsupported: Ignoring delay on this delayed statement.\n #1 clock = ~clock; \n ^\n%Error: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:31: Cannot find file containing module: \'PWM_v3\'\n PWM_v3 UUT\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3.v\n data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3.sv\n PWM_v3\n PWM_v3.v\n PWM_v3.sv\n obj_dir/PWM_v3\n obj_dir/PWM_v3.v\n obj_dir/PWM_v3.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,408 | module | module PWM_testBench(
);
reg clock = 0;
reg [2:0] speed;
wire PWM_pulse;
wire [27:0] debugCustomClkCounter_wire;
defparam UUT.PERIOD = 28'd2500;
PWM_v3 UUT
(
.clock(clock),
.dutyCycle(speed),
.PWM_pulse(PWM_pulse),
.debugCounter(debugCustomClkCounter_wire)
);
initial
begin
speed <= 3'd1;
#5000
speed <= 3'd2;
#5000
speed <= 3'd3;
#5000
speed <= 3'd4;
#5000
speed <= 3'd5;
#5000
speed <= 3'd6;
#5000
speed <= 3'd7;
#5000
speed <= 3'd0;
end
always begin
#1 clock = ~clock;
end
endmodule | module PWM_testBench(
); |
reg clock = 0;
reg [2:0] speed;
wire PWM_pulse;
wire [27:0] debugCustomClkCounter_wire;
defparam UUT.PERIOD = 28'd2500;
PWM_v3 UUT
(
.clock(clock),
.dutyCycle(speed),
.PWM_pulse(PWM_pulse),
.debugCounter(debugCustomClkCounter_wire)
);
initial
begin
speed <= 3'd1;
#5000
speed <= 3'd2;
#5000
speed <= 3'd3;
#5000
speed <= 3'd4;
#5000
speed <= 3'd5;
#5000
speed <= 3'd6;
#5000
speed <= 3'd7;
#5000
speed <= 3'd0;
end
always begin
#1 clock = ~clock;
end
endmodule | 1 |
3,621 | data/full_repos/permissive/105948944/simulations/signalSync_testBench.v | 105,948,944 | signalSync_testBench.v | v | 64 | 83 | [] | [] | [] | null | line:25: before: "=" | null | 1: b'%Error: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:50: syntax error, unexpected \'@\'\n begin @(negedge clk)\n ^\n%Error: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:52: Unsupported or unknown PLI call: $dist_uniform\n delay = $dist_uniform(2,50,150);\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #delay;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 1,410 | module | module signalSync_testBench();
reg clk, async = 0;
wire rise, fall;
signalSync UUT(
.clock(clk),
.asynchronous_signal(async),
.rising_edge(rise),
.falling_edge(fall)
);
initial begin
clk <= 0;
async <= 0;
end
time delay = 0;
initial
begin
while ($time < 1000)
begin @(negedge clk)
delay = $dist_uniform(2,50,150);
#delay;
async = ~async;
end
end
always
begin
#10
clk = ~clk;
end
endmodule | module signalSync_testBench(); |
reg clk, async = 0;
wire rise, fall;
signalSync UUT(
.clock(clk),
.asynchronous_signal(async),
.rising_edge(rise),
.falling_edge(fall)
);
initial begin
clk <= 0;
async <= 0;
end
time delay = 0;
initial
begin
while ($time < 1000)
begin @(negedge clk)
delay = $dist_uniform(2,50,150);
#delay;
async = ~async;
end
end
always
begin
#10
clk = ~clk;
end
endmodule | 1 |
3,623 | data/full_repos/permissive/105948944/sources/basysConnections.v | 105,948,944 | basysConnections.v | v | 83 | 113 | [] | [] | [] | [(3, 83)] | null | null | 1: b"%Error: data/full_repos/permissive/105948944/sources/basysConnections.v:36: Cannot find file containing module: 'sensor_IP_v2'\n sensor_IP_v2 sensor_IP_v2(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sensor_IP_v2\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sensor_IP_v2.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sensor_IP_v2.sv\n sensor_IP_v2\n sensor_IP_v2.v\n sensor_IP_v2.sv\n obj_dir/sensor_IP_v2\n obj_dir/sensor_IP_v2.v\n obj_dir/sensor_IP_v2.sv\n%Error: data/full_repos/permissive/105948944/sources/basysConnections.v:44: Cannot find file containing module: 'sensorIR'\n sensorIR sensorIR(\n ^~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/basysConnections.v:51: Cannot find file containing module: 'decisionMaking_v2'\n decisionMaking_v2 decisionMaking_v2(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/basysConnections.v:65: Cannot find file containing module: 'H_Bridge_v3'\n H_Bridge_v3 H_Bridge_v3(\n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,412 | module | module basysConnections(
input clock,
input [15:0] SW,
input JC4,JC3,JC2,JC1,
input JC10,JC9,JC8,JC7,
input JB7, JB8,
input JB1,
input JB3, JB4,
output JA8,JA7,
output JA4,JA3,JA2,JA1,
output [7:0] LED
);
wire [3:0] IPsensFront_out_wire;
wire [3:0] IPsensBack_out_wire;
wire [3:0] sendToH_BridgeINs_wire;
wire [5:0] motorSpeeds_wire;
wire [5:0] previousSpeedFromDecisionMaking_wire;
wire [5:0] previousSpeedToDecisionMakinFromH_Bridge_wire;
wire [3:0] movDirec_isTurning_leftRight_wire;
wire [3:0] previous_movDirec_isTurning_leftRight_toDecMak_wire;
wire IR_sensed_wire;
sensor_IP_v2 sensor_IP_v2(
.clock(clock),
.IPsensFront_in({JC1,JC2,JC3,JC4}),
.IPsensBack_in({JC10,JC9,JC8,JC7}),
.IPsensFront_out(IPsensFront_out_wire),
.IPsensBack_out(IPsensBack_out_wire)
);
sensorIR sensorIR(
.clock(clock),
.IR_sensors({JB8,JB7}),
.IR_sensed(IR_sensed_wire)
);
decisionMaking_v2 decisionMaking_v2(
.clock(clock),
.IPsensors({IPsensBack_out_wire,IPsensFront_out_wire}),
.IR_sensors(IR_sensed_wire),
.mic(JB1),
.previousH_Bridge_INs({JA4,JA3,JA2,JA1}),
.previousSpeeds(previousSpeedToDecisionMakinFromH_Bridge_wire),
.previous_movDirec_isTurning_leftRight_fromHBridge(previous_movDirec_isTurning_leftRight_toDecMak_wire),
.sendToH_Bridge_INs(sendToH_BridgeINs_wire),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedToH_Bridge(previousSpeedFromDecisionMaking_wire),
.LED_debug({LED[7],LED[5:0]})
);
H_Bridge_v3 H_Bridge_v3(
.clock(clock),
.currentSensing_in({JB4, JB3}),
.INs_from_decisionMakin(sendToH_BridgeINs_wire),
.forwardSpeed(SW[2:0]),
.turningSpeeds({SW[8:6],SW[5:3]}),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedFromDecisionMaking(previousSpeedFromDecisionMaking_wire),
.previousSpeedToDecisionMakin(previousSpeedToDecisionMakinFromH_Bridge_wire),
.enA(JA7),
.enB(JA8),
.in1(JA1),
.in2(JA2),
.in3(JA3),
.in4(JA4),
.LED_currentSense_debug(LED[6]),
.previous_movDirec_isTurning_leftRight_toDecMak(previous_movDirec_isTurning_leftRight_toDecMak_wire)
);
endmodule | module basysConnections(
input clock,
input [15:0] SW,
input JC4,JC3,JC2,JC1,
input JC10,JC9,JC8,JC7,
input JB7, JB8,
input JB1,
input JB3, JB4,
output JA8,JA7,
output JA4,JA3,JA2,JA1,
output [7:0] LED
); |
wire [3:0] IPsensFront_out_wire;
wire [3:0] IPsensBack_out_wire;
wire [3:0] sendToH_BridgeINs_wire;
wire [5:0] motorSpeeds_wire;
wire [5:0] previousSpeedFromDecisionMaking_wire;
wire [5:0] previousSpeedToDecisionMakinFromH_Bridge_wire;
wire [3:0] movDirec_isTurning_leftRight_wire;
wire [3:0] previous_movDirec_isTurning_leftRight_toDecMak_wire;
wire IR_sensed_wire;
sensor_IP_v2 sensor_IP_v2(
.clock(clock),
.IPsensFront_in({JC1,JC2,JC3,JC4}),
.IPsensBack_in({JC10,JC9,JC8,JC7}),
.IPsensFront_out(IPsensFront_out_wire),
.IPsensBack_out(IPsensBack_out_wire)
);
sensorIR sensorIR(
.clock(clock),
.IR_sensors({JB8,JB7}),
.IR_sensed(IR_sensed_wire)
);
decisionMaking_v2 decisionMaking_v2(
.clock(clock),
.IPsensors({IPsensBack_out_wire,IPsensFront_out_wire}),
.IR_sensors(IR_sensed_wire),
.mic(JB1),
.previousH_Bridge_INs({JA4,JA3,JA2,JA1}),
.previousSpeeds(previousSpeedToDecisionMakinFromH_Bridge_wire),
.previous_movDirec_isTurning_leftRight_fromHBridge(previous_movDirec_isTurning_leftRight_toDecMak_wire),
.sendToH_Bridge_INs(sendToH_BridgeINs_wire),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedToH_Bridge(previousSpeedFromDecisionMaking_wire),
.LED_debug({LED[7],LED[5:0]})
);
H_Bridge_v3 H_Bridge_v3(
.clock(clock),
.currentSensing_in({JB4, JB3}),
.INs_from_decisionMakin(sendToH_BridgeINs_wire),
.forwardSpeed(SW[2:0]),
.turningSpeeds({SW[8:6],SW[5:3]}),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedFromDecisionMaking(previousSpeedFromDecisionMaking_wire),
.previousSpeedToDecisionMakin(previousSpeedToDecisionMakinFromH_Bridge_wire),
.enA(JA7),
.enB(JA8),
.in1(JA1),
.in2(JA2),
.in3(JA3),
.in4(JA4),
.LED_currentSense_debug(LED[6]),
.previous_movDirec_isTurning_leftRight_toDecMak(previous_movDirec_isTurning_leftRight_toDecMak_wire)
);
endmodule | 1 |
3,626 | data/full_repos/permissive/105948944/sources/currentSensing.v | 105,948,944 | currentSensing.v | v | 150 | 105 | [] | [] | [] | [(21, 150)] | null | null | 1: b'%Error: data/full_repos/permissive/105948944/sources/currentSensing.v:76: Cannot find file containing module: \'signalSync\'\n signalSync sync_currentOver0(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.sv\n signalSync\n signalSync.v\n signalSync.sv\n obj_dir/signalSync\n obj_dir/signalSync.v\n obj_dir/signalSync.sv\n%Error: data/full_repos/permissive/105948944/sources/currentSensing.v:83: Cannot find file containing module: \'signalSync\'\n signalSync sync_currentOver1(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/currentSensing.v:124: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h1e8480\' generates 28 bits.\n : ... In instance currentSensing\n max_current_period_reg <= 28\'d2000000; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/currentSensing.v:126: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h7a120\' generates 28 bits.\n : ... In instance currentSensing\n max_current_period_reg <= 28\'d500000; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/currentSensing.v:128: Operator GT expects 28 bits on the RHS, but RHS\'s VARREF \'max_current_period_reg\' generates 1 bits.\n : ... In instance currentSensing\n if ( ( counter_currentOverlo_reg_0_0 > max_current_period_reg\n ^\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/currentSensing.v:129: Operator GT expects 28 bits on the RHS, but RHS\'s VARREF \'max_current_period_reg\' generates 1 bits.\n : ... In instance currentSensing\n || counter_currentOverlo_reg_0_1 > max_current_period_reg ) )begin\n ^\n%Error: data/full_repos/permissive/105948944/sources/currentSensing.v:142: Cannot find file containing module: \'counter_up\'\n counter_up currentSens_counterUp( \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 1,415 | module | module currentSensing(
input clock,
input [1:0] currentSensA_B,
input isTurning,
output currentOverload
);
parameter [27:0] TENTH_of_PERIOD = 28'd1000000;
parameter [27:0] PERIOD = ( TENTH_of_PERIOD << 3 ) + ( TENTH_of_PERIOD << 1);
parameter [27:0] HALF_PERIOD = PERIOD >> 1;
parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
parameter [27:0] t_13_PERC_PERIOD = PERIOD >> 2;
parameter [27:0] T_2X_PERIOD = PERIOD << 1;
parameter [27:0] T_2X_and_HALF_PERIOD = T_2X_PERIOD + HALF_PERIOD;
parameter [27:0] T_3X_PERIOD = PERIOD + T_2X_PERIOD;
parameter [27:0] T_3X_and_HALF_PERIOD = T_3X_PERIOD + HALF_PERIOD;
parameter [27:0] T_4X_PERIOD = PERIOD << 2;
parameter [27:0] T_4X_and_QUARTER_PERIOD = T_4X_PERIOD + QUARTER_PERIOD;
parameter [27:0] T_5X_PERIOD = T_3X_PERIOD + T_2X_PERIOD;
parameter [27:0] T_5X_AND_QUARTER_PERIOD = T_5X_PERIOD + QUARTER_PERIOD;
parameter [27:0] T_5X_AND_HALF_PERIOD = T_5X_PERIOD + HALF_PERIOD;
parameter [27:0] T_6X_PERIOD = T_3X_PERIOD << 2;
parameter [27:0] T_7X_PERIOD = T_2X_PERIOD + T_5X_PERIOD;
parameter MAX_CURRENT_PERIOD = TENTH_of_PERIOD << 1;
reg max_current_period_reg;
reg [1:0] rebuiltSignal_reg;
reg [27:0] rebuiltSignal_counter_reg;
reg reset_counter_reg;
wire [1:0] rising_edge_wire;
wire [1:0] falling_edge_wire;
reg [1:0] rebuild_Sense;
reg [27:0] counter_currentOverlo_reg_0_0 = 0;
reg [27:0] counter_currentOverlo_reg_0_1 = 0;
reg currentOverloadOut = 0;
wire [27:0] countedUpTo_wire;
signalSync sync_currentOver0(
.clock(clock),
.asynchronous_signal(currentSensA_B[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
signalSync sync_currentOver1(
.clock(clock),
.asynchronous_signal(currentSensA_B[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuild_Sense[0] <= 1;
else if (falling_edge_wire[0])
rebuild_Sense[0] <= 0;
else
rebuild_Sense[0] <= rebuild_Sense[0];
if (rising_edge_wire[1])
rebuild_Sense[1] <= 1;
else if (falling_edge_wire[0])
rebuild_Sense[1] <= 0;
else
rebuild_Sense[1] <= rebuild_Sense[1];
end
always@(negedge clock) begin
if ( (countedUpTo_wire > 25 ) && (countedUpTo_wire < PERIOD ) ) begin
if (rebuild_Sense[0])
counter_currentOverlo_reg_0_0 <= counter_currentOverlo_reg_0_0 + 1;
else begin
counter_currentOverlo_reg_0_0 <= counter_currentOverlo_reg_0_0;
end
if (rebuild_Sense[1])
counter_currentOverlo_reg_0_1 <= counter_currentOverlo_reg_0_1 + 1;
else begin
counter_currentOverlo_reg_0_1 <= counter_currentOverlo_reg_0_1;
end
end
else if ( (countedUpTo_wire > PERIOD ) && (countedUpTo_wire < (T_2X_PERIOD-500) ) ) begin
;
if (isTurning)
max_current_period_reg <= 28'd2000000;
else
max_current_period_reg <= 28'd500000;
if ( ( counter_currentOverlo_reg_0_0 > max_current_period_reg
|| counter_currentOverlo_reg_0_1 > max_current_period_reg ) )begin
currentOverloadOut = 1'b1;
end
else
currentOverloadOut = 1'b0;
end
else if ( (countedUpTo_wire > (T_2X_PERIOD-499) ) && ( countedUpTo_wire < T_2X_PERIOD ) ) begin
counter_currentOverlo_reg_0_0 <= 0;
counter_currentOverlo_reg_0_1 <= 0;
end
end
counter_up currentSens_counterUp(
.clock(clock),
.reset(1'b0),
.counterPeriod(T_2X_PERIOD),
.countedUpTo(countedUpTo_wire)
);
assign currentOverload = currentOverloadOut;
endmodule | module currentSensing(
input clock,
input [1:0] currentSensA_B,
input isTurning,
output currentOverload
); |
parameter [27:0] TENTH_of_PERIOD = 28'd1000000;
parameter [27:0] PERIOD = ( TENTH_of_PERIOD << 3 ) + ( TENTH_of_PERIOD << 1);
parameter [27:0] HALF_PERIOD = PERIOD >> 1;
parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
parameter [27:0] t_13_PERC_PERIOD = PERIOD >> 2;
parameter [27:0] T_2X_PERIOD = PERIOD << 1;
parameter [27:0] T_2X_and_HALF_PERIOD = T_2X_PERIOD + HALF_PERIOD;
parameter [27:0] T_3X_PERIOD = PERIOD + T_2X_PERIOD;
parameter [27:0] T_3X_and_HALF_PERIOD = T_3X_PERIOD + HALF_PERIOD;
parameter [27:0] T_4X_PERIOD = PERIOD << 2;
parameter [27:0] T_4X_and_QUARTER_PERIOD = T_4X_PERIOD + QUARTER_PERIOD;
parameter [27:0] T_5X_PERIOD = T_3X_PERIOD + T_2X_PERIOD;
parameter [27:0] T_5X_AND_QUARTER_PERIOD = T_5X_PERIOD + QUARTER_PERIOD;
parameter [27:0] T_5X_AND_HALF_PERIOD = T_5X_PERIOD + HALF_PERIOD;
parameter [27:0] T_6X_PERIOD = T_3X_PERIOD << 2;
parameter [27:0] T_7X_PERIOD = T_2X_PERIOD + T_5X_PERIOD;
parameter MAX_CURRENT_PERIOD = TENTH_of_PERIOD << 1;
reg max_current_period_reg;
reg [1:0] rebuiltSignal_reg;
reg [27:0] rebuiltSignal_counter_reg;
reg reset_counter_reg;
wire [1:0] rising_edge_wire;
wire [1:0] falling_edge_wire;
reg [1:0] rebuild_Sense;
reg [27:0] counter_currentOverlo_reg_0_0 = 0;
reg [27:0] counter_currentOverlo_reg_0_1 = 0;
reg currentOverloadOut = 0;
wire [27:0] countedUpTo_wire;
signalSync sync_currentOver0(
.clock(clock),
.asynchronous_signal(currentSensA_B[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
signalSync sync_currentOver1(
.clock(clock),
.asynchronous_signal(currentSensA_B[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuild_Sense[0] <= 1;
else if (falling_edge_wire[0])
rebuild_Sense[0] <= 0;
else
rebuild_Sense[0] <= rebuild_Sense[0];
if (rising_edge_wire[1])
rebuild_Sense[1] <= 1;
else if (falling_edge_wire[0])
rebuild_Sense[1] <= 0;
else
rebuild_Sense[1] <= rebuild_Sense[1];
end
always@(negedge clock) begin
if ( (countedUpTo_wire > 25 ) && (countedUpTo_wire < PERIOD ) ) begin
if (rebuild_Sense[0])
counter_currentOverlo_reg_0_0 <= counter_currentOverlo_reg_0_0 + 1;
else begin
counter_currentOverlo_reg_0_0 <= counter_currentOverlo_reg_0_0;
end
if (rebuild_Sense[1])
counter_currentOverlo_reg_0_1 <= counter_currentOverlo_reg_0_1 + 1;
else begin
counter_currentOverlo_reg_0_1 <= counter_currentOverlo_reg_0_1;
end
end
else if ( (countedUpTo_wire > PERIOD ) && (countedUpTo_wire < (T_2X_PERIOD-500) ) ) begin
;
if (isTurning)
max_current_period_reg <= 28'd2000000;
else
max_current_period_reg <= 28'd500000;
if ( ( counter_currentOverlo_reg_0_0 > max_current_period_reg
|| counter_currentOverlo_reg_0_1 > max_current_period_reg ) )begin
currentOverloadOut = 1'b1;
end
else
currentOverloadOut = 1'b0;
end
else if ( (countedUpTo_wire > (T_2X_PERIOD-499) ) && ( countedUpTo_wire < T_2X_PERIOD ) ) begin
counter_currentOverlo_reg_0_0 <= 0;
counter_currentOverlo_reg_0_1 <= 0;
end
end
counter_up currentSens_counterUp(
.clock(clock),
.reset(1'b0),
.counterPeriod(T_2X_PERIOD),
.countedUpTo(countedUpTo_wire)
);
assign currentOverload = currentOverloadOut;
endmodule | 1 |
3,627 | data/full_repos/permissive/105948944/sources/decisionMaking_v2.v | 105,948,944 | decisionMaking_v2.v | v | 295 | 126 | [] | [] | [] | [(1, 294)] | null | null | 1: b"%Error: data/full_repos/permissive/105948944/sources/decisionMaking_v2.v:271: syntax error, unexpected '(', expecting IDENTIFIER\n .clock(clock),\n ^\n%Error: Exiting due to 1 error(s)\n" | 1,416 | module | module decisionMaking_v2(
input clock,
input [7:0] IPsensors,
input IR_sensors, mic,
input [3:0] previousH_Bridge_INs,
input [5:0] previousSpeeds,
input [3:0] previous_movDirec_isTurning_leftRight_fromHBridge,
output [3:0] sendToH_Bridge_INs,
output [3:0] movDirec_isTurning_leftRight,
output [5:0] previousSpeedToH_Bridge,
output [6:0] LED_debug
);
parameter INTERTIAL_STOP = 4'b0000;
parameter HARD_STOP = 4'b1111;
parameter REVERSE = 4'b0110;
parameter FORWARD = 4'b1001;
reg [3:0] movDirec_isTurning_leftRight_reg;
integer i;
parameter MOVING_FORWARD = 4'b1100;
parameter TURNING_LEFT = 4'b1110;
parameter TURNING_RIGHT = 4'b1111;
parameter STOPPING = 4'b0100;
parameter WEIRD_COMBINATIONS = 4'b1001;
parameter MOVING_REVERSE = 4'b1000;
parameter TURNING_LEFT_REVERSE = 4'b1011;
parameter TURNING_RIGHT_REVERSE = 4'b1010;
reg [3:0] IPsensors_reg;
reg [5:0] previousSpeeds_reg;
reg [3:0] sendToH_BridgeINs_reg;
reg [5:0] motorSpeeds_reg;
reg [5:0] LED_debug_reg;
reg isTurning_reg = 0;
reg stoppedAndWaitingForDetection_reg;
reg reverse_wire_reg;
reg IR_sensed;
reg turning_long_reg;
reg stopLongTurning_reg;
reg [31:0] previousTimeForTogglingReverse_in_reg;
wire [3:0] sendToH_BridgeINs_reg_turning_wire;
wire [3:0] sendToH_Bridge_turn_long_wire;
wire [27:0] countedUpTO_turning_wire;
wire stoppedAndWaitingForDetection_wire;
wire isStoppedAndDetecting_wire;
wire [3:0] virtual_IPsensors_wire;
wire reverse_wire;
wire isTurning_long_out_wire;
wire [31:0] previousTimeForTogglingReverse_in_wire;
always@(posedge clock) begin
IR_sensed <= 0;
turning_long_reg <= 0;
if (IR_sensors)
IR_sensed <= 1;
else
IR_sensed <= 0;
if (stoppedAndWaitingForDetection_wire)
stoppedAndWaitingForDetection_reg <= 1'b1;
else
stoppedAndWaitingForDetection_reg <= 1'b0;
if (~reverse_wire || reverse_wire === 1'bx || reverse_wire === 1'bz ) begin
IPsensors_reg <= IPsensors[3:0];
reverse_wire_reg <= 0;
end
else begin
reverse_wire_reg <= 1;
IPsensors_reg <= IPsensors[7:4];
end
if (isStoppedAndDetecting_wire && ~IPsensors_reg)
IPsensors_reg = virtual_IPsensors_wire;
else
IPsensors_reg = IPsensors_reg;
if(~isTurning_long_out_wire || isTurning_long_out_wire === 1'bx || isTurning_long_out_wire === 1'b0 )
turning_long_reg <=1;
else
turning_long_reg <=0;
if(~turning_long_reg) begin
if (~IR_sensed) begin
case(IPsensors_reg)
4'b0000 : begin
movDirec_isTurning_leftRight_reg <= STOPPING;
sendToH_BridgeINs_reg <= INTERTIAL_STOP;
end
4'b0110 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= MOVING_REVERSE;
sendToH_BridgeINs_reg <= REVERSE;
end
else begin
movDirec_isTurning_leftRight_reg <= MOVING_FORWARD;
sendToH_BridgeINs_reg <= FORWARD;
end
end
4'b0010 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
else begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
end
4'b0001,
4'b0011,
4'b0111,
4'b0101,
4'b1011 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b0100 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
else begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
end
4'b1001 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= MOVING_REVERSE;
sendToH_BridgeINs_reg <= REVERSE;
end
else begin
movDirec_isTurning_leftRight_reg <= MOVING_FORWARD;
sendToH_BridgeINs_reg <= FORWARD;
end
end
4'b1000,
4'b1100,
4'b1110,
4'b1101,
4'b1010 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b1111 : begin
movDirec_isTurning_leftRight_reg <= WEIRD_COMBINATIONS;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
default : begin
movDirec_isTurning_leftRight_reg = WEIRD_COMBINATIONS;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
endcase
end
else begin
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg ;
sendToH_BridgeINs_reg <= HARD_STOP;
end
end
else begin
stopLongTurning_reg <= 0;
if ( ( IPsensors_reg != 4'b0100 || IPsensors_reg != 4'b0010 ) || IPsensors_reg != 4'b0110 ) begin
case(previous_movDirec_isTurning_leftRight_fromHBridge)
4'b1010,
4'b1111 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b1110,
4'b1011 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
default : begin
movDirec_isTurning_leftRight_reg = previous_movDirec_isTurning_leftRight_fromHBridge;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
endcase
end
else begin
stopLongTurning_reg <= 1;
end
end
LED_debug_reg[4] <= stoppedAndWaitingForDetection_reg;
LED_debug_reg[5] <=isStoppedAndDetecting_wire;
previousSpeeds_reg <= previousSpeeds;
previousTimeForTogglingReverse_in_reg <= previousTimeForTogglingReverse_in_wire;
end
turn turn_movFrwrd(
.clock(clock),
.isTurning_leftOrRight(movDirec_isTurning_leftRight_reg[1:0]),
.stopLongTurning(stopLongTurning_reg),
.sendToH_Bridge_turn(sendToH_BridgeINs_reg_turning_wire),
.sendToH_Bridge_turn_long(sendToH_Bridge_turn_long_wire),
.isTurning_long_out(isTurning_long_out_wire)
);
stopping(
.clock(clock),
.present_INs(IPsensors_reg),
.stoppedAndWaitingForDetection(stoppedAndWaitingForDetection_wire)
);
freqDetect(
.clock(clock),
.micInput(mic),
.stoppedAndWaitingForDetection(stoppedAndWaitingForDetection_wire),
.IP_sensors(IPsensors_reg),
.previousTimeForTogglingReverse_in(previousTimeForTogglingReverse_in_reg),
.virtual_IPsensors(virtual_IPsensors_wire),
.isStoppedAndDetecting_out(isStoppedAndDetecting_wire),
.previousTimeForTogglingReverse_out(previousTimeForTogglingReverse_in_wire),
.reverse(reverse_wire)
);
assign sendToH_Bridge_INs = sendToH_BridgeINs_reg;
assign movDirec_isTurning_leftRight = movDirec_isTurning_leftRight_reg;
assign previousSpeedToH_Bridge = previousSpeeds_reg;
assign LED_debug[5:4] = LED_debug_reg[5:4];
assign LED_debug[3:0] = virtual_IPsensors_wire;
assign LED_debug[6] = reverse_wire;
endmodule | module decisionMaking_v2(
input clock,
input [7:0] IPsensors,
input IR_sensors, mic,
input [3:0] previousH_Bridge_INs,
input [5:0] previousSpeeds,
input [3:0] previous_movDirec_isTurning_leftRight_fromHBridge,
output [3:0] sendToH_Bridge_INs,
output [3:0] movDirec_isTurning_leftRight,
output [5:0] previousSpeedToH_Bridge,
output [6:0] LED_debug
); |
parameter INTERTIAL_STOP = 4'b0000;
parameter HARD_STOP = 4'b1111;
parameter REVERSE = 4'b0110;
parameter FORWARD = 4'b1001;
reg [3:0] movDirec_isTurning_leftRight_reg;
integer i;
parameter MOVING_FORWARD = 4'b1100;
parameter TURNING_LEFT = 4'b1110;
parameter TURNING_RIGHT = 4'b1111;
parameter STOPPING = 4'b0100;
parameter WEIRD_COMBINATIONS = 4'b1001;
parameter MOVING_REVERSE = 4'b1000;
parameter TURNING_LEFT_REVERSE = 4'b1011;
parameter TURNING_RIGHT_REVERSE = 4'b1010;
reg [3:0] IPsensors_reg;
reg [5:0] previousSpeeds_reg;
reg [3:0] sendToH_BridgeINs_reg;
reg [5:0] motorSpeeds_reg;
reg [5:0] LED_debug_reg;
reg isTurning_reg = 0;
reg stoppedAndWaitingForDetection_reg;
reg reverse_wire_reg;
reg IR_sensed;
reg turning_long_reg;
reg stopLongTurning_reg;
reg [31:0] previousTimeForTogglingReverse_in_reg;
wire [3:0] sendToH_BridgeINs_reg_turning_wire;
wire [3:0] sendToH_Bridge_turn_long_wire;
wire [27:0] countedUpTO_turning_wire;
wire stoppedAndWaitingForDetection_wire;
wire isStoppedAndDetecting_wire;
wire [3:0] virtual_IPsensors_wire;
wire reverse_wire;
wire isTurning_long_out_wire;
wire [31:0] previousTimeForTogglingReverse_in_wire;
always@(posedge clock) begin
IR_sensed <= 0;
turning_long_reg <= 0;
if (IR_sensors)
IR_sensed <= 1;
else
IR_sensed <= 0;
if (stoppedAndWaitingForDetection_wire)
stoppedAndWaitingForDetection_reg <= 1'b1;
else
stoppedAndWaitingForDetection_reg <= 1'b0;
if (~reverse_wire || reverse_wire === 1'bx || reverse_wire === 1'bz ) begin
IPsensors_reg <= IPsensors[3:0];
reverse_wire_reg <= 0;
end
else begin
reverse_wire_reg <= 1;
IPsensors_reg <= IPsensors[7:4];
end
if (isStoppedAndDetecting_wire && ~IPsensors_reg)
IPsensors_reg = virtual_IPsensors_wire;
else
IPsensors_reg = IPsensors_reg;
if(~isTurning_long_out_wire || isTurning_long_out_wire === 1'bx || isTurning_long_out_wire === 1'b0 )
turning_long_reg <=1;
else
turning_long_reg <=0;
if(~turning_long_reg) begin
if (~IR_sensed) begin
case(IPsensors_reg)
4'b0000 : begin
movDirec_isTurning_leftRight_reg <= STOPPING;
sendToH_BridgeINs_reg <= INTERTIAL_STOP;
end
4'b0110 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= MOVING_REVERSE;
sendToH_BridgeINs_reg <= REVERSE;
end
else begin
movDirec_isTurning_leftRight_reg <= MOVING_FORWARD;
sendToH_BridgeINs_reg <= FORWARD;
end
end
4'b0010 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
else begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
end
4'b0001,
4'b0011,
4'b0111,
4'b0101,
4'b1011 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b0100 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
else begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg_turning_wire;
end
end
4'b1001 : begin
if(reverse_wire_reg) begin
movDirec_isTurning_leftRight_reg <= MOVING_REVERSE;
sendToH_BridgeINs_reg <= REVERSE;
end
else begin
movDirec_isTurning_leftRight_reg <= MOVING_FORWARD;
sendToH_BridgeINs_reg <= FORWARD;
end
end
4'b1000,
4'b1100,
4'b1110,
4'b1101,
4'b1010 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b1111 : begin
movDirec_isTurning_leftRight_reg <= WEIRD_COMBINATIONS;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
default : begin
movDirec_isTurning_leftRight_reg = WEIRD_COMBINATIONS;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
endcase
end
else begin
sendToH_BridgeINs_reg <= sendToH_BridgeINs_reg ;
sendToH_BridgeINs_reg <= HARD_STOP;
end
end
else begin
stopLongTurning_reg <= 0;
if ( ( IPsensors_reg != 4'b0100 || IPsensors_reg != 4'b0010 ) || IPsensors_reg != 4'b0110 ) begin
case(previous_movDirec_isTurning_leftRight_fromHBridge)
4'b1010,
4'b1111 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_RIGHT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
4'b1110,
4'b1011 : begin
if(reverse_wire_reg) begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT_REVERSE;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
else begin
for(i = 0; i < 4; i = i + 1) begin
movDirec_isTurning_leftRight_reg <= TURNING_LEFT;
sendToH_BridgeINs_reg <= sendToH_Bridge_turn_long_wire;
end
end
end
default : begin
movDirec_isTurning_leftRight_reg = previous_movDirec_isTurning_leftRight_fromHBridge;
sendToH_BridgeINs_reg <= previousH_Bridge_INs;
end
endcase
end
else begin
stopLongTurning_reg <= 1;
end
end
LED_debug_reg[4] <= stoppedAndWaitingForDetection_reg;
LED_debug_reg[5] <=isStoppedAndDetecting_wire;
previousSpeeds_reg <= previousSpeeds;
previousTimeForTogglingReverse_in_reg <= previousTimeForTogglingReverse_in_wire;
end
turn turn_movFrwrd(
.clock(clock),
.isTurning_leftOrRight(movDirec_isTurning_leftRight_reg[1:0]),
.stopLongTurning(stopLongTurning_reg),
.sendToH_Bridge_turn(sendToH_BridgeINs_reg_turning_wire),
.sendToH_Bridge_turn_long(sendToH_Bridge_turn_long_wire),
.isTurning_long_out(isTurning_long_out_wire)
);
stopping(
.clock(clock),
.present_INs(IPsensors_reg),
.stoppedAndWaitingForDetection(stoppedAndWaitingForDetection_wire)
);
freqDetect(
.clock(clock),
.micInput(mic),
.stoppedAndWaitingForDetection(stoppedAndWaitingForDetection_wire),
.IP_sensors(IPsensors_reg),
.previousTimeForTogglingReverse_in(previousTimeForTogglingReverse_in_reg),
.virtual_IPsensors(virtual_IPsensors_wire),
.isStoppedAndDetecting_out(isStoppedAndDetecting_wire),
.previousTimeForTogglingReverse_out(previousTimeForTogglingReverse_in_wire),
.reverse(reverse_wire)
);
assign sendToH_Bridge_INs = sendToH_BridgeINs_reg;
assign movDirec_isTurning_leftRight = movDirec_isTurning_leftRight_reg;
assign previousSpeedToH_Bridge = previousSpeeds_reg;
assign LED_debug[5:4] = LED_debug_reg[5:4];
assign LED_debug[3:0] = virtual_IPsensors_wire;
assign LED_debug[6] = reverse_wire;
endmodule | 1 |
3,629 | data/full_repos/permissive/105948944/sources/H_Bridge_v3.v | 105,948,944 | H_Bridge_v3.v | v | 175 | 107 | [] | [] | [] | null | line:141: before: "." | null | 1: b"%Error: data/full_repos/permissive/105948944/sources/H_Bridge_v3.v:142: Cannot find file containing module: 'PWM_v3'\n PWM_v3 pwmH_Bridge1( \n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/PWM_v3\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/PWM_v3.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/PWM_v3.sv\n PWM_v3\n PWM_v3.v\n PWM_v3.sv\n obj_dir/PWM_v3\n obj_dir/PWM_v3.v\n obj_dir/PWM_v3.sv\n%Error: data/full_repos/permissive/105948944/sources/H_Bridge_v3.v:150: Cannot find file containing module: 'PWM_v3'\n PWM_v3 pwmH_Bridge2( \n ^~~~~~\n%Error: data/full_repos/permissive/105948944/sources/H_Bridge_v3.v:158: Cannot find file containing module: 'PWM_v3'\n PWM_v3 customClock (\n ^~~~~~\n%Error: data/full_repos/permissive/105948944/sources/H_Bridge_v3.v:164: Cannot find file containing module: 'currentSensing'\n currentSensing currentSense(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,418 | module | module H_Bridge_v3(
input clock,
input [1:0] currentSensing_in,
input [3:0] INs_from_decisionMakin,
input [2:0] forwardSpeed,
input [5:0] turningSpeeds,
input [3:0] movDirec_isTurning_leftRight,
input [5:0] previousSpeedFromDecisionMaking,
output [5:0] previousSpeedToDecisionMakin,
output enA, enB, in1, in2, in3, in4,
output LED_currentSense_debug,
output[3:0] previous_movDirec_isTurning_leftRight_toDecMak
);
parameter MOVING_FORWARD = 4'b1100;
parameter TURNING_LEFT = 4'b1110;
parameter TURNING_RIGHT = 4'b1111;
parameter STOPPING = 4'B0100;
parameter WEIRD_COMBINATIONS = 4'b1001;
parameter MOVING_REVERSE = 4'b1000;
parameter TURNING_LEFT_REVERSE = 4'b1011;
parameter TURNING_RIGHT_REVERSE = 4'b1010;
reg [3:0] INs_from_decisionMakin_reg;
reg [3:0] movDirec_isTurning_leftRight_reg;
reg [5:0] motorSpeeds_reg;
reg currentSensing_reg;
wire currentSensing_wire;
wire customClock_wire;
always@(posedge customClock_wire) begin
currentSensing_reg <= 0;
if (currentSensing_wire)
currentSensing_reg <= 1;
else
currentSensing_reg <= 0;
case(movDirec_isTurning_leftRight)
4'b1110 : begin
motorSpeeds_reg[2:0] = turningSpeeds[5:3];
motorSpeeds_reg[5:3] = turningSpeeds[2:0];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1111 : begin
motorSpeeds_reg[2:0] = turningSpeeds[2:0];
motorSpeeds_reg[5:3] = turningSpeeds[5:3];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b0000,
4'b0001,
4'b0010,
4'b0011,
4'b0100,
4'b0101,
4'b0110,
4'b0111 : begin
motorSpeeds_reg = 6'b000000;
INs_from_decisionMakin_reg = 4'b0000;
end
4'b1100,
4'b1101 : begin
motorSpeeds_reg = {forwardSpeed,forwardSpeed};
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1000 : begin
motorSpeeds_reg = {forwardSpeed,forwardSpeed};
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1001 : begin
motorSpeeds_reg = previousSpeedFromDecisionMaking;
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1011 : begin
motorSpeeds_reg[2:0] = turningSpeeds[5:3];
motorSpeeds_reg[5:3] = turningSpeeds[2:0];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1010 : begin
motorSpeeds_reg[2:0] = turningSpeeds[2:0];
motorSpeeds_reg[5:3] = turningSpeeds[5:3];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
default : begin
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
endcase
if (currentSensing_reg) begin
motorSpeeds_reg = 6'b000000;
INs_from_decisionMakin_reg = 4'b0000;
end
else begin
motorSpeeds_reg = motorSpeeds_reg;
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
end
defparam pwmH_Bridge2.PERIOD = 28'd125000;
PWM_v3 pwmH_Bridge1(
.clock(clock),
.dutyCycle(motorSpeeds_reg[2:0]),
.PWM_pulse(enA)
);
defparam pwmH_Bridge2.PERIOD = 28'd125000;
PWM_v3 pwmH_Bridge2(
.clock(clock),
.dutyCycle(motorSpeeds_reg[5:3]),
.PWM_pulse(enB)
);
defparam customClock.PERIOD = 725;
PWM_v3 customClock (
.clock(clock),
.dutyCycle(3'b011),
.PWM_pulse(customClock_wire)
);
currentSensing currentSense(
.clock(clock),
.currentSensA_B(~currentSensing_in),
.isTurning(movDirec_isTurning_leftRight[1]),
.currentOverload(currentSensing_wire)
);
assign {in4,in3,in2,in1} = INs_from_decisionMakin_reg;
assign previousSpeedToDecisionMakin = motorSpeeds_reg;
assign LED_currentSense_debug = currentSensing_reg;
endmodule | module H_Bridge_v3(
input clock,
input [1:0] currentSensing_in,
input [3:0] INs_from_decisionMakin,
input [2:0] forwardSpeed,
input [5:0] turningSpeeds,
input [3:0] movDirec_isTurning_leftRight,
input [5:0] previousSpeedFromDecisionMaking,
output [5:0] previousSpeedToDecisionMakin,
output enA, enB, in1, in2, in3, in4,
output LED_currentSense_debug,
output[3:0] previous_movDirec_isTurning_leftRight_toDecMak
); |
parameter MOVING_FORWARD = 4'b1100;
parameter TURNING_LEFT = 4'b1110;
parameter TURNING_RIGHT = 4'b1111;
parameter STOPPING = 4'B0100;
parameter WEIRD_COMBINATIONS = 4'b1001;
parameter MOVING_REVERSE = 4'b1000;
parameter TURNING_LEFT_REVERSE = 4'b1011;
parameter TURNING_RIGHT_REVERSE = 4'b1010;
reg [3:0] INs_from_decisionMakin_reg;
reg [3:0] movDirec_isTurning_leftRight_reg;
reg [5:0] motorSpeeds_reg;
reg currentSensing_reg;
wire currentSensing_wire;
wire customClock_wire;
always@(posedge customClock_wire) begin
currentSensing_reg <= 0;
if (currentSensing_wire)
currentSensing_reg <= 1;
else
currentSensing_reg <= 0;
case(movDirec_isTurning_leftRight)
4'b1110 : begin
motorSpeeds_reg[2:0] = turningSpeeds[5:3];
motorSpeeds_reg[5:3] = turningSpeeds[2:0];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1111 : begin
motorSpeeds_reg[2:0] = turningSpeeds[2:0];
motorSpeeds_reg[5:3] = turningSpeeds[5:3];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b0000,
4'b0001,
4'b0010,
4'b0011,
4'b0100,
4'b0101,
4'b0110,
4'b0111 : begin
motorSpeeds_reg = 6'b000000;
INs_from_decisionMakin_reg = 4'b0000;
end
4'b1100,
4'b1101 : begin
motorSpeeds_reg = {forwardSpeed,forwardSpeed};
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1000 : begin
motorSpeeds_reg = {forwardSpeed,forwardSpeed};
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1001 : begin
motorSpeeds_reg = previousSpeedFromDecisionMaking;
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1011 : begin
motorSpeeds_reg[2:0] = turningSpeeds[5:3];
motorSpeeds_reg[5:3] = turningSpeeds[2:0];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
4'b1010 : begin
motorSpeeds_reg[2:0] = turningSpeeds[2:0];
motorSpeeds_reg[5:3] = turningSpeeds[5:3];
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
default : begin
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
endcase
if (currentSensing_reg) begin
motorSpeeds_reg = 6'b000000;
INs_from_decisionMakin_reg = 4'b0000;
end
else begin
motorSpeeds_reg = motorSpeeds_reg;
INs_from_decisionMakin_reg = INs_from_decisionMakin;
end
end
defparam pwmH_Bridge2.PERIOD = 28'd125000;
PWM_v3 pwmH_Bridge1(
.clock(clock),
.dutyCycle(motorSpeeds_reg[2:0]),
.PWM_pulse(enA)
);
defparam pwmH_Bridge2.PERIOD = 28'd125000;
PWM_v3 pwmH_Bridge2(
.clock(clock),
.dutyCycle(motorSpeeds_reg[5:3]),
.PWM_pulse(enB)
);
defparam customClock.PERIOD = 725;
PWM_v3 customClock (
.clock(clock),
.dutyCycle(3'b011),
.PWM_pulse(customClock_wire)
);
currentSensing currentSense(
.clock(clock),
.currentSensA_B(~currentSensing_in),
.isTurning(movDirec_isTurning_leftRight[1]),
.currentOverload(currentSensing_wire)
);
assign {in4,in3,in2,in1} = INs_from_decisionMakin_reg;
assign previousSpeedToDecisionMakin = motorSpeeds_reg;
assign LED_currentSense_debug = currentSensing_reg;
endmodule | 1 |
3,634 | data/full_repos/permissive/105948944/sources/sensorIR.v | 105,948,944 | sensorIR.v | v | 68 | 99 | [] | [] | [] | [(23, 67)] | null | null | 1: b'%Error: data/full_repos/permissive/105948944/sources/sensorIR.v:33: Cannot find file containing module: \'signalSync\'\n signalSync sync_IR0(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.sv\n signalSync\n signalSync.v\n signalSync.sv\n obj_dir/signalSync\n obj_dir/signalSync.v\n obj_dir/signalSync.sv\n%Error: data/full_repos/permissive/105948944/sources/sensorIR.v:40: Cannot find file containing module: \'signalSync\'\n signalSync sync_IR1(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/sensorIR.v:61: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rebuiltSignal_reg\' generates 2 bits.\n : ... In instance sensorIR\n if ( rebuiltSignal_reg )\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 1,425 | module | module sensorIR(
input clock,
input [1:0] IR_sensors,
output reg IR_sensed
);
reg [1:0] rebuiltSignal_reg;
wire [1:0] rising_edge_wire;
wire [1:0] falling_edge_wire;
signalSync sync_IR0(
.clock(clock),
.asynchronous_signal(~IR_sensors[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
signalSync sync_IR1(
.clock(clock),
.asynchronous_signal(~IR_sensors[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuiltSignal_reg[0] <= 1;
else if (falling_edge_wire[0])
rebuiltSignal_reg[0] <= 0;
end
always@(posedge clock) begin
if (rising_edge_wire[1])
rebuiltSignal_reg[1] <= 1;
else if (falling_edge_wire[1])
rebuiltSignal_reg[1] <= 0;
end
always@(negedge clock) begin
if ( rebuiltSignal_reg )
IR_sensed <= 1;
else
IR_sensed <= 0;
end
endmodule | module sensorIR(
input clock,
input [1:0] IR_sensors,
output reg IR_sensed
); |
reg [1:0] rebuiltSignal_reg;
wire [1:0] rising_edge_wire;
wire [1:0] falling_edge_wire;
signalSync sync_IR0(
.clock(clock),
.asynchronous_signal(~IR_sensors[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
signalSync sync_IR1(
.clock(clock),
.asynchronous_signal(~IR_sensors[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuiltSignal_reg[0] <= 1;
else if (falling_edge_wire[0])
rebuiltSignal_reg[0] <= 0;
end
always@(posedge clock) begin
if (rising_edge_wire[1])
rebuiltSignal_reg[1] <= 1;
else if (falling_edge_wire[1])
rebuiltSignal_reg[1] <= 0;
end
always@(negedge clock) begin
if ( rebuiltSignal_reg )
IR_sensed <= 1;
else
IR_sensed <= 0;
end
endmodule | 1 |
3,635 | data/full_repos/permissive/105948944/sources/sensor_IP_v2.v | 105,948,944 | sensor_IP_v2.v | v | 53 | 83 | [] | [] | [] | [(21, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/105948944/sources/sensor_IP_v2.v:39: Cannot find file containing module: 'sync_rebuiltSignal'\n sync_rebuiltSignal sycIP_front(\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal.sv\n sync_rebuiltSignal\n sync_rebuiltSignal.v\n sync_rebuiltSignal.sv\n obj_dir/sync_rebuiltSignal\n obj_dir/sync_rebuiltSignal.v\n obj_dir/sync_rebuiltSignal.sv\n%Error: data/full_repos/permissive/105948944/sources/sensor_IP_v2.v:45: Cannot find file containing module: 'sync_rebuiltSignal'\n sync_rebuiltSignal sycIP_back(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,426 | module | module sensor_IP_v2(
input clock,
input [3:0] IPsensFront_in,
input [3:0] IPsensBack_in,
output [3:0] IPsensFront_out,
output [3:0] IPsensBack_out
);
reg [3:0] IPsensFront_reg;
reg [3:0] IPsensBack_reg;
wire [3:0] IPsensFront_synced_wire;
wire [3:0] IPsensBack_synced_wire;
always@(posedge clock) begin
IPsensFront_reg <= ~IPsensFront_in;
IPsensBack_reg <= ~IPsensBack_in;
end
sync_rebuiltSignal sycIP_front(
.clock(clock),
.sensors(IPsensFront_reg),
.rebuiltSignal(IPsensFront_synced_wire)
);
sync_rebuiltSignal sycIP_back(
.clock(clock),
.sensors(IPsensBack_reg),
.rebuiltSignal(IPsensBack_synced_wire)
);
assign IPsensFront_out = IPsensFront_synced_wire;
assign IPsensBack_out = IPsensBack_synced_wire;
endmodule | module sensor_IP_v2(
input clock,
input [3:0] IPsensFront_in,
input [3:0] IPsensBack_in,
output [3:0] IPsensFront_out,
output [3:0] IPsensBack_out
); |
reg [3:0] IPsensFront_reg;
reg [3:0] IPsensBack_reg;
wire [3:0] IPsensFront_synced_wire;
wire [3:0] IPsensBack_synced_wire;
always@(posedge clock) begin
IPsensFront_reg <= ~IPsensFront_in;
IPsensBack_reg <= ~IPsensBack_in;
end
sync_rebuiltSignal sycIP_front(
.clock(clock),
.sensors(IPsensFront_reg),
.rebuiltSignal(IPsensFront_synced_wire)
);
sync_rebuiltSignal sycIP_back(
.clock(clock),
.sensors(IPsensBack_reg),
.rebuiltSignal(IPsensBack_synced_wire)
);
assign IPsensFront_out = IPsensFront_synced_wire;
assign IPsensBack_out = IPsensBack_synced_wire;
endmodule | 1 |
3,636 | data/full_repos/permissive/105948944/sources/signalSync.v | 105,948,944 | signalSync.v | v | 56 | 113 | [] | [] | [] | [(23, 56)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/105948944/sources/signalSync.v:30: Little bit endian vector: MSB < LSB of bit range: 1:3\n reg [1:3] resync;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,427 | module | module signalSync(
input clock,
input asynchronous_signal,
output rising_edge,
output falling_edge
);
reg [1:3] resync;
reg fall, rise;
initial
begin
fall <= 0;
rise <= 0;
resync <= 0;
end
always @(posedge clock)
begin
fall <= resync[3] & !resync[2];
rise <= resync[2] & !resync[3];
resync <= {asynchronous_signal , resync[1:2]};
end
assign rising_edge = rise;
assign falling_edge = fall;
endmodule | module signalSync(
input clock,
input asynchronous_signal,
output rising_edge,
output falling_edge
); |
reg [1:3] resync;
reg fall, rise;
initial
begin
fall <= 0;
rise <= 0;
resync <= 0;
end
always @(posedge clock)
begin
fall <= resync[3] & !resync[2];
rise <= resync[2] & !resync[3];
resync <= {asynchronous_signal , resync[1:2]};
end
assign rising_edge = rise;
assign falling_edge = fall;
endmodule | 1 |
3,638 | data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v | 105,948,944 | sync_rebuiltSignal.v | v | 101 | 95 | [] | [] | [] | [(21, 100)] | null | null | 1: b"%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:32: Cannot find file containing module: 'signalSync'\n signalSync sync_reb0(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.v\n data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.sv\n signalSync\n signalSync.v\n signalSync.sv\n obj_dir/signalSync\n obj_dir/signalSync.v\n obj_dir/signalSync.sv\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:48: Cannot find file containing module: 'signalSync'\n signalSync sync_reb1(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:65: Cannot find file containing module: 'signalSync'\n signalSync sync_reb2(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:82: Cannot find file containing module: 'signalSync'\n signalSync sync_reb3(\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,429 | module | module sync_rebuiltSignal(
input clock,
input [3:0] sensors,
output [3:0] rebuiltSignal
);
reg [3:0] rebuiltSignal_reg;
wire [3:0] rising_edge_wire;
wire [3:0] falling_edge_wire;
signalSync sync_reb0(
.clock(clock),
.asynchronous_signal(sensors[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuiltSignal_reg[0] <= 1;
else if (falling_edge_wire[0])
rebuiltSignal_reg[0] <= 0;
end
signalSync sync_reb1(
.clock(clock),
.asynchronous_signal(sensors[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[1])
rebuiltSignal_reg[1] <= 1;
else if (falling_edge_wire[1])
rebuiltSignal_reg[1] <= 0;
end
signalSync sync_reb2(
.clock(clock),
.asynchronous_signal(sensors[2]),
.rising_edge(rising_edge_wire[2]),
.falling_edge(falling_edge_wire[2])
);
always@(posedge clock) begin
if (rising_edge_wire[2])
rebuiltSignal_reg[2] <= 1;
else if (falling_edge_wire[2])
rebuiltSignal_reg[2] <= 0;
end
signalSync sync_reb3(
.clock(clock),
.asynchronous_signal(sensors[3]),
.rising_edge(rising_edge_wire[3]),
.falling_edge(falling_edge_wire[3])
);
always@(posedge clock) begin
if (rising_edge_wire[3])
rebuiltSignal_reg[3] <= 1;
else if (falling_edge_wire[3])
rebuiltSignal_reg[3] <= 0;
end
assign rebuiltSignal = rebuiltSignal_reg;
endmodule | module sync_rebuiltSignal(
input clock,
input [3:0] sensors,
output [3:0] rebuiltSignal
); |
reg [3:0] rebuiltSignal_reg;
wire [3:0] rising_edge_wire;
wire [3:0] falling_edge_wire;
signalSync sync_reb0(
.clock(clock),
.asynchronous_signal(sensors[0]),
.rising_edge(rising_edge_wire[0]),
.falling_edge(falling_edge_wire[0])
);
always@(posedge clock) begin
if (rising_edge_wire[0])
rebuiltSignal_reg[0] <= 1;
else if (falling_edge_wire[0])
rebuiltSignal_reg[0] <= 0;
end
signalSync sync_reb1(
.clock(clock),
.asynchronous_signal(sensors[1]),
.rising_edge(rising_edge_wire[1]),
.falling_edge(falling_edge_wire[1])
);
always@(posedge clock) begin
if (rising_edge_wire[1])
rebuiltSignal_reg[1] <= 1;
else if (falling_edge_wire[1])
rebuiltSignal_reg[1] <= 0;
end
signalSync sync_reb2(
.clock(clock),
.asynchronous_signal(sensors[2]),
.rising_edge(rising_edge_wire[2]),
.falling_edge(falling_edge_wire[2])
);
always@(posedge clock) begin
if (rising_edge_wire[2])
rebuiltSignal_reg[2] <= 1;
else if (falling_edge_wire[2])
rebuiltSignal_reg[2] <= 0;
end
signalSync sync_reb3(
.clock(clock),
.asynchronous_signal(sensors[3]),
.rising_edge(rising_edge_wire[3]),
.falling_edge(falling_edge_wire[3])
);
always@(posedge clock) begin
if (rising_edge_wire[3])
rebuiltSignal_reg[3] <= 1;
else if (falling_edge_wire[3])
rebuiltSignal_reg[3] <= 0;
end
assign rebuiltSignal = rebuiltSignal_reg;
endmodule | 1 |
3,640 | data/full_repos/permissive/105950166/counter.v | 105,950,166 | counter.v | v | 40 | 92 | [] | [] | [] | null | line:29: before: ";" | null | 1: b"%Error: data/full_repos/permissive/105950166/counter.v:29: syntax error, unexpected ';', expecting '}'\n value <= {CNT_SIZE{1'b0};\n ^\n%Error: Exiting due to 1 error(s)\n" | 1,431 | module | module counter #(
parameter CNT_INPUT_SIZE = 2,
parameter CNT_SIZE = 16
) (
input reset_L,
input clk,
input clear,
input en,
input [CNT_INPUT_SIZE-1:0] inc,
output logic non_zero_value,
output logic error_overflow,
output logic [ CNT_SIZE-1:0] value
);
wire [CNT_SIZE:0] next_value;
assign next_value = value+inc;
always_ff @(posedge clk) begin
if( reset_L==0 ) begin
error_overflow <= 1'b0;
value <= {CNT_SIZE{1'b0}};
end
else begin
if( clear ) begin
error_overflow <= 1'b0;
value <= {CNT_SIZE{1'b0};
end
else
if( en )
{error_overflow,value} <= next_value|{error_overflow,{CNT_SIZE{1'b0}}};
end
end
assign non_zero_value = |value;
endmodule | module counter #(
parameter CNT_INPUT_SIZE = 2,
parameter CNT_SIZE = 16
) (
input reset_L,
input clk,
input clear,
input en,
input [CNT_INPUT_SIZE-1:0] inc,
output logic non_zero_value,
output logic error_overflow,
output logic [ CNT_SIZE-1:0] value
); |
wire [CNT_SIZE:0] next_value;
assign next_value = value+inc;
always_ff @(posedge clk) begin
if( reset_L==0 ) begin
error_overflow <= 1'b0;
value <= {CNT_SIZE{1'b0}};
end
else begin
if( clear ) begin
error_overflow <= 1'b0;
value <= {CNT_SIZE{1'b0};
end
else
if( en )
{error_overflow,value} <= next_value|{error_overflow,{CNT_SIZE{1'b0}}};
end
end
assign non_zero_value = |value;
endmodule | 0 |
3,641 | data/full_repos/permissive/106029354/verilog_source/controller.v | 106,029,354 | controller.v | v | 20 | 47 | [] | [] | [] | [(1, 89)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/controller.v:7: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,432 | module | module controller(
opcode,
ctrl
);
`include "params_proc.v"
input [OPCODE_WIDTH-1:0] opcode;
output reg [CTRL_WIDTH-1:0] ctrl;
always @(opcode) begin
ctrl <= opcode[CTRL_WIDTH-1:0];
end
endmodule | module controller(
opcode,
ctrl
); |
`include "params_proc.v"
input [OPCODE_WIDTH-1:0] opcode;
output reg [CTRL_WIDTH-1:0] ctrl;
always @(opcode) begin
ctrl <= opcode[CTRL_WIDTH-1:0];
end
endmodule | 0 |
3,642 | data/full_repos/permissive/106029354/verilog_source/mem_data.v | 106,029,354 | mem_data.v | v | 32 | 60 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_data.v:10: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,433 | module | module mem_data(
clk,
we,
addr,
data_in,
data_out
);
`include "params_proc.v"
input clk, we;
input [MEM_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output reg [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] mem [0:(1<<MEM_WIDTH)-1];
always @(posedge clk) begin
if (we) begin
mem[addr] <= data_in;
data_out <= data_in;
end else begin
data_out <= mem[addr];
end
end
endmodule | module mem_data(
clk,
we,
addr,
data_in,
data_out
); |
`include "params_proc.v"
input clk, we;
input [MEM_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output reg [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] mem [0:(1<<MEM_WIDTH)-1];
always @(posedge clk) begin
if (we) begin
mem[addr] <= data_in;
data_out <= data_in;
end else begin
data_out <= mem[addr];
end
end
endmodule | 0 |
3,643 | data/full_repos/permissive/106029354/verilog_source/mem_dport_sclk.v | 106,029,354 | mem_dport_sclk.v | v | 48 | 64 | [] | [] | [] | [(3, 117)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_dport_sclk.v:16: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,434 | module | module mem_dport_sclk(
clk,
we_a,
we_b,
data_a,
data_b,
addr_a,
addr_b,
out_a,
out_b
);
`include "params_proc.v"
input clk, we_a, we_b;
input signed [DATA_WIDTH-1:0] data_a, data_b;
input [MEM_WIDTH-1:0] addr_a, addr_b;
output reg [DATA_WIDTH-1:0] out_a, out_b;
reg [DATA_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
always @ (posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
out_a <= data_a;
end else begin
out_a <= ram[addr_a];
end
end
always @ (posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
out_b <= data_b;
end else begin
out_b <= ram[addr_b];
end
end
endmodule | module mem_dport_sclk(
clk,
we_a,
we_b,
data_a,
data_b,
addr_a,
addr_b,
out_a,
out_b
); |
`include "params_proc.v"
input clk, we_a, we_b;
input signed [DATA_WIDTH-1:0] data_a, data_b;
input [MEM_WIDTH-1:0] addr_a, addr_b;
output reg [DATA_WIDTH-1:0] out_a, out_b;
reg [DATA_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
always @ (posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
out_a <= data_a;
end else begin
out_a <= ram[addr_a];
end
end
always @ (posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
out_b <= data_b;
end else begin
out_b <= ram[addr_b];
end
end
endmodule | 0 |
3,644 | data/full_repos/permissive/106029354/verilog_source/mem_program.v | 106,029,354 | mem_program.v | v | 38 | 66 | [] | [] | [] | [(1, 107)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_program.v:10: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,435 | module | module mem_program(
clk,
we,
addr,
data_in,
data_out
);
`include "params_proc.v"
input clk, we;
input [INSTR_WIDTH-1:0] data_in;
input [MEM_WIDTH-1:0] addr;
output reg [INSTR_WIDTH-1:0] data_out;
reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data_in;
data_out <= data_in;
end else begin
data_out <= ram[addr];
end
end
initial begin
$readmemb("../assembler/program.bin", ram);
end
endmodule | module mem_program(
clk,
we,
addr,
data_in,
data_out
); |
`include "params_proc.v"
input clk, we;
input [INSTR_WIDTH-1:0] data_in;
input [MEM_WIDTH-1:0] addr;
output reg [INSTR_WIDTH-1:0] data_out;
reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data_in;
data_out <= data_in;
end else begin
data_out <= ram[addr];
end
end
initial begin
$readmemb("../assembler/program.bin", ram);
end
endmodule | 0 |
3,645 | data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v | 106,029,354 | mem_program_testbench.v | v | 106 | 67 | [] | [] | [] | [(1, 175)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,436 | module | module mem_program_testbench();
`include "params_proc.v"
parameter N_TESTES = 6;
integer testes;
reg clk, we;
reg [MEM_WIDTH-1:0] addr;
reg [INSTR_WIDTH-1:0] data_in;
wire [INSTR_WIDTH-1:0] data_out;
mem_program mem_inst (
.clk(clk), .we(we), .addr(addr),
.data_in(data_in), .data_out(data_out));
initial begin
testes = -1;
clk = 0;
addr = PC_INITIAL - 1;
we = 0;
data_in = 0;
end
always begin
#4;
clk = !clk;
end
always @(negedge clk) begin
testes = testes+1;
case(testes)
0: begin
we = 1;
addr = addr + 1;
data_in = 32'h0050;
end
1: begin
we = 1;
addr = addr + 1;
data_in = 32'h0850;
end
2: begin
we = 1;
addr = addr + 1;
data_in = 32'h8152;
end
3: begin
we = 0;
addr = PC_INITIAL;
data_in = 32'h1550;
end
4: begin
we = 0;
addr = addr+1;
data_in = 32'h2875;
end
5: begin
we = 0;
addr = addr+1;
data_in = 32'h1647;
end
default: begin
end
endcase
end
always @(posedge clk) begin
if (testes >= 0 && testes <= N_TESTES) begin
if (testes > 0) begin
$display("\t ------- SAIDAS ------- ");
$display("\t DATA_OUT (%3d): %h ", INSTR_WIDTH, data_out);
$display(" ");
end
if (testes < N_TESTES) begin
$display(" Teste # %2d => ", testes);
$display("\t ------- ENTRADAS ------- ");
$display("\t WE: %6d ", we);
$display("\t ADDR: %6d ", addr);
$display("\t DATA_IN (%3d): %h ", INSTR_WIDTH, data_in);
$display(" ");
end
end
end
endmodule | module mem_program_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 6;
integer testes;
reg clk, we;
reg [MEM_WIDTH-1:0] addr;
reg [INSTR_WIDTH-1:0] data_in;
wire [INSTR_WIDTH-1:0] data_out;
mem_program mem_inst (
.clk(clk), .we(we), .addr(addr),
.data_in(data_in), .data_out(data_out));
initial begin
testes = -1;
clk = 0;
addr = PC_INITIAL - 1;
we = 0;
data_in = 0;
end
always begin
#4;
clk = !clk;
end
always @(negedge clk) begin
testes = testes+1;
case(testes)
0: begin
we = 1;
addr = addr + 1;
data_in = 32'h0050;
end
1: begin
we = 1;
addr = addr + 1;
data_in = 32'h0850;
end
2: begin
we = 1;
addr = addr + 1;
data_in = 32'h8152;
end
3: begin
we = 0;
addr = PC_INITIAL;
data_in = 32'h1550;
end
4: begin
we = 0;
addr = addr+1;
data_in = 32'h2875;
end
5: begin
we = 0;
addr = addr+1;
data_in = 32'h1647;
end
default: begin
end
endcase
end
always @(posedge clk) begin
if (testes >= 0 && testes <= N_TESTES) begin
if (testes > 0) begin
$display("\t ------- SAIDAS ------- ");
$display("\t DATA_OUT (%3d): %h ", INSTR_WIDTH, data_out);
$display(" ");
end
if (testes < N_TESTES) begin
$display(" Teste # %2d => ", testes);
$display("\t ------- ENTRADAS ------- ");
$display("\t WE: %6d ", we);
$display("\t ADDR: %6d ", addr);
$display("\t DATA_IN (%3d): %h ", INSTR_WIDTH, data_in);
$display(" ");
end
end
end
endmodule | 0 |
3,646 | data/full_repos/permissive/106029354/verilog_source/multiplexador.v | 106,029,354 | multiplexador.v | v | 15 | 61 | [] | [] | [] | null | line:12: before: "out" | data/verilator_xmls/e1dab13e-2a85-4cfa-b86d-7cd3083b3bac.xml | null | 1,437 | module | module mux_4x1(in_1, in_2, in_3, in_4, sel_1, sel_2, out);
output reg out;
input in_1, in_2, in_3, in_4, sel_1, sel_2;
always @(sel_1, sel_2)
begin
case({sel_1, sel_2})
0: out = in_1;
1: out = in_2;
2: out = in_3;
3: out = in_4;
default out = 1'bx;
endcase
end
endmodule | module mux_4x1(in_1, in_2, in_3, in_4, sel_1, sel_2, out); |
output reg out;
input in_1, in_2, in_3, in_4, sel_1, sel_2;
always @(sel_1, sel_2)
begin
case({sel_1, sel_2})
0: out = in_1;
1: out = in_2;
2: out = in_3;
3: out = in_4;
default out = 1'bx;
endcase
end
endmodule | 0 |
3,647 | data/full_repos/permissive/106029354/verilog_source/pipeline.v | 106,029,354 | pipeline.v | v | 102 | 119 | [] | [] | [] | [(1, 170)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline.v:7: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,439 | module | module pipeline(
clk_in,
RST
);
`include "params_proc.v"
input clk_in, RST;
wire pc_chg_p1;
wire [PC_WIDTH-1:0] pc_in_p1, pc_out_p1;
wire [INSTR_WIDTH-1:0] instr;
wire [REG_ADDR_WIDTH-1:0] reg_addr_p2;
wire [DATA_WIDTH-1:0] reg_data_p2;
wire reg_en_p2;
wire [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
wire [DATA_WIDTH-1:0] A, B, imm;
wire [PC_WIDTH-1:0] pc_out_p2;
wire [CTRL_WIDTH-1:0] ctrl_p2;
wire mem_we_p3;
wire [DATA_WIDTH-1:0] data_p3;
wire [MEM_WIDTH-1:0] addr_p3;
wire [REG_ADDR_WIDTH-1:0] reg_addr_p3;
wire [CTRL_WIDTH-1:0] ctrl_out_p3;
wire [DATA_WIDTH-1:0] reg_data_out_p4;
wire [REG_ADDR_WIDTH-1:0] reg_addr_out_p4;
wire [CTRL_WIDTH-1:0] ctrl_out_p4;
pipeline1 pipe1(.clk_in(clk_in), .RST(RST),
.pc_chg(pc_chg_p1), .pc_in(pc_in_p1), .pc_out(pc_out_p1),
.instr(instr)
);
pipeline2 pipe2(
.clk_in(clk_in), .RST(RST),
.pc_in(pc_out_p1),
.instr(instr),
.reg_addr(reg_addr_p2), .reg_data(reg_data_p2), .reg_en(reg_en_p2),
.A_addr(A_addr), .B_addr(B_addr),
.A(A), .B(B), .imm(imm),
.pc_out(pc_out_p2),
.ctrl(ctrl_p2)
);
pipeline3 pipe3(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_p2), .pc_in(pc_out_p2),
.A_addr(A_addr), .B_addr(B_addr),
.A(A), .B(B), .imm(imm),
.pc_chg(pc_chg_p1), .pc_out(pc_in_p1),
.mem_we(mem_we_p3), .data(data_p3), .addr(addr_p3),
.reg_addr(reg_addr_p3), .ctrl_out(ctrl_out_p3)
);
pipeline4 pipe4(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_out_p3),
.we(mem_we_p3), .data(data_p3), .addr(addr_p3),
.reg_addr_in(reg_addr_p3),
.reg_data_out(reg_data_out_p4), .reg_addr_out(reg_addr_out_p4),
.ctrl_out(ctrl_out_p4)
);
pipeline5 pipe5(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_out_p4),
.data(reg_data_out_p4), .addr(reg_addr_out_p4),
.data_out(reg_data_p2), .addr_out(reg_addr_p2), .en_out(reg_en_p2)
);
endmodule | module pipeline(
clk_in,
RST
); |
`include "params_proc.v"
input clk_in, RST;
wire pc_chg_p1;
wire [PC_WIDTH-1:0] pc_in_p1, pc_out_p1;
wire [INSTR_WIDTH-1:0] instr;
wire [REG_ADDR_WIDTH-1:0] reg_addr_p2;
wire [DATA_WIDTH-1:0] reg_data_p2;
wire reg_en_p2;
wire [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
wire [DATA_WIDTH-1:0] A, B, imm;
wire [PC_WIDTH-1:0] pc_out_p2;
wire [CTRL_WIDTH-1:0] ctrl_p2;
wire mem_we_p3;
wire [DATA_WIDTH-1:0] data_p3;
wire [MEM_WIDTH-1:0] addr_p3;
wire [REG_ADDR_WIDTH-1:0] reg_addr_p3;
wire [CTRL_WIDTH-1:0] ctrl_out_p3;
wire [DATA_WIDTH-1:0] reg_data_out_p4;
wire [REG_ADDR_WIDTH-1:0] reg_addr_out_p4;
wire [CTRL_WIDTH-1:0] ctrl_out_p4;
pipeline1 pipe1(.clk_in(clk_in), .RST(RST),
.pc_chg(pc_chg_p1), .pc_in(pc_in_p1), .pc_out(pc_out_p1),
.instr(instr)
);
pipeline2 pipe2(
.clk_in(clk_in), .RST(RST),
.pc_in(pc_out_p1),
.instr(instr),
.reg_addr(reg_addr_p2), .reg_data(reg_data_p2), .reg_en(reg_en_p2),
.A_addr(A_addr), .B_addr(B_addr),
.A(A), .B(B), .imm(imm),
.pc_out(pc_out_p2),
.ctrl(ctrl_p2)
);
pipeline3 pipe3(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_p2), .pc_in(pc_out_p2),
.A_addr(A_addr), .B_addr(B_addr),
.A(A), .B(B), .imm(imm),
.pc_chg(pc_chg_p1), .pc_out(pc_in_p1),
.mem_we(mem_we_p3), .data(data_p3), .addr(addr_p3),
.reg_addr(reg_addr_p3), .ctrl_out(ctrl_out_p3)
);
pipeline4 pipe4(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_out_p3),
.we(mem_we_p3), .data(data_p3), .addr(addr_p3),
.reg_addr_in(reg_addr_p3),
.reg_data_out(reg_data_out_p4), .reg_addr_out(reg_addr_out_p4),
.ctrl_out(ctrl_out_p4)
);
pipeline5 pipe5(
.clk_in(clk_in), .RST(RST),
.ctrl_in(ctrl_out_p4),
.data(reg_data_out_p4), .addr(reg_addr_out_p4),
.data_out(reg_data_p2), .addr_out(reg_addr_p2), .en_out(reg_en_p2)
);
endmodule | 0 |
3,648 | data/full_repos/permissive/106029354/verilog_source/pipeline1.v | 106,029,354 | pipeline1.v | v | 51 | 91 | [] | [] | [] | [(1, 119)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1.v:11: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,440 | module | module pipeline1(
clk_in,
RST,
pc_chg,
pc_in,
instr,
pc_out
);
`include "params_proc.v"
input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;
output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;
reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;
mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));
assign we = 0;
assign data = 0;
assign clk_neg = ~clk_in;
assign pc_out = new_pc + 1;
always @(posedge clk_in) begin
if (!RST) begin
new_pc <= PC_INITIAL;
end else if (pc_chg) begin
new_pc <= pc_in;
end else begin
new_pc <= new_pc + 1;
end
end
endmodule | module pipeline1(
clk_in,
RST,
pc_chg,
pc_in,
instr,
pc_out
); |
`include "params_proc.v"
input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;
output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;
reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;
mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));
assign we = 0;
assign data = 0;
assign clk_neg = ~clk_in;
assign pc_out = new_pc + 1;
always @(posedge clk_in) begin
if (!RST) begin
new_pc <= PC_INITIAL;
end else if (pc_chg) begin
new_pc <= pc_in;
end else begin
new_pc <= new_pc + 1;
end
end
endmodule | 0 |
3,649 | data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v | 106,029,354 | pipeline1_testbench.v | v | 157 | 79 | [] | [] | [] | null | line:110: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:153: Cannot find include file: testbench.v\n`include "testbench.v" \n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 1,441 | module | module pipeline1_testbench();
`include "params_proc.v"
parameter N_TESTES = 7;
reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
reg clk_in, RST, pc_chg;
reg [PC_WIDTH-1:0] pc_in;
wire [INSTR_WIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_out;
pipeline1 pipeline10(
.clk_in(clk_in),
.RST(RST),
.pc_chg(pc_chg),
.pc_in(pc_in),
.instr(instr),
.pc_out(pc_out)
);
task init_input;
begin
pc_chg = 0;
pc_in = 0;
$readmemb("../assembler/program.bin", ram);
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CHG = 0,
TESTE1_IN = 3;
parameter TESTE2_CHG = 0,
TESTE2_IN = 4;
parameter TESTE3_CHG = 1,
TESTE3_IN = 6;
parameter TESTE4_CHG = 0,
TESTE4_IN = 1;
parameter TESTE5_CHG = 1,
TESTE5_IN = 2;
parameter TESTE6_CHG = 0,
TESTE6_IN = 10;
begin
#1
case(testes)
0: begin
pc_chg <= TESTE1_CHG;
pc_in <= TESTE1_IN;
if (pc_out == PC_INITIAL+2 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
pc_chg <= TESTE2_CHG;
pc_in <= TESTE2_IN;
if (pc_out == PC_INITIAL+3 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
pc_chg <= TESTE3_CHG;
pc_in <= TESTE3_IN;
if (pc_out == PC_INITIAL+4 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
pc_chg <= TESTE4_CHG;
pc_in <= TESTE4_IN;
if (pc_out == TESTE3_IN+1 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
pc_chg <= TESTE5_CHG;
pc_in <= TESTE5_IN;
if (pc_out == TESTE3_IN+2 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
pc_chg <= TESTE6_CHG;
pc_in <= TESTE6_IN;
if (pc_out == TESTE5_IN+1 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_CHG: %b ", pc_chg);
$display("\t PC_IN: %6d ", pc_in);
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t INSTR (%3d): %b ", INSTR_WIDTH, instr);
$display("\t PC_OUT: %6d ", pc_out);
end
endtask
`include "testbench.v"
endmodule | module pipeline1_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 7;
reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
reg clk_in, RST, pc_chg;
reg [PC_WIDTH-1:0] pc_in;
wire [INSTR_WIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_out;
pipeline1 pipeline10(
.clk_in(clk_in),
.RST(RST),
.pc_chg(pc_chg),
.pc_in(pc_in),
.instr(instr),
.pc_out(pc_out)
);
task init_input;
begin
pc_chg = 0;
pc_in = 0;
$readmemb("../assembler/program.bin", ram);
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CHG = 0,
TESTE1_IN = 3;
parameter TESTE2_CHG = 0,
TESTE2_IN = 4;
parameter TESTE3_CHG = 1,
TESTE3_IN = 6;
parameter TESTE4_CHG = 0,
TESTE4_IN = 1;
parameter TESTE5_CHG = 1,
TESTE5_IN = 2;
parameter TESTE6_CHG = 0,
TESTE6_IN = 10;
begin
#1
case(testes)
0: begin
pc_chg <= TESTE1_CHG;
pc_in <= TESTE1_IN;
if (pc_out == PC_INITIAL+2 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
pc_chg <= TESTE2_CHG;
pc_in <= TESTE2_IN;
if (pc_out == PC_INITIAL+3 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
pc_chg <= TESTE3_CHG;
pc_in <= TESTE3_IN;
if (pc_out == PC_INITIAL+4 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
pc_chg <= TESTE4_CHG;
pc_in <= TESTE4_IN;
if (pc_out == TESTE3_IN+1 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
pc_chg <= TESTE5_CHG;
pc_in <= TESTE5_IN;
if (pc_out == TESTE3_IN+2 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
pc_chg <= TESTE6_CHG;
pc_in <= TESTE6_IN;
if (pc_out == TESTE5_IN+1 && instr == ram[pc_out-1]) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_CHG: %b ", pc_chg);
$display("\t PC_IN: %6d ", pc_in);
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t INSTR (%3d): %b ", INSTR_WIDTH, instr);
$display("\t PC_OUT: %6d ", pc_out);
end
endtask
`include "testbench.v"
endmodule | 0 |
3,650 | data/full_repos/permissive/106029354/verilog_source/pipeline2.v | 106,029,354 | pipeline2.v | v | 74 | 85 | [] | [] | [] | [(1, 142)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline2.v:19: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,442 | module | module pipeline2(
clk_in,
RST,
pc_in,
instr,
reg_addr,
reg_data,
reg_en,
A_addr,
B_addr,
A,
B,
imm,
pc_out,
ctrl
);
`include "params_proc.v"
input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;
output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;
reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;
controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
.en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
.addr_read1(A_addr), .addr_read2(B_addr),
.data_read1(A), .data_read2(B));
assign clk_neg = ~clk_in;
always @(posedge clk_in) begin
if (!RST) begin
opcode <= NOP;
A_addr <= 0;
B_addr <= 0;
imm <= 0;
pc_out <= PC_INITIAL + 1;
end else begin
opcode <= instr[OPCODE_WIDTH-1:0];
A_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
B_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
imm <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];
if (instr[OPCODE_WIDTH-1:0] == RET) begin
A_addr <= REG_FUNC_RET;
end
pc_out <= pc_in;
end
end
endmodule | module pipeline2(
clk_in,
RST,
pc_in,
instr,
reg_addr,
reg_data,
reg_en,
A_addr,
B_addr,
A,
B,
imm,
pc_out,
ctrl
); |
`include "params_proc.v"
input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;
output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;
reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;
controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
.en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
.addr_read1(A_addr), .addr_read2(B_addr),
.data_read1(A), .data_read2(B));
assign clk_neg = ~clk_in;
always @(posedge clk_in) begin
if (!RST) begin
opcode <= NOP;
A_addr <= 0;
B_addr <= 0;
imm <= 0;
pc_out <= PC_INITIAL + 1;
end else begin
opcode <= instr[OPCODE_WIDTH-1:0];
A_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
B_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
imm <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];
if (instr[OPCODE_WIDTH-1:0] == RET) begin
A_addr <= REG_FUNC_RET;
end
pc_out <= pc_in;
end
end
endmodule | 0 |
3,651 | data/full_repos/permissive/106029354/verilog_source/pipeline2_testbench.v | 106,029,354 | pipeline2_testbench.v | v | 535 | 243 | [] | [] | [] | null | line:123: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline2_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline2_testbench.v:531: Cannot find include file: testbench.v\n`include "testbench.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 1,443 | module | module pipeline2_testbench();
`include "params_proc.v"
parameter N_TESTES = 18;
reg clk_in, RST;
reg [PC_WIDTH-1:0] pc_in;
reg [INSTR_WIDTH-1:0] instr;
reg [REG_ADDR_WIDTH-1:0] reg_addr;
reg [DATA_WIDTH-1:0] reg_data;
reg reg_en;
wire signed [DATA_WIDTH-1:0] A, B, imm;
wire [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
wire [PC_WIDTH-1:0] pc_out;
wire [CTRL_WIDTH-1:0] ctrl;
pipeline2 pipeline20(
.clk_in(clk_in),
.RST(RST),
.pc_in(pc_in),
.instr(instr),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_en(reg_en),
.A_addr(A_addr),
.B_addr(B_addr),
.A(A),
.B(B),
.imm(imm),
.ctrl(ctrl),
.pc_out(pc_out)
);
task init_input;
begin
pc_in = PC_INITIAL;
instr = NOP;
reg_addr = 0;
reg_data = 0;
reg_en = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_OPCODE = ADD,
TESTE1_A_ADDR = 31,
TESTE1_B_ADDR = 0,
TESTE1_IMM = 85,
TESTE1_PC_IN = 758,
TESTE1_REG_ADDR = TESTE1_A_ADDR,
TESTE1_REG_DATA = 5,
TESTE1_REG_EN = 1;
parameter TESTE2_OPCODE = SUB,
TESTE2_A_ADDR = 3,
TESTE2_B_ADDR = 17,
TESTE2_IMM = 105,
TESTE2_PC_IN = 1024,
TESTE2_REG_ADDR = 0,
TESTE2_REG_DATA = 5,
TESTE2_REG_EN = 1;
parameter TESTE3_OPCODE = LW,
TESTE3_A_ADDR = 0,
TESTE3_B_ADDR = 3,
TESTE3_IMM = 32767,
TESTE3_PC_IN = 8056,
TESTE3_REG_ADDR = 2,
TESTE3_REG_DATA = 4,
TESTE3_REG_EN = 0;
parameter TESTE4_OPCODE = CMP,
TESTE4_A_ADDR = 0,
TESTE4_B_ADDR = 3,
TESTE4_IMM = -32768,
TESTE4_PC_IN = 0,
TESTE4_REG_ADDR = 3,
TESTE4_REG_DATA = 9,
TESTE4_REG_EN = 1;
parameter TESTE5_OPCODE = MUL,
TESTE5_A_ADDR = 2,
TESTE5_B_ADDR = 3,
TESTE5_IMM = 0,
TESTE5_PC_IN = 64000,
TESTE5_REG_ADDR = 2,
TESTE5_REG_DATA = 16,
TESTE5_REG_EN = 1;
parameter TESTE6_OPCODE = DIV,
TESTE6_A_ADDR = 2,
TESTE6_B_ADDR = 0,
TESTE6_IMM = 145,
TESTE6_PC_IN = 65535,
TESTE6_REG_ADDR = 2,
TESTE6_REG_DATA = 25,
TESTE6_REG_EN = 0;
parameter TESTE7_OPCODE = AND,
TESTE7_A_ADDR = 2,
TESTE7_B_ADDR = 0,
TESTE7_IMM = 145,
TESTE7_PC_IN = 4040,
TESTE7_REG_ADDR = 1,
TESTE7_REG_DATA = 305,
TESTE7_REG_EN = 0;
parameter TESTE8_OPCODE = OR,
TESTE8_A_ADDR = 3,
TESTE8_B_ADDR = 1,
TESTE8_IMM = 1851,
TESTE8_PC_IN = 4654,
TESTE8_REG_ADDR = 6,
TESTE8_REG_DATA = 3415,
TESTE8_REG_EN = 0;
parameter TESTE9_OPCODE = NOT,
TESTE9_A_ADDR = 0,
TESTE9_B_ADDR = 6,
TESTE9_IMM = 1601,
TESTE9_PC_IN = 7584,
TESTE9_REG_ADDR = 9,
TESTE9_REG_DATA = 30115,
TESTE9_REG_EN = 0;
parameter TESTE10_OPCODE = CMP,
TESTE10_A_ADDR = 5,
TESTE10_B_ADDR = 10,
TESTE10_IMM = 18546,
TESTE10_PC_IN = 45012,
TESTE10_REG_ADDR = 15,
TESTE10_REG_DATA = 40254,
TESTE10_REG_EN = 0;
parameter TESTE11_OPCODE = JR,
TESTE11_A_ADDR = 31,
TESTE11_B_ADDR = 28,
TESTE11_IMM = 14521,
TESTE11_PC_IN = 32415,
TESTE11_REG_ADDR = 17,
TESTE11_REG_DATA = 32000,
TESTE11_REG_EN = 0;
parameter TESTE12_OPCODE = JPC,
TESTE12_A_ADDR = 12,
TESTE12_B_ADDR = 13,
TESTE12_IMM = 24821,
TESTE12_PC_IN = 52675,
TESTE12_REG_ADDR = 30,
TESTE12_REG_DATA = 45014,
TESTE12_REG_EN = 0;
parameter TESTE13_OPCODE = BRFL,
TESTE13_A_ADDR = 14,
TESTE13_B_ADDR = 22,
TESTE13_IMM = 31052,
TESTE13_PC_IN = 42890,
TESTE13_REG_ADDR = 26,
TESTE13_REG_DATA = 17084,
TESTE13_REG_EN = 0;
parameter TESTE14_OPCODE = CALL,
TESTE14_A_ADDR = 23,
TESTE14_B_ADDR = 29,
TESTE14_IMM = 32000,
TESTE14_PC_IN = 2090,
TESTE14_REG_ADDR = 31,
TESTE14_REG_DATA = 20000,
TESTE14_REG_EN = 1;
parameter TESTE15_OPCODE = RET,
TESTE15_A_ADDR = 27,
TESTE15_B_ADDR = 4,
TESTE15_IMM = 358,
TESTE15_PC_IN = 896,
TESTE15_REG_ADDR = 10,
TESTE15_REG_DATA = 2587,
TESTE15_REG_EN = 0;
parameter TESTE16_OPCODE = NOP,
TESTE16_A_ADDR = 11,
TESTE16_B_ADDR = 16,
TESTE16_IMM = 4751,
TESTE16_PC_IN = 6521,
TESTE16_REG_ADDR = 17,
TESTE16_REG_DATA = 1125,
TESTE16_REG_EN = 0;
parameter TESTE17_OPCODE = LW_IMM,
TESTE17_A_ADDR = 3,
TESTE17_B_ADDR = 0,
TESTE17_IMM = 3000,
TESTE17_PC_IN = 8056,
TESTE17_REG_ADDR = 2,
TESTE17_REG_DATA = 4,
TESTE17_REG_EN = 0;
begin
case(testes)
0: begin
instr[OPCODE_WIDTH-1:0] <= TESTE1_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE1_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE1_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE1_IMM;
pc_in <= TESTE1_PC_IN;
reg_addr <= TESTE1_REG_ADDR;
reg_data <= TESTE1_REG_DATA;
reg_en <= TESTE1_REG_EN;
if (ctrl == NOP && pc_out == PC_INITIAL+1) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
instr[OPCODE_WIDTH-1:0] <= TESTE2_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE2_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE2_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE2_IMM;
pc_in <= TESTE2_PC_IN;
reg_addr <= TESTE2_REG_ADDR;
reg_data <= TESTE2_REG_DATA;
reg_en <= TESTE2_REG_EN;
if (ctrl == TESTE1_OPCODE && A_addr == TESTE1_A_ADDR && B_addr == TESTE1_B_ADDR && imm == TESTE1_IMM && pc_out == TESTE1_PC_IN && A == TESTE1_REG_DATA) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
instr[OPCODE_WIDTH-1:0] <= TESTE3_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE3_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE3_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE3_IMM;
pc_in <= TESTE3_PC_IN;
reg_addr <= TESTE3_REG_ADDR;
reg_data <= TESTE3_REG_DATA;
reg_en <= TESTE3_REG_EN;
if (ctrl == TESTE2_OPCODE && A_addr == TESTE2_A_ADDR && B_addr == TESTE2_B_ADDR && imm == TESTE2_IMM && pc_out == TESTE2_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
instr[OPCODE_WIDTH-1:0] <= TESTE4_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE4_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE4_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE4_IMM;
pc_in <= TESTE4_PC_IN;
reg_addr <= TESTE4_REG_ADDR;
reg_data <= TESTE4_REG_DATA;
reg_en <= TESTE4_REG_EN;
if (ctrl == TESTE3_OPCODE && A_addr == TESTE3_A_ADDR && B_addr == TESTE3_B_ADDR && imm == TESTE3_IMM && pc_out == TESTE3_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
instr[OPCODE_WIDTH-1:0] <= TESTE5_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE5_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE5_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE5_IMM;
pc_in <= TESTE5_PC_IN;
reg_addr <= TESTE5_REG_ADDR;
reg_data <= TESTE5_REG_DATA;
reg_en <= TESTE5_REG_EN;
if (ctrl == TESTE4_OPCODE && A_addr == TESTE4_A_ADDR && B_addr == TESTE4_B_ADDR && imm == TESTE4_IMM && pc_out == TESTE4_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
instr[OPCODE_WIDTH-1:0] <= TESTE6_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE6_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE6_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE6_IMM;
pc_in <= TESTE6_PC_IN;
reg_addr <= TESTE6_REG_ADDR;
reg_data <= TESTE6_REG_DATA;
reg_en <= TESTE6_REG_EN;
if (ctrl == TESTE5_OPCODE && A_addr == TESTE5_A_ADDR && B_addr == TESTE5_B_ADDR && imm == TESTE5_IMM && pc_out == TESTE5_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
instr[OPCODE_WIDTH-1:0] <= TESTE7_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE7_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE7_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE7_IMM;
pc_in <= TESTE7_PC_IN;
reg_addr <= TESTE7_REG_ADDR;
reg_data <= TESTE7_REG_DATA;
reg_en <= TESTE7_REG_EN;
if (ctrl == TESTE6_OPCODE && A_addr == TESTE6_A_ADDR && B_addr == TESTE6_B_ADDR && imm == TESTE6_IMM && pc_out == TESTE6_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
instr[OPCODE_WIDTH-1:0] <= TESTE8_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE8_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE8_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE8_IMM;
pc_in <= TESTE8_PC_IN;
reg_addr <= TESTE8_REG_ADDR;
reg_data <= TESTE8_REG_DATA;
reg_en <= TESTE8_REG_EN;
if (ctrl == TESTE7_OPCODE && A_addr == TESTE7_A_ADDR && B_addr == TESTE7_B_ADDR && imm == TESTE7_IMM && pc_out == TESTE7_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
instr[OPCODE_WIDTH-1:0] <= TESTE9_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE9_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE9_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE9_IMM;
pc_in <= TESTE9_PC_IN;
reg_addr <= TESTE9_REG_ADDR;
reg_data <= TESTE9_REG_DATA;
reg_en <= TESTE9_REG_EN;
if (ctrl == TESTE8_OPCODE && A_addr == TESTE8_A_ADDR && B_addr == TESTE8_B_ADDR && imm == TESTE8_IMM && pc_out == TESTE8_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
instr[OPCODE_WIDTH-1:0] <= TESTE10_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE10_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE10_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE10_IMM;
pc_in <= TESTE10_PC_IN;
reg_addr <= TESTE10_REG_ADDR;
reg_data <= TESTE10_REG_DATA;
reg_en <= TESTE10_REG_EN;
if (ctrl == TESTE9_OPCODE && A_addr == TESTE9_A_ADDR && B_addr == TESTE9_B_ADDR && imm == TESTE9_IMM && pc_out == TESTE9_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
instr[OPCODE_WIDTH-1:0] <= TESTE11_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE11_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE11_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE11_IMM;
pc_in <= TESTE11_PC_IN;
reg_addr <= TESTE11_REG_ADDR;
reg_data <= TESTE11_REG_DATA;
reg_en <= TESTE11_REG_EN;
if (ctrl == TESTE10_OPCODE && A_addr == TESTE10_A_ADDR && B_addr == TESTE10_B_ADDR && imm == TESTE10_IMM && pc_out == TESTE10_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
instr[OPCODE_WIDTH-1:0] <= TESTE12_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE12_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE12_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE12_IMM;
pc_in <= TESTE12_PC_IN;
reg_addr <= TESTE12_REG_ADDR;
reg_data <= TESTE12_REG_DATA;
reg_en <= TESTE12_REG_EN;
if (ctrl == TESTE11_OPCODE && A_addr == TESTE11_A_ADDR && B_addr == TESTE11_B_ADDR && imm == TESTE11_IMM && pc_out == TESTE11_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
instr[OPCODE_WIDTH-1:0] <= TESTE13_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE13_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE13_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE13_IMM;
pc_in <= TESTE13_PC_IN;
reg_addr <= TESTE13_REG_ADDR;
reg_data <= TESTE13_REG_DATA;
reg_en <= TESTE13_REG_EN;
if (ctrl == TESTE12_OPCODE && A_addr == TESTE12_A_ADDR && B_addr == TESTE12_B_ADDR && imm == TESTE12_IMM && pc_out == TESTE12_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
instr[OPCODE_WIDTH-1:0] <= TESTE14_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE14_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE14_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE14_IMM;
pc_in <= TESTE14_PC_IN;
reg_addr <= TESTE14_REG_ADDR;
reg_data <= TESTE14_REG_DATA;
reg_en <= TESTE14_REG_EN;
if (ctrl == TESTE13_OPCODE && A_addr == TESTE13_A_ADDR && B_addr == TESTE13_B_ADDR && imm == TESTE13_IMM && pc_out == TESTE13_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
instr[OPCODE_WIDTH-1:0] <= TESTE15_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE15_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE15_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE15_IMM;
pc_in <= TESTE15_PC_IN;
reg_addr <= TESTE15_REG_ADDR;
reg_data <= TESTE15_REG_DATA;
reg_en <= TESTE15_REG_EN;
if (ctrl == TESTE14_OPCODE && A_addr == TESTE14_A_ADDR && B_addr == TESTE14_B_ADDR && imm == TESTE14_IMM && pc_out == TESTE14_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
instr[OPCODE_WIDTH-1:0] <= TESTE16_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE16_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE16_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE16_IMM;
pc_in <= TESTE16_PC_IN;
reg_addr <= TESTE16_REG_ADDR;
reg_data <= TESTE16_REG_DATA;
reg_en <= TESTE16_REG_EN;
if (ctrl == TESTE15_OPCODE && A_addr == TESTE15_A_ADDR && B_addr == TESTE15_B_ADDR && imm == TESTE15_IMM && pc_out == TESTE15_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
status <= 0;
end
16: begin
instr[OPCODE_WIDTH-1:0] <= TESTE17_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE17_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE17_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE17_IMM;
pc_in <= TESTE17_PC_IN;
reg_addr <= TESTE17_REG_ADDR;
reg_data <= TESTE17_REG_DATA;
reg_en <= TESTE17_REG_EN;
if (ctrl == TESTE16_OPCODE && A_addr == TESTE16_A_ADDR && B_addr == TESTE16_B_ADDR && imm == TESTE16_IMM && pc_out == TESTE16_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_IN: %6d ", pc_in);
$display("\t REG_WRITE - EN: %b - ADDR: %3d - DATA: %6d ", reg_en, reg_addr, reg_data);
$display("\t INSTR (%2d): %b ", INSTR_WIDTH, instr);
$display("\t IMM (%2d): %b (%6d)", (INSTR_WIDTH)-(OPCODE_WIDTH+REG_ADDR_WIDTH*2), instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2], instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2]);
$display("\t REG_2 (%2d): %b (%2d)", (OPCODE_WIDTH+REG_ADDR_WIDTH*2)-(OPCODE_WIDTH+REG_ADDR_WIDTH), instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH], instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH]);
$display("\t REG_1 (%2d): %b (%2d)", (OPCODE_WIDTH+REG_ADDR_WIDTH)-(OPCODE_WIDTH), instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH], instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH]);
$write( "\t OPCODE (%2d): %b (", OPCODE_WIDTH, instr[OPCODE_WIDTH-1:0]);
case(instr[OPCODE_WIDTH-1:0])
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t B: %6d ", B);
$display("\t A: %6d", A);
$display("\t IMM: %6d ", imm);
$display("\t CTRL: %b ", ctrl);
$display("\t PC_OUT: %6d ", pc_out);
$display(" ");
end
endtask
`include "testbench.v"
endmodule | module pipeline2_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 18;
reg clk_in, RST;
reg [PC_WIDTH-1:0] pc_in;
reg [INSTR_WIDTH-1:0] instr;
reg [REG_ADDR_WIDTH-1:0] reg_addr;
reg [DATA_WIDTH-1:0] reg_data;
reg reg_en;
wire signed [DATA_WIDTH-1:0] A, B, imm;
wire [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
wire [PC_WIDTH-1:0] pc_out;
wire [CTRL_WIDTH-1:0] ctrl;
pipeline2 pipeline20(
.clk_in(clk_in),
.RST(RST),
.pc_in(pc_in),
.instr(instr),
.reg_addr(reg_addr),
.reg_data(reg_data),
.reg_en(reg_en),
.A_addr(A_addr),
.B_addr(B_addr),
.A(A),
.B(B),
.imm(imm),
.ctrl(ctrl),
.pc_out(pc_out)
);
task init_input;
begin
pc_in = PC_INITIAL;
instr = NOP;
reg_addr = 0;
reg_data = 0;
reg_en = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_OPCODE = ADD,
TESTE1_A_ADDR = 31,
TESTE1_B_ADDR = 0,
TESTE1_IMM = 85,
TESTE1_PC_IN = 758,
TESTE1_REG_ADDR = TESTE1_A_ADDR,
TESTE1_REG_DATA = 5,
TESTE1_REG_EN = 1;
parameter TESTE2_OPCODE = SUB,
TESTE2_A_ADDR = 3,
TESTE2_B_ADDR = 17,
TESTE2_IMM = 105,
TESTE2_PC_IN = 1024,
TESTE2_REG_ADDR = 0,
TESTE2_REG_DATA = 5,
TESTE2_REG_EN = 1;
parameter TESTE3_OPCODE = LW,
TESTE3_A_ADDR = 0,
TESTE3_B_ADDR = 3,
TESTE3_IMM = 32767,
TESTE3_PC_IN = 8056,
TESTE3_REG_ADDR = 2,
TESTE3_REG_DATA = 4,
TESTE3_REG_EN = 0;
parameter TESTE4_OPCODE = CMP,
TESTE4_A_ADDR = 0,
TESTE4_B_ADDR = 3,
TESTE4_IMM = -32768,
TESTE4_PC_IN = 0,
TESTE4_REG_ADDR = 3,
TESTE4_REG_DATA = 9,
TESTE4_REG_EN = 1;
parameter TESTE5_OPCODE = MUL,
TESTE5_A_ADDR = 2,
TESTE5_B_ADDR = 3,
TESTE5_IMM = 0,
TESTE5_PC_IN = 64000,
TESTE5_REG_ADDR = 2,
TESTE5_REG_DATA = 16,
TESTE5_REG_EN = 1;
parameter TESTE6_OPCODE = DIV,
TESTE6_A_ADDR = 2,
TESTE6_B_ADDR = 0,
TESTE6_IMM = 145,
TESTE6_PC_IN = 65535,
TESTE6_REG_ADDR = 2,
TESTE6_REG_DATA = 25,
TESTE6_REG_EN = 0;
parameter TESTE7_OPCODE = AND,
TESTE7_A_ADDR = 2,
TESTE7_B_ADDR = 0,
TESTE7_IMM = 145,
TESTE7_PC_IN = 4040,
TESTE7_REG_ADDR = 1,
TESTE7_REG_DATA = 305,
TESTE7_REG_EN = 0;
parameter TESTE8_OPCODE = OR,
TESTE8_A_ADDR = 3,
TESTE8_B_ADDR = 1,
TESTE8_IMM = 1851,
TESTE8_PC_IN = 4654,
TESTE8_REG_ADDR = 6,
TESTE8_REG_DATA = 3415,
TESTE8_REG_EN = 0;
parameter TESTE9_OPCODE = NOT,
TESTE9_A_ADDR = 0,
TESTE9_B_ADDR = 6,
TESTE9_IMM = 1601,
TESTE9_PC_IN = 7584,
TESTE9_REG_ADDR = 9,
TESTE9_REG_DATA = 30115,
TESTE9_REG_EN = 0;
parameter TESTE10_OPCODE = CMP,
TESTE10_A_ADDR = 5,
TESTE10_B_ADDR = 10,
TESTE10_IMM = 18546,
TESTE10_PC_IN = 45012,
TESTE10_REG_ADDR = 15,
TESTE10_REG_DATA = 40254,
TESTE10_REG_EN = 0;
parameter TESTE11_OPCODE = JR,
TESTE11_A_ADDR = 31,
TESTE11_B_ADDR = 28,
TESTE11_IMM = 14521,
TESTE11_PC_IN = 32415,
TESTE11_REG_ADDR = 17,
TESTE11_REG_DATA = 32000,
TESTE11_REG_EN = 0;
parameter TESTE12_OPCODE = JPC,
TESTE12_A_ADDR = 12,
TESTE12_B_ADDR = 13,
TESTE12_IMM = 24821,
TESTE12_PC_IN = 52675,
TESTE12_REG_ADDR = 30,
TESTE12_REG_DATA = 45014,
TESTE12_REG_EN = 0;
parameter TESTE13_OPCODE = BRFL,
TESTE13_A_ADDR = 14,
TESTE13_B_ADDR = 22,
TESTE13_IMM = 31052,
TESTE13_PC_IN = 42890,
TESTE13_REG_ADDR = 26,
TESTE13_REG_DATA = 17084,
TESTE13_REG_EN = 0;
parameter TESTE14_OPCODE = CALL,
TESTE14_A_ADDR = 23,
TESTE14_B_ADDR = 29,
TESTE14_IMM = 32000,
TESTE14_PC_IN = 2090,
TESTE14_REG_ADDR = 31,
TESTE14_REG_DATA = 20000,
TESTE14_REG_EN = 1;
parameter TESTE15_OPCODE = RET,
TESTE15_A_ADDR = 27,
TESTE15_B_ADDR = 4,
TESTE15_IMM = 358,
TESTE15_PC_IN = 896,
TESTE15_REG_ADDR = 10,
TESTE15_REG_DATA = 2587,
TESTE15_REG_EN = 0;
parameter TESTE16_OPCODE = NOP,
TESTE16_A_ADDR = 11,
TESTE16_B_ADDR = 16,
TESTE16_IMM = 4751,
TESTE16_PC_IN = 6521,
TESTE16_REG_ADDR = 17,
TESTE16_REG_DATA = 1125,
TESTE16_REG_EN = 0;
parameter TESTE17_OPCODE = LW_IMM,
TESTE17_A_ADDR = 3,
TESTE17_B_ADDR = 0,
TESTE17_IMM = 3000,
TESTE17_PC_IN = 8056,
TESTE17_REG_ADDR = 2,
TESTE17_REG_DATA = 4,
TESTE17_REG_EN = 0;
begin
case(testes)
0: begin
instr[OPCODE_WIDTH-1:0] <= TESTE1_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE1_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE1_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE1_IMM;
pc_in <= TESTE1_PC_IN;
reg_addr <= TESTE1_REG_ADDR;
reg_data <= TESTE1_REG_DATA;
reg_en <= TESTE1_REG_EN;
if (ctrl == NOP && pc_out == PC_INITIAL+1) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
instr[OPCODE_WIDTH-1:0] <= TESTE2_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE2_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE2_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE2_IMM;
pc_in <= TESTE2_PC_IN;
reg_addr <= TESTE2_REG_ADDR;
reg_data <= TESTE2_REG_DATA;
reg_en <= TESTE2_REG_EN;
if (ctrl == TESTE1_OPCODE && A_addr == TESTE1_A_ADDR && B_addr == TESTE1_B_ADDR && imm == TESTE1_IMM && pc_out == TESTE1_PC_IN && A == TESTE1_REG_DATA) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
instr[OPCODE_WIDTH-1:0] <= TESTE3_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE3_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE3_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE3_IMM;
pc_in <= TESTE3_PC_IN;
reg_addr <= TESTE3_REG_ADDR;
reg_data <= TESTE3_REG_DATA;
reg_en <= TESTE3_REG_EN;
if (ctrl == TESTE2_OPCODE && A_addr == TESTE2_A_ADDR && B_addr == TESTE2_B_ADDR && imm == TESTE2_IMM && pc_out == TESTE2_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
instr[OPCODE_WIDTH-1:0] <= TESTE4_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE4_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE4_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE4_IMM;
pc_in <= TESTE4_PC_IN;
reg_addr <= TESTE4_REG_ADDR;
reg_data <= TESTE4_REG_DATA;
reg_en <= TESTE4_REG_EN;
if (ctrl == TESTE3_OPCODE && A_addr == TESTE3_A_ADDR && B_addr == TESTE3_B_ADDR && imm == TESTE3_IMM && pc_out == TESTE3_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
instr[OPCODE_WIDTH-1:0] <= TESTE5_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE5_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE5_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE5_IMM;
pc_in <= TESTE5_PC_IN;
reg_addr <= TESTE5_REG_ADDR;
reg_data <= TESTE5_REG_DATA;
reg_en <= TESTE5_REG_EN;
if (ctrl == TESTE4_OPCODE && A_addr == TESTE4_A_ADDR && B_addr == TESTE4_B_ADDR && imm == TESTE4_IMM && pc_out == TESTE4_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
instr[OPCODE_WIDTH-1:0] <= TESTE6_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE6_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE6_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE6_IMM;
pc_in <= TESTE6_PC_IN;
reg_addr <= TESTE6_REG_ADDR;
reg_data <= TESTE6_REG_DATA;
reg_en <= TESTE6_REG_EN;
if (ctrl == TESTE5_OPCODE && A_addr == TESTE5_A_ADDR && B_addr == TESTE5_B_ADDR && imm == TESTE5_IMM && pc_out == TESTE5_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
instr[OPCODE_WIDTH-1:0] <= TESTE7_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE7_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE7_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE7_IMM;
pc_in <= TESTE7_PC_IN;
reg_addr <= TESTE7_REG_ADDR;
reg_data <= TESTE7_REG_DATA;
reg_en <= TESTE7_REG_EN;
if (ctrl == TESTE6_OPCODE && A_addr == TESTE6_A_ADDR && B_addr == TESTE6_B_ADDR && imm == TESTE6_IMM && pc_out == TESTE6_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
instr[OPCODE_WIDTH-1:0] <= TESTE8_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE8_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE8_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE8_IMM;
pc_in <= TESTE8_PC_IN;
reg_addr <= TESTE8_REG_ADDR;
reg_data <= TESTE8_REG_DATA;
reg_en <= TESTE8_REG_EN;
if (ctrl == TESTE7_OPCODE && A_addr == TESTE7_A_ADDR && B_addr == TESTE7_B_ADDR && imm == TESTE7_IMM && pc_out == TESTE7_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
instr[OPCODE_WIDTH-1:0] <= TESTE9_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE9_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE9_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE9_IMM;
pc_in <= TESTE9_PC_IN;
reg_addr <= TESTE9_REG_ADDR;
reg_data <= TESTE9_REG_DATA;
reg_en <= TESTE9_REG_EN;
if (ctrl == TESTE8_OPCODE && A_addr == TESTE8_A_ADDR && B_addr == TESTE8_B_ADDR && imm == TESTE8_IMM && pc_out == TESTE8_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
instr[OPCODE_WIDTH-1:0] <= TESTE10_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE10_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE10_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE10_IMM;
pc_in <= TESTE10_PC_IN;
reg_addr <= TESTE10_REG_ADDR;
reg_data <= TESTE10_REG_DATA;
reg_en <= TESTE10_REG_EN;
if (ctrl == TESTE9_OPCODE && A_addr == TESTE9_A_ADDR && B_addr == TESTE9_B_ADDR && imm == TESTE9_IMM && pc_out == TESTE9_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
instr[OPCODE_WIDTH-1:0] <= TESTE11_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE11_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE11_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE11_IMM;
pc_in <= TESTE11_PC_IN;
reg_addr <= TESTE11_REG_ADDR;
reg_data <= TESTE11_REG_DATA;
reg_en <= TESTE11_REG_EN;
if (ctrl == TESTE10_OPCODE && A_addr == TESTE10_A_ADDR && B_addr == TESTE10_B_ADDR && imm == TESTE10_IMM && pc_out == TESTE10_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
instr[OPCODE_WIDTH-1:0] <= TESTE12_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE12_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE12_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE12_IMM;
pc_in <= TESTE12_PC_IN;
reg_addr <= TESTE12_REG_ADDR;
reg_data <= TESTE12_REG_DATA;
reg_en <= TESTE12_REG_EN;
if (ctrl == TESTE11_OPCODE && A_addr == TESTE11_A_ADDR && B_addr == TESTE11_B_ADDR && imm == TESTE11_IMM && pc_out == TESTE11_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
instr[OPCODE_WIDTH-1:0] <= TESTE13_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE13_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE13_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE13_IMM;
pc_in <= TESTE13_PC_IN;
reg_addr <= TESTE13_REG_ADDR;
reg_data <= TESTE13_REG_DATA;
reg_en <= TESTE13_REG_EN;
if (ctrl == TESTE12_OPCODE && A_addr == TESTE12_A_ADDR && B_addr == TESTE12_B_ADDR && imm == TESTE12_IMM && pc_out == TESTE12_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
instr[OPCODE_WIDTH-1:0] <= TESTE14_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE14_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE14_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE14_IMM;
pc_in <= TESTE14_PC_IN;
reg_addr <= TESTE14_REG_ADDR;
reg_data <= TESTE14_REG_DATA;
reg_en <= TESTE14_REG_EN;
if (ctrl == TESTE13_OPCODE && A_addr == TESTE13_A_ADDR && B_addr == TESTE13_B_ADDR && imm == TESTE13_IMM && pc_out == TESTE13_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
instr[OPCODE_WIDTH-1:0] <= TESTE15_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE15_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE15_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE15_IMM;
pc_in <= TESTE15_PC_IN;
reg_addr <= TESTE15_REG_ADDR;
reg_data <= TESTE15_REG_DATA;
reg_en <= TESTE15_REG_EN;
if (ctrl == TESTE14_OPCODE && A_addr == TESTE14_A_ADDR && B_addr == TESTE14_B_ADDR && imm == TESTE14_IMM && pc_out == TESTE14_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
instr[OPCODE_WIDTH-1:0] <= TESTE16_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE16_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE16_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE16_IMM;
pc_in <= TESTE16_PC_IN;
reg_addr <= TESTE16_REG_ADDR;
reg_data <= TESTE16_REG_DATA;
reg_en <= TESTE16_REG_EN;
if (ctrl == TESTE15_OPCODE && A_addr == TESTE15_A_ADDR && B_addr == TESTE15_B_ADDR && imm == TESTE15_IMM && pc_out == TESTE15_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
status <= 0;
end
16: begin
instr[OPCODE_WIDTH-1:0] <= TESTE17_OPCODE;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH] <= TESTE17_A_ADDR;
instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH] <= TESTE17_B_ADDR;
instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2] <= TESTE17_IMM;
pc_in <= TESTE17_PC_IN;
reg_addr <= TESTE17_REG_ADDR;
reg_data <= TESTE17_REG_DATA;
reg_en <= TESTE17_REG_EN;
if (ctrl == TESTE16_OPCODE && A_addr == TESTE16_A_ADDR && B_addr == TESTE16_B_ADDR && imm == TESTE16_IMM && pc_out == TESTE16_PC_IN) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_IN: %6d ", pc_in);
$display("\t REG_WRITE - EN: %b - ADDR: %3d - DATA: %6d ", reg_en, reg_addr, reg_data);
$display("\t INSTR (%2d): %b ", INSTR_WIDTH, instr);
$display("\t IMM (%2d): %b (%6d)", (INSTR_WIDTH)-(OPCODE_WIDTH+REG_ADDR_WIDTH*2), instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2], instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2]);
$display("\t REG_2 (%2d): %b (%2d)", (OPCODE_WIDTH+REG_ADDR_WIDTH*2)-(OPCODE_WIDTH+REG_ADDR_WIDTH), instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH], instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH]);
$display("\t REG_1 (%2d): %b (%2d)", (OPCODE_WIDTH+REG_ADDR_WIDTH)-(OPCODE_WIDTH), instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH], instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH]);
$write( "\t OPCODE (%2d): %b (", OPCODE_WIDTH, instr[OPCODE_WIDTH-1:0]);
case(instr[OPCODE_WIDTH-1:0])
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t B: %6d ", B);
$display("\t A: %6d", A);
$display("\t IMM: %6d ", imm);
$display("\t CTRL: %b ", ctrl);
$display("\t PC_OUT: %6d ", pc_out);
$display(" ");
end
endtask
`include "testbench.v"
endmodule | 0 |
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