Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
3,652 | data/full_repos/permissive/106029354/verilog_source/pipeline3.v | 106,029,354 | pipeline3.v | v | 205 | 59 | [] | [] | [] | [(1, 273)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline3.v:21: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,444 | module | module pipeline3(
clk_in,
RST,
ctrl_in,
pc_in,
A_addr,
B_addr,
A,
B,
imm,
pc_chg,
pc_out,
mem_we,
data,
addr,
reg_addr,
ctrl_out
);
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input [PC_WIDTH-1:0] pc_in;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input signed [DATA_WIDTH-1:0] A, B, imm;
output reg pc_chg;
output reg [PC_WIDTH-1:0] pc_out;
output reg mem_we;
output reg signed [DATA_WIDTH-1:0] data;
output reg [MEM_WIDTH-1:0] addr;
output reg [REG_ADDR_WIDTH-1:0] reg_addr;
output reg [CTRL_WIDTH-1:0] ctrl_out;
reg [RFLAGS_WIDTH-1:0] rflags_last;
wire signed [DATA_WIDTH-1:0] B_imm;
reg ula_to_data;
reg signed [DATA_WIDTH-1:0] data_default;
reg [MEM_WIDTH-1:0] addr_default;
reg signed [DATA_WIDTH-1:0] ula_data1, ula_data2;
reg [OPCODE_WIDTH-1:0] ula_opcode;
wire signed [DATA_WIDTH-1:0] ula_out;
wire [RFLAGS_WIDTH-1:0] rflags;
ula ula0(.opcode(ula_opcode),
.data1(ula_data1), .data2(ula_data2),
.out(ula_out), .rflags(rflags));
always @(negedge clk_in) begin
if (!RST) begin
rflags_last <= 0;
end else begin
rflags_last <= rflags;
end
end
always @(posedge clk_in) begin
if (!RST) begin
ctrl_out <= NOP;
end else begin
ctrl_out <= ctrl_in;
end
end
always @(posedge clk_in) begin
if (!RST) begin
pc_out <= PC_INITIAL + 1;
reg_addr <= 0;
pc_chg <= 0;
ula_to_data <= 0;
data_default <= 0;
addr_default <= 0;
ula_opcode <= NOP;
ula_data1 <= 0;
ula_data2 <= 0;
mem_we <= 0;
end else begin
pc_out <= pc_in;
reg_addr <= A_addr;
pc_chg <= 0;
ula_to_data <= 1;
data_default <= 0;
addr_default <= 0;
ula_opcode <= NOP;
ula_data1 <= 0;
ula_data2 <= 0;
mem_we <= 0;
case(ctrl_in)
LW: begin
ula_to_data <= 0;
ula_opcode <= ADD;
ula_data1 <= B_imm;
ula_data2 <= 0;
reg_addr <= A_addr;
end
LW_IMM: begin
ula_to_data <= 1;
ula_opcode <= ADD;
ula_data1 <= imm;
ula_data2 <= 0;
reg_addr <= A_addr;
end
SW: begin
ula_to_data <= 0;
ula_opcode <= ADD;
ula_data1 <= B_imm;
ula_data2 <= 0;
mem_we <= 1;
data_default <= A;
end
JR: begin
pc_chg <= 1;
pc_out <= A;
end
JPC: begin
pc_chg <= 1;
pc_out <= pc_in + B_imm;
end
BRFL: begin
if (rflags_last[imm[RFLAGS_WIDTH-1:0]] == B) begin
pc_chg <= 1;
pc_out <= A;
end
end
CALL: begin
reg_addr <= REG_FUNC_RET;
ula_to_data <= 1;
ula_opcode <= ADD;
ula_data1 <= pc_in;
ula_data2 <= 0;
pc_chg <= 1;
pc_out <= A;
end
RET: begin
pc_chg <= 1;
pc_out <= A;
end
NOP: begin
end
default: begin
reg_addr <= A_addr;
ula_to_data <= 1;
ula_opcode <= ctrl_in;
ula_data1 <= A;
ula_data2 <= B_imm;
end
endcase
end
end
always @(*) begin
if (ula_to_data) begin
data <= ula_out;
addr <= addr_default;
end else begin
data <= data_default;
addr <= ula_out;
end
end
assign B_imm = B + imm;
endmodule | module pipeline3(
clk_in,
RST,
ctrl_in,
pc_in,
A_addr,
B_addr,
A,
B,
imm,
pc_chg,
pc_out,
mem_we,
data,
addr,
reg_addr,
ctrl_out
); |
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input [PC_WIDTH-1:0] pc_in;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input signed [DATA_WIDTH-1:0] A, B, imm;
output reg pc_chg;
output reg [PC_WIDTH-1:0] pc_out;
output reg mem_we;
output reg signed [DATA_WIDTH-1:0] data;
output reg [MEM_WIDTH-1:0] addr;
output reg [REG_ADDR_WIDTH-1:0] reg_addr;
output reg [CTRL_WIDTH-1:0] ctrl_out;
reg [RFLAGS_WIDTH-1:0] rflags_last;
wire signed [DATA_WIDTH-1:0] B_imm;
reg ula_to_data;
reg signed [DATA_WIDTH-1:0] data_default;
reg [MEM_WIDTH-1:0] addr_default;
reg signed [DATA_WIDTH-1:0] ula_data1, ula_data2;
reg [OPCODE_WIDTH-1:0] ula_opcode;
wire signed [DATA_WIDTH-1:0] ula_out;
wire [RFLAGS_WIDTH-1:0] rflags;
ula ula0(.opcode(ula_opcode),
.data1(ula_data1), .data2(ula_data2),
.out(ula_out), .rflags(rflags));
always @(negedge clk_in) begin
if (!RST) begin
rflags_last <= 0;
end else begin
rflags_last <= rflags;
end
end
always @(posedge clk_in) begin
if (!RST) begin
ctrl_out <= NOP;
end else begin
ctrl_out <= ctrl_in;
end
end
always @(posedge clk_in) begin
if (!RST) begin
pc_out <= PC_INITIAL + 1;
reg_addr <= 0;
pc_chg <= 0;
ula_to_data <= 0;
data_default <= 0;
addr_default <= 0;
ula_opcode <= NOP;
ula_data1 <= 0;
ula_data2 <= 0;
mem_we <= 0;
end else begin
pc_out <= pc_in;
reg_addr <= A_addr;
pc_chg <= 0;
ula_to_data <= 1;
data_default <= 0;
addr_default <= 0;
ula_opcode <= NOP;
ula_data1 <= 0;
ula_data2 <= 0;
mem_we <= 0;
case(ctrl_in)
LW: begin
ula_to_data <= 0;
ula_opcode <= ADD;
ula_data1 <= B_imm;
ula_data2 <= 0;
reg_addr <= A_addr;
end
LW_IMM: begin
ula_to_data <= 1;
ula_opcode <= ADD;
ula_data1 <= imm;
ula_data2 <= 0;
reg_addr <= A_addr;
end
SW: begin
ula_to_data <= 0;
ula_opcode <= ADD;
ula_data1 <= B_imm;
ula_data2 <= 0;
mem_we <= 1;
data_default <= A;
end
JR: begin
pc_chg <= 1;
pc_out <= A;
end
JPC: begin
pc_chg <= 1;
pc_out <= pc_in + B_imm;
end
BRFL: begin
if (rflags_last[imm[RFLAGS_WIDTH-1:0]] == B) begin
pc_chg <= 1;
pc_out <= A;
end
end
CALL: begin
reg_addr <= REG_FUNC_RET;
ula_to_data <= 1;
ula_opcode <= ADD;
ula_data1 <= pc_in;
ula_data2 <= 0;
pc_chg <= 1;
pc_out <= A;
end
RET: begin
pc_chg <= 1;
pc_out <= A;
end
NOP: begin
end
default: begin
reg_addr <= A_addr;
ula_to_data <= 1;
ula_opcode <= ctrl_in;
ula_data1 <= A;
ula_data2 <= B_imm;
end
endcase
end
end
always @(*) begin
if (ula_to_data) begin
data <= ula_out;
addr <= addr_default;
end else begin
data <= data_default;
addr <= ula_out;
end
end
assign B_imm = B + imm;
endmodule | 0 |
3,653 | data/full_repos/permissive/106029354/verilog_source/pipeline3_testbench.v | 106,029,354 | pipeline3_testbench.v | v | 717 | 77 | [] | [] | [] | null | line:128: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline3_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline3_testbench.v:715: Cannot find include file: testbench.v\n`include "testbench.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 1,445 | module | module pipeline3_testbench();
`include "params_proc.v"
parameter N_TESTES = 22;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg [PC_WIDTH-1:0] pc_in;
reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
reg signed [DATA_WIDTH-1:0] A, B, imm;
wire [PC_WIDTH-1:0] pc_out;
wire signed [DATA_WIDTH-1:0] data;
wire [MEM_WIDTH-1:0] addr;
wire [REG_ADDR_WIDTH-1:0] reg_addr;
wire [CTRL_WIDTH-1:0] ctrl_out;
wire pc_chg;
wire we;
pipeline3 pipeline30(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.pc_in(pc_in),
.A_addr(A_addr),
.B_addr(B_addr),
.A(A),
.B(B),
.imm(imm),
.pc_chg(pc_chg),
.pc_out(pc_out),
.mem_we(we),
.data(data),
.addr(addr),
.reg_addr(reg_addr),
.ctrl_out(ctrl_out)
);
task init_input;
begin
ctrl_in = 0;
pc_in = 0;
A_addr = 0;
B_addr = 0;
A = 0;
B = 0;
imm = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CTRL = LW,
TESTE1_PC_IN = 45000,
TESTE1_A_ADDR = 5,
TESTE1_B_ADDR = 6,
TESTE1_A = 0,
TESTE1_B = 8,
TESTE1_IMM = 42;
parameter TESTE2_CTRL = SW,
TESTE2_PC_IN = 32000,
TESTE2_A_ADDR = 8,
TESTE2_B_ADDR = 7,
TESTE2_A = 5,
TESTE2_B = 65,
TESTE2_IMM = 45;
parameter TESTE3_CTRL = ADD,
TESTE3_PC_IN = 38000,
TESTE3_A_ADDR = 10,
TESTE3_B_ADDR = 9,
TESTE3_A = 50,
TESTE3_B = 85,
TESTE3_IMM = 0;
parameter TESTE4_CTRL = SUB,
TESTE4_PC_IN = 40000,
TESTE4_A_ADDR = 20,
TESTE4_B_ADDR = 15,
TESTE4_A = 150,
TESTE4_B = 25,
TESTE4_IMM = 0;
parameter TESTE5_CTRL = MUL,
TESTE5_PC_IN = 1700,
TESTE5_A_ADDR = 18,
TESTE5_B_ADDR = 4,
TESTE5_A = 5,
TESTE5_B = 10,
TESTE5_IMM = 0;
parameter TESTE6_CTRL = DIV,
TESTE6_PC_IN = 300,
TESTE6_A_ADDR = 14,
TESTE6_B_ADDR = 16,
TESTE6_A = 50,
TESTE6_B = -2,
TESTE6_IMM = 0;
parameter TESTE7_CTRL = AND,
TESTE7_PC_IN = 1000,
TESTE7_A_ADDR = 7,
TESTE7_B_ADDR = 3,
TESTE7_A = 5,
TESTE7_B = 7,
TESTE7_IMM = 0;
parameter TESTE8_CTRL = OR,
TESTE8_PC_IN = 7500,
TESTE8_A_ADDR = 11,
TESTE8_B_ADDR = 29,
TESTE8_A = 6,
TESTE8_B = 1,
TESTE8_IMM = 0;
parameter TESTE9_CTRL = CMP,
TESTE9_PC_IN = 9000,
TESTE9_A_ADDR = 18,
TESTE9_B_ADDR = 19,
TESTE9_A = 80,
TESTE9_B = -2,
TESTE9_IMM = 0;
parameter TESTE10_CTRL = NOT,
TESTE10_PC_IN = 15000,
TESTE10_A_ADDR = 9,
TESTE10_B_ADDR = 0,
TESTE10_A = 70,
TESTE10_B = 0,
TESTE10_IMM = 0;
parameter TESTE11_CTRL = JR,
TESTE11_PC_IN = 14250,
TESTE11_A_ADDR = 13,
TESTE11_B_ADDR = 0,
TESTE11_A = 150,
TESTE11_B = 0,
TESTE11_IMM = 0;
parameter TESTE12_CTRL = JPC,
TESTE12_PC_IN = 12000,
TESTE12_A_ADDR = 0,
TESTE12_B_ADDR = 0,
TESTE12_A = 0,
TESTE12_B = 0,
TESTE12_IMM = 350;
parameter TESTE13_CTRL = CMP,
TESTE13_PC_IN = 11529,
TESTE13_A_ADDR = 2,
TESTE13_B_ADDR = 3,
TESTE13_A = -5,
TESTE13_B = 80,
TESTE13_IMM = 0;
parameter TESTE14_CTRL = BRFL,
TESTE14_PC_IN = 11530,
TESTE14_A_ADDR = 7,
TESTE14_B_ADDR = 8,
TESTE14_A = 5000,
TESTE14_B = 1,
TESTE14_IMM = 1;
parameter TESTE15_CTRL = CMP,
TESTE15_PC_IN = 12767,
TESTE15_A_ADDR = 15,
TESTE15_B_ADDR = 9,
TESTE15_A = -1,
TESTE15_B = 1,
TESTE15_IMM = 0;
parameter TESTE16_CTRL = BRFL,
TESTE16_PC_IN = 12768,
TESTE16_A_ADDR = 17,
TESTE16_B_ADDR = 18,
TESTE16_A = 7000,
TESTE16_B = 0,
TESTE16_IMM = 1;
parameter TESTE17_CTRL = CALL,
TESTE17_PC_IN = 17541,
TESTE17_A_ADDR = 19,
TESTE17_B_ADDR = 0,
TESTE17_A = 48000,
TESTE17_B = 0,
TESTE17_IMM = 0;
parameter TESTE18_CTRL = RET,
TESTE18_PC_IN = 48000,
TESTE18_A_ADDR = 0,
TESTE18_B_ADDR = 0,
TESTE18_A = 0,
TESTE18_B = 0,
TESTE18_IMM = 0;
parameter TESTE19_CTRL = NOP,
TESTE19_PC_IN = 17542,
TESTE19_A_ADDR = 0,
TESTE19_B_ADDR = 0,
TESTE19_A = 0,
TESTE19_B = 0,
TESTE19_IMM = 0;
parameter TESTE20_CTRL = LW_IMM,
TESTE20_PC_IN = 45000,
TESTE20_A_ADDR = 8,
TESTE20_B_ADDR = 0,
TESTE20_A = 95,
TESTE20_B = 0,
TESTE20_IMM = 42;
parameter TESTE21_CTRL = ADD,
TESTE21_PC_IN = 17543,
TESTE21_A_ADDR = 0,
TESTE21_B_ADDR = 1,
TESTE21_A = 0,
TESTE21_B = 1,
TESTE21_IMM = 1;
begin
case(testes)
0: begin
ctrl_in <= TESTE1_CTRL;
pc_in <= TESTE1_PC_IN;
A_addr <= TESTE1_A_ADDR;
B_addr <= TESTE1_B_ADDR;
A <= TESTE1_A;
B <= TESTE1_B;
imm <= TESTE1_IMM;
if (pc_out == PC_INITIAL+1 && ctrl_out == NOP) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
ctrl_in <= TESTE2_CTRL;
pc_in <= TESTE2_PC_IN;
A_addr <= TESTE2_A_ADDR;
B_addr <= TESTE2_B_ADDR;
A <= TESTE2_A;
B <= TESTE2_B;
imm <= TESTE2_IMM;
if (pc_out == TESTE1_PC_IN && ctrl_out == TESTE1_CTRL &&
we == 0 && pc_chg == 0 && data == 0 &&
addr == TESTE1_B + TESTE1_IMM && reg_addr == TESTE1_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in <= TESTE3_CTRL;
pc_in <= TESTE3_PC_IN;
A_addr <= TESTE3_A_ADDR;
B_addr <= TESTE3_B_ADDR;
A <= TESTE3_A;
B <= TESTE3_B;
imm <= TESTE3_IMM;
if (pc_out == TESTE2_PC_IN && ctrl_out == TESTE2_CTRL &&
we == 1 && pc_chg == 0 && data == TESTE2_A &&
addr == TESTE2_B + TESTE2_IMM && reg_addr == TESTE2_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in <= TESTE4_CTRL;
pc_in <= TESTE4_PC_IN;
A_addr <= TESTE4_A_ADDR;
B_addr <= TESTE4_B_ADDR;
A <= TESTE4_A;
B <= TESTE4_B;
imm <= TESTE4_IMM;
if (pc_out == TESTE3_PC_IN && ctrl_out == TESTE3_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE3_A + (TESTE3_B + TESTE3_IMM) &&
addr == 0 && reg_addr == TESTE3_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in <= TESTE5_CTRL;
pc_in <= TESTE5_PC_IN;
A_addr <= TESTE5_A_ADDR;
B_addr <= TESTE5_B_ADDR;
A <= TESTE5_A;
B <= TESTE5_B;
imm <= TESTE5_IMM;
if (
pc_out == TESTE4_PC_IN &&
ctrl_out == TESTE4_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE4_A - (TESTE4_B + TESTE4_IMM) &&
addr == 0 &&
reg_addr == TESTE4_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
ctrl_in <= TESTE6_CTRL;
pc_in <= TESTE6_PC_IN;
A_addr <= TESTE6_A_ADDR;
B_addr <= TESTE6_B_ADDR;
A <= TESTE6_A;
B <= TESTE6_B;
imm <= TESTE6_IMM;
if (
pc_out == TESTE5_PC_IN &&
ctrl_out == TESTE5_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE5_A * (TESTE5_B + TESTE5_IMM) &&
addr == 0 &&
reg_addr == TESTE5_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
ctrl_in <= TESTE7_CTRL;
pc_in <= TESTE7_PC_IN;
A_addr <= TESTE7_A_ADDR;
B_addr <= TESTE7_B_ADDR;
A <= TESTE7_A;
B <= TESTE7_B;
imm <= TESTE7_IMM;
if (
pc_out == TESTE6_PC_IN &&
ctrl_out == TESTE6_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE6_A / (TESTE6_B + TESTE6_IMM) &&
addr == 0 &&
reg_addr == TESTE6_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
ctrl_in <= TESTE8_CTRL;
pc_in <= TESTE8_PC_IN;
A_addr <= TESTE8_A_ADDR;
B_addr <= TESTE8_B_ADDR;
A <= TESTE8_A;
B <= TESTE8_B;
imm <= TESTE8_IMM;
if (
pc_out == TESTE7_PC_IN &&
ctrl_out == TESTE7_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE7_A & (TESTE7_B + TESTE7_IMM) &&
addr == 0 &&
reg_addr == TESTE7_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
ctrl_in <= TESTE9_CTRL;
pc_in <= TESTE9_PC_IN;
A_addr <= TESTE9_A_ADDR;
B_addr <= TESTE9_B_ADDR;
A <= TESTE9_A;
B <= TESTE9_B;
imm <= TESTE9_IMM;
if (
pc_out == TESTE8_PC_IN &&
ctrl_out == TESTE8_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE8_A | (TESTE8_B + TESTE8_IMM) &&
addr == 0 &&
reg_addr == TESTE8_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
ctrl_in <= TESTE10_CTRL;
pc_in <= TESTE10_PC_IN;
A_addr <= TESTE10_A_ADDR;
B_addr <= TESTE10_B_ADDR;
A <= TESTE10_A;
B <= TESTE10_B;
imm <= TESTE10_IMM;
if (
pc_out == TESTE9_PC_IN &&
ctrl_out == TESTE9_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE9_A - (TESTE9_B + TESTE9_IMM) &&
addr == 0 &&
reg_addr == TESTE9_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
ctrl_in <= TESTE11_CTRL;
pc_in <= TESTE11_PC_IN;
A_addr <= TESTE11_A_ADDR;
B_addr <= TESTE11_B_ADDR;
A <= TESTE11_A;
B <= TESTE11_B;
imm <= TESTE11_IMM;
if (
pc_out == TESTE10_PC_IN &&
ctrl_out == TESTE10_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE10_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
ctrl_in <= TESTE12_CTRL;
pc_in <= TESTE12_PC_IN;
A_addr <= TESTE12_A_ADDR;
B_addr <= TESTE12_B_ADDR;
A <= TESTE12_A;
B <= TESTE12_B;
imm <= TESTE12_IMM;
if (
pc_out == TESTE11_A &&
ctrl_out == TESTE11_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE11_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
ctrl_in <= TESTE13_CTRL;
pc_in <= TESTE13_PC_IN;
A_addr <= TESTE13_A_ADDR;
B_addr <= TESTE13_B_ADDR;
A <= TESTE13_A;
B <= TESTE13_B;
imm <= TESTE13_IMM;
if (
pc_out == TESTE12_PC_IN + TESTE12_B + TESTE12_IMM &&
ctrl_out == TESTE12_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE12_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
ctrl_in <= TESTE14_CTRL;
pc_in <= TESTE14_PC_IN;
A_addr <= TESTE14_A_ADDR;
B_addr <= TESTE14_B_ADDR;
A <= TESTE14_A;
B <= TESTE14_B;
imm <= TESTE14_IMM;
if (
pc_out == TESTE13_PC_IN &&
ctrl_out == TESTE13_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE13_A - (TESTE13_B + TESTE13_IMM) &&
addr == 0 &&
reg_addr == TESTE13_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
ctrl_in <= TESTE15_CTRL;
pc_in <= TESTE15_PC_IN;
A_addr <= TESTE15_A_ADDR;
B_addr <= TESTE15_B_ADDR;
A <= TESTE15_A;
B <= TESTE15_B;
imm <= TESTE15_IMM;
if (
pc_out == TESTE14_A &&
ctrl_out == TESTE14_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE14_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
ctrl_in <= TESTE16_CTRL;
pc_in <= TESTE16_PC_IN;
A_addr <= TESTE16_A_ADDR;
B_addr <= TESTE16_B_ADDR;
A <= TESTE16_A;
B <= TESTE16_B;
imm <= TESTE16_IMM;
if (
pc_out == TESTE15_PC_IN &&
ctrl_out == TESTE15_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE15_A - (TESTE15_B + TESTE15_IMM) &&
addr == 0 &&
reg_addr == TESTE15_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
16: begin
ctrl_in <= TESTE17_CTRL;
pc_in <= TESTE17_PC_IN;
A_addr <= TESTE17_A_ADDR;
B_addr <= TESTE17_B_ADDR;
A <= TESTE17_A;
B <= TESTE17_B;
imm <= TESTE17_IMM;
if (
pc_out == TESTE16_PC_IN &&
ctrl_out == TESTE16_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE16_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
17: begin
ctrl_in <= TESTE18_CTRL;
pc_in <= TESTE18_PC_IN;
A_addr <= TESTE18_A_ADDR;
B_addr <= TESTE18_B_ADDR;
A <= TESTE18_A;
B <= TESTE18_B;
imm <= TESTE18_IMM;
if (
pc_out == TESTE17_A &&
ctrl_out == TESTE17_CTRL &&
we == 0 && pc_chg == 1 &&
data == TESTE17_PC_IN &&
addr == 0 &&
reg_addr == REG_FUNC_RET ) begin
status <= 0;
end else begin
status <= 1;
end
end
18: begin
ctrl_in <= TESTE19_CTRL;
pc_in <= TESTE19_PC_IN;
A_addr <= TESTE19_A_ADDR;
B_addr <= TESTE19_B_ADDR;
A <= TESTE19_A;
B <= TESTE19_B;
imm <= TESTE19_IMM;
if (
pc_out == TESTE18_A &&
ctrl_out == TESTE18_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE18_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
19: begin
ctrl_in <= TESTE20_CTRL;
pc_in <= TESTE20_PC_IN;
A_addr <= TESTE20_A_ADDR;
B_addr <= TESTE20_B_ADDR;
A <= TESTE20_A;
B <= TESTE20_B;
imm <= TESTE20_IMM;
if (
pc_out == TESTE19_PC_IN &&
ctrl_out == TESTE19_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE19_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
20: begin
ctrl_in <= TESTE21_CTRL;
pc_in <= TESTE21_PC_IN;
A_addr <= TESTE21_A_ADDR;
B_addr <= TESTE21_B_ADDR;
A <= TESTE21_A;
B <= TESTE21_B;
imm <= TESTE21_IMM;
if (
pc_out == TESTE20_PC_IN &&
ctrl_out == TESTE20_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE20_IMM &&
addr == 0 &&
reg_addr == TESTE20_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_IN: %6d ", pc_in);
$display("\t A - ADDR: %3d - DATA: %6d ", A_addr, A);
$display("\t B - ADDR: %3d - DATA: %6d ", B_addr, B);
$display("\t IMM: %6d ", imm);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t PC_CHG: %b", pc_chg);
$display("\t PC_OUT: %6d ", pc_out);
$display("\t DATA: %6d ", data);
$display("\t ADDR: %6d ", addr);
$display("\t REG_ADDR: %3d ", reg_addr);
$write( "\t CTRL_OUT: %b (", ctrl_out);
case(ctrl_out)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
`include "testbench.v"
endmodule | module pipeline3_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 22;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg [PC_WIDTH-1:0] pc_in;
reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
reg signed [DATA_WIDTH-1:0] A, B, imm;
wire [PC_WIDTH-1:0] pc_out;
wire signed [DATA_WIDTH-1:0] data;
wire [MEM_WIDTH-1:0] addr;
wire [REG_ADDR_WIDTH-1:0] reg_addr;
wire [CTRL_WIDTH-1:0] ctrl_out;
wire pc_chg;
wire we;
pipeline3 pipeline30(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.pc_in(pc_in),
.A_addr(A_addr),
.B_addr(B_addr),
.A(A),
.B(B),
.imm(imm),
.pc_chg(pc_chg),
.pc_out(pc_out),
.mem_we(we),
.data(data),
.addr(addr),
.reg_addr(reg_addr),
.ctrl_out(ctrl_out)
);
task init_input;
begin
ctrl_in = 0;
pc_in = 0;
A_addr = 0;
B_addr = 0;
A = 0;
B = 0;
imm = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CTRL = LW,
TESTE1_PC_IN = 45000,
TESTE1_A_ADDR = 5,
TESTE1_B_ADDR = 6,
TESTE1_A = 0,
TESTE1_B = 8,
TESTE1_IMM = 42;
parameter TESTE2_CTRL = SW,
TESTE2_PC_IN = 32000,
TESTE2_A_ADDR = 8,
TESTE2_B_ADDR = 7,
TESTE2_A = 5,
TESTE2_B = 65,
TESTE2_IMM = 45;
parameter TESTE3_CTRL = ADD,
TESTE3_PC_IN = 38000,
TESTE3_A_ADDR = 10,
TESTE3_B_ADDR = 9,
TESTE3_A = 50,
TESTE3_B = 85,
TESTE3_IMM = 0;
parameter TESTE4_CTRL = SUB,
TESTE4_PC_IN = 40000,
TESTE4_A_ADDR = 20,
TESTE4_B_ADDR = 15,
TESTE4_A = 150,
TESTE4_B = 25,
TESTE4_IMM = 0;
parameter TESTE5_CTRL = MUL,
TESTE5_PC_IN = 1700,
TESTE5_A_ADDR = 18,
TESTE5_B_ADDR = 4,
TESTE5_A = 5,
TESTE5_B = 10,
TESTE5_IMM = 0;
parameter TESTE6_CTRL = DIV,
TESTE6_PC_IN = 300,
TESTE6_A_ADDR = 14,
TESTE6_B_ADDR = 16,
TESTE6_A = 50,
TESTE6_B = -2,
TESTE6_IMM = 0;
parameter TESTE7_CTRL = AND,
TESTE7_PC_IN = 1000,
TESTE7_A_ADDR = 7,
TESTE7_B_ADDR = 3,
TESTE7_A = 5,
TESTE7_B = 7,
TESTE7_IMM = 0;
parameter TESTE8_CTRL = OR,
TESTE8_PC_IN = 7500,
TESTE8_A_ADDR = 11,
TESTE8_B_ADDR = 29,
TESTE8_A = 6,
TESTE8_B = 1,
TESTE8_IMM = 0;
parameter TESTE9_CTRL = CMP,
TESTE9_PC_IN = 9000,
TESTE9_A_ADDR = 18,
TESTE9_B_ADDR = 19,
TESTE9_A = 80,
TESTE9_B = -2,
TESTE9_IMM = 0;
parameter TESTE10_CTRL = NOT,
TESTE10_PC_IN = 15000,
TESTE10_A_ADDR = 9,
TESTE10_B_ADDR = 0,
TESTE10_A = 70,
TESTE10_B = 0,
TESTE10_IMM = 0;
parameter TESTE11_CTRL = JR,
TESTE11_PC_IN = 14250,
TESTE11_A_ADDR = 13,
TESTE11_B_ADDR = 0,
TESTE11_A = 150,
TESTE11_B = 0,
TESTE11_IMM = 0;
parameter TESTE12_CTRL = JPC,
TESTE12_PC_IN = 12000,
TESTE12_A_ADDR = 0,
TESTE12_B_ADDR = 0,
TESTE12_A = 0,
TESTE12_B = 0,
TESTE12_IMM = 350;
parameter TESTE13_CTRL = CMP,
TESTE13_PC_IN = 11529,
TESTE13_A_ADDR = 2,
TESTE13_B_ADDR = 3,
TESTE13_A = -5,
TESTE13_B = 80,
TESTE13_IMM = 0;
parameter TESTE14_CTRL = BRFL,
TESTE14_PC_IN = 11530,
TESTE14_A_ADDR = 7,
TESTE14_B_ADDR = 8,
TESTE14_A = 5000,
TESTE14_B = 1,
TESTE14_IMM = 1;
parameter TESTE15_CTRL = CMP,
TESTE15_PC_IN = 12767,
TESTE15_A_ADDR = 15,
TESTE15_B_ADDR = 9,
TESTE15_A = -1,
TESTE15_B = 1,
TESTE15_IMM = 0;
parameter TESTE16_CTRL = BRFL,
TESTE16_PC_IN = 12768,
TESTE16_A_ADDR = 17,
TESTE16_B_ADDR = 18,
TESTE16_A = 7000,
TESTE16_B = 0,
TESTE16_IMM = 1;
parameter TESTE17_CTRL = CALL,
TESTE17_PC_IN = 17541,
TESTE17_A_ADDR = 19,
TESTE17_B_ADDR = 0,
TESTE17_A = 48000,
TESTE17_B = 0,
TESTE17_IMM = 0;
parameter TESTE18_CTRL = RET,
TESTE18_PC_IN = 48000,
TESTE18_A_ADDR = 0,
TESTE18_B_ADDR = 0,
TESTE18_A = 0,
TESTE18_B = 0,
TESTE18_IMM = 0;
parameter TESTE19_CTRL = NOP,
TESTE19_PC_IN = 17542,
TESTE19_A_ADDR = 0,
TESTE19_B_ADDR = 0,
TESTE19_A = 0,
TESTE19_B = 0,
TESTE19_IMM = 0;
parameter TESTE20_CTRL = LW_IMM,
TESTE20_PC_IN = 45000,
TESTE20_A_ADDR = 8,
TESTE20_B_ADDR = 0,
TESTE20_A = 95,
TESTE20_B = 0,
TESTE20_IMM = 42;
parameter TESTE21_CTRL = ADD,
TESTE21_PC_IN = 17543,
TESTE21_A_ADDR = 0,
TESTE21_B_ADDR = 1,
TESTE21_A = 0,
TESTE21_B = 1,
TESTE21_IMM = 1;
begin
case(testes)
0: begin
ctrl_in <= TESTE1_CTRL;
pc_in <= TESTE1_PC_IN;
A_addr <= TESTE1_A_ADDR;
B_addr <= TESTE1_B_ADDR;
A <= TESTE1_A;
B <= TESTE1_B;
imm <= TESTE1_IMM;
if (pc_out == PC_INITIAL+1 && ctrl_out == NOP) begin
status <= 0;
end else begin
status <= 1;
end
end
1: begin
ctrl_in <= TESTE2_CTRL;
pc_in <= TESTE2_PC_IN;
A_addr <= TESTE2_A_ADDR;
B_addr <= TESTE2_B_ADDR;
A <= TESTE2_A;
B <= TESTE2_B;
imm <= TESTE2_IMM;
if (pc_out == TESTE1_PC_IN && ctrl_out == TESTE1_CTRL &&
we == 0 && pc_chg == 0 && data == 0 &&
addr == TESTE1_B + TESTE1_IMM && reg_addr == TESTE1_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in <= TESTE3_CTRL;
pc_in <= TESTE3_PC_IN;
A_addr <= TESTE3_A_ADDR;
B_addr <= TESTE3_B_ADDR;
A <= TESTE3_A;
B <= TESTE3_B;
imm <= TESTE3_IMM;
if (pc_out == TESTE2_PC_IN && ctrl_out == TESTE2_CTRL &&
we == 1 && pc_chg == 0 && data == TESTE2_A &&
addr == TESTE2_B + TESTE2_IMM && reg_addr == TESTE2_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in <= TESTE4_CTRL;
pc_in <= TESTE4_PC_IN;
A_addr <= TESTE4_A_ADDR;
B_addr <= TESTE4_B_ADDR;
A <= TESTE4_A;
B <= TESTE4_B;
imm <= TESTE4_IMM;
if (pc_out == TESTE3_PC_IN && ctrl_out == TESTE3_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE3_A + (TESTE3_B + TESTE3_IMM) &&
addr == 0 && reg_addr == TESTE3_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in <= TESTE5_CTRL;
pc_in <= TESTE5_PC_IN;
A_addr <= TESTE5_A_ADDR;
B_addr <= TESTE5_B_ADDR;
A <= TESTE5_A;
B <= TESTE5_B;
imm <= TESTE5_IMM;
if (
pc_out == TESTE4_PC_IN &&
ctrl_out == TESTE4_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE4_A - (TESTE4_B + TESTE4_IMM) &&
addr == 0 &&
reg_addr == TESTE4_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
ctrl_in <= TESTE6_CTRL;
pc_in <= TESTE6_PC_IN;
A_addr <= TESTE6_A_ADDR;
B_addr <= TESTE6_B_ADDR;
A <= TESTE6_A;
B <= TESTE6_B;
imm <= TESTE6_IMM;
if (
pc_out == TESTE5_PC_IN &&
ctrl_out == TESTE5_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE5_A * (TESTE5_B + TESTE5_IMM) &&
addr == 0 &&
reg_addr == TESTE5_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
ctrl_in <= TESTE7_CTRL;
pc_in <= TESTE7_PC_IN;
A_addr <= TESTE7_A_ADDR;
B_addr <= TESTE7_B_ADDR;
A <= TESTE7_A;
B <= TESTE7_B;
imm <= TESTE7_IMM;
if (
pc_out == TESTE6_PC_IN &&
ctrl_out == TESTE6_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE6_A / (TESTE6_B + TESTE6_IMM) &&
addr == 0 &&
reg_addr == TESTE6_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
ctrl_in <= TESTE8_CTRL;
pc_in <= TESTE8_PC_IN;
A_addr <= TESTE8_A_ADDR;
B_addr <= TESTE8_B_ADDR;
A <= TESTE8_A;
B <= TESTE8_B;
imm <= TESTE8_IMM;
if (
pc_out == TESTE7_PC_IN &&
ctrl_out == TESTE7_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE7_A & (TESTE7_B + TESTE7_IMM) &&
addr == 0 &&
reg_addr == TESTE7_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
ctrl_in <= TESTE9_CTRL;
pc_in <= TESTE9_PC_IN;
A_addr <= TESTE9_A_ADDR;
B_addr <= TESTE9_B_ADDR;
A <= TESTE9_A;
B <= TESTE9_B;
imm <= TESTE9_IMM;
if (
pc_out == TESTE8_PC_IN &&
ctrl_out == TESTE8_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE8_A | (TESTE8_B + TESTE8_IMM) &&
addr == 0 &&
reg_addr == TESTE8_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
ctrl_in <= TESTE10_CTRL;
pc_in <= TESTE10_PC_IN;
A_addr <= TESTE10_A_ADDR;
B_addr <= TESTE10_B_ADDR;
A <= TESTE10_A;
B <= TESTE10_B;
imm <= TESTE10_IMM;
if (
pc_out == TESTE9_PC_IN &&
ctrl_out == TESTE9_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE9_A - (TESTE9_B + TESTE9_IMM) &&
addr == 0 &&
reg_addr == TESTE9_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
ctrl_in <= TESTE11_CTRL;
pc_in <= TESTE11_PC_IN;
A_addr <= TESTE11_A_ADDR;
B_addr <= TESTE11_B_ADDR;
A <= TESTE11_A;
B <= TESTE11_B;
imm <= TESTE11_IMM;
if (
pc_out == TESTE10_PC_IN &&
ctrl_out == TESTE10_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE10_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
ctrl_in <= TESTE12_CTRL;
pc_in <= TESTE12_PC_IN;
A_addr <= TESTE12_A_ADDR;
B_addr <= TESTE12_B_ADDR;
A <= TESTE12_A;
B <= TESTE12_B;
imm <= TESTE12_IMM;
if (
pc_out == TESTE11_A &&
ctrl_out == TESTE11_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE11_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
ctrl_in <= TESTE13_CTRL;
pc_in <= TESTE13_PC_IN;
A_addr <= TESTE13_A_ADDR;
B_addr <= TESTE13_B_ADDR;
A <= TESTE13_A;
B <= TESTE13_B;
imm <= TESTE13_IMM;
if (
pc_out == TESTE12_PC_IN + TESTE12_B + TESTE12_IMM &&
ctrl_out == TESTE12_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE12_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
ctrl_in <= TESTE14_CTRL;
pc_in <= TESTE14_PC_IN;
A_addr <= TESTE14_A_ADDR;
B_addr <= TESTE14_B_ADDR;
A <= TESTE14_A;
B <= TESTE14_B;
imm <= TESTE14_IMM;
if (
pc_out == TESTE13_PC_IN &&
ctrl_out == TESTE13_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE13_A - (TESTE13_B + TESTE13_IMM) &&
addr == 0 &&
reg_addr == TESTE13_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
ctrl_in <= TESTE15_CTRL;
pc_in <= TESTE15_PC_IN;
A_addr <= TESTE15_A_ADDR;
B_addr <= TESTE15_B_ADDR;
A <= TESTE15_A;
B <= TESTE15_B;
imm <= TESTE15_IMM;
if (
pc_out == TESTE14_A &&
ctrl_out == TESTE14_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE14_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
ctrl_in <= TESTE16_CTRL;
pc_in <= TESTE16_PC_IN;
A_addr <= TESTE16_A_ADDR;
B_addr <= TESTE16_B_ADDR;
A <= TESTE16_A;
B <= TESTE16_B;
imm <= TESTE16_IMM;
if (
pc_out == TESTE15_PC_IN &&
ctrl_out == TESTE15_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE15_A - (TESTE15_B + TESTE15_IMM) &&
addr == 0 &&
reg_addr == TESTE15_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
16: begin
ctrl_in <= TESTE17_CTRL;
pc_in <= TESTE17_PC_IN;
A_addr <= TESTE17_A_ADDR;
B_addr <= TESTE17_B_ADDR;
A <= TESTE17_A;
B <= TESTE17_B;
imm <= TESTE17_IMM;
if (
pc_out == TESTE16_PC_IN &&
ctrl_out == TESTE16_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE16_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
17: begin
ctrl_in <= TESTE18_CTRL;
pc_in <= TESTE18_PC_IN;
A_addr <= TESTE18_A_ADDR;
B_addr <= TESTE18_B_ADDR;
A <= TESTE18_A;
B <= TESTE18_B;
imm <= TESTE18_IMM;
if (
pc_out == TESTE17_A &&
ctrl_out == TESTE17_CTRL &&
we == 0 && pc_chg == 1 &&
data == TESTE17_PC_IN &&
addr == 0 &&
reg_addr == REG_FUNC_RET ) begin
status <= 0;
end else begin
status <= 1;
end
end
18: begin
ctrl_in <= TESTE19_CTRL;
pc_in <= TESTE19_PC_IN;
A_addr <= TESTE19_A_ADDR;
B_addr <= TESTE19_B_ADDR;
A <= TESTE19_A;
B <= TESTE19_B;
imm <= TESTE19_IMM;
if (
pc_out == TESTE18_A &&
ctrl_out == TESTE18_CTRL &&
we == 0 && pc_chg == 1 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE18_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
19: begin
ctrl_in <= TESTE20_CTRL;
pc_in <= TESTE20_PC_IN;
A_addr <= TESTE20_A_ADDR;
B_addr <= TESTE20_B_ADDR;
A <= TESTE20_A;
B <= TESTE20_B;
imm <= TESTE20_IMM;
if (
pc_out == TESTE19_PC_IN &&
ctrl_out == TESTE19_CTRL &&
we == 0 && pc_chg == 0 &&
data == 0 &&
addr == 0 &&
reg_addr == TESTE19_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
20: begin
ctrl_in <= TESTE21_CTRL;
pc_in <= TESTE21_PC_IN;
A_addr <= TESTE21_A_ADDR;
B_addr <= TESTE21_B_ADDR;
A <= TESTE21_A;
B <= TESTE21_B;
imm <= TESTE21_IMM;
if (
pc_out == TESTE20_PC_IN &&
ctrl_out == TESTE20_CTRL &&
we == 0 && pc_chg == 0 &&
data == TESTE20_IMM &&
addr == 0 &&
reg_addr == TESTE20_A_ADDR ) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t PC_IN: %6d ", pc_in);
$display("\t A - ADDR: %3d - DATA: %6d ", A_addr, A);
$display("\t B - ADDR: %3d - DATA: %6d ", B_addr, B);
$display("\t IMM: %6d ", imm);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t PC_CHG: %b", pc_chg);
$display("\t PC_OUT: %6d ", pc_out);
$display("\t DATA: %6d ", data);
$display("\t ADDR: %6d ", addr);
$display("\t REG_ADDR: %3d ", reg_addr);
$write( "\t CTRL_OUT: %b (", ctrl_out);
case(ctrl_out)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
`include "testbench.v"
endmodule | 0 |
3,654 | data/full_repos/permissive/106029354/verilog_source/pipeline4.v | 106,029,354 | pipeline4.v | v | 47 | 92 | [] | [] | [] | [(1, 115)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline4.v:15: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,446 | module | module pipeline4(
clk_in,
RST,
ctrl_in,
we,
data,
addr,
reg_addr_in,
reg_data_out,
reg_addr_out,
ctrl_out
);
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input we;
input signed [DATA_WIDTH-1:0] data;
input [MEM_WIDTH-1:0] addr;
input [REG_ADDR_WIDTH-1:0] reg_addr_in;
output wire signed [DATA_WIDTH-1:0] reg_data_out;
output reg [REG_ADDR_WIDTH-1:0] reg_addr_out;
output reg [CTRL_WIDTH-1:0] ctrl_out;
mem_data rom0(.clk(clk_in), .we(we), .addr(addr), .data_in(data), .data_out(reg_data_out));
always @(posedge clk_in) begin
reg_addr_out <= reg_addr_in;
end
always @(posedge clk_in) begin
if (!RST) begin
ctrl_out <= NOP;
end else begin
ctrl_out <= ctrl_in;
end
end
endmodule | module pipeline4(
clk_in,
RST,
ctrl_in,
we,
data,
addr,
reg_addr_in,
reg_data_out,
reg_addr_out,
ctrl_out
); |
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input we;
input signed [DATA_WIDTH-1:0] data;
input [MEM_WIDTH-1:0] addr;
input [REG_ADDR_WIDTH-1:0] reg_addr_in;
output wire signed [DATA_WIDTH-1:0] reg_data_out;
output reg [REG_ADDR_WIDTH-1:0] reg_addr_out;
output reg [CTRL_WIDTH-1:0] ctrl_out;
mem_data rom0(.clk(clk_in), .we(we), .addr(addr), .data_in(data), .data_out(reg_data_out));
always @(posedge clk_in) begin
reg_addr_out <= reg_addr_in;
end
always @(posedge clk_in) begin
if (!RST) begin
ctrl_out <= NOP;
end else begin
ctrl_out <= ctrl_in;
end
end
endmodule | 0 |
3,655 | data/full_repos/permissive/106029354/verilog_source/pipeline4_testbench.v | 106,029,354 | pipeline4_testbench.v | v | 206 | 109 | [] | [] | [] | null | line:117: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline4_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline4_testbench.v:203: Cannot find include file: testbench.v\n`include "testbench.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 1,447 | module | module pipeline4_testbench();
`include "params_proc.v"
parameter N_TESTES = 5;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg we;
reg signed [DATA_WIDTH-1:0] data;
reg [MEM_WIDTH-1:0] addr;
reg [REG_ADDR_WIDTH-1:0] reg_addr_in;
wire signed [DATA_WIDTH-1:0] reg_data_out;
wire [REG_ADDR_WIDTH-1:0] reg_addr_out;
wire [CTRL_WIDTH-1:0] ctrl_out;
pipeline4 pipeline40(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.we(we),
.data(data),
.addr(addr),
.reg_addr_in(reg_addr_in),
.reg_data_out(reg_data_out),
.reg_addr_out(reg_addr_out),
.ctrl_out(ctrl_out)
);
task init_input;
begin
ctrl_in = NOP;
we = 0;
data = 0;
addr = 0;
reg_addr_in = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_DATA = 5,
TESTE1_CTRL = SW,
TESTE1_ADDR = 0,
TESTE1_REG_ADDR = 15;
parameter TESTE2_DATA = 15,
TESTE2_CTRL = LW,
TESTE2_ADDR = TESTE1_ADDR,
TESTE2_REG_ADDR = 20;
parameter TESTE3_DATA = 25,
TESTE3_CTRL = ADD,
TESTE3_ADDR = TESTE1_ADDR+1,
TESTE3_REG_ADDR = 22;
parameter TESTE4_DATA = 37,
TESTE4_CTRL = SUB,
TESTE4_ADDR = TESTE3_ADDR,
TESTE4_REG_ADDR = 30;
begin
case(testes)
0: begin
ctrl_in <= TESTE1_CTRL;
we <= 1;
data <= TESTE1_DATA;
addr <= TESTE1_ADDR;
reg_addr_in <= TESTE1_REG_ADDR;
status <= 0;
end
1: begin
ctrl_in <= TESTE2_CTRL;
we <= 0;
data <= TESTE2_DATA;
addr <= TESTE2_ADDR;
reg_addr_in <= TESTE2_REG_ADDR;
if (reg_data_out == TESTE1_DATA && ctrl_out == TESTE1_CTRL && reg_addr_out == TESTE1_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in <= TESTE3_CTRL;
we <= 1;
data <= TESTE3_DATA;
addr <= TESTE3_ADDR;
reg_addr_in <= TESTE3_REG_ADDR;
if (reg_data_out == TESTE1_DATA && ctrl_out == TESTE2_CTRL && reg_addr_out == TESTE2_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in <= TESTE4_CTRL;
we <= 0;
data <= TESTE4_DATA;
addr <= TESTE4_ADDR;
reg_addr_in <= TESTE4_REG_ADDR;
if (reg_data_out == TESTE3_DATA && ctrl_out == TESTE3_CTRL && reg_addr_out == TESTE3_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in <= TESTE1_CTRL;
we <= 0;
data <= TESTE1_DATA;
addr <= TESTE4_ADDR;
reg_addr_in <= TESTE1_REG_ADDR;
if (reg_data_out == TESTE3_DATA && ctrl_out == TESTE4_CTRL && reg_addr_out == TESTE4_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t WE: %b ", we);
$display("\t ADDR: %6d - DATA: %6d ", addr, data);
$display("\t REG_ADDR_IN: %3d ", reg_addr_in);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t REG_DATA_OUT: %6d ", reg_data_out);
$display("\t REG_ADDR_OUT: %3d ", reg_addr_out);
$write( "\t CTRL_OUT: %b (", ctrl_out);
case(ctrl_out)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
`include "testbench.v"
endmodule | module pipeline4_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 5;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg we;
reg signed [DATA_WIDTH-1:0] data;
reg [MEM_WIDTH-1:0] addr;
reg [REG_ADDR_WIDTH-1:0] reg_addr_in;
wire signed [DATA_WIDTH-1:0] reg_data_out;
wire [REG_ADDR_WIDTH-1:0] reg_addr_out;
wire [CTRL_WIDTH-1:0] ctrl_out;
pipeline4 pipeline40(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.we(we),
.data(data),
.addr(addr),
.reg_addr_in(reg_addr_in),
.reg_data_out(reg_data_out),
.reg_addr_out(reg_addr_out),
.ctrl_out(ctrl_out)
);
task init_input;
begin
ctrl_in = NOP;
we = 0;
data = 0;
addr = 0;
reg_addr_in = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_DATA = 5,
TESTE1_CTRL = SW,
TESTE1_ADDR = 0,
TESTE1_REG_ADDR = 15;
parameter TESTE2_DATA = 15,
TESTE2_CTRL = LW,
TESTE2_ADDR = TESTE1_ADDR,
TESTE2_REG_ADDR = 20;
parameter TESTE3_DATA = 25,
TESTE3_CTRL = ADD,
TESTE3_ADDR = TESTE1_ADDR+1,
TESTE3_REG_ADDR = 22;
parameter TESTE4_DATA = 37,
TESTE4_CTRL = SUB,
TESTE4_ADDR = TESTE3_ADDR,
TESTE4_REG_ADDR = 30;
begin
case(testes)
0: begin
ctrl_in <= TESTE1_CTRL;
we <= 1;
data <= TESTE1_DATA;
addr <= TESTE1_ADDR;
reg_addr_in <= TESTE1_REG_ADDR;
status <= 0;
end
1: begin
ctrl_in <= TESTE2_CTRL;
we <= 0;
data <= TESTE2_DATA;
addr <= TESTE2_ADDR;
reg_addr_in <= TESTE2_REG_ADDR;
if (reg_data_out == TESTE1_DATA && ctrl_out == TESTE1_CTRL && reg_addr_out == TESTE1_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in <= TESTE3_CTRL;
we <= 1;
data <= TESTE3_DATA;
addr <= TESTE3_ADDR;
reg_addr_in <= TESTE3_REG_ADDR;
if (reg_data_out == TESTE1_DATA && ctrl_out == TESTE2_CTRL && reg_addr_out == TESTE2_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in <= TESTE4_CTRL;
we <= 0;
data <= TESTE4_DATA;
addr <= TESTE4_ADDR;
reg_addr_in <= TESTE4_REG_ADDR;
if (reg_data_out == TESTE3_DATA && ctrl_out == TESTE3_CTRL && reg_addr_out == TESTE3_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in <= TESTE1_CTRL;
we <= 0;
data <= TESTE1_DATA;
addr <= TESTE4_ADDR;
reg_addr_in <= TESTE1_REG_ADDR;
if (reg_data_out == TESTE3_DATA && ctrl_out == TESTE4_CTRL && reg_addr_out == TESTE4_REG_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t WE: %b ", we);
$display("\t ADDR: %6d - DATA: %6d ", addr, data);
$display("\t REG_ADDR_IN: %3d ", reg_addr_in);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t REG_DATA_OUT: %6d ", reg_data_out);
$display("\t REG_ADDR_OUT: %3d ", reg_addr_out);
$write( "\t CTRL_OUT: %b (", ctrl_out);
case(ctrl_out)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
`include "testbench.v"
endmodule | 0 |
3,656 | data/full_repos/permissive/106029354/verilog_source/pipeline5.v | 106,029,354 | pipeline5.v | v | 60 | 106 | [] | [] | [] | [(1, 128)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline5.v:13: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,448 | module | module pipeline5(
clk_in,
RST,
ctrl_in,
data,
addr,
data_out,
addr_out,
en_out
);
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input signed [DATA_WIDTH-1:0] data;
input [REG_ADDR_WIDTH-1:0] addr;
output reg signed [DATA_WIDTH-1:0] data_out;
output reg [REG_ADDR_WIDTH-1:0] addr_out;
output reg en_out;
always @(posedge clk_in) begin
data_out <= data;
addr_out <= addr;
end
always @(posedge clk_in) begin
if (!RST) begin
en_out <= 0;
end else begin
case (ctrl_in)
LW: en_out <= 1;
LW_IMM: en_out <= 1;
ADD: en_out <= 1;
SUB: en_out <= 1;
MUL: en_out <= 1;
DIV: en_out <= 1;
AND: en_out <= 1;
OR : en_out <= 1;
NOT: en_out <= 1;
default: en_out <= 0;
endcase
end
end
endmodule | module pipeline5(
clk_in,
RST,
ctrl_in,
data,
addr,
data_out,
addr_out,
en_out
); |
`include "params_proc.v"
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input signed [DATA_WIDTH-1:0] data;
input [REG_ADDR_WIDTH-1:0] addr;
output reg signed [DATA_WIDTH-1:0] data_out;
output reg [REG_ADDR_WIDTH-1:0] addr_out;
output reg en_out;
always @(posedge clk_in) begin
data_out <= data;
addr_out <= addr;
end
always @(posedge clk_in) begin
if (!RST) begin
en_out <= 0;
end else begin
case (ctrl_in)
LW: en_out <= 1;
LW_IMM: en_out <= 1;
ADD: en_out <= 1;
SUB: en_out <= 1;
MUL: en_out <= 1;
DIV: en_out <= 1;
AND: en_out <= 1;
OR : en_out <= 1;
NOT: en_out <= 1;
default: en_out <= 0;
endcase
end
end
endmodule | 0 |
3,657 | data/full_repos/permissive/106029354/verilog_source/pipeline5_testbench.v | 106,029,354 | pipeline5_testbench.v | v | 364 | 96 | [] | [] | [] | null | line:111: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline5_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline5_testbench.v:361: Cannot find include file: testbench.v\n`include "testbench.v" \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 1,449 | module | module pipeline5_testbench();
`include "params_proc.v"
parameter N_TESTES = 18;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg signed [DATA_WIDTH-1:0] data;
reg [REG_ADDR_WIDTH-1:0] addr;
wire signed [DATA_WIDTH-1:0] data_out;
wire [REG_ADDR_WIDTH-1:0] addr_out;
wire en_out;
pipeline5 pipeline50(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.data(data),
.addr(addr),
.data_out(data_out),
.addr_out(addr_out),
.en_out(en_out)
);
task init_input;
begin
ctrl_in = NOP;
data = 0;
addr = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CTRL = LW,
TESTE1_DATA = 15,
TESTE1_ADDR = 1,
TESTE1_EN = 1;
parameter TESTE2_CTRL = LW_IMM,
TESTE2_DATA = 27,
TESTE2_ADDR = 2,
TESTE2_EN = 1;
parameter TESTE3_CTRL = SW,
TESTE3_DATA = 3562,
TESTE3_ADDR = 3,
TESTE3_EN = 0;
parameter TESTE4_CTRL = ADD,
TESTE4_DATA = 1712,
TESTE4_ADDR = 4,
TESTE4_EN = 1;
parameter TESTE5_CTRL = SUB,
TESTE5_DATA = 645,
TESTE5_ADDR = 5,
TESTE5_EN = 1;
parameter TESTE6_CTRL = MUL,
TESTE6_DATA = 12,
TESTE6_ADDR = 6,
TESTE6_EN = 1;
parameter TESTE7_CTRL = DIV,
TESTE7_DATA = 956,
TESTE7_ADDR = 7,
TESTE7_EN = 1;
parameter TESTE8_CTRL = AND,
TESTE8_DATA = 4754,
TESTE8_ADDR = 8,
TESTE8_EN = 1;
parameter TESTE9_CTRL = OR,
TESTE9_DATA = 666,
TESTE9_ADDR = 9,
TESTE9_EN = 1;
parameter TESTE10_CTRL = NOT,
TESTE10_DATA = 75,
TESTE10_ADDR = 10,
TESTE10_EN = 1;
parameter TESTE11_CTRL = CMP,
TESTE11_DATA = 145,
TESTE11_ADDR = 11,
TESTE11_EN = 0;
parameter TESTE12_CTRL = JR,
TESTE12_DATA = 321,
TESTE12_ADDR = 12,
TESTE12_EN = 0;
parameter TESTE13_CTRL = JPC,
TESTE13_DATA = 451,
TESTE13_ADDR = 13,
TESTE13_EN = 0;
parameter TESTE14_CTRL = BRFL,
TESTE14_DATA = 555,
TESTE14_ADDR = 14,
TESTE14_EN = 0;
parameter TESTE15_CTRL = CALL,
TESTE15_DATA = 777,
TESTE15_ADDR = 15,
TESTE15_EN = 0;
parameter TESTE16_CTRL = RET,
TESTE16_DATA = 999,
TESTE16_ADDR = 16,
TESTE16_EN = 0;
parameter TESTE17_CTRL = NOP,
TESTE17_DATA = 6300,
TESTE17_ADDR = 17,
TESTE17_EN = 0;
begin
case(testes)
0: begin
ctrl_in = TESTE1_CTRL;
data = TESTE1_DATA;
addr = TESTE1_ADDR;
status <= 0;
end
1: begin
ctrl_in = TESTE2_CTRL;
data = TESTE2_DATA;
addr = TESTE2_ADDR;
if (data_out == TESTE1_DATA && en_out == TESTE1_EN && addr_out == TESTE1_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in = TESTE3_CTRL;
data = TESTE3_DATA;
addr = TESTE3_ADDR;
if (data_out == TESTE2_DATA && en_out == TESTE2_EN && addr_out == TESTE2_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in = TESTE4_CTRL;
data = TESTE4_DATA;
addr = TESTE4_ADDR;
if (data_out == TESTE3_DATA && en_out == TESTE3_EN && addr_out == TESTE3_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in = TESTE5_CTRL;
data = TESTE5_DATA;
addr = TESTE5_ADDR;
if (data_out == TESTE4_DATA && en_out == TESTE4_EN && addr_out == TESTE4_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
ctrl_in = TESTE6_CTRL;
data = TESTE6_DATA;
addr = TESTE6_ADDR;
if (data_out == TESTE5_DATA && en_out == TESTE5_EN && addr_out == TESTE5_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
ctrl_in = TESTE7_CTRL;
data = TESTE7_DATA;
addr = TESTE7_ADDR;
if (data_out == TESTE6_DATA && en_out == TESTE6_EN && addr_out == TESTE6_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
ctrl_in = TESTE8_CTRL;
data = TESTE8_DATA;
addr = TESTE8_ADDR;
if (data_out == TESTE7_DATA && en_out == TESTE7_EN && addr_out == TESTE7_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
ctrl_in = TESTE9_CTRL;
data = TESTE9_DATA;
addr = TESTE9_ADDR;
if (data_out == TESTE8_DATA && en_out == TESTE8_EN && addr_out == TESTE8_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
ctrl_in = TESTE10_CTRL;
data = TESTE10_DATA;
addr = TESTE10_ADDR;
if (data_out == TESTE9_DATA && en_out == TESTE9_EN && addr_out == TESTE9_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
ctrl_in = TESTE11_CTRL;
data = TESTE11_DATA;
addr = TESTE11_ADDR;
if (data_out == TESTE10_DATA && en_out == TESTE10_EN && addr_out == TESTE10_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
ctrl_in = TESTE12_CTRL;
data = TESTE12_DATA;
addr = TESTE12_ADDR;
if (data_out == TESTE11_DATA && en_out == TESTE11_EN && addr_out == TESTE11_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
ctrl_in = TESTE13_CTRL;
data = TESTE13_DATA;
addr = TESTE13_ADDR;
if (data_out == TESTE12_DATA && en_out == TESTE12_EN && addr_out == TESTE12_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
ctrl_in = TESTE14_CTRL;
data = TESTE14_DATA;
addr = TESTE14_ADDR;
if (data_out == TESTE13_DATA && en_out == TESTE13_EN && addr_out == TESTE13_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
ctrl_in = TESTE15_CTRL;
data = TESTE15_DATA;
addr = TESTE15_ADDR;
if (data_out == TESTE14_DATA && en_out == TESTE14_EN && addr_out == TESTE14_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
ctrl_in = TESTE16_CTRL;
data = TESTE16_DATA;
addr = TESTE16_ADDR;
if (data_out == TESTE15_DATA && en_out == TESTE15_EN && addr_out == TESTE15_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
16: begin
ctrl_in = TESTE17_CTRL;
data = TESTE17_DATA;
addr = TESTE17_ADDR;
if (data_out == TESTE16_DATA && en_out == TESTE16_EN && addr_out == TESTE16_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
17: begin
ctrl_in = TESTE1_CTRL;
data = TESTE1_DATA;
addr = TESTE1_ADDR;
if (data_out == TESTE17_DATA && en_out == TESTE17_EN && addr_out == TESTE17_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t ADDR: %6d - DATA: %6d ", addr, data);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t DATA_OUT: %6d ", data_out);
$display("\t ADDR_OUT: %6d ", addr_out);
$display("\t EN_OUT: %b ", en_out);
end
endtask
`include "testbench.v"
endmodule | module pipeline5_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 18;
reg clk_in, RST;
reg [CTRL_WIDTH-1:0] ctrl_in;
reg signed [DATA_WIDTH-1:0] data;
reg [REG_ADDR_WIDTH-1:0] addr;
wire signed [DATA_WIDTH-1:0] data_out;
wire [REG_ADDR_WIDTH-1:0] addr_out;
wire en_out;
pipeline5 pipeline50(
.clk_in(clk_in),
.RST(RST),
.ctrl_in(ctrl_in),
.data(data),
.addr(addr),
.data_out(data_out),
.addr_out(addr_out),
.en_out(en_out)
);
task init_input;
begin
ctrl_in = NOP;
data = 0;
addr = 0;
end
endtask
task execute_test;
input integer testes;
output reg status;
parameter TESTE1_CTRL = LW,
TESTE1_DATA = 15,
TESTE1_ADDR = 1,
TESTE1_EN = 1;
parameter TESTE2_CTRL = LW_IMM,
TESTE2_DATA = 27,
TESTE2_ADDR = 2,
TESTE2_EN = 1;
parameter TESTE3_CTRL = SW,
TESTE3_DATA = 3562,
TESTE3_ADDR = 3,
TESTE3_EN = 0;
parameter TESTE4_CTRL = ADD,
TESTE4_DATA = 1712,
TESTE4_ADDR = 4,
TESTE4_EN = 1;
parameter TESTE5_CTRL = SUB,
TESTE5_DATA = 645,
TESTE5_ADDR = 5,
TESTE5_EN = 1;
parameter TESTE6_CTRL = MUL,
TESTE6_DATA = 12,
TESTE6_ADDR = 6,
TESTE6_EN = 1;
parameter TESTE7_CTRL = DIV,
TESTE7_DATA = 956,
TESTE7_ADDR = 7,
TESTE7_EN = 1;
parameter TESTE8_CTRL = AND,
TESTE8_DATA = 4754,
TESTE8_ADDR = 8,
TESTE8_EN = 1;
parameter TESTE9_CTRL = OR,
TESTE9_DATA = 666,
TESTE9_ADDR = 9,
TESTE9_EN = 1;
parameter TESTE10_CTRL = NOT,
TESTE10_DATA = 75,
TESTE10_ADDR = 10,
TESTE10_EN = 1;
parameter TESTE11_CTRL = CMP,
TESTE11_DATA = 145,
TESTE11_ADDR = 11,
TESTE11_EN = 0;
parameter TESTE12_CTRL = JR,
TESTE12_DATA = 321,
TESTE12_ADDR = 12,
TESTE12_EN = 0;
parameter TESTE13_CTRL = JPC,
TESTE13_DATA = 451,
TESTE13_ADDR = 13,
TESTE13_EN = 0;
parameter TESTE14_CTRL = BRFL,
TESTE14_DATA = 555,
TESTE14_ADDR = 14,
TESTE14_EN = 0;
parameter TESTE15_CTRL = CALL,
TESTE15_DATA = 777,
TESTE15_ADDR = 15,
TESTE15_EN = 0;
parameter TESTE16_CTRL = RET,
TESTE16_DATA = 999,
TESTE16_ADDR = 16,
TESTE16_EN = 0;
parameter TESTE17_CTRL = NOP,
TESTE17_DATA = 6300,
TESTE17_ADDR = 17,
TESTE17_EN = 0;
begin
case(testes)
0: begin
ctrl_in = TESTE1_CTRL;
data = TESTE1_DATA;
addr = TESTE1_ADDR;
status <= 0;
end
1: begin
ctrl_in = TESTE2_CTRL;
data = TESTE2_DATA;
addr = TESTE2_ADDR;
if (data_out == TESTE1_DATA && en_out == TESTE1_EN && addr_out == TESTE1_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
2: begin
ctrl_in = TESTE3_CTRL;
data = TESTE3_DATA;
addr = TESTE3_ADDR;
if (data_out == TESTE2_DATA && en_out == TESTE2_EN && addr_out == TESTE2_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
3: begin
ctrl_in = TESTE4_CTRL;
data = TESTE4_DATA;
addr = TESTE4_ADDR;
if (data_out == TESTE3_DATA && en_out == TESTE3_EN && addr_out == TESTE3_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
4: begin
ctrl_in = TESTE5_CTRL;
data = TESTE5_DATA;
addr = TESTE5_ADDR;
if (data_out == TESTE4_DATA && en_out == TESTE4_EN && addr_out == TESTE4_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
5: begin
ctrl_in = TESTE6_CTRL;
data = TESTE6_DATA;
addr = TESTE6_ADDR;
if (data_out == TESTE5_DATA && en_out == TESTE5_EN && addr_out == TESTE5_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
6: begin
ctrl_in = TESTE7_CTRL;
data = TESTE7_DATA;
addr = TESTE7_ADDR;
if (data_out == TESTE6_DATA && en_out == TESTE6_EN && addr_out == TESTE6_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
7: begin
ctrl_in = TESTE8_CTRL;
data = TESTE8_DATA;
addr = TESTE8_ADDR;
if (data_out == TESTE7_DATA && en_out == TESTE7_EN && addr_out == TESTE7_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
8: begin
ctrl_in = TESTE9_CTRL;
data = TESTE9_DATA;
addr = TESTE9_ADDR;
if (data_out == TESTE8_DATA && en_out == TESTE8_EN && addr_out == TESTE8_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
9: begin
ctrl_in = TESTE10_CTRL;
data = TESTE10_DATA;
addr = TESTE10_ADDR;
if (data_out == TESTE9_DATA && en_out == TESTE9_EN && addr_out == TESTE9_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
10: begin
ctrl_in = TESTE11_CTRL;
data = TESTE11_DATA;
addr = TESTE11_ADDR;
if (data_out == TESTE10_DATA && en_out == TESTE10_EN && addr_out == TESTE10_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
11: begin
ctrl_in = TESTE12_CTRL;
data = TESTE12_DATA;
addr = TESTE12_ADDR;
if (data_out == TESTE11_DATA && en_out == TESTE11_EN && addr_out == TESTE11_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
12: begin
ctrl_in = TESTE13_CTRL;
data = TESTE13_DATA;
addr = TESTE13_ADDR;
if (data_out == TESTE12_DATA && en_out == TESTE12_EN && addr_out == TESTE12_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
13: begin
ctrl_in = TESTE14_CTRL;
data = TESTE14_DATA;
addr = TESTE14_ADDR;
if (data_out == TESTE13_DATA && en_out == TESTE13_EN && addr_out == TESTE13_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
14: begin
ctrl_in = TESTE15_CTRL;
data = TESTE15_DATA;
addr = TESTE15_ADDR;
if (data_out == TESTE14_DATA && en_out == TESTE14_EN && addr_out == TESTE14_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
15: begin
ctrl_in = TESTE16_CTRL;
data = TESTE16_DATA;
addr = TESTE16_ADDR;
if (data_out == TESTE15_DATA && en_out == TESTE15_EN && addr_out == TESTE15_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
16: begin
ctrl_in = TESTE17_CTRL;
data = TESTE17_DATA;
addr = TESTE17_ADDR;
if (data_out == TESTE16_DATA && en_out == TESTE16_EN && addr_out == TESTE16_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
17: begin
ctrl_in = TESTE1_CTRL;
data = TESTE1_DATA;
addr = TESTE1_ADDR;
if (data_out == TESTE17_DATA && en_out == TESTE17_EN && addr_out == TESTE17_ADDR) begin
status <= 0;
end else begin
status <= 1;
end
end
default: begin
status <= 0;
end
endcase
end
endtask
task display_input;
input integer testes;
input reg status;
begin
$display(" Teste # %2d => ", testes);
$display("\t ------ ENTRADAS ------- ");
$display("\t ADDR: %6d - DATA: %6d ", addr, data);
$write( "\t CTRL: %b (", ctrl_in);
case(ctrl_in)
LW: $display("LW)");
LW_IMM: $display("LW_IMM)");
SW: $display("SW)");
ADD: $display("ADD)");
SUB: $display("SUB)");
MUL: $display("MUL)");
DIV: $display("DIV)");
AND: $display("AND)");
OR: $display("OR)");
NOT: $display("NOT)");
CMP: $display("CMP)");
JR: $display("JR)");
JPC: $display("JPC)");
BRFL: $display("BRFL)");
CALL: $display("CALL)");
RET: $display("RET)");
NOP: $display("NOP)");
endcase
end
endtask
task display_output;
input integer testes;
input reg status;
begin
$display("\t ------ SAIDAS ------- ");
$display("\t DATA_OUT: %6d ", data_out);
$display("\t ADDR_OUT: %6d ", addr_out);
$display("\t EN_OUT: %b ", en_out);
end
endtask
`include "testbench.v"
endmodule | 0 |
3,658 | data/full_repos/permissive/106029354/verilog_source/pipeline_ctrl.v | 106,029,354 | pipeline_ctrl.v | v | 74 | 124 | [] | [] | [] | [(1, 142)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline_ctrl.v:23: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,450 | module | module pipeline_ctrl(
clk, RST,
A_addr,
B_addr,
ctrl,
ctrl_p34,
ctrl_p45,
reg_en_p52,
reg_addr_p34,
reg_addr_p45,
reg_addr_p52,
reg_dataA_p2,
reg_dataB_p2,
reg_data_p34,
imm_data_p34,
reg_data_p45,
reg_data_p52,
muxA_data,
muxB_data
);
`include "params_proc.v"
input clk, RST;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input [CTRL_WIDTH-1:0] ctrl, ctrl_p34, ctrl_p45;
input reg_en_p52;
input [REG_ADDR_WIDTH-1:0] reg_addr_p34, reg_addr_p45, reg_addr_p52;
input signed [DATA_WIDTH-1:0] reg_dataA_p2, reg_dataB_p2, reg_data_p34, imm_data_p34, reg_data_p45, reg_data_p52;
output reg signed [DATA_WIDTH-1:0] muxA_data, muxB_data;
always @(*) begin
muxA_data = reg_dataA_p2;
muxB_data = reg_dataB_p2;
if (ctrl_p34 == LW_IMM) begin
muxA_data = imm_data_p34;
end else if (A_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
muxA_data = reg_data_p34;
end else if (A_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
muxA_data = reg_data_p45;
end else if (A_addr == reg_addr_p52 && reg_en_p52 == 1) begin
muxA_data = reg_data_p52;
end
if (B_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
muxB_data = reg_data_p34;
end else if (B_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
muxB_data = reg_data_p45;
end else if (B_addr == reg_addr_p52 && reg_en_p52 == 1) begin
muxB_data = reg_data_p52;
end
end
endmodule | module pipeline_ctrl(
clk, RST,
A_addr,
B_addr,
ctrl,
ctrl_p34,
ctrl_p45,
reg_en_p52,
reg_addr_p34,
reg_addr_p45,
reg_addr_p52,
reg_dataA_p2,
reg_dataB_p2,
reg_data_p34,
imm_data_p34,
reg_data_p45,
reg_data_p52,
muxA_data,
muxB_data
); |
`include "params_proc.v"
input clk, RST;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input [CTRL_WIDTH-1:0] ctrl, ctrl_p34, ctrl_p45;
input reg_en_p52;
input [REG_ADDR_WIDTH-1:0] reg_addr_p34, reg_addr_p45, reg_addr_p52;
input signed [DATA_WIDTH-1:0] reg_dataA_p2, reg_dataB_p2, reg_data_p34, imm_data_p34, reg_data_p45, reg_data_p52;
output reg signed [DATA_WIDTH-1:0] muxA_data, muxB_data;
always @(*) begin
muxA_data = reg_dataA_p2;
muxB_data = reg_dataB_p2;
if (ctrl_p34 == LW_IMM) begin
muxA_data = imm_data_p34;
end else if (A_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
muxA_data = reg_data_p34;
end else if (A_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
muxA_data = reg_data_p45;
end else if (A_addr == reg_addr_p52 && reg_en_p52 == 1) begin
muxA_data = reg_data_p52;
end
if (B_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
muxB_data = reg_data_p34;
end else if (B_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
muxB_data = reg_data_p45;
end else if (B_addr == reg_addr_p52 && reg_en_p52 == 1) begin
muxB_data = reg_data_p52;
end
end
endmodule | 0 |
3,659 | data/full_repos/permissive/106029354/verilog_source/pipeline_testbench.v | 106,029,354 | pipeline_testbench.v | v | 32 | 70 | [] | [] | [] | [(1, 101)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/pipeline_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/pipeline_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/pipeline_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 1,451 | module | module pipeline_testbench();
`include "params_proc.v"
reg clk_in, RST;
pipeline pipe(.clk_in(clk_in), .RST(RST));
initial begin
clk_in = 0;
RST = 1;
#3;
RST = 0;
#3;
RST = 1;
end
always begin
#4;
clk_in = !clk_in;
end
endmodule | module pipeline_testbench(); |
`include "params_proc.v"
reg clk_in, RST;
pipeline pipe(.clk_in(clk_in), .RST(RST));
initial begin
clk_in = 0;
RST = 1;
#3;
RST = 0;
#3;
RST = 1;
end
always begin
#4;
clk_in = !clk_in;
end
endmodule | 0 |
3,660 | data/full_repos/permissive/106029354/verilog_source/regs.v | 106,029,354 | regs.v | v | 45 | 91 | [] | [] | [] | [(3, 114)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/regs.v:15: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,452 | module | module regs(
clk,
en_write,
data_write,
addr_write,
addr_read1,
addr_read2,
data_read1,
data_read2
);
`include "params_proc.v"
input clk, en_write;
input signed [DATA_WIDTH-1:0] data_write;
input [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
output [DATA_WIDTH-1:0] data_read1, data_read2;
reg [DATA_WIDTH-1:0] ram [0:(1<<REG_ADDR_WIDTH)-1];
always @ (posedge clk) begin
if (en_write) begin
ram[addr_write] <= data_write;
end
end
assign data_read1 = (addr_write == addr_read1 && en_write ? data_write : ram[addr_read1]);
assign data_read2 = (addr_write == addr_read2 && en_write ? data_write : ram[addr_read2]);
initial begin
ram[0] <= 0;
ram[1] <= 1;
end
endmodule | module regs(
clk,
en_write,
data_write,
addr_write,
addr_read1,
addr_read2,
data_read1,
data_read2
); |
`include "params_proc.v"
input clk, en_write;
input signed [DATA_WIDTH-1:0] data_write;
input [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
output [DATA_WIDTH-1:0] data_read1, data_read2;
reg [DATA_WIDTH-1:0] ram [0:(1<<REG_ADDR_WIDTH)-1];
always @ (posedge clk) begin
if (en_write) begin
ram[addr_write] <= data_write;
end
end
assign data_read1 = (addr_write == addr_read1 && en_write ? data_write : ram[addr_read1]);
assign data_read2 = (addr_write == addr_read2 && en_write ? data_write : ram[addr_read2]);
initial begin
ram[0] <= 0;
ram[1] <= 1;
end
endmodule | 0 |
3,661 | data/full_repos/permissive/106029354/verilog_source/regs_testbench.v | 106,029,354 | regs_testbench.v | v | 148 | 99 | [] | [] | [] | [(1, 217)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,453 | module | module regs_testbench();
`include "params_proc.v"
parameter N_TESTES = 11;
integer testes;
reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;
wire signed [DATA_WIDTH-1:0] data_read1, data_read2;
regs regs0(
.clk(clk),
.en_write(en_write),
.data_write(data_write),
.addr_write(addr_write),
.addr_read1(addr_read1),
.addr_read2(addr_read2),
.data_read1(data_read1),
.data_read2(data_read2));
initial begin
testes <= 0;
clk <= 0;
end
always begin
#2;
clk = !clk;
end
always begin
#4;
testes = testes+1;
case(testes)
1: begin
en_write = 1;
addr_write = 0;
data_write = 5;
addr_read1 = 0;
addr_read2 = 0;
end
2: begin
en_write = 0;
addr_write = 7;
data_write = 65;
addr_read1 = 0;
addr_read2 = 1;
end
3: begin
en_write = 1;
addr_write = 8;
data_write = 11;
addr_read1 = 0;
addr_read2 = 1;
end
4: begin
en_write = 0;
addr_write = 7;
data_write = 18;
addr_read1 = 8;
addr_read2 = 1;
end
5: begin
en_write = 1;
addr_write = 1;
data_write = 16;
addr_read1 = 0;
addr_read2 = 1;
end
6: begin
en_write = 1;
addr_write = 2;
data_write = 24;
addr_read1 = 0;
addr_read2 = 1;
end
7: begin
en_write = 0;
addr_write = 2;
data_write = 29;
addr_read1 = 1;
addr_read2 = 2;
end
8: begin
en_write = 1;
addr_write = 15;
data_write = 20;
addr_read1 = 1;
addr_read2 = 2;
end
9: begin
en_write = 0;
addr_write = 21;
data_write = 25400;
addr_read1 = 15;
addr_read2 = 0;
end
10: begin
en_write = 1;
addr_write = 31;
data_write = 2000;
addr_read1 = 15;
addr_read2 = 0;
end
11: begin
en_write = 0;
addr_write = 20;
data_write = 200;
addr_read1 = 31;
addr_read2 = 0;
end
default: begin
end
endcase
end
always @(posedge clk) begin
if (testes > 0 && testes <= N_TESTES) begin
$display(" Teste # %2d => ", testes);
$display("\t WRITE - EN: %b - ADDR: %3d - DATA: %6d ", en_write, addr_write, data_write);
$display("\t READ_1\n\t ADDR: %3d ", addr_read1);
$display("\t DATA: %6d ", data_read1);
$display("\t READ_2\n\t ADDR: %3d ", addr_read2);
$display("\t DATA: %6d ", data_read2);
$display(" ");
end
end
endmodule | module regs_testbench(); |
`include "params_proc.v"
parameter N_TESTES = 11;
integer testes;
reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;
wire signed [DATA_WIDTH-1:0] data_read1, data_read2;
regs regs0(
.clk(clk),
.en_write(en_write),
.data_write(data_write),
.addr_write(addr_write),
.addr_read1(addr_read1),
.addr_read2(addr_read2),
.data_read1(data_read1),
.data_read2(data_read2));
initial begin
testes <= 0;
clk <= 0;
end
always begin
#2;
clk = !clk;
end
always begin
#4;
testes = testes+1;
case(testes)
1: begin
en_write = 1;
addr_write = 0;
data_write = 5;
addr_read1 = 0;
addr_read2 = 0;
end
2: begin
en_write = 0;
addr_write = 7;
data_write = 65;
addr_read1 = 0;
addr_read2 = 1;
end
3: begin
en_write = 1;
addr_write = 8;
data_write = 11;
addr_read1 = 0;
addr_read2 = 1;
end
4: begin
en_write = 0;
addr_write = 7;
data_write = 18;
addr_read1 = 8;
addr_read2 = 1;
end
5: begin
en_write = 1;
addr_write = 1;
data_write = 16;
addr_read1 = 0;
addr_read2 = 1;
end
6: begin
en_write = 1;
addr_write = 2;
data_write = 24;
addr_read1 = 0;
addr_read2 = 1;
end
7: begin
en_write = 0;
addr_write = 2;
data_write = 29;
addr_read1 = 1;
addr_read2 = 2;
end
8: begin
en_write = 1;
addr_write = 15;
data_write = 20;
addr_read1 = 1;
addr_read2 = 2;
end
9: begin
en_write = 0;
addr_write = 21;
data_write = 25400;
addr_read1 = 15;
addr_read2 = 0;
end
10: begin
en_write = 1;
addr_write = 31;
data_write = 2000;
addr_read1 = 15;
addr_read2 = 0;
end
11: begin
en_write = 0;
addr_write = 20;
data_write = 200;
addr_read1 = 31;
addr_read2 = 0;
end
default: begin
end
endcase
end
always @(posedge clk) begin
if (testes > 0 && testes <= N_TESTES) begin
$display(" Teste # %2d => ", testes);
$display("\t WRITE - EN: %b - ADDR: %3d - DATA: %6d ", en_write, addr_write, data_write);
$display("\t READ_1\n\t ADDR: %3d ", addr_read1);
$display("\t DATA: %6d ", data_read1);
$display("\t READ_2\n\t ADDR: %3d ", addr_read2);
$display("\t DATA: %6d ", data_read2);
$display(" ");
end
end
endmodule | 0 |
3,662 | data/full_repos/permissive/106029354/verilog_source/top.v | 106,029,354 | top.v | v | 27 | 47 | [] | [] | [] | [(3, 95)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/top.v:9: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,455 | module | module top(
clk,
RST
);
`include "params_proc.v"
input clk;
input RST;
pipeline pipe(
.clk(clk), .RST(RST)
);
endmodule | module top(
clk,
RST
); |
`include "params_proc.v"
input clk;
input RST;
pipeline pipe(
.clk(clk), .RST(RST)
);
endmodule | 0 |
3,663 | data/full_repos/permissive/106029354/verilog_source/ula.v | 106,029,354 | ula.v | v | 113 | 80 | [] | [] | [] | [(1, 182)] | null | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/ula.v:9: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n' | 1,456 | module | module ula( opcode,
data1,
data2,
out,
rflags
);
`include "params_proc.v"
input [OPCODE_WIDTH-1:0] opcode;
input signed [DATA_WIDTH-1:0] data1, data2;
output reg signed [DATA_WIDTH-1:0] out;
output reg [RFLAGS_WIDTH-1:0] rflags;
reg xor_data12_sign;
reg signed [DATA_WIDTH-1:0] data2_aux;
always @(*) begin
out = data1;
rflags = 0;
data2_aux = 0;
xor_data12_sign = data1[DATA_WIDTH-1] ^ data2[DATA_WIDTH-1];
if (opcode == ADD || opcode == SUB || opcode == CMP) begin
data2_aux = (opcode == SUB || opcode == CMP ? (~ data2) + 1 : data2);
out = data1 + data2_aux;
case(out[DATA_WIDTH-1])
1'b0: begin
if (data1[DATA_WIDTH-1] == 1 && data2_aux[DATA_WIDTH-1] == 1) begin
rflags[4] = 1;
end
end
default: begin
if (data1[DATA_WIDTH-1] == 0 && data2_aux[DATA_WIDTH-1] == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == MUL) begin
out = data1 * data2;
case(out[DATA_WIDTH-1])
1'b0: begin
if (xor_data12_sign == 1) begin
rflags[4] = 1;
end
end
default: begin
if (xor_data12_sign == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == DIV) begin
if (data2 != 0) begin
out = data1 / data2;
end else begin
rflags[0] = 1;
end
end else if (opcode == AND) begin
out = data1 & data2;
end else if (opcode == OR) begin
out = data1 | data2;
end else if (opcode == NOT) begin
out = (data1 == 0 ? 1 : 0) ;
end
if (opcode == CMP) begin
if (out == 0) begin
rflags = 5'b00100;
end else if (xor_data12_sign) begin
if (data1[DATA_WIDTH-1]) begin
rflags = 5'b00010;
end else begin
rflags = 5'b01000;
end
end else begin
if (out[DATA_WIDTH-1]) begin
rflags = 5'b00010;
end else begin
rflags = 5'b01000;
end
end
end
end
endmodule | module ula( opcode,
data1,
data2,
out,
rflags
); |
`include "params_proc.v"
input [OPCODE_WIDTH-1:0] opcode;
input signed [DATA_WIDTH-1:0] data1, data2;
output reg signed [DATA_WIDTH-1:0] out;
output reg [RFLAGS_WIDTH-1:0] rflags;
reg xor_data12_sign;
reg signed [DATA_WIDTH-1:0] data2_aux;
always @(*) begin
out = data1;
rflags = 0;
data2_aux = 0;
xor_data12_sign = data1[DATA_WIDTH-1] ^ data2[DATA_WIDTH-1];
if (opcode == ADD || opcode == SUB || opcode == CMP) begin
data2_aux = (opcode == SUB || opcode == CMP ? (~ data2) + 1 : data2);
out = data1 + data2_aux;
case(out[DATA_WIDTH-1])
1'b0: begin
if (data1[DATA_WIDTH-1] == 1 && data2_aux[DATA_WIDTH-1] == 1) begin
rflags[4] = 1;
end
end
default: begin
if (data1[DATA_WIDTH-1] == 0 && data2_aux[DATA_WIDTH-1] == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == MUL) begin
out = data1 * data2;
case(out[DATA_WIDTH-1])
1'b0: begin
if (xor_data12_sign == 1) begin
rflags[4] = 1;
end
end
default: begin
if (xor_data12_sign == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == DIV) begin
if (data2 != 0) begin
out = data1 / data2;
end else begin
rflags[0] = 1;
end
end else if (opcode == AND) begin
out = data1 & data2;
end else if (opcode == OR) begin
out = data1 | data2;
end else if (opcode == NOT) begin
out = (data1 == 0 ? 1 : 0) ;
end
if (opcode == CMP) begin
if (out == 0) begin
rflags = 5'b00100;
end else if (xor_data12_sign) begin
if (data1[DATA_WIDTH-1]) begin
rflags = 5'b00010;
end else begin
rflags = 5'b01000;
end
end else begin
if (out[DATA_WIDTH-1]) begin
rflags = 5'b00010;
end else begin
rflags = 5'b01000;
end
end
end
end
endmodule | 0 |
3,664 | data/full_repos/permissive/106029354/verilog_source/ula_testbench.v | 106,029,354 | ula_testbench.v | v | 268 | 90 | [] | [] | [] | null | line:154: before: "(" | null | 1: b'%Error: data/full_repos/permissive/106029354/verilog_source/ula_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n params_proc.v\n params_proc.v.v\n params_proc.v.sv\n obj_dir/params_proc.v\n obj_dir/params_proc.v.v\n obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/ula_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,457 | module | module ula_testbench();
`include "params_proc.v"
integer testes;
reg signed [OPCODE_WIDTH-1:0] opcode;
reg signed [DATA_WIDTH-1:0] data1, data2;
wire signed [DATA_WIDTH-1:0] out;
wire [4:0] rflags;
ula ula0(.opcode(opcode), .data1(data1), .data2(data2), .out(out), .rflags(rflags));
initial begin
testes = 0;
end
always begin
#5;
testes <= testes+1;
end
task print_results;
begin
$write(" Teste # %2d => Opcode: %b | RFlags = %b | ", testes, opcode, rflags);
case(opcode)
ADD: begin
$write("%6d + %6d = %6d", data1, data2, out);
end
SUB: begin
$write("%6d - %6d = %6d", data1, data2, out);
end
MUL: begin
$write("%6d * %6d = %6d", data1, data2, out);
end
DIV: begin
$write("%6d / %6d = %6d", data1, data2, out);
end
AND: begin
$write("%6d & %6d = %6d", data1, data2, out);
end
OR: begin
$write("%6d | %6d = %6d", data1, data2, out);
end
NOT: begin
$write("! %6d = %6d", data1, out);
end
CMP: begin
$write("%6d cmp %6d = %6d", data1, data2, out);
end
default: begin
$write("%6d ?? %6d = %6d", data1, data2, out);
end
endcase
$write(" | RFlags (descricao) = ");
if (rflags[4] == 1) begin
$write("OVERFLOW + ");
end
if (rflags[3] == 1) begin
$write("ABOVE + ");
end
if (rflags[2] == 1) begin
$write("EQUAL + ");
end
if (rflags[1] == 1) begin
$write("BELOW + ");
end
if (rflags[0] == 1) begin
$write("ERROR");
end
$display(" ");
end
endtask
always @(out,rflags) begin
print_results();
end
always @(testes) begin
case(testes)
1: begin
data1 = 5;
data2 = 10;
opcode = ADD;
end
2: begin
data1 = 5;
data2 = -5;
opcode = ADD;
end
3: begin
data1 = 5;
data2 = -8;
opcode = ADD;
end
4: begin
data1 = 32767;
data2 = 1;
opcode = ADD;
end
5: begin
data1 = 5;
data2 = 3;
opcode = SUB;
end
6: begin
data1 = 5;
data2 = 9;
opcode = SUB;
end
7: begin
data1 = 5;
data2 = 5;
opcode = SUB;
end
8: begin
data1 = 0;
data2 = 32768;
opcode = SUB;
end
9: begin
data1 = -1;
data2 = 32768;
opcode = SUB;
end
10: begin
data1 = 0;
data2 = 5;
opcode = MUL;
end
11: begin
data1 = 32767;
data2 = 2;
opcode = MUL;
end
12: begin
data1 = 5;
data2 = 2;
opcode = MUL;
end
13: begin
data1 = -5;
data2 = -2;
opcode = MUL;
end
14: begin
data1 = -5;
data2 = 2;
opcode = MUL;
end
15: begin
data1 = -5;
data2 = 2;
opcode = DIV;
end
16: begin
data1 = 5;
data2 = -3;
opcode = DIV;
end
17: begin
data1 = -10;
data2 = -2;
opcode = DIV;
end
18: begin
data1 = 5;
data2 = 5;
opcode = DIV;
end
19: begin
data1 = 0;
data2 = 5;
opcode = DIV;
end
20: begin
data1 = 1;
data2 = 5;
opcode = DIV;
end
21: begin
data1 = 6;
data2 = 0;
opcode = DIV;
end
22: begin
data1 = 5;
data2 = 7;
opcode = AND;
end
23: begin
data1 = 5;
data2 = 7;
opcode = OR;
end
24: begin
data1 = 5;
data2 = 7;
opcode = NOT;
end
25: begin
data1 = 0;
data2 = 8;
opcode = NOT;
end
26: begin
data1 = -5;
data2 = 8;
opcode = CMP;
end
27: begin
data1 = 5;
data2 = -8;
opcode = CMP;
end
28: begin
data1 = 5;
data2 = 8;
opcode = CMP;
end
29: begin
data1 = -32768;
data2 = -32768;
opcode = CMP;
end
30: begin
data1 = 10;
data2 = 6;
opcode = CMP;
end
31: begin
data1 = 32767;
data2 = -1;
opcode = CMP;
end
32: begin
data1 = -32768;
data2 = 32767;
opcode = CMP;
end
33: begin
data1 = 1;
data2 = -32768;
opcode = CMP;
end
34: begin
data1 = 32767;
data2 = 32767;
opcode = CMP;
end
default: begin
end
endcase
end
endmodule | module ula_testbench(); |
`include "params_proc.v"
integer testes;
reg signed [OPCODE_WIDTH-1:0] opcode;
reg signed [DATA_WIDTH-1:0] data1, data2;
wire signed [DATA_WIDTH-1:0] out;
wire [4:0] rflags;
ula ula0(.opcode(opcode), .data1(data1), .data2(data2), .out(out), .rflags(rflags));
initial begin
testes = 0;
end
always begin
#5;
testes <= testes+1;
end
task print_results;
begin
$write(" Teste # %2d => Opcode: %b | RFlags = %b | ", testes, opcode, rflags);
case(opcode)
ADD: begin
$write("%6d + %6d = %6d", data1, data2, out);
end
SUB: begin
$write("%6d - %6d = %6d", data1, data2, out);
end
MUL: begin
$write("%6d * %6d = %6d", data1, data2, out);
end
DIV: begin
$write("%6d / %6d = %6d", data1, data2, out);
end
AND: begin
$write("%6d & %6d = %6d", data1, data2, out);
end
OR: begin
$write("%6d | %6d = %6d", data1, data2, out);
end
NOT: begin
$write("! %6d = %6d", data1, out);
end
CMP: begin
$write("%6d cmp %6d = %6d", data1, data2, out);
end
default: begin
$write("%6d ?? %6d = %6d", data1, data2, out);
end
endcase
$write(" | RFlags (descricao) = ");
if (rflags[4] == 1) begin
$write("OVERFLOW + ");
end
if (rflags[3] == 1) begin
$write("ABOVE + ");
end
if (rflags[2] == 1) begin
$write("EQUAL + ");
end
if (rflags[1] == 1) begin
$write("BELOW + ");
end
if (rflags[0] == 1) begin
$write("ERROR");
end
$display(" ");
end
endtask
always @(out,rflags) begin
print_results();
end
always @(testes) begin
case(testes)
1: begin
data1 = 5;
data2 = 10;
opcode = ADD;
end
2: begin
data1 = 5;
data2 = -5;
opcode = ADD;
end
3: begin
data1 = 5;
data2 = -8;
opcode = ADD;
end
4: begin
data1 = 32767;
data2 = 1;
opcode = ADD;
end
5: begin
data1 = 5;
data2 = 3;
opcode = SUB;
end
6: begin
data1 = 5;
data2 = 9;
opcode = SUB;
end
7: begin
data1 = 5;
data2 = 5;
opcode = SUB;
end
8: begin
data1 = 0;
data2 = 32768;
opcode = SUB;
end
9: begin
data1 = -1;
data2 = 32768;
opcode = SUB;
end
10: begin
data1 = 0;
data2 = 5;
opcode = MUL;
end
11: begin
data1 = 32767;
data2 = 2;
opcode = MUL;
end
12: begin
data1 = 5;
data2 = 2;
opcode = MUL;
end
13: begin
data1 = -5;
data2 = -2;
opcode = MUL;
end
14: begin
data1 = -5;
data2 = 2;
opcode = MUL;
end
15: begin
data1 = -5;
data2 = 2;
opcode = DIV;
end
16: begin
data1 = 5;
data2 = -3;
opcode = DIV;
end
17: begin
data1 = -10;
data2 = -2;
opcode = DIV;
end
18: begin
data1 = 5;
data2 = 5;
opcode = DIV;
end
19: begin
data1 = 0;
data2 = 5;
opcode = DIV;
end
20: begin
data1 = 1;
data2 = 5;
opcode = DIV;
end
21: begin
data1 = 6;
data2 = 0;
opcode = DIV;
end
22: begin
data1 = 5;
data2 = 7;
opcode = AND;
end
23: begin
data1 = 5;
data2 = 7;
opcode = OR;
end
24: begin
data1 = 5;
data2 = 7;
opcode = NOT;
end
25: begin
data1 = 0;
data2 = 8;
opcode = NOT;
end
26: begin
data1 = -5;
data2 = 8;
opcode = CMP;
end
27: begin
data1 = 5;
data2 = -8;
opcode = CMP;
end
28: begin
data1 = 5;
data2 = 8;
opcode = CMP;
end
29: begin
data1 = -32768;
data2 = -32768;
opcode = CMP;
end
30: begin
data1 = 10;
data2 = 6;
opcode = CMP;
end
31: begin
data1 = 32767;
data2 = -1;
opcode = CMP;
end
32: begin
data1 = -32768;
data2 = 32767;
opcode = CMP;
end
33: begin
data1 = 1;
data2 = -32768;
opcode = CMP;
end
34: begin
data1 = 32767;
data2 = 32767;
opcode = CMP;
end
default: begin
end
endcase
end
endmodule | 0 |
3,673 | data/full_repos/permissive/106330868/boards/Spartan3E StarterKit/speech256_s3e.v | 106,330,868 | speech256_s3e.v | v | 874 | 73 | [] | ['general public license', 'free software foundation'] | [] | null | line:32: before: ")" | null | 1: b'%Error: Cannot find file containing module: StarterKit,data/full_repos/permissive/106330868\n ... Looked in:\n data/full_repos/permissive/106330868/boards/Spartan3E/StarterKit,data/full_repos/permissive/106330868\n data/full_repos/permissive/106330868/boards/Spartan3E/StarterKit,data/full_repos/permissive/106330868.v\n data/full_repos/permissive/106330868/boards/Spartan3E/StarterKit,data/full_repos/permissive/106330868.sv\n StarterKit,data/full_repos/permissive/106330868\n StarterKit,data/full_repos/permissive/106330868.v\n StarterKit,data/full_repos/permissive/106330868.sv\n obj_dir/StarterKit,data/full_repos/permissive/106330868\n obj_dir/StarterKit,data/full_repos/permissive/106330868.v\n obj_dir/StarterKit,data/full_repos/permissive/106330868.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/106330868/boards/Spartan3E\n%Error: Cannot find file containing module: StarterKit/speech256_s3e.v\n%Error: Exiting due to 3 error(s)\n' | 1,468 | module | module Speech256_DE0 (
CLOCK_50,
UART_TXD,
);
input CLOCK_50;
output UART_TXD;
reg [5:0] data_in;
reg data_stb;
reg clk;
reg [3:0] divcnt;
reg [2:0] cur_state, next_state;
reg [9:0] rom_addr;
reg [5:0] rom_data;
reg inc_rom_addr;
wire sample_stb;
wire signed [15:0] sample_out;
wire ldq;
wire rst_an;
SPEECH256_TOP u_speech256_top (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (rom_data),
.data_stb (data_stb),
.pwm_out (UART_TXD),
.sample_out (sample_out),
.sample_stb (sample_stb)
);
assign rst_an = 1'b1;
parameter S_IDLE = 4'b000,
S_ALLOPHONE = 4'b001,
S_WAITDONE = 4'b010;
always @(posedge CLOCK_50)
begin
if (divcnt > 9)
begin
clk <= !clk;
divcnt <= 0;
end
else
begin
divcnt <= divcnt + 1;
end
end
always @(posedge clk)
begin
cur_state <= next_state;
if (inc_rom_addr == 1)
rom_addr <= rom_addr + 1;
end
always @(*)
begin
data_stb <= 0;
inc_rom_addr <= 0;
next_state <= cur_state;
case(cur_state)
S_IDLE:
begin
if (ldq == 1)
begin
inc_rom_addr <= 1;
next_state <= S_ALLOPHONE;
end
else
next_state <= S_IDLE;
end
S_ALLOPHONE:
begin
data_stb <= 1;
next_state <= S_WAITDONE;
end
S_WAITDONE:
begin
if (ldq == 0)
begin
next_state <= S_IDLE;
end
end
default:
begin
next_state <= S_IDLE;
end
endcase
`ifdef HELLO_WORLD
case (rom_addr)
4'd0:
rom_data <= 6'h1B;
4'd1:
rom_data <= 6'h07;
4'd2:
rom_data <= 6'h2D;
4'd3:
rom_data <= 6'h35;
4'd4:
rom_data <= 6'h03;
4'd5:
rom_data <= 6'h2E;
4'd6:
rom_data <= 6'h1E;
4'd7:
rom_data <= 6'h33;
4'd8:
rom_data <= 6'h2D;
4'd9:
rom_data <= 6'h15;
4'd10:
rom_data <= 6'h03;
default:
rom_data <= 6'h03;
endcase
end
`endif
`ifdef TEST1
case (rom_addr)
8'h00: rom_data <= 6'h21;
8'h01: rom_data <= 6'h14;
8'h02: rom_data <= 6'h00;
8'h03: rom_data <= 6'h2B;
8'h04: rom_data <= 6'h13;
8'h05: rom_data <= 6'h04;
8'h06: rom_data <= 6'h21;
8'h07: rom_data <= 6'h14;
8'h08: rom_data <= 6'h00;
8'h09: rom_data <= 6'h2B;
8'h0A: rom_data <= 6'h13;
8'h0B: rom_data <= 6'h03;
8'h0C: rom_data <= 6'h0D;
8'h0D: rom_data <= 6'h3E;
8'h0E: rom_data <= 6'h2D;
8'h0F: rom_data <= 6'h02;
8'h10: rom_data <= 6'h10;
8'h11: rom_data <= 6'h13;
8'h12: rom_data <= 6'h02;
8'h13: rom_data <= 6'h0D;
8'h14: rom_data <= 6'h27;
8'h15: rom_data <= 6'h16;
8'h16: rom_data <= 6'h04;
8'h17: rom_data <= 6'h06;
8'h18: rom_data <= 6'h10;
8'h19: rom_data <= 6'h02;
8'h1A: rom_data <= 6'h18;
8'h1B: rom_data <= 6'h28;
8'h1C: rom_data <= 6'h27;
8'h1D: rom_data <= 6'h14;
8'h1E: rom_data <= 6'h15;
8'h1F: rom_data <= 6'h03;
8'h20: rom_data <= 6'h06;
8'h21: rom_data <= 6'h02;
8'h22: rom_data <= 6'h2A;
8'h23: rom_data <= 6'h1A;
8'h24: rom_data <= 6'h0B;
8'h25: rom_data <= 6'h11;
8'h26: rom_data <= 6'h03;
8'h27: rom_data <= 6'h21;
8'h28: rom_data <= 6'h1F;
8'h29: rom_data <= 6'h02;
8'h2A: rom_data <= 6'h1D;
8'h2B: rom_data <= 6'h1A;
8'h2C: rom_data <= 6'h0D;
8'h2D: rom_data <= 6'h04;
8'h2E: rom_data <= 6'h21;
8'h2F: rom_data <= 6'h14;
8'h30: rom_data <= 6'h23;
8'h31: rom_data <= 6'h04;
8'h32: rom_data <= 6'h19;
8'h33: rom_data <= 6'h07;
8'h34: rom_data <= 6'h07;
8'h35: rom_data <= 6'h37;
8'h36: rom_data <= 6'h37;
8'h37: rom_data <= 6'h02;
8'h38: rom_data <= 6'h1A;
8'h39: rom_data <= 6'h0B;
8'h3A: rom_data <= 6'h15;
8'h3B: rom_data <= 6'h03;
8'h3C: rom_data <= 6'h38;
8'h3D: rom_data <= 6'h0F;
8'h3E: rom_data <= 6'h35;
8'h3F: rom_data <= 6'h04;
8'h40: rom_data <= 6'h2B;
8'h41: rom_data <= 6'h3C;
8'h42: rom_data <= 6'h35;
8'h43: rom_data <= 6'h03;
8'h44: rom_data <= 6'h2E;
8'h45: rom_data <= 6'h0F;
8'h46: rom_data <= 6'h0F;
8'h47: rom_data <= 6'h0B;
8'h48: rom_data <= 6'h03;
8'h49: rom_data <= 6'h0D;
8'h4A: rom_data <= 6'h1F;
8'h4B: rom_data <= 6'h03;
8'h4C: rom_data <= 6'h1D;
8'h4D: rom_data <= 6'h0E;
8'h4E: rom_data <= 6'h13;
8'h4F: rom_data <= 6'h03;
8'h50: rom_data <= 6'h28;
8'h51: rom_data <= 6'h28;
8'h52: rom_data <= 6'h3A;
8'h53: rom_data <= 6'h03;
8'h54: rom_data <= 6'h28;
8'h55: rom_data <= 6'h28;
8'h56: rom_data <= 6'h06;
8'h57: rom_data <= 6'h23;
8'h58: rom_data <= 6'h03;
8'h59: rom_data <= 6'h37;
8'h5A: rom_data <= 6'h37;
8'h5B: rom_data <= 6'h0C;
8'h5C: rom_data <= 6'h1E;
8'h5D: rom_data <= 6'h02;
8'h5E: rom_data <= 6'h29;
8'h5F: rom_data <= 6'h37;
8'h60: rom_data <= 6'h03;
8'h61: rom_data <= 6'h37;
8'h62: rom_data <= 6'h37;
8'h63: rom_data <= 6'h07;
8'h64: rom_data <= 6'h07;
8'h65: rom_data <= 6'h23;
8'h66: rom_data <= 6'h0C;
8'h67: rom_data <= 6'h0B;
8'h68: rom_data <= 6'h03;
8'h69: rom_data <= 6'h14;
8'h6A: rom_data <= 6'h02;
8'h6B: rom_data <= 6'h0D;
8'h6C: rom_data <= 6'h03;
8'h6D: rom_data <= 6'h0B;
8'h6E: rom_data <= 6'h06;
8'h6F: rom_data <= 6'h0B;
8'h70: rom_data <= 6'h03;
8'h71: rom_data <= 6'h0D;
8'h72: rom_data <= 6'h07;
8'h73: rom_data <= 6'h07;
8'h74: rom_data <= 6'h0B;
8'h75: rom_data <= 6'h04;
8'h76: rom_data <= 6'h13;
8'h77: rom_data <= 6'h02;
8'h78: rom_data <= 6'h0D;
8'h79: rom_data <= 6'h13;
8'h7A: rom_data <= 6'h03;
8'h7B: rom_data <= 6'h28;
8'h7C: rom_data <= 6'h28;
8'h7D: rom_data <= 6'h35;
8'h7E: rom_data <= 6'h0B;
8'h7F: rom_data <= 6'h02;
8'h80: rom_data <= 6'h39;
8'h81: rom_data <= 6'h35;
8'h82: rom_data <= 6'h10;
8'h83: rom_data <= 6'h10;
8'h84: rom_data <= 6'h04;
default: rom_data <= 6'h00;
endcase
end
`endif
`ifdef YOUTUBE_MESSAGE
case (rom_addr)
10'h00: rom_data <= 6'h3D;
10'h01: rom_data <= 6'h27;
10'h02: rom_data <= 6'h13;
10'h03: rom_data <= 6'h0D;
10'h04: rom_data <= 6'h0C;
10'h05: rom_data <= 6'h2C;
10'h06: rom_data <= 6'h37;
10'h07: rom_data <= 6'h04;
10'h08: rom_data <= 6'h09;
10'h09: rom_data <= 6'h13;
10'h0A: rom_data <= 6'h09;
10'h0B: rom_data <= 6'h3E;
10'h0C: rom_data <= 6'h02;
10'h0D: rom_data <= 6'h17;
10'h0E: rom_data <= 6'h23;
10'h0F: rom_data <= 6'h02;
10'h10: rom_data <= 6'h33;
10'h11: rom_data <= 6'h1D;
10'h12: rom_data <= 6'h1D;
10'h13: rom_data <= 6'h02;
10'h14: rom_data <= 6'h04;
10'h15: rom_data <= 6'h04;
10'h16: rom_data <= 6'h04;
10'h17: rom_data <= 6'h04;
10'h18: rom_data <= 6'h06;
10'h19: rom_data <= 6'h02;
10'h1A: rom_data <= 6'h1A;
10'h1B: rom_data <= 6'h10;
10'h1C: rom_data <= 6'h02;
10'h1D: rom_data <= 6'h37;
10'h1E: rom_data <= 6'h37;
10'h1F: rom_data <= 6'h09;
10'h20: rom_data <= 6'h13;
10'h21: rom_data <= 6'h32;
10'h22: rom_data <= 6'h0D;
10'h23: rom_data <= 6'h1F;
10'h24: rom_data <= 6'h01;
10'h25: rom_data <= 6'h28;
10'h26: rom_data <= 6'h28;
10'h27: rom_data <= 6'h0C;
10'h28: rom_data <= 6'h28;
10'h29: rom_data <= 6'h28;
10'h2A: rom_data <= 6'h01;
10'h2B: rom_data <= 6'h0D;
10'h2C: rom_data <= 6'h13;
10'h2D: rom_data <= 6'h37;
10'h2E: rom_data <= 6'h37;
10'h2F: rom_data <= 6'h0C;
10'h30: rom_data <= 6'h0C;
10'h31: rom_data <= 6'h02;
10'h32: rom_data <= 6'h29;
10'h33: rom_data <= 6'h37;
10'h34: rom_data <= 6'h04;
10'h35: rom_data <= 6'h04;
10'h36: rom_data <= 6'h0F;
10'h37: rom_data <= 6'h0B;
10'h38: rom_data <= 6'h02;
10'h39: rom_data <= 6'h07;
10'h3A: rom_data <= 6'h07;
10'h3B: rom_data <= 6'h28;
10'h3C: rom_data <= 6'h28;
10'h3D: rom_data <= 6'h02;
10'h3E: rom_data <= 6'h09;
10'h3F: rom_data <= 6'h13;
10'h40: rom_data <= 6'h02;
10'h41: rom_data <= 6'h0A;
10'h42: rom_data <= 6'h13;
10'h43: rom_data <= 6'h02;
10'h44: rom_data <= 6'h14;
10'h45: rom_data <= 6'h02;
10'h46: rom_data <= 6'h0C;
10'h47: rom_data <= 6'h10;
10'h48: rom_data <= 6'h01;
10'h49: rom_data <= 6'h09;
10'h4A: rom_data <= 6'h2D;
10'h4B: rom_data <= 6'h07;
10'h4C: rom_data <= 6'h10;
10'h4D: rom_data <= 6'h07;
10'h4E: rom_data <= 6'h0B;
10'h4F: rom_data <= 6'h0D;
10'h50: rom_data <= 6'h14;
10'h51: rom_data <= 6'h32;
10'h52: rom_data <= 6'h1E;
10'h53: rom_data <= 6'h0B;
10'h54: rom_data <= 6'h03;
10'h55: rom_data <= 6'h17;
10'h56: rom_data <= 6'h23;
10'h57: rom_data <= 6'h02;
10'h58: rom_data <= 6'h0F;
10'h59: rom_data <= 6'h0B;
10'h5A: rom_data <= 6'h02;
10'h5B: rom_data <= 6'h14;
10'h5C: rom_data <= 6'h02;
10'h5D: rom_data <= 6'h0D;
10'h5E: rom_data <= 6'h13;
10'h5F: rom_data <= 6'h2B;
10'h60: rom_data <= 6'h02;
10'h61: rom_data <= 6'h37;
10'h62: rom_data <= 6'h37;
10'h63: rom_data <= 6'h09;
10'h64: rom_data <= 6'h13;
10'h65: rom_data <= 6'h32;
10'h66: rom_data <= 6'h02;
10'h67: rom_data <= 6'h37;
10'h68: rom_data <= 6'h0C;
10'h69: rom_data <= 6'h0B;
10'h6A: rom_data <= 6'h1D;
10'h6B: rom_data <= 6'h07;
10'h6C: rom_data <= 6'h37;
10'h6D: rom_data <= 6'h18;
10'h6E: rom_data <= 6'h06;
10'h6F: rom_data <= 6'h2B;
10'h70: rom_data <= 6'h33;
10'h71: rom_data <= 6'h02;
10'h72: rom_data <= 6'h32;
10'h73: rom_data <= 6'h0C;
10'h74: rom_data <= 6'h0C;
10'h75: rom_data <= 6'h09;
10'h76: rom_data <= 6'h04;
10'h77: rom_data <= 6'h04;
10'h78: rom_data <= 6'h04;
10'h79: rom_data <= 6'h04;
10'h7A: rom_data <= 6'h04;
10'h7B: rom_data <= 6'h06;
10'h7C: rom_data <= 6'h02;
10'h7D: rom_data <= 6'h2A;
10'h7E: rom_data <= 6'h33;
10'h7F: rom_data <= 6'h07;
10'h80: rom_data <= 6'h0D;
10'h81: rom_data <= 6'h2D;
10'h82: rom_data <= 6'h13;
10'h83: rom_data <= 6'h02;
10'h84: rom_data <= 6'h2D;
10'h85: rom_data <= 6'h0C;
10'h86: rom_data <= 6'h23;
10'h87: rom_data <= 6'h02;
10'h88: rom_data <= 6'h18;
10'h89: rom_data <= 6'h0B;
10'h8A: rom_data <= 6'h02;
10'h8B: rom_data <= 6'h0F;
10'h8C: rom_data <= 6'h02;
10'h8D: rom_data <= 6'h15;
10'h8E: rom_data <= 6'h0C;
10'h8F: rom_data <= 6'h0C;
10'h90: rom_data <= 6'h0A;
10'h91: rom_data <= 6'h02;
10'h92: rom_data <= 6'h0C;
10'h93: rom_data <= 6'h2D;
10'h94: rom_data <= 6'h07;
10'h95: rom_data <= 6'h07;
10'h96: rom_data <= 6'h0B;
10'h97: rom_data <= 6'h0D;
10'h98: rom_data <= 6'h03;
10'h99: rom_data <= 6'h21;
10'h9A: rom_data <= 6'h13;
10'h9B: rom_data <= 6'h02;
10'h9C: rom_data <= 6'h13;
10'h9D: rom_data <= 6'h02;
10'h9E: rom_data <= 6'h2B;
10'h9F: rom_data <= 6'h3C;
10'hA0: rom_data <= 6'h35;
10'hA1: rom_data <= 6'h02;
10'hA2: rom_data <= 6'h1C;
10'hA3: rom_data <= 6'h3A;
10'hA4: rom_data <= 6'h15;
10'hA5: rom_data <= 6'h04;
10'hA6: rom_data <= 6'h04;
10'hA7: rom_data <= 6'h1A;
10'hA8: rom_data <= 6'h0B;
10'hA9: rom_data <= 6'h15;
10'hAA: rom_data <= 6'h02;
10'hAB: rom_data <= 6'h06;
10'hAC: rom_data <= 6'h03;
10'hAD: rom_data <= 6'h31;
10'hAE: rom_data <= 6'h16;
10'hAF: rom_data <= 6'h2B;
10'hB0: rom_data <= 6'h03;
10'hB1: rom_data <= 6'h0F;
10'hB2: rom_data <= 6'h3F;
10'hB3: rom_data <= 6'h20;
10'hB4: rom_data <= 6'h0D;
10'hB5: rom_data <= 6'h02;
10'hB6: rom_data <= 6'h37;
10'hB7: rom_data <= 6'h37;
10'hB8: rom_data <= 6'h07;
10'hB9: rom_data <= 6'h07;
10'hBA: rom_data <= 6'h23;
10'hBB: rom_data <= 6'h0C;
10'hBC: rom_data <= 6'h0B;
10'hBD: rom_data <= 6'h02;
10'hBE: rom_data <= 6'h39;
10'hBF: rom_data <= 6'h0F;
10'hC0: rom_data <= 6'h0F;
10'hC1: rom_data <= 6'h0B;
10'hC2: rom_data <= 6'h01;
10'hC3: rom_data <= 6'h21;
10'hC4: rom_data <= 6'h27;
10'hC5: rom_data <= 6'h0C;
10'hC6: rom_data <= 6'h0C;
10'hC7: rom_data <= 6'h00;
10'hC8: rom_data <= 6'h15;
10'hC9: rom_data <= 6'h03;
10'hCA: rom_data <= 6'h2D;
10'hCB: rom_data <= 6'h17;
10'hCC: rom_data <= 6'h0A;
10'hCD: rom_data <= 6'h0C;
10'hCE: rom_data <= 6'h0C;
10'hCF: rom_data <= 6'h29;
10'hD0: rom_data <= 6'h02;
10'hD1: rom_data <= 6'h07;
10'hD2: rom_data <= 6'h2D;
10'hD3: rom_data <= 6'h07;
10'hD4: rom_data <= 6'h10;
10'hD5: rom_data <= 6'h07;
10'hD6: rom_data <= 6'h0B;
10'hD7: rom_data <= 6'h0D;
10'hD8: rom_data <= 6'h37;
10'hD9: rom_data <= 6'h03;
10'hDA: rom_data <= 6'h1A;
10'hDB: rom_data <= 6'h0B;
10'hDC: rom_data <= 6'h15;
10'hDD: rom_data <= 6'h02;
10'hDE: rom_data <= 6'h28;
10'hDF: rom_data <= 6'h28;
10'hE0: rom_data <= 6'h3A;
10'hE1: rom_data <= 6'h02;
10'hE2: rom_data <= 6'h2A;
10'hE3: rom_data <= 6'h13;
10'hE4: rom_data <= 6'h2D;
10'hE5: rom_data <= 6'h35;
10'hE6: rom_data <= 6'h3F;
10'hE7: rom_data <= 6'h06;
10'hE8: rom_data <= 6'h0D;
10'hE9: rom_data <= 6'h37;
10'hEA: rom_data <= 6'h02;
10'hEB: rom_data <= 6'h17;
10'hEC: rom_data <= 6'h23;
10'hED: rom_data <= 6'h02;
10'hEE: rom_data <= 6'h0E;
10'hEF: rom_data <= 6'h17;
10'hF0: rom_data <= 6'h10;
10'hF1: rom_data <= 6'h02;
10'hF2: rom_data <= 6'h04;
10'hF3: rom_data <= 6'h04;
10'hF4: rom_data <= 6'h04;
10'hF5: rom_data <= 6'h04;
10'hF6: rom_data <= 6'h10;
10'hF7: rom_data <= 6'h06;
10'hF8: rom_data <= 6'h02;
10'hF9: rom_data <= 6'h37;
10'hFA: rom_data <= 6'h37;
10'hFB: rom_data <= 6'h09;
10'hFC: rom_data <= 6'h13;
10'hFD: rom_data <= 6'h32;
10'hFE: rom_data <= 6'h02;
10'hFF: rom_data <= 6'h0C;
10'h100: rom_data <= 6'h2B;
10'h101: rom_data <= 6'h02;
10'h102: rom_data <= 6'h1C;
10'h103: rom_data <= 6'h14;
10'h104: rom_data <= 6'h37;
10'h105: rom_data <= 6'h0D;
10'h106: rom_data <= 6'h02;
10'h107: rom_data <= 6'h18;
10'h108: rom_data <= 6'h0B;
10'h109: rom_data <= 6'h02;
10'h10A: rom_data <= 6'h12;
10'h10B: rom_data <= 6'h07;
10'h10C: rom_data <= 6'h02;
10'h10D: rom_data <= 6'h08;
10'h10E: rom_data <= 6'h17;
10'h10F: rom_data <= 6'h2C;
10'h110: rom_data <= 6'h08;
10'h111: rom_data <= 6'h1A;
10'h112: rom_data <= 6'h0D;
10'h113: rom_data <= 6'h07;
10'h114: rom_data <= 6'h0B;
10'h115: rom_data <= 6'h14;
10'h116: rom_data <= 6'h32;
10'h117: rom_data <= 6'h1E;
10'h118: rom_data <= 6'h38;
10'h119: rom_data <= 6'h02;
10'h11A: rom_data <= 6'h17;
10'h11B: rom_data <= 6'h23;
10'h11C: rom_data <= 6'h02;
10'h11D: rom_data <= 6'h1A;
10'h11E: rom_data <= 6'h2D;
10'h11F: rom_data <= 6'h35;
10'h120: rom_data <= 6'h28;
10'h121: rom_data <= 6'h35;
10'h122: rom_data <= 6'h0B;
10'h123: rom_data <= 6'h37;
10'h124: rom_data <= 6'h03;
10'h125: rom_data <= 6'h04;
10'h126: rom_data <= 6'h04;
10'h127: rom_data <= 6'h12;
10'h128: rom_data <= 6'h07;
10'h129: rom_data <= 6'h02;
10'h12A: rom_data <= 6'h1B;
10'h12B: rom_data <= 6'h07;
10'h12C: rom_data <= 6'h07;
10'h12D: rom_data <= 6'h08;
10'h12E: rom_data <= 6'h37;
10'h12F: rom_data <= 6'h02;
10'h130: rom_data <= 6'h15;
10'h131: rom_data <= 6'h0C;
10'h132: rom_data <= 6'h0C;
10'h133: rom_data <= 6'h37;
10'h134: rom_data <= 6'h09;
10'h135: rom_data <= 6'h2D;
10'h136: rom_data <= 6'h14;
10'h137: rom_data <= 6'h02;
10'h138: rom_data <= 6'h25;
10'h139: rom_data <= 6'h35;
10'h13A: rom_data <= 6'h37;
10'h13B: rom_data <= 6'h02;
10'h13C: rom_data <= 6'h30;
10'h13D: rom_data <= 6'h0C;
10'h13E: rom_data <= 6'h32;
10'h13F: rom_data <= 6'h02;
10'h140: rom_data <= 6'h1A;
10'h141: rom_data <= 6'h2D;
10'h142: rom_data <= 6'h35;
10'h143: rom_data <= 6'h28;
10'h144: rom_data <= 6'h35;
10'h145: rom_data <= 6'h0B;
10'h146: rom_data <= 6'h03;
10'h147: rom_data <= 6'h0C;
10'h148: rom_data <= 6'h2B;
10'h149: rom_data <= 6'h02;
10'h14A: rom_data <= 6'h3F;
10'h14B: rom_data <= 6'h13;
10'h14C: rom_data <= 6'h0C;
10'h14D: rom_data <= 6'h2C;
10'h14E: rom_data <= 6'h02;
10'h14F: rom_data <= 6'h0A;
10'h150: rom_data <= 6'h07;
10'h151: rom_data <= 6'h0B;
10'h152: rom_data <= 6'h07;
10'h153: rom_data <= 6'h0E;
10'h154: rom_data <= 6'h14;
10'h155: rom_data <= 6'h02;
10'h156: rom_data <= 6'h0D;
10'h157: rom_data <= 6'h0C;
10'h158: rom_data <= 6'h15;
10'h159: rom_data <= 6'h02;
10'h15A: rom_data <= 6'h04;
10'h15B: rom_data <= 6'h04;
10'h15C: rom_data <= 6'h04;
10'h15D: rom_data <= 6'h04;
10'h15E: rom_data <= 6'h10;
10'h15F: rom_data <= 6'h06;
10'h160: rom_data <= 6'h02;
10'h161: rom_data <= 6'h20;
10'h162: rom_data <= 6'h15;
10'h163: rom_data <= 6'h13;
10'h164: rom_data <= 6'h35;
10'h165: rom_data <= 6'h02;
10'h166: rom_data <= 6'h20;
10'h167: rom_data <= 6'h0D;
10'h168: rom_data <= 6'h09;
10'h169: rom_data <= 6'h1E;
10'h16A: rom_data <= 6'h0D;
10'h16B: rom_data <= 6'h02;
10'h16C: rom_data <= 6'h31;
10'h16D: rom_data <= 6'h16;
10'h16E: rom_data <= 6'h2B;
10'h16F: rom_data <= 6'h07;
10'h170: rom_data <= 6'h2B;
10'h171: rom_data <= 6'h02;
10'h172: rom_data <= 6'h35;
10'h173: rom_data <= 6'h0B;
10'h174: rom_data <= 6'h2D;
10'h175: rom_data <= 6'h13;
10'h176: rom_data <= 6'h02;
10'h177: rom_data <= 6'h2E;
10'h178: rom_data <= 6'h0F;
10'h179: rom_data <= 6'h0B;
10'h17A: rom_data <= 6'h02;
10'h17B: rom_data <= 6'h15;
10'h17C: rom_data <= 6'h0C;
10'h17D: rom_data <= 6'h0A;
10'h17E: rom_data <= 6'h0C;
10'h17F: rom_data <= 6'h0D;
10'h180: rom_data <= 6'h0F;
10'h181: rom_data <= 6'h2D;
10'h182: rom_data <= 6'h02;
10'h183: rom_data <= 6'h09;
10'h184: rom_data <= 6'h0C;
10'h185: rom_data <= 6'h0C;
10'h186: rom_data <= 6'h0B;
10'h187: rom_data <= 6'h04;
10'h188: rom_data <= 6'h04;
10'h189: rom_data <= 6'h0F;
10'h18A: rom_data <= 6'h09;
10'h18B: rom_data <= 6'h3B;
10'h18C: rom_data <= 6'h0D;
10'h18D: rom_data <= 6'h02;
10'h18E: rom_data <= 6'h28;
10'h18F: rom_data <= 6'h27;
10'h190: rom_data <= 6'h17;
10'h191: rom_data <= 6'h10;
10'h192: rom_data <= 6'h02;
10'h193: rom_data <= 6'h0F;
10'h194: rom_data <= 6'h0B;
10'h195: rom_data <= 6'h02;
10'h196: rom_data <= 6'h3B;
10'h197: rom_data <= 6'h03;
10'h198: rom_data <= 6'h37;
10'h199: rom_data <= 6'h37;
10'h19A: rom_data <= 6'h13;
10'h19B: rom_data <= 6'h03;
10'h19C: rom_data <= 6'h28;
10'h19D: rom_data <= 6'h0C;
10'h19E: rom_data <= 6'h2D;
10'h19F: rom_data <= 6'h0D;
10'h1A0: rom_data <= 6'h33;
10'h1A1: rom_data <= 6'h04;
10'h1A2: rom_data <= 6'h0B;
10'h1A3: rom_data <= 6'h35;
10'h1A4: rom_data <= 6'h02;
10'h1A5: rom_data <= 6'h0F;
10'h1A6: rom_data <= 6'h0F;
10'h1A7: rom_data <= 6'h21;
10'h1A8: rom_data <= 6'h0C;
10'h1A9: rom_data <= 6'h32;
10'h1AA: rom_data <= 6'h0C;
10'h1AB: rom_data <= 6'h0B;
10'h1AC: rom_data <= 6'h1E;
10'h1AD: rom_data <= 6'h2D;
10'h1AE: rom_data <= 6'h02;
10'h1AF: rom_data <= 6'h13;
10'h1B0: rom_data <= 6'h2D;
10'h1B1: rom_data <= 6'h07;
10'h1B2: rom_data <= 6'h2A;
10'h1B3: rom_data <= 6'h0D;
10'h1B4: rom_data <= 6'h27;
10'h1B5: rom_data <= 6'h17;
10'h1B6: rom_data <= 6'h0B;
10'h1B7: rom_data <= 6'h0C;
10'h1B8: rom_data <= 6'h08;
10'h1B9: rom_data <= 6'h37;
10'h1BA: rom_data <= 6'h02;
10'h1BB: rom_data <= 6'h3B;
10'h1BC: rom_data <= 6'h02;
10'h1BD: rom_data <= 6'h0B;
10'h1BE: rom_data <= 6'h13;
10'h1BF: rom_data <= 6'h21;
10'h1C0: rom_data <= 6'h0C;
10'h1C1: rom_data <= 6'h15;
10'h1C2: rom_data <= 6'h02;
10'h1C3: rom_data <= 6'h04;
10'h1C4: rom_data <= 6'h04;
10'h1C5: rom_data <= 6'h04;
10'h1C6: rom_data <= 6'h04;
10'h1C7: rom_data <= 6'h0B;
10'h1C8: rom_data <= 6'h35;
10'h1C9: rom_data <= 6'h02;
10'h1CA: rom_data <= 6'h37;
10'h1CB: rom_data <= 6'h1A;
10'h1CC: rom_data <= 6'h10;
10'h1CD: rom_data <= 6'h09;
10'h1CE: rom_data <= 6'h3E;
10'h1CF: rom_data <= 6'h37;
10'h1D0: rom_data <= 6'h02;
10'h1D1: rom_data <= 6'h30;
10'h1D2: rom_data <= 6'h34;
10'h1D3: rom_data <= 6'h02;
10'h1D4: rom_data <= 6'h39;
10'h1D5: rom_data <= 6'h33;
10'h1D6: rom_data <= 6'h0D;
10'h1D7: rom_data <= 6'h02;
10'h1D8: rom_data <= 6'h0A;
10'h1D9: rom_data <= 6'h33;
10'h1DA: rom_data <= 6'h27;
10'h1DB: rom_data <= 6'h0C;
10'h1DC: rom_data <= 6'h2C;
10'h1DD: rom_data <= 6'h02;
10'h1DE: rom_data <= 6'h12;
10'h1DF: rom_data <= 6'h07;
10'h1E0: rom_data <= 6'h02;
10'h1E1: rom_data <= 6'h10;
10'h1E2: rom_data <= 6'h14;
10'h1E3: rom_data <= 6'h29;
10'h1E4: rom_data <= 6'h0C;
10'h1E5: rom_data <= 6'h2C;
10'h1E6: rom_data <= 6'h02;
10'h1E7: rom_data <= 6'h17;
10'h1E8: rom_data <= 6'h23;
10'h1E9: rom_data <= 6'h02;
10'h1EA: rom_data <= 6'h12;
10'h1EB: rom_data <= 6'h0C;
10'h1EC: rom_data <= 6'h37;
10'h1ED: rom_data <= 6'h02;
10'h1EE: rom_data <= 6'h23;
10'h1EF: rom_data <= 6'h0C;
10'h1F0: rom_data <= 6'h21;
10'h1F1: rom_data <= 6'h13;
10'h1F2: rom_data <= 6'h35;
10'h1F3: rom_data <= 6'h02;
10'h1F4: rom_data <= 6'h04;
10'h1F5: rom_data <= 6'h04;
10'h1F6: rom_data <= 6'h04;
10'h1F7: rom_data <= 6'h04;
10'h1F8: rom_data <= 6'h04;
10'h1F9: rom_data <= 6'h04;
10'h1FA: rom_data <= 6'h04;
10'h1FB: rom_data <= 6'h04;
10'h1FC: rom_data <= 6'h1D;
10'h1FD: rom_data <= 6'h1A;
10'h1FE: rom_data <= 6'h0B;
10'h1FF: rom_data <= 6'h2A;
10'h200: rom_data <= 6'h02;
10'h201: rom_data <= 6'h19;
10'h202: rom_data <= 6'h1F;
10'h203: rom_data <= 6'h02;
10'h204: rom_data <= 6'h28;
10'h205: rom_data <= 6'h28;
10'h206: rom_data <= 6'h3A;
10'h207: rom_data <= 6'h02;
10'h208: rom_data <= 6'h19;
10'h209: rom_data <= 6'h3A;
10'h20A: rom_data <= 6'h02;
10'h20B: rom_data <= 6'h0C;
10'h20C: rom_data <= 6'h0B;
10'h20D: rom_data <= 6'h0D;
10'h20E: rom_data <= 6'h33;
10'h20F: rom_data <= 6'h07;
10'h210: rom_data <= 6'h37;
10'h211: rom_data <= 6'h0D;
10'h212: rom_data <= 6'h02;
10'h213: rom_data <= 6'h1A;
10'h214: rom_data <= 6'h0B;
10'h215: rom_data <= 6'h15;
10'h216: rom_data <= 6'h02;
10'h217: rom_data <= 6'h2A;
10'h218: rom_data <= 6'h13;
10'h219: rom_data <= 6'h09;
10'h21A: rom_data <= 6'h02;
10'h21B: rom_data <= 6'h0C;
10'h21C: rom_data <= 6'h0D;
10'h21D: rom_data <= 6'h03;
10'h21E: rom_data <= 6'h0E;
10'h21F: rom_data <= 6'h07;
10'h220: rom_data <= 6'h0D;
10'h221: rom_data <= 6'h0E;
10'h222: rom_data <= 6'h35;
10'h223: rom_data <= 6'h04;
10'h224: rom_data <= 6'h04;
10'h225: rom_data <= 6'h04;
10'h226: rom_data <= 6'h04;
10'h227: rom_data <= 6'h04;
10'h228: rom_data <= 6'h04;
10'h229: rom_data <= 6'h04;
10'h22A: rom_data <= 6'h04;
10'h22B: rom_data <= 6'h04;
10'h22C: rom_data <= 6'h04;
10'h22D: rom_data <= 6'h04;
10'h22E: rom_data <= 6'h04;
default: rom_data <= 6'h00;
endcase
end
`endif
endmodule | module Speech256_DE0 (
CLOCK_50,
UART_TXD,
); |
input CLOCK_50;
output UART_TXD;
reg [5:0] data_in;
reg data_stb;
reg clk;
reg [3:0] divcnt;
reg [2:0] cur_state, next_state;
reg [9:0] rom_addr;
reg [5:0] rom_data;
reg inc_rom_addr;
wire sample_stb;
wire signed [15:0] sample_out;
wire ldq;
wire rst_an;
SPEECH256_TOP u_speech256_top (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (rom_data),
.data_stb (data_stb),
.pwm_out (UART_TXD),
.sample_out (sample_out),
.sample_stb (sample_stb)
);
assign rst_an = 1'b1;
parameter S_IDLE = 4'b000,
S_ALLOPHONE = 4'b001,
S_WAITDONE = 4'b010;
always @(posedge CLOCK_50)
begin
if (divcnt > 9)
begin
clk <= !clk;
divcnt <= 0;
end
else
begin
divcnt <= divcnt + 1;
end
end
always @(posedge clk)
begin
cur_state <= next_state;
if (inc_rom_addr == 1)
rom_addr <= rom_addr + 1;
end
always @(*)
begin
data_stb <= 0;
inc_rom_addr <= 0;
next_state <= cur_state;
case(cur_state)
S_IDLE:
begin
if (ldq == 1)
begin
inc_rom_addr <= 1;
next_state <= S_ALLOPHONE;
end
else
next_state <= S_IDLE;
end
S_ALLOPHONE:
begin
data_stb <= 1;
next_state <= S_WAITDONE;
end
S_WAITDONE:
begin
if (ldq == 0)
begin
next_state <= S_IDLE;
end
end
default:
begin
next_state <= S_IDLE;
end
endcase
`ifdef HELLO_WORLD
case (rom_addr)
4'd0:
rom_data <= 6'h1B;
4'd1:
rom_data <= 6'h07;
4'd2:
rom_data <= 6'h2D;
4'd3:
rom_data <= 6'h35;
4'd4:
rom_data <= 6'h03;
4'd5:
rom_data <= 6'h2E;
4'd6:
rom_data <= 6'h1E;
4'd7:
rom_data <= 6'h33;
4'd8:
rom_data <= 6'h2D;
4'd9:
rom_data <= 6'h15;
4'd10:
rom_data <= 6'h03;
default:
rom_data <= 6'h03;
endcase
end
`endif
`ifdef TEST1
case (rom_addr)
8'h00: rom_data <= 6'h21;
8'h01: rom_data <= 6'h14;
8'h02: rom_data <= 6'h00;
8'h03: rom_data <= 6'h2B;
8'h04: rom_data <= 6'h13;
8'h05: rom_data <= 6'h04;
8'h06: rom_data <= 6'h21;
8'h07: rom_data <= 6'h14;
8'h08: rom_data <= 6'h00;
8'h09: rom_data <= 6'h2B;
8'h0A: rom_data <= 6'h13;
8'h0B: rom_data <= 6'h03;
8'h0C: rom_data <= 6'h0D;
8'h0D: rom_data <= 6'h3E;
8'h0E: rom_data <= 6'h2D;
8'h0F: rom_data <= 6'h02;
8'h10: rom_data <= 6'h10;
8'h11: rom_data <= 6'h13;
8'h12: rom_data <= 6'h02;
8'h13: rom_data <= 6'h0D;
8'h14: rom_data <= 6'h27;
8'h15: rom_data <= 6'h16;
8'h16: rom_data <= 6'h04;
8'h17: rom_data <= 6'h06;
8'h18: rom_data <= 6'h10;
8'h19: rom_data <= 6'h02;
8'h1A: rom_data <= 6'h18;
8'h1B: rom_data <= 6'h28;
8'h1C: rom_data <= 6'h27;
8'h1D: rom_data <= 6'h14;
8'h1E: rom_data <= 6'h15;
8'h1F: rom_data <= 6'h03;
8'h20: rom_data <= 6'h06;
8'h21: rom_data <= 6'h02;
8'h22: rom_data <= 6'h2A;
8'h23: rom_data <= 6'h1A;
8'h24: rom_data <= 6'h0B;
8'h25: rom_data <= 6'h11;
8'h26: rom_data <= 6'h03;
8'h27: rom_data <= 6'h21;
8'h28: rom_data <= 6'h1F;
8'h29: rom_data <= 6'h02;
8'h2A: rom_data <= 6'h1D;
8'h2B: rom_data <= 6'h1A;
8'h2C: rom_data <= 6'h0D;
8'h2D: rom_data <= 6'h04;
8'h2E: rom_data <= 6'h21;
8'h2F: rom_data <= 6'h14;
8'h30: rom_data <= 6'h23;
8'h31: rom_data <= 6'h04;
8'h32: rom_data <= 6'h19;
8'h33: rom_data <= 6'h07;
8'h34: rom_data <= 6'h07;
8'h35: rom_data <= 6'h37;
8'h36: rom_data <= 6'h37;
8'h37: rom_data <= 6'h02;
8'h38: rom_data <= 6'h1A;
8'h39: rom_data <= 6'h0B;
8'h3A: rom_data <= 6'h15;
8'h3B: rom_data <= 6'h03;
8'h3C: rom_data <= 6'h38;
8'h3D: rom_data <= 6'h0F;
8'h3E: rom_data <= 6'h35;
8'h3F: rom_data <= 6'h04;
8'h40: rom_data <= 6'h2B;
8'h41: rom_data <= 6'h3C;
8'h42: rom_data <= 6'h35;
8'h43: rom_data <= 6'h03;
8'h44: rom_data <= 6'h2E;
8'h45: rom_data <= 6'h0F;
8'h46: rom_data <= 6'h0F;
8'h47: rom_data <= 6'h0B;
8'h48: rom_data <= 6'h03;
8'h49: rom_data <= 6'h0D;
8'h4A: rom_data <= 6'h1F;
8'h4B: rom_data <= 6'h03;
8'h4C: rom_data <= 6'h1D;
8'h4D: rom_data <= 6'h0E;
8'h4E: rom_data <= 6'h13;
8'h4F: rom_data <= 6'h03;
8'h50: rom_data <= 6'h28;
8'h51: rom_data <= 6'h28;
8'h52: rom_data <= 6'h3A;
8'h53: rom_data <= 6'h03;
8'h54: rom_data <= 6'h28;
8'h55: rom_data <= 6'h28;
8'h56: rom_data <= 6'h06;
8'h57: rom_data <= 6'h23;
8'h58: rom_data <= 6'h03;
8'h59: rom_data <= 6'h37;
8'h5A: rom_data <= 6'h37;
8'h5B: rom_data <= 6'h0C;
8'h5C: rom_data <= 6'h1E;
8'h5D: rom_data <= 6'h02;
8'h5E: rom_data <= 6'h29;
8'h5F: rom_data <= 6'h37;
8'h60: rom_data <= 6'h03;
8'h61: rom_data <= 6'h37;
8'h62: rom_data <= 6'h37;
8'h63: rom_data <= 6'h07;
8'h64: rom_data <= 6'h07;
8'h65: rom_data <= 6'h23;
8'h66: rom_data <= 6'h0C;
8'h67: rom_data <= 6'h0B;
8'h68: rom_data <= 6'h03;
8'h69: rom_data <= 6'h14;
8'h6A: rom_data <= 6'h02;
8'h6B: rom_data <= 6'h0D;
8'h6C: rom_data <= 6'h03;
8'h6D: rom_data <= 6'h0B;
8'h6E: rom_data <= 6'h06;
8'h6F: rom_data <= 6'h0B;
8'h70: rom_data <= 6'h03;
8'h71: rom_data <= 6'h0D;
8'h72: rom_data <= 6'h07;
8'h73: rom_data <= 6'h07;
8'h74: rom_data <= 6'h0B;
8'h75: rom_data <= 6'h04;
8'h76: rom_data <= 6'h13;
8'h77: rom_data <= 6'h02;
8'h78: rom_data <= 6'h0D;
8'h79: rom_data <= 6'h13;
8'h7A: rom_data <= 6'h03;
8'h7B: rom_data <= 6'h28;
8'h7C: rom_data <= 6'h28;
8'h7D: rom_data <= 6'h35;
8'h7E: rom_data <= 6'h0B;
8'h7F: rom_data <= 6'h02;
8'h80: rom_data <= 6'h39;
8'h81: rom_data <= 6'h35;
8'h82: rom_data <= 6'h10;
8'h83: rom_data <= 6'h10;
8'h84: rom_data <= 6'h04;
default: rom_data <= 6'h00;
endcase
end
`endif
`ifdef YOUTUBE_MESSAGE
case (rom_addr)
10'h00: rom_data <= 6'h3D;
10'h01: rom_data <= 6'h27;
10'h02: rom_data <= 6'h13;
10'h03: rom_data <= 6'h0D;
10'h04: rom_data <= 6'h0C;
10'h05: rom_data <= 6'h2C;
10'h06: rom_data <= 6'h37;
10'h07: rom_data <= 6'h04;
10'h08: rom_data <= 6'h09;
10'h09: rom_data <= 6'h13;
10'h0A: rom_data <= 6'h09;
10'h0B: rom_data <= 6'h3E;
10'h0C: rom_data <= 6'h02;
10'h0D: rom_data <= 6'h17;
10'h0E: rom_data <= 6'h23;
10'h0F: rom_data <= 6'h02;
10'h10: rom_data <= 6'h33;
10'h11: rom_data <= 6'h1D;
10'h12: rom_data <= 6'h1D;
10'h13: rom_data <= 6'h02;
10'h14: rom_data <= 6'h04;
10'h15: rom_data <= 6'h04;
10'h16: rom_data <= 6'h04;
10'h17: rom_data <= 6'h04;
10'h18: rom_data <= 6'h06;
10'h19: rom_data <= 6'h02;
10'h1A: rom_data <= 6'h1A;
10'h1B: rom_data <= 6'h10;
10'h1C: rom_data <= 6'h02;
10'h1D: rom_data <= 6'h37;
10'h1E: rom_data <= 6'h37;
10'h1F: rom_data <= 6'h09;
10'h20: rom_data <= 6'h13;
10'h21: rom_data <= 6'h32;
10'h22: rom_data <= 6'h0D;
10'h23: rom_data <= 6'h1F;
10'h24: rom_data <= 6'h01;
10'h25: rom_data <= 6'h28;
10'h26: rom_data <= 6'h28;
10'h27: rom_data <= 6'h0C;
10'h28: rom_data <= 6'h28;
10'h29: rom_data <= 6'h28;
10'h2A: rom_data <= 6'h01;
10'h2B: rom_data <= 6'h0D;
10'h2C: rom_data <= 6'h13;
10'h2D: rom_data <= 6'h37;
10'h2E: rom_data <= 6'h37;
10'h2F: rom_data <= 6'h0C;
10'h30: rom_data <= 6'h0C;
10'h31: rom_data <= 6'h02;
10'h32: rom_data <= 6'h29;
10'h33: rom_data <= 6'h37;
10'h34: rom_data <= 6'h04;
10'h35: rom_data <= 6'h04;
10'h36: rom_data <= 6'h0F;
10'h37: rom_data <= 6'h0B;
10'h38: rom_data <= 6'h02;
10'h39: rom_data <= 6'h07;
10'h3A: rom_data <= 6'h07;
10'h3B: rom_data <= 6'h28;
10'h3C: rom_data <= 6'h28;
10'h3D: rom_data <= 6'h02;
10'h3E: rom_data <= 6'h09;
10'h3F: rom_data <= 6'h13;
10'h40: rom_data <= 6'h02;
10'h41: rom_data <= 6'h0A;
10'h42: rom_data <= 6'h13;
10'h43: rom_data <= 6'h02;
10'h44: rom_data <= 6'h14;
10'h45: rom_data <= 6'h02;
10'h46: rom_data <= 6'h0C;
10'h47: rom_data <= 6'h10;
10'h48: rom_data <= 6'h01;
10'h49: rom_data <= 6'h09;
10'h4A: rom_data <= 6'h2D;
10'h4B: rom_data <= 6'h07;
10'h4C: rom_data <= 6'h10;
10'h4D: rom_data <= 6'h07;
10'h4E: rom_data <= 6'h0B;
10'h4F: rom_data <= 6'h0D;
10'h50: rom_data <= 6'h14;
10'h51: rom_data <= 6'h32;
10'h52: rom_data <= 6'h1E;
10'h53: rom_data <= 6'h0B;
10'h54: rom_data <= 6'h03;
10'h55: rom_data <= 6'h17;
10'h56: rom_data <= 6'h23;
10'h57: rom_data <= 6'h02;
10'h58: rom_data <= 6'h0F;
10'h59: rom_data <= 6'h0B;
10'h5A: rom_data <= 6'h02;
10'h5B: rom_data <= 6'h14;
10'h5C: rom_data <= 6'h02;
10'h5D: rom_data <= 6'h0D;
10'h5E: rom_data <= 6'h13;
10'h5F: rom_data <= 6'h2B;
10'h60: rom_data <= 6'h02;
10'h61: rom_data <= 6'h37;
10'h62: rom_data <= 6'h37;
10'h63: rom_data <= 6'h09;
10'h64: rom_data <= 6'h13;
10'h65: rom_data <= 6'h32;
10'h66: rom_data <= 6'h02;
10'h67: rom_data <= 6'h37;
10'h68: rom_data <= 6'h0C;
10'h69: rom_data <= 6'h0B;
10'h6A: rom_data <= 6'h1D;
10'h6B: rom_data <= 6'h07;
10'h6C: rom_data <= 6'h37;
10'h6D: rom_data <= 6'h18;
10'h6E: rom_data <= 6'h06;
10'h6F: rom_data <= 6'h2B;
10'h70: rom_data <= 6'h33;
10'h71: rom_data <= 6'h02;
10'h72: rom_data <= 6'h32;
10'h73: rom_data <= 6'h0C;
10'h74: rom_data <= 6'h0C;
10'h75: rom_data <= 6'h09;
10'h76: rom_data <= 6'h04;
10'h77: rom_data <= 6'h04;
10'h78: rom_data <= 6'h04;
10'h79: rom_data <= 6'h04;
10'h7A: rom_data <= 6'h04;
10'h7B: rom_data <= 6'h06;
10'h7C: rom_data <= 6'h02;
10'h7D: rom_data <= 6'h2A;
10'h7E: rom_data <= 6'h33;
10'h7F: rom_data <= 6'h07;
10'h80: rom_data <= 6'h0D;
10'h81: rom_data <= 6'h2D;
10'h82: rom_data <= 6'h13;
10'h83: rom_data <= 6'h02;
10'h84: rom_data <= 6'h2D;
10'h85: rom_data <= 6'h0C;
10'h86: rom_data <= 6'h23;
10'h87: rom_data <= 6'h02;
10'h88: rom_data <= 6'h18;
10'h89: rom_data <= 6'h0B;
10'h8A: rom_data <= 6'h02;
10'h8B: rom_data <= 6'h0F;
10'h8C: rom_data <= 6'h02;
10'h8D: rom_data <= 6'h15;
10'h8E: rom_data <= 6'h0C;
10'h8F: rom_data <= 6'h0C;
10'h90: rom_data <= 6'h0A;
10'h91: rom_data <= 6'h02;
10'h92: rom_data <= 6'h0C;
10'h93: rom_data <= 6'h2D;
10'h94: rom_data <= 6'h07;
10'h95: rom_data <= 6'h07;
10'h96: rom_data <= 6'h0B;
10'h97: rom_data <= 6'h0D;
10'h98: rom_data <= 6'h03;
10'h99: rom_data <= 6'h21;
10'h9A: rom_data <= 6'h13;
10'h9B: rom_data <= 6'h02;
10'h9C: rom_data <= 6'h13;
10'h9D: rom_data <= 6'h02;
10'h9E: rom_data <= 6'h2B;
10'h9F: rom_data <= 6'h3C;
10'hA0: rom_data <= 6'h35;
10'hA1: rom_data <= 6'h02;
10'hA2: rom_data <= 6'h1C;
10'hA3: rom_data <= 6'h3A;
10'hA4: rom_data <= 6'h15;
10'hA5: rom_data <= 6'h04;
10'hA6: rom_data <= 6'h04;
10'hA7: rom_data <= 6'h1A;
10'hA8: rom_data <= 6'h0B;
10'hA9: rom_data <= 6'h15;
10'hAA: rom_data <= 6'h02;
10'hAB: rom_data <= 6'h06;
10'hAC: rom_data <= 6'h03;
10'hAD: rom_data <= 6'h31;
10'hAE: rom_data <= 6'h16;
10'hAF: rom_data <= 6'h2B;
10'hB0: rom_data <= 6'h03;
10'hB1: rom_data <= 6'h0F;
10'hB2: rom_data <= 6'h3F;
10'hB3: rom_data <= 6'h20;
10'hB4: rom_data <= 6'h0D;
10'hB5: rom_data <= 6'h02;
10'hB6: rom_data <= 6'h37;
10'hB7: rom_data <= 6'h37;
10'hB8: rom_data <= 6'h07;
10'hB9: rom_data <= 6'h07;
10'hBA: rom_data <= 6'h23;
10'hBB: rom_data <= 6'h0C;
10'hBC: rom_data <= 6'h0B;
10'hBD: rom_data <= 6'h02;
10'hBE: rom_data <= 6'h39;
10'hBF: rom_data <= 6'h0F;
10'hC0: rom_data <= 6'h0F;
10'hC1: rom_data <= 6'h0B;
10'hC2: rom_data <= 6'h01;
10'hC3: rom_data <= 6'h21;
10'hC4: rom_data <= 6'h27;
10'hC5: rom_data <= 6'h0C;
10'hC6: rom_data <= 6'h0C;
10'hC7: rom_data <= 6'h00;
10'hC8: rom_data <= 6'h15;
10'hC9: rom_data <= 6'h03;
10'hCA: rom_data <= 6'h2D;
10'hCB: rom_data <= 6'h17;
10'hCC: rom_data <= 6'h0A;
10'hCD: rom_data <= 6'h0C;
10'hCE: rom_data <= 6'h0C;
10'hCF: rom_data <= 6'h29;
10'hD0: rom_data <= 6'h02;
10'hD1: rom_data <= 6'h07;
10'hD2: rom_data <= 6'h2D;
10'hD3: rom_data <= 6'h07;
10'hD4: rom_data <= 6'h10;
10'hD5: rom_data <= 6'h07;
10'hD6: rom_data <= 6'h0B;
10'hD7: rom_data <= 6'h0D;
10'hD8: rom_data <= 6'h37;
10'hD9: rom_data <= 6'h03;
10'hDA: rom_data <= 6'h1A;
10'hDB: rom_data <= 6'h0B;
10'hDC: rom_data <= 6'h15;
10'hDD: rom_data <= 6'h02;
10'hDE: rom_data <= 6'h28;
10'hDF: rom_data <= 6'h28;
10'hE0: rom_data <= 6'h3A;
10'hE1: rom_data <= 6'h02;
10'hE2: rom_data <= 6'h2A;
10'hE3: rom_data <= 6'h13;
10'hE4: rom_data <= 6'h2D;
10'hE5: rom_data <= 6'h35;
10'hE6: rom_data <= 6'h3F;
10'hE7: rom_data <= 6'h06;
10'hE8: rom_data <= 6'h0D;
10'hE9: rom_data <= 6'h37;
10'hEA: rom_data <= 6'h02;
10'hEB: rom_data <= 6'h17;
10'hEC: rom_data <= 6'h23;
10'hED: rom_data <= 6'h02;
10'hEE: rom_data <= 6'h0E;
10'hEF: rom_data <= 6'h17;
10'hF0: rom_data <= 6'h10;
10'hF1: rom_data <= 6'h02;
10'hF2: rom_data <= 6'h04;
10'hF3: rom_data <= 6'h04;
10'hF4: rom_data <= 6'h04;
10'hF5: rom_data <= 6'h04;
10'hF6: rom_data <= 6'h10;
10'hF7: rom_data <= 6'h06;
10'hF8: rom_data <= 6'h02;
10'hF9: rom_data <= 6'h37;
10'hFA: rom_data <= 6'h37;
10'hFB: rom_data <= 6'h09;
10'hFC: rom_data <= 6'h13;
10'hFD: rom_data <= 6'h32;
10'hFE: rom_data <= 6'h02;
10'hFF: rom_data <= 6'h0C;
10'h100: rom_data <= 6'h2B;
10'h101: rom_data <= 6'h02;
10'h102: rom_data <= 6'h1C;
10'h103: rom_data <= 6'h14;
10'h104: rom_data <= 6'h37;
10'h105: rom_data <= 6'h0D;
10'h106: rom_data <= 6'h02;
10'h107: rom_data <= 6'h18;
10'h108: rom_data <= 6'h0B;
10'h109: rom_data <= 6'h02;
10'h10A: rom_data <= 6'h12;
10'h10B: rom_data <= 6'h07;
10'h10C: rom_data <= 6'h02;
10'h10D: rom_data <= 6'h08;
10'h10E: rom_data <= 6'h17;
10'h10F: rom_data <= 6'h2C;
10'h110: rom_data <= 6'h08;
10'h111: rom_data <= 6'h1A;
10'h112: rom_data <= 6'h0D;
10'h113: rom_data <= 6'h07;
10'h114: rom_data <= 6'h0B;
10'h115: rom_data <= 6'h14;
10'h116: rom_data <= 6'h32;
10'h117: rom_data <= 6'h1E;
10'h118: rom_data <= 6'h38;
10'h119: rom_data <= 6'h02;
10'h11A: rom_data <= 6'h17;
10'h11B: rom_data <= 6'h23;
10'h11C: rom_data <= 6'h02;
10'h11D: rom_data <= 6'h1A;
10'h11E: rom_data <= 6'h2D;
10'h11F: rom_data <= 6'h35;
10'h120: rom_data <= 6'h28;
10'h121: rom_data <= 6'h35;
10'h122: rom_data <= 6'h0B;
10'h123: rom_data <= 6'h37;
10'h124: rom_data <= 6'h03;
10'h125: rom_data <= 6'h04;
10'h126: rom_data <= 6'h04;
10'h127: rom_data <= 6'h12;
10'h128: rom_data <= 6'h07;
10'h129: rom_data <= 6'h02;
10'h12A: rom_data <= 6'h1B;
10'h12B: rom_data <= 6'h07;
10'h12C: rom_data <= 6'h07;
10'h12D: rom_data <= 6'h08;
10'h12E: rom_data <= 6'h37;
10'h12F: rom_data <= 6'h02;
10'h130: rom_data <= 6'h15;
10'h131: rom_data <= 6'h0C;
10'h132: rom_data <= 6'h0C;
10'h133: rom_data <= 6'h37;
10'h134: rom_data <= 6'h09;
10'h135: rom_data <= 6'h2D;
10'h136: rom_data <= 6'h14;
10'h137: rom_data <= 6'h02;
10'h138: rom_data <= 6'h25;
10'h139: rom_data <= 6'h35;
10'h13A: rom_data <= 6'h37;
10'h13B: rom_data <= 6'h02;
10'h13C: rom_data <= 6'h30;
10'h13D: rom_data <= 6'h0C;
10'h13E: rom_data <= 6'h32;
10'h13F: rom_data <= 6'h02;
10'h140: rom_data <= 6'h1A;
10'h141: rom_data <= 6'h2D;
10'h142: rom_data <= 6'h35;
10'h143: rom_data <= 6'h28;
10'h144: rom_data <= 6'h35;
10'h145: rom_data <= 6'h0B;
10'h146: rom_data <= 6'h03;
10'h147: rom_data <= 6'h0C;
10'h148: rom_data <= 6'h2B;
10'h149: rom_data <= 6'h02;
10'h14A: rom_data <= 6'h3F;
10'h14B: rom_data <= 6'h13;
10'h14C: rom_data <= 6'h0C;
10'h14D: rom_data <= 6'h2C;
10'h14E: rom_data <= 6'h02;
10'h14F: rom_data <= 6'h0A;
10'h150: rom_data <= 6'h07;
10'h151: rom_data <= 6'h0B;
10'h152: rom_data <= 6'h07;
10'h153: rom_data <= 6'h0E;
10'h154: rom_data <= 6'h14;
10'h155: rom_data <= 6'h02;
10'h156: rom_data <= 6'h0D;
10'h157: rom_data <= 6'h0C;
10'h158: rom_data <= 6'h15;
10'h159: rom_data <= 6'h02;
10'h15A: rom_data <= 6'h04;
10'h15B: rom_data <= 6'h04;
10'h15C: rom_data <= 6'h04;
10'h15D: rom_data <= 6'h04;
10'h15E: rom_data <= 6'h10;
10'h15F: rom_data <= 6'h06;
10'h160: rom_data <= 6'h02;
10'h161: rom_data <= 6'h20;
10'h162: rom_data <= 6'h15;
10'h163: rom_data <= 6'h13;
10'h164: rom_data <= 6'h35;
10'h165: rom_data <= 6'h02;
10'h166: rom_data <= 6'h20;
10'h167: rom_data <= 6'h0D;
10'h168: rom_data <= 6'h09;
10'h169: rom_data <= 6'h1E;
10'h16A: rom_data <= 6'h0D;
10'h16B: rom_data <= 6'h02;
10'h16C: rom_data <= 6'h31;
10'h16D: rom_data <= 6'h16;
10'h16E: rom_data <= 6'h2B;
10'h16F: rom_data <= 6'h07;
10'h170: rom_data <= 6'h2B;
10'h171: rom_data <= 6'h02;
10'h172: rom_data <= 6'h35;
10'h173: rom_data <= 6'h0B;
10'h174: rom_data <= 6'h2D;
10'h175: rom_data <= 6'h13;
10'h176: rom_data <= 6'h02;
10'h177: rom_data <= 6'h2E;
10'h178: rom_data <= 6'h0F;
10'h179: rom_data <= 6'h0B;
10'h17A: rom_data <= 6'h02;
10'h17B: rom_data <= 6'h15;
10'h17C: rom_data <= 6'h0C;
10'h17D: rom_data <= 6'h0A;
10'h17E: rom_data <= 6'h0C;
10'h17F: rom_data <= 6'h0D;
10'h180: rom_data <= 6'h0F;
10'h181: rom_data <= 6'h2D;
10'h182: rom_data <= 6'h02;
10'h183: rom_data <= 6'h09;
10'h184: rom_data <= 6'h0C;
10'h185: rom_data <= 6'h0C;
10'h186: rom_data <= 6'h0B;
10'h187: rom_data <= 6'h04;
10'h188: rom_data <= 6'h04;
10'h189: rom_data <= 6'h0F;
10'h18A: rom_data <= 6'h09;
10'h18B: rom_data <= 6'h3B;
10'h18C: rom_data <= 6'h0D;
10'h18D: rom_data <= 6'h02;
10'h18E: rom_data <= 6'h28;
10'h18F: rom_data <= 6'h27;
10'h190: rom_data <= 6'h17;
10'h191: rom_data <= 6'h10;
10'h192: rom_data <= 6'h02;
10'h193: rom_data <= 6'h0F;
10'h194: rom_data <= 6'h0B;
10'h195: rom_data <= 6'h02;
10'h196: rom_data <= 6'h3B;
10'h197: rom_data <= 6'h03;
10'h198: rom_data <= 6'h37;
10'h199: rom_data <= 6'h37;
10'h19A: rom_data <= 6'h13;
10'h19B: rom_data <= 6'h03;
10'h19C: rom_data <= 6'h28;
10'h19D: rom_data <= 6'h0C;
10'h19E: rom_data <= 6'h2D;
10'h19F: rom_data <= 6'h0D;
10'h1A0: rom_data <= 6'h33;
10'h1A1: rom_data <= 6'h04;
10'h1A2: rom_data <= 6'h0B;
10'h1A3: rom_data <= 6'h35;
10'h1A4: rom_data <= 6'h02;
10'h1A5: rom_data <= 6'h0F;
10'h1A6: rom_data <= 6'h0F;
10'h1A7: rom_data <= 6'h21;
10'h1A8: rom_data <= 6'h0C;
10'h1A9: rom_data <= 6'h32;
10'h1AA: rom_data <= 6'h0C;
10'h1AB: rom_data <= 6'h0B;
10'h1AC: rom_data <= 6'h1E;
10'h1AD: rom_data <= 6'h2D;
10'h1AE: rom_data <= 6'h02;
10'h1AF: rom_data <= 6'h13;
10'h1B0: rom_data <= 6'h2D;
10'h1B1: rom_data <= 6'h07;
10'h1B2: rom_data <= 6'h2A;
10'h1B3: rom_data <= 6'h0D;
10'h1B4: rom_data <= 6'h27;
10'h1B5: rom_data <= 6'h17;
10'h1B6: rom_data <= 6'h0B;
10'h1B7: rom_data <= 6'h0C;
10'h1B8: rom_data <= 6'h08;
10'h1B9: rom_data <= 6'h37;
10'h1BA: rom_data <= 6'h02;
10'h1BB: rom_data <= 6'h3B;
10'h1BC: rom_data <= 6'h02;
10'h1BD: rom_data <= 6'h0B;
10'h1BE: rom_data <= 6'h13;
10'h1BF: rom_data <= 6'h21;
10'h1C0: rom_data <= 6'h0C;
10'h1C1: rom_data <= 6'h15;
10'h1C2: rom_data <= 6'h02;
10'h1C3: rom_data <= 6'h04;
10'h1C4: rom_data <= 6'h04;
10'h1C5: rom_data <= 6'h04;
10'h1C6: rom_data <= 6'h04;
10'h1C7: rom_data <= 6'h0B;
10'h1C8: rom_data <= 6'h35;
10'h1C9: rom_data <= 6'h02;
10'h1CA: rom_data <= 6'h37;
10'h1CB: rom_data <= 6'h1A;
10'h1CC: rom_data <= 6'h10;
10'h1CD: rom_data <= 6'h09;
10'h1CE: rom_data <= 6'h3E;
10'h1CF: rom_data <= 6'h37;
10'h1D0: rom_data <= 6'h02;
10'h1D1: rom_data <= 6'h30;
10'h1D2: rom_data <= 6'h34;
10'h1D3: rom_data <= 6'h02;
10'h1D4: rom_data <= 6'h39;
10'h1D5: rom_data <= 6'h33;
10'h1D6: rom_data <= 6'h0D;
10'h1D7: rom_data <= 6'h02;
10'h1D8: rom_data <= 6'h0A;
10'h1D9: rom_data <= 6'h33;
10'h1DA: rom_data <= 6'h27;
10'h1DB: rom_data <= 6'h0C;
10'h1DC: rom_data <= 6'h2C;
10'h1DD: rom_data <= 6'h02;
10'h1DE: rom_data <= 6'h12;
10'h1DF: rom_data <= 6'h07;
10'h1E0: rom_data <= 6'h02;
10'h1E1: rom_data <= 6'h10;
10'h1E2: rom_data <= 6'h14;
10'h1E3: rom_data <= 6'h29;
10'h1E4: rom_data <= 6'h0C;
10'h1E5: rom_data <= 6'h2C;
10'h1E6: rom_data <= 6'h02;
10'h1E7: rom_data <= 6'h17;
10'h1E8: rom_data <= 6'h23;
10'h1E9: rom_data <= 6'h02;
10'h1EA: rom_data <= 6'h12;
10'h1EB: rom_data <= 6'h0C;
10'h1EC: rom_data <= 6'h37;
10'h1ED: rom_data <= 6'h02;
10'h1EE: rom_data <= 6'h23;
10'h1EF: rom_data <= 6'h0C;
10'h1F0: rom_data <= 6'h21;
10'h1F1: rom_data <= 6'h13;
10'h1F2: rom_data <= 6'h35;
10'h1F3: rom_data <= 6'h02;
10'h1F4: rom_data <= 6'h04;
10'h1F5: rom_data <= 6'h04;
10'h1F6: rom_data <= 6'h04;
10'h1F7: rom_data <= 6'h04;
10'h1F8: rom_data <= 6'h04;
10'h1F9: rom_data <= 6'h04;
10'h1FA: rom_data <= 6'h04;
10'h1FB: rom_data <= 6'h04;
10'h1FC: rom_data <= 6'h1D;
10'h1FD: rom_data <= 6'h1A;
10'h1FE: rom_data <= 6'h0B;
10'h1FF: rom_data <= 6'h2A;
10'h200: rom_data <= 6'h02;
10'h201: rom_data <= 6'h19;
10'h202: rom_data <= 6'h1F;
10'h203: rom_data <= 6'h02;
10'h204: rom_data <= 6'h28;
10'h205: rom_data <= 6'h28;
10'h206: rom_data <= 6'h3A;
10'h207: rom_data <= 6'h02;
10'h208: rom_data <= 6'h19;
10'h209: rom_data <= 6'h3A;
10'h20A: rom_data <= 6'h02;
10'h20B: rom_data <= 6'h0C;
10'h20C: rom_data <= 6'h0B;
10'h20D: rom_data <= 6'h0D;
10'h20E: rom_data <= 6'h33;
10'h20F: rom_data <= 6'h07;
10'h210: rom_data <= 6'h37;
10'h211: rom_data <= 6'h0D;
10'h212: rom_data <= 6'h02;
10'h213: rom_data <= 6'h1A;
10'h214: rom_data <= 6'h0B;
10'h215: rom_data <= 6'h15;
10'h216: rom_data <= 6'h02;
10'h217: rom_data <= 6'h2A;
10'h218: rom_data <= 6'h13;
10'h219: rom_data <= 6'h09;
10'h21A: rom_data <= 6'h02;
10'h21B: rom_data <= 6'h0C;
10'h21C: rom_data <= 6'h0D;
10'h21D: rom_data <= 6'h03;
10'h21E: rom_data <= 6'h0E;
10'h21F: rom_data <= 6'h07;
10'h220: rom_data <= 6'h0D;
10'h221: rom_data <= 6'h0E;
10'h222: rom_data <= 6'h35;
10'h223: rom_data <= 6'h04;
10'h224: rom_data <= 6'h04;
10'h225: rom_data <= 6'h04;
10'h226: rom_data <= 6'h04;
10'h227: rom_data <= 6'h04;
10'h228: rom_data <= 6'h04;
10'h229: rom_data <= 6'h04;
10'h22A: rom_data <= 6'h04;
10'h22B: rom_data <= 6'h04;
10'h22C: rom_data <= 6'h04;
10'h22D: rom_data <= 6'h04;
10'h22E: rom_data <= 6'h04;
default: rom_data <= 6'h00;
endcase
end
`endif
endmodule | 58 |
3,675 | data/full_repos/permissive/106330868/verilog/controller/controller_tb.v | 106,330,868 | controller_tb.v | v | 80 | 73 | [] | ['general public license', 'free software foundation'] | [] | null | line:68: before: "$" | null | 1: b'%Error: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:52: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("controller.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #300000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,470 | module | module CONTROLLER_TB;
reg clk, rst_an;
reg [5:0] data_in;
reg data_stb, serve_next;
reg period_done;
wire clear_states;
wire ldq;
wire [9:0] coeff;
wire coeff_load;
wire [7:0] period;
wire [15:0] amp;
wire [7:0] dur;
CONTROLLER u_controller (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (data_in),
.data_stb (data_stb),
.period_out (period),
.amp_out (amp),
.coeff_out (coeff),
.coeff_stb (coeff_load),
.clear_states (clear_states),
.period_done_in (period_done)
);
initial
begin
$dumpfile ("controller.vcd");
$dumpvars;
clk = 0;
rst_an = 0;
data_in = 6;
data_stb = 0;
period_done = 0;
#5
rst_an = 1;
#5
data_stb = 1;
#10
data_stb = 0;
serve_next = 1;
#300000
$finish;
end
always @(posedge clk)
begin
;
end
always
#5 clk = !clk;
endmodule | module CONTROLLER_TB; |
reg clk, rst_an;
reg [5:0] data_in;
reg data_stb, serve_next;
reg period_done;
wire clear_states;
wire ldq;
wire [9:0] coeff;
wire coeff_load;
wire [7:0] period;
wire [15:0] amp;
wire [7:0] dur;
CONTROLLER u_controller (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (data_in),
.data_stb (data_stb),
.period_out (period),
.amp_out (amp),
.coeff_out (coeff),
.coeff_stb (coeff_load),
.clear_states (clear_states),
.period_done_in (period_done)
);
initial
begin
$dumpfile ("controller.vcd");
$dumpvars;
clk = 0;
rst_an = 0;
data_in = 6;
data_stb = 0;
period_done = 0;
#5
rst_an = 1;
#5
data_stb = 1;
#10
data_stb = 0;
serve_next = 1;
#300000
$finish;
end
always @(posedge clk)
begin
;
end
always
#5 clk = !clk;
endmodule | 58 |
3,677 | data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v | 106,330,868 | xlat_tb.v | v | 45 | 73 | [] | ['general public license', 'free software foundation'] | [] | [(21, 44)] | null | null | 1: b'%Error: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("xlat.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,473 | module | module XLAT_TB;
reg [7:0] c8_in;
wire [9:0] c10_out;
XLAT u_xlat (
c8_in,
c10_out
);
integer i;
initial
begin
$dumpfile ("xlat.vcd");
$dumpvars;
c8_in[7] = 0;
for(i=0; i<128; i=i+1)
begin
c8_in[6:0] = i;
#10;
end
$finish;
end
endmodule | module XLAT_TB; |
reg [7:0] c8_in;
wire [9:0] c10_out;
XLAT u_xlat (
c8_in,
c10_out
);
integer i;
initial
begin
$dumpfile ("xlat.vcd");
$dumpvars;
c8_in[7] = 0;
for(i=0; i<128; i=i+1)
begin
c8_in[6:0] = i;
#10;
end
$finish;
end
endmodule | 58 |
3,680 | data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v | 106,330,868 | pwmdac.v | v | 122 | 94 | [] | ['general public license', 'free software foundation'] | [] | [(27, 121)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v:61: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'data\' generates 8 bits.\n : ... In instance PWMDAC\n assign sum1 = $signed({data[7] ,{data, 2\'b00}}) + data - $signed({last_data, 2\'b00});\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v:69: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance PWMDAC\n quantdata = sum1[10] ? 8\'h80 : 8\'h7F;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,476 | module | module PWMDAC (
clk,
rst_an,
din,
din_ack,
dacout
);
input clk;
input rst_an;
output reg dacout;
input signed [7:0] din;
output reg din_ack;
reg signed [7:0] counter;
reg signed [7:0] data;
reg signed [7:0] last_data;
wire signed [10:0] sum1;
reg signed [6:0] quantdata;
assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data - $signed({last_data, 2'b00});
always @(*)
begin
if (sum1[10] ^ sum1[9] != 0)
begin
quantdata = sum1[10] ? 8'h80 : 8'h7F;
end
else
quantdata = sum1[9:3];
end
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
counter <= 0;
dacout <= 0;
din_ack <= 0;
data <= 0;
end
else
begin
counter <= counter + 8'b00000001;
`ifdef USE_PREFILTER
if (quantdata > $signed(counter[6:0]))
dacout <= 1;
else
dacout <= 0;
`else
if ($signed(data[7:1]) > $signed(counter[6:0]))
dacout <= 1;
else
dacout <= 0;
`endif
if (counter == 8'h7F)
begin
last_data <= data;
data <= din;
din_ack <= 1;
end
else
din_ack <= 0;
end
end
endmodule | module PWMDAC (
clk,
rst_an,
din,
din_ack,
dacout
); |
input clk;
input rst_an;
output reg dacout;
input signed [7:0] din;
output reg din_ack;
reg signed [7:0] counter;
reg signed [7:0] data;
reg signed [7:0] last_data;
wire signed [10:0] sum1;
reg signed [6:0] quantdata;
assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data - $signed({last_data, 2'b00});
always @(*)
begin
if (sum1[10] ^ sum1[9] != 0)
begin
quantdata = sum1[10] ? 8'h80 : 8'h7F;
end
else
quantdata = sum1[9:3];
end
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
counter <= 0;
dacout <= 0;
din_ack <= 0;
data <= 0;
end
else
begin
counter <= counter + 8'b00000001;
`ifdef USE_PREFILTER
if (quantdata > $signed(counter[6:0]))
dacout <= 1;
else
dacout <= 0;
`else
if ($signed(data[7:1]) > $signed(counter[6:0]))
dacout <= 1;
else
dacout <= 0;
`endif
if (counter == 8'h7F)
begin
last_data <= data;
data <= din;
din_ack <= 1;
end
else
din_ack <= 0;
end
end
endmodule | 58 |
3,684 | data/full_repos/permissive/106330868/verilog/source/source.v | 106,330,868 | source.v | v | 118 | 101 | [] | ['general public license', 'free software foundation'] | [] | [(21, 117)] | null | data/verilator_xmls/08ef7ed6-dfba-44a1-b35c-13fafa225a1d.xml | null | 1,480 | module | module SOURCE (
clk,
rst_an,
period,
amplitude,
strobe,
period_done,
source_out
);
input clk;
input rst_an;
output reg signed [15:0] source_out;
output reg period_done;
input [14:0] amplitude;
input [7:0] period;
input strobe;
reg signed [7:0] periodcnt;
reg [16:0] lfsr;
reg last_strobe;
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
periodcnt <= 0;
period_done <= 1;
source_out <= 0;
last_strobe <= 0;
lfsr <= 17'h1;
end
else
begin
period_done <= 0;
if ((strobe == 1) && (last_strobe == 0))
begin
if (period == 0)
begin
if (periodcnt >= 64)
begin
periodcnt <= 0;
period_done <= 1;
end
else
periodcnt <= periodcnt + 1;
lfsr <= {lfsr[15:0], lfsr[16] ^ lfsr[2]};
source_out <= lfsr[0] ? {1'b0, amplitude} : {1'b1, ~amplitude};
end
else
begin
if (periodcnt >= period)
begin
periodcnt <= 0;
period_done <= 1;
end
else
periodcnt <= periodcnt + 1;
if (periodcnt < 8)
source_out <= {1'b0, amplitude};
else
source_out <= 16'h0000;
lfsr <= 17'h1;
end
end
last_strobe <= strobe;
end
end
endmodule | module SOURCE (
clk,
rst_an,
period,
amplitude,
strobe,
period_done,
source_out
); |
input clk;
input rst_an;
output reg signed [15:0] source_out;
output reg period_done;
input [14:0] amplitude;
input [7:0] period;
input strobe;
reg signed [7:0] periodcnt;
reg [16:0] lfsr;
reg last_strobe;
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
periodcnt <= 0;
period_done <= 1;
source_out <= 0;
last_strobe <= 0;
lfsr <= 17'h1;
end
else
begin
period_done <= 0;
if ((strobe == 1) && (last_strobe == 0))
begin
if (period == 0)
begin
if (periodcnt >= 64)
begin
periodcnt <= 0;
period_done <= 1;
end
else
periodcnt <= periodcnt + 1;
lfsr <= {lfsr[15:0], lfsr[16] ^ lfsr[2]};
source_out <= lfsr[0] ? {1'b0, amplitude} : {1'b1, ~amplitude};
end
else
begin
if (periodcnt >= period)
begin
periodcnt <= 0;
period_done <= 1;
end
else
periodcnt <= periodcnt + 1;
if (periodcnt < 8)
source_out <= {1'b0, amplitude};
else
source_out <= 16'h0000;
lfsr <= 17'h1;
end
end
last_strobe <= strobe;
end
end
endmodule | 58 |
3,686 | data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v | 106,330,868 | speech256_top.v | v | 140 | 102 | [] | ['general public license', 'free software foundation'] | [] | [(21, 139)] | null | null | 1: b"%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:65: Cannot find file containing module: 'SOURCE'\n SOURCE u_source (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE\n data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE.v\n data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE.sv\n SOURCE\n SOURCE.v\n SOURCE.sv\n obj_dir/SOURCE\n obj_dir/SOURCE.v\n obj_dir/SOURCE.sv\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:77: Cannot find file containing module: 'FILTER'\n FILTER u_filter (\n ^~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:101: Cannot find file containing module: 'PWMDAC'\n PWMDAC u_pwmdac (\n ^~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:110: Cannot find file containing module: 'CONTROLLER'\n CONTROLLER u_controller (\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,482 | module | module SPEECH256_TOP (
clk,
rst_an,
ldq,
data_in,
data_stb,
pwm_out,
sample_out,
sample_stb
);
input clk;
input rst_an;
output pwm_out;
output ldq;
output signed [15:0] sample_out;
output sample_stb;
input [5:0] data_in;
input data_stb;
wire pwmdac_ack, src_strobe;
wire signed [15:0] sig_source;
wire signed [15:0] sig_filter;
wire period_done;
wire clear_states;
wire [7:0] period;
wire [7:0] dur;
wire [15:0] amp;
wire signed [9:0] coef_bus;
wire coef_load;
wire done;
SOURCE u_source (
.clk (clk),
.rst_an (rst_an),
.period (period[7:0]),
.amplitude (amp[14:0]),
.strobe (src_strobe),
.period_done (period_done),
.source_out (sig_source)
);
FILTER u_filter (
.clk (clk),
.rst_an (rst_an),
.coef_in (coef_bus),
.coef_load (coef_load),
.clear_states (clear_states),
.sig_in (sig_source),
.sig_out (sig_filter),
.start (pwmdac_ack),
.done (src_strobe)
);
`ifdef USE_SDDAC
SD2DAC u_sd2dac (
.clk (clk),
.rst_an (rst_an),
.din ($signed({sig_filter[11:0],4'h0})),
.din_ack (pwmdac_ack),
.dacout (pwm_out)
);
`else
PWMDAC u_pwmdac (
.clk (clk),
.rst_an (rst_an),
.din (sig_filter[10:3]),
.din_ack (pwmdac_ack),
.dacout (pwm_out)
);
`endif
CONTROLLER u_controller (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (data_in),
.data_stb (data_stb),
.period_out (period),
.amp_out (amp),
.coeff_out (coef_bus),
.coeff_stb (coef_load),
.clear_states (clear_states),
.period_done_in (period_done)
);
assign sample_out = sig_filter[15:0];
assign sample_stb = src_strobe;
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
end
else
begin
end
end
endmodule | module SPEECH256_TOP (
clk,
rst_an,
ldq,
data_in,
data_stb,
pwm_out,
sample_out,
sample_stb
); |
input clk;
input rst_an;
output pwm_out;
output ldq;
output signed [15:0] sample_out;
output sample_stb;
input [5:0] data_in;
input data_stb;
wire pwmdac_ack, src_strobe;
wire signed [15:0] sig_source;
wire signed [15:0] sig_filter;
wire period_done;
wire clear_states;
wire [7:0] period;
wire [7:0] dur;
wire [15:0] amp;
wire signed [9:0] coef_bus;
wire coef_load;
wire done;
SOURCE u_source (
.clk (clk),
.rst_an (rst_an),
.period (period[7:0]),
.amplitude (amp[14:0]),
.strobe (src_strobe),
.period_done (period_done),
.source_out (sig_source)
);
FILTER u_filter (
.clk (clk),
.rst_an (rst_an),
.coef_in (coef_bus),
.coef_load (coef_load),
.clear_states (clear_states),
.sig_in (sig_source),
.sig_out (sig_filter),
.start (pwmdac_ack),
.done (src_strobe)
);
`ifdef USE_SDDAC
SD2DAC u_sd2dac (
.clk (clk),
.rst_an (rst_an),
.din ($signed({sig_filter[11:0],4'h0})),
.din_ack (pwmdac_ack),
.dacout (pwm_out)
);
`else
PWMDAC u_pwmdac (
.clk (clk),
.rst_an (rst_an),
.din (sig_filter[10:3]),
.din_ack (pwmdac_ack),
.dacout (pwm_out)
);
`endif
CONTROLLER u_controller (
.clk (clk),
.rst_an (rst_an),
.ldq (ldq),
.data_in (data_in),
.data_stb (data_stb),
.period_out (period),
.amp_out (amp),
.coeff_out (coef_bus),
.coeff_stb (coef_load),
.clear_states (clear_states),
.period_done_in (period_done)
);
assign sample_out = sig_filter[15:0];
assign sample_stb = src_strobe;
always @(posedge clk, negedge rst_an)
begin
if (rst_an == 0)
begin
end
else
begin
end
end
endmodule | 58 |
3,690 | data/full_repos/permissive/106408053/verilog/async_fifo.v | 106,408,053 | async_fifo.v | v | 441 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:109: before: "." | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n gray.v\n gray.v.v\n gray.v.sv\n obj_dir/gray.v\n obj_dir/gray.v.v\n obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n #1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n' | 1,486 | module | module async_fifo (
wrclk, wrreset, rdclk, rdreset,
space_avail, wrenb, wrdata,
read_req, data_avail,
data_valid, data_out);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;
input wrclk, wrreset;
input rdclk, rdreset;
output space_avail;
input wrenb;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
wire [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, stable_rdptr;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr, ram_rdaddr;
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata, ram_rddata;
async_fifo_ram ram (
wrclk, rdclk,
ram_wrenb, ram_wraddr, ram_wrdata,
ram_rdenb, ram_rdaddr, ram_rddata);
defparam ram.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam ram.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
async_fifo_wrpath wrpath (
wrclk, wrreset,
space_avail, wrenb, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr);
defparam wrpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam wrpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
defparam wrpath.ASYNC_FIFO_FULLTHRESHOLD = ASYNC_FIFO_FULLTHRESHOLD;
async_fifo_rdpath rdpath (
rdclk, rdreset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr);
defparam rdpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam rdpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
endmodule | module async_fifo (
wrclk, wrreset, rdclk, rdreset,
space_avail, wrenb, wrdata,
read_req, data_avail,
data_valid, data_out); |
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;
input wrclk, wrreset;
input rdclk, rdreset;
output space_avail;
input wrenb;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
wire [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, stable_rdptr;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr, ram_rdaddr;
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata, ram_rddata;
async_fifo_ram ram (
wrclk, rdclk,
ram_wrenb, ram_wraddr, ram_wrdata,
ram_rdenb, ram_rdaddr, ram_rddata);
defparam ram.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam ram.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
async_fifo_wrpath wrpath (
wrclk, wrreset,
space_avail, wrenb, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr);
defparam wrpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam wrpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
defparam wrpath.ASYNC_FIFO_FULLTHRESHOLD = ASYNC_FIFO_FULLTHRESHOLD;
async_fifo_rdpath rdpath (
rdclk, rdreset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr);
defparam rdpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam rdpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
endmodule | 6 |
3,691 | data/full_repos/permissive/106408053/verilog/async_fifo.v | 106,408,053 | async_fifo.v | v | 441 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:109: before: "." | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n gray.v\n gray.v.v\n gray.v.sv\n obj_dir/gray.v\n obj_dir/gray.v.v\n obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n #1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n' | 1,486 | module | module async_fifo_wrpath (
clk, reset,
space_avail, data_valid, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;
input clk, reset;
output space_avail;
input data_valid;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output ram_wrenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_wraddr;
output [ASYNC_FIFO_MAXDATA:0] ram_wrdata;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, next_stable_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg space_avail, next_space_avail;
wire [ASYNC_FIFO_MAXINDEX+1:0] wrptr_plus1 = wrptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] fifo_depth = wrptr-rdptr;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_rdptr;
full_synchronizer #(WIDTH) sync_gray_rdptr (clk, reset, stable_rdptr, gray_rdptr);
wire ram_wrenb = data_valid;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr = wrptr[ASYNC_FIFO_MAXINDEX:0];
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata = wrdata;
initial
begin
stable_wrptr = 0;
rdptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_wrptr = 0;
rdptr = 0;
end
else
begin
stable_wrptr = next_stable_wrptr;
rdptr = next_rdptr;
end
end
always @(*)
begin
#1;
next_stable_wrptr = bin2gray(next_wrptr);
next_rdptr = gray2bin(gray_rdptr);
end
initial
begin
space_avail = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
space_avail = 1'b1;
wrptr = 0;
end
else
begin
space_avail = next_space_avail;
wrptr = next_wrptr;
if (data_valid)
begin
#1;
if (fifo_depth >= (1<<(ASYNC_FIFO_MAXINDEX+1)))
begin
$display ("%t: FIFO OVERFLOW!",$realtime);
$finish;
end
end
end
end
always @(*)
begin
#1;
next_space_avail = fifo_depth<((1<<(ASYNC_FIFO_MAXINDEX+1))-ASYNC_FIFO_FULLTHRESHOLD);
next_wrptr = (data_valid && space_avail) ? wrptr_plus1 : wrptr;
end
endmodule | module async_fifo_wrpath (
clk, reset,
space_avail, data_valid, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr); |
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;
input clk, reset;
output space_avail;
input data_valid;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output ram_wrenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_wraddr;
output [ASYNC_FIFO_MAXDATA:0] ram_wrdata;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, next_stable_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg space_avail, next_space_avail;
wire [ASYNC_FIFO_MAXINDEX+1:0] wrptr_plus1 = wrptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] fifo_depth = wrptr-rdptr;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_rdptr;
full_synchronizer #(WIDTH) sync_gray_rdptr (clk, reset, stable_rdptr, gray_rdptr);
wire ram_wrenb = data_valid;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr = wrptr[ASYNC_FIFO_MAXINDEX:0];
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata = wrdata;
initial
begin
stable_wrptr = 0;
rdptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_wrptr = 0;
rdptr = 0;
end
else
begin
stable_wrptr = next_stable_wrptr;
rdptr = next_rdptr;
end
end
always @(*)
begin
#1;
next_stable_wrptr = bin2gray(next_wrptr);
next_rdptr = gray2bin(gray_rdptr);
end
initial
begin
space_avail = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
space_avail = 1'b1;
wrptr = 0;
end
else
begin
space_avail = next_space_avail;
wrptr = next_wrptr;
if (data_valid)
begin
#1;
if (fifo_depth >= (1<<(ASYNC_FIFO_MAXINDEX+1)))
begin
$display ("%t: FIFO OVERFLOW!",$realtime);
$finish;
end
end
end
end
always @(*)
begin
#1;
next_space_avail = fifo_depth<((1<<(ASYNC_FIFO_MAXINDEX+1))-ASYNC_FIFO_FULLTHRESHOLD);
next_wrptr = (data_valid && space_avail) ? wrptr_plus1 : wrptr;
end
endmodule | 6 |
3,692 | data/full_repos/permissive/106408053/verilog/async_fifo.v | 106,408,053 | async_fifo.v | v | 441 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:109: before: "." | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n gray.v\n gray.v.v\n gray.v.sv\n obj_dir/gray.v\n obj_dir/gray.v.v\n obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n #1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n' | 1,486 | module | module async_fifo_rdpath (
clk, reset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
input clk, reset;
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
output ram_rdenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
input [ASYNC_FIFO_MAXDATA:0] ram_rddata;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr, next_stable_rdptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg data_avail, next_data_avail;
reg data_valid, next_data_valid;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg [ASYNC_FIFO_MAXDATA:0] data_out, next_data_out;
wire ram_rdenb = data_avail;
reg [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
wire [ASYNC_FIFO_MAXINDEX+1:0] rdptr_plus1 = rdptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_wrptr;
full_synchronizer #(WIDTH) sync_gray_wrptr (clk, reset, stable_wrptr, gray_wrptr);
initial
begin
stable_rdptr = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_rdptr = 0;
wrptr = 0;
end
else
begin
stable_rdptr = next_stable_rdptr;
wrptr = next_wrptr;
end
end
always @(*)
begin
#1;
next_stable_rdptr = bin2gray(rdptr);
next_wrptr = gray2bin(gray_wrptr);
end
initial
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
else
begin
rdptr = next_rdptr;
data_avail = next_data_avail;
data_valid = next_data_valid;
end
end
always @ (posedge clk) data_out = next_data_out;
always @(*)
begin
#1;
next_rdptr = rdptr;
next_data_out = {(ASYNC_FIFO_MAXDATA+1){data_avail}} & ram_rddata;
next_data_valid = 1'b0;
if (read_req && data_avail)
begin
next_data_valid = 1'b1;
next_rdptr = rdptr_plus1;
end
next_data_avail = (next_wrptr != next_rdptr);
ram_rdaddr = next_rdptr[ASYNC_FIFO_MAXINDEX:0];
end
endmodule | module async_fifo_rdpath (
clk, reset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr); |
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
input clk, reset;
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
output ram_rdenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
input [ASYNC_FIFO_MAXDATA:0] ram_rddata;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr, next_stable_rdptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg data_avail, next_data_avail;
reg data_valid, next_data_valid;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg [ASYNC_FIFO_MAXDATA:0] data_out, next_data_out;
wire ram_rdenb = data_avail;
reg [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
wire [ASYNC_FIFO_MAXINDEX+1:0] rdptr_plus1 = rdptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_wrptr;
full_synchronizer #(WIDTH) sync_gray_wrptr (clk, reset, stable_wrptr, gray_wrptr);
initial
begin
stable_rdptr = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_rdptr = 0;
wrptr = 0;
end
else
begin
stable_rdptr = next_stable_rdptr;
wrptr = next_wrptr;
end
end
always @(*)
begin
#1;
next_stable_rdptr = bin2gray(rdptr);
next_wrptr = gray2bin(gray_wrptr);
end
initial
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
else
begin
rdptr = next_rdptr;
data_avail = next_data_avail;
data_valid = next_data_valid;
end
end
always @ (posedge clk) data_out = next_data_out;
always @(*)
begin
#1;
next_rdptr = rdptr;
next_data_out = {(ASYNC_FIFO_MAXDATA+1){data_avail}} & ram_rddata;
next_data_valid = 1'b0;
if (read_req && data_avail)
begin
next_data_valid = 1'b1;
next_rdptr = rdptr_plus1;
end
next_data_avail = (next_wrptr != next_rdptr);
ram_rdaddr = next_rdptr[ASYNC_FIFO_MAXINDEX:0];
end
endmodule | 6 |
3,693 | data/full_repos/permissive/106408053/verilog/async_fifo.v | 106,408,053 | async_fifo.v | v | 441 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | line:109: before: "." | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n gray.v\n gray.v.v\n gray.v.sv\n obj_dir/gray.v\n obj_dir/gray.v.v\n obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n #1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n' | 1,486 | module | module async_fifo_ram (wrclk, rdclk, wrenb, wrptr, wrdata, rdenb, rdptr, rddata);
parameter ASYNC_FIFO_MAXINDEX = 4;
parameter ASYNC_FIFO_MAXDATA = 31;
input wrclk, rdclk;
input wrenb, rdenb;
input [ASYNC_FIFO_MAXINDEX:0] wrptr, rdptr;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output [ASYNC_FIFO_MAXDATA:0] rddata;
wire #1 dly_wrenb = wrenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_wrptr = wrptr;
wire [ASYNC_FIFO_MAXDATA:0] #1 dly_wrdata = wrdata;
wire #1 dly_rdenb = rdenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_rdptr = rdptr;
reg [ASYNC_FIFO_MAXDATA:0] mem[0:(1<<(ASYNC_FIFO_MAXINDEX+1))-1];
reg [ASYNC_FIFO_MAXINDEX:0] rdptr_reg;
assign rddata = mem[rdptr_reg];
always @ (posedge wrclk)
begin
if (dly_wrenb) mem[dly_wrptr] = dly_wrdata;
end
always @ (posedge rdclk)
begin
rdptr_reg = dly_rdptr;
end
endmodule | module async_fifo_ram (wrclk, rdclk, wrenb, wrptr, wrdata, rdenb, rdptr, rddata); |
parameter ASYNC_FIFO_MAXINDEX = 4;
parameter ASYNC_FIFO_MAXDATA = 31;
input wrclk, rdclk;
input wrenb, rdenb;
input [ASYNC_FIFO_MAXINDEX:0] wrptr, rdptr;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output [ASYNC_FIFO_MAXDATA:0] rddata;
wire #1 dly_wrenb = wrenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_wrptr = wrptr;
wire [ASYNC_FIFO_MAXDATA:0] #1 dly_wrdata = wrdata;
wire #1 dly_rdenb = rdenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_rdptr = rdptr;
reg [ASYNC_FIFO_MAXDATA:0] mem[0:(1<<(ASYNC_FIFO_MAXINDEX+1))-1];
reg [ASYNC_FIFO_MAXINDEX:0] rdptr_reg;
assign rddata = mem[rdptr_reg];
always @ (posedge wrclk)
begin
if (dly_wrenb) mem[dly_wrptr] = dly_wrdata;
end
always @ (posedge rdclk)
begin
rdptr_reg = dly_rdptr;
end
endmodule | 6 |
3,695 | data/full_repos/permissive/106408053/verilog/clockman.v | 106,408,053 | clockman.v | v | 62 | 83 | [] | [] | [] | [(22, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/106408053/verilog/clockman.v:35: Cannot find file containing module: 'DCM_SP'\nDCM_SP #(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP.sv\n DCM_SP\n DCM_SP.v\n DCM_SP.sv\n obj_dir/DCM_SP\n obj_dir/DCM_SP.v\n obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/106408053/verilog/clockman.v:60: Cannot find file containing module: 'BUFG'\n BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 1,489 | module | module pll_wrapper (clkin, clk0);
input clkin;
output clk0;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
wire clkin;
wire clk0;
wire clkfb;
wire clkfbbuf;
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(31.250),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DFS_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_baseClock (
.CLK0(clkfb),
.CLKFX(clk0),
.CLKFB(clkfbbuf),
.CLKIN(clkin),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(1'b0)
);
BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));
endmodule | module pll_wrapper (clkin, clk0); |
input clkin;
output clk0;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
wire clkin;
wire clk0;
wire clkfb;
wire clkfbbuf;
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(31.250),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DFS_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_baseClock (
.CLK0(clkfb),
.CLKFX(clk0),
.CLKFB(clkfbbuf),
.CLKIN(clkin),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(1'b0)
);
BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));
endmodule | 6 |
3,696 | data/full_repos/permissive/106408053/verilog/controller.v | 106,408,053 | controller.v | v | 218 | 96 | [] | ['general public license', 'free software foundation'] | [] | [(39, 216)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/controller.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1; next_memoryWrData = dataIn;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/controller.v:127: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/controller.v:206: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,490 | module | module controller(
clock, reset, run,
wrSize, config_data,
validIn, dataIn, busy, arm,
send, memoryWrData, memoryRead,
memoryWrite, memoryLastWrite);
input clock;
input reset;
input run;
input wrSize;
input [31:0] config_data;
input validIn;
input [31:0] dataIn;
input busy;
input arm;
output send;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
reg [15:0] fwd, next_fwd;
reg [15:0] bwd, next_bwd;
reg send, next_send;
reg memoryRead, next_memoryRead;
reg memoryWrite, next_memoryWrite;
reg memoryLastWrite, next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
reg [31:0] memoryWrData, next_memoryWrData;
always @(posedge clock)
begin
memoryWrData = next_memoryWrData;
end
always @*
begin
#1; next_memoryWrData = dataIn;
end
parameter [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
state = IDLE;
memoryWrite = 1'b0;
memoryLastWrite = 1'b0;
memoryRead = 1'b0;
end
else
begin
state = next_state;
memoryWrite = next_memoryWrite;
memoryLastWrite = next_memoryLastWrite;
memoryRead = next_memoryRead;
end
end
always @(posedge clock)
begin
counter = next_counter;
send = next_send;
end
always @*
begin
#1;
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11})
begin
next_memoryLastWrite = 1'b1;
next_counter = 0;
next_state = READ;
end
end
end
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
always @(posedge clock)
begin
fwd = next_fwd;
bwd = next_bwd;
end
always @*
begin
#1;
next_fwd = fwd;
next_bwd = bwd;
if (wrSize)
begin
next_fwd = config_data[31:16];
next_bwd = config_data[15:0];
end
end
endmodule | module controller(
clock, reset, run,
wrSize, config_data,
validIn, dataIn, busy, arm,
send, memoryWrData, memoryRead,
memoryWrite, memoryLastWrite); |
input clock;
input reset;
input run;
input wrSize;
input [31:0] config_data;
input validIn;
input [31:0] dataIn;
input busy;
input arm;
output send;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
reg [15:0] fwd, next_fwd;
reg [15:0] bwd, next_bwd;
reg send, next_send;
reg memoryRead, next_memoryRead;
reg memoryWrite, next_memoryWrite;
reg memoryLastWrite, next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
reg [31:0] memoryWrData, next_memoryWrData;
always @(posedge clock)
begin
memoryWrData = next_memoryWrData;
end
always @*
begin
#1; next_memoryWrData = dataIn;
end
parameter [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
state = IDLE;
memoryWrite = 1'b0;
memoryLastWrite = 1'b0;
memoryRead = 1'b0;
end
else
begin
state = next_state;
memoryWrite = next_memoryWrite;
memoryLastWrite = next_memoryLastWrite;
memoryRead = next_memoryRead;
end
end
always @(posedge clock)
begin
counter = next_counter;
send = next_send;
end
always @*
begin
#1;
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11})
begin
next_memoryLastWrite = 1'b1;
next_counter = 0;
next_state = READ;
end
end
end
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
always @(posedge clock)
begin
fwd = next_fwd;
bwd = next_bwd;
end
always @*
begin
#1;
next_fwd = fwd;
next_bwd = bwd;
if (wrSize)
begin
next_fwd = config_data[31:16];
next_bwd = config_data[15:0];
end
end
endmodule | 6 |
3,697 | data/full_repos/permissive/106408053/verilog/core.v | 106,408,053 | core.v | v | 431 | 112 | [] | ['general public license', 'free software foundation'] | [] | null | line:355: before: "." | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/core.v:195: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:168: Signal definition not found, creating implicitly: \'sampled_extTriggerIn\'\nassign run = run_basic | run_adv | sampled_extTriggerIn;\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:342: Signal definition not found, creating implicitly: \'capture_basic\'\n : ... Suggested alternative: \'arm_basic\'\nwire capture = capture_basic || capture_adv;\n ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:342: Signal definition not found, creating implicitly: \'capture_adv\'\n : ... Suggested alternative: \'capture\'\nwire capture = capture_basic || capture_adv;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:141: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_core (clock, reset, reset_core); \n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync.sv\n reset_sync\n reset_sync.v\n reset_sync.sv\n obj_dir/reset_sync\n obj_dir/reset_sync.v\n obj_dir/reset_sync.sv\n%Error: data/full_repos/permissive/106408053/verilog/core.v:142: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:165: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:166: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerOut_reg (clock, run, extTriggerOut);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:220: Cannot find file containing module: \'BUFGMUX\'\nBUFGMUX BUFGMUX_intex(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:230: Cannot find file containing module: \'decoder\'\ndecoder decoder(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:253: Cannot find file containing module: \'flags\'\nflags flags(\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:265: Cannot find file containing module: \'sync\'\nsync sync(\n^~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:281: Cannot find file containing module: \'async_fifo\'\nasync_fifo async_fifo(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:292: Cannot find file containing module: \'sampler\'\nsampler sampler(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:308: Cannot find file containing module: \'trigger\'\ntrigger trigger(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:328: Cannot find file containing module: \'trigger_adv\'\ntrigger_adv trigger_adv(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:348: Cannot find file containing module: \'delay_fifo\'\ndelay_fifo delay_fifo (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:361: Cannot find file containing module: \'data_align\'\ndata_align data_align (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:375: Cannot find file containing module: \'rle_enc\'\nrle_enc rle_enc (\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:394: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall dly_arm_reg (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:401: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall dly_run_reg (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:412: Cannot find file containing module: \'controller\'\ncontroller controller(\n^~~~~~~~~~\n%Error: Exiting due to 18 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,491 | module | module core(
clock, extReset,
extClock, extTriggerIn,
opcode, config_data, execute, indata, outputBusy,
sampleReady50, outputSend, stableInput,
memoryWrData, memoryRead, memoryWrite, memoryLastWrite,
extTriggerOut, extClockOut, armLEDnn,
triggerLEDnn, wrFlags, extTestMode);
parameter [31:0] MEMORY_DEPTH=6;
input clock;
input extReset;
input [7:0] opcode;
input [31:0] config_data;
input execute;
input [31:0] indata;
input extClock;
input outputBusy;
input extTriggerIn;
output sampleReady50;
output outputSend;
output [31:0] stableInput;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
output extTriggerOut;
output extClockOut;
output armLEDnn;
output triggerLEDnn;
output wrFlags;
output extTestMode;
wire [31:0] syncedInput;
wire [3:0] wrtrigmask;
wire [3:0] wrtrigval;
wire [3:0] wrtrigcfg;
wire [3:0] wrtrigedge;
wire wrDivider;
wire wrsize;
wire sample_valid;
wire [31:0] sample_data;
wire dly_sample_valid;
wire [31:0] dly_sample_data;
wire aligned_data_valid;
wire [31:0] aligned_data;
wire rle_data_valid;
wire [31:0] rle_data;
wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;
wire sampleClock;
`ifdef SLOW_EXTCLK
reg [1:0] scount, next_scount;
assign extClockOut = scount[1];
initial scount=0;
always @ (posedge sampleClock)
begin
scount = next_scount;
end
always @*
begin
next_scount = scount+1'b1;
end
`else
wire extClockOut = sampleClock;
`endif
wire resetCmd;
wire reset = extReset | resetCmd;
reset_sync reset_sync_core (clock, reset, reset_core);
reset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);
wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
wire extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
wire extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];
wire run_basic, run_adv, run;
dly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (clock, run, extTriggerOut);
assign run = run_basic | run_adv | sampled_extTriggerIn;
reg armLEDnn, next_armLEDnn;
reg triggerLEDnn, next_triggerLEDnn;
`ifdef HEARTBEAT
reg [31:0] hcount, next_hcount;
initial hcount=0;
always @ (posedge clock)
begin
hcount = next_hcount;
end
`endif
always @(posedge clock)
begin
armLEDnn = next_armLEDnn;
triggerLEDnn = next_triggerLEDnn;
end
always @*
begin
#1;
next_armLEDnn = armLEDnn;
next_triggerLEDnn = triggerLEDnn;
if (arm)
begin
next_armLEDnn = ~1'b1;
next_triggerLEDnn = ~1'b0;
end
else if (run)
begin
next_armLEDnn = ~1'b0;
next_triggerLEDnn = ~1'b1;
end
`ifdef HEARTBEAT
next_hcount = (~|hcount) ? 100000000 : (hcount-1'b1);
next_armLEDnn = armLEDnn;
if (~|hcount) next_armLEDnn = !armLEDnn;
`endif
end
BUFGMUX BUFGMUX_intex(
.O(sampleClock),
.I0(clock),
.I1(extClock),
.S(extClock_mode));
decoder decoder(
.clock(clock),
.execute(execute),
.opcode(opcode),
.wrtrigmask(wrtrigmask),
.wrtrigval(wrtrigval),
.wrtrigcfg(wrtrigcfg),
.wrtrigedge(wrtrigedge),
.wrspeed(wrDivider),
.wrsize(wrsize),
.wrFlags(wrFlags),
.wrTrigSelect(wrTrigSelect),
.wrTrigChain(wrTrigChain),
.finish_now(finish_now),
.arm_basic(arm_basic),
.arm_adv(arm_adv),
.resetCmd(resetCmd));
flags flags(
.clock(clock),
.wrFlags(wrFlags),
.config_data(config_data),
.finish_now(finish_now),
.flags_reg(flags_reg));
sync sync(
.clock(sampleClock),
.indata(indata),
.intTestMode(intTestMode),
.numberScheme(numberScheme),
.filter_mode(filter_mode),
.demux_mode(demux_mode),
.falling_edge(falling_edge),
.outdata(syncedInput));
async_fifo async_fifo(
.wrclk(sampleClock), .wrreset(reset_sample),
.rdclk(clock), .rdreset(reset_core),
.space_avail(), .wrenb(1'b1), .wrdata(syncedInput),
.read_req(1'b1), .data_avail(),
.data_valid(stableValid), .data_out(stableInput));
sampler sampler(
.clock(clock),
.extClock_mode(extClock_mode),
.wrDivider(wrDivider),
.config_data(config_data[23:0]),
.validIn(stableValid),
.dataIn(stableInput),
.validOut(sample_valid),
.dataOut(sample_data),
.ready50(sampleReady50));
trigger trigger(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrMask(wrtrigmask),
.wrValue(wrtrigval),
.wrConfig(wrtrigcfg),
.wrEdge(wrtrigedge),
.config_data(config_data),
.arm(arm_basic),
.demux_mode(demux_mode),
.run(run_basic),
.capture(capture_basic));
trigger_adv trigger_adv(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrSelect(wrTrigSelect),
.wrChain(wrTrigChain),
.config_data(config_data),
.arm(arm_adv),
.finish_now(finish_now),
.run(run_adv),
.capture(capture_adv));
wire capture = capture_basic || capture_adv;
delay_fifo delay_fifo (
.clock(clock),
.validIn(sample_valid),
.dataIn(sample_data),
.validOut(dly_sample_valid),
.dataOut(dly_sample_data));
defparam delay_fifo.DELAY = 3;
data_align data_align (
.clock(clock),
.disabledGroups(disabledGroups),
.validIn(dly_sample_valid && capture),
.dataIn(dly_sample_data),
.validOut(aligned_data_valid),
.dataOut(aligned_data));
rle_enc rle_enc (
.clock(clock),
.reset(reset_core),
.enable(rleEnable),
.arm(arm),
.rle_mode(rle_mode),
.demux_mode(demux_mode),
.disabledGroups(disabledGroups),
.validIn(aligned_data_valid),
.dataIn(aligned_data),
.validOut(rle_data_valid),
.dataOut(rle_data));
pipeline_stall dly_arm_reg (
.clk(clock),
.reset(reset_core),
.datain(arm),
.dataout(dly_arm));
defparam dly_arm_reg.DELAY = 2;
pipeline_stall dly_run_reg (
.clk(clock),
.reset(reset_core),
.datain(run),
.dataout(dly_run));
defparam dly_run_reg.DELAY = 1;
controller controller(
.clock(clock),
.reset(reset_core),
.run(dly_run),
.wrSize(wrsize),
.config_data(config_data),
.validIn(rle_data_valid),
.dataIn(rle_data),
.arm(dly_arm),
.busy(outputBusy),
.send(outputSend),
.memoryWrData(memoryWrData),
.memoryRead(memoryRead),
.memoryWrite(memoryWrite),
.memoryLastWrite(memoryLastWrite));
endmodule | module core(
clock, extReset,
extClock, extTriggerIn,
opcode, config_data, execute, indata, outputBusy,
sampleReady50, outputSend, stableInput,
memoryWrData, memoryRead, memoryWrite, memoryLastWrite,
extTriggerOut, extClockOut, armLEDnn,
triggerLEDnn, wrFlags, extTestMode); |
parameter [31:0] MEMORY_DEPTH=6;
input clock;
input extReset;
input [7:0] opcode;
input [31:0] config_data;
input execute;
input [31:0] indata;
input extClock;
input outputBusy;
input extTriggerIn;
output sampleReady50;
output outputSend;
output [31:0] stableInput;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
output extTriggerOut;
output extClockOut;
output armLEDnn;
output triggerLEDnn;
output wrFlags;
output extTestMode;
wire [31:0] syncedInput;
wire [3:0] wrtrigmask;
wire [3:0] wrtrigval;
wire [3:0] wrtrigcfg;
wire [3:0] wrtrigedge;
wire wrDivider;
wire wrsize;
wire sample_valid;
wire [31:0] sample_data;
wire dly_sample_valid;
wire [31:0] dly_sample_data;
wire aligned_data_valid;
wire [31:0] aligned_data;
wire rle_data_valid;
wire [31:0] rle_data;
wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;
wire sampleClock;
`ifdef SLOW_EXTCLK
reg [1:0] scount, next_scount;
assign extClockOut = scount[1];
initial scount=0;
always @ (posedge sampleClock)
begin
scount = next_scount;
end
always @*
begin
next_scount = scount+1'b1;
end
`else
wire extClockOut = sampleClock;
`endif
wire resetCmd;
wire reset = extReset | resetCmd;
reset_sync reset_sync_core (clock, reset, reset_core);
reset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);
wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
wire extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
wire extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];
wire run_basic, run_adv, run;
dly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (clock, run, extTriggerOut);
assign run = run_basic | run_adv | sampled_extTriggerIn;
reg armLEDnn, next_armLEDnn;
reg triggerLEDnn, next_triggerLEDnn;
`ifdef HEARTBEAT
reg [31:0] hcount, next_hcount;
initial hcount=0;
always @ (posedge clock)
begin
hcount = next_hcount;
end
`endif
always @(posedge clock)
begin
armLEDnn = next_armLEDnn;
triggerLEDnn = next_triggerLEDnn;
end
always @*
begin
#1;
next_armLEDnn = armLEDnn;
next_triggerLEDnn = triggerLEDnn;
if (arm)
begin
next_armLEDnn = ~1'b1;
next_triggerLEDnn = ~1'b0;
end
else if (run)
begin
next_armLEDnn = ~1'b0;
next_triggerLEDnn = ~1'b1;
end
`ifdef HEARTBEAT
next_hcount = (~|hcount) ? 100000000 : (hcount-1'b1);
next_armLEDnn = armLEDnn;
if (~|hcount) next_armLEDnn = !armLEDnn;
`endif
end
BUFGMUX BUFGMUX_intex(
.O(sampleClock),
.I0(clock),
.I1(extClock),
.S(extClock_mode));
decoder decoder(
.clock(clock),
.execute(execute),
.opcode(opcode),
.wrtrigmask(wrtrigmask),
.wrtrigval(wrtrigval),
.wrtrigcfg(wrtrigcfg),
.wrtrigedge(wrtrigedge),
.wrspeed(wrDivider),
.wrsize(wrsize),
.wrFlags(wrFlags),
.wrTrigSelect(wrTrigSelect),
.wrTrigChain(wrTrigChain),
.finish_now(finish_now),
.arm_basic(arm_basic),
.arm_adv(arm_adv),
.resetCmd(resetCmd));
flags flags(
.clock(clock),
.wrFlags(wrFlags),
.config_data(config_data),
.finish_now(finish_now),
.flags_reg(flags_reg));
sync sync(
.clock(sampleClock),
.indata(indata),
.intTestMode(intTestMode),
.numberScheme(numberScheme),
.filter_mode(filter_mode),
.demux_mode(demux_mode),
.falling_edge(falling_edge),
.outdata(syncedInput));
async_fifo async_fifo(
.wrclk(sampleClock), .wrreset(reset_sample),
.rdclk(clock), .rdreset(reset_core),
.space_avail(), .wrenb(1'b1), .wrdata(syncedInput),
.read_req(1'b1), .data_avail(),
.data_valid(stableValid), .data_out(stableInput));
sampler sampler(
.clock(clock),
.extClock_mode(extClock_mode),
.wrDivider(wrDivider),
.config_data(config_data[23:0]),
.validIn(stableValid),
.dataIn(stableInput),
.validOut(sample_valid),
.dataOut(sample_data),
.ready50(sampleReady50));
trigger trigger(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrMask(wrtrigmask),
.wrValue(wrtrigval),
.wrConfig(wrtrigcfg),
.wrEdge(wrtrigedge),
.config_data(config_data),
.arm(arm_basic),
.demux_mode(demux_mode),
.run(run_basic),
.capture(capture_basic));
trigger_adv trigger_adv(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrSelect(wrTrigSelect),
.wrChain(wrTrigChain),
.config_data(config_data),
.arm(arm_adv),
.finish_now(finish_now),
.run(run_adv),
.capture(capture_adv));
wire capture = capture_basic || capture_adv;
delay_fifo delay_fifo (
.clock(clock),
.validIn(sample_valid),
.dataIn(sample_data),
.validOut(dly_sample_valid),
.dataOut(dly_sample_data));
defparam delay_fifo.DELAY = 3;
data_align data_align (
.clock(clock),
.disabledGroups(disabledGroups),
.validIn(dly_sample_valid && capture),
.dataIn(dly_sample_data),
.validOut(aligned_data_valid),
.dataOut(aligned_data));
rle_enc rle_enc (
.clock(clock),
.reset(reset_core),
.enable(rleEnable),
.arm(arm),
.rle_mode(rle_mode),
.demux_mode(demux_mode),
.disabledGroups(disabledGroups),
.validIn(aligned_data_valid),
.dataIn(aligned_data),
.validOut(rle_data_valid),
.dataOut(rle_data));
pipeline_stall dly_arm_reg (
.clk(clock),
.reset(reset_core),
.datain(arm),
.dataout(dly_arm));
defparam dly_arm_reg.DELAY = 2;
pipeline_stall dly_run_reg (
.clk(clock),
.reset(reset_core),
.datain(run),
.dataout(dly_run));
defparam dly_run_reg.DELAY = 1;
controller controller(
.clock(clock),
.reset(reset_core),
.run(dly_run),
.wrSize(wrsize),
.config_data(config_data),
.validIn(rle_data_valid),
.dataIn(rle_data),
.arm(dly_arm),
.busy(outputBusy),
.send(outputSend),
.memoryWrData(memoryWrData),
.memoryRead(memoryRead),
.memoryWrite(memoryWrite),
.memoryLastWrite(memoryLastWrite));
endmodule | 6 |
3,698 | data/full_repos/permissive/106408053/verilog/data_align.v | 106,408,053 | data_align.v | v | 146 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(42, 144)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/data_align.v:78: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/data_align.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,492 | module | module data_align(
clock, disabledGroups,
validIn, dataIn,
validOut, dataOut);
input clock;
input [3:0] disabledGroups;
input validIn;
input [31:0] dataIn;
output validOut;
output [31:0] dataOut;
reg [1:0] insel0, next_insel0;
reg [1:0] insel1, next_insel1;
reg insel2, next_insel2;
reg [31:0] dataOut, next_dataOut;
reg validOut, next_validOut;
always @ (posedge clock)
begin
dataOut = next_dataOut;
validOut = next_validOut;
end
always @*
begin
#1;
next_dataOut = dataIn;
next_validOut = validIn;
case (insel0[1:0])
2'h1 : next_dataOut[7:0] = dataIn[15:8];
2'h2 : next_dataOut[7:0] = dataIn[23:16];
2'h3 : next_dataOut[7:0] = dataIn[31:24];
endcase
case (insel1[1:0])
2'h1 : next_dataOut[15:8] = dataIn[23:16];
2'h2 : next_dataOut[15:8] = dataIn[31:24];
endcase
case (insel2)
1'b1 : next_dataOut[23:16] = dataIn[31:24];
endcase
end
always @(posedge clock)
begin
insel0 = next_insel0;
insel1 = next_insel1;
insel2 = next_insel2;
end
always @*
begin
#1;
next_insel0 = 2'h0;
next_insel1 = 2'h0;
next_insel2 = 1'b0;
case (disabledGroups)
4'b0001 : begin next_insel2 = 1'b1; next_insel1=2'h1; next_insel0=2'h1; end
4'b0010 : begin next_insel2 = 1'b1; next_insel1=2'h1; end
4'b0100 : begin next_insel2 = 1'b1; end
4'b0011 : begin next_insel1=2'h2; next_insel0=2'h2; end
4'b0101 : begin next_insel1=2'h2; next_insel0=2'h1; end
4'b1001 : begin next_insel1=2'h1; next_insel0=2'h1; end
4'b0110 : begin next_insel1=2'h2; end
4'b1010 : begin next_insel1=2'h1; end
4'b1100 : begin next_insel1=2'h0; end
4'b0111 : next_insel0 = 2'h3;
4'b1011 : next_insel0 = 2'h2;
4'b1101 : next_insel0 = 2'h1;
endcase
end
endmodule | module data_align(
clock, disabledGroups,
validIn, dataIn,
validOut, dataOut); |
input clock;
input [3:0] disabledGroups;
input validIn;
input [31:0] dataIn;
output validOut;
output [31:0] dataOut;
reg [1:0] insel0, next_insel0;
reg [1:0] insel1, next_insel1;
reg insel2, next_insel2;
reg [31:0] dataOut, next_dataOut;
reg validOut, next_validOut;
always @ (posedge clock)
begin
dataOut = next_dataOut;
validOut = next_validOut;
end
always @*
begin
#1;
next_dataOut = dataIn;
next_validOut = validIn;
case (insel0[1:0])
2'h1 : next_dataOut[7:0] = dataIn[15:8];
2'h2 : next_dataOut[7:0] = dataIn[23:16];
2'h3 : next_dataOut[7:0] = dataIn[31:24];
endcase
case (insel1[1:0])
2'h1 : next_dataOut[15:8] = dataIn[23:16];
2'h2 : next_dataOut[15:8] = dataIn[31:24];
endcase
case (insel2)
1'b1 : next_dataOut[23:16] = dataIn[31:24];
endcase
end
always @(posedge clock)
begin
insel0 = next_insel0;
insel1 = next_insel1;
insel2 = next_insel2;
end
always @*
begin
#1;
next_insel0 = 2'h0;
next_insel1 = 2'h0;
next_insel2 = 1'b0;
case (disabledGroups)
4'b0001 : begin next_insel2 = 1'b1; next_insel1=2'h1; next_insel0=2'h1; end
4'b0010 : begin next_insel2 = 1'b1; next_insel1=2'h1; end
4'b0100 : begin next_insel2 = 1'b1; end
4'b0011 : begin next_insel1=2'h2; next_insel0=2'h2; end
4'b0101 : begin next_insel1=2'h2; next_insel0=2'h1; end
4'b1001 : begin next_insel1=2'h1; next_insel0=2'h1; end
4'b0110 : begin next_insel1=2'h2; end
4'b1010 : begin next_insel1=2'h1; end
4'b1100 : begin next_insel1=2'h0; end
4'b0111 : next_insel0 = 2'h3;
4'b1011 : next_insel0 = 2'h2;
4'b1101 : next_insel0 = 2'h1;
endcase
end
endmodule | 6 |
3,699 | data/full_repos/permissive/106408053/verilog/decoder.v | 106,408,053 | decoder.v | v | 167 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(39, 165)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/decoder.v:109: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,494 | module | module decoder(
clock, execute, opcode,
wrtrigmask, wrtrigval, wrtrigcfg, wrtrigedge,
wrspeed, wrsize, wrFlags,
wrTrigSelect, wrTrigChain,
finish_now,
arm_basic, arm_adv, resetCmd);
input clock;
input execute;
input [7:0] opcode;
output [3:0] wrtrigmask;
output [3:0] wrtrigval;
output [3:0] wrtrigcfg;
output [3:0] wrtrigedge;
output wrspeed;
output wrsize;
output wrFlags;
output wrTrigSelect;
output wrTrigChain;
output finish_now;
output arm_basic;
output arm_adv;
output resetCmd;
reg resetCmd, next_resetCmd;
reg arm_basic, next_arm_basic;
reg arm_adv, next_arm_adv;
reg [3:0] wrtrigmask, next_wrtrigmask;
reg [3:0] wrtrigval, next_wrtrigval;
reg [3:0] wrtrigcfg, next_wrtrigcfg;
reg [3:0] wrtrigedge, next_wrtrigedge;
reg wrspeed, next_wrspeed;
reg wrsize, next_wrsize;
reg wrFlags, next_wrFlags;
reg finish_now, next_finish_now;
reg wrTrigSelect, next_wrTrigSelect;
reg wrTrigChain, next_wrTrigChain;
reg dly_execute, next_dly_execute;
always @(posedge clock)
begin
resetCmd = next_resetCmd;
arm_basic = next_arm_basic;
arm_adv = next_arm_adv;
wrtrigmask = next_wrtrigmask;
wrtrigval = next_wrtrigval;
wrtrigcfg = next_wrtrigcfg;
wrtrigedge = next_wrtrigedge;
wrspeed = next_wrspeed;
wrsize = next_wrsize;
wrFlags = next_wrFlags;
finish_now = next_finish_now;
wrTrigSelect = next_wrTrigSelect;
wrTrigChain = next_wrTrigChain;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_resetCmd = 1'b0;
next_arm_basic = 1'b0;
next_arm_adv = 1'b0;
next_wrtrigmask = 4'b0000;
next_wrtrigval = 4'b0000;
next_wrtrigcfg = 4'b0000;
next_wrtrigedge = 4'b0000;
next_wrspeed = 1'b0;
next_wrsize = 1'b0;
next_wrFlags = 1'b0;
next_finish_now = 1'b0;
next_wrTrigSelect = 1'b0;
next_wrTrigChain = 1'b0;
next_dly_execute = execute;
if (execute & !dly_execute)
case(opcode)
8'h00 : next_resetCmd = 1'b1;
8'h01 : next_arm_basic = 1'b1;
8'h02 :;
8'h03 :;
8'h04 :;
8'h05 : next_finish_now = 1'b1;
8'h06 :;
8'h0F : next_arm_adv = 1'b1;
8'h11 :;
8'h13 :;
8'h80 : next_wrspeed = 1'b1;
8'h81 : next_wrsize = 1'b1;
8'h82 : next_wrFlags = 1'b1;
8'h9E : next_wrTrigSelect = 1'b1;
8'h9F : next_wrTrigChain = 1'b1;
8'hC0 : next_wrtrigmask[0] = 1'b1;
8'hC1 : next_wrtrigval[0] = 1'b1;
8'hC2 : next_wrtrigcfg[0] = 1'b1;
8'hC3 : next_wrtrigedge[0] = 1'b1;
8'hC4 : next_wrtrigmask[1] = 1'b1;
8'hC5 : next_wrtrigval[1] = 1'b1;
8'hC6 : next_wrtrigcfg[1] = 1'b1;
8'hC7 : next_wrtrigedge[1] = 1'b1;
8'hC8 : next_wrtrigmask[2] = 1'b1;
8'hC9 : next_wrtrigval[2] = 1'b1;
8'hCA : next_wrtrigcfg[2] = 1'b1;
8'hCB : next_wrtrigedge[2] = 1'b1;
8'hCC : next_wrtrigmask[3] = 1'b1;
8'hCD : next_wrtrigval[3] = 1'b1;
8'hCE : next_wrtrigcfg[3] = 1'b1;
8'hCF : next_wrtrigedge[3] = 1'b1;
endcase
end
endmodule | module decoder(
clock, execute, opcode,
wrtrigmask, wrtrigval, wrtrigcfg, wrtrigedge,
wrspeed, wrsize, wrFlags,
wrTrigSelect, wrTrigChain,
finish_now,
arm_basic, arm_adv, resetCmd); |
input clock;
input execute;
input [7:0] opcode;
output [3:0] wrtrigmask;
output [3:0] wrtrigval;
output [3:0] wrtrigcfg;
output [3:0] wrtrigedge;
output wrspeed;
output wrsize;
output wrFlags;
output wrTrigSelect;
output wrTrigChain;
output finish_now;
output arm_basic;
output arm_adv;
output resetCmd;
reg resetCmd, next_resetCmd;
reg arm_basic, next_arm_basic;
reg arm_adv, next_arm_adv;
reg [3:0] wrtrigmask, next_wrtrigmask;
reg [3:0] wrtrigval, next_wrtrigval;
reg [3:0] wrtrigcfg, next_wrtrigcfg;
reg [3:0] wrtrigedge, next_wrtrigedge;
reg wrspeed, next_wrspeed;
reg wrsize, next_wrsize;
reg wrFlags, next_wrFlags;
reg finish_now, next_finish_now;
reg wrTrigSelect, next_wrTrigSelect;
reg wrTrigChain, next_wrTrigChain;
reg dly_execute, next_dly_execute;
always @(posedge clock)
begin
resetCmd = next_resetCmd;
arm_basic = next_arm_basic;
arm_adv = next_arm_adv;
wrtrigmask = next_wrtrigmask;
wrtrigval = next_wrtrigval;
wrtrigcfg = next_wrtrigcfg;
wrtrigedge = next_wrtrigedge;
wrspeed = next_wrspeed;
wrsize = next_wrsize;
wrFlags = next_wrFlags;
finish_now = next_finish_now;
wrTrigSelect = next_wrTrigSelect;
wrTrigChain = next_wrTrigChain;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_resetCmd = 1'b0;
next_arm_basic = 1'b0;
next_arm_adv = 1'b0;
next_wrtrigmask = 4'b0000;
next_wrtrigval = 4'b0000;
next_wrtrigcfg = 4'b0000;
next_wrtrigedge = 4'b0000;
next_wrspeed = 1'b0;
next_wrsize = 1'b0;
next_wrFlags = 1'b0;
next_finish_now = 1'b0;
next_wrTrigSelect = 1'b0;
next_wrTrigChain = 1'b0;
next_dly_execute = execute;
if (execute & !dly_execute)
case(opcode)
8'h00 : next_resetCmd = 1'b1;
8'h01 : next_arm_basic = 1'b1;
8'h02 :;
8'h03 :;
8'h04 :;
8'h05 : next_finish_now = 1'b1;
8'h06 :;
8'h0F : next_arm_adv = 1'b1;
8'h11 :;
8'h13 :;
8'h80 : next_wrspeed = 1'b1;
8'h81 : next_wrsize = 1'b1;
8'h82 : next_wrFlags = 1'b1;
8'h9E : next_wrTrigSelect = 1'b1;
8'h9F : next_wrTrigChain = 1'b1;
8'hC0 : next_wrtrigmask[0] = 1'b1;
8'hC1 : next_wrtrigval[0] = 1'b1;
8'hC2 : next_wrtrigcfg[0] = 1'b1;
8'hC3 : next_wrtrigedge[0] = 1'b1;
8'hC4 : next_wrtrigmask[1] = 1'b1;
8'hC5 : next_wrtrigval[1] = 1'b1;
8'hC6 : next_wrtrigcfg[1] = 1'b1;
8'hC7 : next_wrtrigedge[1] = 1'b1;
8'hC8 : next_wrtrigmask[2] = 1'b1;
8'hC9 : next_wrtrigval[2] = 1'b1;
8'hCA : next_wrtrigcfg[2] = 1'b1;
8'hCB : next_wrtrigedge[2] = 1'b1;
8'hCC : next_wrtrigmask[3] = 1'b1;
8'hCD : next_wrtrigval[3] = 1'b1;
8'hCE : next_wrtrigcfg[3] = 1'b1;
8'hCF : next_wrtrigedge[3] = 1'b1;
endcase
end
endmodule | 6 |
3,702 | data/full_repos/permissive/106408053/verilog/filter.v | 106,408,053 | filter.v | v | 62 | 83 | [] | ['general public license', 'free software foundation'] | [] | [(36, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/filter.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,497 | module | module filter (clock, indata, indata180, outdata);
input clock;
input [31:0] indata;
input [31:0] indata180;
output [31:0] outdata;
reg [31:0] dly_indata, next_dly_indata;
reg [31:0] dly_indata180, next_dly_indata180;
reg [31:0] outdata, next_outdata;
always @(posedge clock)
begin
outdata = next_outdata;
dly_indata = next_dly_indata;
dly_indata180 = next_dly_indata180;
end
always @*
begin
#1;
next_outdata = (outdata | dly_indata | indata) & dly_indata180;
next_dly_indata = indata;
next_dly_indata180 = indata180;
end
endmodule | module filter (clock, indata, indata180, outdata); |
input clock;
input [31:0] indata;
input [31:0] indata180;
output [31:0] outdata;
reg [31:0] dly_indata, next_dly_indata;
reg [31:0] dly_indata180, next_dly_indata180;
reg [31:0] outdata, next_outdata;
always @(posedge clock)
begin
outdata = next_outdata;
dly_indata = next_dly_indata;
dly_indata180 = next_dly_indata180;
end
always @*
begin
#1;
next_outdata = (outdata | dly_indata | indata) & dly_indata180;
next_dly_indata = indata;
next_dly_indata180 = indata180;
end
endmodule | 6 |
3,703 | data/full_repos/permissive/106408053/verilog/gray.v | 106,408,053 | gray.v | v | 105 | 88 | [] | ['general public license', 'free software foundation'] | [] | null | line:47: before: "prototypes" | null | 1: b"%Error: data/full_repos/permissive/106408053/verilog/gray.v:84: Can't find definition of variable: 'WIDTH'\nfunction [WIDTH-1:0] gray2bin;\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 1,499 | function | function [WIDTH-1:0] gray2bin;
input [WIDTH-1:0] gray;
integer i;
begin
gray2bin[WIDTH-1] = gray[WIDTH-1];
for (i=WIDTH-2; i>=0; i=i-1) gray2bin[i] = gray2bin[i+1]^gray[i];
end
endfunction | function [WIDTH-1:0] gray2bin; |
input [WIDTH-1:0] gray;
integer i;
begin
gray2bin[WIDTH-1] = gray[WIDTH-1];
for (i=WIDTH-2; i>=0; i=i-1) gray2bin[i] = gray2bin[i+1]^gray[i];
end
endfunction | 6 |
3,704 | data/full_repos/permissive/106408053/verilog/gray.v | 106,408,053 | gray.v | v | 105 | 88 | [] | ['general public license', 'free software foundation'] | [] | null | line:47: before: "prototypes" | null | 1: b"%Error: data/full_repos/permissive/106408053/verilog/gray.v:84: Can't find definition of variable: 'WIDTH'\nfunction [WIDTH-1:0] gray2bin;\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 1,499 | function | function [WIDTH-1:0] bin2gray;
input [WIDTH-1:0] bin;
integer i;
begin
for (i=0; i<WIDTH-1; i=i+1) bin2gray[i] = bin[i+1] ^ bin[i];
bin2gray[WIDTH-1] = bin[WIDTH-1];
end
endfunction | function [WIDTH-1:0] bin2gray; |
input [WIDTH-1:0] bin;
integer i;
begin
for (i=0; i<WIDTH-1; i=i+1) bin2gray[i] = bin[i+1] ^ bin[i];
bin2gray[WIDTH-1] = bin[WIDTH-1];
end
endfunction | 6 |
3,708 | data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v | 106,408,053 | Logic_Sniffer.v | v | 236 | 136 | [] | ['general public license', 'free software foundation'] | [] | [(41, 234)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:123: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:117: Signal definition not found, creating implicitly: \'clock\'\n : ... Suggested alternative: \'bf_clock\'\nalways @ (posedge clock) \n ^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:101: Cannot find file containing module: \'pll_wrapper\'\npll_wrapper pll_wrapper ( .clkin(bf_clock), .clk0(clock));\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/pll_wrapper\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/pll_wrapper.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/pll_wrapper.sv\n pll_wrapper\n pll_wrapper.v\n pll_wrapper.sv\n obj_dir/pll_wrapper\n obj_dir/pll_wrapper.v\n obj_dir/pll_wrapper.sv\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:105: Cannot find file containing module: \'dly_signal\'\ndly_signal dataReady_reg (clock, busy, dataReady);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:109: Cannot find file containing module: \'ddr_clkout\'\nddr_clkout extclock_pad (.pad(extClockOut), .clk(extclock));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:137: Cannot find file containing module: \'outbuf\'\noutbuf io_indata31 (.pad(indata[31]), .clk(clock), .outsig(test_pattern[15]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:138: Cannot find file containing module: \'outbuf\'\noutbuf io_indata30 (.pad(indata[30]), .clk(clock), .outsig(test_pattern[14]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:139: Cannot find file containing module: \'outbuf\'\noutbuf io_indata29 (.pad(indata[29]), .clk(clock), .outsig(test_pattern[13]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:140: Cannot find file containing module: \'outbuf\'\noutbuf io_indata28 (.pad(indata[28]), .clk(clock), .outsig(test_pattern[12]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:141: Cannot find file containing module: \'outbuf\'\noutbuf io_indata27 (.pad(indata[27]), .clk(clock), .outsig(test_pattern[11]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:142: Cannot find file containing module: \'outbuf\'\noutbuf io_indata26 (.pad(indata[26]), .clk(clock), .outsig(test_pattern[10]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:143: Cannot find file containing module: \'outbuf\'\noutbuf io_indata25 (.pad(indata[25]), .clk(clock), .outsig(test_pattern[9]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:144: Cannot find file containing module: \'outbuf\'\noutbuf io_indata24 (.pad(indata[24]), .clk(clock), .outsig(test_pattern[8]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:145: Cannot find file containing module: \'outbuf\'\noutbuf io_indata23 (.pad(indata[23]), .clk(clock), .outsig(test_pattern[7]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:146: Cannot find file containing module: \'outbuf\'\noutbuf io_indata22 (.pad(indata[22]), .clk(clock), .outsig(test_pattern[6]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:147: Cannot find file containing module: \'outbuf\'\noutbuf io_indata21 (.pad(indata[21]), .clk(clock), .outsig(test_pattern[5]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:148: Cannot find file containing module: \'outbuf\'\noutbuf io_indata20 (.pad(indata[20]), .clk(clock), .outsig(test_pattern[4]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:149: Cannot find file containing module: \'outbuf\'\noutbuf io_indata19 (.pad(indata[19]), .clk(clock), .outsig(test_pattern[3]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:150: Cannot find file containing module: \'outbuf\'\noutbuf io_indata18 (.pad(indata[18]), .clk(clock), .outsig(test_pattern[2]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:151: Cannot find file containing module: \'outbuf\'\noutbuf io_indata17 (.pad(indata[17]), .clk(clock), .outsig(test_pattern[1]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:152: Cannot find file containing module: \'outbuf\'\noutbuf io_indata16 (.pad(indata[16]), .clk(clock), .outsig(test_pattern[0]), .oe(extTestMode));\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:177: Cannot find file containing module: \'serial\'\nserial #(.FREQ(FREQ), .RATE(RATE)) serial (\n^~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:195: Cannot find file containing module: \'core\'\ncore #(.MEMORY_DEPTH(MEMORY_DEPTH)) core (\n^~~~\n%Error: data/full_repos/permissive/106408053/verilog/Logic_Sniffer.v:224: Cannot find file containing module: \'sram_interface\'\nsram_interface sram_interface (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,501 | module | module Logic_Sniffer(
bf_clock,
extClockIn,
extClockOut,
extTriggerIn,
extTriggerOut,
indata,
`ifdef COMM_TYPE_SPI
miso, mosi, sclk, cs,
`else
rx, tx,
`endif
dataReady,
armLEDnn,
triggerLEDnn);
parameter [31:0] MEMORY_DEPTH=6;
parameter [31:0] CLOCK_SPEED=50;
parameter [1:0] SPEED=2'b00;
input bf_clock;
input extClockIn;
output extClockOut;
input extTriggerIn;
output extTriggerOut;
inout [31:0] indata;
output dataReady;
output armLEDnn;
output triggerLEDnn;
`ifdef COMM_TYPE_SPI
output miso;
input mosi;
input sclk;
input cs;
`else
input rx;
output tx;
`endif
parameter FREQ = 100000000;
parameter TRXSCALE = 28;
parameter RATE = 921600;
wire extReset = 1'b0;
wire [39:0] cmd;
wire [31:0] sram_wrdata;
wire [35:0] sram_rddata;
wire [3:0] sram_rdvalid;
wire [31:0] stableInput;
wire [7:0] opcode;
wire [31:0] config_data;
assign {config_data,opcode} = cmd;
pll_wrapper pll_wrapper ( .clkin(bf_clock), .clk0(clock));
dly_signal dataReady_reg (clock, busy, dataReady);
ddr_clkout extclock_pad (.pad(extClockOut), .clk(extclock));
reg [10:0] test_counter, next_test_counter;
always @ (posedge clock)
begin
test_counter = next_test_counter;
end
always @*
begin
#1;
next_test_counter = test_counter+1'b1;
end
wire [15:0] test_pattern = {
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4]};
outbuf io_indata31 (.pad(indata[31]), .clk(clock), .outsig(test_pattern[15]), .oe(extTestMode));
outbuf io_indata30 (.pad(indata[30]), .clk(clock), .outsig(test_pattern[14]), .oe(extTestMode));
outbuf io_indata29 (.pad(indata[29]), .clk(clock), .outsig(test_pattern[13]), .oe(extTestMode));
outbuf io_indata28 (.pad(indata[28]), .clk(clock), .outsig(test_pattern[12]), .oe(extTestMode));
outbuf io_indata27 (.pad(indata[27]), .clk(clock), .outsig(test_pattern[11]), .oe(extTestMode));
outbuf io_indata26 (.pad(indata[26]), .clk(clock), .outsig(test_pattern[10]), .oe(extTestMode));
outbuf io_indata25 (.pad(indata[25]), .clk(clock), .outsig(test_pattern[9]), .oe(extTestMode));
outbuf io_indata24 (.pad(indata[24]), .clk(clock), .outsig(test_pattern[8]), .oe(extTestMode));
outbuf io_indata23 (.pad(indata[23]), .clk(clock), .outsig(test_pattern[7]), .oe(extTestMode));
outbuf io_indata22 (.pad(indata[22]), .clk(clock), .outsig(test_pattern[6]), .oe(extTestMode));
outbuf io_indata21 (.pad(indata[21]), .clk(clock), .outsig(test_pattern[5]), .oe(extTestMode));
outbuf io_indata20 (.pad(indata[20]), .clk(clock), .outsig(test_pattern[4]), .oe(extTestMode));
outbuf io_indata19 (.pad(indata[19]), .clk(clock), .outsig(test_pattern[3]), .oe(extTestMode));
outbuf io_indata18 (.pad(indata[18]), .clk(clock), .outsig(test_pattern[2]), .oe(extTestMode));
outbuf io_indata17 (.pad(indata[17]), .clk(clock), .outsig(test_pattern[1]), .oe(extTestMode));
outbuf io_indata16 (.pad(indata[16]), .clk(clock), .outsig(test_pattern[0]), .oe(extTestMode));
`ifdef COMM_TYPE_SPI
spi_slave spi_slave (
.clock(clock),
.extReset(extReset),
.sclk(sclk),
.cs(cs),
.mosi(mosi),
.dataIn(stableInput),
.send(send),
.send_data(sram_rddata[31:0]),
.send_valid(sram_rdvalid),
.cmd(cmd), .execute(execute),
.busy(busy), .miso(miso));
`else
serial #(.FREQ(FREQ), .RATE(RATE)) serial (
.clock(clock),
.extReset(extReset),
.rx(rx),
.dataIn(stableInput),
.send(send),
.send_data(sram_rddata[31:0]),
.send_valid(sram_rdvalid),
.cmd(cmd), .execute(execute),
.busy(busy), .tx(tx));
`endif
core #(.MEMORY_DEPTH(MEMORY_DEPTH)) core (
.clock(clock),
.extReset(extReset),
.extClock(extClockIn),
.extTriggerIn(extTriggerIn),
.opcode(opcode),
.config_data(config_data),
.execute(execute),
.indata(indata),
.outputBusy(busy),
.sampleReady50(),
.stableInput(stableInput),
.outputSend(send),
.memoryWrData(sram_wrdata),
.memoryRead(read),
.memoryWrite(write),
.memoryLastWrite(lastwrite),
.extTriggerOut(extTriggerOut),
.extClockOut(extclock),
.armLEDnn(armLEDnn),
.triggerLEDnn(triggerLEDnn),
.wrFlags(wrFlags),
.extTestMode(extTestMode));
sram_interface sram_interface (
.clk(clock),
.wrFlags(wrFlags),
.config_data(config_data[5:2]),
.write(write), .lastwrite(lastwrite), .read(read),
.wrdata({4'h0,sram_wrdata}),
.rddata(sram_rddata),
.rdvalid(sram_rdvalid));
endmodule | module Logic_Sniffer(
bf_clock,
extClockIn,
extClockOut,
extTriggerIn,
extTriggerOut,
indata,
`ifdef COMM_TYPE_SPI
miso, mosi, sclk, cs,
`else
rx, tx,
`endif
dataReady,
armLEDnn,
triggerLEDnn); |
parameter [31:0] MEMORY_DEPTH=6;
parameter [31:0] CLOCK_SPEED=50;
parameter [1:0] SPEED=2'b00;
input bf_clock;
input extClockIn;
output extClockOut;
input extTriggerIn;
output extTriggerOut;
inout [31:0] indata;
output dataReady;
output armLEDnn;
output triggerLEDnn;
`ifdef COMM_TYPE_SPI
output miso;
input mosi;
input sclk;
input cs;
`else
input rx;
output tx;
`endif
parameter FREQ = 100000000;
parameter TRXSCALE = 28;
parameter RATE = 921600;
wire extReset = 1'b0;
wire [39:0] cmd;
wire [31:0] sram_wrdata;
wire [35:0] sram_rddata;
wire [3:0] sram_rdvalid;
wire [31:0] stableInput;
wire [7:0] opcode;
wire [31:0] config_data;
assign {config_data,opcode} = cmd;
pll_wrapper pll_wrapper ( .clkin(bf_clock), .clk0(clock));
dly_signal dataReady_reg (clock, busy, dataReady);
ddr_clkout extclock_pad (.pad(extClockOut), .clk(extclock));
reg [10:0] test_counter, next_test_counter;
always @ (posedge clock)
begin
test_counter = next_test_counter;
end
always @*
begin
#1;
next_test_counter = test_counter+1'b1;
end
wire [15:0] test_pattern = {
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4],
test_counter[10], test_counter[4]};
outbuf io_indata31 (.pad(indata[31]), .clk(clock), .outsig(test_pattern[15]), .oe(extTestMode));
outbuf io_indata30 (.pad(indata[30]), .clk(clock), .outsig(test_pattern[14]), .oe(extTestMode));
outbuf io_indata29 (.pad(indata[29]), .clk(clock), .outsig(test_pattern[13]), .oe(extTestMode));
outbuf io_indata28 (.pad(indata[28]), .clk(clock), .outsig(test_pattern[12]), .oe(extTestMode));
outbuf io_indata27 (.pad(indata[27]), .clk(clock), .outsig(test_pattern[11]), .oe(extTestMode));
outbuf io_indata26 (.pad(indata[26]), .clk(clock), .outsig(test_pattern[10]), .oe(extTestMode));
outbuf io_indata25 (.pad(indata[25]), .clk(clock), .outsig(test_pattern[9]), .oe(extTestMode));
outbuf io_indata24 (.pad(indata[24]), .clk(clock), .outsig(test_pattern[8]), .oe(extTestMode));
outbuf io_indata23 (.pad(indata[23]), .clk(clock), .outsig(test_pattern[7]), .oe(extTestMode));
outbuf io_indata22 (.pad(indata[22]), .clk(clock), .outsig(test_pattern[6]), .oe(extTestMode));
outbuf io_indata21 (.pad(indata[21]), .clk(clock), .outsig(test_pattern[5]), .oe(extTestMode));
outbuf io_indata20 (.pad(indata[20]), .clk(clock), .outsig(test_pattern[4]), .oe(extTestMode));
outbuf io_indata19 (.pad(indata[19]), .clk(clock), .outsig(test_pattern[3]), .oe(extTestMode));
outbuf io_indata18 (.pad(indata[18]), .clk(clock), .outsig(test_pattern[2]), .oe(extTestMode));
outbuf io_indata17 (.pad(indata[17]), .clk(clock), .outsig(test_pattern[1]), .oe(extTestMode));
outbuf io_indata16 (.pad(indata[16]), .clk(clock), .outsig(test_pattern[0]), .oe(extTestMode));
`ifdef COMM_TYPE_SPI
spi_slave spi_slave (
.clock(clock),
.extReset(extReset),
.sclk(sclk),
.cs(cs),
.mosi(mosi),
.dataIn(stableInput),
.send(send),
.send_data(sram_rddata[31:0]),
.send_valid(sram_rdvalid),
.cmd(cmd), .execute(execute),
.busy(busy), .miso(miso));
`else
serial #(.FREQ(FREQ), .RATE(RATE)) serial (
.clock(clock),
.extReset(extReset),
.rx(rx),
.dataIn(stableInput),
.send(send),
.send_data(sram_rddata[31:0]),
.send_valid(sram_rdvalid),
.cmd(cmd), .execute(execute),
.busy(busy), .tx(tx));
`endif
core #(.MEMORY_DEPTH(MEMORY_DEPTH)) core (
.clock(clock),
.extReset(extReset),
.extClock(extClockIn),
.extTriggerIn(extTriggerIn),
.opcode(opcode),
.config_data(config_data),
.execute(execute),
.indata(indata),
.outputBusy(busy),
.sampleReady50(),
.stableInput(stableInput),
.outputSend(send),
.memoryWrData(sram_wrdata),
.memoryRead(read),
.memoryWrite(write),
.memoryLastWrite(lastwrite),
.extTriggerOut(extTriggerOut),
.extClockOut(extclock),
.armLEDnn(armLEDnn),
.triggerLEDnn(triggerLEDnn),
.wrFlags(wrFlags),
.extTestMode(extTestMode));
sram_interface sram_interface (
.clk(clock),
.wrFlags(wrFlags),
.config_data(config_data[5:2]),
.write(write), .lastwrite(lastwrite), .read(read),
.wrdata({4'h0,sram_wrdata}),
.rddata(sram_rddata),
.rdvalid(sram_rdvalid));
endmodule | 6 |
3,714 | data/full_repos/permissive/106408053/verilog/sampler.v | 106,408,053 | sampler.v | v | 150 | 92 | [] | ['general public license', 'free software foundation'] | [] | [(43, 148)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sampler.v:96: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sampler.v:139: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/sampler.v:145: Operator EQ expects 24 bits on the RHS, but RHS\'s SEL generates 23 bits.\n : ... In instance sampler\n else if (counter == divider[23:1])\n ^~\n%Error: Exiting due to 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,505 | module | module sampler (
clock, extClock_mode,
wrDivider, config_data,
validIn, dataIn,
validOut, dataOut, ready50);
input clock;
input extClock_mode;
input wrDivider;
input [23:0] config_data;
input validIn;
input [31:0] dataIn;
output validOut;
output [31:0] dataOut;
output ready50;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
reg validOut, next_validOut;
reg [31:0] dataOut, next_dataOut;
reg ready50, next_ready50;
reg [23:0] divider, next_divider;
reg [23:0] counter, next_counter;
wire counter_zero = ~|counter;
initial
begin
divider = 0;
counter = 0;
validOut = 0;
dataOut = 0;
end
always @ (posedge clock)
begin
divider = next_divider;
counter = next_counter;
validOut = next_validOut;
dataOut = next_dataOut;
end
always @*
begin
#1;
next_divider = divider;
next_counter = counter;
next_validOut = FALSE;
next_dataOut = dataOut;
if (extClock_mode)
begin
next_validOut = validIn;
next_dataOut = dataIn;
end
else if (validIn && counter_zero)
begin
next_validOut = TRUE;
next_dataOut = dataIn;
end
if (wrDivider)
begin
next_divider = config_data[23:0];
next_counter = next_divider;
next_validOut = FALSE;
end
else if (validIn)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
always @(posedge clock)
begin
ready50 = next_ready50;
end
always @*
begin
#1;
next_ready50 = ready50;
if (wrDivider)
next_ready50 = FALSE;
else if (counter_zero)
next_ready50 = TRUE;
else if (counter == divider[23:1])
next_ready50 = FALSE;
end
endmodule | module sampler (
clock, extClock_mode,
wrDivider, config_data,
validIn, dataIn,
validOut, dataOut, ready50); |
input clock;
input extClock_mode;
input wrDivider;
input [23:0] config_data;
input validIn;
input [31:0] dataIn;
output validOut;
output [31:0] dataOut;
output ready50;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
reg validOut, next_validOut;
reg [31:0] dataOut, next_dataOut;
reg ready50, next_ready50;
reg [23:0] divider, next_divider;
reg [23:0] counter, next_counter;
wire counter_zero = ~|counter;
initial
begin
divider = 0;
counter = 0;
validOut = 0;
dataOut = 0;
end
always @ (posedge clock)
begin
divider = next_divider;
counter = next_counter;
validOut = next_validOut;
dataOut = next_dataOut;
end
always @*
begin
#1;
next_divider = divider;
next_counter = counter;
next_validOut = FALSE;
next_dataOut = dataOut;
if (extClock_mode)
begin
next_validOut = validIn;
next_dataOut = dataIn;
end
else if (validIn && counter_zero)
begin
next_validOut = TRUE;
next_dataOut = dataIn;
end
if (wrDivider)
begin
next_divider = config_data[23:0];
next_counter = next_divider;
next_validOut = FALSE;
end
else if (validIn)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
always @(posedge clock)
begin
ready50 = next_ready50;
end
always @*
begin
#1;
next_ready50 = ready50;
if (wrDivider)
next_ready50 = FALSE;
else if (counter_zero)
next_ready50 = TRUE;
else if (counter == divider[23:1])
next_ready50 = FALSE;
end
endmodule | 6 |
3,715 | data/full_repos/permissive/106408053/verilog/serial.v | 106,408,053 | serial.v | v | 137 | 82 | [] | ['general public license', 'free software foundation'] | [] | [(35, 136)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial.v:123: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/serial.v:80: Cannot find file containing module: \'full_synchronizer\'\nfull_synchronizer rx_sync (clock, extReset, rx, sync_rx);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer.sv\n full_synchronizer\n full_synchronizer.v\n full_synchronizer.sv\n obj_dir/full_synchronizer\n obj_dir/full_synchronizer.v\n obj_dir/full_synchronizer.sv\n%Error: data/full_repos/permissive/106408053/verilog/serial.v:87: Cannot find file containing module: \'meta_handler\'\nmeta_handler meta_handler(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/serial.v:96: Cannot find file containing module: \'serial_receiver\'\nserial_receiver #(.FREQ(FREQ), .RATE(RATE)) serial_receiver(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/serial.v:101: Cannot find file containing module: \'serial_transmitter\'\nserial_transmitter #(.FREQ(FREQ), .RATE(RATE)) serial_transmitter(\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,506 | module | module serial(
clock, extReset,
rx, dataIn,
send, send_data, send_valid,
cmd, execute, busy, tx);
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input [31:0] dataIn;
input rx;
output [39:0] cmd;
output execute;
output busy;
output tx;
wire [39:0] cmd;
wire execute;
wire busy;
wire tx;
reg query_id, next_query_id;
reg query_metadata, next_query_metadata;
reg query_dataIn, next_query_dataIn;
reg dly_execute, next_dly_execute;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
full_synchronizer rx_sync (clock, extReset, rx, sync_rx);
wire [7:0] meta_data;
meta_handler meta_handler(
.clock(clock), .extReset(extReset),
.query_metadata(query_metadata), .xmit_idle(!busy && !send && byteDone),
.writeMeta(writeMeta), .meta_data(meta_data));
serial_receiver #(.FREQ(FREQ), .RATE(RATE)) serial_receiver(
.clock(clock), .extReset(extReset),
.rx(sync_rx), .transmitting(busy),
.op(opcode), .data(opdata), .execute(execute));
serial_transmitter #(.FREQ(FREQ), .RATE(RATE)) serial_transmitter(
.clock(clock), .extReset(extReset),
.send(send), .send_data(send_data), .send_valid(send_valid),
.writeMeta(writeMeta), .meta_data(meta_data),
.query_id(query_id),
.query_dataIn(query_dataIn), .dataIn(dataIn),
.tx(tx), .busy(busy), .byteDone(byteDone));
always @(posedge clock)
begin
query_id = next_query_id;
query_metadata = next_query_metadata;
query_dataIn = next_query_dataIn;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_query_id = 1'b0;
next_query_metadata = 1'b0;
next_query_dataIn = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case (opcode)
8'h02 : next_query_id = 1'b1;
8'h04 : next_query_metadata = 1'b1;
8'h06 : next_query_dataIn = 1'b1;
endcase
end
endmodule | module serial(
clock, extReset,
rx, dataIn,
send, send_data, send_valid,
cmd, execute, busy, tx); |
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input [31:0] dataIn;
input rx;
output [39:0] cmd;
output execute;
output busy;
output tx;
wire [39:0] cmd;
wire execute;
wire busy;
wire tx;
reg query_id, next_query_id;
reg query_metadata, next_query_metadata;
reg query_dataIn, next_query_dataIn;
reg dly_execute, next_dly_execute;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
full_synchronizer rx_sync (clock, extReset, rx, sync_rx);
wire [7:0] meta_data;
meta_handler meta_handler(
.clock(clock), .extReset(extReset),
.query_metadata(query_metadata), .xmit_idle(!busy && !send && byteDone),
.writeMeta(writeMeta), .meta_data(meta_data));
serial_receiver #(.FREQ(FREQ), .RATE(RATE)) serial_receiver(
.clock(clock), .extReset(extReset),
.rx(sync_rx), .transmitting(busy),
.op(opcode), .data(opdata), .execute(execute));
serial_transmitter #(.FREQ(FREQ), .RATE(RATE)) serial_transmitter(
.clock(clock), .extReset(extReset),
.send(send), .send_data(send_data), .send_valid(send_valid),
.writeMeta(writeMeta), .meta_data(meta_data),
.query_id(query_id),
.query_dataIn(query_dataIn), .dataIn(dataIn),
.tx(tx), .busy(busy), .byteDone(byteDone));
always @(posedge clock)
begin
query_id = next_query_id;
query_metadata = next_query_metadata;
query_dataIn = next_query_dataIn;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_query_id = 1'b0;
next_query_metadata = 1'b0;
next_query_dataIn = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case (opcode)
8'h02 : next_query_id = 1'b1;
8'h04 : next_query_metadata = 1'b1;
8'h06 : next_query_dataIn = 1'b1;
endcase
end
endmodule | 6 |
3,716 | data/full_repos/permissive/106408053/verilog/serial_receiver.v | 106,408,053 | serial_receiver.v | v | 219 | 85 | [] | ['general public license', 'free software foundation'] | [] | [(44, 217)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_receiver.v:111: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_receiver.v:178: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:127: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n : ... In instance serial_receiver\n if (rx_count == BITLENGTH/2 - 1) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:138: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n : ... In instance serial_receiver\n if (rx_count == BITLENGTH - 1) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:148: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n : ... In instance serial_receiver\n if (rx_count == BITLENGTH - 1) begin\n ^~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,507 | module | module serial_receiver(
clock, extReset,
rx, transmitting,
op, data, execute);
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input rx;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;
parameter
READOPCODE = 1'h0,
READLONG = 1'h1;
parameter [1:0]
RX_IDLE = 2'h0,
RX_START = 2'h1,
RX_RECEIVE = 2'h2,
RX_STOP = 2'h3;
parameter BITLENGTH = FREQ / RATE;
reg state, next_state;
reg [1:0] bytecount, next_bytecount;
reg [7:0] opcode, next_opcode;
reg [31:0] databuf, next_databuf;
reg execute, next_execute;
reg [1:0] rx_state, next_rx_state;
reg [9:0] rx_count, next_rx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] rxByte, next_rxByte;
reg byteready, next_byteready;
assign op = opcode;
assign data = databuf;
always @(posedge clock or posedge extReset)
begin
if (extReset) begin
rx_state = RX_IDLE;
bitcount = 3'b0;
rxByte = 8'b0;
byteready = 1'b0;
rx_count = 10'd0;
end else begin
rx_state = next_rx_state;
bitcount = next_bitcount;
rxByte = next_rxByte;
byteready = next_byteready;
rx_count = next_rx_count;
end
end
always @*
begin
#1;
next_rx_state = rx_state;
next_bitcount = bitcount;
next_rxByte = rxByte;
next_byteready = 1'b0;
next_rx_count = 0;
case(rx_state)
RX_IDLE: begin
if (!rx & !transmitting) begin
next_rx_state = RX_START;
end
end
RX_START: begin
if (!rx) begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH/2 - 1) begin
next_rx_state = RX_RECEIVE;
next_rx_count = 0;
next_rxByte = 8'b0;
end
end else begin
next_rx_state = RX_IDLE;
end
end
RX_RECEIVE: begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH - 1) begin
next_rx_count = 0;
next_bitcount = bitcount + 1'b1;
next_rxByte = {rx, rxByte[7:1]};
if (bitcount == 3'd7)
next_rx_state = RX_STOP;
end
end
RX_STOP: begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH - 1) begin
next_rx_count = 0;
next_byteready = 1'b1;
next_rx_state = RX_IDLE;
end
end
endcase
end
always @(posedge clock or posedge extReset)
begin
if (extReset)
state = READOPCODE;
else state = next_state;
end
initial databuf = 0;
always @(posedge clock)
begin
bytecount = next_bytecount;
opcode = next_opcode;
databuf = next_databuf;
execute = next_execute;
end
always @*
begin
#1;
next_state = state;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case (state)
READOPCODE :
begin
next_bytecount = 0;
if (byteready)
begin
next_opcode = rxByte;
if (rxByte[7])
next_state = READLONG;
else
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
READLONG :
begin
if (byteready)
begin
next_bytecount = bytecount + 1'b1;
next_databuf = {rxByte,databuf[31:8]};
if (&bytecount)
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
endcase
end
endmodule | module serial_receiver(
clock, extReset,
rx, transmitting,
op, data, execute); |
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input rx;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;
parameter
READOPCODE = 1'h0,
READLONG = 1'h1;
parameter [1:0]
RX_IDLE = 2'h0,
RX_START = 2'h1,
RX_RECEIVE = 2'h2,
RX_STOP = 2'h3;
parameter BITLENGTH = FREQ / RATE;
reg state, next_state;
reg [1:0] bytecount, next_bytecount;
reg [7:0] opcode, next_opcode;
reg [31:0] databuf, next_databuf;
reg execute, next_execute;
reg [1:0] rx_state, next_rx_state;
reg [9:0] rx_count, next_rx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] rxByte, next_rxByte;
reg byteready, next_byteready;
assign op = opcode;
assign data = databuf;
always @(posedge clock or posedge extReset)
begin
if (extReset) begin
rx_state = RX_IDLE;
bitcount = 3'b0;
rxByte = 8'b0;
byteready = 1'b0;
rx_count = 10'd0;
end else begin
rx_state = next_rx_state;
bitcount = next_bitcount;
rxByte = next_rxByte;
byteready = next_byteready;
rx_count = next_rx_count;
end
end
always @*
begin
#1;
next_rx_state = rx_state;
next_bitcount = bitcount;
next_rxByte = rxByte;
next_byteready = 1'b0;
next_rx_count = 0;
case(rx_state)
RX_IDLE: begin
if (!rx & !transmitting) begin
next_rx_state = RX_START;
end
end
RX_START: begin
if (!rx) begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH/2 - 1) begin
next_rx_state = RX_RECEIVE;
next_rx_count = 0;
next_rxByte = 8'b0;
end
end else begin
next_rx_state = RX_IDLE;
end
end
RX_RECEIVE: begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH - 1) begin
next_rx_count = 0;
next_bitcount = bitcount + 1'b1;
next_rxByte = {rx, rxByte[7:1]};
if (bitcount == 3'd7)
next_rx_state = RX_STOP;
end
end
RX_STOP: begin
next_rx_count = rx_count + 1'b1;
if (rx_count == BITLENGTH - 1) begin
next_rx_count = 0;
next_byteready = 1'b1;
next_rx_state = RX_IDLE;
end
end
endcase
end
always @(posedge clock or posedge extReset)
begin
if (extReset)
state = READOPCODE;
else state = next_state;
end
initial databuf = 0;
always @(posedge clock)
begin
bytecount = next_bytecount;
opcode = next_opcode;
databuf = next_databuf;
execute = next_execute;
end
always @*
begin
#1;
next_state = state;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case (state)
READOPCODE :
begin
next_bytecount = 0;
if (byteready)
begin
next_opcode = rxByte;
if (rxByte[7])
next_state = READLONG;
else
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
READLONG :
begin
if (byteready)
begin
next_bytecount = bytecount + 1'b1;
next_databuf = {rxByte,databuf[31:8]};
if (&bytecount)
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
endcase
end
endmodule | 6 |
3,717 | data/full_repos/permissive/106408053/verilog/serial_transmitter.v | 106,408,053 | serial_transmitter.v | v | 278 | 89 | [] | ['general public license', 'free software foundation'] | [] | [(37, 276)] | null | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:89: syntax error, unexpected byte, expecting IDENTIFIER or \'=\' or do or final\nreg [7:0] byte;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:93: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:94: syntax error, unexpected \'=\', expecting "\'{"\n byte = 0;\n ^\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:97: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:98: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:99: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:100: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end\n ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:129: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:144: syntax error, unexpected \';\', expecting "\'{"\n next_txByte = writeMeta ? meta_data : byte;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_transmitter.v:219: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n' | 1,508 | module | module serial_transmitter(
clock, extReset,
send, send_data, send_valid,
writeMeta, meta_data,
query_id, query_dataIn, dataIn,
tx, busy, byteDone);
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;
parameter [1:0]
TX_IDLE = 2'h0,
TX_START = 2'h1,
TX_SEND = 2'h2,
TX_STOP = 2'h3;
parameter BITLENGTH = FREQ / RATE;
reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg busy, next_busy;
reg writeByte;
reg [1:0] tx_state, next_tx_state;
reg [9:0] tx_count, next_tx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] txByte, next_txByte;
reg tx, next_tx;
reg byteDone, next_byteDone;
reg [7:0] byte;
reg disabled;
always @*
begin
#1;
byte = 0;
disabled = 0;
case (bytesel)
2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
endcase
end
always @(posedge clock or posedge extReset)
begin
if (extReset) begin
tx_state = TX_IDLE;
bitcount = 3'b0;
txByte = 8'b0;
byteDone = 1'b1;
tx_count = 10'd0;
tx = 1'b1;
end else begin
tx_state = next_tx_state;
bitcount = next_bitcount;
txByte = next_txByte;
byteDone = next_byteDone;
tx_count = next_tx_count;
tx = next_tx;
end
end
always @*
begin
#1;
next_tx_state = tx_state;
next_bitcount = bitcount;
next_txByte = txByte;
next_byteDone = 1'b1;
next_tx_count = 0;
next_tx = tx;
case(tx_state)
TX_IDLE: begin
next_tx = 1'b1;
next_bitcount = 0;
if ((writeByte & !disabled) | writeMeta) begin
next_tx_state = TX_START;
next_byteDone = 0;
next_txByte = writeMeta ? meta_data : byte;
next_tx = 1'b0;
end
end
TX_START: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_state = TX_SEND;
next_tx_count = 0;
next_tx = txByte[0];
next_txByte = {1'b0, txByte[7:1]};
end
end
TX_SEND: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_count = 0;
next_bitcount = bitcount + 1'b1;
if (bitcount == 3'd7) begin
next_tx_state = TX_STOP;
next_tx = 1'b1;
end else begin
next_tx = txByte[0];
next_txByte = {1'b0, txByte[7:1]};
end
end
end
TX_STOP: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_count = 0;
next_bitcount = bitcount + 1'b1;
if (bitcount == 3'd1) begin
next_tx_state = TX_IDLE;
next_byteDone = 1'b1;
end
end
end
endcase
end
parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;
initial state = INIT;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = INIT;
sampled_send_data = 32'h0;
sampled_send_valid = 4'h0;
bytesel = 3'h0;
busy = 1'b0;
end
else
begin
state = next_state;
sampled_send_data = next_sampled_send_data;
sampled_send_valid = next_sampled_send_valid;
bytesel = next_bytesel;
busy = next_busy;
end
end
always @*
begin
#1;
next_state = state;
next_sampled_send_data = sampled_send_data;
next_sampled_send_valid = sampled_send_valid;
next_bytesel = bytesel;
next_busy = (state != IDLE) || send || !byteDone;
writeByte = 1'b0;
case (state)
INIT :
begin
next_sampled_send_data = 32'h0;
next_sampled_send_valid = 4'hF;
next_bytesel = 3'h0;
next_busy = 1'b0;
next_state = IDLE;
end
IDLE :
begin
next_sampled_send_data = send_data;
next_sampled_send_valid = send_valid;
next_bytesel = 0;
if (send)
next_state = SEND;
else if (query_id)
begin
next_sampled_send_data = 32'h534c4131;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
else if (query_dataIn)
begin
next_sampled_send_data = dataIn;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
end
SEND :
begin
writeByte = 1'b1;
next_bytesel = bytesel + 1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone)
next_state = (~|bytesel) ? IDLE : SEND;
end
default : next_state = INIT;
endcase
end
endmodule | module serial_transmitter(
clock, extReset,
send, send_data, send_valid,
writeMeta, meta_data,
query_id, query_dataIn, dataIn,
tx, busy, byteDone); |
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;
parameter [1:0]
TX_IDLE = 2'h0,
TX_START = 2'h1,
TX_SEND = 2'h2,
TX_STOP = 2'h3;
parameter BITLENGTH = FREQ / RATE;
reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg busy, next_busy;
reg writeByte;
reg [1:0] tx_state, next_tx_state;
reg [9:0] tx_count, next_tx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] txByte, next_txByte;
reg tx, next_tx;
reg byteDone, next_byteDone;
reg [7:0] byte;
reg disabled;
always @*
begin
#1;
byte = 0;
disabled = 0;
case (bytesel)
2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
endcase
end
always @(posedge clock or posedge extReset)
begin
if (extReset) begin
tx_state = TX_IDLE;
bitcount = 3'b0;
txByte = 8'b0;
byteDone = 1'b1;
tx_count = 10'd0;
tx = 1'b1;
end else begin
tx_state = next_tx_state;
bitcount = next_bitcount;
txByte = next_txByte;
byteDone = next_byteDone;
tx_count = next_tx_count;
tx = next_tx;
end
end
always @*
begin
#1;
next_tx_state = tx_state;
next_bitcount = bitcount;
next_txByte = txByte;
next_byteDone = 1'b1;
next_tx_count = 0;
next_tx = tx;
case(tx_state)
TX_IDLE: begin
next_tx = 1'b1;
next_bitcount = 0;
if ((writeByte & !disabled) | writeMeta) begin
next_tx_state = TX_START;
next_byteDone = 0;
next_txByte = writeMeta ? meta_data : byte;
next_tx = 1'b0;
end
end
TX_START: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_state = TX_SEND;
next_tx_count = 0;
next_tx = txByte[0];
next_txByte = {1'b0, txByte[7:1]};
end
end
TX_SEND: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_count = 0;
next_bitcount = bitcount + 1'b1;
if (bitcount == 3'd7) begin
next_tx_state = TX_STOP;
next_tx = 1'b1;
end else begin
next_tx = txByte[0];
next_txByte = {1'b0, txByte[7:1]};
end
end
end
TX_STOP: begin
next_tx_count = tx_count + 1'b1;
next_byteDone = 0;
if (tx_count == BITLENGTH - 1) begin
next_tx_count = 0;
next_bitcount = bitcount + 1'b1;
if (bitcount == 3'd1) begin
next_tx_state = TX_IDLE;
next_byteDone = 1'b1;
end
end
end
endcase
end
parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;
initial state = INIT;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = INIT;
sampled_send_data = 32'h0;
sampled_send_valid = 4'h0;
bytesel = 3'h0;
busy = 1'b0;
end
else
begin
state = next_state;
sampled_send_data = next_sampled_send_data;
sampled_send_valid = next_sampled_send_valid;
bytesel = next_bytesel;
busy = next_busy;
end
end
always @*
begin
#1;
next_state = state;
next_sampled_send_data = sampled_send_data;
next_sampled_send_valid = sampled_send_valid;
next_bytesel = bytesel;
next_busy = (state != IDLE) || send || !byteDone;
writeByte = 1'b0;
case (state)
INIT :
begin
next_sampled_send_data = 32'h0;
next_sampled_send_valid = 4'hF;
next_bytesel = 3'h0;
next_busy = 1'b0;
next_state = IDLE;
end
IDLE :
begin
next_sampled_send_data = send_data;
next_sampled_send_valid = send_valid;
next_bytesel = 0;
if (send)
next_state = SEND;
else if (query_id)
begin
next_sampled_send_data = 32'h534c4131;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
else if (query_dataIn)
begin
next_sampled_send_data = dataIn;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
end
SEND :
begin
writeByte = 1'b1;
next_bytesel = bytesel + 1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone)
next_state = (~|bytesel) ? IDLE : SEND;
end
default : next_state = INIT;
endcase
end
endmodule | 6 |
3,719 | data/full_repos/permissive/106408053/verilog/spi_slave.v | 106,408,053 | spi_slave.v | v | 135 | 83 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_slave.v:121: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/spi_slave.v:77: Cannot find file containing module: \'full_synchronizer\'\nfull_synchronizer sclk_sync (clock, extReset, sclk, sync_sclk);\n^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/full_synchronizer.sv\n full_synchronizer\n full_synchronizer.v\n full_synchronizer.sv\n obj_dir/full_synchronizer\n obj_dir/full_synchronizer.v\n obj_dir/full_synchronizer.sv\n%Error: data/full_repos/permissive/106408053/verilog/spi_slave.v:78: Cannot find file containing module: \'full_synchronizer\'\nfull_synchronizer cs_sync (clock, extReset, cs, sync_cs);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_slave.v:85: Cannot find file containing module: \'meta_handler\'\nmeta_handler meta_handler(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_slave.v:94: Cannot find file containing module: \'spi_receiver\'\nspi_receiver spi_receiver(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_slave.v:99: Cannot find file containing module: \'spi_transmitter\'\nspi_transmitter spi_transmitter(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,510 | module | module spi_slave(
clock, extReset,
sclk, cs, mosi, dataIn,
send, send_data, send_valid,
cmd, execute, busy, miso);
input clock;
input sclk;
input extReset;
input cs;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input [31:0] dataIn;
input mosi;
output [39:0] cmd;
output execute;
output busy;
output miso;
wire [39:0] cmd;
wire execute;
wire busy;
wire miso;
reg query_id, next_query_id;
reg query_metadata, next_query_metadata;
reg query_dataIn, next_query_dataIn;
reg dly_execute, next_dly_execute;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
full_synchronizer sclk_sync (clock, extReset, sclk, sync_sclk);
full_synchronizer cs_sync (clock, extReset, cs, sync_cs);
wire [7:0] meta_data;
meta_handler meta_handler(
.clock(clock), .extReset(extReset),
.query_metadata(query_metadata), .xmit_idle(!busy && !send && byteDone),
.writeMeta(writeMeta), .meta_data(meta_data));
spi_receiver spi_receiver(
.clock(clock), .sclk(sync_sclk), .extReset(extReset),
.mosi(mosi), .cs(sync_cs), .transmitting(busy),
.op(opcode), .data(opdata), .execute(execute));
spi_transmitter spi_transmitter(
.clock(clock), .sclk(sync_sclk), .extReset(extReset),
.send(send), .send_data(send_data), .send_valid(send_valid),
.writeMeta(writeMeta), .meta_data(meta_data),
.cs(sync_cs), .query_id(query_id),
.query_dataIn(query_dataIn), .dataIn(dataIn),
.tx(miso), .busy(busy), .byteDone(byteDone));
always @(posedge clock)
begin
query_id = next_query_id;
query_metadata = next_query_metadata;
query_dataIn = next_query_dataIn;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_query_id = 1'b0;
next_query_metadata = 1'b0;
next_query_dataIn = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case (opcode)
8'h02 : next_query_id = 1'b1;
8'h04 : next_query_metadata = 1'b1;
8'h06 : next_query_dataIn = 1'b1;
endcase
end
endmodule | module spi_slave(
clock, extReset,
sclk, cs, mosi, dataIn,
send, send_data, send_valid,
cmd, execute, busy, miso); |
input clock;
input sclk;
input extReset;
input cs;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input [31:0] dataIn;
input mosi;
output [39:0] cmd;
output execute;
output busy;
output miso;
wire [39:0] cmd;
wire execute;
wire busy;
wire miso;
reg query_id, next_query_id;
reg query_metadata, next_query_metadata;
reg query_dataIn, next_query_dataIn;
reg dly_execute, next_dly_execute;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
full_synchronizer sclk_sync (clock, extReset, sclk, sync_sclk);
full_synchronizer cs_sync (clock, extReset, cs, sync_cs);
wire [7:0] meta_data;
meta_handler meta_handler(
.clock(clock), .extReset(extReset),
.query_metadata(query_metadata), .xmit_idle(!busy && !send && byteDone),
.writeMeta(writeMeta), .meta_data(meta_data));
spi_receiver spi_receiver(
.clock(clock), .sclk(sync_sclk), .extReset(extReset),
.mosi(mosi), .cs(sync_cs), .transmitting(busy),
.op(opcode), .data(opdata), .execute(execute));
spi_transmitter spi_transmitter(
.clock(clock), .sclk(sync_sclk), .extReset(extReset),
.send(send), .send_data(send_data), .send_valid(send_valid),
.writeMeta(writeMeta), .meta_data(meta_data),
.cs(sync_cs), .query_id(query_id),
.query_dataIn(query_dataIn), .dataIn(dataIn),
.tx(miso), .busy(busy), .byteDone(byteDone));
always @(posedge clock)
begin
query_id = next_query_id;
query_metadata = next_query_metadata;
query_dataIn = next_query_dataIn;
dly_execute = next_dly_execute;
end
always @*
begin
#1;
next_query_id = 1'b0;
next_query_metadata = 1'b0;
next_query_dataIn = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case (opcode)
8'h02 : next_query_id = 1'b1;
8'h04 : next_query_metadata = 1'b1;
8'h06 : next_query_dataIn = 1'b1;
endcase
end
endmodule | 6 |
3,720 | data/full_repos/permissive/106408053/verilog/spi_transmitter.v | 106,408,053 | spi_transmitter.v | v | 243 | 89 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xbd in position 1817: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:78: syntax error, unexpected byte, expecting IDENTIFIER or \'=\' or do or final\nreg [7:0] byte;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:83: syntax error, unexpected \'=\', expecting "\'{"\n byte = 0;\n ^\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:86: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:87: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:88: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:89: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n 2\'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end\n ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:109: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:126: syntax error, unexpected \';\', expecting "\'{"\n next_txBuffer = byte;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:181: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n' | 1,511 | module | module spi_transmitter(
clock, sclk, extReset,
send, send_data, send_valid,
writeMeta, meta_data,
cs, query_id, query_dataIn, dataIn,
tx, busy, byteDone);
input clock;
input sclk;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input cs;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;
reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg byteDone, next_byteDone;
reg dly_sclk, next_dly_sclk;
reg busy, next_busy;
reg [7:0] txBuffer, next_txBuffer;
reg tx, next_tx;
reg writeReset, writeByte;
reg [7:0] byte;
reg disabled;
always @*
begin
#1;
byte = 0;
disabled = 0;
case (bytesel)
2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
endcase
end
always @(posedge clock)
begin
dly_sclk = next_dly_sclk;
bits = next_bits;
byteDone = next_byteDone;
txBuffer = next_txBuffer;
tx = next_tx;
end
always @*
begin
#1;
next_dly_sclk = sclk;
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_tx = tx;
if (writeReset)
begin
next_bits = 0;
next_byteDone = 1'b1;
next_txBuffer = 8'hFF;
end
else if (writeByte)
begin
next_bits = 0;
next_byteDone = disabled;
next_txBuffer = byte;
end
else if (writeMeta)
begin
next_bits = 0;
next_byteDone = 0;
next_txBuffer = meta_data;
end
if (cs) next_bits = 0;
if (!cs && dly_sclk && !sclk && !byteDone)
begin
next_bits = bits + 1'b1;
next_byteDone = &bits;
end
next_tx = (cs || byteDone) ? 1'b1 : next_txBuffer[~bits];
end
parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;
initial state = INIT;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = INIT;
sampled_send_data = 32'h0;
sampled_send_valid = 4'h0;
bytesel = 3'h0;
busy = 1'b0;
end
else
begin
state = next_state;
sampled_send_data = next_sampled_send_data;
sampled_send_valid = next_sampled_send_valid;
bytesel = next_bytesel;
busy = next_busy;
end
end
always @*
begin
#1;
next_state = state;
next_sampled_send_data = sampled_send_data;
next_sampled_send_valid = sampled_send_valid;
next_bytesel = bytesel;
next_busy = (state != IDLE) || send || !byteDone;
writeReset = 1'b0;
writeByte = 1'b0;
case (state)
INIT :
begin
writeReset = 1'b1;
next_sampled_send_data = 32'h0;
next_sampled_send_valid = 4'hF;
next_bytesel = 3'h0;
next_busy = 1'b0;
next_state = IDLE;
end
IDLE :
begin
next_sampled_send_data = send_data;
next_sampled_send_valid = send_valid;
next_bytesel = 0;
if (send)
next_state = SEND;
else if (query_id)
begin
next_sampled_send_data = 32'h534c4131;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
else if (query_dataIn)
begin
next_sampled_send_data = dataIn;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
end
SEND :
begin
writeByte = 1'b1;
next_bytesel = bytesel + 1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone)
next_state = (~|bytesel) ? IDLE : SEND;
end
default : next_state = INIT;
endcase
end
endmodule | module spi_transmitter(
clock, sclk, extReset,
send, send_data, send_valid,
writeMeta, meta_data,
cs, query_id, query_dataIn, dataIn,
tx, busy, byteDone); |
input clock;
input sclk;
input extReset;
input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input cs;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;
reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg byteDone, next_byteDone;
reg dly_sclk, next_dly_sclk;
reg busy, next_busy;
reg [7:0] txBuffer, next_txBuffer;
reg tx, next_tx;
reg writeReset, writeByte;
reg [7:0] byte;
reg disabled;
always @*
begin
#1;
byte = 0;
disabled = 0;
case (bytesel)
2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
endcase
end
always @(posedge clock)
begin
dly_sclk = next_dly_sclk;
bits = next_bits;
byteDone = next_byteDone;
txBuffer = next_txBuffer;
tx = next_tx;
end
always @*
begin
#1;
next_dly_sclk = sclk;
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_tx = tx;
if (writeReset)
begin
next_bits = 0;
next_byteDone = 1'b1;
next_txBuffer = 8'hFF;
end
else if (writeByte)
begin
next_bits = 0;
next_byteDone = disabled;
next_txBuffer = byte;
end
else if (writeMeta)
begin
next_bits = 0;
next_byteDone = 0;
next_txBuffer = meta_data;
end
if (cs) next_bits = 0;
if (!cs && dly_sclk && !sclk && !byteDone)
begin
next_bits = bits + 1'b1;
next_byteDone = &bits;
end
next_tx = (cs || byteDone) ? 1'b1 : next_txBuffer[~bits];
end
parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;
initial state = INIT;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = INIT;
sampled_send_data = 32'h0;
sampled_send_valid = 4'h0;
bytesel = 3'h0;
busy = 1'b0;
end
else
begin
state = next_state;
sampled_send_data = next_sampled_send_data;
sampled_send_valid = next_sampled_send_valid;
bytesel = next_bytesel;
busy = next_busy;
end
end
always @*
begin
#1;
next_state = state;
next_sampled_send_data = sampled_send_data;
next_sampled_send_valid = sampled_send_valid;
next_bytesel = bytesel;
next_busy = (state != IDLE) || send || !byteDone;
writeReset = 1'b0;
writeByte = 1'b0;
case (state)
INIT :
begin
writeReset = 1'b1;
next_sampled_send_data = 32'h0;
next_sampled_send_valid = 4'hF;
next_bytesel = 3'h0;
next_busy = 1'b0;
next_state = IDLE;
end
IDLE :
begin
next_sampled_send_data = send_data;
next_sampled_send_valid = send_valid;
next_bytesel = 0;
if (send)
next_state = SEND;
else if (query_id)
begin
next_sampled_send_data = 32'h534c4131;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
else if (query_dataIn)
begin
next_sampled_send_data = dataIn;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
end
SEND :
begin
writeByte = 1'b1;
next_bytesel = bytesel + 1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone)
next_state = (~|bytesel) ? IDLE : SEND;
end
default : next_state = INIT;
endcase
end
endmodule | 6 |
3,721 | data/full_repos/permissive/106408053/verilog/sram_interface.v | 106,408,053 | sram_interface.v | v | 227 | 107 | [] | ['general public license', 'free software foundation'] | [] | [(40, 225)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sram_interface.v:104: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sram_interface.v:189: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/sram_interface.v:89: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance sram_interface\n rdvalid = 1\'b0;\n ^\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:203: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG0(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit.sv\n BRAM8k9bit\n BRAM8k9bit.v\n BRAM8k9bit.sv\n obj_dir/BRAM8k9bit\n obj_dir/BRAM8k9bit.v\n obj_dir/BRAM8k9bit.sv\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:208: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG1(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:213: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG2(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:218: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG3(\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,512 | module | module sram_interface(
clk, wrFlags, config_data,
write, lastwrite,
read, wrdata,
rddata, rdvalid);
input clk;
input wrFlags;
input [3:0] config_data;
input read, write, lastwrite;
input [`BRAM_MAXDATA:0] wrdata;
output [`BRAM_MAXDATA:0] rddata;
output [3:0] rdvalid;
wire [`BRAM_MAXDATA:0] wrdata;
wire [`BRAM_MAXDATA:0] ram_dataout;
reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;
reg [3:0] clkenb, next_clkenb;
reg [`BRAM_MAXINDEX:0] address, next_address;
reg [3:0] rdvalid, next_rdvalid;
wire maxaddr = &address[`BRAM_MAXINDEX:0];
wire addrzero = ~|address;
initial
begin
init = 1'b0;
mode = 2'b00;
validmask = 4'hF;
clkenb = 4'b1111;
address = 0;
rdvalid = 1'b0;
end
always @ (posedge clk)
begin
init = next_init;
mode = next_mode;
validmask = next_validmask;
clkenb = next_clkenb;
address = next_address;
rdvalid = next_rdvalid;
end
always @*
begin
#1;
next_init = 1'b0;
next_mode = mode;
next_validmask = validmask;
next_clkenb = clkenb;
next_address = address;
next_rdvalid = clkenb & validmask;
if (wrFlags)
begin
next_init = 1'b1;
next_mode = 0;
case (config_data)
4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
endcase
next_validmask = 4'hF;
case (config_data)
4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
endcase
end
casex ({write && !lastwrite, read})
2'b1x :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
end
2'bx1 :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[0]) next_address = (addrzero) ? `BRAM_MAX_ADDRESS : address-1'b1;
end
endcase
if (init)
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = 4'b0001;
2'b1x : next_clkenb = 4'b0011;
endcase
next_address = 0;
end
end
reg [`BRAM_MAXDATA:0] ram_datain;
always @*
begin
#1;
ram_datain = wrdata;
casex (mode[1:0])
2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
endcase
end
wire [`BRAM_MAXINDEX:0] #1 ram_ADDR = address;
wire #1 ram_WE = write;
BRAM8k9bit RAMBG0(
.CLK(clk), .WE(ram_WE), .EN(clkenb[0]), .ADDR(ram_ADDR),
.DIN(ram_datain[7:0]), .DOUT(ram_dataout[7:0]),
.DINP(ram_datain[32]), .DOUTP(ram_dataout[32]));
BRAM8k9bit RAMBG1(
.CLK(clk), .WE(ram_WE), .EN(clkenb[1]), .ADDR(ram_ADDR),
.DIN(ram_datain[15:8]), .DOUT(ram_dataout[15:8]),
.DINP(ram_datain[33]), .DOUTP(ram_dataout[33]));
BRAM8k9bit RAMBG2(
.CLK(clk), .WE(ram_WE), .EN(clkenb[2]), .ADDR(ram_ADDR),
.DIN(ram_datain[23:16]), .DOUT(ram_dataout[23:16]),
.DINP(ram_datain[34]), .DOUTP(ram_dataout[34]));
BRAM8k9bit RAMBG3(
.CLK(clk), .WE(ram_WE), .EN(clkenb[3]), .ADDR(ram_ADDR),
.DIN(ram_datain[31:24]), .DOUT(ram_dataout[31:24]),
.DINP(ram_datain[35]), .DOUTP(ram_dataout[35]));
assign rddata = ram_dataout;
endmodule | module sram_interface(
clk, wrFlags, config_data,
write, lastwrite,
read, wrdata,
rddata, rdvalid); |
input clk;
input wrFlags;
input [3:0] config_data;
input read, write, lastwrite;
input [`BRAM_MAXDATA:0] wrdata;
output [`BRAM_MAXDATA:0] rddata;
output [3:0] rdvalid;
wire [`BRAM_MAXDATA:0] wrdata;
wire [`BRAM_MAXDATA:0] ram_dataout;
reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;
reg [3:0] clkenb, next_clkenb;
reg [`BRAM_MAXINDEX:0] address, next_address;
reg [3:0] rdvalid, next_rdvalid;
wire maxaddr = &address[`BRAM_MAXINDEX:0];
wire addrzero = ~|address;
initial
begin
init = 1'b0;
mode = 2'b00;
validmask = 4'hF;
clkenb = 4'b1111;
address = 0;
rdvalid = 1'b0;
end
always @ (posedge clk)
begin
init = next_init;
mode = next_mode;
validmask = next_validmask;
clkenb = next_clkenb;
address = next_address;
rdvalid = next_rdvalid;
end
always @*
begin
#1;
next_init = 1'b0;
next_mode = mode;
next_validmask = validmask;
next_clkenb = clkenb;
next_address = address;
next_rdvalid = clkenb & validmask;
if (wrFlags)
begin
next_init = 1'b1;
next_mode = 0;
case (config_data)
4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
endcase
next_validmask = 4'hF;
case (config_data)
4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
endcase
end
casex ({write && !lastwrite, read})
2'b1x :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
end
2'bx1 :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
endcase
if (clkenb[0]) next_address = (addrzero) ? `BRAM_MAX_ADDRESS : address-1'b1;
end
endcase
if (init)
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = 4'b0001;
2'b1x : next_clkenb = 4'b0011;
endcase
next_address = 0;
end
end
reg [`BRAM_MAXDATA:0] ram_datain;
always @*
begin
#1;
ram_datain = wrdata;
casex (mode[1:0])
2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
endcase
end
wire [`BRAM_MAXINDEX:0] #1 ram_ADDR = address;
wire #1 ram_WE = write;
BRAM8k9bit RAMBG0(
.CLK(clk), .WE(ram_WE), .EN(clkenb[0]), .ADDR(ram_ADDR),
.DIN(ram_datain[7:0]), .DOUT(ram_dataout[7:0]),
.DINP(ram_datain[32]), .DOUTP(ram_dataout[32]));
BRAM8k9bit RAMBG1(
.CLK(clk), .WE(ram_WE), .EN(clkenb[1]), .ADDR(ram_ADDR),
.DIN(ram_datain[15:8]), .DOUT(ram_dataout[15:8]),
.DINP(ram_datain[33]), .DOUTP(ram_dataout[33]));
BRAM8k9bit RAMBG2(
.CLK(clk), .WE(ram_WE), .EN(clkenb[2]), .ADDR(ram_ADDR),
.DIN(ram_datain[23:16]), .DOUT(ram_dataout[23:16]),
.DINP(ram_datain[34]), .DOUTP(ram_dataout[34]));
BRAM8k9bit RAMBG3(
.CLK(clk), .WE(ram_WE), .EN(clkenb[3]), .ADDR(ram_ADDR),
.DIN(ram_datain[31:24]), .DOUT(ram_dataout[31:24]),
.DINP(ram_datain[35]), .DOUTP(ram_dataout[35]));
assign rddata = ram_dataout;
endmodule | 6 |
3,723 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module BUFG(I,O);
input I;
output O;
assign #1 O=I;
endmodule | module BUFG(I,O); |
input I;
output O;
assign #1 O=I;
endmodule | 6 |
3,724 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module BUFGMUX(O,I0,I1,S);
input I0,I1,S;
output O;
assign #1 O = (S) ? I1 : I0;
endmodule | module BUFGMUX(O,I0,I1,S); |
input I0,I1,S;
output O;
assign #1 O = (S) ? I1 : I0;
endmodule | 6 |
3,725 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);
input CLKIN, PSCLK, PSEN, PSINCDEC, RST, CLKFB;
output CLK2X, CLK0;
assign #1 CLK0 = CLKIN;
reg CLK2X;
initial CLK2X=0;
always @(posedge CLK0)
begin
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
#5;
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
end
endmodule | module DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB); |
input CLKIN, PSCLK, PSEN, PSINCDEC, RST, CLKFB;
output CLK2X, CLK0;
assign #1 CLK0 = CLKIN;
reg CLK2X;
initial CLK2X=0;
always @(posedge CLK0)
begin
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
#5;
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
end
endmodule | 6 |
3,726 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module ODDR2(Q,D0,D1,C0,C1);
input D0,D1,C0,C1;
output Q;
reg Q;
initial Q=0;
always @(posedge C0) Q=D0;
always @(posedge C1) Q=D1;
endmodule | module ODDR2(Q,D0,D1,C0,C1); |
input D0,D1,C0,C1;
output Q;
reg Q;
initial Q=0;
always @(posedge C0) Q=D0;
always @(posedge C1) Q=D1;
endmodule | 6 |
3,727 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);
input CLK, EN, SSR, WE;
input [10:0] ADDR;
input [7:0] DI;
input DIP;
output [7:0] DO;
output DOP;
parameter WRITE_MODE = 0;
wire [10:0] #1 dly_ADDR = ADDR;
wire [8:0] #1 dly_DATA = {DIP,DI};
wire #1 dly_EN = EN;
wire #1 dly_WE = WE;
reg [8:0] mem[0:2047];
reg [7:0] DO;
reg DOP;
reg sampled_EN;
reg [8:0] rddata;
integer i;
initial
begin
for (i=0; i<2048; i=i+1) mem[i] = 9'h15A;
end
always @(posedge CLK)
begin
if (dly_EN && dly_WE) mem[dly_ADDR] = dly_DATA;
rddata = mem[dly_ADDR];
sampled_EN = dly_EN;
#1;
if (sampled_EN) {DOP,DO} = rddata;
end
endmodule | module RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE); |
input CLK, EN, SSR, WE;
input [10:0] ADDR;
input [7:0] DI;
input DIP;
output [7:0] DO;
output DOP;
parameter WRITE_MODE = 0;
wire [10:0] #1 dly_ADDR = ADDR;
wire [8:0] #1 dly_DATA = {DIP,DI};
wire #1 dly_EN = EN;
wire #1 dly_WE = WE;
reg [8:0] mem[0:2047];
reg [7:0] DO;
reg DOP;
reg sampled_EN;
reg [8:0] rddata;
integer i;
initial
begin
for (i=0; i<2048; i=i+1) mem[i] = 9'h15A;
end
always @(posedge CLK)
begin
if (dly_EN && dly_WE) mem[dly_ADDR] = dly_DATA;
rddata = mem[dly_ADDR];
sampled_EN = dly_EN;
#1;
if (sampled_EN) {DOP,DO} = rddata;
end
endmodule | 6 |
3,728 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module RAM16X1S (A0,A1,A2,A3,WCLK,WE,D,O);
input A0,A1,A2,A3,WCLK,WE,D;
output O;
reg mem[0:15];
wire #1 dly_WE = WE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
always @(posedge WCLK)
begin
if (dly_WE) mem[dly_addr] = dly_D;
end
reg [3:0] rdaddr;
reg O;
always @*
begin
rdaddr = dly_addr;
#1;
O = mem[rdaddr];
end
endmodule | module RAM16X1S (A0,A1,A2,A3,WCLK,WE,D,O); |
input A0,A1,A2,A3,WCLK,WE,D;
output O;
reg mem[0:15];
wire #1 dly_WE = WE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
always @(posedge WCLK)
begin
if (dly_WE) mem[dly_addr] = dly_D;
end
reg [3:0] rdaddr;
reg O;
always @*
begin
rdaddr = dly_addr;
#1;
O = mem[rdaddr];
end
endmodule | 6 |
3,729 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);
input A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3;
output O0,O1,O2,O3;
RAM16X1S bit0 (A0,A1,A2,A3,WCLK,WE,D0,O0);
RAM16X1S bit1 (A0,A1,A2,A3,WCLK,WE,D1,O1);
RAM16X1S bit2 (A0,A1,A2,A3,WCLK,WE,D2,O2);
RAM16X1S bit3 (A0,A1,A2,A3,WCLK,WE,D3,O3);
endmodule | module RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3); |
input A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3;
output O0,O1,O2,O3;
RAM16X1S bit0 (A0,A1,A2,A3,WCLK,WE,D0,O0);
RAM16X1S bit1 (A0,A1,A2,A3,WCLK,WE,D1,O1);
RAM16X1S bit2 (A0,A1,A2,A3,WCLK,WE,D2,O2);
RAM16X1S bit3 (A0,A1,A2,A3,WCLK,WE,D3,O3);
endmodule | 6 |
3,730 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);
input A0,A1,A2,A3,CLK,CE,D;
output Q15,Q;
reg [15:0] mem;
wire #1 dly_CE = CE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
assign Q15 = mem[15];
always @(posedge CLK)
begin
if (dly_CE) mem = {mem,dly_D};
end
reg [3:0] rdaddr;
reg Q;
always @*
begin
rdaddr = dly_addr;
#1;
Q = mem[rdaddr];
end
endmodule | module SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q); |
input A0,A1,A2,A3,CLK,CE,D;
output Q15,Q;
reg [15:0] mem;
wire #1 dly_CE = CE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
assign Q15 = mem[15];
always @(posedge CLK)
begin
if (dly_CE) mem = {mem,dly_D};
end
reg [3:0] rdaddr;
reg Q;
always @*
begin
rdaddr = dly_addr;
#1;
Q = mem[rdaddr];
end
endmodule | 6 |
3,731 | data/full_repos/permissive/106408053/verilog/stubs.v | 106,408,053 | stubs.v | v | 166 | 63 | [] | [] | [] | [(6, 10), (13, 17), (20, 38), (41, 48), (51, 88), (91, 115), (118, 125), (128, 154), (157, 162)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n ^~~~\n : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n ^~~~~~~\n : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n ^~~\n : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n ^~~~~\n : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n ^~~~~~~~~\n : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n ^~~~~~~~\n : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n ^~~~~~~\n : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance SRLC16E\n if (dly_CE) mem = {mem,dly_D};\n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,514 | module | module MUXCY (S,CI,DI,O);
input S,CI,DI;
output O;
reg O;
always @* begin #0.1; O = (S) ? CI : DI; end
endmodule | module MUXCY (S,CI,DI,O); |
input S,CI,DI;
output O;
reg O;
always @* begin #0.1; O = (S) ? CI : DI; end
endmodule | 6 |
3,732 | data/full_repos/permissive/106408053/verilog/sync.v | 106,408,053 | sync.v | v | 166 | 121 | [] | ['general public license', 'free software foundation'] | [] | [(37, 164)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sync.v:71: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #1; next_testcount = testcount+1\'b1; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sync.v:144: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/sync.v:91: Signal definition not found, creating implicitly: \'sampled_intTestMode\'\nwire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/sync.v:115: Signal definition not found, creating implicitly: \'sampled_numberScheme\'\nwire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:52: Cannot find file containing module: \'dly_signal\'\ndly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal.sv\n dly_signal\n dly_signal.v\n dly_signal.sv\n obj_dir/dly_signal\n obj_dir/dly_signal.v\n obj_dir/dly_signal.sv\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:53: Cannot find file containing module: \'dly_signal\'\ndly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:60: Cannot find file containing module: \'ddr_inbuf\'\nddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);\n^~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:87: Cannot find file containing module: \'dly_signal\'\ndly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:102: Cannot find file containing module: \'demux\'\ndemux demuxL (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:109: Cannot find file containing module: \'demux\'\ndemux demuxH (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:122: Cannot find file containing module: \'filter\'\nfilter filter (\n^~~~~~\n%Error: Exiting due to 7 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,515 | module | module sync (clock, indata, intTestMode, numberScheme, filter_mode, demux_mode, falling_edge, outdata);
input clock;
input [31:0] indata;
input intTestMode;
input numberScheme;
input filter_mode;
input demux_mode;
input falling_edge;
output [31:0] outdata;
dly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);
dly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);
wire [31:0] sync_indata, sync_indata180;
ddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);
reg [7:0] testcount, next_testcount;
initial testcount=0;
always @ (posedge clock) testcount = next_testcount;
always @* begin #1; next_testcount = testcount+1'b1; end
wire [7:0] testcount1 = {
testcount[0],testcount[1],testcount[2],testcount[3],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount2 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount3 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[7],testcount[6],testcount[5],testcount[4]};
wire [31:0] itm_count;
(* equivalent_register_removal = "no" *)
dly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);
wire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;
wire [31:0] itm_indata180 = (sampled_intTestMode) ? ~itm_count : sync_indata180;
wire [31:0] demuxL_indata;
demux demuxL (
.clock(clock),
.indata(itm_indata[15:0]),
.indata180(itm_indata180[15:0]),
.outdata(demuxL_indata));
wire [31:0] demuxH_indata;
demux demuxH (
.clock(clock),
.indata(itm_indata[31:16]),
.indata180(itm_indata180[31:16]),
.outdata(demuxH_indata));
wire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;
wire [31:0] filtered_indata;
filter filter (
.clock(clock),
.indata(itm_indata),
.indata180(itm_indata180),
.outdata(filtered_indata));
reg [1:0] select, next_select;
reg [31:0] selectdata, next_selectdata;
reg [31:0] outdata;
always @(posedge clock)
begin
select = next_select;
selectdata = next_selectdata;
end
always @*
begin
#1;
if (demux_mode)
next_select = 2'b10;
else if (filter_mode)
next_select = 2'b11;
else next_select = {1'b0,falling_edge};
case (select)
2'b00 : next_selectdata = itm_indata;
2'b01 : next_selectdata = itm_indata180;
2'b10 : next_selectdata = demux_indata;
2'b11 : next_selectdata = filtered_indata;
endcase
outdata = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
end
endmodule | module sync (clock, indata, intTestMode, numberScheme, filter_mode, demux_mode, falling_edge, outdata); |
input clock;
input [31:0] indata;
input intTestMode;
input numberScheme;
input filter_mode;
input demux_mode;
input falling_edge;
output [31:0] outdata;
dly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);
dly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);
wire [31:0] sync_indata, sync_indata180;
ddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);
reg [7:0] testcount, next_testcount;
initial testcount=0;
always @ (posedge clock) testcount = next_testcount;
always @* begin #1; next_testcount = testcount+1'b1; end
wire [7:0] testcount1 = {
testcount[0],testcount[1],testcount[2],testcount[3],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount2 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[4],testcount[5],testcount[6],testcount[7]};
wire [7:0] testcount3 = {
testcount[3],testcount[2],testcount[1],testcount[0],
testcount[7],testcount[6],testcount[5],testcount[4]};
wire [31:0] itm_count;
(* equivalent_register_removal = "no" *)
dly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);
wire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;
wire [31:0] itm_indata180 = (sampled_intTestMode) ? ~itm_count : sync_indata180;
wire [31:0] demuxL_indata;
demux demuxL (
.clock(clock),
.indata(itm_indata[15:0]),
.indata180(itm_indata180[15:0]),
.outdata(demuxL_indata));
wire [31:0] demuxH_indata;
demux demuxH (
.clock(clock),
.indata(itm_indata[31:16]),
.indata180(itm_indata180[31:16]),
.outdata(demuxH_indata));
wire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;
wire [31:0] filtered_indata;
filter filter (
.clock(clock),
.indata(itm_indata),
.indata180(itm_indata180),
.outdata(filtered_indata));
reg [1:0] select, next_select;
reg [31:0] selectdata, next_selectdata;
reg [31:0] outdata;
always @(posedge clock)
begin
select = next_select;
selectdata = next_selectdata;
end
always @*
begin
#1;
if (demux_mode)
next_select = 2'b10;
else if (filter_mode)
next_select = 2'b11;
else next_select = {1'b0,falling_edge};
case (select)
2'b00 : next_selectdata = itm_indata;
2'b01 : next_selectdata = itm_indata180;
2'b10 : next_selectdata = demux_indata;
2'b11 : next_selectdata = filtered_indata;
endcase
outdata = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
end
endmodule | 6 |
3,737 | data/full_repos/permissive/106408053/verilog/trigger.v | 106,408,053 | trigger.v | v | 132 | 86 | [] | ['general public license', 'free software foundation'] | [] | [(40, 129)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger.v:124: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:75: Cannot find file containing module: \'stage\'\nstage stage0 (\n^~~~~\n ... Looked in:\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage.v\n data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage.sv\n stage\n stage.v\n stage.sv\n obj_dir/stage\n obj_dir/stage.v\n obj_dir/stage.sv\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:82: Cannot find file containing module: \'stage\'\nstage stage1 (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:89: Cannot find file containing module: \'stage\'\nstage stage2 (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:96: Cannot find file containing module: \'stage\'\nstage stage3 (\n^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,522 | module | module trigger(
clock, reset,
dataIn, validIn,
wrMask, wrValue,
wrConfig, wrEdge,
config_data,
arm, demux_mode,
capture, run);
input clock, reset;
input validIn;
input [31:0] dataIn;
input [3:0] wrMask;
input [3:0] wrValue;
input [3:0] wrConfig;
input [3:0] wrEdge;
input [31:0] config_data;
input arm;
input demux_mode;
output capture;
output run;
reg capture, next_capture;
reg [1:0] levelReg, next_levelReg;
wire [3:0] stageRun;
wire run = |stageRun;
wire [3:0] stageMatch;
stage stage0 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[0]), .wrValue(wrValue[0]), .wrEdge(wrEdge[0]),
.wrConfig(wrConfig[0]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[0]), .match(stageMatch[0]));
stage stage1 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[1]), .wrValue(wrValue[1]), .wrEdge(wrEdge[1]),
.wrConfig(wrConfig[1]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[1]), .match(stageMatch[1]));
stage stage2 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[2]), .wrValue(wrValue[2]), .wrEdge(wrEdge[2]),
.wrConfig(wrConfig[2]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[2]), .match(stageMatch[2]));
stage stage3 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[3]), .wrValue(wrValue[3]), .wrEdge(wrEdge[3]),
.wrConfig(wrConfig[3]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[3]), .match(stageMatch[3]));
initial levelReg = 2'b00;
always @(posedge clock or posedge reset)
begin : P2
if (reset)
begin
capture = 1'b0;
levelReg = 2'b00;
end
else
begin
capture = next_capture;
levelReg = next_levelReg;
end
end
always @*
begin
#1;
next_capture = arm | capture;
next_levelReg = levelReg;
if (|stageMatch) next_levelReg = levelReg + 1;
end
endmodule | module trigger(
clock, reset,
dataIn, validIn,
wrMask, wrValue,
wrConfig, wrEdge,
config_data,
arm, demux_mode,
capture, run); |
input clock, reset;
input validIn;
input [31:0] dataIn;
input [3:0] wrMask;
input [3:0] wrValue;
input [3:0] wrConfig;
input [3:0] wrEdge;
input [31:0] config_data;
input arm;
input demux_mode;
output capture;
output run;
reg capture, next_capture;
reg [1:0] levelReg, next_levelReg;
wire [3:0] stageRun;
wire run = |stageRun;
wire [3:0] stageMatch;
stage stage0 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[0]), .wrValue(wrValue[0]), .wrEdge(wrEdge[0]),
.wrConfig(wrConfig[0]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[0]), .match(stageMatch[0]));
stage stage1 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[1]), .wrValue(wrValue[1]), .wrEdge(wrEdge[1]),
.wrConfig(wrConfig[1]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[1]), .match(stageMatch[1]));
stage stage2 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[2]), .wrValue(wrValue[2]), .wrEdge(wrEdge[2]),
.wrConfig(wrConfig[2]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[2]), .match(stageMatch[2]));
stage stage3 (
.clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn),
.wrMask(wrMask[3]), .wrValue(wrValue[3]), .wrEdge(wrEdge[3]),
.wrConfig(wrConfig[3]), .config_data(config_data),
.arm(arm), .level(levelReg), .demux_mode(demux_mode),
.run(stageRun[3]), .match(stageMatch[3]));
initial levelReg = 2'b00;
always @(posedge clock or posedge reset)
begin : P2
if (reset)
begin
capture = 1'b0;
levelReg = 2'b00;
end
else
begin
capture = next_capture;
levelReg = next_levelReg;
end
end
always @*
begin
#1;
next_capture = arm | capture;
next_levelReg = levelReg;
if (|stageMatch) next_levelReg = levelReg + 1;
end
endmodule | 6 |
3,738 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigger_adv (
clock, reset,
dataIn, validIn, arm, finish_now,
wrSelect, wrChain, config_data,
run, capture);
input clock, reset;
input validIn;
input [31:0] dataIn;
input arm, finish_now;
input wrSelect,wrChain;
input [31:0] config_data;
output run;
output capture;
reg [4:0] wrcount, next_wrcount;
reg [6:0] wraddr, next_wraddr;
reg [31:0] wrdata, next_wrdata;
reg wrenb, next_wrenb;
reg active, next_active;
reg finished, next_finished;
reg force_capture, next_force_capture;
reg [3:0] state, next_state;
reg [19:0] hit_count, next_hit_count;
reg run, next_run;
reg capture, next_capture;
wire last_state = &state;
pipeline_stall #(.DELAY(2)) dly_validIn_reg (clock, reset, validIn, dly_validIn);
initial
begin
wrcount=0;
wraddr=0;
wrdata=0;
wrenb=1'b0;
end
always @ (posedge clock)
begin
wrcount = next_wrcount;
wraddr = next_wraddr;
wrdata = next_wrdata;
wrenb = next_wrenb;
end
always @*
begin
next_wrcount = (wrenb) ? wrcount+1'b1 : 0;
next_wraddr = wraddr;
next_wrdata = wrdata;
next_wrenb = wrenb && (~&wrcount);
if (wrSelect) next_wraddr = config_data[6:0];
if (wrChain)
begin
next_wrcount = 0;
next_wrdata = config_data;
next_wrenb = 1'b1;
end
else if (wrenb)
next_wrdata = {wrdata,1'b0};
if (reset)
begin
next_wrcount = 0;
next_wraddr = 0;
next_wrenb = 1'b0;
end
end
wire wrenb_fsm = wrChain && ~|wraddr[6:5];
wire [3:0] fsm_ramaddr = (wrChain) ? wraddr[3:0] : state;
wire [31:0] fsm_state;
ram_dword fsm_ram (clock, fsm_ramaddr, wrenb_fsm, config_data, fsm_state);
wire fsm_laststate;
wire fsm_trigger;
wire fsm_start_timer1;
wire fsm_clear_timer1;
wire fsm_stop_timer1;
wire fsm_start_timer2;
wire fsm_clear_timer2;
wire fsm_stop_timer2;
wire [3:0] fsm_else_state;
wire [19:0] fsm_count;
assign {
fsm_laststate, fsm_trigger,
fsm_start_timer2, fsm_start_timer1,
fsm_clear_timer2, fsm_clear_timer1,
fsm_stop_timer2, fsm_stop_timer1,
fsm_else_state[3:0], fsm_count[19:0]} = fsm_state;
reg [1:0] wrenb_timer;
reg update_timers;
always @*
begin
wrenb_timer=0;
if ({wraddr[6:3],3'b0}==7'h38)
case (wraddr[1])
1'b0 : wrenb_timer[0] = wrChain;
1'b1 : wrenb_timer[1] = wrChain;
endcase
end
timer timer1 (clock, reset, wrenb_timer[0], wraddr[0], config_data,
update_timers, fsm_start_timer1, fsm_clear_timer1, fsm_stop_timer1,
timer1_elapsed);
timer timer2 (clock, reset, wrenb_timer[1], wraddr[0], config_data,
update_timers, fsm_start_timer2, fsm_clear_timer2, fsm_stop_timer2,
timer2_elapsed);
wire hit_term, else_term, capture_term;
trigterms trigterms (
clock, dataIn, timer1_elapsed, timer2_elapsed,
wrenb, wraddr, wrdata[31],
state, {capture_term, else_term, hit_term});
initial
begin
active = 1'b0;
finished = 1'b0;
force_capture = 1'b0;
state = 4'h0;
hit_count = 20'h0;
run = 1'b0;
capture = 1'b0;
end
always @ (posedge clock)
begin
active = next_active;
finished = next_finished;
force_capture = next_force_capture;
state = next_state;
hit_count = next_hit_count;
run = next_run;
capture = next_capture;
end
always @*
begin
next_active = active | arm;
next_finished = finished;
next_force_capture = force_capture;
next_state = state;
next_hit_count = hit_count;
next_run = 1'b0;
next_capture = 1'b0;
update_timers = 1'b0;
if (active && dly_validIn)
begin
next_capture = capture_term || force_capture;
if (!finished)
if (hit_term)
begin
next_hit_count = hit_count+1'b1;
if (hit_count==fsm_count)
begin
update_timers = 1'b1;
next_hit_count = 0;
if (fsm_trigger || fsm_laststate || last_state)
next_run = 1'b1;
if (fsm_laststate || last_state)
next_finished = 1'b1;
else next_state = state + 1;
end
end
else if (else_term)
begin
next_hit_count = 0;
next_state = fsm_else_state;
end
end
if (active && finish_now)
begin
next_finished = 1'b1;
next_force_capture = 1'b1;
next_run = 1;
end
if (reset)
begin
next_active = 1'b0;
next_finished = 1'b0;
next_force_capture = 1'b0;
next_state = 0;
next_hit_count = 0;
next_run = 0;
end
end
endmodule | module trigger_adv (
clock, reset,
dataIn, validIn, arm, finish_now,
wrSelect, wrChain, config_data,
run, capture); |
input clock, reset;
input validIn;
input [31:0] dataIn;
input arm, finish_now;
input wrSelect,wrChain;
input [31:0] config_data;
output run;
output capture;
reg [4:0] wrcount, next_wrcount;
reg [6:0] wraddr, next_wraddr;
reg [31:0] wrdata, next_wrdata;
reg wrenb, next_wrenb;
reg active, next_active;
reg finished, next_finished;
reg force_capture, next_force_capture;
reg [3:0] state, next_state;
reg [19:0] hit_count, next_hit_count;
reg run, next_run;
reg capture, next_capture;
wire last_state = &state;
pipeline_stall #(.DELAY(2)) dly_validIn_reg (clock, reset, validIn, dly_validIn);
initial
begin
wrcount=0;
wraddr=0;
wrdata=0;
wrenb=1'b0;
end
always @ (posedge clock)
begin
wrcount = next_wrcount;
wraddr = next_wraddr;
wrdata = next_wrdata;
wrenb = next_wrenb;
end
always @*
begin
next_wrcount = (wrenb) ? wrcount+1'b1 : 0;
next_wraddr = wraddr;
next_wrdata = wrdata;
next_wrenb = wrenb && (~&wrcount);
if (wrSelect) next_wraddr = config_data[6:0];
if (wrChain)
begin
next_wrcount = 0;
next_wrdata = config_data;
next_wrenb = 1'b1;
end
else if (wrenb)
next_wrdata = {wrdata,1'b0};
if (reset)
begin
next_wrcount = 0;
next_wraddr = 0;
next_wrenb = 1'b0;
end
end
wire wrenb_fsm = wrChain && ~|wraddr[6:5];
wire [3:0] fsm_ramaddr = (wrChain) ? wraddr[3:0] : state;
wire [31:0] fsm_state;
ram_dword fsm_ram (clock, fsm_ramaddr, wrenb_fsm, config_data, fsm_state);
wire fsm_laststate;
wire fsm_trigger;
wire fsm_start_timer1;
wire fsm_clear_timer1;
wire fsm_stop_timer1;
wire fsm_start_timer2;
wire fsm_clear_timer2;
wire fsm_stop_timer2;
wire [3:0] fsm_else_state;
wire [19:0] fsm_count;
assign {
fsm_laststate, fsm_trigger,
fsm_start_timer2, fsm_start_timer1,
fsm_clear_timer2, fsm_clear_timer1,
fsm_stop_timer2, fsm_stop_timer1,
fsm_else_state[3:0], fsm_count[19:0]} = fsm_state;
reg [1:0] wrenb_timer;
reg update_timers;
always @*
begin
wrenb_timer=0;
if ({wraddr[6:3],3'b0}==7'h38)
case (wraddr[1])
1'b0 : wrenb_timer[0] = wrChain;
1'b1 : wrenb_timer[1] = wrChain;
endcase
end
timer timer1 (clock, reset, wrenb_timer[0], wraddr[0], config_data,
update_timers, fsm_start_timer1, fsm_clear_timer1, fsm_stop_timer1,
timer1_elapsed);
timer timer2 (clock, reset, wrenb_timer[1], wraddr[0], config_data,
update_timers, fsm_start_timer2, fsm_clear_timer2, fsm_stop_timer2,
timer2_elapsed);
wire hit_term, else_term, capture_term;
trigterms trigterms (
clock, dataIn, timer1_elapsed, timer2_elapsed,
wrenb, wraddr, wrdata[31],
state, {capture_term, else_term, hit_term});
initial
begin
active = 1'b0;
finished = 1'b0;
force_capture = 1'b0;
state = 4'h0;
hit_count = 20'h0;
run = 1'b0;
capture = 1'b0;
end
always @ (posedge clock)
begin
active = next_active;
finished = next_finished;
force_capture = next_force_capture;
state = next_state;
hit_count = next_hit_count;
run = next_run;
capture = next_capture;
end
always @*
begin
next_active = active | arm;
next_finished = finished;
next_force_capture = force_capture;
next_state = state;
next_hit_count = hit_count;
next_run = 1'b0;
next_capture = 1'b0;
update_timers = 1'b0;
if (active && dly_validIn)
begin
next_capture = capture_term || force_capture;
if (!finished)
if (hit_term)
begin
next_hit_count = hit_count+1'b1;
if (hit_count==fsm_count)
begin
update_timers = 1'b1;
next_hit_count = 0;
if (fsm_trigger || fsm_laststate || last_state)
next_run = 1'b1;
if (fsm_laststate || last_state)
next_finished = 1'b1;
else next_state = state + 1;
end
end
else if (else_term)
begin
next_hit_count = 0;
next_state = fsm_else_state;
end
end
if (active && finish_now)
begin
next_finished = 1'b1;
next_force_capture = 1'b1;
next_run = 1;
end
if (reset)
begin
next_active = 1'b0;
next_finished = 1'b0;
next_force_capture = 1'b0;
next_state = 0;
next_hit_count = 0;
next_run = 0;
end
end
endmodule | 6 |
3,739 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterms (clock, dataIn, timer1_hit, timer2_hit, wrenb, wraddr, din, state, hit);
input clock;
input [31:0] dataIn;
input timer1_hit, timer2_hit;
input wrenb;
input [6:0] wraddr;
input din;
input [3:0] state;
output [2:0] hit;
reg [15:0] wrenb_term;
reg [7:0] wrenb_range_edge;
reg [15:0] wrenb_state;
always @*
begin
#1;
wrenb_term = 0;
wrenb_range_edge = 0;
wrenb_state = 0;
casex (wraddr[6:3])
4'b010x : wrenb_term[wraddr[3:0]] = wrenb;
4'b0110 : wrenb_range_edge[wraddr[2:0]] = wrenb;
4'b1xxx : wrenb_state[wraddr[5:2]] = wrenb;
endcase
end
wire [7:0] terma_hit, termb_hit, termc_hit, termd_hit;
wire [7:0] terme_hit, termf_hit, termg_hit, termh_hit;
wire [7:0] termi_hit, termj_hit;
trigterm_32bit terma (dataIn, clock, wrenb_term[0] || wrenb_term[15], din, terma_dout, terma_hit);
trigterm_32bit termb (dataIn, clock, wrenb_term[1] || wrenb_term[15], din, termb_dout, termb_hit);
trigterm_32bit termc (dataIn, clock, wrenb_term[2] || wrenb_term[15], din, termc_dout, termc_hit);
trigterm_32bit termd (dataIn, clock, wrenb_term[3] || wrenb_term[15], din, termd_dout, termd_hit);
trigterm_32bit terme (dataIn, clock, wrenb_term[4] || wrenb_term[15], din, terme_dout, terme_hit);
trigterm_32bit termf (dataIn, clock, wrenb_term[5] || wrenb_term[15], din, termf_dout, termf_hit);
trigterm_32bit termg (dataIn, clock, wrenb_term[6] || wrenb_term[15], din, termg_dout, termg_hit);
trigterm_32bit termh (dataIn, clock, wrenb_term[7] || wrenb_term[15], din, termh_dout, termh_hit);
trigterm_32bit termi (dataIn, clock, wrenb_term[8] || wrenb_term[15], din, termi_dout, termi_hit);
trigterm_32bit termj (dataIn, clock, wrenb_term[9] || wrenb_term[15], din, termj_dout, termj_hit);
trigterm_range range1l (dataIn, clock, wrenb_range_edge[0], din, range1_lower);
trigterm_range range1u (dataIn, clock, wrenb_range_edge[1], din, range1_upper);
trigterm_range range2l (dataIn, clock, wrenb_range_edge[2], din, range2_lower);
trigterm_range range2u (dataIn, clock, wrenb_range_edge[3], din, range2_upper);
wire [31:0] dly_dataIn;
dly_signal #(32) dly_dataIn_reg (clock, dataIn, dly_dataIn);
trigterm_edge edge1 (dataIn, dly_dataIn, clock, wrenb_range_edge[4], din, edge1_hit);
trigterm_edge edge2 (dataIn, dly_dataIn, clock, wrenb_range_edge[5], din, edge2_hit);
wire range1_upper_hit = !range1_upper;
wire range2_upper_hit = !range2_upper;
wire [31:0] term_hits;
assign term_hits[31:30] = 0;
assign term_hits[29] = &termj_hit[7:4];
assign term_hits[28] = &termj_hit[3:0];
assign term_hits[27] = edge2_hit;
assign term_hits[26] = edge2_hit;
assign term_hits[25] = &termi_hit[7:4];
assign term_hits[24] = &termi_hit[3:0];
assign term_hits[23] = range2_upper_hit;
assign term_hits[22] = range2_lower;
assign term_hits[21] = &termh_hit[7:4];
assign term_hits[20] = &termh_hit[3:0];
assign term_hits[19] = &termg_hit[7:4];
assign term_hits[18] = &termg_hit[3:0];
assign term_hits[17] = &termf_hit[7:4];
assign term_hits[16] = &termf_hit[3:0];
assign term_hits[15:14] = 0;
assign term_hits[13] = &terme_hit[7:4];
assign term_hits[12] = &terme_hit[3:0];
assign term_hits[11] = edge1_hit;
assign term_hits[10] = edge1_hit;
assign term_hits[9] = &termd_hit[7:4];
assign term_hits[8] = &termd_hit[3:0];
assign term_hits[7] = range1_upper_hit;
assign term_hits[6] = range1_lower;
assign term_hits[5] = &termc_hit[7:4];
assign term_hits[4] = &termc_hit[3:0];
assign term_hits[3] = &termb_hit[7:4];
assign term_hits[2] = &termb_hit[3:0];
assign term_hits[1] = &terma_hit[7:4];
assign term_hits[0] = &terma_hit[3:0];
wire [31:0] sampled_term_hits;
dly_signal #(32) sampled_term_hits_reg (clock, term_hits, sampled_term_hits);
wire [31:0] use_term_hits = {
timer2_hit, timer2_hit, sampled_term_hits[29:16],
timer1_hit, timer1_hit, sampled_term_hits[13:0]};
wire [2:0] state_hit[0:15];
trigstate state0 (use_term_hits, clock, wrenb_state[0], wraddr[1:0], din, state_hit[0]);
trigstate state1 (use_term_hits, clock, wrenb_state[1], wraddr[1:0], din, state_hit[1]);
trigstate state2 (use_term_hits, clock, wrenb_state[2], wraddr[1:0], din, state_hit[2]);
trigstate state3 (use_term_hits, clock, wrenb_state[3], wraddr[1:0], din, state_hit[3]);
trigstate state4 (use_term_hits, clock, wrenb_state[4], wraddr[1:0], din, state_hit[4]);
trigstate state5 (use_term_hits, clock, wrenb_state[5], wraddr[1:0], din, state_hit[5]);
trigstate state6 (use_term_hits, clock, wrenb_state[6], wraddr[1:0], din, state_hit[6]);
trigstate state7 (use_term_hits, clock, wrenb_state[7], wraddr[1:0], din, state_hit[7]);
trigstate state8 (use_term_hits, clock, wrenb_state[8], wraddr[1:0], din, state_hit[8]);
trigstate state9 (use_term_hits, clock, wrenb_state[9], wraddr[1:0], din, state_hit[9]);
trigstate stateA (use_term_hits, clock, wrenb_state[10], wraddr[1:0], din, state_hit[10]);
trigstate stateB (use_term_hits, clock, wrenb_state[11], wraddr[1:0], din, state_hit[11]);
trigstate stateC (use_term_hits, clock, wrenb_state[12], wraddr[1:0], din, state_hit[12]);
trigstate stateD (use_term_hits, clock, wrenb_state[13], wraddr[1:0], din, state_hit[13]);
trigstate stateE (use_term_hits, clock, wrenb_state[14], wraddr[1:0], din, state_hit[14]);
trigstate stateF (use_term_hits, clock, wrenb_state[15], wraddr[1:0], din, state_hit[15]);
wire [2:0] hit = state_hit[state];
endmodule | module trigterms (clock, dataIn, timer1_hit, timer2_hit, wrenb, wraddr, din, state, hit); |
input clock;
input [31:0] dataIn;
input timer1_hit, timer2_hit;
input wrenb;
input [6:0] wraddr;
input din;
input [3:0] state;
output [2:0] hit;
reg [15:0] wrenb_term;
reg [7:0] wrenb_range_edge;
reg [15:0] wrenb_state;
always @*
begin
#1;
wrenb_term = 0;
wrenb_range_edge = 0;
wrenb_state = 0;
casex (wraddr[6:3])
4'b010x : wrenb_term[wraddr[3:0]] = wrenb;
4'b0110 : wrenb_range_edge[wraddr[2:0]] = wrenb;
4'b1xxx : wrenb_state[wraddr[5:2]] = wrenb;
endcase
end
wire [7:0] terma_hit, termb_hit, termc_hit, termd_hit;
wire [7:0] terme_hit, termf_hit, termg_hit, termh_hit;
wire [7:0] termi_hit, termj_hit;
trigterm_32bit terma (dataIn, clock, wrenb_term[0] || wrenb_term[15], din, terma_dout, terma_hit);
trigterm_32bit termb (dataIn, clock, wrenb_term[1] || wrenb_term[15], din, termb_dout, termb_hit);
trigterm_32bit termc (dataIn, clock, wrenb_term[2] || wrenb_term[15], din, termc_dout, termc_hit);
trigterm_32bit termd (dataIn, clock, wrenb_term[3] || wrenb_term[15], din, termd_dout, termd_hit);
trigterm_32bit terme (dataIn, clock, wrenb_term[4] || wrenb_term[15], din, terme_dout, terme_hit);
trigterm_32bit termf (dataIn, clock, wrenb_term[5] || wrenb_term[15], din, termf_dout, termf_hit);
trigterm_32bit termg (dataIn, clock, wrenb_term[6] || wrenb_term[15], din, termg_dout, termg_hit);
trigterm_32bit termh (dataIn, clock, wrenb_term[7] || wrenb_term[15], din, termh_dout, termh_hit);
trigterm_32bit termi (dataIn, clock, wrenb_term[8] || wrenb_term[15], din, termi_dout, termi_hit);
trigterm_32bit termj (dataIn, clock, wrenb_term[9] || wrenb_term[15], din, termj_dout, termj_hit);
trigterm_range range1l (dataIn, clock, wrenb_range_edge[0], din, range1_lower);
trigterm_range range1u (dataIn, clock, wrenb_range_edge[1], din, range1_upper);
trigterm_range range2l (dataIn, clock, wrenb_range_edge[2], din, range2_lower);
trigterm_range range2u (dataIn, clock, wrenb_range_edge[3], din, range2_upper);
wire [31:0] dly_dataIn;
dly_signal #(32) dly_dataIn_reg (clock, dataIn, dly_dataIn);
trigterm_edge edge1 (dataIn, dly_dataIn, clock, wrenb_range_edge[4], din, edge1_hit);
trigterm_edge edge2 (dataIn, dly_dataIn, clock, wrenb_range_edge[5], din, edge2_hit);
wire range1_upper_hit = !range1_upper;
wire range2_upper_hit = !range2_upper;
wire [31:0] term_hits;
assign term_hits[31:30] = 0;
assign term_hits[29] = &termj_hit[7:4];
assign term_hits[28] = &termj_hit[3:0];
assign term_hits[27] = edge2_hit;
assign term_hits[26] = edge2_hit;
assign term_hits[25] = &termi_hit[7:4];
assign term_hits[24] = &termi_hit[3:0];
assign term_hits[23] = range2_upper_hit;
assign term_hits[22] = range2_lower;
assign term_hits[21] = &termh_hit[7:4];
assign term_hits[20] = &termh_hit[3:0];
assign term_hits[19] = &termg_hit[7:4];
assign term_hits[18] = &termg_hit[3:0];
assign term_hits[17] = &termf_hit[7:4];
assign term_hits[16] = &termf_hit[3:0];
assign term_hits[15:14] = 0;
assign term_hits[13] = &terme_hit[7:4];
assign term_hits[12] = &terme_hit[3:0];
assign term_hits[11] = edge1_hit;
assign term_hits[10] = edge1_hit;
assign term_hits[9] = &termd_hit[7:4];
assign term_hits[8] = &termd_hit[3:0];
assign term_hits[7] = range1_upper_hit;
assign term_hits[6] = range1_lower;
assign term_hits[5] = &termc_hit[7:4];
assign term_hits[4] = &termc_hit[3:0];
assign term_hits[3] = &termb_hit[7:4];
assign term_hits[2] = &termb_hit[3:0];
assign term_hits[1] = &terma_hit[7:4];
assign term_hits[0] = &terma_hit[3:0];
wire [31:0] sampled_term_hits;
dly_signal #(32) sampled_term_hits_reg (clock, term_hits, sampled_term_hits);
wire [31:0] use_term_hits = {
timer2_hit, timer2_hit, sampled_term_hits[29:16],
timer1_hit, timer1_hit, sampled_term_hits[13:0]};
wire [2:0] state_hit[0:15];
trigstate state0 (use_term_hits, clock, wrenb_state[0], wraddr[1:0], din, state_hit[0]);
trigstate state1 (use_term_hits, clock, wrenb_state[1], wraddr[1:0], din, state_hit[1]);
trigstate state2 (use_term_hits, clock, wrenb_state[2], wraddr[1:0], din, state_hit[2]);
trigstate state3 (use_term_hits, clock, wrenb_state[3], wraddr[1:0], din, state_hit[3]);
trigstate state4 (use_term_hits, clock, wrenb_state[4], wraddr[1:0], din, state_hit[4]);
trigstate state5 (use_term_hits, clock, wrenb_state[5], wraddr[1:0], din, state_hit[5]);
trigstate state6 (use_term_hits, clock, wrenb_state[6], wraddr[1:0], din, state_hit[6]);
trigstate state7 (use_term_hits, clock, wrenb_state[7], wraddr[1:0], din, state_hit[7]);
trigstate state8 (use_term_hits, clock, wrenb_state[8], wraddr[1:0], din, state_hit[8]);
trigstate state9 (use_term_hits, clock, wrenb_state[9], wraddr[1:0], din, state_hit[9]);
trigstate stateA (use_term_hits, clock, wrenb_state[10], wraddr[1:0], din, state_hit[10]);
trigstate stateB (use_term_hits, clock, wrenb_state[11], wraddr[1:0], din, state_hit[11]);
trigstate stateC (use_term_hits, clock, wrenb_state[12], wraddr[1:0], din, state_hit[12]);
trigstate stateD (use_term_hits, clock, wrenb_state[13], wraddr[1:0], din, state_hit[13]);
trigstate stateE (use_term_hits, clock, wrenb_state[14], wraddr[1:0], din, state_hit[14]);
trigstate stateF (use_term_hits, clock, wrenb_state[15], wraddr[1:0], din, state_hit[15]);
wire [2:0] hit = state_hit[state];
endmodule | 6 |
3,740 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigstate (term_hits, clock, wrenb, wraddr, din, hit);
input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;
reg [3:0] wrenb_sum;
always @*
begin
wrenb_sum = 0;
wrenb_sum[wraddr] = wrenb;
end
trigsum hit_sum (term_hits, clock, wrenb_sum[0], din, hit_term);
trigsum else_sum (term_hits, clock, wrenb_sum[1], din, else_term);
trigsum capture_sum (term_hits, clock, wrenb_sum[2], din, capture_term);
reg [2:0] hit, next_hit;
always @ (posedge clock) hit = next_hit;
always @* next_hit = {capture_term, else_term, hit_term};
endmodule | module trigstate (term_hits, clock, wrenb, wraddr, din, hit); |
input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;
reg [3:0] wrenb_sum;
always @*
begin
wrenb_sum = 0;
wrenb_sum[wraddr] = wrenb;
end
trigsum hit_sum (term_hits, clock, wrenb_sum[0], din, hit_term);
trigsum else_sum (term_hits, clock, wrenb_sum[1], din, else_term);
trigsum capture_sum (term_hits, clock, wrenb_sum[2], din, capture_term);
reg [2:0] hit, next_hit;
always @ (posedge clock) hit = next_hit;
always @* next_hit = {capture_term, else_term, hit_term};
endmodule | 6 |
3,741 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigsum (term_hits, clock, wrenb, din, hit);
input [31:0] term_hits;
input clock,wrenb,din;
output hit;
wire [7:0] pair_sum;
trigterm_32bit pair (term_hits, clock, wrenb, din, dout_pair, pair_sum);
trigterm_4bit mid0 (pair_sum[3:0], clock, wrenb, dout_pair, dout_mid0, mid0_sum);
trigterm_4bit mid1 (pair_sum[7:4], clock, wrenb, dout_mid0, dout_mid1, mid1_sum);
trigterm_4bit final ({2'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);
endmodule | module trigsum (term_hits, clock, wrenb, din, hit); |
input [31:0] term_hits;
input clock,wrenb,din;
output hit;
wire [7:0] pair_sum;
trigterm_32bit pair (term_hits, clock, wrenb, din, dout_pair, pair_sum);
trigterm_4bit mid0 (pair_sum[3:0], clock, wrenb, dout_pair, dout_mid0, mid0_sum);
trigterm_4bit mid1 (pair_sum[7:4], clock, wrenb, dout_mid0, dout_mid1, mid1_sum);
trigterm_4bit final ({2'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);
endmodule | 6 |
3,742 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_32bit (dataIn, clock, wrenb, din, dout, hit);
input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (dataIn[3:0], clock, wrenb, din, n0, hit[0]);
trigterm_4bit nyb1 (dataIn[7:4], clock, wrenb, n0, n1, hit[1]);
trigterm_4bit nyb2 (dataIn[11:8], clock, wrenb, n1, n2, hit[2]);
trigterm_4bit nyb3 (dataIn[15:12], clock, wrenb, n2, n3, hit[3]);
trigterm_4bit nyb4 (dataIn[19:16], clock, wrenb, n3, n4, hit[4]);
trigterm_4bit nyb5 (dataIn[23:20], clock, wrenb, n4, n5, hit[5]);
trigterm_4bit nyb6 (dataIn[27:24], clock, wrenb, n5, n6, hit[6]);
trigterm_4bit nyb7 (dataIn[31:28], clock, wrenb, n6, dout, hit[7]);
endmodule | module trigterm_32bit (dataIn, clock, wrenb, din, dout, hit); |
input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (dataIn[3:0], clock, wrenb, din, n0, hit[0]);
trigterm_4bit nyb1 (dataIn[7:4], clock, wrenb, n0, n1, hit[1]);
trigterm_4bit nyb2 (dataIn[11:8], clock, wrenb, n1, n2, hit[2]);
trigterm_4bit nyb3 (dataIn[15:12], clock, wrenb, n2, n3, hit[3]);
trigterm_4bit nyb4 (dataIn[19:16], clock, wrenb, n3, n4, hit[4]);
trigterm_4bit nyb5 (dataIn[23:20], clock, wrenb, n4, n5, hit[5]);
trigterm_4bit nyb6 (dataIn[27:24], clock, wrenb, n5, n6, hit[6]);
trigterm_4bit nyb7 (dataIn[31:28], clock, wrenb, n6, dout, hit[7]);
endmodule | 6 |
3,743 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_4bit (addr, clock, wrenb, din, dout, hit);
input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]),
.CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
endmodule | module trigterm_4bit (addr, clock, wrenb, din, dout, hit); |
input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]),
.CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
endmodule | 6 |
3,744 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_range (dataIn, clock, wrenb, din, hit);
input [31:0] dataIn;
input clock, wrenb, din;
output hit;
trigterm_range_byte byte0 (dataIn[7:0], clock, wrenb, din, dout0, 1'b1, cout0);
trigterm_range_byte byte1 (dataIn[15:8], clock, wrenb, dout0, dout1, cout0, cout1);
trigterm_range_byte byte2 (dataIn[23:16], clock, wrenb, dout1, dout2, cout1, cout2);
trigterm_range_byte byte3 (dataIn[31:24], clock, wrenb, dout2, dout, cout2, hit);
endmodule | module trigterm_range (dataIn, clock, wrenb, din, hit); |
input [31:0] dataIn;
input clock, wrenb, din;
output hit;
trigterm_range_byte byte0 (dataIn[7:0], clock, wrenb, din, dout0, 1'b1, cout0);
trigterm_range_byte byte1 (dataIn[15:8], clock, wrenb, dout0, dout1, cout0, cout1);
trigterm_range_byte byte2 (dataIn[23:16], clock, wrenb, dout1, dout2, cout1, cout2);
trigterm_range_byte byte3 (dataIn[31:24], clock, wrenb, dout2, dout, cout2, hit);
endmodule | 6 |
3,745 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_range_byte (dataIn, clock, wrenb, din, dout, cin, cout);
input [7:0] dataIn;
input clock, wrenb, din, cin;
output dout, cout;
wire [6:0] chain, carry;
trigterm_range_bit bit0 (dataIn[0], clock, wrenb, din, chain[0], cin, carry[0]);
trigterm_range_bit bit1 (dataIn[1], clock, wrenb, chain[0], chain[1], carry[0], carry[1]);
trigterm_range_bit bit2 (dataIn[2], clock, wrenb, chain[1], chain[2], carry[1], carry[2]);
trigterm_range_bit bit3 (dataIn[3], clock, wrenb, chain[2], chain[3], carry[2], carry[3]);
trigterm_range_bit bit4 (dataIn[4], clock, wrenb, chain[3], chain[4], carry[3], carry[4]);
trigterm_range_bit bit5 (dataIn[5], clock, wrenb, chain[4], chain[5], carry[4], carry[5]);
trigterm_range_bit bit6 (dataIn[6], clock, wrenb, chain[5], chain[6], carry[5], carry[6]);
trigterm_range_bit bit7 (dataIn[7], clock, wrenb, chain[6], dout, carry[6], cout);
endmodule | module trigterm_range_byte (dataIn, clock, wrenb, din, dout, cin, cout); |
input [7:0] dataIn;
input clock, wrenb, din, cin;
output dout, cout;
wire [6:0] chain, carry;
trigterm_range_bit bit0 (dataIn[0], clock, wrenb, din, chain[0], cin, carry[0]);
trigterm_range_bit bit1 (dataIn[1], clock, wrenb, chain[0], chain[1], carry[0], carry[1]);
trigterm_range_bit bit2 (dataIn[2], clock, wrenb, chain[1], chain[2], carry[1], carry[2]);
trigterm_range_bit bit3 (dataIn[3], clock, wrenb, chain[2], chain[3], carry[2], carry[3]);
trigterm_range_bit bit4 (dataIn[4], clock, wrenb, chain[3], chain[4], carry[3], carry[4]);
trigterm_range_bit bit5 (dataIn[5], clock, wrenb, chain[4], chain[5], carry[4], carry[5]);
trigterm_range_bit bit6 (dataIn[6], clock, wrenb, chain[5], chain[6], carry[5], carry[6]);
trigterm_range_bit bit7 (dataIn[7], clock, wrenb, chain[6], dout, carry[6], cout);
endmodule | 6 |
3,746 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_range_bit (dataIn, clock, wrenb, din, dout, cin, cout);
input dataIn;
input clock, wrenb, din, cin;
output dout, cout;
SRLC16E ram0 (
.A0(dataIn), .A1(1'b0), .A2(1'b0), .A3(1'b0),
.CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
MUXCY MUXCY_inst (.S(hit), .DI(dataIn), .CI(cin), .O(cout));
endmodule | module trigterm_range_bit (dataIn, clock, wrenb, din, dout, cin, cout); |
input dataIn;
input clock, wrenb, din, cin;
output dout, cout;
SRLC16E ram0 (
.A0(dataIn), .A1(1'b0), .A2(1'b0), .A3(1'b0),
.CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
MUXCY MUXCY_inst (.S(hit), .DI(dataIn), .CI(cin), .O(cout));
endmodule | 6 |
3,747 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module trigterm_edge (dataIn, dly_dataIn, clock, wrenb, din, hit);
input [31:0] dataIn, dly_dataIn;
input clock, wrenb, din;
output hit;
wire [63:0] use_dataIn = {
dly_dataIn[31:30], dataIn[31:30],
dly_dataIn[29:28], dataIn[29:28],
dly_dataIn[27:26], dataIn[27:26],
dly_dataIn[25:24], dataIn[25:24],
dly_dataIn[23:22], dataIn[23:22],
dly_dataIn[21:20], dataIn[21:20],
dly_dataIn[19:18], dataIn[19:18],
dly_dataIn[17:16], dataIn[17:16],
dly_dataIn[15:14], dataIn[15:14],
dly_dataIn[13:12], dataIn[13:12],
dly_dataIn[11:10], dataIn[11:10],
dly_dataIn[9:8], dataIn[9:8],
dly_dataIn[7:6], dataIn[7:6],
dly_dataIn[5:4], dataIn[5:4],
dly_dataIn[3:2], dataIn[3:2],
dly_dataIn[1:0], dataIn[1:0]};
wire [7:0] lohit, hihit;
trigterm_32bit loword (use_dataIn[31:0], clock, wrenb, din, doutlo, lohit);
trigterm_32bit hiword (use_dataIn[63:32], clock, wrenb, doutlo, dout, hihit);
assign hit = |{hihit,lohit};
endmodule | module trigterm_edge (dataIn, dly_dataIn, clock, wrenb, din, hit); |
input [31:0] dataIn, dly_dataIn;
input clock, wrenb, din;
output hit;
wire [63:0] use_dataIn = {
dly_dataIn[31:30], dataIn[31:30],
dly_dataIn[29:28], dataIn[29:28],
dly_dataIn[27:26], dataIn[27:26],
dly_dataIn[25:24], dataIn[25:24],
dly_dataIn[23:22], dataIn[23:22],
dly_dataIn[21:20], dataIn[21:20],
dly_dataIn[19:18], dataIn[19:18],
dly_dataIn[17:16], dataIn[17:16],
dly_dataIn[15:14], dataIn[15:14],
dly_dataIn[13:12], dataIn[13:12],
dly_dataIn[11:10], dataIn[11:10],
dly_dataIn[9:8], dataIn[9:8],
dly_dataIn[7:6], dataIn[7:6],
dly_dataIn[5:4], dataIn[5:4],
dly_dataIn[3:2], dataIn[3:2],
dly_dataIn[1:0], dataIn[1:0]};
wire [7:0] lohit, hihit;
trigterm_32bit loword (use_dataIn[31:0], clock, wrenb, din, doutlo, lohit);
trigterm_32bit hiword (use_dataIn[63:32], clock, wrenb, doutlo, dout, hihit);
assign hit = |{hihit,lohit};
endmodule | 6 |
3,748 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module ram_dword (clock, addr, wrenb, wrdata, rddata);
input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (clock, addr, wrenb, wrdata[7:0], rddata[7:0]);
ram_byte byte1 (clock, addr, wrenb, wrdata[15:8], rddata[15:8]);
ram_byte byte2 (clock, addr, wrenb, wrdata[23:16], rddata[23:16]);
ram_byte byte3 (clock, addr, wrenb, wrdata[31:24], rddata[31:24]);
endmodule | module ram_dword (clock, addr, wrenb, wrdata, rddata); |
input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (clock, addr, wrenb, wrdata[7:0], rddata[7:0]);
ram_byte byte1 (clock, addr, wrenb, wrdata[15:8], rddata[15:8]);
ram_byte byte2 (clock, addr, wrenb, wrdata[23:16], rddata[23:16]);
ram_byte byte3 (clock, addr, wrenb, wrdata[31:24], rddata[31:24]);
endmodule | 6 |
3,749 | data/full_repos/permissive/106408053/verilog/trigger_adv.v | 106,408,053 | trigger_adv.v | v | 703 | 135 | [] | ['general public license', 'free software foundation'] | [] | [(136, 372), (379, 493), (507, 531), (538, 547), (554, 567), (574, 581), (592, 600), (604, 617), (620, 629), (638, 666), (673, 683), (686, 700)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,523 | module | module ram_byte (clock, addr, wrenb, wrdata, rddata);
input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb),
.D0(wrdata[0]), .D1(wrdata[1]), .D2(wrdata[2]), .D3(wrdata[3]),
.O0(rddata[0]), .O1(rddata[1]), .O2(rddata[2]), .O3(rddata[3]));
RAM16X4S ram1 (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb),
.D0(wrdata[4]), .D1(wrdata[5]), .D2(wrdata[6]), .D3(wrdata[7]),
.O0(rddata[4]), .O1(rddata[5]), .O2(rddata[6]), .O3(rddata[7]));
endmodule | module ram_byte (clock, addr, wrenb, wrdata, rddata); |
input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb),
.D0(wrdata[0]), .D1(wrdata[1]), .D2(wrdata[2]), .D3(wrdata[3]),
.O0(rddata[0]), .O1(rddata[1]), .O2(rddata[2]), .O3(rddata[3]));
RAM16X4S ram1 (
.A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb),
.D0(wrdata[4]), .D1(wrdata[5]), .D2(wrdata[6]), .D3(wrdata[7]),
.O0(rddata[4]), .O1(rddata[5]), .O2(rddata[6]), .O3(rddata[7]));
endmodule | 6 |
3,750 | data/full_repos/permissive/106492436/LCD_Controller_MIPS.sv | 106,492,436 | LCD_Controller_MIPS.sv | sv | 58 | 62 | [] | [] | [] | null | line:20: before: "{" | data/verilator_xmls/72e8d362-1bb2-448f-8efb-f7095ca333bb.xml | null | 1,524 | module | module LCD_Controller_MIPS #(
parameter clk_wait = 16)
(
input reset,clk, iRS, LCD_start,
input [7:0] DATA,
output [7:0] LCD_DATA,
output logic LCD_EN, LCD_DONE,
output LCD_RW, LCD_RS, LCD_ON
);
assign LCD_ON = 1;
assign LCD_DATA = DATA;
assign LCD_RW = 1'b0;
assign LCD_RS = iRS;
enum {start, init, delay, done} state, next_state;
logic [4:0] counter;
always_ff @(posedge clk) begin
state = (reset)? start : next_state;
end
always_ff @(posedge clk) begin
unique case(state)
start:begin
LCD_DONE = 1'b0;
LCD_EN = 1'b0;
counter = 0;
next_state = init;
end
init: begin
LCD_EN = 1'b1;
next_state = delay;
end
delay:begin
if(counter<clk_wait)
counter = counter+1;
else
next_state = done;
end
done: begin
LCD_EN = 1'b0;
LCD_DONE = 1'b1;
counter = 0;
if (LCD_start) begin
next_state = start;
end
end
endcase
end
endmodule | module LCD_Controller_MIPS #(
parameter clk_wait = 16)
(
input reset,clk, iRS, LCD_start,
input [7:0] DATA,
output [7:0] LCD_DATA,
output logic LCD_EN, LCD_DONE,
output LCD_RW, LCD_RS, LCD_ON
); |
assign LCD_ON = 1;
assign LCD_DATA = DATA;
assign LCD_RW = 1'b0;
assign LCD_RS = iRS;
enum {start, init, delay, done} state, next_state;
logic [4:0] counter;
always_ff @(posedge clk) begin
state = (reset)? start : next_state;
end
always_ff @(posedge clk) begin
unique case(state)
start:begin
LCD_DONE = 1'b0;
LCD_EN = 1'b0;
counter = 0;
next_state = init;
end
init: begin
LCD_EN = 1'b1;
next_state = delay;
end
delay:begin
if(counter<clk_wait)
counter = counter+1;
else
next_state = done;
end
done: begin
LCD_EN = 1'b0;
LCD_DONE = 1'b1;
counter = 0;
if (LCD_start) begin
next_state = start;
end
end
endcase
end
endmodule | 0 |
3,751 | data/full_repos/permissive/106492436/memory.sv | 106,492,436 | memory.sv | sv | 71 | 42 | [] | [] | [] | [(1, 71)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:25: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h38\' generates 9 bits.\n : ... In instance memory\n rf[0] = 9\'h038;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc\' generates 9 bits.\n : ... In instance memory\n rf[1] = 9\'h00C;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n : ... In instance memory\n rf[2] = 9\'h001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h6\' generates 9 bits.\n : ... In instance memory\n rf[3] = 9\'h006;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:29: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n : ... In instance memory\n rf[4] = 9\'h080;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:30: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[5] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h148\' generates 9 bits.\n : ... In instance memory\n rf[6] = 9\'h148;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h145\' generates 9 bits.\n : ... In instance memory\n rf[7] = 9\'h145;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14c\' generates 9 bits.\n : ... In instance memory\n rf[8] = 9\'h14C;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:34: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14c\' generates 9 bits.\n : ... In instance memory\n rf[9] = 9\'h14C;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:35: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14f\' generates 9 bits.\n : ... In instance memory\n rf[10] = 9\'h14F;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:36: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[11] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[12] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:38: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[13] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:39: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[14] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[15] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[16] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[17] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[18] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:44: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[19] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[20] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:46: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n : ... In instance memory\n rf[21] = 9\'h0C0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[22] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:48: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[23] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:49: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[24] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:50: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[25] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[26] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[27] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:53: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[28] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:54: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[29] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:55: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[30] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:56: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[31] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:57: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[32] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:58: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[33] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:59: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[34] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:60: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[35] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:61: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[36] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:62: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[37] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:63: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[38] = 9\'h120;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n : ... In instance memory\n rf[39] = 9\'h120;\n ^\n%Error: Exiting due to 40 warning(s)\n' | 1,526 | module | module memory
#(
parameter NUM_REGS = 64,
parameter SIZE = 32
)(
input clk,
input rst,
input [5:0] wr_addr,
input wr_en,
input [31:0] wr_data,
input [5:0] rd_addr,
output [31:0] rd_data
);
logic [SIZE-1:0] rf [NUM_REGS-1:0];
integer i;
always_ff @ (posedge clk) begin
if (rst)
for (i = 0; i < NUM_REGS-1; i = i + 1)
rf[i] <= 0;
else if (wr_en)
rf[wr_addr] <= wr_data;
else begin
rf[0] = 9'h038;
rf[1] = 9'h00C;
rf[2] = 9'h001;
rf[3] = 9'h006;
rf[4] = 9'h080;
rf[5] = 9'h120;
rf[6] = 9'h148;
rf[7] = 9'h145;
rf[8] = 9'h14C;
rf[9] = 9'h14C;
rf[10] = 9'h14F;
rf[11] = 9'h120;
rf[12] = 9'h120;
rf[13] = 9'h120;
rf[14] = 9'h120;
rf[15] = 9'h120;
rf[16] = 9'h120;
rf[17] = 9'h120;
rf[18] = 9'h120;
rf[19] = 9'h120;
rf[20] = 9'h120;
rf[21] = 9'h0C0;
rf[22] = 9'h120;
rf[23] = 9'h120;
rf[24] = 9'h120;
rf[25] = 9'h120;
rf[26] = 9'h120;
rf[27] = 9'h120;
rf[28] = 9'h120;
rf[29] = 9'h120;
rf[30] = 9'h120;
rf[31] = 9'h120;
rf[32] = 9'h120;
rf[33] = 9'h120;
rf[34] = 9'h120;
rf[35] = 9'h120;
rf[36] = 9'h120;
rf[37] = 9'h120;
rf[38] = 9'h120;
rf[39] = 9'h120;
end
end
assign rd_data = rf[rd_addr];
endmodule | module memory
#(
parameter NUM_REGS = 64,
parameter SIZE = 32
)(
input clk,
input rst,
input [5:0] wr_addr,
input wr_en,
input [31:0] wr_data,
input [5:0] rd_addr,
output [31:0] rd_data
); |
logic [SIZE-1:0] rf [NUM_REGS-1:0];
integer i;
always_ff @ (posedge clk) begin
if (rst)
for (i = 0; i < NUM_REGS-1; i = i + 1)
rf[i] <= 0;
else if (wr_en)
rf[wr_addr] <= wr_data;
else begin
rf[0] = 9'h038;
rf[1] = 9'h00C;
rf[2] = 9'h001;
rf[3] = 9'h006;
rf[4] = 9'h080;
rf[5] = 9'h120;
rf[6] = 9'h148;
rf[7] = 9'h145;
rf[8] = 9'h14C;
rf[9] = 9'h14C;
rf[10] = 9'h14F;
rf[11] = 9'h120;
rf[12] = 9'h120;
rf[13] = 9'h120;
rf[14] = 9'h120;
rf[15] = 9'h120;
rf[16] = 9'h120;
rf[17] = 9'h120;
rf[18] = 9'h120;
rf[19] = 9'h120;
rf[20] = 9'h120;
rf[21] = 9'h0C0;
rf[22] = 9'h120;
rf[23] = 9'h120;
rf[24] = 9'h120;
rf[25] = 9'h120;
rf[26] = 9'h120;
rf[27] = 9'h120;
rf[28] = 9'h120;
rf[29] = 9'h120;
rf[30] = 9'h120;
rf[31] = 9'h120;
rf[32] = 9'h120;
rf[33] = 9'h120;
rf[34] = 9'h120;
rf[35] = 9'h120;
rf[36] = 9'h120;
rf[37] = 9'h120;
rf[38] = 9'h120;
rf[39] = 9'h120;
end
end
assign rd_data = rf[rd_addr];
endmodule | 0 |
3,752 | data/full_repos/permissive/106492436/test_1.sv | 106,492,436 | test_1.sv | sv | 45 | 44 | [] | [] | [] | [(1, 45)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:31: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:36: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:43: Unsupported: Ignoring delay on this delayed statement.\n initial forever #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/106492436/test_1.sv:15: Cannot find file containing module: \'MIPS\'\n MIPS uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS.v\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS.sv\n MIPS\n MIPS.v\n MIPS.sv\n obj_dir/MIPS\n obj_dir/MIPS.v\n obj_dir/MIPS.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,527 | module | module test_1;
logic clk;
logic rst;
logic [7:0] DATA;
logic RW;
logic EN;
logic RS;
logic ON;
MIPS uut (
.clk(clk),
.rst(rst),
.DATA(DATA),
.RW(RW),
.EN(EN),
.RS(RS),
.ON(ON)
);
initial begin
clk = 0;
rst = 1;
#100;
rst= 1;
#200;
rst= 0;
#200;
rst = 1;
end
initial forever #10 clk = ~clk;
endmodule | module test_1; |
logic clk;
logic rst;
logic [7:0] DATA;
logic RW;
logic EN;
logic RS;
logic ON;
MIPS uut (
.clk(clk),
.rst(rst),
.DATA(DATA),
.RW(RW),
.EN(EN),
.RS(RS),
.ON(ON)
);
initial begin
clk = 0;
rst = 1;
#100;
rst= 1;
#200;
rst= 0;
#200;
rst = 1;
end
initial forever #10 clk = ~clk;
endmodule | 0 |
3,753 | data/full_repos/permissive/106492436/Top_MIPS.sv | 106,492,436 | Top_MIPS.sv | sv | 34 | 23 | [] | [] | [] | [(1, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/106492436/Top_MIPS.sv:12: Cannot find file containing module: 'LCD_MIPS'\nLCD_MIPS lm(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/LCD_MIPS\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/LCD_MIPS.v\n data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/LCD_MIPS.sv\n LCD_MIPS\n LCD_MIPS.v\n LCD_MIPS.sv\n obj_dir/LCD_MIPS\n obj_dir/LCD_MIPS.v\n obj_dir/LCD_MIPS.sv\n%Error: data/full_repos/permissive/106492436/Top_MIPS.sv:24: Cannot find file containing module: 'memory'\nmemory mem(\n^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,528 | module | module Top_MIPS (
input clk,
input rst,
input start,
output [7:0] DATA,
output RW, EN, RS, ON
);
logic [8:0] data_mem;
logic [5:0] address;
LCD_MIPS lm(
.clk(clk),
.rst(rst),
.data_mem(data_mem),
.DATA(DATA),
.address(address),
.RW(RW),
.EN(EN),
.RS(RS),
.ON(ON)
);
memory mem(
.clk(clk),
.rst(~rst),
.wr_addr(),
.wr_en(),
.wr_data(),
.rd_addr(address),
.rd_data(data_mem)
);
endmodule | module Top_MIPS (
input clk,
input rst,
input start,
output [7:0] DATA,
output RW, EN, RS, ON
); |
logic [8:0] data_mem;
logic [5:0] address;
LCD_MIPS lm(
.clk(clk),
.rst(rst),
.data_mem(data_mem),
.DATA(DATA),
.address(address),
.RW(RW),
.EN(EN),
.RS(RS),
.ON(ON)
);
memory mem(
.clk(clk),
.rst(~rst),
.wr_addr(),
.wr_en(),
.wr_data(),
.rd_addr(address),
.rd_data(data_mem)
);
endmodule | 0 |
3,756 | data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v | 106,583,614 | Div_mod_top_level.v | v | 45 | 86 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v:30: Operator COND expects 32 or 17 bits on the Conditional False, but Conditional False\'s VARREF \'mod_res\' generates 16 bits.\n : ... In instance Div_mod_top_level\n assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : \'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v:32: Cannot find file containing module: \'interconect_cells\'\n interconect_cells connected_cells \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells.v\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells.sv\n interconect_cells\n interconect_cells.v\n interconect_cells.sv\n obj_dir/interconect_cells\n obj_dir/interconect_cells.v\n obj_dir/interconect_cells.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,534 | module | module Div_mod_top_level(
clk,
reset,
divisor,
dividend,
mode,
valid_input,
valid_output,
final_output
);
input signed [31:0] dividend;
input signed [15:0] divisor;
input clk, reset;
input valid_input, mode;
output valid_output;
output signed [16:0] final_output;
wire signed [16:0] div_res;
wire signed [15:0] mod_res;
assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : 'b0;
interconect_cells connected_cells
(
.clk(clk) ,
.reset(reset) ,
.in_divisor(divisor),
.in_dividend(dividend),
.valid_input(valid_input),
.valid_output(valid_output),
.mod_res(mod_res),
.div_res_tmp(div_res)
);
endmodule | module Div_mod_top_level(
clk,
reset,
divisor,
dividend,
mode,
valid_input,
valid_output,
final_output
); |
input signed [31:0] dividend;
input signed [15:0] divisor;
input clk, reset;
input valid_input, mode;
output valid_output;
output signed [16:0] final_output;
wire signed [16:0] div_res;
wire signed [15:0] mod_res;
assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : 'b0;
interconect_cells connected_cells
(
.clk(clk) ,
.reset(reset) ,
.in_divisor(divisor),
.in_dividend(dividend),
.valid_input(valid_input),
.valid_output(valid_output),
.mod_res(mod_res),
.div_res_tmp(div_res)
);
endmodule | 1 |
3,757 | data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v | 106,583,614 | interconect_cells.v | v | 777 | 175 | [] | [] | [] | null | line:777: before: "/" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:255: Signal definition not found, creating implicitly: \'wire_0_14_1_15_remainter\'\n reg_0_1[14] <= wire_0_14_1_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:256: Signal definition not found, creating implicitly: \'wire_0_13_1_14_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_0_1[13] <= wire_0_13_1_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:257: Signal definition not found, creating implicitly: \'wire_0_12_1_13_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_0_1[12] <= wire_0_12_1_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:258: Signal definition not found, creating implicitly: \'wire_0_11_1_12_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_0_1[11] <= wire_0_11_1_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:259: Signal definition not found, creating implicitly: \'wire_0_10_1_11_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_0_1[10] <= wire_0_10_1_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:260: Signal definition not found, creating implicitly: \'wire_0_9_1_10_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_0_1[9] <= wire_0_9_1_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:261: Signal definition not found, creating implicitly: \'wire_0_8_1_9_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_0_1[8] <= wire_0_8_1_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:262: Signal definition not found, creating implicitly: \'wire_0_7_1_8_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_0_1[7] <= wire_0_7_1_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:263: Signal definition not found, creating implicitly: \'wire_0_6_1_7_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_0_1[6] <= wire_0_6_1_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:264: Signal definition not found, creating implicitly: \'wire_0_5_1_6_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_0_1[5] <= wire_0_5_1_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:265: Signal definition not found, creating implicitly: \'wire_0_4_1_5_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_0_1[4] <= wire_0_4_1_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:266: Signal definition not found, creating implicitly: \'wire_0_3_1_4_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_0_1[3] <= wire_0_3_1_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:267: Signal definition not found, creating implicitly: \'wire_0_2_1_3_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_0_1[2] <= wire_0_2_1_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:268: Signal definition not found, creating implicitly: \'wire_0_1_1_2_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_0_1[1] <= wire_0_1_1_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:269: Signal definition not found, creating implicitly: \'wire_0_0_1_1_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_0_1[0] <= wire_0_0_1_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:322: Signal definition not found, creating implicitly: \'wire_2_14_3_15_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_2_3[14] <= wire_2_14_3_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:323: Signal definition not found, creating implicitly: \'wire_2_13_3_14_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_2_3[13] <= wire_2_13_3_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:324: Signal definition not found, creating implicitly: \'wire_2_12_3_13_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_2_3[12] <= wire_2_12_3_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:325: Signal definition not found, creating implicitly: \'wire_2_11_3_12_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_2_3[11] <= wire_2_11_3_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:326: Signal definition not found, creating implicitly: \'wire_2_10_3_11_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_2_3[10] <= wire_2_10_3_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:327: Signal definition not found, creating implicitly: \'wire_2_9_3_10_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_2_3[9] <= wire_2_9_3_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:328: Signal definition not found, creating implicitly: \'wire_2_8_3_9_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_2_3[8] <= wire_2_8_3_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:329: Signal definition not found, creating implicitly: \'wire_2_7_3_8_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_2_3[7] <= wire_2_7_3_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:330: Signal definition not found, creating implicitly: \'wire_2_6_3_7_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_2_3[6] <= wire_2_6_3_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:331: Signal definition not found, creating implicitly: \'wire_2_5_3_6_remainter\'\n : ... Suggested alternative: \'wire_0_5_1_6_remainter\'\n reg_2_3[5] <= wire_2_5_3_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:332: Signal definition not found, creating implicitly: \'wire_2_4_3_5_remainter\'\n : ... Suggested alternative: \'wire_0_4_1_5_remainter\'\n reg_2_3[4] <= wire_2_4_3_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:333: Signal definition not found, creating implicitly: \'wire_2_3_3_4_remainter\'\n : ... Suggested alternative: \'wire_0_3_1_4_remainter\'\n reg_2_3[3] <= wire_2_3_3_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:334: Signal definition not found, creating implicitly: \'wire_2_2_3_3_remainter\'\n : ... Suggested alternative: \'wire_0_2_1_3_remainter\'\n reg_2_3[2] <= wire_2_2_3_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:335: Signal definition not found, creating implicitly: \'wire_2_1_3_2_remainter\'\n : ... Suggested alternative: \'wire_0_1_1_2_remainter\'\n reg_2_3[1] <= wire_2_1_3_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:336: Signal definition not found, creating implicitly: \'wire_2_0_3_1_remainter\'\n : ... Suggested alternative: \'wire_0_0_1_1_remainter\'\n reg_2_3[0] <= wire_2_0_3_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:388: Signal definition not found, creating implicitly: \'wire_4_14_5_15_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_4_5[14] <= wire_4_14_5_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:389: Signal definition not found, creating implicitly: \'wire_4_13_5_14_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_4_5[13] <= wire_4_13_5_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:390: Signal definition not found, creating implicitly: \'wire_4_12_5_13_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_4_5[12] <= wire_4_12_5_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:391: Signal definition not found, creating implicitly: \'wire_4_11_5_12_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_4_5[11] <= wire_4_11_5_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:392: Signal definition not found, creating implicitly: \'wire_4_10_5_11_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_4_5[10] <= wire_4_10_5_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:393: Signal definition not found, creating implicitly: \'wire_4_9_5_10_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_4_5[9] <= wire_4_9_5_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:394: Signal definition not found, creating implicitly: \'wire_4_8_5_9_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_4_5[8] <= wire_4_8_5_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:395: Signal definition not found, creating implicitly: \'wire_4_7_5_8_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_4_5[7] <= wire_4_7_5_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:396: Signal definition not found, creating implicitly: \'wire_4_6_5_7_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_4_5[6] <= wire_4_6_5_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:397: Signal definition not found, creating implicitly: \'wire_4_5_5_6_remainter\'\n : ... Suggested alternative: \'wire_0_5_1_6_remainter\'\n reg_4_5[5] <= wire_4_5_5_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:398: Signal definition not found, creating implicitly: \'wire_4_4_5_5_remainter\'\n : ... Suggested alternative: \'wire_0_4_1_5_remainter\'\n reg_4_5[4] <= wire_4_4_5_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:399: Signal definition not found, creating implicitly: \'wire_4_3_5_4_remainter\'\n : ... Suggested alternative: \'wire_0_3_1_4_remainter\'\n reg_4_5[3] <= wire_4_3_5_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:400: Signal definition not found, creating implicitly: \'wire_4_2_5_3_remainter\'\n : ... Suggested alternative: \'wire_0_2_1_3_remainter\'\n reg_4_5[2] <= wire_4_2_5_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:401: Signal definition not found, creating implicitly: \'wire_4_1_5_2_remainter\'\n : ... Suggested alternative: \'wire_0_1_1_2_remainter\'\n reg_4_5[1] <= wire_4_1_5_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:402: Signal definition not found, creating implicitly: \'wire_4_0_5_1_remainter\'\n : ... Suggested alternative: \'wire_0_0_1_1_remainter\'\n reg_4_5[0] <= wire_4_0_5_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:454: Signal definition not found, creating implicitly: \'wire_6_14_7_15_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_6_7[14] <= wire_6_14_7_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:455: Signal definition not found, creating implicitly: \'wire_6_13_7_14_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_6_7[13] <= wire_6_13_7_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:456: Signal definition not found, creating implicitly: \'wire_6_12_7_13_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_6_7[12] <= wire_6_12_7_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:457: Signal definition not found, creating implicitly: \'wire_6_11_7_12_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_6_7[11] <= wire_6_11_7_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:458: Signal definition not found, creating implicitly: \'wire_6_10_7_11_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_6_7[10] <= wire_6_10_7_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:459: Signal definition not found, creating implicitly: \'wire_6_9_7_10_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_6_7[9] <= wire_6_9_7_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:460: Signal definition not found, creating implicitly: \'wire_6_8_7_9_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_6_7[8] <= wire_6_8_7_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:461: Signal definition not found, creating implicitly: \'wire_6_7_7_8_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_6_7[7] <= wire_6_7_7_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:462: Signal definition not found, creating implicitly: \'wire_6_6_7_7_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_6_7[6] <= wire_6_6_7_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:463: Signal definition not found, creating implicitly: \'wire_6_5_7_6_remainter\'\n : ... Suggested alternative: \'wire_0_5_1_6_remainter\'\n reg_6_7[5] <= wire_6_5_7_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:464: Signal definition not found, creating implicitly: \'wire_6_4_7_5_remainter\'\n : ... Suggested alternative: \'wire_0_4_1_5_remainter\'\n reg_6_7[4] <= wire_6_4_7_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:465: Signal definition not found, creating implicitly: \'wire_6_3_7_4_remainter\'\n : ... Suggested alternative: \'wire_0_3_1_4_remainter\'\n reg_6_7[3] <= wire_6_3_7_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:466: Signal definition not found, creating implicitly: \'wire_6_2_7_3_remainter\'\n : ... Suggested alternative: \'wire_0_2_1_3_remainter\'\n reg_6_7[2] <= wire_6_2_7_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:467: Signal definition not found, creating implicitly: \'wire_6_1_7_2_remainter\'\n : ... Suggested alternative: \'wire_0_1_1_2_remainter\'\n reg_6_7[1] <= wire_6_1_7_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:468: Signal definition not found, creating implicitly: \'wire_6_0_7_1_remainter\'\n : ... Suggested alternative: \'wire_0_0_1_1_remainter\'\n reg_6_7[0] <= wire_6_0_7_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:520: Signal definition not found, creating implicitly: \'wire_8_14_9_15_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_8_9[14] <= wire_8_14_9_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:521: Signal definition not found, creating implicitly: \'wire_8_13_9_14_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_8_9[13] <= wire_8_13_9_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:522: Signal definition not found, creating implicitly: \'wire_8_12_9_13_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_8_9[12] <= wire_8_12_9_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:523: Signal definition not found, creating implicitly: \'wire_8_11_9_12_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_8_9[11] <= wire_8_11_9_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:524: Signal definition not found, creating implicitly: \'wire_8_10_9_11_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_8_9[10] <= wire_8_10_9_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:525: Signal definition not found, creating implicitly: \'wire_8_9_9_10_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_8_9[9] <= wire_8_9_9_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:526: Signal definition not found, creating implicitly: \'wire_8_8_9_9_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_8_9[8] <= wire_8_8_9_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:527: Signal definition not found, creating implicitly: \'wire_8_7_9_8_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_8_9[7] <= wire_8_7_9_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:528: Signal definition not found, creating implicitly: \'wire_8_6_9_7_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_8_9[6] <= wire_8_6_9_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:529: Signal definition not found, creating implicitly: \'wire_8_5_9_6_remainter\'\n : ... Suggested alternative: \'wire_0_5_1_6_remainter\'\n reg_8_9[5] <= wire_8_5_9_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:530: Signal definition not found, creating implicitly: \'wire_8_4_9_5_remainter\'\n : ... Suggested alternative: \'wire_0_4_1_5_remainter\'\n reg_8_9[4] <= wire_8_4_9_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:531: Signal definition not found, creating implicitly: \'wire_8_3_9_4_remainter\'\n : ... Suggested alternative: \'wire_0_3_1_4_remainter\'\n reg_8_9[3] <= wire_8_3_9_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:532: Signal definition not found, creating implicitly: \'wire_8_2_9_3_remainter\'\n : ... Suggested alternative: \'wire_0_2_1_3_remainter\'\n reg_8_9[2] <= wire_8_2_9_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:533: Signal definition not found, creating implicitly: \'wire_8_1_9_2_remainter\'\n : ... Suggested alternative: \'wire_0_1_1_2_remainter\'\n reg_8_9[1] <= wire_8_1_9_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:534: Signal definition not found, creating implicitly: \'wire_8_0_9_1_remainter\'\n : ... Suggested alternative: \'wire_0_0_1_1_remainter\'\n reg_8_9[0] <= wire_8_0_9_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:586: Signal definition not found, creating implicitly: \'wire_10_14_11_15_remainter\'\n : ... Suggested alternative: \'wire_0_14_1_15_remainter\'\n reg_10_11[14] <= wire_10_14_11_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:587: Signal definition not found, creating implicitly: \'wire_10_13_11_14_remainter\'\n : ... Suggested alternative: \'wire_0_13_1_14_remainter\'\n reg_10_11[13] <= wire_10_13_11_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:588: Signal definition not found, creating implicitly: \'wire_10_12_11_13_remainter\'\n : ... Suggested alternative: \'wire_0_12_1_13_remainter\'\n reg_10_11[12] <= wire_10_12_11_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:589: Signal definition not found, creating implicitly: \'wire_10_11_11_12_remainter\'\n : ... Suggested alternative: \'wire_0_11_1_12_remainter\'\n reg_10_11[11] <= wire_10_11_11_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:590: Signal definition not found, creating implicitly: \'wire_10_10_11_11_remainter\'\n : ... Suggested alternative: \'wire_0_10_1_11_remainter\'\n reg_10_11[10] <= wire_10_10_11_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:591: Signal definition not found, creating implicitly: \'wire_10_9_11_10_remainter\'\n : ... Suggested alternative: \'wire_0_9_1_10_remainter\'\n reg_10_11[9] <= wire_10_9_11_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:592: Signal definition not found, creating implicitly: \'wire_10_8_11_9_remainter\'\n : ... Suggested alternative: \'wire_0_8_1_9_remainter\'\n reg_10_11[8] <= wire_10_8_11_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:593: Signal definition not found, creating implicitly: \'wire_10_7_11_8_remainter\'\n : ... Suggested alternative: \'wire_0_7_1_8_remainter\'\n reg_10_11[7] <= wire_10_7_11_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:594: Signal definition not found, creating implicitly: \'wire_10_6_11_7_remainter\'\n : ... Suggested alternative: \'wire_0_6_1_7_remainter\'\n reg_10_11[6] <= wire_10_6_11_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:595: Signal definition not found, creating implicitly: \'wire_10_5_11_6_remainter\'\n : ... Suggested alternative: \'wire_0_5_1_6_remainter\'\n reg_10_11[5] <= wire_10_5_11_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:596: Signal definition not found, creating implicitly: \'wire_10_4_11_5_remainter\'\n : ... Suggested alternative: \'wire_0_4_1_5_remainter\'\n reg_10_11[4] <= wire_10_4_11_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:597: Signal definition not found, creating implicitly: \'wire_10_3_11_4_remainter\'\n : ... Suggested alternative: \'wire_0_3_1_4_remainter\'\n reg_10_11[3] <= wire_10_3_11_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:598: Signal definition not found, creating implicitly: \'wire_10_2_11_3_remainter\'\n : ... Suggested alternative: \'wire_0_2_1_3_remainter\'\n reg_10_11[2] <= wire_10_2_11_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:599: Signal definition not found, creating implicitly: \'wire_10_1_11_2_remainter\'\n : ... Suggested alternative: \'wire_0_1_1_2_remainter\'\n reg_10_11[1] <= wire_10_1_11_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:600: Signal definition not found, creating implicitly: \'wire_10_0_11_1_remainter\'\n : ... Suggested alternative: \'wire_0_0_1_1_remainter\'\n reg_10_11[0] <= wire_10_0_11_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:651: Signal definition not found, creating implicitly: \'wire_12_14_13_15_remainter\'\n : ... Suggested alternative: \'wire_10_14_11_15_remainter\'\n reg_12_13[14] <= wire_12_14_13_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:652: Signal definition not found, creating implicitly: \'wire_12_13_13_14_remainter\'\n : ... Suggested alternative: \'wire_10_13_11_14_remainter\'\n reg_12_13[13] <= wire_12_13_13_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:653: Signal definition not found, creating implicitly: \'wire_12_12_13_13_remainter\'\n : ... Suggested alternative: \'wire_10_12_11_13_remainter\'\n reg_12_13[12] <= wire_12_12_13_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:654: Signal definition not found, creating implicitly: \'wire_12_11_13_12_remainter\'\n : ... Suggested alternative: \'wire_10_11_11_12_remainter\'\n reg_12_13[11] <= wire_12_11_13_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:655: Signal definition not found, creating implicitly: \'wire_12_10_13_11_remainter\'\n : ... Suggested alternative: \'wire_10_10_11_11_remainter\'\n reg_12_13[10] <= wire_12_10_13_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:656: Signal definition not found, creating implicitly: \'wire_12_9_13_10_remainter\'\n : ... Suggested alternative: \'wire_10_9_11_10_remainter\'\n reg_12_13[9] <= wire_12_9_13_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:657: Signal definition not found, creating implicitly: \'wire_12_8_13_9_remainter\'\n : ... Suggested alternative: \'wire_10_8_11_9_remainter\'\n reg_12_13[8] <= wire_12_8_13_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:658: Signal definition not found, creating implicitly: \'wire_12_7_13_8_remainter\'\n : ... Suggested alternative: \'wire_10_7_11_8_remainter\'\n reg_12_13[7] <= wire_12_7_13_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:659: Signal definition not found, creating implicitly: \'wire_12_6_13_7_remainter\'\n : ... Suggested alternative: \'wire_10_6_11_7_remainter\'\n reg_12_13[6] <= wire_12_6_13_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:660: Signal definition not found, creating implicitly: \'wire_12_5_13_6_remainter\'\n : ... Suggested alternative: \'wire_10_5_11_6_remainter\'\n reg_12_13[5] <= wire_12_5_13_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:661: Signal definition not found, creating implicitly: \'wire_12_4_13_5_remainter\'\n : ... Suggested alternative: \'wire_10_4_11_5_remainter\'\n reg_12_13[4] <= wire_12_4_13_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:662: Signal definition not found, creating implicitly: \'wire_12_3_13_4_remainter\'\n : ... Suggested alternative: \'wire_10_3_11_4_remainter\'\n reg_12_13[3] <= wire_12_3_13_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:663: Signal definition not found, creating implicitly: \'wire_12_2_13_3_remainter\'\n : ... Suggested alternative: \'wire_10_2_11_3_remainter\'\n reg_12_13[2] <= wire_12_2_13_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:664: Signal definition not found, creating implicitly: \'wire_12_1_13_2_remainter\'\n : ... Suggested alternative: \'wire_10_1_11_2_remainter\'\n reg_12_13[1] <= wire_12_1_13_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:665: Signal definition not found, creating implicitly: \'wire_12_0_13_1_remainter\'\n : ... Suggested alternative: \'wire_10_0_11_1_remainter\'\n reg_12_13[0] <= wire_12_0_13_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:717: Signal definition not found, creating implicitly: \'wire_14_14_15_15_remainter\'\n : ... Suggested alternative: \'wire_10_14_11_15_remainter\'\n reg_14_15[14] <= wire_14_14_15_15_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:718: Signal definition not found, creating implicitly: \'wire_14_13_15_14_remainter\'\n : ... Suggested alternative: \'wire_10_13_11_14_remainter\'\n reg_14_15[13] <= wire_14_13_15_14_remainter; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:719: Signal definition not found, creating implicitly: \'wire_14_12_15_13_remainter\'\n : ... Suggested alternative: \'wire_10_12_11_13_remainter\'\n reg_14_15[12] <= wire_14_12_15_13_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:720: Signal definition not found, creating implicitly: \'wire_14_11_15_12_remainter\'\n : ... Suggested alternative: \'wire_10_11_11_12_remainter\'\n reg_14_15[11] <= wire_14_11_15_12_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:721: Signal definition not found, creating implicitly: \'wire_14_10_15_11_remainter\'\n : ... Suggested alternative: \'wire_10_10_11_11_remainter\'\n reg_14_15[10] <= wire_14_10_15_11_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:722: Signal definition not found, creating implicitly: \'wire_14_9_15_10_remainter\'\n : ... Suggested alternative: \'wire_10_9_11_10_remainter\'\n reg_14_15[9] <= wire_14_9_15_10_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:723: Signal definition not found, creating implicitly: \'wire_14_8_15_9_remainter\'\n : ... Suggested alternative: \'wire_10_8_11_9_remainter\'\n reg_14_15[8] <= wire_14_8_15_9_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:724: Signal definition not found, creating implicitly: \'wire_14_7_15_8_remainter\'\n : ... Suggested alternative: \'wire_10_7_11_8_remainter\'\n reg_14_15[7] <= wire_14_7_15_8_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:725: Signal definition not found, creating implicitly: \'wire_14_6_15_7_remainter\'\n : ... Suggested alternative: \'wire_10_6_11_7_remainter\'\n reg_14_15[6] <= wire_14_6_15_7_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:726: Signal definition not found, creating implicitly: \'wire_14_5_15_6_remainter\'\n : ... Suggested alternative: \'wire_10_5_11_6_remainter\'\n reg_14_15[5] <= wire_14_5_15_6_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:727: Signal definition not found, creating implicitly: \'wire_14_4_15_5_remainter\'\n : ... Suggested alternative: \'wire_10_4_11_5_remainter\'\n reg_14_15[4] <= wire_14_4_15_5_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:728: Signal definition not found, creating implicitly: \'wire_14_3_15_4_remainter\'\n : ... Suggested alternative: \'wire_10_3_11_4_remainter\'\n reg_14_15[3] <= wire_14_3_15_4_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:729: Signal definition not found, creating implicitly: \'wire_14_2_15_3_remainter\'\n : ... Suggested alternative: \'wire_10_2_11_3_remainter\'\n reg_14_15[2] <= wire_14_2_15_3_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:730: Signal definition not found, creating implicitly: \'wire_14_1_15_2_remainter\'\n : ... Suggested alternative: \'wire_10_1_11_2_remainter\'\n reg_14_15[1] <= wire_14_1_15_2_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:731: Signal definition not found, creating implicitly: \'wire_14_0_15_1_remainter\'\n : ... Suggested alternative: \'wire_10_0_11_1_remainter\'\n reg_14_15[0] <= wire_14_0_15_1_remainter;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:219: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance interconect_cells\n cycle_count <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:230: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_15 ( one , two_sc_divisor[15] , two_sc_dividend[31] , wire_out_quotient[16] , wire_0_14_15_curry , hang_0_wire_15 );\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/div_cell\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/div_cell.v\n data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/div_cell.sv\n div_cell\n div_cell.v\n div_cell.sv\n obj_dir/div_cell\n obj_dir/div_cell.v\n obj_dir/div_cell.sv\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:232: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_14 ( one , two_sc_divisor[14] , two_sc_dividend[30] , wire_0_14_1_15_remainter , wire_0_13_14_curry , wire_0_14_15_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:233: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_13 ( one , two_sc_divisor[13] , two_sc_dividend[29] , wire_0_13_1_14_remainter , wire_0_12_13_curry , wire_0_13_14_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:234: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_12 ( one , two_sc_divisor[12] , two_sc_dividend[28] , wire_0_12_1_13_remainter , wire_0_11_12_curry , wire_0_12_13_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:235: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_11 ( one , two_sc_divisor[11] , two_sc_dividend[27] , wire_0_11_1_12_remainter , wire_0_10_11_curry , wire_0_11_12_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:236: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_10 ( one , two_sc_divisor[10] , two_sc_dividend[26] , wire_0_10_1_11_remainter , wire_0_09_10_curry , wire_0_10_11_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:237: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_9 ( one , two_sc_divisor[9] , two_sc_dividend[25] , wire_0_9_1_10_remainter , wire_0_08_09_curry , wire_0_09_10_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:238: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_8 ( one , two_sc_divisor[8] , two_sc_dividend[24] , wire_0_8_1_9_remainter , wire_0_07_08_curry , wire_0_08_09_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:239: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_7 ( one , two_sc_divisor[7] , two_sc_dividend[23] , wire_0_7_1_8_remainter , wire_0_06_07_curry , wire_0_07_08_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:240: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_6 ( one , two_sc_divisor[6] , two_sc_dividend[22] , wire_0_6_1_7_remainter , wire_0_05_06_curry , wire_0_06_07_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:241: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_5 ( one , two_sc_divisor[5] , two_sc_dividend[21] , wire_0_5_1_6_remainter , wire_0_04_05_curry , wire_0_05_06_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:242: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_4 ( one , two_sc_divisor[4] , two_sc_dividend[20] , wire_0_4_1_5_remainter , wire_0_03_04_curry , wire_0_04_05_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:243: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_3 ( one , two_sc_divisor[3] , two_sc_dividend[19] , wire_0_3_1_4_remainter , wire_0_02_03_curry , wire_0_03_04_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:244: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_2 ( one , two_sc_divisor[2] , two_sc_dividend[18] , wire_0_2_1_3_remainter , wire_0_01_02_curry , wire_0_02_03_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:245: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_1 ( one , two_sc_divisor[1] , two_sc_dividend[17] , wire_0_1_1_2_remainter , wire_0_00_01_curry , wire_0_01_02_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:247: Cannot find file containing module: \'div_cell\'\n div_cell cas_0_0 ( one , two_sc_divisor[0] , two_sc_dividend[16] , wire_0_0_1_1_remainter , one , wire_0_00_01_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:277: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_15 (~reg_0_1_curry, two_sc_divisor[15], reg_0_1[14] , wire_out_quotient[15], wire_1_14_15_curry, hang_1_wire_15);\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:279: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_14 ( ~reg_0_1_curry , two_sc_divisor[14] , reg_0_1[13] , wire_1_14_2_15_remainter , wire_1_13_14_curry , wire_1_14_15_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:280: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_13 ( ~reg_0_1_curry , two_sc_divisor[13] , reg_0_1[12] , wire_1_13_2_14_remainter , wire_1_12_13_curry , wire_1_13_14_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:281: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_12 ( ~reg_0_1_curry , two_sc_divisor[12] , reg_0_1[11] , wire_1_12_2_13_remainter , wire_1_11_12_curry , wire_1_12_13_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:282: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_11 ( ~reg_0_1_curry , two_sc_divisor[11] , reg_0_1[10] , wire_1_11_2_12_remainter , wire_1_10_11_curry , wire_1_11_12_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:283: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_10 ( ~reg_0_1_curry , two_sc_divisor[10] , reg_0_1[9], wire_1_10_2_11_remainter , wire_1_09_10_curry , wire_1_10_11_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:284: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_9 ( ~reg_0_1_curry , two_sc_divisor[9] , reg_0_1[8] , wire_1_9_2_10_remainter , wire_1_08_09_curry , wire_1_09_10_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:285: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_8 ( ~reg_0_1_curry , two_sc_divisor[8] , reg_0_1[7] , wire_1_8_2_9_remainter , wire_1_07_08_curry , wire_1_08_09_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:286: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_7 ( ~reg_0_1_curry , two_sc_divisor[7] , reg_0_1[6] , wire_1_7_2_8_remainter , wire_1_06_07_curry , wire_1_07_08_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:287: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_6 ( ~reg_0_1_curry , two_sc_divisor[6] , reg_0_1[5] , wire_1_6_2_7_remainter , wire_1_05_06_curry , wire_1_06_07_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:288: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_5 ( ~reg_0_1_curry , two_sc_divisor[5] , reg_0_1[4] , wire_1_5_2_6_remainter , wire_1_04_05_curry , wire_1_05_06_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:289: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_4 ( ~reg_0_1_curry , two_sc_divisor[4] , reg_0_1[3] , wire_1_4_2_5_remainter , wire_1_03_04_curry , wire_1_04_05_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:290: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_3 ( ~reg_0_1_curry , two_sc_divisor[3] , reg_0_1[2] , wire_1_3_2_4_remainter , wire_1_02_03_curry , wire_1_03_04_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:291: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_2 ( ~reg_0_1_curry , two_sc_divisor[2] , reg_0_1[1] , wire_1_2_2_3_remainter , wire_1_01_02_curry , wire_1_02_03_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:292: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_1 ( ~reg_0_1_curry , two_sc_divisor[1] , reg_0_1[0] , wire_1_1_2_2_remainter , wire_1_00_01_curry , wire_1_01_02_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:294: Cannot find file containing module: \'div_cell\'\n div_cell cas_1_0 ( ~reg_0_1_curry , two_sc_divisor[0] , two_sc_dividend[15] , wire_1_0_2_1_remainter , ~reg_0_1_curry , wire_1_00_01_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:297: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_15 ( ~wire_out_quotient[15] , two_sc_divisor[15] , wire_1_14_2_15_remainter , wire_out_quotient[14] , wire_2_14_15_curry , hang_2_wire_15 );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:299: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_14 ( ~wire_out_quotient[15] , two_sc_divisor[14] , wire_1_13_2_14_remainter , wire_2_14_3_15_remainter , wire_2_13_14_curry , wire_2_14_15_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:300: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_13 ( ~wire_out_quotient[15] , two_sc_divisor[13] , wire_1_12_2_13_remainter , wire_2_13_3_14_remainter , wire_2_12_13_curry , wire_2_13_14_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:301: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_12 ( ~wire_out_quotient[15] , two_sc_divisor[12] , wire_1_11_2_12_remainter , wire_2_12_3_13_remainter , wire_2_11_12_curry , wire_2_12_13_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:302: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_11 ( ~wire_out_quotient[15] , two_sc_divisor[11] , wire_1_10_2_11_remainter , wire_2_11_3_12_remainter , wire_2_10_11_curry , wire_2_11_12_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:303: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_10 ( ~wire_out_quotient[15] , two_sc_divisor[10] , wire_1_9_2_10_remainter , wire_2_10_3_11_remainter , wire_2_09_10_curry , wire_2_10_11_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:304: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_9 ( ~wire_out_quotient[15] , two_sc_divisor[9] , wire_1_8_2_9_remainter , wire_2_9_3_10_remainter , wire_2_08_09_curry , wire_2_09_10_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:305: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_8 ( ~wire_out_quotient[15] , two_sc_divisor[8] , wire_1_7_2_8_remainter , wire_2_8_3_9_remainter , wire_2_07_08_curry , wire_2_08_09_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:306: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_7 ( ~wire_out_quotient[15] , two_sc_divisor[7] , wire_1_6_2_7_remainter , wire_2_7_3_8_remainter , wire_2_06_07_curry , wire_2_07_08_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:307: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_6 ( ~wire_out_quotient[15] , two_sc_divisor[6] , wire_1_5_2_6_remainter , wire_2_6_3_7_remainter , wire_2_05_06_curry , wire_2_06_07_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:308: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_5 ( ~wire_out_quotient[15] , two_sc_divisor[5] , wire_1_4_2_5_remainter , wire_2_5_3_6_remainter , wire_2_04_05_curry , wire_2_05_06_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:309: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_4 ( ~wire_out_quotient[15] , two_sc_divisor[4] , wire_1_3_2_4_remainter , wire_2_4_3_5_remainter , wire_2_03_04_curry , wire_2_04_05_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:310: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_3 ( ~wire_out_quotient[15] , two_sc_divisor[3] , wire_1_2_2_3_remainter , wire_2_3_3_4_remainter , wire_2_02_03_curry , wire_2_03_04_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:311: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_2 ( ~wire_out_quotient[15] , two_sc_divisor[2] , wire_1_1_2_2_remainter , wire_2_2_3_3_remainter , wire_2_01_02_curry , wire_2_02_03_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:312: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_1 ( ~wire_out_quotient[15] , two_sc_divisor[1] , wire_1_0_2_1_remainter , wire_2_1_3_2_remainter , wire_2_00_01_curry , wire_2_01_02_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:314: Cannot find file containing module: \'div_cell\'\n div_cell cas_2_0 ( ~wire_out_quotient[15] , two_sc_divisor[0] , two_sc_dividend[14] , wire_2_0_3_1_remainter , ~wire_out_quotient[15] , wire_2_00_01_curry );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:343: Cannot find file containing module: \'div_cell\'\n div_cell cas_3_15 ( ~reg_2_3_curry , two_sc_divisor[15] , reg_2_3[14] , wire_out_quotient[13] , wire_3_14_15_curry , hang_3_wire_15 );\n ^~~~~~~~\n%Error: data/full_repos/permissive/106583614/Final_project_divider/interconect_cells.v:345: Cannot find file containing module: \'div_cell\'\n div_cell cas_3_14 ( ~reg_2_3_curry , two_sc_divisor[14] , reg_2_3[13] , wire_3_14_4_15_remainter , wire_3_13_14_curry , wire_3_14_15_curry );\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 1,535 | module | module interconect_cells(
clk,
reset,
in_divisor,
in_dividend,
valid_input,
valid_output,
mod_res,
div_res_tmp
);
input signed [31:0] in_dividend;
input signed [15:0] in_divisor;
input clk, reset;
input valid_input;
output reg valid_output;
reg signed [16:0] div_res;
output reg signed [15:0] mod_res;
output reg signed [16:0] div_res_tmp;
reg signed [31:0] dividend;
reg signed [15:0] divisor;
reg signed [31:0] two_sc_dividend;
reg signed [15:0] two_sc_divisor;
wire [16:0] wire_out_quotient;
wire [14:0] wire_out_remainder;
wire one=1'b1;
reg [2:0] cycle_count;
reg [14:0] reg_14_15;
reg [14:0] reg_12_13;
reg [14:0] reg_10_11;
reg [14:0] reg_8_9;
reg [14:0] reg_6_7;
reg [14:0] reg_4_5;
reg [14:0] reg_2_3;
reg [14:0] reg_0_1;
reg reg_14_15_curry;
reg reg_12_13_curry;
reg reg_10_11_curry;
reg reg_8_9_curry;
reg reg_6_7_curry;
reg reg_4_5_curry;
reg reg_2_3_curry;
reg reg_0_1_curry;
always @(posedge clk or posedge reset) begin
if (reset) begin
dividend <= 'b0;
divisor <= 'b0;
end else begin
if (!valid_input) begin
dividend <= 'b0;
divisor <= 'b0;
end else begin
dividend <= in_dividend;
divisor <= in_divisor;
end
end
end
always @(*) begin
if (reset) begin
div_res[16] = 'd0;
div_res[15] = 'd0;
div_res[14] = 'd0;
div_res[13] = 'd0;
div_res[12] = 'd0;
div_res[11] = 'd0;
div_res[10] = 'd0;
div_res[9] = 'd0;
div_res[8] = 'd0;
div_res[7] = 'd0;
div_res[6] = 'd0;
div_res[5] = 'd0;
div_res[4] = 'd0;
div_res[3] = 'd0;
div_res[2] = 'd0;
div_res[1] = 'd0;
div_res[0] = 'd0;
end else begin
div_res[16] = ~wire_out_quotient[16];
div_res[15] = ~wire_out_quotient[15];
div_res[14] = ~wire_out_quotient[14];
div_res[13] = ~wire_out_quotient[13];
div_res[12] = ~wire_out_quotient[12];
div_res[11] = ~wire_out_quotient[11];
div_res[10] = ~wire_out_quotient[10];
div_res[9] = ~wire_out_quotient[9];
div_res[8] = ~wire_out_quotient[8];
div_res[7] = ~wire_out_quotient[7];
div_res[6] = ~wire_out_quotient[6];
div_res[5] = ~wire_out_quotient[5];
div_res[4] = ~wire_out_quotient[4];
div_res[3] = ~wire_out_quotient[3];
div_res[2] = ~wire_out_quotient[2];
div_res[1] = ~wire_out_quotient[1];
div_res[0] = ~wire_out_quotient[0];
end
end
always @(*) begin
if ((dividend[31] && !divisor[15]) || (!dividend[31] && divisor[15])) begin
div_res_tmp = ~div_res;
end else begin
div_res_tmp = div_res;
end
end
always @(*) begin
if (reset) begin
mod_res[15] ='d0;
mod_res[14] ='d0;
mod_res[13] ='d0;
mod_res[12] ='d0;
mod_res[11] ='d0;
mod_res[10] ='d0;
mod_res[9] = 'd0;
mod_res[8] = 'd0;
mod_res[7] = 'd0;
mod_res[6] = 'd0;
mod_res[5] = 'd0;
mod_res[4] = 'd0;
mod_res[3] = 'd0;
mod_res[2] = 'd0;
mod_res[1] = 'd0;
mod_res[0] = 'd0;
end else begin
mod_res[15] = wire_out_quotient[0];
mod_res[14] = wire_out_remainder[14];
mod_res[13] = wire_out_remainder[13];
mod_res[12] = wire_out_remainder[12];
mod_res[11] = wire_out_remainder[11];
mod_res[10] = wire_out_remainder[10];
mod_res[9] = wire_out_remainder[9];
mod_res[8] = wire_out_remainder[8];
mod_res[7] = wire_out_remainder[7];
mod_res[6] = wire_out_remainder[6];
mod_res[5] = wire_out_remainder[5];
mod_res[4] = wire_out_remainder[4];
mod_res[3] = wire_out_remainder[3];
mod_res[2] = wire_out_remainder[2];
mod_res[1] = wire_out_remainder[1];
mod_res[0] = wire_out_remainder[0];
if ( (dividend[31] == 1) && (divisor[15] == 0) ) begin
mod_res = ~mod_res;
mod_res = mod_res + 1'b1;
if (wire_out_quotient[0] == 1) begin
mod_res = mod_res + divisor;
end
end
if ( (wire_out_quotient[0] == 1) && (dividend[31] == 0) && (divisor[15] == 0)) begin
mod_res = mod_res + divisor;
end
if ( (divisor[15] == 1) && (dividend[31] ==1 ) ) begin
mod_res = ~mod_res;
mod_res = mod_res + 1'b1;
if (wire_out_quotient[0] == 1) begin
mod_res = mod_res + divisor;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
two_sc_divisor = 'b0;
two_sc_dividend = 'b0;
end else begin
if (divisor[15]) begin
two_sc_divisor = ~divisor;
two_sc_divisor = two_sc_divisor + 1'b1;
end else begin
two_sc_divisor = divisor;
end
if (dividend[31]) begin
two_sc_dividend = ~dividend;
two_sc_dividend = two_sc_dividend + 1'b1;
end else begin
two_sc_dividend = dividend;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
valid_output <= 1'b0;
cycle_count <= 'b0;
end else begin
cycle_count <= cycle_count + 1'b1;
if (cycle_count == 4) begin
valid_output <= 1'b1;
cycle_count <= 1'b0;
end else begin
valid_output <= 1'b0;
end
end
end
div_cell cas_0_15 ( one , two_sc_divisor[15] , two_sc_dividend[31] , wire_out_quotient[16] , wire_0_14_15_curry , hang_0_wire_15 );
div_cell cas_0_14 ( one , two_sc_divisor[14] , two_sc_dividend[30] , wire_0_14_1_15_remainter , wire_0_13_14_curry , wire_0_14_15_curry );
div_cell cas_0_13 ( one , two_sc_divisor[13] , two_sc_dividend[29] , wire_0_13_1_14_remainter , wire_0_12_13_curry , wire_0_13_14_curry );
div_cell cas_0_12 ( one , two_sc_divisor[12] , two_sc_dividend[28] , wire_0_12_1_13_remainter , wire_0_11_12_curry , wire_0_12_13_curry );
div_cell cas_0_11 ( one , two_sc_divisor[11] , two_sc_dividend[27] , wire_0_11_1_12_remainter , wire_0_10_11_curry , wire_0_11_12_curry );
div_cell cas_0_10 ( one , two_sc_divisor[10] , two_sc_dividend[26] , wire_0_10_1_11_remainter , wire_0_09_10_curry , wire_0_10_11_curry );
div_cell cas_0_9 ( one , two_sc_divisor[9] , two_sc_dividend[25] , wire_0_9_1_10_remainter , wire_0_08_09_curry , wire_0_09_10_curry );
div_cell cas_0_8 ( one , two_sc_divisor[8] , two_sc_dividend[24] , wire_0_8_1_9_remainter , wire_0_07_08_curry , wire_0_08_09_curry );
div_cell cas_0_7 ( one , two_sc_divisor[7] , two_sc_dividend[23] , wire_0_7_1_8_remainter , wire_0_06_07_curry , wire_0_07_08_curry );
div_cell cas_0_6 ( one , two_sc_divisor[6] , two_sc_dividend[22] , wire_0_6_1_7_remainter , wire_0_05_06_curry , wire_0_06_07_curry );
div_cell cas_0_5 ( one , two_sc_divisor[5] , two_sc_dividend[21] , wire_0_5_1_6_remainter , wire_0_04_05_curry , wire_0_05_06_curry );
div_cell cas_0_4 ( one , two_sc_divisor[4] , two_sc_dividend[20] , wire_0_4_1_5_remainter , wire_0_03_04_curry , wire_0_04_05_curry );
div_cell cas_0_3 ( one , two_sc_divisor[3] , two_sc_dividend[19] , wire_0_3_1_4_remainter , wire_0_02_03_curry , wire_0_03_04_curry );
div_cell cas_0_2 ( one , two_sc_divisor[2] , two_sc_dividend[18] , wire_0_2_1_3_remainter , wire_0_01_02_curry , wire_0_02_03_curry );
div_cell cas_0_1 ( one , two_sc_divisor[1] , two_sc_dividend[17] , wire_0_1_1_2_remainter , wire_0_00_01_curry , wire_0_01_02_curry );
div_cell cas_0_0 ( one , two_sc_divisor[0] , two_sc_dividend[16] , wire_0_0_1_1_remainter , one , wire_0_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_0_1 <= 'b0;
reg_0_1_curry <= 'b0;
end else begin
reg_0_1[14] <= wire_0_14_1_15_remainter;
reg_0_1[13] <= wire_0_13_1_14_remainter;
reg_0_1[12] <= wire_0_12_1_13_remainter;
reg_0_1[11] <= wire_0_11_1_12_remainter;
reg_0_1[10] <= wire_0_10_1_11_remainter;
reg_0_1[9] <= wire_0_9_1_10_remainter;
reg_0_1[8] <= wire_0_8_1_9_remainter;
reg_0_1[7] <= wire_0_7_1_8_remainter;
reg_0_1[6] <= wire_0_6_1_7_remainter;
reg_0_1[5] <= wire_0_5_1_6_remainter;
reg_0_1[4] <= wire_0_4_1_5_remainter;
reg_0_1[3] <= wire_0_3_1_4_remainter;
reg_0_1[2] <= wire_0_2_1_3_remainter;
reg_0_1[1] <= wire_0_1_1_2_remainter;
reg_0_1[0] <= wire_0_0_1_1_remainter;
reg_0_1_curry <= wire_out_quotient[16];
end
end
div_cell cas_1_15 (~reg_0_1_curry, two_sc_divisor[15], reg_0_1[14] , wire_out_quotient[15], wire_1_14_15_curry, hang_1_wire_15);
div_cell cas_1_14 ( ~reg_0_1_curry , two_sc_divisor[14] , reg_0_1[13] , wire_1_14_2_15_remainter , wire_1_13_14_curry , wire_1_14_15_curry );
div_cell cas_1_13 ( ~reg_0_1_curry , two_sc_divisor[13] , reg_0_1[12] , wire_1_13_2_14_remainter , wire_1_12_13_curry , wire_1_13_14_curry );
div_cell cas_1_12 ( ~reg_0_1_curry , two_sc_divisor[12] , reg_0_1[11] , wire_1_12_2_13_remainter , wire_1_11_12_curry , wire_1_12_13_curry );
div_cell cas_1_11 ( ~reg_0_1_curry , two_sc_divisor[11] , reg_0_1[10] , wire_1_11_2_12_remainter , wire_1_10_11_curry , wire_1_11_12_curry );
div_cell cas_1_10 ( ~reg_0_1_curry , two_sc_divisor[10] , reg_0_1[9], wire_1_10_2_11_remainter , wire_1_09_10_curry , wire_1_10_11_curry );
div_cell cas_1_9 ( ~reg_0_1_curry , two_sc_divisor[9] , reg_0_1[8] , wire_1_9_2_10_remainter , wire_1_08_09_curry , wire_1_09_10_curry );
div_cell cas_1_8 ( ~reg_0_1_curry , two_sc_divisor[8] , reg_0_1[7] , wire_1_8_2_9_remainter , wire_1_07_08_curry , wire_1_08_09_curry );
div_cell cas_1_7 ( ~reg_0_1_curry , two_sc_divisor[7] , reg_0_1[6] , wire_1_7_2_8_remainter , wire_1_06_07_curry , wire_1_07_08_curry );
div_cell cas_1_6 ( ~reg_0_1_curry , two_sc_divisor[6] , reg_0_1[5] , wire_1_6_2_7_remainter , wire_1_05_06_curry , wire_1_06_07_curry );
div_cell cas_1_5 ( ~reg_0_1_curry , two_sc_divisor[5] , reg_0_1[4] , wire_1_5_2_6_remainter , wire_1_04_05_curry , wire_1_05_06_curry );
div_cell cas_1_4 ( ~reg_0_1_curry , two_sc_divisor[4] , reg_0_1[3] , wire_1_4_2_5_remainter , wire_1_03_04_curry , wire_1_04_05_curry );
div_cell cas_1_3 ( ~reg_0_1_curry , two_sc_divisor[3] , reg_0_1[2] , wire_1_3_2_4_remainter , wire_1_02_03_curry , wire_1_03_04_curry );
div_cell cas_1_2 ( ~reg_0_1_curry , two_sc_divisor[2] , reg_0_1[1] , wire_1_2_2_3_remainter , wire_1_01_02_curry , wire_1_02_03_curry );
div_cell cas_1_1 ( ~reg_0_1_curry , two_sc_divisor[1] , reg_0_1[0] , wire_1_1_2_2_remainter , wire_1_00_01_curry , wire_1_01_02_curry );
div_cell cas_1_0 ( ~reg_0_1_curry , two_sc_divisor[0] , two_sc_dividend[15] , wire_1_0_2_1_remainter , ~reg_0_1_curry , wire_1_00_01_curry );
div_cell cas_2_15 ( ~wire_out_quotient[15] , two_sc_divisor[15] , wire_1_14_2_15_remainter , wire_out_quotient[14] , wire_2_14_15_curry , hang_2_wire_15 );
div_cell cas_2_14 ( ~wire_out_quotient[15] , two_sc_divisor[14] , wire_1_13_2_14_remainter , wire_2_14_3_15_remainter , wire_2_13_14_curry , wire_2_14_15_curry );
div_cell cas_2_13 ( ~wire_out_quotient[15] , two_sc_divisor[13] , wire_1_12_2_13_remainter , wire_2_13_3_14_remainter , wire_2_12_13_curry , wire_2_13_14_curry );
div_cell cas_2_12 ( ~wire_out_quotient[15] , two_sc_divisor[12] , wire_1_11_2_12_remainter , wire_2_12_3_13_remainter , wire_2_11_12_curry , wire_2_12_13_curry );
div_cell cas_2_11 ( ~wire_out_quotient[15] , two_sc_divisor[11] , wire_1_10_2_11_remainter , wire_2_11_3_12_remainter , wire_2_10_11_curry , wire_2_11_12_curry );
div_cell cas_2_10 ( ~wire_out_quotient[15] , two_sc_divisor[10] , wire_1_9_2_10_remainter , wire_2_10_3_11_remainter , wire_2_09_10_curry , wire_2_10_11_curry );
div_cell cas_2_9 ( ~wire_out_quotient[15] , two_sc_divisor[9] , wire_1_8_2_9_remainter , wire_2_9_3_10_remainter , wire_2_08_09_curry , wire_2_09_10_curry );
div_cell cas_2_8 ( ~wire_out_quotient[15] , two_sc_divisor[8] , wire_1_7_2_8_remainter , wire_2_8_3_9_remainter , wire_2_07_08_curry , wire_2_08_09_curry );
div_cell cas_2_7 ( ~wire_out_quotient[15] , two_sc_divisor[7] , wire_1_6_2_7_remainter , wire_2_7_3_8_remainter , wire_2_06_07_curry , wire_2_07_08_curry );
div_cell cas_2_6 ( ~wire_out_quotient[15] , two_sc_divisor[6] , wire_1_5_2_6_remainter , wire_2_6_3_7_remainter , wire_2_05_06_curry , wire_2_06_07_curry );
div_cell cas_2_5 ( ~wire_out_quotient[15] , two_sc_divisor[5] , wire_1_4_2_5_remainter , wire_2_5_3_6_remainter , wire_2_04_05_curry , wire_2_05_06_curry );
div_cell cas_2_4 ( ~wire_out_quotient[15] , two_sc_divisor[4] , wire_1_3_2_4_remainter , wire_2_4_3_5_remainter , wire_2_03_04_curry , wire_2_04_05_curry );
div_cell cas_2_3 ( ~wire_out_quotient[15] , two_sc_divisor[3] , wire_1_2_2_3_remainter , wire_2_3_3_4_remainter , wire_2_02_03_curry , wire_2_03_04_curry );
div_cell cas_2_2 ( ~wire_out_quotient[15] , two_sc_divisor[2] , wire_1_1_2_2_remainter , wire_2_2_3_3_remainter , wire_2_01_02_curry , wire_2_02_03_curry );
div_cell cas_2_1 ( ~wire_out_quotient[15] , two_sc_divisor[1] , wire_1_0_2_1_remainter , wire_2_1_3_2_remainter , wire_2_00_01_curry , wire_2_01_02_curry );
div_cell cas_2_0 ( ~wire_out_quotient[15] , two_sc_divisor[0] , two_sc_dividend[14] , wire_2_0_3_1_remainter , ~wire_out_quotient[15] , wire_2_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_2_3 <= 'b0;
reg_2_3_curry <= 'b0;
end else begin
reg_2_3[14] <= wire_2_14_3_15_remainter;
reg_2_3[13] <= wire_2_13_3_14_remainter;
reg_2_3[12] <= wire_2_12_3_13_remainter;
reg_2_3[11] <= wire_2_11_3_12_remainter;
reg_2_3[10] <= wire_2_10_3_11_remainter;
reg_2_3[9] <= wire_2_9_3_10_remainter;
reg_2_3[8] <= wire_2_8_3_9_remainter;
reg_2_3[7] <= wire_2_7_3_8_remainter;
reg_2_3[6] <= wire_2_6_3_7_remainter;
reg_2_3[5] <= wire_2_5_3_6_remainter;
reg_2_3[4] <= wire_2_4_3_5_remainter;
reg_2_3[3] <= wire_2_3_3_4_remainter;
reg_2_3[2] <= wire_2_2_3_3_remainter;
reg_2_3[1] <= wire_2_1_3_2_remainter;
reg_2_3[0] <= wire_2_0_3_1_remainter;
reg_2_3_curry <= wire_out_quotient[14];
end
end
div_cell cas_3_15 ( ~reg_2_3_curry , two_sc_divisor[15] , reg_2_3[14] , wire_out_quotient[13] , wire_3_14_15_curry , hang_3_wire_15 );
div_cell cas_3_14 ( ~reg_2_3_curry , two_sc_divisor[14] , reg_2_3[13] , wire_3_14_4_15_remainter , wire_3_13_14_curry , wire_3_14_15_curry );
div_cell cas_3_13 ( ~reg_2_3_curry , two_sc_divisor[13] , reg_2_3[12] , wire_3_13_4_14_remainter , wire_3_12_13_curry , wire_3_13_14_curry );
div_cell cas_3_12 ( ~reg_2_3_curry , two_sc_divisor[12] , reg_2_3[11] , wire_3_12_4_13_remainter , wire_3_11_12_curry , wire_3_12_13_curry );
div_cell cas_3_11 ( ~reg_2_3_curry , two_sc_divisor[11] , reg_2_3[10] , wire_3_11_4_12_remainter , wire_3_10_11_curry , wire_3_11_12_curry );
div_cell cas_3_10 ( ~reg_2_3_curry , two_sc_divisor[10] , reg_2_3[9], wire_3_10_4_11_remainter , wire_3_09_10_curry , wire_3_10_11_curry );
div_cell cas_3_9 ( ~reg_2_3_curry , two_sc_divisor[9] , reg_2_3[8] , wire_3_9_4_10_remainter , wire_3_08_09_curry , wire_3_09_10_curry );
div_cell cas_3_8 ( ~reg_2_3_curry , two_sc_divisor[8] , reg_2_3[7] , wire_3_8_4_9_remainter , wire_3_07_08_curry , wire_3_08_09_curry );
div_cell cas_3_7 ( ~reg_2_3_curry , two_sc_divisor[7] , reg_2_3[6] , wire_3_7_4_8_remainter , wire_3_06_07_curry , wire_3_07_08_curry );
div_cell cas_3_6 ( ~reg_2_3_curry , two_sc_divisor[6] , reg_2_3[5] , wire_3_6_4_7_remainter , wire_3_05_06_curry , wire_3_06_07_curry );
div_cell cas_3_5 ( ~reg_2_3_curry , two_sc_divisor[5] , reg_2_3[4] , wire_3_5_4_6_remainter , wire_3_04_05_curry , wire_3_05_06_curry );
div_cell cas_3_4 ( ~reg_2_3_curry , two_sc_divisor[4] , reg_2_3[3] , wire_3_4_4_5_remainter , wire_3_03_04_curry , wire_3_04_05_curry );
div_cell cas_3_3 ( ~reg_2_3_curry , two_sc_divisor[3] , reg_2_3[2] , wire_3_3_4_4_remainter , wire_3_02_03_curry , wire_3_03_04_curry );
div_cell cas_3_2 ( ~reg_2_3_curry , two_sc_divisor[2] , reg_2_3[1] , wire_3_2_4_3_remainter , wire_3_01_02_curry , wire_3_02_03_curry );
div_cell cas_3_1 ( ~reg_2_3_curry , two_sc_divisor[1] , reg_2_3[0] , wire_3_1_4_2_remainter , wire_3_00_01_curry , wire_3_01_02_curry );
div_cell cas_3_0 ( ~reg_2_3_curry , two_sc_divisor[0] , two_sc_dividend[13] , wire_3_0_4_1_remainter , ~reg_2_3_curry , wire_3_00_01_curry );
div_cell cas_4_15 ( ~wire_out_quotient[13] , two_sc_divisor[15] , wire_3_14_4_15_remainter , wire_out_quotient[12] , wire_4_14_15_curry , hang_4_wire_15 );
div_cell cas_4_14 ( ~wire_out_quotient[13] , two_sc_divisor[14] , wire_3_13_4_14_remainter , wire_4_14_5_15_remainter , wire_4_13_14_curry , wire_4_14_15_curry );
div_cell cas_4_13 ( ~wire_out_quotient[13] , two_sc_divisor[13] , wire_3_12_4_13_remainter , wire_4_13_5_14_remainter , wire_4_12_13_curry , wire_4_13_14_curry );
div_cell cas_4_12 ( ~wire_out_quotient[13] , two_sc_divisor[12] , wire_3_11_4_12_remainter , wire_4_12_5_13_remainter , wire_4_11_12_curry , wire_4_12_13_curry );
div_cell cas_4_11 ( ~wire_out_quotient[13] , two_sc_divisor[11] , wire_3_10_4_11_remainter , wire_4_11_5_12_remainter , wire_4_10_11_curry , wire_4_11_12_curry );
div_cell cas_4_10 ( ~wire_out_quotient[13] , two_sc_divisor[10] , wire_3_9_4_10_remainter , wire_4_10_5_11_remainter , wire_4_09_10_curry , wire_4_10_11_curry );
div_cell cas_4_9 ( ~wire_out_quotient[13] , two_sc_divisor[9] , wire_3_8_4_9_remainter , wire_4_9_5_10_remainter , wire_4_08_09_curry , wire_4_09_10_curry );
div_cell cas_4_8 ( ~wire_out_quotient[13] , two_sc_divisor[8] , wire_3_7_4_8_remainter , wire_4_8_5_9_remainter , wire_4_07_08_curry , wire_4_08_09_curry );
div_cell cas_4_7 ( ~wire_out_quotient[13] , two_sc_divisor[7] , wire_3_6_4_7_remainter , wire_4_7_5_8_remainter , wire_4_06_07_curry , wire_4_07_08_curry );
div_cell cas_4_6 ( ~wire_out_quotient[13] , two_sc_divisor[6] , wire_3_5_4_6_remainter , wire_4_6_5_7_remainter , wire_4_05_06_curry , wire_4_06_07_curry );
div_cell cas_4_5 ( ~wire_out_quotient[13] , two_sc_divisor[5] , wire_3_4_4_5_remainter , wire_4_5_5_6_remainter , wire_4_04_05_curry , wire_4_05_06_curry );
div_cell cas_4_4 ( ~wire_out_quotient[13] , two_sc_divisor[4] , wire_3_3_4_4_remainter , wire_4_4_5_5_remainter , wire_4_03_04_curry , wire_4_04_05_curry );
div_cell cas_4_3 ( ~wire_out_quotient[13] , two_sc_divisor[3] , wire_3_2_4_3_remainter , wire_4_3_5_4_remainter , wire_4_02_03_curry , wire_4_03_04_curry );
div_cell cas_4_2 ( ~wire_out_quotient[13] , two_sc_divisor[2] , wire_3_1_4_2_remainter , wire_4_2_5_3_remainter , wire_4_01_02_curry , wire_4_02_03_curry );
div_cell cas_4_1 ( ~wire_out_quotient[13] , two_sc_divisor[1] , wire_3_0_4_1_remainter , wire_4_1_5_2_remainter , wire_4_00_01_curry , wire_4_01_02_curry );
div_cell cas_4_0 ( ~wire_out_quotient[13] , two_sc_divisor[0] , two_sc_dividend[12] , wire_4_0_5_1_remainter , ~wire_out_quotient[13] , wire_4_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_4_5 <= 'b0;
reg_4_5_curry <= 'b0;
end else begin
reg_4_5[14] <= wire_4_14_5_15_remainter;
reg_4_5[13] <= wire_4_13_5_14_remainter;
reg_4_5[12] <= wire_4_12_5_13_remainter;
reg_4_5[11] <= wire_4_11_5_12_remainter;
reg_4_5[10] <= wire_4_10_5_11_remainter;
reg_4_5[9] <= wire_4_9_5_10_remainter;
reg_4_5[8] <= wire_4_8_5_9_remainter;
reg_4_5[7] <= wire_4_7_5_8_remainter;
reg_4_5[6] <= wire_4_6_5_7_remainter;
reg_4_5[5] <= wire_4_5_5_6_remainter;
reg_4_5[4] <= wire_4_4_5_5_remainter;
reg_4_5[3] <= wire_4_3_5_4_remainter;
reg_4_5[2] <= wire_4_2_5_3_remainter;
reg_4_5[1] <= wire_4_1_5_2_remainter;
reg_4_5[0] <= wire_4_0_5_1_remainter;
reg_4_5_curry <= wire_out_quotient[12];
end
end
div_cell cas_5_15 ( ~reg_4_5_curry , two_sc_divisor[15] ,reg_4_5[14] , wire_out_quotient[11] , wire_5_14_15_curry , hang_5_wire_15 );
div_cell cas_5_14 ( ~reg_4_5_curry , two_sc_divisor[14] ,reg_4_5[13] , wire_5_14_6_15_remainter , wire_5_13_14_curry , wire_5_14_15_curry );
div_cell cas_5_13 ( ~reg_4_5_curry , two_sc_divisor[13] ,reg_4_5[12] , wire_5_13_6_14_remainter , wire_5_12_13_curry , wire_5_13_14_curry );
div_cell cas_5_12 ( ~reg_4_5_curry , two_sc_divisor[12] ,reg_4_5[11] , wire_5_12_6_13_remainter , wire_5_11_12_curry , wire_5_12_13_curry );
div_cell cas_5_11 ( ~reg_4_5_curry , two_sc_divisor[11] ,reg_4_5[10] , wire_5_11_6_12_remainter , wire_5_10_11_curry , wire_5_11_12_curry );
div_cell cas_5_10 ( ~reg_4_5_curry , two_sc_divisor[10] ,reg_4_5[9] , wire_5_10_6_11_remainter , wire_5_09_10_curry , wire_5_10_11_curry );
div_cell cas_5_9 ( ~reg_4_5_curry , two_sc_divisor[9] , reg_4_5[8] , wire_5_9_6_10_remainter , wire_5_08_09_curry , wire_5_09_10_curry );
div_cell cas_5_8 ( ~reg_4_5_curry , two_sc_divisor[8] , reg_4_5[7] , wire_5_8_6_9_remainter , wire_5_07_08_curry , wire_5_08_09_curry );
div_cell cas_5_7 ( ~reg_4_5_curry , two_sc_divisor[7] , reg_4_5[6] , wire_5_7_6_8_remainter , wire_5_06_07_curry , wire_5_07_08_curry );
div_cell cas_5_6 ( ~reg_4_5_curry , two_sc_divisor[6] , reg_4_5[5] , wire_5_6_6_7_remainter , wire_5_05_06_curry , wire_5_06_07_curry );
div_cell cas_5_5 ( ~reg_4_5_curry , two_sc_divisor[5] , reg_4_5[4] , wire_5_5_6_6_remainter , wire_5_04_05_curry , wire_5_05_06_curry );
div_cell cas_5_4 ( ~reg_4_5_curry , two_sc_divisor[4] , reg_4_5[3] , wire_5_4_6_5_remainter , wire_5_03_04_curry , wire_5_04_05_curry );
div_cell cas_5_3 ( ~reg_4_5_curry , two_sc_divisor[3] , reg_4_5[2] , wire_5_3_6_4_remainter , wire_5_02_03_curry , wire_5_03_04_curry );
div_cell cas_5_2 ( ~reg_4_5_curry , two_sc_divisor[2] , reg_4_5[1] , wire_5_2_6_3_remainter , wire_5_01_02_curry , wire_5_02_03_curry );
div_cell cas_5_1 ( ~reg_4_5_curry , two_sc_divisor[1] , reg_4_5[0] , wire_5_1_6_2_remainter , wire_5_00_01_curry , wire_5_01_02_curry );
div_cell cas_5_0 ( ~reg_4_5_curry , two_sc_divisor[0] , two_sc_dividend[11] , wire_5_0_6_1_remainter , ~reg_4_5_curry , wire_5_00_01_curry );
div_cell cas_6_15 ( ~wire_out_quotient[11] , two_sc_divisor[15] , wire_5_14_6_15_remainter , wire_out_quotient[10] , wire_6_14_15_curry , hang_6_wire_15 );
div_cell cas_6_14 ( ~wire_out_quotient[11] , two_sc_divisor[14] , wire_5_13_6_14_remainter , wire_6_14_7_15_remainter , wire_6_13_14_curry , wire_6_14_15_curry );
div_cell cas_6_13 ( ~wire_out_quotient[11] , two_sc_divisor[13] , wire_5_12_6_13_remainter , wire_6_13_7_14_remainter , wire_6_12_13_curry , wire_6_13_14_curry );
div_cell cas_6_12 ( ~wire_out_quotient[11] , two_sc_divisor[12] , wire_5_11_6_12_remainter , wire_6_12_7_13_remainter , wire_6_11_12_curry , wire_6_12_13_curry );
div_cell cas_6_11 ( ~wire_out_quotient[11] , two_sc_divisor[11] , wire_5_10_6_11_remainter , wire_6_11_7_12_remainter , wire_6_10_11_curry , wire_6_11_12_curry );
div_cell cas_6_10 ( ~wire_out_quotient[11] , two_sc_divisor[10] , wire_5_9_6_10_remainter , wire_6_10_7_11_remainter , wire_6_09_10_curry , wire_6_10_11_curry );
div_cell cas_6_9 ( ~wire_out_quotient[11] , two_sc_divisor[9] , wire_5_8_6_9_remainter , wire_6_9_7_10_remainter , wire_6_08_09_curry , wire_6_09_10_curry );
div_cell cas_6_8 ( ~wire_out_quotient[11] , two_sc_divisor[8] , wire_5_7_6_8_remainter , wire_6_8_7_9_remainter , wire_6_07_08_curry , wire_6_08_09_curry );
div_cell cas_6_7 ( ~wire_out_quotient[11] , two_sc_divisor[7] , wire_5_6_6_7_remainter , wire_6_7_7_8_remainter , wire_6_06_07_curry , wire_6_07_08_curry );
div_cell cas_6_6 ( ~wire_out_quotient[11] , two_sc_divisor[6] , wire_5_5_6_6_remainter , wire_6_6_7_7_remainter , wire_6_05_06_curry , wire_6_06_07_curry );
div_cell cas_6_5 ( ~wire_out_quotient[11] , two_sc_divisor[5] , wire_5_4_6_5_remainter , wire_6_5_7_6_remainter , wire_6_04_05_curry , wire_6_05_06_curry );
div_cell cas_6_4 ( ~wire_out_quotient[11] , two_sc_divisor[4] , wire_5_3_6_4_remainter , wire_6_4_7_5_remainter , wire_6_03_04_curry , wire_6_04_05_curry );
div_cell cas_6_3 ( ~wire_out_quotient[11] , two_sc_divisor[3] , wire_5_2_6_3_remainter , wire_6_3_7_4_remainter , wire_6_02_03_curry , wire_6_03_04_curry );
div_cell cas_6_2 ( ~wire_out_quotient[11] , two_sc_divisor[2] , wire_5_1_6_2_remainter , wire_6_2_7_3_remainter , wire_6_01_02_curry , wire_6_02_03_curry );
div_cell cas_6_1 ( ~wire_out_quotient[11] , two_sc_divisor[1] , wire_5_0_6_1_remainter , wire_6_1_7_2_remainter , wire_6_00_01_curry , wire_6_01_02_curry );
div_cell cas_6_0 ( ~wire_out_quotient[11] , two_sc_divisor[0] , two_sc_dividend[10] , wire_6_0_7_1_remainter , ~wire_out_quotient[11] , wire_6_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_6_7 <= 'b0;
reg_6_7_curry <= 'b0;
end else begin
reg_6_7[14] <= wire_6_14_7_15_remainter;
reg_6_7[13] <= wire_6_13_7_14_remainter;
reg_6_7[12] <= wire_6_12_7_13_remainter;
reg_6_7[11] <= wire_6_11_7_12_remainter;
reg_6_7[10] <= wire_6_10_7_11_remainter;
reg_6_7[9] <= wire_6_9_7_10_remainter;
reg_6_7[8] <= wire_6_8_7_9_remainter;
reg_6_7[7] <= wire_6_7_7_8_remainter;
reg_6_7[6] <= wire_6_6_7_7_remainter;
reg_6_7[5] <= wire_6_5_7_6_remainter;
reg_6_7[4] <= wire_6_4_7_5_remainter;
reg_6_7[3] <= wire_6_3_7_4_remainter;
reg_6_7[2] <= wire_6_2_7_3_remainter;
reg_6_7[1] <= wire_6_1_7_2_remainter;
reg_6_7[0] <= wire_6_0_7_1_remainter;
reg_6_7_curry <= wire_out_quotient[10];
end
end
div_cell cas_7_15 ( ~reg_6_7_curry , two_sc_divisor[15] , reg_6_7[14] , wire_out_quotient[9] , wire_7_14_15_curry , hang_7_wire_15 );
div_cell cas_7_14 ( ~reg_6_7_curry , two_sc_divisor[14] , reg_6_7[13] , wire_7_14_8_15_remainter , wire_7_13_14_curry , wire_7_14_15_curry );
div_cell cas_7_13 ( ~reg_6_7_curry , two_sc_divisor[13] , reg_6_7[12] , wire_7_13_8_14_remainter , wire_7_12_13_curry , wire_7_13_14_curry );
div_cell cas_7_12 ( ~reg_6_7_curry , two_sc_divisor[12] , reg_6_7[11] , wire_7_12_8_13_remainter , wire_7_11_12_curry , wire_7_12_13_curry );
div_cell cas_7_11 ( ~reg_6_7_curry , two_sc_divisor[11] , reg_6_7[10] , wire_7_11_8_12_remainter , wire_7_10_11_curry , wire_7_11_12_curry );
div_cell cas_7_10 ( ~reg_6_7_curry , two_sc_divisor[10] , reg_6_7[9] , wire_7_10_8_11_remainter , wire_7_09_10_curry , wire_7_10_11_curry );
div_cell cas_7_9 ( ~reg_6_7_curry , two_sc_divisor[9] , reg_6_7[8] , wire_7_9_8_10_remainter , wire_7_08_09_curry , wire_7_09_10_curry );
div_cell cas_7_8 ( ~reg_6_7_curry , two_sc_divisor[8] , reg_6_7[7] , wire_7_8_8_9_remainter , wire_7_07_08_curry , wire_7_08_09_curry );
div_cell cas_7_7 ( ~reg_6_7_curry , two_sc_divisor[7] , reg_6_7[6] , wire_7_7_8_8_remainter , wire_7_06_07_curry , wire_7_07_08_curry );
div_cell cas_7_6 ( ~reg_6_7_curry , two_sc_divisor[6] , reg_6_7[5] , wire_7_6_8_7_remainter , wire_7_05_06_curry , wire_7_06_07_curry );
div_cell cas_7_5 ( ~reg_6_7_curry , two_sc_divisor[5] , reg_6_7[4] , wire_7_5_8_6_remainter , wire_7_04_05_curry , wire_7_05_06_curry );
div_cell cas_7_4 ( ~reg_6_7_curry , two_sc_divisor[4] , reg_6_7[3] , wire_7_4_8_5_remainter , wire_7_03_04_curry , wire_7_04_05_curry );
div_cell cas_7_3 ( ~reg_6_7_curry , two_sc_divisor[3] , reg_6_7[2] , wire_7_3_8_4_remainter , wire_7_02_03_curry , wire_7_03_04_curry );
div_cell cas_7_2 ( ~reg_6_7_curry , two_sc_divisor[2] , reg_6_7[1] , wire_7_2_8_3_remainter , wire_7_01_02_curry , wire_7_02_03_curry );
div_cell cas_7_1 ( ~reg_6_7_curry , two_sc_divisor[1] , reg_6_7[0] , wire_7_1_8_2_remainter , wire_7_00_01_curry , wire_7_01_02_curry );
div_cell cas_7_0 ( ~reg_6_7_curry , two_sc_divisor[0] , two_sc_dividend[9] , wire_7_0_8_1_remainter , ~reg_6_7_curry , wire_7_00_01_curry );
div_cell cas_8_15 ( ~wire_out_quotient[9] , two_sc_divisor[15] , wire_7_14_8_15_remainter , wire_out_quotient[8] , wire_8_14_15_curry , hang_8_wire_15 );
div_cell cas_8_14 ( ~wire_out_quotient[9] , two_sc_divisor[14] , wire_7_13_8_14_remainter , wire_8_14_9_15_remainter , wire_8_13_14_curry , wire_8_14_15_curry );
div_cell cas_8_13 ( ~wire_out_quotient[9] , two_sc_divisor[13] , wire_7_12_8_13_remainter , wire_8_13_9_14_remainter , wire_8_12_13_curry , wire_8_13_14_curry );
div_cell cas_8_12 ( ~wire_out_quotient[9] , two_sc_divisor[12] , wire_7_11_8_12_remainter , wire_8_12_9_13_remainter , wire_8_11_12_curry , wire_8_12_13_curry );
div_cell cas_8_11 ( ~wire_out_quotient[9] , two_sc_divisor[11] , wire_7_10_8_11_remainter , wire_8_11_9_12_remainter , wire_8_10_11_curry , wire_8_11_12_curry );
div_cell cas_8_10 ( ~wire_out_quotient[9] , two_sc_divisor[10] , wire_7_9_8_10_remainter , wire_8_10_9_11_remainter , wire_8_09_10_curry , wire_8_10_11_curry );
div_cell cas_8_9 ( ~wire_out_quotient[9] , two_sc_divisor[9] , wire_7_8_8_9_remainter , wire_8_9_9_10_remainter , wire_8_08_09_curry , wire_8_09_10_curry );
div_cell cas_8_8 ( ~wire_out_quotient[9] , two_sc_divisor[8] , wire_7_7_8_8_remainter , wire_8_8_9_9_remainter , wire_8_07_08_curry , wire_8_08_09_curry );
div_cell cas_8_7 ( ~wire_out_quotient[9] , two_sc_divisor[7] , wire_7_6_8_7_remainter , wire_8_7_9_8_remainter , wire_8_06_07_curry , wire_8_07_08_curry );
div_cell cas_8_6 ( ~wire_out_quotient[9] , two_sc_divisor[6] , wire_7_5_8_6_remainter , wire_8_6_9_7_remainter , wire_8_05_06_curry , wire_8_06_07_curry );
div_cell cas_8_5 ( ~wire_out_quotient[9] , two_sc_divisor[5] , wire_7_4_8_5_remainter , wire_8_5_9_6_remainter , wire_8_04_05_curry , wire_8_05_06_curry );
div_cell cas_8_4 ( ~wire_out_quotient[9] , two_sc_divisor[4] , wire_7_3_8_4_remainter , wire_8_4_9_5_remainter , wire_8_03_04_curry , wire_8_04_05_curry );
div_cell cas_8_3 ( ~wire_out_quotient[9] , two_sc_divisor[3] , wire_7_2_8_3_remainter , wire_8_3_9_4_remainter , wire_8_02_03_curry , wire_8_03_04_curry );
div_cell cas_8_2 ( ~wire_out_quotient[9] , two_sc_divisor[2] , wire_7_1_8_2_remainter , wire_8_2_9_3_remainter , wire_8_01_02_curry , wire_8_02_03_curry );
div_cell cas_8_1 ( ~wire_out_quotient[9] , two_sc_divisor[1] , wire_7_0_8_1_remainter , wire_8_1_9_2_remainter , wire_8_00_01_curry , wire_8_01_02_curry );
div_cell cas_8_0 ( ~wire_out_quotient[9] , two_sc_divisor[0] , two_sc_dividend[8] , wire_8_0_9_1_remainter , ~wire_out_quotient[9] , wire_8_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_8_9 <= 'b0;
reg_8_9_curry <= 'b0;
end else begin
reg_8_9[14] <= wire_8_14_9_15_remainter;
reg_8_9[13] <= wire_8_13_9_14_remainter;
reg_8_9[12] <= wire_8_12_9_13_remainter;
reg_8_9[11] <= wire_8_11_9_12_remainter;
reg_8_9[10] <= wire_8_10_9_11_remainter;
reg_8_9[9] <= wire_8_9_9_10_remainter;
reg_8_9[8] <= wire_8_8_9_9_remainter;
reg_8_9[7] <= wire_8_7_9_8_remainter;
reg_8_9[6] <= wire_8_6_9_7_remainter;
reg_8_9[5] <= wire_8_5_9_6_remainter;
reg_8_9[4] <= wire_8_4_9_5_remainter;
reg_8_9[3] <= wire_8_3_9_4_remainter;
reg_8_9[2] <= wire_8_2_9_3_remainter;
reg_8_9[1] <= wire_8_1_9_2_remainter;
reg_8_9[0] <= wire_8_0_9_1_remainter;
reg_8_9_curry <= wire_out_quotient[8];
end
end
div_cell cas_9_15 ( ~reg_8_9_curry , two_sc_divisor[15] , reg_8_9[14] , wire_out_quotient[7] , wire_9_14_15_curry , hang_9_wire_15 );
div_cell cas_9_14 ( ~reg_8_9_curry , two_sc_divisor[14] , reg_8_9[13] , wire_9_14_10_15_remainter , wire_9_13_14_curry , wire_9_14_15_curry );
div_cell cas_9_13 ( ~reg_8_9_curry , two_sc_divisor[13] , reg_8_9[12] , wire_9_13_10_14_remainter , wire_9_12_13_curry , wire_9_13_14_curry );
div_cell cas_9_12 ( ~reg_8_9_curry , two_sc_divisor[12] , reg_8_9[11] , wire_9_12_10_13_remainter , wire_9_11_12_curry , wire_9_12_13_curry );
div_cell cas_9_11 ( ~reg_8_9_curry , two_sc_divisor[11] , reg_8_9[10] , wire_9_11_10_12_remainter , wire_9_10_11_curry , wire_9_11_12_curry );
div_cell cas_9_10 ( ~reg_8_9_curry , two_sc_divisor[10] , reg_8_9[9] , wire_9_10_10_11_remainter , wire_9_09_10_curry , wire_9_10_11_curry );
div_cell cas_9_9 ( ~reg_8_9_curry , two_sc_divisor[9] , reg_8_9[8] , wire_9_9_10_10_remainter , wire_9_08_09_curry , wire_9_09_10_curry );
div_cell cas_9_8 ( ~reg_8_9_curry , two_sc_divisor[8] , reg_8_9[7] , wire_9_8_10_9_remainter , wire_9_07_08_curry , wire_9_08_09_curry );
div_cell cas_9_7 ( ~reg_8_9_curry , two_sc_divisor[7] , reg_8_9[6] , wire_9_7_10_8_remainter , wire_9_06_07_curry , wire_9_07_08_curry );
div_cell cas_9_6 ( ~reg_8_9_curry , two_sc_divisor[6] , reg_8_9[5] , wire_9_6_10_7_remainter , wire_9_05_06_curry , wire_9_06_07_curry );
div_cell cas_9_5 ( ~reg_8_9_curry , two_sc_divisor[5] , reg_8_9[4] , wire_9_5_10_6_remainter , wire_9_04_05_curry , wire_9_05_06_curry );
div_cell cas_9_4 ( ~reg_8_9_curry , two_sc_divisor[4] , reg_8_9[3] , wire_9_4_10_5_remainter , wire_9_03_04_curry , wire_9_04_05_curry );
div_cell cas_9_3 ( ~reg_8_9_curry , two_sc_divisor[3] , reg_8_9[2] , wire_9_3_10_4_remainter , wire_9_02_03_curry , wire_9_03_04_curry );
div_cell cas_9_2 ( ~reg_8_9_curry , two_sc_divisor[2] , reg_8_9[1] , wire_9_2_10_3_remainter , wire_9_01_02_curry , wire_9_02_03_curry );
div_cell cas_9_1 ( ~reg_8_9_curry , two_sc_divisor[1] , reg_8_9[0] , wire_9_1_10_2_remainter , wire_9_00_01_curry , wire_9_01_02_curry );
div_cell cas_9_0 ( ~reg_8_9_curry , two_sc_divisor[0] , two_sc_dividend[7] , wire_9_0_10_1_remainter , ~reg_8_9_curry , wire_9_00_01_curry );
div_cell cas_10_15 ( ~wire_out_quotient[7] , two_sc_divisor[15] , wire_9_14_10_15_remainter , wire_out_quotient[6] , wire_10_14_15_curry , hang_10_wire_15 );
div_cell cas_10_14 ( ~wire_out_quotient[7] , two_sc_divisor[14] , wire_9_13_10_14_remainter , wire_10_14_11_15_remainter , wire_10_13_14_curry , wire_10_14_15_curry );
div_cell cas_10_13 ( ~wire_out_quotient[7] , two_sc_divisor[13] , wire_9_12_10_13_remainter , wire_10_13_11_14_remainter , wire_10_12_13_curry , wire_10_13_14_curry );
div_cell cas_10_12 ( ~wire_out_quotient[7] , two_sc_divisor[12] , wire_9_11_10_12_remainter , wire_10_12_11_13_remainter , wire_10_11_12_curry , wire_10_12_13_curry );
div_cell cas_10_11 ( ~wire_out_quotient[7] , two_sc_divisor[11] , wire_9_10_10_11_remainter , wire_10_11_11_12_remainter , wire_10_10_11_curry , wire_10_11_12_curry );
div_cell cas_10_10 ( ~wire_out_quotient[7] , two_sc_divisor[10] , wire_9_9_10_10_remainter , wire_10_10_11_11_remainter , wire_10_09_10_curry , wire_10_10_11_curry );
div_cell cas_10_9 ( ~wire_out_quotient[7] , two_sc_divisor[9] , wire_9_8_10_9_remainter , wire_10_9_11_10_remainter , wire_10_08_09_curry , wire_10_09_10_curry );
div_cell cas_10_8 ( ~wire_out_quotient[7] , two_sc_divisor[8] , wire_9_7_10_8_remainter , wire_10_8_11_9_remainter , wire_10_07_08_curry , wire_10_08_09_curry );
div_cell cas_10_7 ( ~wire_out_quotient[7] , two_sc_divisor[7] , wire_9_6_10_7_remainter , wire_10_7_11_8_remainter , wire_10_06_07_curry , wire_10_07_08_curry );
div_cell cas_10_6 ( ~wire_out_quotient[7] , two_sc_divisor[6] , wire_9_5_10_6_remainter , wire_10_6_11_7_remainter , wire_10_05_06_curry , wire_10_06_07_curry );
div_cell cas_10_5 ( ~wire_out_quotient[7] , two_sc_divisor[5] , wire_9_4_10_5_remainter , wire_10_5_11_6_remainter , wire_10_04_05_curry , wire_10_05_06_curry );
div_cell cas_10_4 ( ~wire_out_quotient[7] , two_sc_divisor[4] , wire_9_3_10_4_remainter , wire_10_4_11_5_remainter , wire_10_03_04_curry , wire_10_04_05_curry );
div_cell cas_10_3 ( ~wire_out_quotient[7] , two_sc_divisor[3] , wire_9_2_10_3_remainter , wire_10_3_11_4_remainter , wire_10_02_03_curry , wire_10_03_04_curry );
div_cell cas_10_2 ( ~wire_out_quotient[7] , two_sc_divisor[2] , wire_9_1_10_2_remainter , wire_10_2_11_3_remainter , wire_10_01_02_curry , wire_10_02_03_curry );
div_cell cas_10_1 ( ~wire_out_quotient[7] , two_sc_divisor[1] , wire_9_0_10_1_remainter , wire_10_1_11_2_remainter , wire_10_00_01_curry , wire_10_01_02_curry );
div_cell cas_10_0 ( ~wire_out_quotient[7] , two_sc_divisor[0] , two_sc_dividend[6] , wire_10_0_11_1_remainter , ~wire_out_quotient[7] , wire_10_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_10_11 <= 'b0;
reg_10_11_curry <= 'b0;
end else begin
reg_10_11[14] <= wire_10_14_11_15_remainter;
reg_10_11[13] <= wire_10_13_11_14_remainter;
reg_10_11[12] <= wire_10_12_11_13_remainter;
reg_10_11[11] <= wire_10_11_11_12_remainter;
reg_10_11[10] <= wire_10_10_11_11_remainter;
reg_10_11[9] <= wire_10_9_11_10_remainter;
reg_10_11[8] <= wire_10_8_11_9_remainter;
reg_10_11[7] <= wire_10_7_11_8_remainter;
reg_10_11[6] <= wire_10_6_11_7_remainter;
reg_10_11[5] <= wire_10_5_11_6_remainter;
reg_10_11[4] <= wire_10_4_11_5_remainter;
reg_10_11[3] <= wire_10_3_11_4_remainter;
reg_10_11[2] <= wire_10_2_11_3_remainter;
reg_10_11[1] <= wire_10_1_11_2_remainter;
reg_10_11[0] <= wire_10_0_11_1_remainter;
reg_10_11_curry <= wire_out_quotient[6];
end
end
div_cell cas_11_15 ( ~reg_10_11_curry , two_sc_divisor[15] , reg_10_11[14] , wire_out_quotient[5] , wire_11_14_15_curry , hang_11_wire_15 );
div_cell cas_11_14 ( ~reg_10_11_curry , two_sc_divisor[14] , reg_10_11[13] , wire_11_14_12_15_remainter , wire_11_13_14_curry , wire_11_14_15_curry );
div_cell cas_11_13 ( ~reg_10_11_curry , two_sc_divisor[13] , reg_10_11[12] , wire_11_13_12_14_remainter , wire_11_12_13_curry , wire_11_13_14_curry );
div_cell cas_11_12 ( ~reg_10_11_curry , two_sc_divisor[12] , reg_10_11[11] , wire_11_12_12_13_remainter , wire_11_11_12_curry , wire_11_12_13_curry );
div_cell cas_11_11 ( ~reg_10_11_curry , two_sc_divisor[11] , reg_10_11[10] , wire_11_11_12_12_remainter , wire_11_10_11_curry , wire_11_11_12_curry );
div_cell cas_11_10 ( ~reg_10_11_curry , two_sc_divisor[10] , reg_10_11[9], wire_11_10_12_11_remainter , wire_11_09_10_curry , wire_11_10_11_curry );
div_cell cas_11_9 ( ~reg_10_11_curry , two_sc_divisor[9] , reg_10_11[8] , wire_11_9_12_10_remainter , wire_11_08_09_curry , wire_11_09_10_curry );
div_cell cas_11_8 ( ~reg_10_11_curry , two_sc_divisor[8] , reg_10_11[7] , wire_11_8_12_9_remainter , wire_11_07_08_curry , wire_11_08_09_curry );
div_cell cas_11_7 ( ~reg_10_11_curry , two_sc_divisor[7] , reg_10_11[6] , wire_11_7_12_8_remainter , wire_11_06_07_curry , wire_11_07_08_curry );
div_cell cas_11_6 ( ~reg_10_11_curry , two_sc_divisor[6] , reg_10_11[5] , wire_11_6_12_7_remainter , wire_11_05_06_curry , wire_11_06_07_curry );
div_cell cas_11_5 ( ~reg_10_11_curry , two_sc_divisor[5] , reg_10_11[4] , wire_11_5_12_6_remainter , wire_11_04_05_curry , wire_11_05_06_curry );
div_cell cas_11_4 ( ~reg_10_11_curry , two_sc_divisor[4] , reg_10_11[3] , wire_11_4_12_5_remainter , wire_11_03_04_curry , wire_11_04_05_curry );
div_cell cas_11_3 ( ~reg_10_11_curry , two_sc_divisor[3] , reg_10_11[2] , wire_11_3_12_4_remainter , wire_11_02_03_curry , wire_11_03_04_curry );
div_cell cas_11_2 ( ~reg_10_11_curry , two_sc_divisor[2] , reg_10_11[1] , wire_11_2_12_3_remainter , wire_11_01_02_curry , wire_11_02_03_curry );
div_cell cas_11_1 ( ~reg_10_11_curry , two_sc_divisor[1] , reg_10_11[0] , wire_11_1_12_2_remainter , wire_11_00_01_curry , wire_11_01_02_curry );
div_cell cas_11_0 ( ~reg_10_11_curry , two_sc_divisor[0] , two_sc_dividend[5] , wire_11_0_12_1_remainter , ~reg_10_11_curry , wire_11_00_01_curry );
div_cell cas_12_15 ( ~wire_out_quotient[5] , two_sc_divisor[15] , wire_11_14_12_15_remainter , wire_out_quotient[4] , wire_12_14_15_curry , hang_12_wire_15 );
div_cell cas_12_14 ( ~wire_out_quotient[5] , two_sc_divisor[14] , wire_11_13_12_14_remainter , wire_12_14_13_15_remainter , wire_12_13_14_curry , wire_12_14_15_curry );
div_cell cas_12_13 ( ~wire_out_quotient[5] , two_sc_divisor[13] , wire_11_12_12_13_remainter , wire_12_13_13_14_remainter , wire_12_12_13_curry , wire_12_13_14_curry );
div_cell cas_12_12 ( ~wire_out_quotient[5] , two_sc_divisor[12] , wire_11_11_12_12_remainter , wire_12_12_13_13_remainter , wire_12_11_12_curry , wire_12_12_13_curry );
div_cell cas_12_11 ( ~wire_out_quotient[5] , two_sc_divisor[11] , wire_11_10_12_11_remainter , wire_12_11_13_12_remainter , wire_12_10_11_curry , wire_12_11_12_curry );
div_cell cas_12_10 ( ~wire_out_quotient[5] , two_sc_divisor[10] , wire_11_9_12_10_remainter , wire_12_10_13_11_remainter , wire_12_09_10_curry , wire_12_10_11_curry );
div_cell cas_12_9 ( ~wire_out_quotient[5] , two_sc_divisor[9] , wire_11_8_12_9_remainter , wire_12_9_13_10_remainter , wire_12_08_09_curry , wire_12_09_10_curry );
div_cell cas_12_8 ( ~wire_out_quotient[5] , two_sc_divisor[8] , wire_11_7_12_8_remainter , wire_12_8_13_9_remainter , wire_12_07_08_curry , wire_12_08_09_curry );
div_cell cas_12_7 ( ~wire_out_quotient[5] , two_sc_divisor[7] , wire_11_6_12_7_remainter , wire_12_7_13_8_remainter , wire_12_06_07_curry , wire_12_07_08_curry );
div_cell cas_12_6 ( ~wire_out_quotient[5] , two_sc_divisor[6] , wire_11_5_12_6_remainter , wire_12_6_13_7_remainter , wire_12_05_06_curry , wire_12_06_07_curry );
div_cell cas_12_5 ( ~wire_out_quotient[5] , two_sc_divisor[5] , wire_11_4_12_5_remainter , wire_12_5_13_6_remainter , wire_12_04_05_curry , wire_12_05_06_curry );
div_cell cas_12_4 ( ~wire_out_quotient[5] , two_sc_divisor[4] , wire_11_3_12_4_remainter , wire_12_4_13_5_remainter , wire_12_03_04_curry , wire_12_04_05_curry );
div_cell cas_12_3 ( ~wire_out_quotient[5] , two_sc_divisor[3] , wire_11_2_12_3_remainter , wire_12_3_13_4_remainter , wire_12_02_03_curry , wire_12_03_04_curry );
div_cell cas_12_2 ( ~wire_out_quotient[5] , two_sc_divisor[2] , wire_11_1_12_2_remainter , wire_12_2_13_3_remainter , wire_12_01_02_curry , wire_12_02_03_curry );
div_cell cas_12_1 ( ~wire_out_quotient[5] , two_sc_divisor[1] , wire_11_0_12_1_remainter , wire_12_1_13_2_remainter , wire_12_00_01_curry , wire_12_01_02_curry );
div_cell cas_12_0 ( ~wire_out_quotient[5] , two_sc_divisor[0] , two_sc_dividend[4] , wire_12_0_13_1_remainter , ~wire_out_quotient[5] , wire_12_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_12_13 <= 'b0;
reg_12_13_curry <= 'b0;
end else begin
reg_12_13[14] <= wire_12_14_13_15_remainter;
reg_12_13[13] <= wire_12_13_13_14_remainter;
reg_12_13[12] <= wire_12_12_13_13_remainter;
reg_12_13[11] <= wire_12_11_13_12_remainter;
reg_12_13[10] <= wire_12_10_13_11_remainter;
reg_12_13[9] <= wire_12_9_13_10_remainter;
reg_12_13[8] <= wire_12_8_13_9_remainter;
reg_12_13[7] <= wire_12_7_13_8_remainter;
reg_12_13[6] <= wire_12_6_13_7_remainter;
reg_12_13[5] <= wire_12_5_13_6_remainter;
reg_12_13[4] <= wire_12_4_13_5_remainter;
reg_12_13[3] <= wire_12_3_13_4_remainter;
reg_12_13[2] <= wire_12_2_13_3_remainter;
reg_12_13[1] <= wire_12_1_13_2_remainter;
reg_12_13[0] <= wire_12_0_13_1_remainter;
reg_12_13_curry <= wire_out_quotient[4];
end
end
div_cell cas_13_15 ( ~reg_12_13_curry , two_sc_divisor[15] , reg_12_13[14] , wire_out_quotient[3] , wire_13_14_15_curry , hang_13_wire_15 );
div_cell cas_13_14 ( ~reg_12_13_curry , two_sc_divisor[14] ,reg_12_13[13] , wire_13_14_14_15_remainter , wire_13_13_14_curry , wire_13_14_15_curry );
div_cell cas_13_13 ( ~reg_12_13_curry , two_sc_divisor[13] ,reg_12_13[12] , wire_13_13_14_14_remainter , wire_13_12_13_curry , wire_13_13_14_curry );
div_cell cas_13_12 ( ~reg_12_13_curry , two_sc_divisor[12] ,reg_12_13[11] , wire_13_12_14_13_remainter , wire_13_11_12_curry , wire_13_12_13_curry );
div_cell cas_13_11 ( ~reg_12_13_curry , two_sc_divisor[11] ,reg_12_13[10] , wire_13_11_14_12_remainter , wire_13_10_11_curry , wire_13_11_12_curry );
div_cell cas_13_10 ( ~reg_12_13_curry , two_sc_divisor[10] ,reg_12_13[9], wire_13_10_14_11_remainter , wire_13_09_10_curry , wire_13_10_11_curry );
div_cell cas_13_9 ( ~reg_12_13_curry , two_sc_divisor[9] , reg_12_13[8] , wire_13_9_14_10_remainter , wire_13_08_09_curry , wire_13_09_10_curry );
div_cell cas_13_8 ( ~reg_12_13_curry , two_sc_divisor[8] , reg_12_13[7] , wire_13_8_14_9_remainter , wire_13_07_08_curry , wire_13_08_09_curry );
div_cell cas_13_7 ( ~reg_12_13_curry , two_sc_divisor[7] , reg_12_13[6] , wire_13_7_14_8_remainter , wire_13_06_07_curry , wire_13_07_08_curry );
div_cell cas_13_6 ( ~reg_12_13_curry , two_sc_divisor[6] , reg_12_13[5] , wire_13_6_14_7_remainter , wire_13_05_06_curry , wire_13_06_07_curry );
div_cell cas_13_5 ( ~reg_12_13_curry , two_sc_divisor[5] , reg_12_13[4] , wire_13_5_14_6_remainter , wire_13_04_05_curry , wire_13_05_06_curry );
div_cell cas_13_4 ( ~reg_12_13_curry , two_sc_divisor[4] , reg_12_13[3] , wire_13_4_14_5_remainter , wire_13_03_04_curry , wire_13_04_05_curry );
div_cell cas_13_3 ( ~reg_12_13_curry , two_sc_divisor[3] , reg_12_13[2] , wire_13_3_14_4_remainter , wire_13_02_03_curry , wire_13_03_04_curry );
div_cell cas_13_2 ( ~reg_12_13_curry , two_sc_divisor[2] , reg_12_13[1] , wire_13_2_14_3_remainter , wire_13_01_02_curry , wire_13_02_03_curry );
div_cell cas_13_1 ( ~reg_12_13_curry , two_sc_divisor[1] , reg_12_13[0] , wire_13_1_14_2_remainter , wire_13_00_01_curry , wire_13_01_02_curry );
div_cell cas_13_0 ( ~reg_12_13_curry , two_sc_divisor[0] , two_sc_dividend[3] , wire_13_0_14_1_remainter , ~reg_12_13_curry , wire_13_00_01_curry );
div_cell cas_14_15 ( ~wire_out_quotient[3] , two_sc_divisor[15] , wire_13_14_14_15_remainter , wire_out_quotient[2] , wire_14_14_15_curry , hang_14_wire_15 );
div_cell cas_14_14 ( ~wire_out_quotient[3] , two_sc_divisor[14] , wire_13_13_14_14_remainter , wire_14_14_15_15_remainter , wire_14_13_14_curry , wire_14_14_15_curry );
div_cell cas_14_13 ( ~wire_out_quotient[3] , two_sc_divisor[13] , wire_13_12_14_13_remainter , wire_14_13_15_14_remainter , wire_14_12_13_curry , wire_14_13_14_curry );
div_cell cas_14_12 ( ~wire_out_quotient[3] , two_sc_divisor[12] , wire_13_11_14_12_remainter , wire_14_12_15_13_remainter , wire_14_11_12_curry , wire_14_12_13_curry );
div_cell cas_14_11 ( ~wire_out_quotient[3] , two_sc_divisor[11] , wire_13_10_14_11_remainter , wire_14_11_15_12_remainter , wire_14_10_11_curry , wire_14_11_12_curry );
div_cell cas_14_10 ( ~wire_out_quotient[3] , two_sc_divisor[10] , wire_13_9_14_10_remainter , wire_14_10_15_11_remainter , wire_14_09_10_curry , wire_14_10_11_curry );
div_cell cas_14_9 ( ~wire_out_quotient[3] , two_sc_divisor[9] , wire_13_8_14_9_remainter , wire_14_9_15_10_remainter , wire_14_08_09_curry , wire_14_09_10_curry );
div_cell cas_14_8 ( ~wire_out_quotient[3] , two_sc_divisor[8] , wire_13_7_14_8_remainter , wire_14_8_15_9_remainter , wire_14_07_08_curry , wire_14_08_09_curry );
div_cell cas_14_7 ( ~wire_out_quotient[3] , two_sc_divisor[7] , wire_13_6_14_7_remainter , wire_14_7_15_8_remainter , wire_14_06_07_curry , wire_14_07_08_curry );
div_cell cas_14_6 ( ~wire_out_quotient[3] , two_sc_divisor[6] , wire_13_5_14_6_remainter , wire_14_6_15_7_remainter , wire_14_05_06_curry , wire_14_06_07_curry );
div_cell cas_14_5 ( ~wire_out_quotient[3] , two_sc_divisor[5] , wire_13_4_14_5_remainter , wire_14_5_15_6_remainter , wire_14_04_05_curry , wire_14_05_06_curry );
div_cell cas_14_4 ( ~wire_out_quotient[3] , two_sc_divisor[4] , wire_13_3_14_4_remainter , wire_14_4_15_5_remainter , wire_14_03_04_curry , wire_14_04_05_curry );
div_cell cas_14_3 ( ~wire_out_quotient[3] , two_sc_divisor[3] , wire_13_2_14_3_remainter , wire_14_3_15_4_remainter , wire_14_02_03_curry , wire_14_03_04_curry );
div_cell cas_14_2 ( ~wire_out_quotient[3] , two_sc_divisor[2] , wire_13_1_14_2_remainter , wire_14_2_15_3_remainter , wire_14_01_02_curry , wire_14_02_03_curry );
div_cell cas_14_1 ( ~wire_out_quotient[3] , two_sc_divisor[1] , wire_13_0_14_1_remainter , wire_14_1_15_2_remainter , wire_14_00_01_curry , wire_14_01_02_curry );
div_cell cas_14_0 ( ~wire_out_quotient[3] , two_sc_divisor[0] , two_sc_dividend[2] , wire_14_0_15_1_remainter , ~wire_out_quotient[3] , wire_14_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_14_15 <= 'b0;
reg_14_15_curry <= 'b0;
end else begin
reg_14_15[14] <= wire_14_14_15_15_remainter;
reg_14_15[13] <= wire_14_13_15_14_remainter;
reg_14_15[12] <= wire_14_12_15_13_remainter;
reg_14_15[11] <= wire_14_11_15_12_remainter;
reg_14_15[10] <= wire_14_10_15_11_remainter;
reg_14_15[9] <= wire_14_9_15_10_remainter;
reg_14_15[8] <= wire_14_8_15_9_remainter;
reg_14_15[7] <= wire_14_7_15_8_remainter;
reg_14_15[6] <= wire_14_6_15_7_remainter;
reg_14_15[5] <= wire_14_5_15_6_remainter;
reg_14_15[4] <= wire_14_4_15_5_remainter;
reg_14_15[3] <= wire_14_3_15_4_remainter;
reg_14_15[2] <= wire_14_2_15_3_remainter;
reg_14_15[1] <= wire_14_1_15_2_remainter;
reg_14_15[0] <= wire_14_0_15_1_remainter;
reg_14_15_curry <= wire_out_quotient[2];
end
end
div_cell cas_15_15 ( ~reg_14_15_curry , two_sc_divisor[15] , reg_14_15[14] , wire_out_quotient[1] , wire_15_14_15_curry , hang_15_wire_15 );
div_cell cas_15_14 ( ~reg_14_15_curry , two_sc_divisor[14] , reg_14_15[13] , wire_15_14_16_15_remainter , wire_15_13_14_curry , wire_15_14_15_curry );
div_cell cas_15_13 ( ~reg_14_15_curry , two_sc_divisor[13] , reg_14_15[12] , wire_15_13_16_14_remainter , wire_15_12_13_curry , wire_15_13_14_curry );
div_cell cas_15_12 ( ~reg_14_15_curry , two_sc_divisor[12] , reg_14_15[11] , wire_15_12_16_13_remainter , wire_15_11_12_curry , wire_15_12_13_curry );
div_cell cas_15_11 ( ~reg_14_15_curry , two_sc_divisor[11] , reg_14_15[10] , wire_15_11_16_12_remainter , wire_15_10_11_curry , wire_15_11_12_curry );
div_cell cas_15_10 ( ~reg_14_15_curry , two_sc_divisor[10] , reg_14_15[9], wire_15_10_16_11_remainter , wire_15_09_10_curry , wire_15_10_11_curry );
div_cell cas_15_9 ( ~reg_14_15_curry , two_sc_divisor[9] , reg_14_15[8] , wire_15_9_16_10_remainter , wire_15_08_09_curry , wire_15_09_10_curry );
div_cell cas_15_8 ( ~reg_14_15_curry , two_sc_divisor[8] , reg_14_15[7] , wire_15_8_16_9_remainter , wire_15_07_08_curry , wire_15_08_09_curry );
div_cell cas_15_7 ( ~reg_14_15_curry , two_sc_divisor[7] , reg_14_15[6] , wire_15_7_16_8_remainter , wire_15_06_07_curry , wire_15_07_08_curry );
div_cell cas_15_6 ( ~reg_14_15_curry , two_sc_divisor[6] , reg_14_15[5] , wire_15_6_16_7_remainter , wire_15_05_06_curry , wire_15_06_07_curry );
div_cell cas_15_5 ( ~reg_14_15_curry , two_sc_divisor[5] , reg_14_15[4] , wire_15_5_16_6_remainter , wire_15_04_05_curry , wire_15_05_06_curry );
div_cell cas_15_4 ( ~reg_14_15_curry , two_sc_divisor[4] , reg_14_15[3] , wire_15_4_16_5_remainter , wire_15_03_04_curry , wire_15_04_05_curry );
div_cell cas_15_3 ( ~reg_14_15_curry , two_sc_divisor[3] , reg_14_15[2] , wire_15_3_16_4_remainter , wire_15_02_03_curry , wire_15_03_04_curry );
div_cell cas_15_2 ( ~reg_14_15_curry , two_sc_divisor[2] , reg_14_15[1] , wire_15_2_16_3_remainter , wire_15_01_02_curry , wire_15_02_03_curry );
div_cell cas_15_1 ( ~reg_14_15_curry , two_sc_divisor[1] , reg_14_15[0] , wire_15_1_16_2_remainter , wire_15_00_01_curry , wire_15_01_02_curry );
div_cell cas_15_0 ( ~reg_14_15_curry , two_sc_divisor[0] , two_sc_dividend[1] , wire_15_0_16_1_remainter , ~reg_14_15_curry , wire_15_00_01_curry );
div_cell cas_16_15 ( ~wire_out_quotient[1] , two_sc_divisor[15] , wire_15_14_16_15_remainter , wire_out_quotient[0] , wire_16_14_15_curry , hang_16_wire_15 );
div_cell cas_16_14 ( ~wire_out_quotient[1] , two_sc_divisor[14] , wire_15_13_16_14_remainter , wire_out_remainder[14] , wire_16_13_14_curry , wire_16_14_15_curry );
div_cell cas_16_13 ( ~wire_out_quotient[1] , two_sc_divisor[13] , wire_15_12_16_13_remainter , wire_out_remainder[13] , wire_16_12_13_curry , wire_16_13_14_curry );
div_cell cas_16_12 ( ~wire_out_quotient[1] , two_sc_divisor[12] , wire_15_11_16_12_remainter , wire_out_remainder[12] , wire_16_11_12_curry , wire_16_12_13_curry );
div_cell cas_16_11 ( ~wire_out_quotient[1] , two_sc_divisor[11] , wire_15_10_16_11_remainter , wire_out_remainder[11] , wire_16_10_11_curry , wire_16_11_12_curry );
div_cell cas_16_10 ( ~wire_out_quotient[1] , two_sc_divisor[10] , wire_15_9_16_10_remainter , wire_out_remainder[10] , wire_16_09_10_curry , wire_16_10_11_curry );
div_cell cas_16_9 ( ~wire_out_quotient[1] , two_sc_divisor[9] , wire_15_8_16_9_remainter , wire_out_remainder[9] , wire_16_08_09_curry , wire_16_09_10_curry );
div_cell cas_16_8 ( ~wire_out_quotient[1] , two_sc_divisor[8] , wire_15_7_16_8_remainter , wire_out_remainder[8] , wire_16_07_08_curry , wire_16_08_09_curry );
div_cell cas_16_7 ( ~wire_out_quotient[1] , two_sc_divisor[7] , wire_15_6_16_7_remainter , wire_out_remainder[7] , wire_16_06_07_curry , wire_16_07_08_curry );
div_cell cas_16_6 ( ~wire_out_quotient[1] , two_sc_divisor[6] , wire_15_5_16_6_remainter , wire_out_remainder[6] , wire_16_05_06_curry , wire_16_06_07_curry );
div_cell cas_16_5 ( ~wire_out_quotient[1] , two_sc_divisor[5] , wire_15_4_16_5_remainter , wire_out_remainder[5] , wire_16_04_05_curry , wire_16_05_06_curry );
div_cell cas_16_4 ( ~wire_out_quotient[1] , two_sc_divisor[4] , wire_15_3_16_4_remainter , wire_out_remainder[4] , wire_16_03_04_curry , wire_16_04_05_curry );
div_cell cas_16_3 ( ~wire_out_quotient[1] , two_sc_divisor[3] , wire_15_2_16_3_remainter , wire_out_remainder[3] , wire_16_02_03_curry , wire_16_03_04_curry );
div_cell cas_16_2 ( ~wire_out_quotient[1] , two_sc_divisor[2] , wire_15_1_16_2_remainter , wire_out_remainder[2] , wire_16_01_02_curry , wire_16_02_03_curry );
div_cell cas_16_1 ( ~wire_out_quotient[1] , two_sc_divisor[1] , wire_15_0_16_1_remainter , wire_out_remainder[1] , wire_16_00_01_curry , wire_16_01_02_curry );
div_cell cas_16_0 ( ~wire_out_quotient[1] , two_sc_divisor[0] , two_sc_dividend[0] , wire_out_remainder[0] , ~wire_out_quotient[1] , wire_16_00_01_curry );
endmodule | module interconect_cells(
clk,
reset,
in_divisor,
in_dividend,
valid_input,
valid_output,
mod_res,
div_res_tmp
); |
input signed [31:0] in_dividend;
input signed [15:0] in_divisor;
input clk, reset;
input valid_input;
output reg valid_output;
reg signed [16:0] div_res;
output reg signed [15:0] mod_res;
output reg signed [16:0] div_res_tmp;
reg signed [31:0] dividend;
reg signed [15:0] divisor;
reg signed [31:0] two_sc_dividend;
reg signed [15:0] two_sc_divisor;
wire [16:0] wire_out_quotient;
wire [14:0] wire_out_remainder;
wire one=1'b1;
reg [2:0] cycle_count;
reg [14:0] reg_14_15;
reg [14:0] reg_12_13;
reg [14:0] reg_10_11;
reg [14:0] reg_8_9;
reg [14:0] reg_6_7;
reg [14:0] reg_4_5;
reg [14:0] reg_2_3;
reg [14:0] reg_0_1;
reg reg_14_15_curry;
reg reg_12_13_curry;
reg reg_10_11_curry;
reg reg_8_9_curry;
reg reg_6_7_curry;
reg reg_4_5_curry;
reg reg_2_3_curry;
reg reg_0_1_curry;
always @(posedge clk or posedge reset) begin
if (reset) begin
dividend <= 'b0;
divisor <= 'b0;
end else begin
if (!valid_input) begin
dividend <= 'b0;
divisor <= 'b0;
end else begin
dividend <= in_dividend;
divisor <= in_divisor;
end
end
end
always @(*) begin
if (reset) begin
div_res[16] = 'd0;
div_res[15] = 'd0;
div_res[14] = 'd0;
div_res[13] = 'd0;
div_res[12] = 'd0;
div_res[11] = 'd0;
div_res[10] = 'd0;
div_res[9] = 'd0;
div_res[8] = 'd0;
div_res[7] = 'd0;
div_res[6] = 'd0;
div_res[5] = 'd0;
div_res[4] = 'd0;
div_res[3] = 'd0;
div_res[2] = 'd0;
div_res[1] = 'd0;
div_res[0] = 'd0;
end else begin
div_res[16] = ~wire_out_quotient[16];
div_res[15] = ~wire_out_quotient[15];
div_res[14] = ~wire_out_quotient[14];
div_res[13] = ~wire_out_quotient[13];
div_res[12] = ~wire_out_quotient[12];
div_res[11] = ~wire_out_quotient[11];
div_res[10] = ~wire_out_quotient[10];
div_res[9] = ~wire_out_quotient[9];
div_res[8] = ~wire_out_quotient[8];
div_res[7] = ~wire_out_quotient[7];
div_res[6] = ~wire_out_quotient[6];
div_res[5] = ~wire_out_quotient[5];
div_res[4] = ~wire_out_quotient[4];
div_res[3] = ~wire_out_quotient[3];
div_res[2] = ~wire_out_quotient[2];
div_res[1] = ~wire_out_quotient[1];
div_res[0] = ~wire_out_quotient[0];
end
end
always @(*) begin
if ((dividend[31] && !divisor[15]) || (!dividend[31] && divisor[15])) begin
div_res_tmp = ~div_res;
end else begin
div_res_tmp = div_res;
end
end
always @(*) begin
if (reset) begin
mod_res[15] ='d0;
mod_res[14] ='d0;
mod_res[13] ='d0;
mod_res[12] ='d0;
mod_res[11] ='d0;
mod_res[10] ='d0;
mod_res[9] = 'd0;
mod_res[8] = 'd0;
mod_res[7] = 'd0;
mod_res[6] = 'd0;
mod_res[5] = 'd0;
mod_res[4] = 'd0;
mod_res[3] = 'd0;
mod_res[2] = 'd0;
mod_res[1] = 'd0;
mod_res[0] = 'd0;
end else begin
mod_res[15] = wire_out_quotient[0];
mod_res[14] = wire_out_remainder[14];
mod_res[13] = wire_out_remainder[13];
mod_res[12] = wire_out_remainder[12];
mod_res[11] = wire_out_remainder[11];
mod_res[10] = wire_out_remainder[10];
mod_res[9] = wire_out_remainder[9];
mod_res[8] = wire_out_remainder[8];
mod_res[7] = wire_out_remainder[7];
mod_res[6] = wire_out_remainder[6];
mod_res[5] = wire_out_remainder[5];
mod_res[4] = wire_out_remainder[4];
mod_res[3] = wire_out_remainder[3];
mod_res[2] = wire_out_remainder[2];
mod_res[1] = wire_out_remainder[1];
mod_res[0] = wire_out_remainder[0];
if ( (dividend[31] == 1) && (divisor[15] == 0) ) begin
mod_res = ~mod_res;
mod_res = mod_res + 1'b1;
if (wire_out_quotient[0] == 1) begin
mod_res = mod_res + divisor;
end
end
if ( (wire_out_quotient[0] == 1) && (dividend[31] == 0) && (divisor[15] == 0)) begin
mod_res = mod_res + divisor;
end
if ( (divisor[15] == 1) && (dividend[31] ==1 ) ) begin
mod_res = ~mod_res;
mod_res = mod_res + 1'b1;
if (wire_out_quotient[0] == 1) begin
mod_res = mod_res + divisor;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
two_sc_divisor = 'b0;
two_sc_dividend = 'b0;
end else begin
if (divisor[15]) begin
two_sc_divisor = ~divisor;
two_sc_divisor = two_sc_divisor + 1'b1;
end else begin
two_sc_divisor = divisor;
end
if (dividend[31]) begin
two_sc_dividend = ~dividend;
two_sc_dividend = two_sc_dividend + 1'b1;
end else begin
two_sc_dividend = dividend;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
valid_output <= 1'b0;
cycle_count <= 'b0;
end else begin
cycle_count <= cycle_count + 1'b1;
if (cycle_count == 4) begin
valid_output <= 1'b1;
cycle_count <= 1'b0;
end else begin
valid_output <= 1'b0;
end
end
end
div_cell cas_0_15 ( one , two_sc_divisor[15] , two_sc_dividend[31] , wire_out_quotient[16] , wire_0_14_15_curry , hang_0_wire_15 );
div_cell cas_0_14 ( one , two_sc_divisor[14] , two_sc_dividend[30] , wire_0_14_1_15_remainter , wire_0_13_14_curry , wire_0_14_15_curry );
div_cell cas_0_13 ( one , two_sc_divisor[13] , two_sc_dividend[29] , wire_0_13_1_14_remainter , wire_0_12_13_curry , wire_0_13_14_curry );
div_cell cas_0_12 ( one , two_sc_divisor[12] , two_sc_dividend[28] , wire_0_12_1_13_remainter , wire_0_11_12_curry , wire_0_12_13_curry );
div_cell cas_0_11 ( one , two_sc_divisor[11] , two_sc_dividend[27] , wire_0_11_1_12_remainter , wire_0_10_11_curry , wire_0_11_12_curry );
div_cell cas_0_10 ( one , two_sc_divisor[10] , two_sc_dividend[26] , wire_0_10_1_11_remainter , wire_0_09_10_curry , wire_0_10_11_curry );
div_cell cas_0_9 ( one , two_sc_divisor[9] , two_sc_dividend[25] , wire_0_9_1_10_remainter , wire_0_08_09_curry , wire_0_09_10_curry );
div_cell cas_0_8 ( one , two_sc_divisor[8] , two_sc_dividend[24] , wire_0_8_1_9_remainter , wire_0_07_08_curry , wire_0_08_09_curry );
div_cell cas_0_7 ( one , two_sc_divisor[7] , two_sc_dividend[23] , wire_0_7_1_8_remainter , wire_0_06_07_curry , wire_0_07_08_curry );
div_cell cas_0_6 ( one , two_sc_divisor[6] , two_sc_dividend[22] , wire_0_6_1_7_remainter , wire_0_05_06_curry , wire_0_06_07_curry );
div_cell cas_0_5 ( one , two_sc_divisor[5] , two_sc_dividend[21] , wire_0_5_1_6_remainter , wire_0_04_05_curry , wire_0_05_06_curry );
div_cell cas_0_4 ( one , two_sc_divisor[4] , two_sc_dividend[20] , wire_0_4_1_5_remainter , wire_0_03_04_curry , wire_0_04_05_curry );
div_cell cas_0_3 ( one , two_sc_divisor[3] , two_sc_dividend[19] , wire_0_3_1_4_remainter , wire_0_02_03_curry , wire_0_03_04_curry );
div_cell cas_0_2 ( one , two_sc_divisor[2] , two_sc_dividend[18] , wire_0_2_1_3_remainter , wire_0_01_02_curry , wire_0_02_03_curry );
div_cell cas_0_1 ( one , two_sc_divisor[1] , two_sc_dividend[17] , wire_0_1_1_2_remainter , wire_0_00_01_curry , wire_0_01_02_curry );
div_cell cas_0_0 ( one , two_sc_divisor[0] , two_sc_dividend[16] , wire_0_0_1_1_remainter , one , wire_0_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_0_1 <= 'b0;
reg_0_1_curry <= 'b0;
end else begin
reg_0_1[14] <= wire_0_14_1_15_remainter;
reg_0_1[13] <= wire_0_13_1_14_remainter;
reg_0_1[12] <= wire_0_12_1_13_remainter;
reg_0_1[11] <= wire_0_11_1_12_remainter;
reg_0_1[10] <= wire_0_10_1_11_remainter;
reg_0_1[9] <= wire_0_9_1_10_remainter;
reg_0_1[8] <= wire_0_8_1_9_remainter;
reg_0_1[7] <= wire_0_7_1_8_remainter;
reg_0_1[6] <= wire_0_6_1_7_remainter;
reg_0_1[5] <= wire_0_5_1_6_remainter;
reg_0_1[4] <= wire_0_4_1_5_remainter;
reg_0_1[3] <= wire_0_3_1_4_remainter;
reg_0_1[2] <= wire_0_2_1_3_remainter;
reg_0_1[1] <= wire_0_1_1_2_remainter;
reg_0_1[0] <= wire_0_0_1_1_remainter;
reg_0_1_curry <= wire_out_quotient[16];
end
end
div_cell cas_1_15 (~reg_0_1_curry, two_sc_divisor[15], reg_0_1[14] , wire_out_quotient[15], wire_1_14_15_curry, hang_1_wire_15);
div_cell cas_1_14 ( ~reg_0_1_curry , two_sc_divisor[14] , reg_0_1[13] , wire_1_14_2_15_remainter , wire_1_13_14_curry , wire_1_14_15_curry );
div_cell cas_1_13 ( ~reg_0_1_curry , two_sc_divisor[13] , reg_0_1[12] , wire_1_13_2_14_remainter , wire_1_12_13_curry , wire_1_13_14_curry );
div_cell cas_1_12 ( ~reg_0_1_curry , two_sc_divisor[12] , reg_0_1[11] , wire_1_12_2_13_remainter , wire_1_11_12_curry , wire_1_12_13_curry );
div_cell cas_1_11 ( ~reg_0_1_curry , two_sc_divisor[11] , reg_0_1[10] , wire_1_11_2_12_remainter , wire_1_10_11_curry , wire_1_11_12_curry );
div_cell cas_1_10 ( ~reg_0_1_curry , two_sc_divisor[10] , reg_0_1[9], wire_1_10_2_11_remainter , wire_1_09_10_curry , wire_1_10_11_curry );
div_cell cas_1_9 ( ~reg_0_1_curry , two_sc_divisor[9] , reg_0_1[8] , wire_1_9_2_10_remainter , wire_1_08_09_curry , wire_1_09_10_curry );
div_cell cas_1_8 ( ~reg_0_1_curry , two_sc_divisor[8] , reg_0_1[7] , wire_1_8_2_9_remainter , wire_1_07_08_curry , wire_1_08_09_curry );
div_cell cas_1_7 ( ~reg_0_1_curry , two_sc_divisor[7] , reg_0_1[6] , wire_1_7_2_8_remainter , wire_1_06_07_curry , wire_1_07_08_curry );
div_cell cas_1_6 ( ~reg_0_1_curry , two_sc_divisor[6] , reg_0_1[5] , wire_1_6_2_7_remainter , wire_1_05_06_curry , wire_1_06_07_curry );
div_cell cas_1_5 ( ~reg_0_1_curry , two_sc_divisor[5] , reg_0_1[4] , wire_1_5_2_6_remainter , wire_1_04_05_curry , wire_1_05_06_curry );
div_cell cas_1_4 ( ~reg_0_1_curry , two_sc_divisor[4] , reg_0_1[3] , wire_1_4_2_5_remainter , wire_1_03_04_curry , wire_1_04_05_curry );
div_cell cas_1_3 ( ~reg_0_1_curry , two_sc_divisor[3] , reg_0_1[2] , wire_1_3_2_4_remainter , wire_1_02_03_curry , wire_1_03_04_curry );
div_cell cas_1_2 ( ~reg_0_1_curry , two_sc_divisor[2] , reg_0_1[1] , wire_1_2_2_3_remainter , wire_1_01_02_curry , wire_1_02_03_curry );
div_cell cas_1_1 ( ~reg_0_1_curry , two_sc_divisor[1] , reg_0_1[0] , wire_1_1_2_2_remainter , wire_1_00_01_curry , wire_1_01_02_curry );
div_cell cas_1_0 ( ~reg_0_1_curry , two_sc_divisor[0] , two_sc_dividend[15] , wire_1_0_2_1_remainter , ~reg_0_1_curry , wire_1_00_01_curry );
div_cell cas_2_15 ( ~wire_out_quotient[15] , two_sc_divisor[15] , wire_1_14_2_15_remainter , wire_out_quotient[14] , wire_2_14_15_curry , hang_2_wire_15 );
div_cell cas_2_14 ( ~wire_out_quotient[15] , two_sc_divisor[14] , wire_1_13_2_14_remainter , wire_2_14_3_15_remainter , wire_2_13_14_curry , wire_2_14_15_curry );
div_cell cas_2_13 ( ~wire_out_quotient[15] , two_sc_divisor[13] , wire_1_12_2_13_remainter , wire_2_13_3_14_remainter , wire_2_12_13_curry , wire_2_13_14_curry );
div_cell cas_2_12 ( ~wire_out_quotient[15] , two_sc_divisor[12] , wire_1_11_2_12_remainter , wire_2_12_3_13_remainter , wire_2_11_12_curry , wire_2_12_13_curry );
div_cell cas_2_11 ( ~wire_out_quotient[15] , two_sc_divisor[11] , wire_1_10_2_11_remainter , wire_2_11_3_12_remainter , wire_2_10_11_curry , wire_2_11_12_curry );
div_cell cas_2_10 ( ~wire_out_quotient[15] , two_sc_divisor[10] , wire_1_9_2_10_remainter , wire_2_10_3_11_remainter , wire_2_09_10_curry , wire_2_10_11_curry );
div_cell cas_2_9 ( ~wire_out_quotient[15] , two_sc_divisor[9] , wire_1_8_2_9_remainter , wire_2_9_3_10_remainter , wire_2_08_09_curry , wire_2_09_10_curry );
div_cell cas_2_8 ( ~wire_out_quotient[15] , two_sc_divisor[8] , wire_1_7_2_8_remainter , wire_2_8_3_9_remainter , wire_2_07_08_curry , wire_2_08_09_curry );
div_cell cas_2_7 ( ~wire_out_quotient[15] , two_sc_divisor[7] , wire_1_6_2_7_remainter , wire_2_7_3_8_remainter , wire_2_06_07_curry , wire_2_07_08_curry );
div_cell cas_2_6 ( ~wire_out_quotient[15] , two_sc_divisor[6] , wire_1_5_2_6_remainter , wire_2_6_3_7_remainter , wire_2_05_06_curry , wire_2_06_07_curry );
div_cell cas_2_5 ( ~wire_out_quotient[15] , two_sc_divisor[5] , wire_1_4_2_5_remainter , wire_2_5_3_6_remainter , wire_2_04_05_curry , wire_2_05_06_curry );
div_cell cas_2_4 ( ~wire_out_quotient[15] , two_sc_divisor[4] , wire_1_3_2_4_remainter , wire_2_4_3_5_remainter , wire_2_03_04_curry , wire_2_04_05_curry );
div_cell cas_2_3 ( ~wire_out_quotient[15] , two_sc_divisor[3] , wire_1_2_2_3_remainter , wire_2_3_3_4_remainter , wire_2_02_03_curry , wire_2_03_04_curry );
div_cell cas_2_2 ( ~wire_out_quotient[15] , two_sc_divisor[2] , wire_1_1_2_2_remainter , wire_2_2_3_3_remainter , wire_2_01_02_curry , wire_2_02_03_curry );
div_cell cas_2_1 ( ~wire_out_quotient[15] , two_sc_divisor[1] , wire_1_0_2_1_remainter , wire_2_1_3_2_remainter , wire_2_00_01_curry , wire_2_01_02_curry );
div_cell cas_2_0 ( ~wire_out_quotient[15] , two_sc_divisor[0] , two_sc_dividend[14] , wire_2_0_3_1_remainter , ~wire_out_quotient[15] , wire_2_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_2_3 <= 'b0;
reg_2_3_curry <= 'b0;
end else begin
reg_2_3[14] <= wire_2_14_3_15_remainter;
reg_2_3[13] <= wire_2_13_3_14_remainter;
reg_2_3[12] <= wire_2_12_3_13_remainter;
reg_2_3[11] <= wire_2_11_3_12_remainter;
reg_2_3[10] <= wire_2_10_3_11_remainter;
reg_2_3[9] <= wire_2_9_3_10_remainter;
reg_2_3[8] <= wire_2_8_3_9_remainter;
reg_2_3[7] <= wire_2_7_3_8_remainter;
reg_2_3[6] <= wire_2_6_3_7_remainter;
reg_2_3[5] <= wire_2_5_3_6_remainter;
reg_2_3[4] <= wire_2_4_3_5_remainter;
reg_2_3[3] <= wire_2_3_3_4_remainter;
reg_2_3[2] <= wire_2_2_3_3_remainter;
reg_2_3[1] <= wire_2_1_3_2_remainter;
reg_2_3[0] <= wire_2_0_3_1_remainter;
reg_2_3_curry <= wire_out_quotient[14];
end
end
div_cell cas_3_15 ( ~reg_2_3_curry , two_sc_divisor[15] , reg_2_3[14] , wire_out_quotient[13] , wire_3_14_15_curry , hang_3_wire_15 );
div_cell cas_3_14 ( ~reg_2_3_curry , two_sc_divisor[14] , reg_2_3[13] , wire_3_14_4_15_remainter , wire_3_13_14_curry , wire_3_14_15_curry );
div_cell cas_3_13 ( ~reg_2_3_curry , two_sc_divisor[13] , reg_2_3[12] , wire_3_13_4_14_remainter , wire_3_12_13_curry , wire_3_13_14_curry );
div_cell cas_3_12 ( ~reg_2_3_curry , two_sc_divisor[12] , reg_2_3[11] , wire_3_12_4_13_remainter , wire_3_11_12_curry , wire_3_12_13_curry );
div_cell cas_3_11 ( ~reg_2_3_curry , two_sc_divisor[11] , reg_2_3[10] , wire_3_11_4_12_remainter , wire_3_10_11_curry , wire_3_11_12_curry );
div_cell cas_3_10 ( ~reg_2_3_curry , two_sc_divisor[10] , reg_2_3[9], wire_3_10_4_11_remainter , wire_3_09_10_curry , wire_3_10_11_curry );
div_cell cas_3_9 ( ~reg_2_3_curry , two_sc_divisor[9] , reg_2_3[8] , wire_3_9_4_10_remainter , wire_3_08_09_curry , wire_3_09_10_curry );
div_cell cas_3_8 ( ~reg_2_3_curry , two_sc_divisor[8] , reg_2_3[7] , wire_3_8_4_9_remainter , wire_3_07_08_curry , wire_3_08_09_curry );
div_cell cas_3_7 ( ~reg_2_3_curry , two_sc_divisor[7] , reg_2_3[6] , wire_3_7_4_8_remainter , wire_3_06_07_curry , wire_3_07_08_curry );
div_cell cas_3_6 ( ~reg_2_3_curry , two_sc_divisor[6] , reg_2_3[5] , wire_3_6_4_7_remainter , wire_3_05_06_curry , wire_3_06_07_curry );
div_cell cas_3_5 ( ~reg_2_3_curry , two_sc_divisor[5] , reg_2_3[4] , wire_3_5_4_6_remainter , wire_3_04_05_curry , wire_3_05_06_curry );
div_cell cas_3_4 ( ~reg_2_3_curry , two_sc_divisor[4] , reg_2_3[3] , wire_3_4_4_5_remainter , wire_3_03_04_curry , wire_3_04_05_curry );
div_cell cas_3_3 ( ~reg_2_3_curry , two_sc_divisor[3] , reg_2_3[2] , wire_3_3_4_4_remainter , wire_3_02_03_curry , wire_3_03_04_curry );
div_cell cas_3_2 ( ~reg_2_3_curry , two_sc_divisor[2] , reg_2_3[1] , wire_3_2_4_3_remainter , wire_3_01_02_curry , wire_3_02_03_curry );
div_cell cas_3_1 ( ~reg_2_3_curry , two_sc_divisor[1] , reg_2_3[0] , wire_3_1_4_2_remainter , wire_3_00_01_curry , wire_3_01_02_curry );
div_cell cas_3_0 ( ~reg_2_3_curry , two_sc_divisor[0] , two_sc_dividend[13] , wire_3_0_4_1_remainter , ~reg_2_3_curry , wire_3_00_01_curry );
div_cell cas_4_15 ( ~wire_out_quotient[13] , two_sc_divisor[15] , wire_3_14_4_15_remainter , wire_out_quotient[12] , wire_4_14_15_curry , hang_4_wire_15 );
div_cell cas_4_14 ( ~wire_out_quotient[13] , two_sc_divisor[14] , wire_3_13_4_14_remainter , wire_4_14_5_15_remainter , wire_4_13_14_curry , wire_4_14_15_curry );
div_cell cas_4_13 ( ~wire_out_quotient[13] , two_sc_divisor[13] , wire_3_12_4_13_remainter , wire_4_13_5_14_remainter , wire_4_12_13_curry , wire_4_13_14_curry );
div_cell cas_4_12 ( ~wire_out_quotient[13] , two_sc_divisor[12] , wire_3_11_4_12_remainter , wire_4_12_5_13_remainter , wire_4_11_12_curry , wire_4_12_13_curry );
div_cell cas_4_11 ( ~wire_out_quotient[13] , two_sc_divisor[11] , wire_3_10_4_11_remainter , wire_4_11_5_12_remainter , wire_4_10_11_curry , wire_4_11_12_curry );
div_cell cas_4_10 ( ~wire_out_quotient[13] , two_sc_divisor[10] , wire_3_9_4_10_remainter , wire_4_10_5_11_remainter , wire_4_09_10_curry , wire_4_10_11_curry );
div_cell cas_4_9 ( ~wire_out_quotient[13] , two_sc_divisor[9] , wire_3_8_4_9_remainter , wire_4_9_5_10_remainter , wire_4_08_09_curry , wire_4_09_10_curry );
div_cell cas_4_8 ( ~wire_out_quotient[13] , two_sc_divisor[8] , wire_3_7_4_8_remainter , wire_4_8_5_9_remainter , wire_4_07_08_curry , wire_4_08_09_curry );
div_cell cas_4_7 ( ~wire_out_quotient[13] , two_sc_divisor[7] , wire_3_6_4_7_remainter , wire_4_7_5_8_remainter , wire_4_06_07_curry , wire_4_07_08_curry );
div_cell cas_4_6 ( ~wire_out_quotient[13] , two_sc_divisor[6] , wire_3_5_4_6_remainter , wire_4_6_5_7_remainter , wire_4_05_06_curry , wire_4_06_07_curry );
div_cell cas_4_5 ( ~wire_out_quotient[13] , two_sc_divisor[5] , wire_3_4_4_5_remainter , wire_4_5_5_6_remainter , wire_4_04_05_curry , wire_4_05_06_curry );
div_cell cas_4_4 ( ~wire_out_quotient[13] , two_sc_divisor[4] , wire_3_3_4_4_remainter , wire_4_4_5_5_remainter , wire_4_03_04_curry , wire_4_04_05_curry );
div_cell cas_4_3 ( ~wire_out_quotient[13] , two_sc_divisor[3] , wire_3_2_4_3_remainter , wire_4_3_5_4_remainter , wire_4_02_03_curry , wire_4_03_04_curry );
div_cell cas_4_2 ( ~wire_out_quotient[13] , two_sc_divisor[2] , wire_3_1_4_2_remainter , wire_4_2_5_3_remainter , wire_4_01_02_curry , wire_4_02_03_curry );
div_cell cas_4_1 ( ~wire_out_quotient[13] , two_sc_divisor[1] , wire_3_0_4_1_remainter , wire_4_1_5_2_remainter , wire_4_00_01_curry , wire_4_01_02_curry );
div_cell cas_4_0 ( ~wire_out_quotient[13] , two_sc_divisor[0] , two_sc_dividend[12] , wire_4_0_5_1_remainter , ~wire_out_quotient[13] , wire_4_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_4_5 <= 'b0;
reg_4_5_curry <= 'b0;
end else begin
reg_4_5[14] <= wire_4_14_5_15_remainter;
reg_4_5[13] <= wire_4_13_5_14_remainter;
reg_4_5[12] <= wire_4_12_5_13_remainter;
reg_4_5[11] <= wire_4_11_5_12_remainter;
reg_4_5[10] <= wire_4_10_5_11_remainter;
reg_4_5[9] <= wire_4_9_5_10_remainter;
reg_4_5[8] <= wire_4_8_5_9_remainter;
reg_4_5[7] <= wire_4_7_5_8_remainter;
reg_4_5[6] <= wire_4_6_5_7_remainter;
reg_4_5[5] <= wire_4_5_5_6_remainter;
reg_4_5[4] <= wire_4_4_5_5_remainter;
reg_4_5[3] <= wire_4_3_5_4_remainter;
reg_4_5[2] <= wire_4_2_5_3_remainter;
reg_4_5[1] <= wire_4_1_5_2_remainter;
reg_4_5[0] <= wire_4_0_5_1_remainter;
reg_4_5_curry <= wire_out_quotient[12];
end
end
div_cell cas_5_15 ( ~reg_4_5_curry , two_sc_divisor[15] ,reg_4_5[14] , wire_out_quotient[11] , wire_5_14_15_curry , hang_5_wire_15 );
div_cell cas_5_14 ( ~reg_4_5_curry , two_sc_divisor[14] ,reg_4_5[13] , wire_5_14_6_15_remainter , wire_5_13_14_curry , wire_5_14_15_curry );
div_cell cas_5_13 ( ~reg_4_5_curry , two_sc_divisor[13] ,reg_4_5[12] , wire_5_13_6_14_remainter , wire_5_12_13_curry , wire_5_13_14_curry );
div_cell cas_5_12 ( ~reg_4_5_curry , two_sc_divisor[12] ,reg_4_5[11] , wire_5_12_6_13_remainter , wire_5_11_12_curry , wire_5_12_13_curry );
div_cell cas_5_11 ( ~reg_4_5_curry , two_sc_divisor[11] ,reg_4_5[10] , wire_5_11_6_12_remainter , wire_5_10_11_curry , wire_5_11_12_curry );
div_cell cas_5_10 ( ~reg_4_5_curry , two_sc_divisor[10] ,reg_4_5[9] , wire_5_10_6_11_remainter , wire_5_09_10_curry , wire_5_10_11_curry );
div_cell cas_5_9 ( ~reg_4_5_curry , two_sc_divisor[9] , reg_4_5[8] , wire_5_9_6_10_remainter , wire_5_08_09_curry , wire_5_09_10_curry );
div_cell cas_5_8 ( ~reg_4_5_curry , two_sc_divisor[8] , reg_4_5[7] , wire_5_8_6_9_remainter , wire_5_07_08_curry , wire_5_08_09_curry );
div_cell cas_5_7 ( ~reg_4_5_curry , two_sc_divisor[7] , reg_4_5[6] , wire_5_7_6_8_remainter , wire_5_06_07_curry , wire_5_07_08_curry );
div_cell cas_5_6 ( ~reg_4_5_curry , two_sc_divisor[6] , reg_4_5[5] , wire_5_6_6_7_remainter , wire_5_05_06_curry , wire_5_06_07_curry );
div_cell cas_5_5 ( ~reg_4_5_curry , two_sc_divisor[5] , reg_4_5[4] , wire_5_5_6_6_remainter , wire_5_04_05_curry , wire_5_05_06_curry );
div_cell cas_5_4 ( ~reg_4_5_curry , two_sc_divisor[4] , reg_4_5[3] , wire_5_4_6_5_remainter , wire_5_03_04_curry , wire_5_04_05_curry );
div_cell cas_5_3 ( ~reg_4_5_curry , two_sc_divisor[3] , reg_4_5[2] , wire_5_3_6_4_remainter , wire_5_02_03_curry , wire_5_03_04_curry );
div_cell cas_5_2 ( ~reg_4_5_curry , two_sc_divisor[2] , reg_4_5[1] , wire_5_2_6_3_remainter , wire_5_01_02_curry , wire_5_02_03_curry );
div_cell cas_5_1 ( ~reg_4_5_curry , two_sc_divisor[1] , reg_4_5[0] , wire_5_1_6_2_remainter , wire_5_00_01_curry , wire_5_01_02_curry );
div_cell cas_5_0 ( ~reg_4_5_curry , two_sc_divisor[0] , two_sc_dividend[11] , wire_5_0_6_1_remainter , ~reg_4_5_curry , wire_5_00_01_curry );
div_cell cas_6_15 ( ~wire_out_quotient[11] , two_sc_divisor[15] , wire_5_14_6_15_remainter , wire_out_quotient[10] , wire_6_14_15_curry , hang_6_wire_15 );
div_cell cas_6_14 ( ~wire_out_quotient[11] , two_sc_divisor[14] , wire_5_13_6_14_remainter , wire_6_14_7_15_remainter , wire_6_13_14_curry , wire_6_14_15_curry );
div_cell cas_6_13 ( ~wire_out_quotient[11] , two_sc_divisor[13] , wire_5_12_6_13_remainter , wire_6_13_7_14_remainter , wire_6_12_13_curry , wire_6_13_14_curry );
div_cell cas_6_12 ( ~wire_out_quotient[11] , two_sc_divisor[12] , wire_5_11_6_12_remainter , wire_6_12_7_13_remainter , wire_6_11_12_curry , wire_6_12_13_curry );
div_cell cas_6_11 ( ~wire_out_quotient[11] , two_sc_divisor[11] , wire_5_10_6_11_remainter , wire_6_11_7_12_remainter , wire_6_10_11_curry , wire_6_11_12_curry );
div_cell cas_6_10 ( ~wire_out_quotient[11] , two_sc_divisor[10] , wire_5_9_6_10_remainter , wire_6_10_7_11_remainter , wire_6_09_10_curry , wire_6_10_11_curry );
div_cell cas_6_9 ( ~wire_out_quotient[11] , two_sc_divisor[9] , wire_5_8_6_9_remainter , wire_6_9_7_10_remainter , wire_6_08_09_curry , wire_6_09_10_curry );
div_cell cas_6_8 ( ~wire_out_quotient[11] , two_sc_divisor[8] , wire_5_7_6_8_remainter , wire_6_8_7_9_remainter , wire_6_07_08_curry , wire_6_08_09_curry );
div_cell cas_6_7 ( ~wire_out_quotient[11] , two_sc_divisor[7] , wire_5_6_6_7_remainter , wire_6_7_7_8_remainter , wire_6_06_07_curry , wire_6_07_08_curry );
div_cell cas_6_6 ( ~wire_out_quotient[11] , two_sc_divisor[6] , wire_5_5_6_6_remainter , wire_6_6_7_7_remainter , wire_6_05_06_curry , wire_6_06_07_curry );
div_cell cas_6_5 ( ~wire_out_quotient[11] , two_sc_divisor[5] , wire_5_4_6_5_remainter , wire_6_5_7_6_remainter , wire_6_04_05_curry , wire_6_05_06_curry );
div_cell cas_6_4 ( ~wire_out_quotient[11] , two_sc_divisor[4] , wire_5_3_6_4_remainter , wire_6_4_7_5_remainter , wire_6_03_04_curry , wire_6_04_05_curry );
div_cell cas_6_3 ( ~wire_out_quotient[11] , two_sc_divisor[3] , wire_5_2_6_3_remainter , wire_6_3_7_4_remainter , wire_6_02_03_curry , wire_6_03_04_curry );
div_cell cas_6_2 ( ~wire_out_quotient[11] , two_sc_divisor[2] , wire_5_1_6_2_remainter , wire_6_2_7_3_remainter , wire_6_01_02_curry , wire_6_02_03_curry );
div_cell cas_6_1 ( ~wire_out_quotient[11] , two_sc_divisor[1] , wire_5_0_6_1_remainter , wire_6_1_7_2_remainter , wire_6_00_01_curry , wire_6_01_02_curry );
div_cell cas_6_0 ( ~wire_out_quotient[11] , two_sc_divisor[0] , two_sc_dividend[10] , wire_6_0_7_1_remainter , ~wire_out_quotient[11] , wire_6_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_6_7 <= 'b0;
reg_6_7_curry <= 'b0;
end else begin
reg_6_7[14] <= wire_6_14_7_15_remainter;
reg_6_7[13] <= wire_6_13_7_14_remainter;
reg_6_7[12] <= wire_6_12_7_13_remainter;
reg_6_7[11] <= wire_6_11_7_12_remainter;
reg_6_7[10] <= wire_6_10_7_11_remainter;
reg_6_7[9] <= wire_6_9_7_10_remainter;
reg_6_7[8] <= wire_6_8_7_9_remainter;
reg_6_7[7] <= wire_6_7_7_8_remainter;
reg_6_7[6] <= wire_6_6_7_7_remainter;
reg_6_7[5] <= wire_6_5_7_6_remainter;
reg_6_7[4] <= wire_6_4_7_5_remainter;
reg_6_7[3] <= wire_6_3_7_4_remainter;
reg_6_7[2] <= wire_6_2_7_3_remainter;
reg_6_7[1] <= wire_6_1_7_2_remainter;
reg_6_7[0] <= wire_6_0_7_1_remainter;
reg_6_7_curry <= wire_out_quotient[10];
end
end
div_cell cas_7_15 ( ~reg_6_7_curry , two_sc_divisor[15] , reg_6_7[14] , wire_out_quotient[9] , wire_7_14_15_curry , hang_7_wire_15 );
div_cell cas_7_14 ( ~reg_6_7_curry , two_sc_divisor[14] , reg_6_7[13] , wire_7_14_8_15_remainter , wire_7_13_14_curry , wire_7_14_15_curry );
div_cell cas_7_13 ( ~reg_6_7_curry , two_sc_divisor[13] , reg_6_7[12] , wire_7_13_8_14_remainter , wire_7_12_13_curry , wire_7_13_14_curry );
div_cell cas_7_12 ( ~reg_6_7_curry , two_sc_divisor[12] , reg_6_7[11] , wire_7_12_8_13_remainter , wire_7_11_12_curry , wire_7_12_13_curry );
div_cell cas_7_11 ( ~reg_6_7_curry , two_sc_divisor[11] , reg_6_7[10] , wire_7_11_8_12_remainter , wire_7_10_11_curry , wire_7_11_12_curry );
div_cell cas_7_10 ( ~reg_6_7_curry , two_sc_divisor[10] , reg_6_7[9] , wire_7_10_8_11_remainter , wire_7_09_10_curry , wire_7_10_11_curry );
div_cell cas_7_9 ( ~reg_6_7_curry , two_sc_divisor[9] , reg_6_7[8] , wire_7_9_8_10_remainter , wire_7_08_09_curry , wire_7_09_10_curry );
div_cell cas_7_8 ( ~reg_6_7_curry , two_sc_divisor[8] , reg_6_7[7] , wire_7_8_8_9_remainter , wire_7_07_08_curry , wire_7_08_09_curry );
div_cell cas_7_7 ( ~reg_6_7_curry , two_sc_divisor[7] , reg_6_7[6] , wire_7_7_8_8_remainter , wire_7_06_07_curry , wire_7_07_08_curry );
div_cell cas_7_6 ( ~reg_6_7_curry , two_sc_divisor[6] , reg_6_7[5] , wire_7_6_8_7_remainter , wire_7_05_06_curry , wire_7_06_07_curry );
div_cell cas_7_5 ( ~reg_6_7_curry , two_sc_divisor[5] , reg_6_7[4] , wire_7_5_8_6_remainter , wire_7_04_05_curry , wire_7_05_06_curry );
div_cell cas_7_4 ( ~reg_6_7_curry , two_sc_divisor[4] , reg_6_7[3] , wire_7_4_8_5_remainter , wire_7_03_04_curry , wire_7_04_05_curry );
div_cell cas_7_3 ( ~reg_6_7_curry , two_sc_divisor[3] , reg_6_7[2] , wire_7_3_8_4_remainter , wire_7_02_03_curry , wire_7_03_04_curry );
div_cell cas_7_2 ( ~reg_6_7_curry , two_sc_divisor[2] , reg_6_7[1] , wire_7_2_8_3_remainter , wire_7_01_02_curry , wire_7_02_03_curry );
div_cell cas_7_1 ( ~reg_6_7_curry , two_sc_divisor[1] , reg_6_7[0] , wire_7_1_8_2_remainter , wire_7_00_01_curry , wire_7_01_02_curry );
div_cell cas_7_0 ( ~reg_6_7_curry , two_sc_divisor[0] , two_sc_dividend[9] , wire_7_0_8_1_remainter , ~reg_6_7_curry , wire_7_00_01_curry );
div_cell cas_8_15 ( ~wire_out_quotient[9] , two_sc_divisor[15] , wire_7_14_8_15_remainter , wire_out_quotient[8] , wire_8_14_15_curry , hang_8_wire_15 );
div_cell cas_8_14 ( ~wire_out_quotient[9] , two_sc_divisor[14] , wire_7_13_8_14_remainter , wire_8_14_9_15_remainter , wire_8_13_14_curry , wire_8_14_15_curry );
div_cell cas_8_13 ( ~wire_out_quotient[9] , two_sc_divisor[13] , wire_7_12_8_13_remainter , wire_8_13_9_14_remainter , wire_8_12_13_curry , wire_8_13_14_curry );
div_cell cas_8_12 ( ~wire_out_quotient[9] , two_sc_divisor[12] , wire_7_11_8_12_remainter , wire_8_12_9_13_remainter , wire_8_11_12_curry , wire_8_12_13_curry );
div_cell cas_8_11 ( ~wire_out_quotient[9] , two_sc_divisor[11] , wire_7_10_8_11_remainter , wire_8_11_9_12_remainter , wire_8_10_11_curry , wire_8_11_12_curry );
div_cell cas_8_10 ( ~wire_out_quotient[9] , two_sc_divisor[10] , wire_7_9_8_10_remainter , wire_8_10_9_11_remainter , wire_8_09_10_curry , wire_8_10_11_curry );
div_cell cas_8_9 ( ~wire_out_quotient[9] , two_sc_divisor[9] , wire_7_8_8_9_remainter , wire_8_9_9_10_remainter , wire_8_08_09_curry , wire_8_09_10_curry );
div_cell cas_8_8 ( ~wire_out_quotient[9] , two_sc_divisor[8] , wire_7_7_8_8_remainter , wire_8_8_9_9_remainter , wire_8_07_08_curry , wire_8_08_09_curry );
div_cell cas_8_7 ( ~wire_out_quotient[9] , two_sc_divisor[7] , wire_7_6_8_7_remainter , wire_8_7_9_8_remainter , wire_8_06_07_curry , wire_8_07_08_curry );
div_cell cas_8_6 ( ~wire_out_quotient[9] , two_sc_divisor[6] , wire_7_5_8_6_remainter , wire_8_6_9_7_remainter , wire_8_05_06_curry , wire_8_06_07_curry );
div_cell cas_8_5 ( ~wire_out_quotient[9] , two_sc_divisor[5] , wire_7_4_8_5_remainter , wire_8_5_9_6_remainter , wire_8_04_05_curry , wire_8_05_06_curry );
div_cell cas_8_4 ( ~wire_out_quotient[9] , two_sc_divisor[4] , wire_7_3_8_4_remainter , wire_8_4_9_5_remainter , wire_8_03_04_curry , wire_8_04_05_curry );
div_cell cas_8_3 ( ~wire_out_quotient[9] , two_sc_divisor[3] , wire_7_2_8_3_remainter , wire_8_3_9_4_remainter , wire_8_02_03_curry , wire_8_03_04_curry );
div_cell cas_8_2 ( ~wire_out_quotient[9] , two_sc_divisor[2] , wire_7_1_8_2_remainter , wire_8_2_9_3_remainter , wire_8_01_02_curry , wire_8_02_03_curry );
div_cell cas_8_1 ( ~wire_out_quotient[9] , two_sc_divisor[1] , wire_7_0_8_1_remainter , wire_8_1_9_2_remainter , wire_8_00_01_curry , wire_8_01_02_curry );
div_cell cas_8_0 ( ~wire_out_quotient[9] , two_sc_divisor[0] , two_sc_dividend[8] , wire_8_0_9_1_remainter , ~wire_out_quotient[9] , wire_8_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_8_9 <= 'b0;
reg_8_9_curry <= 'b0;
end else begin
reg_8_9[14] <= wire_8_14_9_15_remainter;
reg_8_9[13] <= wire_8_13_9_14_remainter;
reg_8_9[12] <= wire_8_12_9_13_remainter;
reg_8_9[11] <= wire_8_11_9_12_remainter;
reg_8_9[10] <= wire_8_10_9_11_remainter;
reg_8_9[9] <= wire_8_9_9_10_remainter;
reg_8_9[8] <= wire_8_8_9_9_remainter;
reg_8_9[7] <= wire_8_7_9_8_remainter;
reg_8_9[6] <= wire_8_6_9_7_remainter;
reg_8_9[5] <= wire_8_5_9_6_remainter;
reg_8_9[4] <= wire_8_4_9_5_remainter;
reg_8_9[3] <= wire_8_3_9_4_remainter;
reg_8_9[2] <= wire_8_2_9_3_remainter;
reg_8_9[1] <= wire_8_1_9_2_remainter;
reg_8_9[0] <= wire_8_0_9_1_remainter;
reg_8_9_curry <= wire_out_quotient[8];
end
end
div_cell cas_9_15 ( ~reg_8_9_curry , two_sc_divisor[15] , reg_8_9[14] , wire_out_quotient[7] , wire_9_14_15_curry , hang_9_wire_15 );
div_cell cas_9_14 ( ~reg_8_9_curry , two_sc_divisor[14] , reg_8_9[13] , wire_9_14_10_15_remainter , wire_9_13_14_curry , wire_9_14_15_curry );
div_cell cas_9_13 ( ~reg_8_9_curry , two_sc_divisor[13] , reg_8_9[12] , wire_9_13_10_14_remainter , wire_9_12_13_curry , wire_9_13_14_curry );
div_cell cas_9_12 ( ~reg_8_9_curry , two_sc_divisor[12] , reg_8_9[11] , wire_9_12_10_13_remainter , wire_9_11_12_curry , wire_9_12_13_curry );
div_cell cas_9_11 ( ~reg_8_9_curry , two_sc_divisor[11] , reg_8_9[10] , wire_9_11_10_12_remainter , wire_9_10_11_curry , wire_9_11_12_curry );
div_cell cas_9_10 ( ~reg_8_9_curry , two_sc_divisor[10] , reg_8_9[9] , wire_9_10_10_11_remainter , wire_9_09_10_curry , wire_9_10_11_curry );
div_cell cas_9_9 ( ~reg_8_9_curry , two_sc_divisor[9] , reg_8_9[8] , wire_9_9_10_10_remainter , wire_9_08_09_curry , wire_9_09_10_curry );
div_cell cas_9_8 ( ~reg_8_9_curry , two_sc_divisor[8] , reg_8_9[7] , wire_9_8_10_9_remainter , wire_9_07_08_curry , wire_9_08_09_curry );
div_cell cas_9_7 ( ~reg_8_9_curry , two_sc_divisor[7] , reg_8_9[6] , wire_9_7_10_8_remainter , wire_9_06_07_curry , wire_9_07_08_curry );
div_cell cas_9_6 ( ~reg_8_9_curry , two_sc_divisor[6] , reg_8_9[5] , wire_9_6_10_7_remainter , wire_9_05_06_curry , wire_9_06_07_curry );
div_cell cas_9_5 ( ~reg_8_9_curry , two_sc_divisor[5] , reg_8_9[4] , wire_9_5_10_6_remainter , wire_9_04_05_curry , wire_9_05_06_curry );
div_cell cas_9_4 ( ~reg_8_9_curry , two_sc_divisor[4] , reg_8_9[3] , wire_9_4_10_5_remainter , wire_9_03_04_curry , wire_9_04_05_curry );
div_cell cas_9_3 ( ~reg_8_9_curry , two_sc_divisor[3] , reg_8_9[2] , wire_9_3_10_4_remainter , wire_9_02_03_curry , wire_9_03_04_curry );
div_cell cas_9_2 ( ~reg_8_9_curry , two_sc_divisor[2] , reg_8_9[1] , wire_9_2_10_3_remainter , wire_9_01_02_curry , wire_9_02_03_curry );
div_cell cas_9_1 ( ~reg_8_9_curry , two_sc_divisor[1] , reg_8_9[0] , wire_9_1_10_2_remainter , wire_9_00_01_curry , wire_9_01_02_curry );
div_cell cas_9_0 ( ~reg_8_9_curry , two_sc_divisor[0] , two_sc_dividend[7] , wire_9_0_10_1_remainter , ~reg_8_9_curry , wire_9_00_01_curry );
div_cell cas_10_15 ( ~wire_out_quotient[7] , two_sc_divisor[15] , wire_9_14_10_15_remainter , wire_out_quotient[6] , wire_10_14_15_curry , hang_10_wire_15 );
div_cell cas_10_14 ( ~wire_out_quotient[7] , two_sc_divisor[14] , wire_9_13_10_14_remainter , wire_10_14_11_15_remainter , wire_10_13_14_curry , wire_10_14_15_curry );
div_cell cas_10_13 ( ~wire_out_quotient[7] , two_sc_divisor[13] , wire_9_12_10_13_remainter , wire_10_13_11_14_remainter , wire_10_12_13_curry , wire_10_13_14_curry );
div_cell cas_10_12 ( ~wire_out_quotient[7] , two_sc_divisor[12] , wire_9_11_10_12_remainter , wire_10_12_11_13_remainter , wire_10_11_12_curry , wire_10_12_13_curry );
div_cell cas_10_11 ( ~wire_out_quotient[7] , two_sc_divisor[11] , wire_9_10_10_11_remainter , wire_10_11_11_12_remainter , wire_10_10_11_curry , wire_10_11_12_curry );
div_cell cas_10_10 ( ~wire_out_quotient[7] , two_sc_divisor[10] , wire_9_9_10_10_remainter , wire_10_10_11_11_remainter , wire_10_09_10_curry , wire_10_10_11_curry );
div_cell cas_10_9 ( ~wire_out_quotient[7] , two_sc_divisor[9] , wire_9_8_10_9_remainter , wire_10_9_11_10_remainter , wire_10_08_09_curry , wire_10_09_10_curry );
div_cell cas_10_8 ( ~wire_out_quotient[7] , two_sc_divisor[8] , wire_9_7_10_8_remainter , wire_10_8_11_9_remainter , wire_10_07_08_curry , wire_10_08_09_curry );
div_cell cas_10_7 ( ~wire_out_quotient[7] , two_sc_divisor[7] , wire_9_6_10_7_remainter , wire_10_7_11_8_remainter , wire_10_06_07_curry , wire_10_07_08_curry );
div_cell cas_10_6 ( ~wire_out_quotient[7] , two_sc_divisor[6] , wire_9_5_10_6_remainter , wire_10_6_11_7_remainter , wire_10_05_06_curry , wire_10_06_07_curry );
div_cell cas_10_5 ( ~wire_out_quotient[7] , two_sc_divisor[5] , wire_9_4_10_5_remainter , wire_10_5_11_6_remainter , wire_10_04_05_curry , wire_10_05_06_curry );
div_cell cas_10_4 ( ~wire_out_quotient[7] , two_sc_divisor[4] , wire_9_3_10_4_remainter , wire_10_4_11_5_remainter , wire_10_03_04_curry , wire_10_04_05_curry );
div_cell cas_10_3 ( ~wire_out_quotient[7] , two_sc_divisor[3] , wire_9_2_10_3_remainter , wire_10_3_11_4_remainter , wire_10_02_03_curry , wire_10_03_04_curry );
div_cell cas_10_2 ( ~wire_out_quotient[7] , two_sc_divisor[2] , wire_9_1_10_2_remainter , wire_10_2_11_3_remainter , wire_10_01_02_curry , wire_10_02_03_curry );
div_cell cas_10_1 ( ~wire_out_quotient[7] , two_sc_divisor[1] , wire_9_0_10_1_remainter , wire_10_1_11_2_remainter , wire_10_00_01_curry , wire_10_01_02_curry );
div_cell cas_10_0 ( ~wire_out_quotient[7] , two_sc_divisor[0] , two_sc_dividend[6] , wire_10_0_11_1_remainter , ~wire_out_quotient[7] , wire_10_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_10_11 <= 'b0;
reg_10_11_curry <= 'b0;
end else begin
reg_10_11[14] <= wire_10_14_11_15_remainter;
reg_10_11[13] <= wire_10_13_11_14_remainter;
reg_10_11[12] <= wire_10_12_11_13_remainter;
reg_10_11[11] <= wire_10_11_11_12_remainter;
reg_10_11[10] <= wire_10_10_11_11_remainter;
reg_10_11[9] <= wire_10_9_11_10_remainter;
reg_10_11[8] <= wire_10_8_11_9_remainter;
reg_10_11[7] <= wire_10_7_11_8_remainter;
reg_10_11[6] <= wire_10_6_11_7_remainter;
reg_10_11[5] <= wire_10_5_11_6_remainter;
reg_10_11[4] <= wire_10_4_11_5_remainter;
reg_10_11[3] <= wire_10_3_11_4_remainter;
reg_10_11[2] <= wire_10_2_11_3_remainter;
reg_10_11[1] <= wire_10_1_11_2_remainter;
reg_10_11[0] <= wire_10_0_11_1_remainter;
reg_10_11_curry <= wire_out_quotient[6];
end
end
div_cell cas_11_15 ( ~reg_10_11_curry , two_sc_divisor[15] , reg_10_11[14] , wire_out_quotient[5] , wire_11_14_15_curry , hang_11_wire_15 );
div_cell cas_11_14 ( ~reg_10_11_curry , two_sc_divisor[14] , reg_10_11[13] , wire_11_14_12_15_remainter , wire_11_13_14_curry , wire_11_14_15_curry );
div_cell cas_11_13 ( ~reg_10_11_curry , two_sc_divisor[13] , reg_10_11[12] , wire_11_13_12_14_remainter , wire_11_12_13_curry , wire_11_13_14_curry );
div_cell cas_11_12 ( ~reg_10_11_curry , two_sc_divisor[12] , reg_10_11[11] , wire_11_12_12_13_remainter , wire_11_11_12_curry , wire_11_12_13_curry );
div_cell cas_11_11 ( ~reg_10_11_curry , two_sc_divisor[11] , reg_10_11[10] , wire_11_11_12_12_remainter , wire_11_10_11_curry , wire_11_11_12_curry );
div_cell cas_11_10 ( ~reg_10_11_curry , two_sc_divisor[10] , reg_10_11[9], wire_11_10_12_11_remainter , wire_11_09_10_curry , wire_11_10_11_curry );
div_cell cas_11_9 ( ~reg_10_11_curry , two_sc_divisor[9] , reg_10_11[8] , wire_11_9_12_10_remainter , wire_11_08_09_curry , wire_11_09_10_curry );
div_cell cas_11_8 ( ~reg_10_11_curry , two_sc_divisor[8] , reg_10_11[7] , wire_11_8_12_9_remainter , wire_11_07_08_curry , wire_11_08_09_curry );
div_cell cas_11_7 ( ~reg_10_11_curry , two_sc_divisor[7] , reg_10_11[6] , wire_11_7_12_8_remainter , wire_11_06_07_curry , wire_11_07_08_curry );
div_cell cas_11_6 ( ~reg_10_11_curry , two_sc_divisor[6] , reg_10_11[5] , wire_11_6_12_7_remainter , wire_11_05_06_curry , wire_11_06_07_curry );
div_cell cas_11_5 ( ~reg_10_11_curry , two_sc_divisor[5] , reg_10_11[4] , wire_11_5_12_6_remainter , wire_11_04_05_curry , wire_11_05_06_curry );
div_cell cas_11_4 ( ~reg_10_11_curry , two_sc_divisor[4] , reg_10_11[3] , wire_11_4_12_5_remainter , wire_11_03_04_curry , wire_11_04_05_curry );
div_cell cas_11_3 ( ~reg_10_11_curry , two_sc_divisor[3] , reg_10_11[2] , wire_11_3_12_4_remainter , wire_11_02_03_curry , wire_11_03_04_curry );
div_cell cas_11_2 ( ~reg_10_11_curry , two_sc_divisor[2] , reg_10_11[1] , wire_11_2_12_3_remainter , wire_11_01_02_curry , wire_11_02_03_curry );
div_cell cas_11_1 ( ~reg_10_11_curry , two_sc_divisor[1] , reg_10_11[0] , wire_11_1_12_2_remainter , wire_11_00_01_curry , wire_11_01_02_curry );
div_cell cas_11_0 ( ~reg_10_11_curry , two_sc_divisor[0] , two_sc_dividend[5] , wire_11_0_12_1_remainter , ~reg_10_11_curry , wire_11_00_01_curry );
div_cell cas_12_15 ( ~wire_out_quotient[5] , two_sc_divisor[15] , wire_11_14_12_15_remainter , wire_out_quotient[4] , wire_12_14_15_curry , hang_12_wire_15 );
div_cell cas_12_14 ( ~wire_out_quotient[5] , two_sc_divisor[14] , wire_11_13_12_14_remainter , wire_12_14_13_15_remainter , wire_12_13_14_curry , wire_12_14_15_curry );
div_cell cas_12_13 ( ~wire_out_quotient[5] , two_sc_divisor[13] , wire_11_12_12_13_remainter , wire_12_13_13_14_remainter , wire_12_12_13_curry , wire_12_13_14_curry );
div_cell cas_12_12 ( ~wire_out_quotient[5] , two_sc_divisor[12] , wire_11_11_12_12_remainter , wire_12_12_13_13_remainter , wire_12_11_12_curry , wire_12_12_13_curry );
div_cell cas_12_11 ( ~wire_out_quotient[5] , two_sc_divisor[11] , wire_11_10_12_11_remainter , wire_12_11_13_12_remainter , wire_12_10_11_curry , wire_12_11_12_curry );
div_cell cas_12_10 ( ~wire_out_quotient[5] , two_sc_divisor[10] , wire_11_9_12_10_remainter , wire_12_10_13_11_remainter , wire_12_09_10_curry , wire_12_10_11_curry );
div_cell cas_12_9 ( ~wire_out_quotient[5] , two_sc_divisor[9] , wire_11_8_12_9_remainter , wire_12_9_13_10_remainter , wire_12_08_09_curry , wire_12_09_10_curry );
div_cell cas_12_8 ( ~wire_out_quotient[5] , two_sc_divisor[8] , wire_11_7_12_8_remainter , wire_12_8_13_9_remainter , wire_12_07_08_curry , wire_12_08_09_curry );
div_cell cas_12_7 ( ~wire_out_quotient[5] , two_sc_divisor[7] , wire_11_6_12_7_remainter , wire_12_7_13_8_remainter , wire_12_06_07_curry , wire_12_07_08_curry );
div_cell cas_12_6 ( ~wire_out_quotient[5] , two_sc_divisor[6] , wire_11_5_12_6_remainter , wire_12_6_13_7_remainter , wire_12_05_06_curry , wire_12_06_07_curry );
div_cell cas_12_5 ( ~wire_out_quotient[5] , two_sc_divisor[5] , wire_11_4_12_5_remainter , wire_12_5_13_6_remainter , wire_12_04_05_curry , wire_12_05_06_curry );
div_cell cas_12_4 ( ~wire_out_quotient[5] , two_sc_divisor[4] , wire_11_3_12_4_remainter , wire_12_4_13_5_remainter , wire_12_03_04_curry , wire_12_04_05_curry );
div_cell cas_12_3 ( ~wire_out_quotient[5] , two_sc_divisor[3] , wire_11_2_12_3_remainter , wire_12_3_13_4_remainter , wire_12_02_03_curry , wire_12_03_04_curry );
div_cell cas_12_2 ( ~wire_out_quotient[5] , two_sc_divisor[2] , wire_11_1_12_2_remainter , wire_12_2_13_3_remainter , wire_12_01_02_curry , wire_12_02_03_curry );
div_cell cas_12_1 ( ~wire_out_quotient[5] , two_sc_divisor[1] , wire_11_0_12_1_remainter , wire_12_1_13_2_remainter , wire_12_00_01_curry , wire_12_01_02_curry );
div_cell cas_12_0 ( ~wire_out_quotient[5] , two_sc_divisor[0] , two_sc_dividend[4] , wire_12_0_13_1_remainter , ~wire_out_quotient[5] , wire_12_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_12_13 <= 'b0;
reg_12_13_curry <= 'b0;
end else begin
reg_12_13[14] <= wire_12_14_13_15_remainter;
reg_12_13[13] <= wire_12_13_13_14_remainter;
reg_12_13[12] <= wire_12_12_13_13_remainter;
reg_12_13[11] <= wire_12_11_13_12_remainter;
reg_12_13[10] <= wire_12_10_13_11_remainter;
reg_12_13[9] <= wire_12_9_13_10_remainter;
reg_12_13[8] <= wire_12_8_13_9_remainter;
reg_12_13[7] <= wire_12_7_13_8_remainter;
reg_12_13[6] <= wire_12_6_13_7_remainter;
reg_12_13[5] <= wire_12_5_13_6_remainter;
reg_12_13[4] <= wire_12_4_13_5_remainter;
reg_12_13[3] <= wire_12_3_13_4_remainter;
reg_12_13[2] <= wire_12_2_13_3_remainter;
reg_12_13[1] <= wire_12_1_13_2_remainter;
reg_12_13[0] <= wire_12_0_13_1_remainter;
reg_12_13_curry <= wire_out_quotient[4];
end
end
div_cell cas_13_15 ( ~reg_12_13_curry , two_sc_divisor[15] , reg_12_13[14] , wire_out_quotient[3] , wire_13_14_15_curry , hang_13_wire_15 );
div_cell cas_13_14 ( ~reg_12_13_curry , two_sc_divisor[14] ,reg_12_13[13] , wire_13_14_14_15_remainter , wire_13_13_14_curry , wire_13_14_15_curry );
div_cell cas_13_13 ( ~reg_12_13_curry , two_sc_divisor[13] ,reg_12_13[12] , wire_13_13_14_14_remainter , wire_13_12_13_curry , wire_13_13_14_curry );
div_cell cas_13_12 ( ~reg_12_13_curry , two_sc_divisor[12] ,reg_12_13[11] , wire_13_12_14_13_remainter , wire_13_11_12_curry , wire_13_12_13_curry );
div_cell cas_13_11 ( ~reg_12_13_curry , two_sc_divisor[11] ,reg_12_13[10] , wire_13_11_14_12_remainter , wire_13_10_11_curry , wire_13_11_12_curry );
div_cell cas_13_10 ( ~reg_12_13_curry , two_sc_divisor[10] ,reg_12_13[9], wire_13_10_14_11_remainter , wire_13_09_10_curry , wire_13_10_11_curry );
div_cell cas_13_9 ( ~reg_12_13_curry , two_sc_divisor[9] , reg_12_13[8] , wire_13_9_14_10_remainter , wire_13_08_09_curry , wire_13_09_10_curry );
div_cell cas_13_8 ( ~reg_12_13_curry , two_sc_divisor[8] , reg_12_13[7] , wire_13_8_14_9_remainter , wire_13_07_08_curry , wire_13_08_09_curry );
div_cell cas_13_7 ( ~reg_12_13_curry , two_sc_divisor[7] , reg_12_13[6] , wire_13_7_14_8_remainter , wire_13_06_07_curry , wire_13_07_08_curry );
div_cell cas_13_6 ( ~reg_12_13_curry , two_sc_divisor[6] , reg_12_13[5] , wire_13_6_14_7_remainter , wire_13_05_06_curry , wire_13_06_07_curry );
div_cell cas_13_5 ( ~reg_12_13_curry , two_sc_divisor[5] , reg_12_13[4] , wire_13_5_14_6_remainter , wire_13_04_05_curry , wire_13_05_06_curry );
div_cell cas_13_4 ( ~reg_12_13_curry , two_sc_divisor[4] , reg_12_13[3] , wire_13_4_14_5_remainter , wire_13_03_04_curry , wire_13_04_05_curry );
div_cell cas_13_3 ( ~reg_12_13_curry , two_sc_divisor[3] , reg_12_13[2] , wire_13_3_14_4_remainter , wire_13_02_03_curry , wire_13_03_04_curry );
div_cell cas_13_2 ( ~reg_12_13_curry , two_sc_divisor[2] , reg_12_13[1] , wire_13_2_14_3_remainter , wire_13_01_02_curry , wire_13_02_03_curry );
div_cell cas_13_1 ( ~reg_12_13_curry , two_sc_divisor[1] , reg_12_13[0] , wire_13_1_14_2_remainter , wire_13_00_01_curry , wire_13_01_02_curry );
div_cell cas_13_0 ( ~reg_12_13_curry , two_sc_divisor[0] , two_sc_dividend[3] , wire_13_0_14_1_remainter , ~reg_12_13_curry , wire_13_00_01_curry );
div_cell cas_14_15 ( ~wire_out_quotient[3] , two_sc_divisor[15] , wire_13_14_14_15_remainter , wire_out_quotient[2] , wire_14_14_15_curry , hang_14_wire_15 );
div_cell cas_14_14 ( ~wire_out_quotient[3] , two_sc_divisor[14] , wire_13_13_14_14_remainter , wire_14_14_15_15_remainter , wire_14_13_14_curry , wire_14_14_15_curry );
div_cell cas_14_13 ( ~wire_out_quotient[3] , two_sc_divisor[13] , wire_13_12_14_13_remainter , wire_14_13_15_14_remainter , wire_14_12_13_curry , wire_14_13_14_curry );
div_cell cas_14_12 ( ~wire_out_quotient[3] , two_sc_divisor[12] , wire_13_11_14_12_remainter , wire_14_12_15_13_remainter , wire_14_11_12_curry , wire_14_12_13_curry );
div_cell cas_14_11 ( ~wire_out_quotient[3] , two_sc_divisor[11] , wire_13_10_14_11_remainter , wire_14_11_15_12_remainter , wire_14_10_11_curry , wire_14_11_12_curry );
div_cell cas_14_10 ( ~wire_out_quotient[3] , two_sc_divisor[10] , wire_13_9_14_10_remainter , wire_14_10_15_11_remainter , wire_14_09_10_curry , wire_14_10_11_curry );
div_cell cas_14_9 ( ~wire_out_quotient[3] , two_sc_divisor[9] , wire_13_8_14_9_remainter , wire_14_9_15_10_remainter , wire_14_08_09_curry , wire_14_09_10_curry );
div_cell cas_14_8 ( ~wire_out_quotient[3] , two_sc_divisor[8] , wire_13_7_14_8_remainter , wire_14_8_15_9_remainter , wire_14_07_08_curry , wire_14_08_09_curry );
div_cell cas_14_7 ( ~wire_out_quotient[3] , two_sc_divisor[7] , wire_13_6_14_7_remainter , wire_14_7_15_8_remainter , wire_14_06_07_curry , wire_14_07_08_curry );
div_cell cas_14_6 ( ~wire_out_quotient[3] , two_sc_divisor[6] , wire_13_5_14_6_remainter , wire_14_6_15_7_remainter , wire_14_05_06_curry , wire_14_06_07_curry );
div_cell cas_14_5 ( ~wire_out_quotient[3] , two_sc_divisor[5] , wire_13_4_14_5_remainter , wire_14_5_15_6_remainter , wire_14_04_05_curry , wire_14_05_06_curry );
div_cell cas_14_4 ( ~wire_out_quotient[3] , two_sc_divisor[4] , wire_13_3_14_4_remainter , wire_14_4_15_5_remainter , wire_14_03_04_curry , wire_14_04_05_curry );
div_cell cas_14_3 ( ~wire_out_quotient[3] , two_sc_divisor[3] , wire_13_2_14_3_remainter , wire_14_3_15_4_remainter , wire_14_02_03_curry , wire_14_03_04_curry );
div_cell cas_14_2 ( ~wire_out_quotient[3] , two_sc_divisor[2] , wire_13_1_14_2_remainter , wire_14_2_15_3_remainter , wire_14_01_02_curry , wire_14_02_03_curry );
div_cell cas_14_1 ( ~wire_out_quotient[3] , two_sc_divisor[1] , wire_13_0_14_1_remainter , wire_14_1_15_2_remainter , wire_14_00_01_curry , wire_14_01_02_curry );
div_cell cas_14_0 ( ~wire_out_quotient[3] , two_sc_divisor[0] , two_sc_dividend[2] , wire_14_0_15_1_remainter , ~wire_out_quotient[3] , wire_14_00_01_curry );
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_14_15 <= 'b0;
reg_14_15_curry <= 'b0;
end else begin
reg_14_15[14] <= wire_14_14_15_15_remainter;
reg_14_15[13] <= wire_14_13_15_14_remainter;
reg_14_15[12] <= wire_14_12_15_13_remainter;
reg_14_15[11] <= wire_14_11_15_12_remainter;
reg_14_15[10] <= wire_14_10_15_11_remainter;
reg_14_15[9] <= wire_14_9_15_10_remainter;
reg_14_15[8] <= wire_14_8_15_9_remainter;
reg_14_15[7] <= wire_14_7_15_8_remainter;
reg_14_15[6] <= wire_14_6_15_7_remainter;
reg_14_15[5] <= wire_14_5_15_6_remainter;
reg_14_15[4] <= wire_14_4_15_5_remainter;
reg_14_15[3] <= wire_14_3_15_4_remainter;
reg_14_15[2] <= wire_14_2_15_3_remainter;
reg_14_15[1] <= wire_14_1_15_2_remainter;
reg_14_15[0] <= wire_14_0_15_1_remainter;
reg_14_15_curry <= wire_out_quotient[2];
end
end
div_cell cas_15_15 ( ~reg_14_15_curry , two_sc_divisor[15] , reg_14_15[14] , wire_out_quotient[1] , wire_15_14_15_curry , hang_15_wire_15 );
div_cell cas_15_14 ( ~reg_14_15_curry , two_sc_divisor[14] , reg_14_15[13] , wire_15_14_16_15_remainter , wire_15_13_14_curry , wire_15_14_15_curry );
div_cell cas_15_13 ( ~reg_14_15_curry , two_sc_divisor[13] , reg_14_15[12] , wire_15_13_16_14_remainter , wire_15_12_13_curry , wire_15_13_14_curry );
div_cell cas_15_12 ( ~reg_14_15_curry , two_sc_divisor[12] , reg_14_15[11] , wire_15_12_16_13_remainter , wire_15_11_12_curry , wire_15_12_13_curry );
div_cell cas_15_11 ( ~reg_14_15_curry , two_sc_divisor[11] , reg_14_15[10] , wire_15_11_16_12_remainter , wire_15_10_11_curry , wire_15_11_12_curry );
div_cell cas_15_10 ( ~reg_14_15_curry , two_sc_divisor[10] , reg_14_15[9], wire_15_10_16_11_remainter , wire_15_09_10_curry , wire_15_10_11_curry );
div_cell cas_15_9 ( ~reg_14_15_curry , two_sc_divisor[9] , reg_14_15[8] , wire_15_9_16_10_remainter , wire_15_08_09_curry , wire_15_09_10_curry );
div_cell cas_15_8 ( ~reg_14_15_curry , two_sc_divisor[8] , reg_14_15[7] , wire_15_8_16_9_remainter , wire_15_07_08_curry , wire_15_08_09_curry );
div_cell cas_15_7 ( ~reg_14_15_curry , two_sc_divisor[7] , reg_14_15[6] , wire_15_7_16_8_remainter , wire_15_06_07_curry , wire_15_07_08_curry );
div_cell cas_15_6 ( ~reg_14_15_curry , two_sc_divisor[6] , reg_14_15[5] , wire_15_6_16_7_remainter , wire_15_05_06_curry , wire_15_06_07_curry );
div_cell cas_15_5 ( ~reg_14_15_curry , two_sc_divisor[5] , reg_14_15[4] , wire_15_5_16_6_remainter , wire_15_04_05_curry , wire_15_05_06_curry );
div_cell cas_15_4 ( ~reg_14_15_curry , two_sc_divisor[4] , reg_14_15[3] , wire_15_4_16_5_remainter , wire_15_03_04_curry , wire_15_04_05_curry );
div_cell cas_15_3 ( ~reg_14_15_curry , two_sc_divisor[3] , reg_14_15[2] , wire_15_3_16_4_remainter , wire_15_02_03_curry , wire_15_03_04_curry );
div_cell cas_15_2 ( ~reg_14_15_curry , two_sc_divisor[2] , reg_14_15[1] , wire_15_2_16_3_remainter , wire_15_01_02_curry , wire_15_02_03_curry );
div_cell cas_15_1 ( ~reg_14_15_curry , two_sc_divisor[1] , reg_14_15[0] , wire_15_1_16_2_remainter , wire_15_00_01_curry , wire_15_01_02_curry );
div_cell cas_15_0 ( ~reg_14_15_curry , two_sc_divisor[0] , two_sc_dividend[1] , wire_15_0_16_1_remainter , ~reg_14_15_curry , wire_15_00_01_curry );
div_cell cas_16_15 ( ~wire_out_quotient[1] , two_sc_divisor[15] , wire_15_14_16_15_remainter , wire_out_quotient[0] , wire_16_14_15_curry , hang_16_wire_15 );
div_cell cas_16_14 ( ~wire_out_quotient[1] , two_sc_divisor[14] , wire_15_13_16_14_remainter , wire_out_remainder[14] , wire_16_13_14_curry , wire_16_14_15_curry );
div_cell cas_16_13 ( ~wire_out_quotient[1] , two_sc_divisor[13] , wire_15_12_16_13_remainter , wire_out_remainder[13] , wire_16_12_13_curry , wire_16_13_14_curry );
div_cell cas_16_12 ( ~wire_out_quotient[1] , two_sc_divisor[12] , wire_15_11_16_12_remainter , wire_out_remainder[12] , wire_16_11_12_curry , wire_16_12_13_curry );
div_cell cas_16_11 ( ~wire_out_quotient[1] , two_sc_divisor[11] , wire_15_10_16_11_remainter , wire_out_remainder[11] , wire_16_10_11_curry , wire_16_11_12_curry );
div_cell cas_16_10 ( ~wire_out_quotient[1] , two_sc_divisor[10] , wire_15_9_16_10_remainter , wire_out_remainder[10] , wire_16_09_10_curry , wire_16_10_11_curry );
div_cell cas_16_9 ( ~wire_out_quotient[1] , two_sc_divisor[9] , wire_15_8_16_9_remainter , wire_out_remainder[9] , wire_16_08_09_curry , wire_16_09_10_curry );
div_cell cas_16_8 ( ~wire_out_quotient[1] , two_sc_divisor[8] , wire_15_7_16_8_remainter , wire_out_remainder[8] , wire_16_07_08_curry , wire_16_08_09_curry );
div_cell cas_16_7 ( ~wire_out_quotient[1] , two_sc_divisor[7] , wire_15_6_16_7_remainter , wire_out_remainder[7] , wire_16_06_07_curry , wire_16_07_08_curry );
div_cell cas_16_6 ( ~wire_out_quotient[1] , two_sc_divisor[6] , wire_15_5_16_6_remainter , wire_out_remainder[6] , wire_16_05_06_curry , wire_16_06_07_curry );
div_cell cas_16_5 ( ~wire_out_quotient[1] , two_sc_divisor[5] , wire_15_4_16_5_remainter , wire_out_remainder[5] , wire_16_04_05_curry , wire_16_05_06_curry );
div_cell cas_16_4 ( ~wire_out_quotient[1] , two_sc_divisor[4] , wire_15_3_16_4_remainter , wire_out_remainder[4] , wire_16_03_04_curry , wire_16_04_05_curry );
div_cell cas_16_3 ( ~wire_out_quotient[1] , two_sc_divisor[3] , wire_15_2_16_3_remainter , wire_out_remainder[3] , wire_16_02_03_curry , wire_16_03_04_curry );
div_cell cas_16_2 ( ~wire_out_quotient[1] , two_sc_divisor[2] , wire_15_1_16_2_remainter , wire_out_remainder[2] , wire_16_01_02_curry , wire_16_02_03_curry );
div_cell cas_16_1 ( ~wire_out_quotient[1] , two_sc_divisor[1] , wire_15_0_16_1_remainter , wire_out_remainder[1] , wire_16_00_01_curry , wire_16_01_02_curry );
div_cell cas_16_0 ( ~wire_out_quotient[1] , two_sc_divisor[0] , two_sc_dividend[0] , wire_out_remainder[0] , ~wire_out_quotient[1] , wire_16_00_01_curry );
endmodule | 1 |
3,759 | data/full_repos/permissive/106583614/Final_project_mac/MAC_control_unit.v | 106,583,614 | MAC_control_unit.v | v | 170 | 120 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/106583614/Final_project_mac/MAC_control_unit.v:58: Cannot find file containing module: \'MAC_mac_unit\'\n MAC_mac_unit mac_0(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_mac_unit\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_mac_unit.v\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_mac_unit.sv\n MAC_mac_unit\n MAC_mac_unit.v\n MAC_mac_unit.sv\n obj_dir/MAC_mac_unit\n obj_dir/MAC_mac_unit.v\n obj_dir/MAC_mac_unit.sv\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/MAC_control_unit.v:70: Operator COND expects 25 bits on the Conditional False, but Conditional False\'s CONST \'17\'h0\' generates 17 bits.\n : ... In instance MAC_control_unit\n assign final_output = (valid_output) ? mac_output : 17\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,537 | module | module MAC_control_unit(
clk,
reset,
valid_input,
valid_output,
last_input,
num_a,
num_b,
num_c,
num_x,
final_output,
mode
);
input clk, reset;
input valid_input, last_input;
input [7:0] num_a, num_b, num_c, num_x;
input mode;
output reg valid_output;
output signed [24:0] final_output;
reg [1:0] tri_state;
reg [2:0] tri_state_counter;
reg sump_state;
reg sump_state_counter;
wire signed [24:0] mac_output;
reg mul_input_mux, adder_input_mux;
reg [7:0] in_1, in_2, in_add;
parameter IDLE_TRI = 2'b00;
parameter MUL_WITH_INPUT = 2'b01;
parameter MUL_WITH_REG = 2'b10;
parameter IDLE_SUM = 0;
parameter CULCULATE = 1;
MAC_mac_unit mac_0(
.clk(clk) ,
.reset(reset) ,
.in_1(in_1) ,
.in_2(in_2) ,
.in_add(in_add) ,
.mul_input_mux(mul_input_mux) ,
.adder_input_mux(adder_input_mux) ,
.mac_output(mac_output)
);
assign final_output = (valid_output) ? mac_output : 17'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
tri_state <= 'b0;
valid_output <= 'b0;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b0;
in_1 <= 'b0;
in_2 <= 'b0;
in_add <= 'b0;
tri_state_counter <= 'b0;
sump_state <= 'b0;
sump_state_counter <= 'b0;
end else begin
if (mode) begin
case (tri_state)
IDLE_TRI:
begin
valid_output <= 1'b0;
mul_input_mux <= 1'b0;
if ((last_input) && (valid_input) ) begin
in_1 <= num_a;
in_2 <= num_x;
in_add <= num_b;
tri_state <= MUL_WITH_INPUT;
end
end
MUL_WITH_INPUT:
begin
in_1 <= num_a;
in_2 <= num_x;
in_add <= num_b;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b0;
tri_state_counter <= tri_state_counter + 1'b1;
if ((tri_state_counter == 1) ) begin
mul_input_mux <= 1'b1;
tri_state <= MUL_WITH_REG;
end
end
MUL_WITH_REG:
begin
in_add <= num_c;
mul_input_mux <= 1'b1;
tri_state_counter <= tri_state_counter + 1'b1;
if (tri_state_counter == 4) begin
tri_state_counter <= 'b0;
valid_output <= 1'b1;
tri_state <= IDLE_TRI;
end
end
default:
begin
end
endcase
end else begin
case (sump_state)
IDLE_SUM:
begin
valid_output <= 1'b0;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b1;
if ((valid_input) && (last_input)) begin
in_1 <= num_a;
in_2 <= num_x;
sump_state <= CULCULATE;
end
end
CULCULATE:
begin
in_1 <= num_a;
in_2 <= num_x;
sump_state_counter <= sump_state_counter + 1'b1;
if (sump_state_counter == 1) begin
valid_output <= 1'b1;
sump_state_counter <= 0;
sump_state <= IDLE_SUM;
end
end
default:
begin
end
endcase
end
end
end
endmodule | module MAC_control_unit(
clk,
reset,
valid_input,
valid_output,
last_input,
num_a,
num_b,
num_c,
num_x,
final_output,
mode
); |
input clk, reset;
input valid_input, last_input;
input [7:0] num_a, num_b, num_c, num_x;
input mode;
output reg valid_output;
output signed [24:0] final_output;
reg [1:0] tri_state;
reg [2:0] tri_state_counter;
reg sump_state;
reg sump_state_counter;
wire signed [24:0] mac_output;
reg mul_input_mux, adder_input_mux;
reg [7:0] in_1, in_2, in_add;
parameter IDLE_TRI = 2'b00;
parameter MUL_WITH_INPUT = 2'b01;
parameter MUL_WITH_REG = 2'b10;
parameter IDLE_SUM = 0;
parameter CULCULATE = 1;
MAC_mac_unit mac_0(
.clk(clk) ,
.reset(reset) ,
.in_1(in_1) ,
.in_2(in_2) ,
.in_add(in_add) ,
.mul_input_mux(mul_input_mux) ,
.adder_input_mux(adder_input_mux) ,
.mac_output(mac_output)
);
assign final_output = (valid_output) ? mac_output : 17'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
tri_state <= 'b0;
valid_output <= 'b0;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b0;
in_1 <= 'b0;
in_2 <= 'b0;
in_add <= 'b0;
tri_state_counter <= 'b0;
sump_state <= 'b0;
sump_state_counter <= 'b0;
end else begin
if (mode) begin
case (tri_state)
IDLE_TRI:
begin
valid_output <= 1'b0;
mul_input_mux <= 1'b0;
if ((last_input) && (valid_input) ) begin
in_1 <= num_a;
in_2 <= num_x;
in_add <= num_b;
tri_state <= MUL_WITH_INPUT;
end
end
MUL_WITH_INPUT:
begin
in_1 <= num_a;
in_2 <= num_x;
in_add <= num_b;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b0;
tri_state_counter <= tri_state_counter + 1'b1;
if ((tri_state_counter == 1) ) begin
mul_input_mux <= 1'b1;
tri_state <= MUL_WITH_REG;
end
end
MUL_WITH_REG:
begin
in_add <= num_c;
mul_input_mux <= 1'b1;
tri_state_counter <= tri_state_counter + 1'b1;
if (tri_state_counter == 4) begin
tri_state_counter <= 'b0;
valid_output <= 1'b1;
tri_state <= IDLE_TRI;
end
end
default:
begin
end
endcase
end else begin
case (sump_state)
IDLE_SUM:
begin
valid_output <= 1'b0;
mul_input_mux <= 1'b0;
adder_input_mux <= 1'b1;
if ((valid_input) && (last_input)) begin
in_1 <= num_a;
in_2 <= num_x;
sump_state <= CULCULATE;
end
end
CULCULATE:
begin
in_1 <= num_a;
in_2 <= num_x;
sump_state_counter <= sump_state_counter + 1'b1;
if (sump_state_counter == 1) begin
valid_output <= 1'b1;
sump_state_counter <= 0;
sump_state <= IDLE_SUM;
end
end
default:
begin
end
endcase
end
end
end
endmodule | 1 |
3,761 | data/full_repos/permissive/106583614/Final_project_mac/MAC_top_level.v | 106,583,614 | MAC_top_level.v | v | 42 | 105 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/106583614/Final_project_mac/MAC_top_level.v:28: Cannot find file containing module: 'MAC_control_unit'\n MAC_control_unit control_unit_trinomial_sump_0(\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_control_unit\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_control_unit.v\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_control_unit.sv\n MAC_control_unit\n MAC_control_unit.v\n MAC_control_unit.sv\n obj_dir/MAC_control_unit\n obj_dir/MAC_control_unit.v\n obj_dir/MAC_control_unit.sv\n%Error: Exiting due to 1 error(s)\n" | 1,539 | module | module MAC_top_level(
clk,
reset,
valid_input,
valid_output,
last_input,
num_a,
num_b,
num_c,
num_x,
final_output,
mode
);
input clk, reset;
input valid_input, last_input;
input signed [7:0] num_a, num_b, num_c, num_x;
input mode;
output valid_output;
output signed [24:0] final_output;
MAC_control_unit control_unit_trinomial_sump_0(
.clk(clk) ,
.reset(reset) ,
.valid_input(valid_input) ,
.valid_output(valid_output) ,
.last_input(last_input) ,
.num_a(num_a) ,
.num_b(num_b) ,
.num_c(num_c) ,
.num_x(num_x) ,
.final_output(final_output) ,
.mode(mode)
);
endmodule | module MAC_top_level(
clk,
reset,
valid_input,
valid_output,
last_input,
num_a,
num_b,
num_c,
num_x,
final_output,
mode
); |
input clk, reset;
input valid_input, last_input;
input signed [7:0] num_a, num_b, num_c, num_x;
input mode;
output valid_output;
output signed [24:0] final_output;
MAC_control_unit control_unit_trinomial_sump_0(
.clk(clk) ,
.reset(reset) ,
.valid_input(valid_input) ,
.valid_output(valid_output) ,
.last_input(last_input) ,
.num_a(num_a) ,
.num_b(num_b) ,
.num_c(num_c) ,
.num_x(num_x) ,
.final_output(final_output) ,
.mode(mode)
);
endmodule | 1 |
3,762 | data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v | 106,583,614 | tb_Control_unit.v | v | 192 | 110 | [] | [] | [] | null | line:193: before: "wire" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:124: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:152: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:155: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:172: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:189: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n ^\n%Error: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:31: Cannot find file containing module: \'MAC_top_level\'\nMAC_top_level MAC_top_level_0(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level.v\n data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level.sv\n MAC_top_level\n MAC_top_level.v\n MAC_top_level.sv\n obj_dir/MAC_top_level\n obj_dir/MAC_top_level.v\n obj_dir/MAC_top_level.sv\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:51: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'num_b\' generates 8 bits.\n : ... In instance tb_Control_unit\n check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:51: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'num_c\' generates 8 bits.\n : ... In instance tb_Control_unit\n check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:97: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_a_test[2] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:98: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_x_test[2] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:99: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_b_test[2] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:100: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_c_test[2] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:102: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_a_test[3] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:103: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_x_test[3] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:105: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_a_test[4] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:106: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_x_test[4] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:108: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_a_test[5] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_x_test[5] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:111: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_a_test[6] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:112: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance tb_Control_unit\n num_x_test[6] <= $random;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:137: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_a_in = num_a_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:138: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_a = num_a_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:140: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_x_in = num_x_test[tri_test_inputs]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:141: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_x = num_x_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:160: Operator LT expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'tri_test_inputs\' generates 2 bits.\n : ... In instance tb_Control_unit\n for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1\'b1 ) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:165: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_a_in = num_a_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:166: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_a = num_a_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:168: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_x_in = num_x_test[tri_test_inputs];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:169: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n : ... In instance tb_Control_unit\n num_x = num_x_test[tri_test_inputs];\n ^\n%Error: Exiting due to 1 error(s), 31 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,540 | module | module tb_Control_unit;
reg clk;
reg reset;
reg signed [7:0] num_a_in, num_b_in, num_c_in, num_x_in;
reg signed [7:0] num_a, num_x, num_b, num_c;
reg valid_input, last_input;
wire valid_output;
wire signed [24:0] final_output;
reg mode;
reg signed [24:0] check_tri, check_sump;
reg signed [24:0] y_reg;
reg signed [7:0] num_a_test [6:0];
reg signed [7:0] num_x_test [6:0];
reg signed [7:0] num_b_test [2:0];
reg signed [7:0] num_c_test [2:0];
reg [1:0] tri_test_inputs;
reg test_mode;
parameter TEST_TRI = 1'b0;
parameter TEST_SUMP = 1'b1;
MAC_top_level MAC_top_level_0(
.clk(clk) ,
.reset(reset) ,
.valid_input(valid_input) ,
.valid_output(valid_output) ,
.last_input(last_input) ,
.num_a(num_a_in) ,
.num_b(num_b_in) ,
.num_c(num_c_in) ,
.num_x(num_x_in) ,
.final_output(final_output) ,
.mode(mode)
);
always @ (posedge clk or posedge reset) begin
if (reset) begin
check_tri <= 'b0;
end else begin
check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;
end
end
always @(posedge clk or posedge reset) begin
if ((check_tri == final_output) && (mode)) begin
$display ("Success\n");
$display("\tin_1 (a),\tin_2 (x),\tin_add (b),\tin_add (c),\tmac_output, \tideal_out");
$display("\t%d,\t%d,\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in, num_b_in, num_c_in, final_output, check_tri);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
check_sump <= 'b0;
y_reg <= 'b0;
end else begin
#10;
check_sump <= (num_a*num_x) + y_reg;
y_reg <= check_sump;
#10;
end
end
always @(posedge clk or posedge reset) begin
if ((check_sump == final_output) && (!mode)) begin
$display ("Success\n");
$display("\tin_1 (a),\tin_2 (x),\ty (y),\tmac_output, \tideal_out");
$display("\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in,final_output, check_sump);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
num_a_test[0] <= -8'd5;
num_x_test[0] <= -8'd3;
num_b_test[0] <= -8'd2;
num_c_test[0] <= -8'd1;
num_a_test[1] <= 'd127;
num_x_test[1] <= -'d127;
num_b_test[1] <= 'd1;
num_c_test[1] <= 'd50;
num_a_test[2] <= $random;
num_x_test[2] <= $random;
num_b_test[2] <= $random;
num_c_test[2] <= $random;
num_a_test[3] <= $random;
num_x_test[3] <= $random;
num_a_test[4] <= $random;
num_x_test[4] <= $random;
num_a_test[5] <= $random;
num_x_test[5] <= $random;
num_a_test[6] <= $random;
num_x_test[6] <= $random;
end
end
initial begin
clk = 1;
reset = 1;
valid_input = 1'b0;
last_input = 1'b0;
test_mode = TEST_SUMP;
#10;
reset = 0;
case (test_mode)
TEST_TRI:
begin
for (tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1) begin
mode = 'd1;
valid_input = 1'b1;
num_a_in = num_a_test[tri_test_inputs];
num_a = num_a_test[tri_test_inputs];
num_x_in = num_x_test[tri_test_inputs];
num_x = num_x_test[tri_test_inputs];
num_b_in = num_b_test[tri_test_inputs];
num_b = num_b_test[tri_test_inputs];
num_c = num_c_test[tri_test_inputs];
num_c_in = num_c_test[tri_test_inputs];
last_input = 1'b1;
#40;
last_input = 1'b0;
valid_input = 1'b0;
#20;
end
end
TEST_SUMP:
begin
for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1'b1 ) begin
mode = 1'b0;
valid_input = 1'b1;
num_a_in = num_a_test[tri_test_inputs];
num_a = num_a_test[tri_test_inputs];
num_x_in = num_x_test[tri_test_inputs];
num_x = num_x_test[tri_test_inputs];
last_input = 1'b1;
#20;
valid_input = 1'b0;
last_input = 1'b0;
#10;
end
end
default:
begin
end
endcase
$finish;
end
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
endmodule | module tb_Control_unit; |
reg clk;
reg reset;
reg signed [7:0] num_a_in, num_b_in, num_c_in, num_x_in;
reg signed [7:0] num_a, num_x, num_b, num_c;
reg valid_input, last_input;
wire valid_output;
wire signed [24:0] final_output;
reg mode;
reg signed [24:0] check_tri, check_sump;
reg signed [24:0] y_reg;
reg signed [7:0] num_a_test [6:0];
reg signed [7:0] num_x_test [6:0];
reg signed [7:0] num_b_test [2:0];
reg signed [7:0] num_c_test [2:0];
reg [1:0] tri_test_inputs;
reg test_mode;
parameter TEST_TRI = 1'b0;
parameter TEST_SUMP = 1'b1;
MAC_top_level MAC_top_level_0(
.clk(clk) ,
.reset(reset) ,
.valid_input(valid_input) ,
.valid_output(valid_output) ,
.last_input(last_input) ,
.num_a(num_a_in) ,
.num_b(num_b_in) ,
.num_c(num_c_in) ,
.num_x(num_x_in) ,
.final_output(final_output) ,
.mode(mode)
);
always @ (posedge clk or posedge reset) begin
if (reset) begin
check_tri <= 'b0;
end else begin
check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;
end
end
always @(posedge clk or posedge reset) begin
if ((check_tri == final_output) && (mode)) begin
$display ("Success\n");
$display("\tin_1 (a),\tin_2 (x),\tin_add (b),\tin_add (c),\tmac_output, \tideal_out");
$display("\t%d,\t%d,\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in, num_b_in, num_c_in, final_output, check_tri);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
check_sump <= 'b0;
y_reg <= 'b0;
end else begin
#10;
check_sump <= (num_a*num_x) + y_reg;
y_reg <= check_sump;
#10;
end
end
always @(posedge clk or posedge reset) begin
if ((check_sump == final_output) && (!mode)) begin
$display ("Success\n");
$display("\tin_1 (a),\tin_2 (x),\ty (y),\tmac_output, \tideal_out");
$display("\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in,final_output, check_sump);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
num_a_test[0] <= -8'd5;
num_x_test[0] <= -8'd3;
num_b_test[0] <= -8'd2;
num_c_test[0] <= -8'd1;
num_a_test[1] <= 'd127;
num_x_test[1] <= -'d127;
num_b_test[1] <= 'd1;
num_c_test[1] <= 'd50;
num_a_test[2] <= $random;
num_x_test[2] <= $random;
num_b_test[2] <= $random;
num_c_test[2] <= $random;
num_a_test[3] <= $random;
num_x_test[3] <= $random;
num_a_test[4] <= $random;
num_x_test[4] <= $random;
num_a_test[5] <= $random;
num_x_test[5] <= $random;
num_a_test[6] <= $random;
num_x_test[6] <= $random;
end
end
initial begin
clk = 1;
reset = 1;
valid_input = 1'b0;
last_input = 1'b0;
test_mode = TEST_SUMP;
#10;
reset = 0;
case (test_mode)
TEST_TRI:
begin
for (tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1) begin
mode = 'd1;
valid_input = 1'b1;
num_a_in = num_a_test[tri_test_inputs];
num_a = num_a_test[tri_test_inputs];
num_x_in = num_x_test[tri_test_inputs];
num_x = num_x_test[tri_test_inputs];
num_b_in = num_b_test[tri_test_inputs];
num_b = num_b_test[tri_test_inputs];
num_c = num_c_test[tri_test_inputs];
num_c_in = num_c_test[tri_test_inputs];
last_input = 1'b1;
#40;
last_input = 1'b0;
valid_input = 1'b0;
#20;
end
end
TEST_SUMP:
begin
for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1'b1 ) begin
mode = 1'b0;
valid_input = 1'b1;
num_a_in = num_a_test[tri_test_inputs];
num_a = num_a_test[tri_test_inputs];
num_x_in = num_x_test[tri_test_inputs];
num_x = num_x_test[tri_test_inputs];
last_input = 1'b1;
#20;
valid_input = 1'b0;
last_input = 1'b0;
#10;
end
end
default:
begin
end
endcase
$finish;
end
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
endmodule | 1 |
3,764 | data/full_repos/permissive/106583614/Lab1/LEDbtnRModule.v | 106,583,614 | LEDbtnRModule.v | v | 83 | 109 | [] | [] | [] | null | line:83: before: "/" | data/verilator_xmls/e487050b-6e6a-4339-a26e-48815089995b.xml | null | 1,542 | module | module LEDbtnRModule(
clk,
reset,
r_btn,
char_an0,
char_an1,
char_an2,
char_an3
);
parameter N = 16;
input clk, reset, r_btn;
output reg [3:0] char_an0, char_an1, char_an2, char_an3;
reg [3:0]index;
reg inc_flag, first_flag;
reg [3:0] message [N-1:0];
always @(posedge clk or posedge reset ) begin
if (reset)
begin
message[0] <= 4'h0;
message[1] <= 4'h1;
message[2] <= 4'h3;
message[3] <= 4'h4;
message[4] <= 4'h5;
message[5] <= 4'h6;
message[6] <= 4'h7;
message[7] <= 4'h8;
message[8] <= 4'h9;
message[9] <= 4'h0;
message[10] <= 4'ha;
message[11] <= 4'hb;
message[12] <= 4'hc;
message[13] <= 4'hd;
message[14] <= 4'he;
message[15] <= 4'hf;
end
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
index <=0;
char_an3 <= message [index ];
char_an2 <= message [index + 1];
char_an1 <= message [index + 2];
char_an0 <= message [index + 3];
inc_flag <=0;
first_flag <=1;
end else begin
if (r_btn || first_flag)
begin
char_an3 <= message [index ];
char_an2 <= message [index + 1];
char_an1 <= message [index + 2];
char_an0 <= message [index + 3];
first_flag <= 0;
inc_flag <= 1;
end
if (!r_btn & inc_flag)
begin
index <= index + 1;
inc_flag <= 0;
end
end
end
endmodule | module LEDbtnRModule(
clk,
reset,
r_btn,
char_an0,
char_an1,
char_an2,
char_an3
); |
parameter N = 16;
input clk, reset, r_btn;
output reg [3:0] char_an0, char_an1, char_an2, char_an3;
reg [3:0]index;
reg inc_flag, first_flag;
reg [3:0] message [N-1:0];
always @(posedge clk or posedge reset ) begin
if (reset)
begin
message[0] <= 4'h0;
message[1] <= 4'h1;
message[2] <= 4'h3;
message[3] <= 4'h4;
message[4] <= 4'h5;
message[5] <= 4'h6;
message[6] <= 4'h7;
message[7] <= 4'h8;
message[8] <= 4'h9;
message[9] <= 4'h0;
message[10] <= 4'ha;
message[11] <= 4'hb;
message[12] <= 4'hc;
message[13] <= 4'hd;
message[14] <= 4'he;
message[15] <= 4'hf;
end
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
index <=0;
char_an3 <= message [index ];
char_an2 <= message [index + 1];
char_an1 <= message [index + 2];
char_an0 <= message [index + 3];
inc_flag <=0;
first_flag <=1;
end else begin
if (r_btn || first_flag)
begin
char_an3 <= message [index ];
char_an2 <= message [index + 1];
char_an1 <= message [index + 2];
char_an0 <= message [index + 3];
first_flag <= 0;
inc_flag <= 1;
end
if (!r_btn & inc_flag)
begin
index <= index + 1;
inc_flag <= 0;
end
end
end
endmodule | 1 |
3,766 | data/full_repos/permissive/106583614/Lab1/LEDdecoder.v | 106,583,614 | LEDdecoder.v | v | 52 | 30 | [] | [] | [] | null | line:52: before: "/" | data/verilator_xmls/b8cb4610-c916-4ffd-8837-8f86f4472fe8.xml | null | 1,544 | module | module LEDdecoder(
char,
LED
);
input [3:0] char;
output reg [7:0] LED;
always @(char)
begin
case (char)
4'h0: LED = 8'b00000011;
4'h1: LED = 8'b10011111;
4'h2: LED = 8'b00100101;
4'h3: LED = 8'b00001101;
4'h4: LED = 8'b10011001;
4'h5: LED = 8'b01001001;
4'h6: LED = 8'b01000001;
4'h7: LED = 8'b00011111;
4'h8: LED = 8'b00000001;
4'h9: LED = 8'b00001001;
4'ha: LED = 8'b00010001;
4'hb: LED = 8'b11000001;
4'hc: LED = 8'b01100011;
4'hd: LED = 8'b10000101;
4'he: LED = 8'b01100001;
4'hf: LED = 8'b01110001;
default: LED = 8'b11111110;
endcase
end
endmodule | module LEDdecoder(
char,
LED
); |
input [3:0] char;
output reg [7:0] LED;
always @(char)
begin
case (char)
4'h0: LED = 8'b00000011;
4'h1: LED = 8'b10011111;
4'h2: LED = 8'b00100101;
4'h3: LED = 8'b00001101;
4'h4: LED = 8'b10011001;
4'h5: LED = 8'b01001001;
4'h6: LED = 8'b01000001;
4'h7: LED = 8'b00011111;
4'h8: LED = 8'b00000001;
4'h9: LED = 8'b00001001;
4'ha: LED = 8'b00010001;
4'hb: LED = 8'b11000001;
4'hc: LED = 8'b01100011;
4'hd: LED = 8'b10000101;
4'he: LED = 8'b01100001;
4'hf: LED = 8'b01110001;
default: LED = 8'b11111110;
endcase
end
endmodule | 1 |
3,767 | data/full_repos/permissive/106583614/Lab1/LEDfourDigitDriver.v | 106,583,614 | LEDfourDigitDriver.v | v | 69 | 71 | [] | [] | [] | null | line:69: before: "/" | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab1/LEDfourDigitDriver.v:42: Cannot find file containing module: 'LEDdecoder'\n LEDdecoder leddecoder_0(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDdecoder\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDdecoder.v\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDdecoder.sv\n LEDdecoder\n LEDdecoder.v\n LEDdecoder.sv\n obj_dir/LEDdecoder\n obj_dir/LEDdecoder.v\n obj_dir/LEDdecoder.sv\n%Error: data/full_repos/permissive/106583614/Lab1/LEDfourDigitDriver.v:56: Cannot find file containing module: 'LEDstateDriver'\n LEDstateDriver ledStateDriver_0(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,545 | module | module LEDfourDigitDriver(
reset,
clk,
an3,
an2,
an1,
an0,
a,
b,
c,
d,
e,
f,
g,
dp,
r_btn,
Rx_DATA
);
input reset, clk, r_btn;
output wire an3, an2, an1, an0;
output wire a, b, c, d, e, f, g, dp;
input [7:0] Rx_DATA;
wire [3:0] char;
reg [3:0] state;
wire [7:0] LED;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 4'b1111;
end else begin
state <= state - 1'b1;
end
end
LEDdecoder leddecoder_0(
.char(char),
.LED(LED)
);
assign a = LED[7];
assign b = LED[6];
assign c = LED[5];
assign d = LED[4];
assign e = LED[3];
assign f = LED[2];
assign g = LED[1];
assign dp = LED[0];
LEDstateDriver ledStateDriver_0(
.clk(clk),
.reset(reset),
.state_in(state),
.char_out(char),
.an0_out(an0),
.an1_out(an1),
.an2_out(an2),
.an3_out(an3),
.r_btn(r_btn),
.Rx_DATA(Rx_DATA)
);
endmodule | module LEDfourDigitDriver(
reset,
clk,
an3,
an2,
an1,
an0,
a,
b,
c,
d,
e,
f,
g,
dp,
r_btn,
Rx_DATA
); |
input reset, clk, r_btn;
output wire an3, an2, an1, an0;
output wire a, b, c, d, e, f, g, dp;
input [7:0] Rx_DATA;
wire [3:0] char;
reg [3:0] state;
wire [7:0] LED;
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 4'b1111;
end else begin
state <= state - 1'b1;
end
end
LEDdecoder leddecoder_0(
.char(char),
.LED(LED)
);
assign a = LED[7];
assign b = LED[6];
assign c = LED[5];
assign d = LED[4];
assign e = LED[3];
assign f = LED[2];
assign g = LED[1];
assign dp = LED[0];
LEDstateDriver ledStateDriver_0(
.clk(clk),
.reset(reset),
.state_in(state),
.char_out(char),
.an0_out(an0),
.an1_out(an1),
.an2_out(an2),
.an3_out(an3),
.r_btn(r_btn),
.Rx_DATA(Rx_DATA)
);
endmodule | 1 |
3,769 | data/full_repos/permissive/106583614/Lab1/LEDstateDriver.v | 106,583,614 | LEDstateDriver.v | v | 235 | 80 | [] | [] | [] | [(4, 234)] | null | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab1/LEDstateDriver.v:37: Cannot find file containing module: 'LEDbtnRModule'\n LEDbtnRModule led_r_btn_0(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDbtnRModule\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDbtnRModule.v\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDbtnRModule.sv\n LEDbtnRModule\n LEDbtnRModule.v\n LEDbtnRModule.sv\n obj_dir/LEDbtnRModule\n obj_dir/LEDbtnRModule.v\n obj_dir/LEDbtnRModule.sv\n%Error: Exiting due to 1 error(s)\n" | 1,548 | module | module LEDstateDriver(
clk,
reset,
state_in,
char_out,
an0_out,
an1_out,
an2_out,
an3_out,
r_btn,
Rx_DATA
);
input [3:0] state_in;
input clk, reset;
input r_btn;
input [7:0] Rx_DATA;
output reg [3:0] char_out;
output reg an3_out, an2_out, an1_out, an0_out;
wire [3:0] char_an0, char_an1, char_an2, char_an3;
LEDbtnRModule led_r_btn_0(
.clk(clk),
.reset(reset),
.r_btn(r_btn),
.char_an0(char_an0),
.char_an1(char_an1),
.char_an2(char_an2),
.char_an3(char_an3)
);
always @ ( state_in or char_an0 or char_an1 or char_an2 or char_an3)
begin
case (state_in)
4'b0000:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0001:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0010:
begin
an0_out = 0;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0011:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0100:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0101:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0110:
begin
an0_out = 1;
an1_out = 0;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0111:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1000:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1001:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1010:
begin
an0_out = 1;
an1_out = 1;
an2_out = 0;
an3_out = 1;
char_out = char_an2;
end
4'b1011:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1100:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1101:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1110:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 0;
char_out = char_an3;
end
4'b1111:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
default:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
end
endcase
end
endmodule | module LEDstateDriver(
clk,
reset,
state_in,
char_out,
an0_out,
an1_out,
an2_out,
an3_out,
r_btn,
Rx_DATA
); |
input [3:0] state_in;
input clk, reset;
input r_btn;
input [7:0] Rx_DATA;
output reg [3:0] char_out;
output reg an3_out, an2_out, an1_out, an0_out;
wire [3:0] char_an0, char_an1, char_an2, char_an3;
LEDbtnRModule led_r_btn_0(
.clk(clk),
.reset(reset),
.r_btn(r_btn),
.char_an0(char_an0),
.char_an1(char_an1),
.char_an2(char_an2),
.char_an3(char_an3)
);
always @ ( state_in or char_an0 or char_an1 or char_an2 or char_an3)
begin
case (state_in)
4'b0000:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0001:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0010:
begin
an0_out = 0;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
4'b0011:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0100:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0101:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0110:
begin
an0_out = 1;
an1_out = 0;
an2_out = 1;
an3_out = 1;
char_out = char_an1;
end
4'b0111:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1000:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1001:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an2;
end
4'b1010:
begin
an0_out = 1;
an1_out = 1;
an2_out = 0;
an3_out = 1;
char_out = char_an2;
end
4'b1011:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1100:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1101:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an3;
end
4'b1110:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 0;
char_out = char_an3;
end
4'b1111:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
char_out = char_an0;
end
default:
begin
an0_out = 1;
an1_out = 1;
an2_out = 1;
an3_out = 1;
end
endcase
end
endmodule | 1 |
3,771 | data/full_repos/permissive/106583614/Lab1/LEDtb.v | 106,583,614 | LEDtb.v | v | 45 | 30 | [] | [] | [] | null | line:39: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/106583614/Lab1/LEDtb.v:12: Cannot find file containing module: \'LEDsystem\'\nLEDsystem sys0\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem.v\n data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem.sv\n LEDsystem\n LEDsystem.v\n LEDsystem.sv\n obj_dir/LEDsystem\n obj_dir/LEDsystem.v\n obj_dir/LEDsystem.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,550 | module | module tb_LEDsystem;
reg clk;
reg rst_p;
wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;
LEDsystem sys0
(
.reset (rst_p),
.clk (clk),
.an3(an3),
.an2(an2),
.an1(an1),
.an0(an0),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp)
);
always #10 clk=~clk;
initial begin
rst_p = 1'b1;
clk = 1'b1;
#10
rst_p = 1'b0;
#1000
$finish;
end
endmodule | module tb_LEDsystem; |
reg clk;
reg rst_p;
wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;
LEDsystem sys0
(
.reset (rst_p),
.clk (clk),
.an3(an3),
.an2(an2),
.an1(an1),
.an0(an0),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp)
);
always #10 clk=~clk;
initial begin
rst_p = 1'b1;
clk = 1'b1;
#10
rst_p = 1'b0;
#1000
$finish;
end
endmodule | 1 |
3,774 | data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v | 106,583,614 | UARTBaudController_tb.v | v | 35 | 38 | [] | [] | [] | null | line:35 column:2: Illegal character '`' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:10: Cannot find file containing module: \'UARTBaudController\'\nUARTBaudController uart_controller_0 \n^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.v\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.sv\n UARTBaudController\n UARTBaudController.v\n UARTBaudController.sv\n obj_dir/UARTBaudController\n obj_dir/UARTBaudController.v\n obj_dir/UARTBaudController.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,553 | module | module tb_UARTBaudController;
reg clk;
reg rst_n;
reg [2:0] baud_in;
wire mod_en;
UARTBaudController uart_controller_0
(
.clk (clk),
.reset (rst_n),
.baud_select (baud_in),
.sample_enable (mod_en)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
initial
begin
clk = 1;
rst_n = 1;
#10;
rst_n = 0;
baud_in = 3'b101;
#1000;
end
endmodule | module tb_UARTBaudController; |
reg clk;
reg rst_n;
reg [2:0] baud_in;
wire mod_en;
UARTBaudController uart_controller_0
(
.clk (clk),
.reset (rst_n),
.baud_select (baud_in),
.sample_enable (mod_en)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
initial
begin
clk = 1;
rst_n = 1;
#10;
rst_n = 0;
baud_in = 3'b101;
#1000;
end
endmodule | 1 |
3,775 | data/full_repos/permissive/106583614/Lab2/UARTReciver.v | 106,583,614 | UARTReciver.v | v | 266 | 87 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab2/UARTReciver.v:47: Cannot find file containing module: 'UARTBaudController'\n UARTBaudController baud_controller_0(\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.v\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.sv\n UARTBaudController\n UARTBaudController.v\n UARTBaudController.sv\n obj_dir/UARTBaudController\n obj_dir/UARTBaudController.v\n obj_dir/UARTBaudController.sv\n%Error: Exiting due to 1 error(s)\n" | 1,554 | module | module UARTReciver(
clk,
reset,
baud_select,
Rx_EN,
Rx_PERROR,
Rx_FERROR,
Rx_DATA,
Rx_VALID,
Rx_D
);
parameter IDLE = 2'b00;
parameter RECEIVING = 2'b01;
parameter ERROR_CHECK = 2'b10;
input clk, reset;
input [2:0] baud_select;
input Rx_EN, Rx_D;
reg Rx_D_1st, Rx_D_2nd;
output reg Rx_PERROR, Rx_FERROR, Rx_VALID;
output reg [7:0] Rx_DATA;
wire baud_enable;
reg [1:0] state, next_state;
reg [10:0] data_to_check;
wire parity_to_check;
reg start_reciving_flag, error_check_flag;
reg data_prossecing_done, data_recived_flag;
reg f_error_flag;
reg [3:0] index;
reg [3:0] trans_counter;
UARTBaudController baud_controller_0(
.clk(clk),
.reset(reset),
.baud_select(baud_select),
.sample_enable(baud_enable)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_D_1st <= 1;
end else begin
Rx_D_1st <= Rx_D;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_D_2nd <= 1;
end else begin
Rx_D_2nd <= Rx_D_1st;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
case (state)
IDLE:
begin
if (Rx_D_2nd) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
error_check_flag <= 0;
start_reciving_flag <= 1;
next_state <= RECEIVING;
end
end
RECEIVING:
begin
if (data_recived_flag) begin
start_reciving_flag <= 0;
error_check_flag <= 1;
next_state <= ERROR_CHECK;
end else begin
start_reciving_flag <= 1;
error_check_flag <= 0;
next_state <= RECEIVING;
end
end
ERROR_CHECK:
begin
if (data_prossecing_done) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= ERROR_CHECK;
end
end
2'b11:
begin
error_check_flag <= 0;
start_reciving_flag <= 0;
next_state <= IDLE;
end
default:
begin
error_check_flag <= 0;
start_reciving_flag <= 0;
next_state <= IDLE;
end
endcase
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state ;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
index <= 0;
data_recived_flag <= 0;
trans_counter <= 0;
f_error_flag <= 0;
end else begin
if (!Rx_EN) begin
index <= 0;
data_recived_flag <= 0;
end else begin
if (!start_reciving_flag) begin
index <= 0;
if (data_prossecing_done) begin
f_error_flag <= 0;
end
data_recived_flag <= 0;
end else begin
if (baud_enable) begin
if (trans_counter == 15) begin
index <= index + 1;
trans_counter <= 0;
end else begin
trans_counter <= trans_counter + 1;
end
if (index == 0 && Rx_D_2nd) begin
f_error_flag <= 1;
end
if ((index == 10) && (~Rx_D_2nd)) begin
f_error_flag <= 1;
end
data_to_check[index] <= Rx_D_2nd;
if (index == 11) begin
data_recived_flag <= 1;
end else begin
data_recived_flag <= 0;
end
end
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_DATA <= 8'b000000000;
end else begin
Rx_DATA[7] <= data_to_check[8];
Rx_DATA[6] <= data_to_check[7];
Rx_DATA[5] <= data_to_check[6];
Rx_DATA[4] <= data_to_check[5];
Rx_DATA[3] <= data_to_check[4];
Rx_DATA[2] <= data_to_check[3];
Rx_DATA[1] <= data_to_check[2];
Rx_DATA[0] <= data_to_check[1];
end
end
assign parity_to_check = ^Rx_DATA;
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_FERROR <= 0;
Rx_PERROR <= 0;
Rx_VALID <= 0;
data_prossecing_done <= 0;
end else begin
if (!error_check_flag) begin
Rx_FERROR <= 0;
Rx_PERROR <= 0;
Rx_VALID <= 0;
data_prossecing_done <= 0;
end else begin
if (f_error_flag) begin
Rx_VALID <= 0;
Rx_FERROR <= 1;
data_prossecing_done <= 1;
end else if (data_to_check[9] != parity_to_check) begin
Rx_VALID <= 0;
Rx_PERROR <= 1;
data_prossecing_done <= 1;
end else begin
Rx_VALID <= 1;
Rx_FERROR <= 0;
Rx_PERROR <= 0;
data_prossecing_done <= 1;
end
end
end
end
endmodule | module UARTReciver(
clk,
reset,
baud_select,
Rx_EN,
Rx_PERROR,
Rx_FERROR,
Rx_DATA,
Rx_VALID,
Rx_D
); |
parameter IDLE = 2'b00;
parameter RECEIVING = 2'b01;
parameter ERROR_CHECK = 2'b10;
input clk, reset;
input [2:0] baud_select;
input Rx_EN, Rx_D;
reg Rx_D_1st, Rx_D_2nd;
output reg Rx_PERROR, Rx_FERROR, Rx_VALID;
output reg [7:0] Rx_DATA;
wire baud_enable;
reg [1:0] state, next_state;
reg [10:0] data_to_check;
wire parity_to_check;
reg start_reciving_flag, error_check_flag;
reg data_prossecing_done, data_recived_flag;
reg f_error_flag;
reg [3:0] index;
reg [3:0] trans_counter;
UARTBaudController baud_controller_0(
.clk(clk),
.reset(reset),
.baud_select(baud_select),
.sample_enable(baud_enable)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_D_1st <= 1;
end else begin
Rx_D_1st <= Rx_D;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_D_2nd <= 1;
end else begin
Rx_D_2nd <= Rx_D_1st;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
case (state)
IDLE:
begin
if (Rx_D_2nd) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
error_check_flag <= 0;
start_reciving_flag <= 1;
next_state <= RECEIVING;
end
end
RECEIVING:
begin
if (data_recived_flag) begin
start_reciving_flag <= 0;
error_check_flag <= 1;
next_state <= ERROR_CHECK;
end else begin
start_reciving_flag <= 1;
error_check_flag <= 0;
next_state <= RECEIVING;
end
end
ERROR_CHECK:
begin
if (data_prossecing_done) begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= IDLE;
end else begin
start_reciving_flag <= 0;
error_check_flag <= 0;
next_state <= ERROR_CHECK;
end
end
2'b11:
begin
error_check_flag <= 0;
start_reciving_flag <= 0;
next_state <= IDLE;
end
default:
begin
error_check_flag <= 0;
start_reciving_flag <= 0;
next_state <= IDLE;
end
endcase
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state ;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
index <= 0;
data_recived_flag <= 0;
trans_counter <= 0;
f_error_flag <= 0;
end else begin
if (!Rx_EN) begin
index <= 0;
data_recived_flag <= 0;
end else begin
if (!start_reciving_flag) begin
index <= 0;
if (data_prossecing_done) begin
f_error_flag <= 0;
end
data_recived_flag <= 0;
end else begin
if (baud_enable) begin
if (trans_counter == 15) begin
index <= index + 1;
trans_counter <= 0;
end else begin
trans_counter <= trans_counter + 1;
end
if (index == 0 && Rx_D_2nd) begin
f_error_flag <= 1;
end
if ((index == 10) && (~Rx_D_2nd)) begin
f_error_flag <= 1;
end
data_to_check[index] <= Rx_D_2nd;
if (index == 11) begin
data_recived_flag <= 1;
end else begin
data_recived_flag <= 0;
end
end
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_DATA <= 8'b000000000;
end else begin
Rx_DATA[7] <= data_to_check[8];
Rx_DATA[6] <= data_to_check[7];
Rx_DATA[5] <= data_to_check[6];
Rx_DATA[4] <= data_to_check[5];
Rx_DATA[3] <= data_to_check[4];
Rx_DATA[2] <= data_to_check[3];
Rx_DATA[1] <= data_to_check[2];
Rx_DATA[0] <= data_to_check[1];
end
end
assign parity_to_check = ^Rx_DATA;
always @(posedge clk or posedge reset) begin
if (reset) begin
Rx_FERROR <= 0;
Rx_PERROR <= 0;
Rx_VALID <= 0;
data_prossecing_done <= 0;
end else begin
if (!error_check_flag) begin
Rx_FERROR <= 0;
Rx_PERROR <= 0;
Rx_VALID <= 0;
data_prossecing_done <= 0;
end else begin
if (f_error_flag) begin
Rx_VALID <= 0;
Rx_FERROR <= 1;
data_prossecing_done <= 1;
end else if (data_to_check[9] != parity_to_check) begin
Rx_VALID <= 0;
Rx_PERROR <= 1;
data_prossecing_done <= 1;
end else begin
Rx_VALID <= 1;
Rx_FERROR <= 0;
Rx_PERROR <= 0;
data_prossecing_done <= 1;
end
end
end
end
endmodule | 1 |
3,779 | data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v | 106,583,614 | UARTSystem_tb.v | v | 84 | 63 | [] | [] | [] | null | line:84 column:2: Illegal character '`' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD_2/2) clk_2=~clk_2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #1000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:21: Cannot find file containing module: \'UARTTransmeter\'\nUARTTransmeter uart_transmeter_0(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.v\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.sv\n UARTTransmeter\n UARTTransmeter.v\n UARTTransmeter.sv\n obj_dir/UARTTransmeter\n obj_dir/UARTTransmeter.v\n obj_dir/UARTTransmeter.sv\n%Error: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:32: Cannot find file containing module: \'UARTReciver\'\nUARTReciver uart_reciver_0(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,561 | module | module UARTSystem_tb;
reg clk;
reg clk_2;
reg rst_n;
reg [2:0] baud_in;
reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;
reg Rx_EN;
wire Rx_PERROR, Rx_FERROR, Rx_VALID;
wire [7:0] Rx_DATA;
wire Tx_BUSY, Tx_D;
UARTTransmeter uart_transmeter_0(
.clk(clk) ,
.reset(rst_n) ,
.Tx_DATA(Tx_DATA) ,
.baud_select(baud_in) ,
.Tx_WR(Tx_WR) ,
.Tx_EN(Tx_EN) ,
.Tx_D(Tx_D) ,
.Tx_BUSY(Tx_BUSY)
);
UARTReciver uart_reciver_0(
.clk(clk_2) ,
.reset(rst_n) ,
.baud_select(baud_in) ,
.Rx_EN(Rx_EN) ,
.Rx_PERROR(Rx_PERROR) ,
.Rx_FERROR(Rx_FERROR) ,
.Rx_DATA(Rx_DATA) ,
.Rx_VALID(Rx_VALID) ,
.Rx_D (Tx_D)
);
localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;
localparam CLK_PERIOD_2 = 20;
always #(CLK_PERIOD_2/2) clk_2=~clk_2;
initial
begin
clk = 1;
clk_2 = 1;
Tx_EN = 1;
Rx_EN = 1;
Tx_DATA = 8'b11111110;
Tx_WR = 0;
rst_n = 1;
#10;
Tx_WR = 1;
rst_n = 0;
#10;
baud_in = 3'b111;
#100;
#10;
Tx_WR = 0;
#1000000;
Tx_DATA = 8'b10111010;
Tx_WR = 1;
#20;
Tx_WR = 0;
$finish;
end
endmodule | module UARTSystem_tb; |
reg clk;
reg clk_2;
reg rst_n;
reg [2:0] baud_in;
reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;
reg Rx_EN;
wire Rx_PERROR, Rx_FERROR, Rx_VALID;
wire [7:0] Rx_DATA;
wire Tx_BUSY, Tx_D;
UARTTransmeter uart_transmeter_0(
.clk(clk) ,
.reset(rst_n) ,
.Tx_DATA(Tx_DATA) ,
.baud_select(baud_in) ,
.Tx_WR(Tx_WR) ,
.Tx_EN(Tx_EN) ,
.Tx_D(Tx_D) ,
.Tx_BUSY(Tx_BUSY)
);
UARTReciver uart_reciver_0(
.clk(clk_2) ,
.reset(rst_n) ,
.baud_select(baud_in) ,
.Rx_EN(Rx_EN) ,
.Rx_PERROR(Rx_PERROR) ,
.Rx_FERROR(Rx_FERROR) ,
.Rx_DATA(Rx_DATA) ,
.Rx_VALID(Rx_VALID) ,
.Rx_D (Tx_D)
);
localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;
localparam CLK_PERIOD_2 = 20;
always #(CLK_PERIOD_2/2) clk_2=~clk_2;
initial
begin
clk = 1;
clk_2 = 1;
Tx_EN = 1;
Rx_EN = 1;
Tx_DATA = 8'b11111110;
Tx_WR = 0;
rst_n = 1;
#10;
Tx_WR = 1;
rst_n = 0;
#10;
baud_in = 3'b111;
#100;
#10;
Tx_WR = 0;
#1000000;
Tx_DATA = 8'b10111010;
Tx_WR = 1;
#20;
Tx_WR = 0;
$finish;
end
endmodule | 1 |
3,780 | data/full_repos/permissive/106583614/Lab2/UARTTransmeter.v | 106,583,614 | UARTTransmeter.v | v | 176 | 91 | [] | [] | [] | null | line:176: before: "/" | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab2/UARTTransmeter.v:39: Cannot find file containing module: 'UARTBaudController'\n UARTBaudController baud_controller_0(\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.v\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.sv\n UARTBaudController\n UARTBaudController.v\n UARTBaudController.sv\n obj_dir/UARTBaudController\n obj_dir/UARTBaudController.v\n obj_dir/UARTBaudController.sv\n%Error: Exiting due to 1 error(s)\n" | 1,562 | module | module UARTTransmeter(
clk,
reset,
Tx_DATA,
baud_select,
Tx_WR,
Tx_EN,
Tx_D,
Tx_BUSY
);
parameter IDLE = 1'b0;
parameter TRANSMITTING = 1'b1;
input clk, reset;
input Tx_EN, Tx_WR;
input [2:0] baud_select;
input [7:0] Tx_DATA;
output reg Tx_BUSY, Tx_D;
wire baud_enable;
reg trans_en;
reg [3:0] baud_count;
reg [10:0] data_to_send;
reg state;
reg next_state;
reg [3:0] index;
reg char_to_send, data_transmitting_done;
UARTBaudController baud_controller_0(
.clk(clk),
.reset(reset),
.baud_select(baud_select),
.sample_enable(baud_enable)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
data_to_send <= 11'b1;
end else begin
if (Tx_WR) begin
data_to_send[10] <= 1;
data_to_send[9] <= ^Tx_DATA ;
data_to_send[8] <= Tx_DATA[7];
data_to_send[7] <= Tx_DATA[6];
data_to_send[6] <= Tx_DATA[5];
data_to_send[5] <= Tx_DATA[4];
data_to_send[4] <= Tx_DATA[3];
data_to_send[3] <= Tx_DATA[2];
data_to_send[2] <= Tx_DATA[1];
data_to_send[1] <= Tx_DATA[0];
data_to_send[0] <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
baud_count <= 0;
trans_en <= 0;
end else begin
if (!Tx_EN) begin
baud_count <= 0;
trans_en <= 0;
end else begin
if (baud_enable) begin
baud_count <= baud_count + 1;
trans_en <= 0;
if (baud_count == 15) begin
trans_en <= 1;
baud_count <= 0;
end
end else begin
if (baud_count == 0) begin
trans_en <= 0;
end
end
end
end
end
always @(state or Tx_WR or char_to_send or data_transmitting_done or Tx_BUSY) begin
case (state)
IDLE:
begin
if (!Tx_WR) begin
Tx_BUSY <= 0;
Tx_D <= 1;
next_state <= IDLE;
end else begin
Tx_BUSY <= 1;
Tx_D <= 1;
next_state <= TRANSMITTING;
end
end
TRANSMITTING:
begin
if (data_transmitting_done) begin
next_state <= IDLE;
Tx_D <= 1;
Tx_BUSY <= 0;
end else begin
Tx_BUSY <= 1;
Tx_D <= char_to_send;
next_state <= TRANSMITTING;
end
end
default:
begin
Tx_BUSY <= 0;
Tx_D <= 1;
next_state <= IDLE;
end
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
char_to_send <= 1;
index <= 0;
data_transmitting_done <= 0;
end else begin
if (!Tx_BUSY) begin
char_to_send <= 1;
index <= 0;
data_transmitting_done <= 0;
end else begin
if (trans_en) begin
char_to_send <= data_to_send[index];
index <= index + 1;
data_transmitting_done <= 0;
end else begin
if (index == 11) begin
data_transmitting_done <= 1;
index <= 0;
end else begin
data_transmitting_done <= 0;
end
end
end
end
end
endmodule | module UARTTransmeter(
clk,
reset,
Tx_DATA,
baud_select,
Tx_WR,
Tx_EN,
Tx_D,
Tx_BUSY
); |
parameter IDLE = 1'b0;
parameter TRANSMITTING = 1'b1;
input clk, reset;
input Tx_EN, Tx_WR;
input [2:0] baud_select;
input [7:0] Tx_DATA;
output reg Tx_BUSY, Tx_D;
wire baud_enable;
reg trans_en;
reg [3:0] baud_count;
reg [10:0] data_to_send;
reg state;
reg next_state;
reg [3:0] index;
reg char_to_send, data_transmitting_done;
UARTBaudController baud_controller_0(
.clk(clk),
.reset(reset),
.baud_select(baud_select),
.sample_enable(baud_enable)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
data_to_send <= 11'b1;
end else begin
if (Tx_WR) begin
data_to_send[10] <= 1;
data_to_send[9] <= ^Tx_DATA ;
data_to_send[8] <= Tx_DATA[7];
data_to_send[7] <= Tx_DATA[6];
data_to_send[6] <= Tx_DATA[5];
data_to_send[5] <= Tx_DATA[4];
data_to_send[4] <= Tx_DATA[3];
data_to_send[3] <= Tx_DATA[2];
data_to_send[2] <= Tx_DATA[1];
data_to_send[1] <= Tx_DATA[0];
data_to_send[0] <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
baud_count <= 0;
trans_en <= 0;
end else begin
if (!Tx_EN) begin
baud_count <= 0;
trans_en <= 0;
end else begin
if (baud_enable) begin
baud_count <= baud_count + 1;
trans_en <= 0;
if (baud_count == 15) begin
trans_en <= 1;
baud_count <= 0;
end
end else begin
if (baud_count == 0) begin
trans_en <= 0;
end
end
end
end
end
always @(state or Tx_WR or char_to_send or data_transmitting_done or Tx_BUSY) begin
case (state)
IDLE:
begin
if (!Tx_WR) begin
Tx_BUSY <= 0;
Tx_D <= 1;
next_state <= IDLE;
end else begin
Tx_BUSY <= 1;
Tx_D <= 1;
next_state <= TRANSMITTING;
end
end
TRANSMITTING:
begin
if (data_transmitting_done) begin
next_state <= IDLE;
Tx_D <= 1;
Tx_BUSY <= 0;
end else begin
Tx_BUSY <= 1;
Tx_D <= char_to_send;
next_state <= TRANSMITTING;
end
end
default:
begin
Tx_BUSY <= 0;
Tx_D <= 1;
next_state <= IDLE;
end
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
char_to_send <= 1;
index <= 0;
data_transmitting_done <= 0;
end else begin
if (!Tx_BUSY) begin
char_to_send <= 1;
index <= 0;
data_transmitting_done <= 0;
end else begin
if (trans_en) begin
char_to_send <= data_to_send[index];
index <= index + 1;
data_transmitting_done <= 0;
end else begin
if (index == 11) begin
data_transmitting_done <= 1;
index <= 0;
end else begin
data_transmitting_done <= 0;
end
end
end
end
end
endmodule | 1 |
3,781 | data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v | 106,583,614 | UARTTransmeter_tb.v | v | 62 | 36 | [] | [] | [] | null | line:45: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100000;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:14: Cannot find file containing module: \'UARTTransmeter\'\n UARTTransmeter uart_transmitter_0(\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.v\n data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.sv\n UARTTransmeter\n UARTTransmeter.v\n UARTTransmeter.sv\n obj_dir/UARTTransmeter\n obj_dir/UARTTransmeter.v\n obj_dir/UARTTransmeter.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,563 | module | module UARTTransmeter_tb;
reg clk;
reg rst_n;
reg [2:0] baud_in;
reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;
wire Tx_BUSY, Tx_D;
UARTTransmeter uart_transmitter_0(
.clk(clk) ,
.reset(rst_n) ,
.Tx_DATA(Tx_DATA) ,
.baud_select(baud_in) ,
.Tx_WR(Tx_WR) ,
.Tx_EN(Tx_EN) ,
.Tx_D(Tx_D) ,
.Tx_BUSY(Tx_BUSY)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
initial
begin
clk = 1;
Tx_EN = 0;
baud_in = 3'b111;
Tx_WR = 0;
rst_n = 1;
#10;
rst_n = 0;
Tx_DATA = 8'b00001111;
Tx_WR = 1;
#10;
Tx_WR = 0;
Tx_EN = 1;
#10
#100000
Tx_WR = 1;
Tx_DATA = 8'b11101010;
#10;
Tx_WR = 0;
#100;
#100000;
Tx_WR = 0;
$finish;
end
endmodule | module UARTTransmeter_tb; |
reg clk;
reg rst_n;
reg [2:0] baud_in;
reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;
wire Tx_BUSY, Tx_D;
UARTTransmeter uart_transmitter_0(
.clk(clk) ,
.reset(rst_n) ,
.Tx_DATA(Tx_DATA) ,
.baud_select(baud_in) ,
.Tx_WR(Tx_WR) ,
.Tx_EN(Tx_EN) ,
.Tx_D(Tx_D) ,
.Tx_BUSY(Tx_BUSY)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
initial
begin
clk = 1;
Tx_EN = 0;
baud_in = 3'b111;
Tx_WR = 0;
rst_n = 1;
#10;
rst_n = 0;
Tx_DATA = 8'b00001111;
Tx_WR = 1;
#10;
Tx_WR = 0;
Tx_EN = 1;
#10
#100000
Tx_WR = 1;
Tx_DATA = 8'b11101010;
#10;
Tx_WR = 0;
#100;
#100000;
Tx_WR = 0;
$finish;
end
endmodule | 1 |
3,783 | data/full_repos/permissive/106583614/Lab3/VGAHsync_back_up.v | 106,583,614 | VGAHsync_back_up.v | v | 151 | 70 | [] | [] | [] | null | line:151: before: "/" | null | 1: b'%Error: data/full_repos/permissive/106583614/Lab3/VGAHsync_back_up.v:42: Cannot find file containing module: \'VGAMemory\'\n VGAMemory vga_vram_0(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.v\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.sv\n VGAMemory\n VGAMemory.v\n VGAMemory.sv\n obj_dir/VGAMemory\n obj_dir/VGAMemory.v\n obj_dir/VGAMemory.sv\n%Warning-WIDTH: data/full_repos/permissive/106583614/Lab3/VGAHsync_back_up.v:140: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n : ... In instance VGAHsync\n vga_red <= port_a_b_data_red[pixel_counter];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/106583614/Lab3/VGAHsync_back_up.v:141: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n : ... In instance VGAHsync\n vga_green <= port_a_b_data_green[pixel_counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Lab3/VGAHsync_back_up.v:142: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n : ... In instance VGAHsync\n vga_blue <= port_a_b_data_blue[pixel_counter];\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 1,565 | module | module VGAHsync(
clk,
clk_d,
reset,
h_sync,
vga_red,
vga_green,
vga_blue,
h_sync_en
);
input clk, reset;
input h_sync_en;
input clk_d;
output reg h_sync;
output reg vga_red, vga_green, vga_blue;
reg [63:0] port_a_b_data_red;
reg [63:0] port_a_b_data_green;
reg [63:0] port_a_b_data_blue;
wire [31:0] port_a_red_data;
wire [31:0] port_b_red_data;
wire [31:0] port_a_green_data;
wire [31:0] port_b_green_data;
wire [31:0] port_a_blue_data;
wire [31:0] port_b_blue_data;
reg [13:0] port_a_addr, port_b_addr;
reg [11:0] master_hsync_count;
reg [6:0] pixel_counter;
reg [2:0] pixel_scale_count;
reg [1:0]line_comp_counter;
reg display_time_en;
VGAMemory vga_vram_0(
.reset (reset),
.clk (clk),
.pixel_addr_a(port_a_addr),
.pixel_addr_b(port_b_addr),
.red_out_p1 (port_a_red_data),
.green_out_p1 (port_a_green_data),
.blue_out_p1 (port_a_blue_data) ,
.red_out_p2 (port_b_red_data),
.green_out_p2 (port_b_green_data),
.blue_out_p2 (port_b_blue_data)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
h_sync <= 1;
master_hsync_count <= 0;
display_time_en <= 0;
end else begin
if (!h_sync_en) begin
h_sync <= 1;
master_hsync_count <= 0;
display_time_en <= 0;
end else begin
if (master_hsync_count == 0) begin
h_sync <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 192) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 287) begin
h_sync <= 1;
display_time_en <= 1;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 1567) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 1599) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= 0;
end else begin
master_hsync_count <= master_hsync_count + 1;
end
end
end
end
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
port_a_addr <= 'h0000;
port_b_addr <= 'h0020;
pixel_counter <= 0;
line_comp_counter <= 0;
pixel_scale_count <= 0;
end else begin
if (line_comp_counter == 2) begin
port_a_addr <= port_a_addr + 'h40;
port_b_addr <= port_b_addr + 'h40;
if (port_a_addr == 'h3000) begin
port_a_addr <= 'h0000;
port_b_addr <= 'h0020;
end
pixel_counter <= 0;
line_comp_counter <= 0;
pixel_scale_count <= 0;
end else begin
if ( !display_time_en ) begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
pixel_counter <= 0;
pixel_scale_count <= 0;
end else begin
port_a_b_data_red <= {port_b_red_data, port_a_red_data};
port_a_b_data_green <= {port_b_green_data , port_a_green_data };
port_a_b_data_blue <= {port_b_blue_data , port_a_blue_data };
if (pixel_counter == 63) begin
pixel_counter <= 0;
line_comp_counter <= line_comp_counter + 1;
end else begin
if (pixel_scale_count == 4) begin
pixel_counter <= pixel_counter + 1;
pixel_scale_count <= 0;
end else begin
vga_red <= port_a_b_data_red[pixel_counter];
vga_green <= port_a_b_data_green[pixel_counter];
vga_blue <= port_a_b_data_blue[pixel_counter];
pixel_scale_count <= pixel_scale_count + 1;
end
end
end
end
end
end
endmodule | module VGAHsync(
clk,
clk_d,
reset,
h_sync,
vga_red,
vga_green,
vga_blue,
h_sync_en
); |
input clk, reset;
input h_sync_en;
input clk_d;
output reg h_sync;
output reg vga_red, vga_green, vga_blue;
reg [63:0] port_a_b_data_red;
reg [63:0] port_a_b_data_green;
reg [63:0] port_a_b_data_blue;
wire [31:0] port_a_red_data;
wire [31:0] port_b_red_data;
wire [31:0] port_a_green_data;
wire [31:0] port_b_green_data;
wire [31:0] port_a_blue_data;
wire [31:0] port_b_blue_data;
reg [13:0] port_a_addr, port_b_addr;
reg [11:0] master_hsync_count;
reg [6:0] pixel_counter;
reg [2:0] pixel_scale_count;
reg [1:0]line_comp_counter;
reg display_time_en;
VGAMemory vga_vram_0(
.reset (reset),
.clk (clk),
.pixel_addr_a(port_a_addr),
.pixel_addr_b(port_b_addr),
.red_out_p1 (port_a_red_data),
.green_out_p1 (port_a_green_data),
.blue_out_p1 (port_a_blue_data) ,
.red_out_p2 (port_b_red_data),
.green_out_p2 (port_b_green_data),
.blue_out_p2 (port_b_blue_data)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
h_sync <= 1;
master_hsync_count <= 0;
display_time_en <= 0;
end else begin
if (!h_sync_en) begin
h_sync <= 1;
master_hsync_count <= 0;
display_time_en <= 0;
end else begin
if (master_hsync_count == 0) begin
h_sync <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 192) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 287) begin
h_sync <= 1;
display_time_en <= 1;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 1567) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= master_hsync_count + 1;
end else begin
if (master_hsync_count == 1599) begin
h_sync <= 1;
display_time_en <= 0;
master_hsync_count <= 0;
end else begin
master_hsync_count <= master_hsync_count + 1;
end
end
end
end
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
port_a_addr <= 'h0000;
port_b_addr <= 'h0020;
pixel_counter <= 0;
line_comp_counter <= 0;
pixel_scale_count <= 0;
end else begin
if (line_comp_counter == 2) begin
port_a_addr <= port_a_addr + 'h40;
port_b_addr <= port_b_addr + 'h40;
if (port_a_addr == 'h3000) begin
port_a_addr <= 'h0000;
port_b_addr <= 'h0020;
end
pixel_counter <= 0;
line_comp_counter <= 0;
pixel_scale_count <= 0;
end else begin
if ( !display_time_en ) begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
pixel_counter <= 0;
pixel_scale_count <= 0;
end else begin
port_a_b_data_red <= {port_b_red_data, port_a_red_data};
port_a_b_data_green <= {port_b_green_data , port_a_green_data };
port_a_b_data_blue <= {port_b_blue_data , port_a_blue_data };
if (pixel_counter == 63) begin
pixel_counter <= 0;
line_comp_counter <= line_comp_counter + 1;
end else begin
if (pixel_scale_count == 4) begin
pixel_counter <= pixel_counter + 1;
pixel_scale_count <= 0;
end else begin
vga_red <= port_a_b_data_red[pixel_counter];
vga_green <= port_a_b_data_green[pixel_counter];
vga_blue <= port_a_b_data_blue[pixel_counter];
pixel_scale_count <= pixel_scale_count + 1;
end
end
end
end
end
end
endmodule | 1 |
3,784 | data/full_repos/permissive/106583614/Lab3/VGAMemory.v | 106,583,614 | VGAMemory.v | v | 481 | 123 | [] | [] | [] | null | line:481: before: "/" | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab3/VGAMemory.v:32: Cannot find file containing module: 'RAMB16BWER'\n RAMB16BWER #(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/RAMB16BWER\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/RAMB16BWER.v\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/RAMB16BWER.sv\n RAMB16BWER\n RAMB16BWER.v\n RAMB16BWER.sv\n obj_dir/RAMB16BWER\n obj_dir/RAMB16BWER.v\n obj_dir/RAMB16BWER.sv\n%Error: data/full_repos/permissive/106583614/Lab3/VGAMemory.v:184: Cannot find file containing module: 'RAMB16BWER'\n RAMB16BWER #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/106583614/Lab3/VGAMemory.v:336: Cannot find file containing module: 'RAMB16BWER'\n RAMB16BWER #(\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 1,567 | module | module VGAMemory(
reset,
clk,
pixel_addr_a,
pixel_addr_b,
red_out_p1,
green_out_p1,
blue_out_p1,
red_out_p2,
green_out_p2,
blue_out_p2
);
input reset, clk;
input [13:0] pixel_addr_a;
input [13:0] pixel_addr_b;
output [31:0] red_out_p1, green_out_p1, blue_out_p1;
output [31:0] red_out_p2, green_out_p2, blue_out_p2;
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_01(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_02(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_03(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_04(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_05(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_06(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_07(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_08(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_09(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0A(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0B(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_25(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_26(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_27(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_28(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_29(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2A(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2B(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2C(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2D(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2E(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2F(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_30(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_31(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_32(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_33(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_34(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_35(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_36(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_37(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_38(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_39(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3A(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3B(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3C(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3D(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3E(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3F(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
VGA_RED_memory_inst (
.DOA(red_out_p1),
.DOB(red_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_01(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_02(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_03(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_04(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_05(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_06(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_07(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_08(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_09(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0C(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_25(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_26(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_27(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_28(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_29(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2A(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2B(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2C(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2D(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2E(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2F(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
VGA_GREEN_memory_inst (
.DOA(green_out_p1),
.DOB(green_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.EN_RSTRAM_A("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_01(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_02(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_03(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_04(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_05(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_06(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_07(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_08(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_09(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_25(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_26(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_27(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_28(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_29(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2A(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2B(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2C(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2D(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2E(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2F(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
) VGA_BLUE_memory_inst (
.DOA(blue_out_p1),
.DOB(blue_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
endmodule | module VGAMemory(
reset,
clk,
pixel_addr_a,
pixel_addr_b,
red_out_p1,
green_out_p1,
blue_out_p1,
red_out_p2,
green_out_p2,
blue_out_p2
); |
input reset, clk;
input [13:0] pixel_addr_a;
input [13:0] pixel_addr_b;
output [31:0] red_out_p1, green_out_p1, blue_out_p1;
output [31:0] red_out_p2, green_out_p2, blue_out_p2;
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_01(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_02(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_03(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_04(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_05(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_06(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_07(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_08(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_09(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0A(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0B(256'hffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff_ffffffff),
.INIT_0C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_25(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_26(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_27(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_28(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_29(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2A(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2B(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2C(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2D(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2E(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_2F(256'h99999999999999999999999999999999_11111111111111111111111111111111),
.INIT_30(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_31(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_32(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_33(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_34(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_35(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_36(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_37(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_38(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_39(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3A(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3B(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3C(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3D(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3E(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_3F(256'h00000000000000000000000000000000_00000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
VGA_RED_memory_inst (
.DOA(red_out_p1),
.DOB(red_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("TRUE"),
.EN_RSTRAM_B("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_01(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_02(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_03(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_04(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_05(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_06(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_07(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_08(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_09(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0C(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_25(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_26(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_27(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_28(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_29(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2A(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2B(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2C(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2D(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2E(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_2F(256'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa_22222222222222222222222222222222),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
VGA_GREEN_memory_inst (
.DOA(green_out_p1),
.DOB(green_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.DOA_REG(0),
.EN_RSTRAM_A("TRUE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_01(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_02(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_03(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_04(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_05(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_06(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_07(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_08(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_09(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0A(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0B(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0C(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0D(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0E(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_0F(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_10(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_11(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_12(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_13(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_14(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_15(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_16(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_17(256'h0000000000000000_0000000000000000_ffffffffffffffff_ffffffffffffffff),
.INIT_18(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_19(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1A(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1B(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1C(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1D(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1E(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_1F(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_20(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_21(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_22(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_23(256'hffffffffffffffff_ffffffffffffffff_ffffffffffffffff_ffffffffffffffff),
.INIT_24(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_25(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_26(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_27(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_28(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_29(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2A(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2B(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2C(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2D(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2E(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_2F(256'hcccccccccccccccccccccccccccccccc_44444444444444444444444444444444),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.RSTTYPE("SYNC"),
.RST_PRIORITY_A("CE"),
.RST_PRIORITY_B("CE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("SPARTAN6"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
) VGA_BLUE_memory_inst (
.DOA(blue_out_p1),
.DOB(blue_out_p2),
.ADDRA(pixel_addr_a),
.CLKA(clk),
.ENA(1'b1),
.REGCEA(1'b1),
.RSTA(reset),
.WEA(4'b0000),
.ADDRB(pixel_addr_b),
.CLKB(clk),
.ENB(1'b1),
.REGCEB(1'b1),
.RSTB(reset),
.WEB(4'b0000)
);
endmodule | 1 |
3,785 | data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v | 106,583,614 | VGAMemory_tb.v | v | 55 | 54 | [] | [] | [] | null | line:50: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:12: Cannot find file containing module: \'VGAMemory\'\nVGAMemory vga_vram_0(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.v\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.sv\n VGAMemory\n VGAMemory.v\n VGAMemory.sv\n obj_dir/VGAMemory\n obj_dir/VGAMemory.v\n obj_dir/VGAMemory.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,568 | module | module VGAMemory_tb;
reg clk;
reg rst_n;
reg [13:0] pixel_addr_a;
reg [13:0] pixel_addr_b;
wire [31:0] VGA_Red0_p1, VGA_Green0_p1, VGA_Blue1_p1;
wire [31:0] VGA_Red0_p2, VGA_Green0_p2, VGA_Blue1_p2;
VGAMemory vga_vram_0(
.reset (rst_n),
.clk (clk),
.pixel_addr_a(pixel_addr_a),
.pixel_addr_b(pixel_addr_b),
.red_out_p1 (VGA_Red0_p1),
.green_out_p1 (VGA_Green0_p1),
.blue_out_p1 (VGA_Blue1_p1) ,
.red_out_p2 (VGA_Red0_p2),
.green_out_p2 (VGA_Green0_p2),
.blue_out_p2 (VGA_Blue1_p2)
);
localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;
initial begin
rst_n = 1;
clk = 1;
#20;
rst_n = 0;
#200
pixel_addr_a = 14'h0000;
pixel_addr_b = 14'h0020;
#20;
pixel_addr_a = 14'h0040;
pixel_addr_b = 14'h0060;
#20;
pixel_addr_a = 14'h0080;
pixel_addr_b = 14'h00a0;
#20;
pixel_addr_a = 14'h00c0;
pixel_addr_b = 14'h00e0;
#20;
pixel_addr_a = 14'h00ff;
pixel_addr_b = 14'h0100;
#1000
$finish;
end
endmodule | module VGAMemory_tb; |
reg clk;
reg rst_n;
reg [13:0] pixel_addr_a;
reg [13:0] pixel_addr_b;
wire [31:0] VGA_Red0_p1, VGA_Green0_p1, VGA_Blue1_p1;
wire [31:0] VGA_Red0_p2, VGA_Green0_p2, VGA_Blue1_p2;
VGAMemory vga_vram_0(
.reset (rst_n),
.clk (clk),
.pixel_addr_a(pixel_addr_a),
.pixel_addr_b(pixel_addr_b),
.red_out_p1 (VGA_Red0_p1),
.green_out_p1 (VGA_Green0_p1),
.blue_out_p1 (VGA_Blue1_p1) ,
.red_out_p2 (VGA_Red0_p2),
.green_out_p2 (VGA_Green0_p2),
.blue_out_p2 (VGA_Blue1_p2)
);
localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;
initial begin
rst_n = 1;
clk = 1;
#20;
rst_n = 0;
#200
pixel_addr_a = 14'h0000;
pixel_addr_b = 14'h0020;
#20;
pixel_addr_a = 14'h0040;
pixel_addr_b = 14'h0060;
#20;
pixel_addr_a = 14'h0080;
pixel_addr_b = 14'h00a0;
#20;
pixel_addr_a = 14'h00c0;
pixel_addr_b = 14'h00e0;
#20;
pixel_addr_a = 14'h00ff;
pixel_addr_b = 14'h0100;
#1000
$finish;
end
endmodule | 1 |
3,789 | data/full_repos/permissive/106583614/Lab3/VGAVsync.v | 106,583,614 | VGAVsync.v | v | 67 | 104 | [] | [] | [] | null | line:67: before: "/" | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab3/VGAVsync.v:34: Cannot find file containing module: 'VGAHsync'\n VGAHsync vga_hsync_0(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.v\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.sv\n VGAHsync\n VGAHsync.v\n VGAHsync.sv\n obj_dir/VGAHsync\n obj_dir/VGAHsync.v\n obj_dir/VGAHsync.sv\n%Error: Exiting due to 1 error(s)\n" | 1,572 | module | module VGAVsync(
clk,
reset,
vga_red_0,
vga_red_1,
vga_red_2,
vga_green_0,
vga_green_1,
vga_green_2,
vga_blue_1,
vga_blue_2,
h_sync,
v_sync
);
input clk, reset;
output vga_red_0, vga_red_1, vga_red_2;
output vga_green_0, vga_green_1, vga_green_2;
output vga_blue_1, vga_blue_2;
output wire v_sync;
output wire h_sync;
reg [19:0] master_vsync_count;
wire h_sync_en;
VGAHsync vga_hsync_0(
.clk(clk) ,
.reset(reset) ,
.h_sync(h_sync) ,
.vga_red_0( vga_red_0),
.vga_red_1( vga_red_1) ,
.vga_red_2( vga_red_2) ,
.vga_green_0 (vga_green_0),
.vga_green_1 (vga_green_1),
.vga_green_2 (vga_green_2),
.vga_blue_1 (vga_blue_1),
.vga_blue_2 (vga_blue_2),
.h_sync_en(h_sync_en)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
master_vsync_count <= 0;
end else begin
master_vsync_count <= master_vsync_count + 1;
if (master_vsync_count == 833599) begin
master_vsync_count <= 0;
end
end
end
assign v_sync = ( (master_vsync_count >= 20'd0) && (master_vsync_count <= 20'd3199) ) ? 0 : 1;
assign h_sync_en = ( (master_vsync_count > 20'd49599) && (master_vsync_count <= 20'd817599) ) ? 1 : 0;
endmodule | module VGAVsync(
clk,
reset,
vga_red_0,
vga_red_1,
vga_red_2,
vga_green_0,
vga_green_1,
vga_green_2,
vga_blue_1,
vga_blue_2,
h_sync,
v_sync
); |
input clk, reset;
output vga_red_0, vga_red_1, vga_red_2;
output vga_green_0, vga_green_1, vga_green_2;
output vga_blue_1, vga_blue_2;
output wire v_sync;
output wire h_sync;
reg [19:0] master_vsync_count;
wire h_sync_en;
VGAHsync vga_hsync_0(
.clk(clk) ,
.reset(reset) ,
.h_sync(h_sync) ,
.vga_red_0( vga_red_0),
.vga_red_1( vga_red_1) ,
.vga_red_2( vga_red_2) ,
.vga_green_0 (vga_green_0),
.vga_green_1 (vga_green_1),
.vga_green_2 (vga_green_2),
.vga_blue_1 (vga_blue_1),
.vga_blue_2 (vga_blue_2),
.h_sync_en(h_sync_en)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
master_vsync_count <= 0;
end else begin
master_vsync_count <= master_vsync_count + 1;
if (master_vsync_count == 833599) begin
master_vsync_count <= 0;
end
end
end
assign v_sync = ( (master_vsync_count >= 20'd0) && (master_vsync_count <= 20'd3199) ) ? 0 : 1;
assign h_sync_en = ( (master_vsync_count > 20'd49599) && (master_vsync_count <= 20'd817599) ) ? 1 : 0;
endmodule | 1 |
3,790 | data/full_repos/permissive/106583614/Lab3/VGAVsync_back_up.v | 106,583,614 | VGAVsync_back_up.v | v | 81 | 54 | [] | [] | [] | null | line:81: before: "/" | null | 1: b"%Error: data/full_repos/permissive/106583614/Lab3/VGAVsync_back_up.v:21: Cannot find file containing module: 'VGAHsync'\n VGAHsync vga_hsync_0(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.v\n data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.sv\n VGAHsync\n VGAHsync.v\n VGAHsync.sv\n obj_dir/VGAHsync\n obj_dir/VGAHsync.v\n obj_dir/VGAHsync.sv\n%Error: Exiting due to 1 error(s)\n" | 1,573 | module | module VGAVsync(
clk,
reset,
vga_red,
vga_green,
vga_blue,
h_sync,
v_sync
);
input clk, reset;
output vga_red, vga_green, vga_blue;
output reg v_sync;
output h_sync;
reg [19:0] master_vsync_count;
reg h_sync_en;
VGAHsync vga_hsync_0(
.clk(clk) ,
.clk_d(clk_d) ,
.reset(reset) ,
.h_sync(h_sync) ,
.vga_red(vga_red) ,
.vga_green(vga_green) ,
.vga_blue(vga_blue) ,
.h_sync_en(h_sync_en)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
master_vsync_count <= 0;
v_sync <= 1;
h_sync_en <= 0;
end else begin
if (master_vsync_count == 0) begin
v_sync <= 0;
h_sync_en <= 0;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 3200) begin
v_sync <= 1;
h_sync_en <= 0;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 49600) begin
h_sync_en <= 1;
v_sync <= 1;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 817600) begin
h_sync_en <= 0;
v_sync <= 1;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 833600) begin
h_sync_en <= 0;
v_sync <= 1;
master_vsync_count <= 0;
end else begin
master_vsync_count <= master_vsync_count + 1;
end
end
end
end
end
end
end
endmodule | module VGAVsync(
clk,
reset,
vga_red,
vga_green,
vga_blue,
h_sync,
v_sync
); |
input clk, reset;
output vga_red, vga_green, vga_blue;
output reg v_sync;
output h_sync;
reg [19:0] master_vsync_count;
reg h_sync_en;
VGAHsync vga_hsync_0(
.clk(clk) ,
.clk_d(clk_d) ,
.reset(reset) ,
.h_sync(h_sync) ,
.vga_red(vga_red) ,
.vga_green(vga_green) ,
.vga_blue(vga_blue) ,
.h_sync_en(h_sync_en)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
master_vsync_count <= 0;
v_sync <= 1;
h_sync_en <= 0;
end else begin
if (master_vsync_count == 0) begin
v_sync <= 0;
h_sync_en <= 0;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 3200) begin
v_sync <= 1;
h_sync_en <= 0;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 49600) begin
h_sync_en <= 1;
v_sync <= 1;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 817600) begin
h_sync_en <= 0;
v_sync <= 1;
master_vsync_count <= master_vsync_count + 1;
end else begin
if (master_vsync_count == 833600) begin
h_sync_en <= 0;
v_sync <= 1;
master_vsync_count <= 0;
end else begin
master_vsync_count <= master_vsync_count + 1;
end
end
end
end
end
end
end
endmodule | 1 |
3,792 | data/full_repos/permissive/106583614/Lab4/LCD_control_unit.v | 106,583,614 | LCD_control_unit.v | v | 485 | 111 | [] | [] | [] | null | line:485: before: "/" | null | 1: b'%Error: data/full_repos/permissive/106583614/Lab4/LCD_control_unit.v:56: Cannot find file containing module: \'LCD_inst_decode\'\nLCD_inst_decode lcd_decode_0(\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106583614/Lab4,data/full_repos/permissive/106583614/LCD_inst_decode\n data/full_repos/permissive/106583614/Lab4,data/full_repos/permissive/106583614/LCD_inst_decode.v\n data/full_repos/permissive/106583614/Lab4,data/full_repos/permissive/106583614/LCD_inst_decode.sv\n LCD_inst_decode\n LCD_inst_decode.v\n LCD_inst_decode.sv\n obj_dir/LCD_inst_decode\n obj_dir/LCD_inst_decode.v\n obj_dir/LCD_inst_decode.sv\n%Warning-WIDTH: data/full_repos/permissive/106583614/Lab4/LCD_control_unit.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'message_counter\' generates 5 bits.\n : ... In instance LCD_control_unit\n data_reg <= message_counter;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,575 | module | module LCD_control_unit(
clk,
reset,
LCD_RS,
LCD_RW,
LCD_EN,
LCD_SF_D
);
input clk, reset;
output [3:0] LCD_SF_D;
output LCD_RS, LCD_RW, LCD_EN;
reg [7:0] message [30:0];
reg [7:0] data_reg;
reg [3:0] next_send_state;
reg [4:0] next_control_state;
reg [3:0] instruction;
wire [3:0] LCD_upper_4, LCD_lower_4;
reg LCD_EN_send, LCD_EN_cont;
reg in_send_flag;
reg upper_flag;
reg send_complete_flag;
reg cont_flag;
reg message_send_flag;
reg cont_counter;
reg [12:0] send_counter;
reg [21:0] control_counter;
reg [4:0] message_counter;
LCD_inst_decode lcd_decode_0(
.clk(clk) ,
.reset(reset) ,
.instruction(instruction) ,
.LCD_RS(LCD_RS) ,
.LCD_RW(LCD_RW) ,
.LCD_upper_4(LCD_upper_4) ,
.LCD_lower_4(LCD_lower_4) ,
.address_reg(data_reg)
);
assign LCD_SF_D = (upper_flag) ? LCD_upper_4 : LCD_lower_4;
assign LCD_EN = (in_send_flag) ? LCD_EN_send : LCD_EN_cont;
always @(posedge clk or posedge reset) begin
if (reset) begin
message[0] <= 'h41;
message[1] <= 'h68;
message[2] <= 'h6d;
message[3] <= 'h65;
message[4] <= 'h74;
message[5] <= 'h21;
message[6] <= 'h21;
message[7] <= 'h21;
message[8] <= 'h21;
message[9] <= 'h21;
message[10] <= 'h21;
message[11] <= 'h21;
message[12] <= 'h3c;
message[13] <= 'h33;
message[14] <= 'h3c;
message[15] <= 'h33;
message[16] <= 'h43;
message[17] <= 'h45;
message[18] <= 'h20;
message[19] <= 'h34;
message[20] <= 'h33;
message[21] <= 'h30;
message[22] <= 'h3c;
message[23] <= 'h33;
message[24] <= 'h3c;
message[25] <= 'h33;
message[26] <= 'h21;
message[27] <= 'h20;
message[28] <= 'h20;
message[29] <= 'h20;
message[30] <= 'h23;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
send_counter <= 'b0;
end else begin
if (cont_flag) begin
send_counter <= send_counter + 1'b1;
if (send_counter == 'd2080) begin
send_counter <= 'b0;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
upper_flag <= 'b1;
in_send_flag <= 1'b0;
send_complete_flag <= 1'b0;
LCD_EN_send <= 1'b0;
next_send_state <= 'd1;
end else begin
case (next_send_state)
'd1:
begin
if ((send_counter == 'd2) && cont_flag) begin
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b1;
next_send_state <= 'd2;
end else begin
send_complete_flag <= 1'b0;
if (send_counter == 'd1) begin
upper_flag <= 1'b1;
end
end
end
'd2:
begin
if (send_counter == 'd14) begin
upper_flag <= 1'b1;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd3;
end
end
'd3:
begin
if (send_counter == 'd15) begin
upper_flag <= 1'b1;
LCD_EN_send <= 1'b0;
in_send_flag <= 1'b1;
next_send_state <= 'd4;
end
end
'd4:
begin
if (send_counter == 'd65) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd5;
end
end
'd5:
begin
if (send_counter == 'd67) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b1;
next_send_state <= 'd6;
end
end
'd6:
begin
if (send_counter == 'd79) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd7;
end
end
'd7:
begin
if (send_counter == 'd80) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd8;
end
end
'd8:
begin
if (send_counter == 'd2080) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b0;
LCD_EN_send <= 1'b0;
send_complete_flag <= 1'b1;
next_send_state <= 'd1;
end
end
default:
begin
upper_flag <= 'b0;
in_send_flag <= 1'b0;
send_complete_flag <= 1'b0;
end
endcase
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
control_counter <= 'b0;
end else begin
if (cont_counter) begin
control_counter <= control_counter + 1'b1;
end else begin
if (control_counter == 1046049) begin
control_counter <= 'd964048;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
cont_flag <= 1'b0;
message_counter <= 'd0;
next_control_state <= 'd1;
message_send_flag <= 1'b0;
cont_counter <= 1'b1;
LCD_EN_cont <= 1'b0;
data_reg <= 'd0;
instruction <= 'd0;
end else begin
case (next_control_state)
'd1:
begin
if (control_counter == 'd750000) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd2;
end
end
'd2:
begin
if (control_counter == 750012) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd3;
end
end
'd3:
begin
if (control_counter == 955012) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd4;
end
end
'd4:
begin
if (control_counter == 955024) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd5;
end
end
'd5:
begin
if (control_counter == 960024) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd6;
end
end
'd6:
begin
if (control_counter == 960036) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd7;
end
end
'd7:
begin
if (control_counter == 962036) begin
instruction <= 'd12;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd8;
end
end
'd8:
begin
if (control_counter == 962048) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd9;
end
end
'd9:
begin
if (control_counter == 964048) begin
instruction <= 'd5;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b1;
cont_counter <= 1'b0;
next_control_state <= 'd10;
end
end
'd10:
begin
if (send_complete_flag) begin
instruction <= 'd2;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
cont_counter <= 1'b0;
next_control_state <= 'd11;
end else begin
cont_flag <= 1'b1;
end
end
'd11:
begin
if (send_complete_flag) begin
instruction <= 'd3;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd12;
end else begin
cont_flag <= 1'b1;
end
end
'd12:
begin
if (send_complete_flag) begin
instruction <= 'd3;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd13;
end else begin
cont_flag <= 1'b1;
end
end
'd13:
begin
if (send_complete_flag) begin
instruction <= 'd0;
LCD_EN_cont <= 1'b0;
cont_counter <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd14;
end else begin
cont_flag <= 1'b1;
end
end
'd14:
begin
if (control_counter == 1046048) begin
data_reg <= message_counter;
instruction <= 'd7;
cont_flag <= 1'b1;
cont_counter <= 1'b0;
next_control_state <= 'd15;
end
end
'd15:
begin
if (send_complete_flag) begin
message_counter <= message_counter + 1'b1;
data_reg <= message[message_counter];
instruction <= 'd9;
cont_flag <= 1'b0;
next_control_state <= 'd16;
end else begin
cont_flag <= 1'b1;
end
end
'd16:
begin
if (message_send_flag) begin
instruction <= 'd5;
message_send_flag <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd10;
end else begin
if (send_complete_flag) begin
instruction <= 'd9;
cont_flag <= 1'b0;
message_counter <= message_counter + 1'b1;
if (message_counter <= 16) begin
data_reg <= message[message_counter];
end else begin
data_reg <= message[message_counter-1'b1];
end
if (message_counter == 16) begin
if (send_complete_flag) begin
data_reg <= 'h40;
instruction <=7;
end
end
if (message_counter == 30) begin
message_counter <= 'b0;
message_send_flag <= 1'b1;
end
next_control_state <= 'd16;
end else begin
cont_flag <= 1'b1;
end
end
end
default:
begin
cont_flag <= 1'b0;
end
endcase
end
end
endmodule | module LCD_control_unit(
clk,
reset,
LCD_RS,
LCD_RW,
LCD_EN,
LCD_SF_D
); |
input clk, reset;
output [3:0] LCD_SF_D;
output LCD_RS, LCD_RW, LCD_EN;
reg [7:0] message [30:0];
reg [7:0] data_reg;
reg [3:0] next_send_state;
reg [4:0] next_control_state;
reg [3:0] instruction;
wire [3:0] LCD_upper_4, LCD_lower_4;
reg LCD_EN_send, LCD_EN_cont;
reg in_send_flag;
reg upper_flag;
reg send_complete_flag;
reg cont_flag;
reg message_send_flag;
reg cont_counter;
reg [12:0] send_counter;
reg [21:0] control_counter;
reg [4:0] message_counter;
LCD_inst_decode lcd_decode_0(
.clk(clk) ,
.reset(reset) ,
.instruction(instruction) ,
.LCD_RS(LCD_RS) ,
.LCD_RW(LCD_RW) ,
.LCD_upper_4(LCD_upper_4) ,
.LCD_lower_4(LCD_lower_4) ,
.address_reg(data_reg)
);
assign LCD_SF_D = (upper_flag) ? LCD_upper_4 : LCD_lower_4;
assign LCD_EN = (in_send_flag) ? LCD_EN_send : LCD_EN_cont;
always @(posedge clk or posedge reset) begin
if (reset) begin
message[0] <= 'h41;
message[1] <= 'h68;
message[2] <= 'h6d;
message[3] <= 'h65;
message[4] <= 'h74;
message[5] <= 'h21;
message[6] <= 'h21;
message[7] <= 'h21;
message[8] <= 'h21;
message[9] <= 'h21;
message[10] <= 'h21;
message[11] <= 'h21;
message[12] <= 'h3c;
message[13] <= 'h33;
message[14] <= 'h3c;
message[15] <= 'h33;
message[16] <= 'h43;
message[17] <= 'h45;
message[18] <= 'h20;
message[19] <= 'h34;
message[20] <= 'h33;
message[21] <= 'h30;
message[22] <= 'h3c;
message[23] <= 'h33;
message[24] <= 'h3c;
message[25] <= 'h33;
message[26] <= 'h21;
message[27] <= 'h20;
message[28] <= 'h20;
message[29] <= 'h20;
message[30] <= 'h23;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
send_counter <= 'b0;
end else begin
if (cont_flag) begin
send_counter <= send_counter + 1'b1;
if (send_counter == 'd2080) begin
send_counter <= 'b0;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
upper_flag <= 'b1;
in_send_flag <= 1'b0;
send_complete_flag <= 1'b0;
LCD_EN_send <= 1'b0;
next_send_state <= 'd1;
end else begin
case (next_send_state)
'd1:
begin
if ((send_counter == 'd2) && cont_flag) begin
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b1;
next_send_state <= 'd2;
end else begin
send_complete_flag <= 1'b0;
if (send_counter == 'd1) begin
upper_flag <= 1'b1;
end
end
end
'd2:
begin
if (send_counter == 'd14) begin
upper_flag <= 1'b1;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd3;
end
end
'd3:
begin
if (send_counter == 'd15) begin
upper_flag <= 1'b1;
LCD_EN_send <= 1'b0;
in_send_flag <= 1'b1;
next_send_state <= 'd4;
end
end
'd4:
begin
if (send_counter == 'd65) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd5;
end
end
'd5:
begin
if (send_counter == 'd67) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b1;
next_send_state <= 'd6;
end
end
'd6:
begin
if (send_counter == 'd79) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd7;
end
end
'd7:
begin
if (send_counter == 'd80) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b1;
LCD_EN_send <= 1'b0;
next_send_state <= 'd8;
end
end
'd8:
begin
if (send_counter == 'd2080) begin
upper_flag <= 1'b0;
in_send_flag <= 1'b0;
LCD_EN_send <= 1'b0;
send_complete_flag <= 1'b1;
next_send_state <= 'd1;
end
end
default:
begin
upper_flag <= 'b0;
in_send_flag <= 1'b0;
send_complete_flag <= 1'b0;
end
endcase
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
control_counter <= 'b0;
end else begin
if (cont_counter) begin
control_counter <= control_counter + 1'b1;
end else begin
if (control_counter == 1046049) begin
control_counter <= 'd964048;
end
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
cont_flag <= 1'b0;
message_counter <= 'd0;
next_control_state <= 'd1;
message_send_flag <= 1'b0;
cont_counter <= 1'b1;
LCD_EN_cont <= 1'b0;
data_reg <= 'd0;
instruction <= 'd0;
end else begin
case (next_control_state)
'd1:
begin
if (control_counter == 'd750000) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd2;
end
end
'd2:
begin
if (control_counter == 750012) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd3;
end
end
'd3:
begin
if (control_counter == 955012) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd4;
end
end
'd4:
begin
if (control_counter == 955024) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd5;
end
end
'd5:
begin
if (control_counter == 960024) begin
instruction <= 'd11;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd6;
end
end
'd6:
begin
if (control_counter == 960036) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd7;
end
end
'd7:
begin
if (control_counter == 962036) begin
instruction <= 'd12;
LCD_EN_cont <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd8;
end
end
'd8:
begin
if (control_counter == 962048) begin
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd9;
end
end
'd9:
begin
if (control_counter == 964048) begin
instruction <= 'd5;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b1;
cont_counter <= 1'b0;
next_control_state <= 'd10;
end
end
'd10:
begin
if (send_complete_flag) begin
instruction <= 'd2;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
cont_counter <= 1'b0;
next_control_state <= 'd11;
end else begin
cont_flag <= 1'b1;
end
end
'd11:
begin
if (send_complete_flag) begin
instruction <= 'd3;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd12;
end else begin
cont_flag <= 1'b1;
end
end
'd12:
begin
if (send_complete_flag) begin
instruction <= 'd3;
LCD_EN_cont <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd13;
end else begin
cont_flag <= 1'b1;
end
end
'd13:
begin
if (send_complete_flag) begin
instruction <= 'd0;
LCD_EN_cont <= 1'b0;
cont_counter <= 1'b1;
cont_flag <= 1'b0;
next_control_state <= 'd14;
end else begin
cont_flag <= 1'b1;
end
end
'd14:
begin
if (control_counter == 1046048) begin
data_reg <= message_counter;
instruction <= 'd7;
cont_flag <= 1'b1;
cont_counter <= 1'b0;
next_control_state <= 'd15;
end
end
'd15:
begin
if (send_complete_flag) begin
message_counter <= message_counter + 1'b1;
data_reg <= message[message_counter];
instruction <= 'd9;
cont_flag <= 1'b0;
next_control_state <= 'd16;
end else begin
cont_flag <= 1'b1;
end
end
'd16:
begin
if (message_send_flag) begin
instruction <= 'd5;
message_send_flag <= 1'b0;
cont_flag <= 1'b0;
next_control_state <= 'd10;
end else begin
if (send_complete_flag) begin
instruction <= 'd9;
cont_flag <= 1'b0;
message_counter <= message_counter + 1'b1;
if (message_counter <= 16) begin
data_reg <= message[message_counter];
end else begin
data_reg <= message[message_counter-1'b1];
end
if (message_counter == 16) begin
if (send_complete_flag) begin
data_reg <= 'h40;
instruction <=7;
end
end
if (message_counter == 30) begin
message_counter <= 'b0;
message_send_flag <= 1'b1;
end
next_control_state <= 'd16;
end else begin
cont_flag <= 1'b1;
end
end
end
default:
begin
cont_flag <= 1'b0;
end
endcase
end
end
endmodule | 1 |
3,793 | data/full_repos/permissive/106583614/Lab4/LCD_inst_decode.v | 106,583,614 | LCD_inst_decode.v | v | 151 | 79 | [] | [] | [] | null | line:151: before: "/" | data/verilator_xmls/f9f0fc0a-16c3-4973-b097-c3f482d410e7.xml | null | 1,576 | module | module LCD_inst_decode(
clk,
reset,
instruction,
LCD_RS,
LCD_RW,
LCD_upper_4,
LCD_lower_4,
address_reg
);
input clk, reset;
input [7:0] address_reg;
output reg LCD_RS, LCD_RW;
output reg [3:0] LCD_upper_4;
output reg [3:0] LCD_lower_4;
input [3:0] instruction;
always @(posedge clk or posedge reset) begin
if (reset) begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0001;
end else begin
case(instruction)
'd0:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0001;
end
'd1:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0010;
end
'd2:
begin
LCD_RS <= 'b0;
LCD_RW <= 'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0110;
end
'd3:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b1100;
end
'd4:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0001;
LCD_lower_4 <= 4'b0001;
end
'd5:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0010;
LCD_lower_4 <= 4'b1000;
end
'd6:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= {2'b01, address_reg[5:4]};
LCD_lower_4 <= address_reg[3:0];
end
'd7:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= {1'b1, address_reg[6:4]};
LCD_lower_4 <= address_reg[3:0];
end
'd8:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b1;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd9:
begin
LCD_RS <= 1'b1;
LCD_RW <= 1'b0;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd10:
begin
LCD_RS <= 1'b1;
LCD_RW <= 1'b1;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd11:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0011;
LCD_lower_4 <= 4'b0011;
end
'd12:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0010;
LCD_lower_4 <= 4'b0010;
end
default:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0000;
end
endcase
end
end
endmodule | module LCD_inst_decode(
clk,
reset,
instruction,
LCD_RS,
LCD_RW,
LCD_upper_4,
LCD_lower_4,
address_reg
); |
input clk, reset;
input [7:0] address_reg;
output reg LCD_RS, LCD_RW;
output reg [3:0] LCD_upper_4;
output reg [3:0] LCD_lower_4;
input [3:0] instruction;
always @(posedge clk or posedge reset) begin
if (reset) begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0001;
end else begin
case(instruction)
'd0:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0001;
end
'd1:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0010;
end
'd2:
begin
LCD_RS <= 'b0;
LCD_RW <= 'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0110;
end
'd3:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b1100;
end
'd4:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0001;
LCD_lower_4 <= 4'b0001;
end
'd5:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0010;
LCD_lower_4 <= 4'b1000;
end
'd6:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= {2'b01, address_reg[5:4]};
LCD_lower_4 <= address_reg[3:0];
end
'd7:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= {1'b1, address_reg[6:4]};
LCD_lower_4 <= address_reg[3:0];
end
'd8:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b1;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd9:
begin
LCD_RS <= 1'b1;
LCD_RW <= 1'b0;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd10:
begin
LCD_RS <= 1'b1;
LCD_RW <= 1'b1;
LCD_upper_4 <= address_reg[7:4];
LCD_lower_4 <= address_reg[3:0];
end
'd11:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0011;
LCD_lower_4 <= 4'b0011;
end
'd12:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0010;
LCD_lower_4 <= 4'b0010;
end
default:
begin
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
LCD_upper_4 <= 4'b0000;
LCD_lower_4 <= 4'b0000;
end
endcase
end
end
endmodule | 1 |
3,795 | data/full_repos/permissive/106596430/clockReset.v | 106,596,430 | clockReset.v | v | 100 | 104 | [] | [] | [] | [(13, 99)] | null | null | 1: b"%Error: data/full_repos/permissive/106596430/clockReset.v:39: Cannot find file containing module: 'IBUF'\n IBUF clkin_ibuf\n ^~~~\n ... Looked in:\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF.v\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF.sv\n IBUF\n IBUF.v\n IBUF.sv\n obj_dir/IBUF\n obj_dir/IBUF.v\n obj_dir/IBUF.sv\n%Error: data/full_repos/permissive/106596430/clockReset.v:45: Cannot find file containing module: 'MMCME2_BASE'\n MMCME2_BASE #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/106596430/clockReset.v:81: Cannot find file containing module: 'BUFG'\n BUFG clkout1_bufg\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 1,578 | module | module clockReset(
input clk100,
input rstPBn,
output clk5,
output reset
);
wire clk100buf;
wire clk5_0;
wire clkfbout;
wire locked;
wire reset_high;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
IBUF clkin_ibuf
(.O (clk100buf),
.I (clk100));
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT4_CASCADE("FALSE"),
.STARTUP_WAIT("FALSE"),
.DIVCLK_DIVIDE(5),
.CLKFBOUT_MULT_F(32.0),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.0),
.REF_JITTER1(0.01),
.CLKOUT0_DIVIDE_F(128.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0)
)
MMCME2_BASE_inst (
.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk5_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
.CLKFBIN (clkfbout),
.CLKIN1 (clk100buf),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (1'b0)
);
BUFG clkout1_bufg
(.O (clk5),
.I (clk5_0));
wire resetIn = ~rstPBn | ~locked;
reg resetFFn;
always @ (posedge clk5, posedge resetIn)
if (resetIn) resetFFn <= 1'b0;
else resetFFn <= 1'b1;
assign reset = ~resetFFn;
endmodule | module clockReset(
input clk100,
input rstPBn,
output clk5,
output reset
); |
wire clk100buf;
wire clk5_0;
wire clkfbout;
wire locked;
wire reset_high;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
IBUF clkin_ibuf
(.O (clk100buf),
.I (clk100));
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT4_CASCADE("FALSE"),
.STARTUP_WAIT("FALSE"),
.DIVCLK_DIVIDE(5),
.CLKFBOUT_MULT_F(32.0),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.0),
.REF_JITTER1(0.01),
.CLKOUT0_DIVIDE_F(128.0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0)
)
MMCME2_BASE_inst (
.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk5_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
.CLKFBIN (clkfbout),
.CLKIN1 (clk100buf),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (1'b0)
);
BUFG clkout1_bufg
(.O (clk5),
.I (clk5_0));
wire resetIn = ~rstPBn | ~locked;
reg resetFFn;
always @ (posedge clk5, posedge resetIn)
if (resetIn) resetFFn <= 1'b0;
else resetFFn <= 1'b1;
assign reset = ~resetFFn;
endmodule | 0 |
3,796 | data/full_repos/permissive/106596430/displayTest.v | 106,596,430 | displayTest.v | v | 66 | 91 | [] | [] | [] | [(12, 65)] | null | null | 1: b"%Error: data/full_repos/permissive/106596430/displayTest.v:28: Cannot find file containing module: 'clockReset'\n clockReset clkGen (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset.v\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset.sv\n clockReset\n clockReset.v\n clockReset.sv\n obj_dir/clockReset\n obj_dir/clockReset.v\n obj_dir/clockReset.sv\n%Error: data/full_repos/permissive/106596430/displayTest.v:57: Cannot find file containing module: 'DisplayInterface'\n DisplayInterface disp1 (\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,579 | module | module displayTest(
input clk100,
input rstPBn,
input [3:0] point,
output [7:0] digit,
output [7:0] segment
);
wire clk5;
wire reset;
wire [15:0] dispVal;
clockReset clkGen (
.clk100 (clk100),
.rstPBn (rstPBn),
.clk5 (clk5),
.reset (reset) );
reg [28:0] testCount;
always @ (posedge clk5)
begin
if (reset) testCount <= 29'b0;
else testCount <= testCount + 1'b1;
end
assign dispVal[15:12] = testCount[28:25];
assign dispVal[11:8] = testCount[27:24];
assign dispVal[7:4] = testCount[26:23];
assign dispVal[3:0] = testCount[25:22];
DisplayInterface disp1 (
.clk5(clk5),
.reset(reset),
.point(point),
.dispVal(dispVal),
.digit(digit),
.segment(segment));
endmodule | module displayTest(
input clk100,
input rstPBn,
input [3:0] point,
output [7:0] digit,
output [7:0] segment
); |
wire clk5;
wire reset;
wire [15:0] dispVal;
clockReset clkGen (
.clk100 (clk100),
.rstPBn (rstPBn),
.clk5 (clk5),
.reset (reset) );
reg [28:0] testCount;
always @ (posedge clk5)
begin
if (reset) testCount <= 29'b0;
else testCount <= testCount + 1'b1;
end
assign dispVal[15:12] = testCount[28:25];
assign dispVal[11:8] = testCount[27:24];
assign dispVal[7:4] = testCount[26:23];
assign dispVal[3:0] = testCount[25:22];
DisplayInterface disp1 (
.clk5(clk5),
.reset(reset),
.point(point),
.dispVal(dispVal),
.digit(digit),
.segment(segment));
endmodule | 0 |
3,797 | data/full_repos/permissive/106596430/hex2seg.v | 106,596,430 | hex2seg.v | v | 48 | 84 | [] | [] | [] | [(23, 48)] | null | data/verilator_xmls/5bae6df0-6f61-4f99-9378-35f9940171b4.xml | null | 1,580 | module | module hex2seg (
input [3:0] number,
output reg [6:0] pattern );
always @ (number)
case(number)
4'h0: pattern = 7'b0000001;
4'h1: pattern = 7'b1001111;
4'h2: pattern = 7'b0010010;
4'h3: pattern = 7'b0000110;
4'h4: pattern = 7'b1001100;
4'h5: pattern = 7'b0100100;
4'h6: pattern = 7'b0100000;
4'h7: pattern = 7'b0001111;
4'h8: pattern = 7'b0000000;
4'h9: pattern = 7'b0000100;
4'hA: pattern = 7'b0001000;
4'hB: pattern = 7'b1100000;
4'hC: pattern = 7'b0110001;
4'hD: pattern = 7'b1000010;
4'hE: pattern = 7'b0110000;
4'hF: pattern = 7'b0111000;
endcase
endmodule | module hex2seg (
input [3:0] number,
output reg [6:0] pattern ); |
always @ (number)
case(number)
4'h0: pattern = 7'b0000001;
4'h1: pattern = 7'b1001111;
4'h2: pattern = 7'b0010010;
4'h3: pattern = 7'b0000110;
4'h4: pattern = 7'b1001100;
4'h5: pattern = 7'b0100100;
4'h6: pattern = 7'b0100000;
4'h7: pattern = 7'b0001111;
4'h8: pattern = 7'b0000000;
4'h9: pattern = 7'b0000100;
4'hA: pattern = 7'b0001000;
4'hB: pattern = 7'b1100000;
4'hC: pattern = 7'b0110001;
4'hD: pattern = 7'b1000010;
4'hE: pattern = 7'b0110000;
4'hF: pattern = 7'b0111000;
endcase
endmodule | 0 |
3,798 | data/full_repos/permissive/106596430/moduleverilog.v | 106,596,430 | moduleverilog.v | v | 131 | 102 | [] | [] | [] | [(34, 130)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/106596430/moduleverilog.v:74: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance DisplayInterface\n counterDisplay <= 1\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106596430/moduleverilog.v:126: Cannot find file containing module: \'hex2seg\'\n hex2seg seg1 (.number(hexOutput),\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg.v\n data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg.sv\n hex2seg\n hex2seg.v\n hex2seg.sv\n obj_dir/hex2seg\n obj_dir/hex2seg.v\n obj_dir/hex2seg.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,581 | module | module DisplayInterface(input clk5,
input reset,
input [3:0] point,
input [15:0] dispVal,
output reg [7:0] digit,
output [7:0] segment
);
localparam compare = 2047;
reg [10:0] countClkDiv;
reg [1:0] counterDisplay;
reg Enable;
reg [3:0] hexOutput;
reg pointOn;
always @(posedge clk5)
begin
if(reset)
begin
countClkDiv <= 11'b0;
Enable <= 1'b0;
end
else if (countClkDiv == compare)
begin
countClkDiv <= 11'b0;
Enable <= 1'b1;
end
else
begin
countClkDiv <= countClkDiv + 1'b1;
Enable <= 1'b0;
end
end
always @(posedge clk5)
begin
if(reset)
counterDisplay <= 1'b0;
else if(Enable)
counterDisplay <= counterDisplay + 1'b1;
else
counterDisplay <= counterDisplay;
end
always @(counterDisplay)
case(counterDisplay)
2'b00: hexOutput = dispVal[3:0];
2'b01: hexOutput = dispVal[7:4];
2'b10: hexOutput = dispVal[11:8];
2'b11: hexOutput = dispVal[15:12];
endcase
always @(counterDisplay,point)
case(counterDisplay)
2'b00: begin
digit = 8'b11111110;
if(point[0] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b01: begin
digit = 8'b11111101;
if(point[1] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b10: begin
digit = 8'b11111011;
if(point[2] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b11: begin
digit = 8'b11110111;
if(point[3] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
endcase
assign segment[0] = ~pointOn;
hex2seg seg1 (.number(hexOutput),
.pattern (segment[7:1])
);
endmodule | module DisplayInterface(input clk5,
input reset,
input [3:0] point,
input [15:0] dispVal,
output reg [7:0] digit,
output [7:0] segment
); |
localparam compare = 2047;
reg [10:0] countClkDiv;
reg [1:0] counterDisplay;
reg Enable;
reg [3:0] hexOutput;
reg pointOn;
always @(posedge clk5)
begin
if(reset)
begin
countClkDiv <= 11'b0;
Enable <= 1'b0;
end
else if (countClkDiv == compare)
begin
countClkDiv <= 11'b0;
Enable <= 1'b1;
end
else
begin
countClkDiv <= countClkDiv + 1'b1;
Enable <= 1'b0;
end
end
always @(posedge clk5)
begin
if(reset)
counterDisplay <= 1'b0;
else if(Enable)
counterDisplay <= counterDisplay + 1'b1;
else
counterDisplay <= counterDisplay;
end
always @(counterDisplay)
case(counterDisplay)
2'b00: hexOutput = dispVal[3:0];
2'b01: hexOutput = dispVal[7:4];
2'b10: hexOutput = dispVal[11:8];
2'b11: hexOutput = dispVal[15:12];
endcase
always @(counterDisplay,point)
case(counterDisplay)
2'b00: begin
digit = 8'b11111110;
if(point[0] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b01: begin
digit = 8'b11111101;
if(point[1] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b10: begin
digit = 8'b11111011;
if(point[2] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
2'b11: begin
digit = 8'b11110111;
if(point[3] == 1'b1)
pointOn = 1'b1;
else
pointOn = 1'b0;
end
endcase
assign segment[0] = ~pointOn;
hex2seg seg1 (.number(hexOutput),
.pattern (segment[7:1])
);
endmodule | 0 |
3,799 | data/full_repos/permissive/106966316/alu32tb.v | 106,966,316 | alu32tb.v | v | 54 | 83 | [] | [] | [] | [(23, 53)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#100; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/alu32tb.v:32: Cannot find file containing module: \'alu32\'\nalu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.sv\n alu32\n alu32.v\n alu32.sv\n obj_dir/alu32\n obj_dir/alu32.v\n obj_dir/alu32.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,583 | module | module alu32tb();
reg [31:0] iA;
reg [31:0] iB;
reg [2:0] ctrl;
wire [31:0]out;
wire oCarry;
alu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));
initial begin
iA = 32'b1;
iB = 32'b1;
ctrl = 3'b000;
#100;
iA = 32'b1;
iB = 32'b0;
ctrl = 3'b000;
#100;
$finish;
end
endmodule | module alu32tb(); |
reg [31:0] iA;
reg [31:0] iB;
reg [2:0] ctrl;
wire [31:0]out;
wire oCarry;
alu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));
initial begin
iA = 32'b1;
iB = 32'b1;
ctrl = 3'b000;
#100;
iA = 32'b1;
iB = 32'b0;
ctrl = 3'b000;
#100;
$finish;
end
endmodule | 0 |
3,800 | data/full_repos/permissive/106966316/alu32_tb.v | 106,966,316 | alu32_tb.v | v | 129 | 83 | [] | [] | [] | [(23, 128)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#50 clk = 1\'b1;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#50 clk = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Error: data/full_repos/permissive/106966316/alu32_tb.v:33: Cannot find file containing module: \'alu32\'\nalu32 uut(\n^~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.sv\n alu32\n alu32.v\n alu32.sv\n obj_dir/alu32\n obj_dir/alu32.v\n obj_dir/alu32.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,584 | module | module alu32_tb();
reg [31:0] data1;
reg [31:0] data2;
reg [2:0] ctrl;
reg clk;
wire oCarry;
wire oZero;
wire [31:0]out;
alu32 uut(
.data1(data1),
.data2(data2),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
always begin
#50 clk = 1'b1;
#50 clk = 1'b0;
end
initial begin
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b000;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b000;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b001;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b001;
#100;
data1 = 32'b00000000_00000000_00000000_00000000;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b001;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b010;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00001000_00000000_00000000;
ctrl = 3'b010;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b011;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b011;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b100;
#100;
data1 = 32'b11111111_11111111_11111111_11111110;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b100;
#100;
end
endmodule | module alu32_tb(); |
reg [31:0] data1;
reg [31:0] data2;
reg [2:0] ctrl;
reg clk;
wire oCarry;
wire oZero;
wire [31:0]out;
alu32 uut(
.data1(data1),
.data2(data2),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
always begin
#50 clk = 1'b1;
#50 clk = 1'b0;
end
initial begin
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b000;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b000;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b001;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000001;
ctrl = 3'b001;
#100;
data1 = 32'b00000000_00000000_00000000_00000000;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b001;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b010;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00001000_00000000_00000000;
ctrl = 3'b010;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b011;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b011;
#100;
data1 = 32'b11111111_11111111_11111111_11111111;
data2 = 32'b11111111_11111111_11111111_11111111;
ctrl = 3'b100;
#100;
data1 = 32'b11111111_11111111_11111111_11111110;
data2 = 32'b00000000_00000000_00000000_00000000;
ctrl = 3'b100;
#100;
end
endmodule | 0 |
3,801 | data/full_repos/permissive/106966316/bankregister.v | 106,966,316 | bankregister.v | v | 68 | 83 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/60525767-a04b-4705-af08-c106986d18af.xml | null | 1,585 | module | module bankregister(
input [4:0] RegLe1,
input [4:0] RegLe2,
input [4:0] RegEscr,
input EscrReg,
input clk,
input [31:0] datain,
output wire [31:0] data1,
output wire [31:0] data2,
input reset
);
reg [31:0] register [31:0];
wire [31:0] aux;
assign data1 = register[RegLe1];
assign data2 = register[RegLe2];
always @(posedge clk )
begin
if(reset==1)
begin
register[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
register[1] = 32'b0000_0000_0000_0000_0000_0000_0000_0100;
register[2] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[3] = 32'b0000_0000_0000_0000_0000_0000_0000_1001;
register[4] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[6] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
else
register[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
register[RegEscr] = aux;
end
assign aux = (EscrReg==1) ? datain : register[RegEscr];
endmodule | module bankregister(
input [4:0] RegLe1,
input [4:0] RegLe2,
input [4:0] RegEscr,
input EscrReg,
input clk,
input [31:0] datain,
output wire [31:0] data1,
output wire [31:0] data2,
input reset
); |
reg [31:0] register [31:0];
wire [31:0] aux;
assign data1 = register[RegLe1];
assign data2 = register[RegLe2];
always @(posedge clk )
begin
if(reset==1)
begin
register[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
register[1] = 32'b0000_0000_0000_0000_0000_0000_0000_0100;
register[2] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[3] = 32'b0000_0000_0000_0000_0000_0000_0000_1001;
register[4] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[6] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
register[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
else
register[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
register[RegEscr] = aux;
end
assign aux = (EscrReg==1) ? datain : register[RegEscr];
endmodule | 0 |
3,802 | data/full_repos/permissive/106966316/bankregister_tb.v | 106,966,316 | bankregister_tb.v | v | 88 | 83 | [] | [] | [] | [(23, 86)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/bankregister_tb.v:35: Cannot find file containing module: \'bankregister\'\n bankregister uut(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister.sv\n bankregister\n bankregister.v\n bankregister.sv\n obj_dir/bankregister\n obj_dir/bankregister.v\n obj_dir/bankregister.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,586 | module | module bankregister_tb;
reg [5:0] RegLe1;
reg [5:0] RegLe2;
reg [5:0] RegEscr;
reg EscrReg;
reg clk;
reg [31:0] datain;
wire [31:0] data1;
wire [31:0] data2;
reg reset;
bankregister uut(
.RegLe1(RegLe1),
.RegLe2(RegLe2),
.RegEscr(RegEscr),
.EscrReg(EscrReg),
.clk(clk),
.datain(datain),
.data1(data1),
.data2(data2),
.reset(reset)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100;
reset = 1'b0;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000000;
#100;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain = 32'b00000000_00000000_00000000_10000101;
#100;
RegLe1 = 6'b000010;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000001;
#100;
end
endmodule | module bankregister_tb; |
reg [5:0] RegLe1;
reg [5:0] RegLe2;
reg [5:0] RegEscr;
reg EscrReg;
reg clk;
reg [31:0] datain;
wire [31:0] data1;
wire [31:0] data2;
reg reset;
bankregister uut(
.RegLe1(RegLe1),
.RegLe2(RegLe2),
.RegEscr(RegEscr),
.EscrReg(EscrReg),
.clk(clk),
.datain(datain),
.data1(data1),
.data2(data2),
.reset(reset)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100;
reset = 1'b0;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000000;
#100;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain = 32'b00000000_00000000_00000000_10000101;
#100;
RegLe1 = 6'b000010;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000001;
#100;
end
endmodule | 0 |
3,803 | data/full_repos/permissive/106966316/control.v | 106,966,316 | control.v | v | 64 | 106 | [] | [] | [] | [(23, 63)] | null | data/verilator_xmls/041874b1-10be-4659-963f-0c3972957d1d.xml | null | 1,587 | module | module control(Saltoincond,instru,clk,RegDest,SaltoCond,LeerMem,MemaReg,ALUOp,EscrMem,FuenteALU,EscrReg);
input [5:0]instru;
input clk;
output wire RegDest;
output wire SaltoCond;
output wire LeerMem;
output wire MemaReg;
output wire [1:0]ALUOp;
output wire EscrMem;
output wire FuenteALU;
output wire EscrReg;
output wire Saltoincond;
reg [9:0]aux;
always @ (*)
begin
case(instru)
6'b000_000: aux=10'b0100_100_010;
6'b100_011: aux=10'b00_1111_0000;
6'b101_011: aux=10'b0x1x001000;
6'b000_100: aux=10'b0x0x000101;
6'b111_111: aux=10'b00_1010_0000;
6'b111_110: aux=10'b00_0000_0101;
default: aux=10'b00_1010_0000;
endcase
end
assign Saltoincond = aux[9];
assign RegDest = aux[8];
assign FuenteALU = aux[7];
assign MemaReg = aux[6];
assign EscrReg = aux[5];
assign LeerMem = aux[4];
assign EscrMem = aux[3];
assign SaltoCond = aux[2];
assign ALUOp = aux[1:0];
endmodule | module control(Saltoincond,instru,clk,RegDest,SaltoCond,LeerMem,MemaReg,ALUOp,EscrMem,FuenteALU,EscrReg); |
input [5:0]instru;
input clk;
output wire RegDest;
output wire SaltoCond;
output wire LeerMem;
output wire MemaReg;
output wire [1:0]ALUOp;
output wire EscrMem;
output wire FuenteALU;
output wire EscrReg;
output wire Saltoincond;
reg [9:0]aux;
always @ (*)
begin
case(instru)
6'b000_000: aux=10'b0100_100_010;
6'b100_011: aux=10'b00_1111_0000;
6'b101_011: aux=10'b0x1x001000;
6'b000_100: aux=10'b0x0x000101;
6'b111_111: aux=10'b00_1010_0000;
6'b111_110: aux=10'b00_0000_0101;
default: aux=10'b00_1010_0000;
endcase
end
assign Saltoincond = aux[9];
assign RegDest = aux[8];
assign FuenteALU = aux[7];
assign MemaReg = aux[6];
assign EscrReg = aux[5];
assign LeerMem = aux[4];
assign EscrMem = aux[3];
assign SaltoCond = aux[2];
assign ALUOp = aux[1:0];
endmodule | 0 |
3,804 | data/full_repos/permissive/106966316/controlALU.v | 106,966,316 | controlALU.v | v | 58 | 83 | [] | [] | [] | [(23, 57)] | null | data/verilator_xmls/f23a0e9a-c952-4939-ad3d-5807f6b6488e.xml | null | 1,588 | module | module controlALU(
input [1:0] ALUop,
input [5:0] instru,
input clk,
output reg [2:0]contALU
);
always @(*)
begin
if (ALUop==2'b00)
begin
contALU= 3'b010;
end
else if (ALUop==2'b01)
begin
contALU= 3'b110;
end
else
begin
case (instru)
6'b100000:contALU= 3'b010;
6'b100010:contALU= 3'b110;
6'b100100:contALU= 3'b000;
6'b100101:contALU= 3'b001;
6'b101010:contALU= 3'b111;
default: contALU= 3'b101;
endcase
end
end
endmodule | module controlALU(
input [1:0] ALUop,
input [5:0] instru,
input clk,
output reg [2:0]contALU
); |
always @(*)
begin
if (ALUop==2'b00)
begin
contALU= 3'b010;
end
else if (ALUop==2'b01)
begin
contALU= 3'b110;
end
else
begin
case (instru)
6'b100000:contALU= 3'b010;
6'b100010:contALU= 3'b110;
6'b100100:contALU= 3'b000;
6'b100101:contALU= 3'b001;
6'b101010:contALU= 3'b111;
default: contALU= 3'b101;
endcase
end
end
endmodule | 0 |
3,805 | data/full_repos/permissive/106966316/controlALU_tb.v | 106,966,316 | controlALU_tb.v | v | 74 | 83 | [] | [] | [] | [(23, 73)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/controlALU_tb.v:29: Cannot find file containing module: \'controlALU\'\n controlALU uut(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU.sv\n controlALU\n controlALU.v\n controlALU.sv\n obj_dir/controlALU\n obj_dir/controlALU.v\n obj_dir/controlALU.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,589 | module | module controlALU_tb();
reg [1:0]ALUop;
reg [5:0]instru;
reg clk;
wire [2:0] contALU;
controlALU uut(
.ALUop(ALUop),
.instru(instru),
.clk(clk),
.contALU(contALU)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
ALUop=2'b00;
instru=6'bx1x_x1x;
#100;
ALUop=2'b00;
instru=6'b001_101;
#100;
ALUop=2'b01;
instru=6'b111_001;
#100;
ALUop=2'b10;
instru=6'b100000;
#100;
ALUop=2'b10;
instru=6'b100010;
#100;
ALUop=2'b10;
instru=6'b100100;
#100;
ALUop=2'b10;
instru=6'b100101;
#100;
ALUop=2'b10;
instru=6'b101010;
#100;
ALUop=2'b11;
instru=6'b111111;
end
endmodule | module controlALU_tb(); |
reg [1:0]ALUop;
reg [5:0]instru;
reg clk;
wire [2:0] contALU;
controlALU uut(
.ALUop(ALUop),
.instru(instru),
.clk(clk),
.contALU(contALU)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
ALUop=2'b00;
instru=6'bx1x_x1x;
#100;
ALUop=2'b00;
instru=6'b001_101;
#100;
ALUop=2'b01;
instru=6'b111_001;
#100;
ALUop=2'b10;
instru=6'b100000;
#100;
ALUop=2'b10;
instru=6'b100010;
#100;
ALUop=2'b10;
instru=6'b100100;
#100;
ALUop=2'b10;
instru=6'b100101;
#100;
ALUop=2'b10;
instru=6'b101010;
#100;
ALUop=2'b11;
instru=6'b111111;
end
endmodule | 0 |
3,806 | data/full_repos/permissive/106966316/control_tb.v | 106,966,316 | control_tb.v | v | 73 | 83 | [] | [] | [] | [(23, 72)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/control_tb.v:36: Cannot find file containing module: \'control\'\n control uut(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control.sv\n control\n control.v\n control.sv\n obj_dir/control\n obj_dir/control.v\n obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,590 | module | module control_tb();
reg [5:0] instru;
reg clk;
wire RegDest;
wire SaltoCond;
wire LeerMem;
wire MemaReg;
wire [1:0] ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
control uut(
.instru(instru),
.clk(clk),
.RegDest(RegDest),
.SaltoCond(SaltoCond),
.LeerMem(LeerMem),
.MemaReg(MemaReg),
.ALUOp(ALUOp),
.EscrMem(EscrMem),
.FuenteALU(FuenteALU),
.EscrReg(EscrReg)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
instru=6'b000000;
#100
instru=6'b000000;
#100
instru=6'b100011;
#100
instru=6'b101011;
#100
instru=6'b000100;
#100;
end
endmodule | module control_tb(); |
reg [5:0] instru;
reg clk;
wire RegDest;
wire SaltoCond;
wire LeerMem;
wire MemaReg;
wire [1:0] ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
control uut(
.instru(instru),
.clk(clk),
.RegDest(RegDest),
.SaltoCond(SaltoCond),
.LeerMem(LeerMem),
.MemaReg(MemaReg),
.ALUOp(ALUOp),
.EscrMem(EscrMem),
.FuenteALU(FuenteALU),
.EscrReg(EscrReg)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
instru=6'b000000;
#100
instru=6'b000000;
#100
instru=6'b100011;
#100
instru=6'b101011;
#100
instru=6'b000100;
#100;
end
endmodule | 0 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.