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3,908 | data/full_repos/permissive/107499099/mips_de2-115/V/vga_controller.v | 107,499,099 | vga_controller.v | v | 89 | 53 | [] | [] | [] | [(1, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/107499099/mips_de2-115/V/vga_controller.v:26: Cannot find file containing module: 'video_sync_generator'\nvideo_sync_generator LTM_ins (.vga_clk(iVGA_CLK),\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115/V,data/full_repos/permissive/107499099/video_sync_generator\n data/full_repos/permissive/107499099/mips_de2-115/V,data/full_repos/permissive/107499099/video_sync_generator.v\n data/full_repos/permissive/107499099/mips_de2-115/V,data/full_repos/permissive/107499099/video_sync_generator.sv\n video_sync_generator\n video_sync_generator.v\n video_sync_generator.sv\n obj_dir/video_sync_generator\n obj_dir/video_sync_generator.v\n obj_dir/video_sync_generator.sv\n%Error: data/full_repos/permissive/107499099/mips_de2-115/V/vga_controller.v:45: Cannot find file containing module: 'img_data'\nimg_data img_data_inst (\n^~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/V/vga_controller.v:51: Cannot find file containing module: 'img_index'\nimg_index img_index_inst (\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 1,709 | module | module vga_controller(iRST_n,
iVGA_CLK,
oBLANK_n,
oHS,
oVS,
b_data,
g_data,
r_data);
input iRST_n;
input iVGA_CLK;
output reg oBLANK_n;
output reg oHS;
output reg oVS;
output [7:0] b_data;
output [7:0] g_data;
output [7:0] r_data;
reg [18:0] ADDR;
reg [23:0] bgr_data;
wire VGA_CLK_n;
wire [7:0] index;
wire [23:0] bgr_data_raw;
wire cBLANK_n,cHS,cVS,rst;
assign rst = ~iRST_n;
video_sync_generator LTM_ins (.vga_clk(iVGA_CLK),
.reset(rst),
.blank_n(cBLANK_n),
.HS(cHS),
.VS(cVS));
always@(posedge iVGA_CLK,negedge iRST_n)
begin
if (!iRST_n)
ADDR<=19'd0;
else if (cHS==1'b0 && cVS==1'b0)
ADDR<=19'd0;
else if (cBLANK_n==1'b1)
ADDR<=ADDR+1;
end
assign VGA_CLK_n = ~iVGA_CLK;
img_data img_data_inst (
.address ( ADDR ),
.clock ( VGA_CLK_n ),
.q ( index )
);
img_index img_index_inst (
.address ( index ),
.clock ( iVGA_CLK ),
.q ( bgr_data_raw)
);
always@(posedge VGA_CLK_n) bgr_data <= bgr_data_raw;
assign b_data = bgr_data[23:16];
assign g_data = bgr_data[15:8];
assign r_data = bgr_data[7:0];
always@(negedge iVGA_CLK)
begin
oHS<=cHS;
oVS<=cVS;
oBLANK_n<=cBLANK_n;
end
endmodule | module vga_controller(iRST_n,
iVGA_CLK,
oBLANK_n,
oHS,
oVS,
b_data,
g_data,
r_data); |
input iRST_n;
input iVGA_CLK;
output reg oBLANK_n;
output reg oHS;
output reg oVS;
output [7:0] b_data;
output [7:0] g_data;
output [7:0] r_data;
reg [18:0] ADDR;
reg [23:0] bgr_data;
wire VGA_CLK_n;
wire [7:0] index;
wire [23:0] bgr_data_raw;
wire cBLANK_n,cHS,cVS,rst;
assign rst = ~iRST_n;
video_sync_generator LTM_ins (.vga_clk(iVGA_CLK),
.reset(rst),
.blank_n(cBLANK_n),
.HS(cHS),
.VS(cVS));
always@(posedge iVGA_CLK,negedge iRST_n)
begin
if (!iRST_n)
ADDR<=19'd0;
else if (cHS==1'b0 && cVS==1'b0)
ADDR<=19'd0;
else if (cBLANK_n==1'b1)
ADDR<=ADDR+1;
end
assign VGA_CLK_n = ~iVGA_CLK;
img_data img_data_inst (
.address ( ADDR ),
.clock ( VGA_CLK_n ),
.q ( index )
);
img_index img_index_inst (
.address ( index ),
.clock ( iVGA_CLK ),
.q ( bgr_data_raw)
);
always@(posedge VGA_CLK_n) bgr_data <= bgr_data_raw;
assign b_data = bgr_data[23:16];
assign g_data = bgr_data[15:8];
assign r_data = bgr_data[7:0];
always@(negedge iVGA_CLK)
begin
oHS<=cHS;
oVS<=cVS;
oBLANK_n<=cBLANK_n;
end
endmodule | 0 |
3,909 | data/full_repos/permissive/107660616/Altera/EDAC_SDRAM_Controller_Demo/EDAC_SDRAM_Controller_Demo_bb.v | 107,660,616 | EDAC_SDRAM_Controller_Demo_bb.v | v | 55 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/231a1ccb-0758-4c0b-a5a9-000c69946a8e.xml | null | 1,735 | module | module EDAC_SDRAM_Controller_Demo (
debug_err_counter_o,
debug_err_detect_o,
debug_healing_proc_run_o,
debug_mem_ready_o,
debug_scrubbing_proc_run_o,
debug_voted_data_o,
sdram_cke_o,
sdram_bank_o,
sdram_addr_o,
sdram_cs_o,
sdram_ras_o,
sdram_cas_o,
sdram_we_o,
sdram_dqm_o,
sdram_dataQ_io,
sevensegment_hex7,
sevensegment_hex6,
sevensegment_hex5,
sevensegment_hex4,
sevensegment_hex3,
sevensegment_hex2,
sevensegment_hex1,
sevensegment_hex0,
sys_clk_clk,
sys_rst_reset_n);
output [31:0] debug_err_counter_o;
output debug_err_detect_o;
output debug_healing_proc_run_o;
output debug_mem_ready_o;
output debug_scrubbing_proc_run_o;
output [31:0] debug_voted_data_o;
output sdram_cke_o;
output [1:0] sdram_bank_o;
output [12:0] sdram_addr_o;
output sdram_cs_o;
output sdram_ras_o;
output sdram_cas_o;
output sdram_we_o;
output [3:0] sdram_dqm_o;
inout [31:0] sdram_dataQ_io;
output [6:0] sevensegment_hex7;
output [6:0] sevensegment_hex6;
output [6:0] sevensegment_hex5;
output [6:0] sevensegment_hex4;
output [6:0] sevensegment_hex3;
output [6:0] sevensegment_hex2;
output [6:0] sevensegment_hex1;
output [6:0] sevensegment_hex0;
input sys_clk_clk;
input sys_rst_reset_n;
endmodule | module EDAC_SDRAM_Controller_Demo (
debug_err_counter_o,
debug_err_detect_o,
debug_healing_proc_run_o,
debug_mem_ready_o,
debug_scrubbing_proc_run_o,
debug_voted_data_o,
sdram_cke_o,
sdram_bank_o,
sdram_addr_o,
sdram_cs_o,
sdram_ras_o,
sdram_cas_o,
sdram_we_o,
sdram_dqm_o,
sdram_dataQ_io,
sevensegment_hex7,
sevensegment_hex6,
sevensegment_hex5,
sevensegment_hex4,
sevensegment_hex3,
sevensegment_hex2,
sevensegment_hex1,
sevensegment_hex0,
sys_clk_clk,
sys_rst_reset_n); |
output [31:0] debug_err_counter_o;
output debug_err_detect_o;
output debug_healing_proc_run_o;
output debug_mem_ready_o;
output debug_scrubbing_proc_run_o;
output [31:0] debug_voted_data_o;
output sdram_cke_o;
output [1:0] sdram_bank_o;
output [12:0] sdram_addr_o;
output sdram_cs_o;
output sdram_ras_o;
output sdram_cas_o;
output sdram_we_o;
output [3:0] sdram_dqm_o;
inout [31:0] sdram_dataQ_io;
output [6:0] sevensegment_hex7;
output [6:0] sevensegment_hex6;
output [6:0] sevensegment_hex5;
output [6:0] sevensegment_hex4;
output [6:0] sevensegment_hex3;
output [6:0] sevensegment_hex2;
output [6:0] sevensegment_hex1;
output [6:0] sevensegment_hex0;
input sys_clk_clk;
input sys_rst_reset_n;
endmodule | 8 |
3,910 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/datarate.v | 107,735,152 | datarate.v | v | 24 | 81 | [] | [] | [] | [(1, 24)] | null | data/verilator_xmls/05fb7d41-5cc0-4c95-886a-fcc688bfff45.xml | null | 2,105 | module | module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);
input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;
reg switch;
reg init = 1;
assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;
always @(samplePoint)
begin
if (init) begin
init <= 0;
switch <= 0;
end else begin
if (edl & brs & brsStop)
switch <= edl & brs & brsStop;
else
switch <= 0;
end
end
endmodule | module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT); |
input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;
reg switch;
reg init = 1;
assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;
always @(samplePoint)
begin
if (init) begin
init <= 0;
switch <= 0;
end else begin
if (edl & brs & brsStop)
switch <= edl & brs & brsStop;
else
switch <= 0;
end
end
endmodule | 0 |
3,911 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/DatavsRemote.v | 107,735,152 | DatavsRemote.v | v | 11 | 46 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/11d995f7-3bfa-4275-98cd-55a647fc5765.xml | null | 2,106 | module | module DatavsRemote(
RTR_SRR,
IDE,
RTR_r1,
isRemote
);
input RTR_SRR, IDE, RTR_r1;
output isRemote;
assign isRemote = RTR_SRR & (IDE ~^ RTR_r1);
endmodule | module DatavsRemote(
RTR_SRR,
IDE,
RTR_r1,
isRemote
); |
input RTR_SRR, IDE, RTR_r1;
output isRemote;
assign isRemote = RTR_SRR & (IDE ~^ RTR_r1);
endmodule | 0 |
3,912 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v | 107,735,152 | framecontroller.v | v | 335 | 84 | [] | [] | [] | [(4, 334)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:180: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'CAN_RX\' generates 1 bits.\n : ... In instance framecontroller\n dlc = dlc + CAN_RX;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:192: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh10\' generates 32 or 5 bits.\n : ... In instance framecontroller\n dlc = 16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:194: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh14\' generates 32 or 5 bits.\n : ... In instance framecontroller\n dlc = 20;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:196: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh18\' generates 32 or 5 bits.\n : ... In instance framecontroller\n dlc = 24;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:198: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh20\' generates 32 or 6 bits.\n : ... In instance framecontroller\n dlc = 32;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:200: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh30\' generates 32 or 6 bits.\n : ... In instance framecontroller\n dlc = 48;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:202: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh40\' generates 32 or 7 bits.\n : ... In instance framecontroller\n dlc = 64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:214: Operator LTE expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'dlc\' generates 4 bits.\n : ... In instance framecontroller\n else if(dlc <= 16)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/framecontroller.v:238: Operator LTE expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'dlc\' generates 4 bits.\n : ... In instance framecontroller\n else if(dlc <= 16)\n ^~\n%Error: Exiting due to 9 warning(s)\n' | 2,107 | module | module framecontroller
(
input sp, CAN_RX, reset, isStuff, errorFlag,
output reg BS_onoff,
output reg [1:0]CRCtype,
output reg BRS_Stop,
output reg invalidBit,
output reg CRCcalc_on,
output reg CRCtime,
output reg ackValue,
output reg RTR_SRR,
output reg IDE,
output reg EDL,
output reg BRS,
output reg RTR_r1,
output reg frameReady
);
parameter arbID_st = 0, RTR_SRR_st = 1, IDE0_st = 2, IDE1_st = 3, r0_EDL_st = 4;
parameter extID_st = 5, extRTR_st = 6, r1_EDL_st = 7, r0_FD_st = 8, BRS_st = 9;
parameter ESI_st = 10, DLC_st = 11, data_st = 12, crc15_st = 13, crc17_st = 14;
parameter crc21_st = 15, crcDel_st = 16, ack_st = 17, ackDel_st = 18, eof_st = 19;
parameter ready_st = 20, error_st = 21;
reg [4:0]state = ready_st;
reg [7:0]cont;
reg [3:0]dlc;
reg FD;
reg bitlido;
always @ (posedge sp) begin
if (reset) begin
state <= arbID_st;
cont = 1;
dlc = 0;
FD = 0;
BS_onoff = 0;
CRCtype = 0;
CRCtime = 0;
CRCcalc_on = 0;
BRS_Stop = 0;
invalidBit = 0;
ackValue = 0;
RTR_SRR = 0;
IDE = 0;
EDL = 0;
BRS = 0;
RTR_r1 = 0;
frameReady = 0;
BS_onoff = 1;
CRCcalc_on = 1;
if(errorFlag)
begin
state <= error_st;
end
end
else
if (~isStuff) begin
case (state)
arbID_st:
begin
if(cont < 10)
begin
cont = cont +1;
end
else
begin
state <= RTR_SRR_st;
end
end
RTR_SRR_st:
begin
RTR_SRR = CAN_RX;
if (CAN_RX)
begin
state <= IDE1_st;
end
else
begin
state <= IDE0_st;
end
end
IDE0_st:
begin
IDE = CAN_RX;
if(~CAN_RX)
begin
state <= r0_EDL_st;
end
else
begin
state <= error_st;
end
end
IDE1_st:
begin
IDE = CAN_RX;
if (CAN_RX)
begin
cont = 0;
state <= extID_st;
end
else
begin
state <= r0_EDL_st;
end
end
extID_st:
if (cont < 17)
begin
cont = cont + 1;
end
else
begin
state <= extRTR_st;
end
extRTR_st:
begin
RTR_r1 = CAN_RX;
state <= r1_EDL_st;
end
r1_EDL_st:
begin
EDL = CAN_RX;
if (CAN_RX)
begin
state <= r0_FD_st;
end
else
begin
state <= r0_EDL_st;
end
end
r0_EDL_st:
begin
EDL = CAN_RX;
if (CAN_RX)
begin
state <= r0_FD_st;
end
else
begin
cont = 0;
state <= DLC_st;
end
end
r0_FD_st:
if(~CAN_RX)
begin
FD = 1;
state <= BRS_st;
end
else
begin
state <= error_st;
end
BRS_st:
begin
BRS = CAN_RX;
BRS_Stop = CAN_RX;
state <= ESI_st;
end
ESI_st:
begin
cont = 0;
state <= DLC_st;
end
DLC_st:
begin
dlc = dlc << 1;
dlc = dlc + CAN_RX;
cont = cont + 1;
bitlido = CAN_RX;
if (cont == 4 && dlc != 0)
begin
cont = 0;
if(dlc > 8)
begin
case(dlc)
9:
dlc = 12;
10:
dlc = 16;
11:
dlc = 20;
12:
dlc = 24;
13:
dlc = 32;
14:
dlc = 48;
15:
dlc = 64;
endcase
end
state <= data_st;
end
else if(cont == 4 && dlc == 0)
begin
cont =0;
if(FD == 0)
begin
state <= crc15_st;
end
else if(dlc <= 16)
begin
state <= crc17_st;
end
else
begin
state <= crc21_st;
end
end
end
data_st:
begin
if(FD)
begin
BRS_Stop = 1;
end
cont = cont + 1;
if (cont==8*dlc)
begin
if(FD == 0)
begin
cont = 0;
state <= crc15_st;
end
else if(dlc <= 16)
begin
cont = 0;
state <= crc17_st;
end
else
begin
cont = 0;
state <= crc21_st;
end
end
end
crc15_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 1;
cont = cont +1;
if (cont==15)
begin
state <= crcDel_st;
end
end
crc17_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 2;
cont = cont +1;
if (cont==17)
begin
state <= crcDel_st;
end
end
crc21_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 3;
cont = cont +1;
if (cont==21)
begin
state <= crcDel_st;
end
end
crcDel_st:
begin
CRCtime = 0;
CRCtype = 0;
BS_onoff = 0;
BRS_Stop = 0;
if(CAN_RX)
begin
state <= ack_st;
end
else
begin
state <= error_st;
end
end
ack_st:
state <= ackDel_st;
ackDel_st:
if(CAN_RX)
begin
cont = 0;
state <= eof_st;
end
else
begin
state <= error_st;
end
eof_st:
begin
cont = cont +1;
if(cont==7)
begin
frameReady = 1;
state <= ready_st;
end
end
ready_st:
begin
frameReady = 1;
state <= ready_st;
end
error_st:
begin
cont = 0;
dlc = 0;
FD = 0;
end
endcase
end
end
endmodule | module framecontroller
(
input sp, CAN_RX, reset, isStuff, errorFlag,
output reg BS_onoff,
output reg [1:0]CRCtype,
output reg BRS_Stop,
output reg invalidBit,
output reg CRCcalc_on,
output reg CRCtime,
output reg ackValue,
output reg RTR_SRR,
output reg IDE,
output reg EDL,
output reg BRS,
output reg RTR_r1,
output reg frameReady
); |
parameter arbID_st = 0, RTR_SRR_st = 1, IDE0_st = 2, IDE1_st = 3, r0_EDL_st = 4;
parameter extID_st = 5, extRTR_st = 6, r1_EDL_st = 7, r0_FD_st = 8, BRS_st = 9;
parameter ESI_st = 10, DLC_st = 11, data_st = 12, crc15_st = 13, crc17_st = 14;
parameter crc21_st = 15, crcDel_st = 16, ack_st = 17, ackDel_st = 18, eof_st = 19;
parameter ready_st = 20, error_st = 21;
reg [4:0]state = ready_st;
reg [7:0]cont;
reg [3:0]dlc;
reg FD;
reg bitlido;
always @ (posedge sp) begin
if (reset) begin
state <= arbID_st;
cont = 1;
dlc = 0;
FD = 0;
BS_onoff = 0;
CRCtype = 0;
CRCtime = 0;
CRCcalc_on = 0;
BRS_Stop = 0;
invalidBit = 0;
ackValue = 0;
RTR_SRR = 0;
IDE = 0;
EDL = 0;
BRS = 0;
RTR_r1 = 0;
frameReady = 0;
BS_onoff = 1;
CRCcalc_on = 1;
if(errorFlag)
begin
state <= error_st;
end
end
else
if (~isStuff) begin
case (state)
arbID_st:
begin
if(cont < 10)
begin
cont = cont +1;
end
else
begin
state <= RTR_SRR_st;
end
end
RTR_SRR_st:
begin
RTR_SRR = CAN_RX;
if (CAN_RX)
begin
state <= IDE1_st;
end
else
begin
state <= IDE0_st;
end
end
IDE0_st:
begin
IDE = CAN_RX;
if(~CAN_RX)
begin
state <= r0_EDL_st;
end
else
begin
state <= error_st;
end
end
IDE1_st:
begin
IDE = CAN_RX;
if (CAN_RX)
begin
cont = 0;
state <= extID_st;
end
else
begin
state <= r0_EDL_st;
end
end
extID_st:
if (cont < 17)
begin
cont = cont + 1;
end
else
begin
state <= extRTR_st;
end
extRTR_st:
begin
RTR_r1 = CAN_RX;
state <= r1_EDL_st;
end
r1_EDL_st:
begin
EDL = CAN_RX;
if (CAN_RX)
begin
state <= r0_FD_st;
end
else
begin
state <= r0_EDL_st;
end
end
r0_EDL_st:
begin
EDL = CAN_RX;
if (CAN_RX)
begin
state <= r0_FD_st;
end
else
begin
cont = 0;
state <= DLC_st;
end
end
r0_FD_st:
if(~CAN_RX)
begin
FD = 1;
state <= BRS_st;
end
else
begin
state <= error_st;
end
BRS_st:
begin
BRS = CAN_RX;
BRS_Stop = CAN_RX;
state <= ESI_st;
end
ESI_st:
begin
cont = 0;
state <= DLC_st;
end
DLC_st:
begin
dlc = dlc << 1;
dlc = dlc + CAN_RX;
cont = cont + 1;
bitlido = CAN_RX;
if (cont == 4 && dlc != 0)
begin
cont = 0;
if(dlc > 8)
begin
case(dlc)
9:
dlc = 12;
10:
dlc = 16;
11:
dlc = 20;
12:
dlc = 24;
13:
dlc = 32;
14:
dlc = 48;
15:
dlc = 64;
endcase
end
state <= data_st;
end
else if(cont == 4 && dlc == 0)
begin
cont =0;
if(FD == 0)
begin
state <= crc15_st;
end
else if(dlc <= 16)
begin
state <= crc17_st;
end
else
begin
state <= crc21_st;
end
end
end
data_st:
begin
if(FD)
begin
BRS_Stop = 1;
end
cont = cont + 1;
if (cont==8*dlc)
begin
if(FD == 0)
begin
cont = 0;
state <= crc15_st;
end
else if(dlc <= 16)
begin
cont = 0;
state <= crc17_st;
end
else
begin
cont = 0;
state <= crc21_st;
end
end
end
crc15_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 1;
cont = cont +1;
if (cont==15)
begin
state <= crcDel_st;
end
end
crc17_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 2;
cont = cont +1;
if (cont==17)
begin
state <= crcDel_st;
end
end
crc21_st:
begin
CRCcalc_on =0;
CRCtime = 1;
CRCtype = 3;
cont = cont +1;
if (cont==21)
begin
state <= crcDel_st;
end
end
crcDel_st:
begin
CRCtime = 0;
CRCtype = 0;
BS_onoff = 0;
BRS_Stop = 0;
if(CAN_RX)
begin
state <= ack_st;
end
else
begin
state <= error_st;
end
end
ack_st:
state <= ackDel_st;
ackDel_st:
if(CAN_RX)
begin
cont = 0;
state <= eof_st;
end
else
begin
state <= error_st;
end
eof_st:
begin
cont = cont +1;
if(cont==7)
begin
frameReady = 1;
state <= ready_st;
end
end
ready_st:
begin
frameReady = 1;
state <= ready_st;
end
error_st:
begin
cont = 0;
dlc = 0;
FD = 0;
end
endcase
end
end
endmodule | 0 |
3,913 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v | 107,735,152 | frameMakerTop.v | v | 19 | 220 | [] | [] | [] | [(1, 19)] | null | null | 1: b"%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:11: Cannot find file containing module: 'datarate'\n datarate dt(samplePoint, samplePointFD, EDL, BRS, BRS_Stop, samplePointOUT);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/datarate\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/datarate.v\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/datarate.sv\n datarate\n datarate.v\n datarate.sv\n obj_dir/datarate\n obj_dir/datarate.v\n obj_dir/datarate.sv\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:12: Cannot find file containing module: 'interFrameSpace'\n interFrameSpace ifs (samplePointOUT, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:13: Cannot find file containing module: 'overload'\n overload ov (samplePointOUT, canRX, isOverloadFromInterframe, isError, endOverload);\n ^~~~~~~~\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:14: Cannot find file containing module: 'framecontroller'\n framecontroller fc (samplePointOUT, canRX, isStart, isStuff, isError, BS_onoff, CRCtype, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, RTR_SRR, IDE, EDL, BRS, RTR_r1, frameReady);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:15: Cannot find file containing module: 'DatavsRemote'\n DatavsRemote dr (RTR_SRR, IDE, RTR_r1, isRemote);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:16: Cannot find file containing module: 'frameSize'\n frameSize fsz (samplePointOUT, isStuff, isStart, size);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop.v:17: Cannot find file containing module: 'frameStorage'\n frameStorage fst (samplePointOUT, canRX, isStuff, isStart, frame);\n ^~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 2,108 | module | module frameMakerTop (samplePoint, samplePointFD, canRX, isError, isStuff, endOverload, BS_onoff, CRCtype, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, IDE, EDL, BRS, isRemote, size, frame, frameReady, isStart);
input wire samplePoint, samplePointFD, canRX, isError, isStuff;
output wire endOverload, BS_onoff, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, IDE, EDL, BRS, isRemote, frameReady, isStart;
output wire [1:0] CRCtype;
output wire [9:0] size;
output wire [150:0] frame;
wire isOverloadFromInterframe, samplePointOUT, RTR_SRR, RTR_r1;
datarate dt(samplePoint, samplePointFD, EDL, BRS, BRS_Stop, samplePointOUT);
interFrameSpace ifs (samplePointOUT, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);
overload ov (samplePointOUT, canRX, isOverloadFromInterframe, isError, endOverload);
framecontroller fc (samplePointOUT, canRX, isStart, isStuff, isError, BS_onoff, CRCtype, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, RTR_SRR, IDE, EDL, BRS, RTR_r1, frameReady);
DatavsRemote dr (RTR_SRR, IDE, RTR_r1, isRemote);
frameSize fsz (samplePointOUT, isStuff, isStart, size);
frameStorage fst (samplePointOUT, canRX, isStuff, isStart, frame);
endmodule | module frameMakerTop (samplePoint, samplePointFD, canRX, isError, isStuff, endOverload, BS_onoff, CRCtype, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, IDE, EDL, BRS, isRemote, size, frame, frameReady, isStart); |
input wire samplePoint, samplePointFD, canRX, isError, isStuff;
output wire endOverload, BS_onoff, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, IDE, EDL, BRS, isRemote, frameReady, isStart;
output wire [1:0] CRCtype;
output wire [9:0] size;
output wire [150:0] frame;
wire isOverloadFromInterframe, samplePointOUT, RTR_SRR, RTR_r1;
datarate dt(samplePoint, samplePointFD, EDL, BRS, BRS_Stop, samplePointOUT);
interFrameSpace ifs (samplePointOUT, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);
overload ov (samplePointOUT, canRX, isOverloadFromInterframe, isError, endOverload);
framecontroller fc (samplePointOUT, canRX, isStart, isStuff, isError, BS_onoff, CRCtype, BRS_Stop, invalidBit, CRCcalc_on, CRCtime, ackValue, RTR_SRR, IDE, EDL, BRS, RTR_r1, frameReady);
DatavsRemote dr (RTR_SRR, IDE, RTR_r1, isRemote);
frameSize fsz (samplePointOUT, isStuff, isStart, size);
frameStorage fst (samplePointOUT, canRX, isStuff, isStart, frame);
endmodule | 0 |
3,914 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v | 107,735,152 | frameMakerTop_TB.v | v | 62 | 280 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 samplePoint_tb = ~samplePoint_tb;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1 samplePointFD_tb = ~samplePointFD_tb;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5 canRX_tb = messageTest[124];\n ^\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:11: Cannot find file containing module: \'frameMakerTop\'\n frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop.v\n data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop.sv\n frameMakerTop\n frameMakerTop.v\n frameMakerTop.sv\n obj_dir/frameMakerTop\n obj_dir/frameMakerTop.v\n obj_dir/frameMakerTop.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,109 | module | module frameMakerTop_TB();
reg [124:0] messageTest;
reg samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb;
wire endOverload_tb, BS_onoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, frameReady_tb, isStart_tb;
wire [1:0] CRCtype_tb;
wire [9:0] size_tb;
wire [150:0] frame_tb;
frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);
initial
begin
$stop;
canRX_tb = 1'b1;
samplePoint_tb = 1'b1;
samplePointFD_tb = 1'b0;
isStuff_tb = 1'b0;
isError_tb = 1'b0;
messageTest = 125'b11011001001001000000110101010010101010101010111111111111101100100100110000000101010101010101111111111100000011111111111110111;
end
always
begin
#5 samplePoint_tb = ~samplePoint_tb;
#1 samplePointFD_tb = ~samplePointFD_tb;
end
always @(posedge samplePoint_tb)
begin
if(messageTest != 0)
begin
#5 canRX_tb = messageTest[124];
messageTest <= messageTest << 1;
end
else
begin
$stop;
end
end
endmodule | module frameMakerTop_TB(); |
reg [124:0] messageTest;
reg samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb;
wire endOverload_tb, BS_onoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, frameReady_tb, isStart_tb;
wire [1:0] CRCtype_tb;
wire [9:0] size_tb;
wire [150:0] frame_tb;
frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);
initial
begin
$stop;
canRX_tb = 1'b1;
samplePoint_tb = 1'b1;
samplePointFD_tb = 1'b0;
isStuff_tb = 1'b0;
isError_tb = 1'b0;
messageTest = 125'b11011001001001000000110101010010101010101010111111111111101100100100110000000101010101010101111111111100000011111111111110111;
end
always
begin
#5 samplePoint_tb = ~samplePoint_tb;
#1 samplePointFD_tb = ~samplePointFD_tb;
end
always @(posedge samplePoint_tb)
begin
if(messageTest != 0)
begin
#5 canRX_tb = messageTest[124];
messageTest <= messageTest << 1;
end
else
begin
$stop;
end
end
endmodule | 0 |
3,915 | data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/overload.v | 107,735,152 | overload.v | v | 94 | 104 | [] | [] | [] | [(1, 94)] | null | data/verilator_xmls/3a770e60-79c2-4a4f-b472-d82f1cd9faca.xml | null | 2,113 | module | module overload (samplePoint, canRX, isOverload, isError, endOverload);
input wire samplePoint, canRX, isOverload, isError;
output wire endOverload;
parameter overload_flag = 0, overload_superposition = 1, overload_delimiter = 2;
reg [1:0]state = overload_flag;
reg [4:0]count = 0;
reg endOverload0 = 0;
reg alredyOverError = 0;
assign endOverload = endOverload0;
always @ (posedge samplePoint) begin
if (endOverload0) begin
endOverload0 <= 0;
end
if (isOverload == 1 || isError == 1 || alredyOverError == 1) begin
case (state)
overload_flag:
if (isOverload == 1 || alredyOverError == 1) begin
if (canRX == 0) begin
if (count == 4) begin
state <= overload_superposition;
count <= count + 1;
end else begin
alredyOverError <= 1;
count <= count + 1;
end
end else if (canRX == 1) begin
alredyOverError <= 1;
count <= 0;
state <= overload_flag;
end
end else if (isError == 1 || alredyOverError == 1) begin
if (canRX == 0) begin
if (count == 5) begin
state <= overload_superposition;
count <= count + 1;
end else begin
alredyOverError <= 1;
count <= count + 1;
end
end else if (canRX == 1) begin
alredyOverError <= 1;
count <= 0;
state <= overload_flag;
end
end
overload_superposition:
if (canRX == 0) begin
if (count < 11) begin
count <= count + 1;
end else begin
count <= 0;
state <= overload_flag;
end
end else if (canRX == 1) begin
state <= overload_delimiter;
count <= 1;
end
overload_delimiter:
if (canRX == 1) begin
if (count < 7) begin
count <= count + 1;
end else begin
endOverload0 <= 1;
alredyOverError <= 0;
state <= overload_flag;
count <= 0;
end
end else if (canRX == 0) begin
if (count == 7) begin
state <= overload_flag;
count <= 1;
end else begin
count <= 0;
state <= overload_flag;
end
end
endcase
end
end
endmodule | module overload (samplePoint, canRX, isOverload, isError, endOverload); |
input wire samplePoint, canRX, isOverload, isError;
output wire endOverload;
parameter overload_flag = 0, overload_superposition = 1, overload_delimiter = 2;
reg [1:0]state = overload_flag;
reg [4:0]count = 0;
reg endOverload0 = 0;
reg alredyOverError = 0;
assign endOverload = endOverload0;
always @ (posedge samplePoint) begin
if (endOverload0) begin
endOverload0 <= 0;
end
if (isOverload == 1 || isError == 1 || alredyOverError == 1) begin
case (state)
overload_flag:
if (isOverload == 1 || alredyOverError == 1) begin
if (canRX == 0) begin
if (count == 4) begin
state <= overload_superposition;
count <= count + 1;
end else begin
alredyOverError <= 1;
count <= count + 1;
end
end else if (canRX == 1) begin
alredyOverError <= 1;
count <= 0;
state <= overload_flag;
end
end else if (isError == 1 || alredyOverError == 1) begin
if (canRX == 0) begin
if (count == 5) begin
state <= overload_superposition;
count <= count + 1;
end else begin
alredyOverError <= 1;
count <= count + 1;
end
end else if (canRX == 1) begin
alredyOverError <= 1;
count <= 0;
state <= overload_flag;
end
end
overload_superposition:
if (canRX == 0) begin
if (count < 11) begin
count <= count + 1;
end else begin
count <= 0;
state <= overload_flag;
end
end else if (canRX == 1) begin
state <= overload_delimiter;
count <= 1;
end
overload_delimiter:
if (canRX == 1) begin
if (count < 7) begin
count <= count + 1;
end else begin
endOverload0 <= 1;
alredyOverError <= 0;
state <= overload_flag;
count <= 0;
end
end else if (canRX == 0) begin
if (count == 7) begin
state <= overload_flag;
count <= 1;
end else begin
count <= 0;
state <= overload_flag;
end
end
endcase
end
end
endmodule | 0 |
3,916 | data/full_repos/permissive/107735152/src/bitstuffing.v | 107,735,152 | bitstuffing.v | v | 61 | 69 | [] | [] | [] | null | line:8: before: "," | data/verilator_xmls/b19d4b5f-35c8-4c93-98cf-f7d48d995fcd.xml | null | 2,114 | module | module bitstuffing (samplePoint, canRX, bsOnOff, stuffing, bsError);
input wire samplePoint, canRX, bsOnOff;
output wire stuffing, bsError;
reg [2:0]count = 3'b000;
reg mem = 0;
reg stuffing0 = 0, bsError0 = 0;
reg debug = 0;
assign stuffing = stuffing0;
assign bsError = bsError0;
always @ (posedge samplePoint) begin
if (bsOnOff == 1'b1) begin
if (canRX == mem) begin
if (count == 3'b101) begin
bsError0 <= 1'b1;
stuffing0 <= 1'b0;
count <= 3'b000;
end else begin
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
count <= count + 1;
end
end else begin
if (count == 5) begin
bsError0 <= 1'b0;
stuffing0 <= 1'b1;
count <= 3'b000;
end else begin
mem <= canRX;
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
count <= 3'b001;
end
end
end else begin
count <= 3'b000;
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
end
end
endmodule | module bitstuffing (samplePoint, canRX, bsOnOff, stuffing, bsError); |
input wire samplePoint, canRX, bsOnOff;
output wire stuffing, bsError;
reg [2:0]count = 3'b000;
reg mem = 0;
reg stuffing0 = 0, bsError0 = 0;
reg debug = 0;
assign stuffing = stuffing0;
assign bsError = bsError0;
always @ (posedge samplePoint) begin
if (bsOnOff == 1'b1) begin
if (canRX == mem) begin
if (count == 3'b101) begin
bsError0 <= 1'b1;
stuffing0 <= 1'b0;
count <= 3'b000;
end else begin
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
count <= count + 1;
end
end else begin
if (count == 5) begin
bsError0 <= 1'b0;
stuffing0 <= 1'b1;
count <= 3'b000;
end else begin
mem <= canRX;
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
count <= 3'b001;
end
end
end else begin
count <= 3'b000;
bsError0 <= 1'b0;
stuffing0 <= 1'b0;
end
end
endmodule | 0 |
3,917 | data/full_repos/permissive/107735152/src/bitstuffing_TB.v | 107,735,152 | bitstuffing_TB.v | v | 70 | 80 | [] | [] | [] | null | line:67: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:11: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:13: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b1; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; canRX_tb = 1\'b0; bsOnOff_tb = 1\'b1; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/bitstuffing_TB.v:6: Cannot find file containing module: \'bitstuffing\'\nbitstuffing dut(samplePoint_tb, canRX_tb, bsOnOff_tb, stuffing_tb, bsError_tb);\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/bitstuffing\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/bitstuffing.v\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/bitstuffing.sv\n bitstuffing\n bitstuffing.v\n bitstuffing.sv\n obj_dir/bitstuffing\n obj_dir/bitstuffing.v\n obj_dir/bitstuffing.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,115 | module | module bitstuffing_TB;
reg samplePoint_tb, canRX_tb, bsOnOff_tb;
wire stuffing_tb, bsError_tb;
bitstuffing dut(samplePoint_tb, canRX_tb, bsOnOff_tb, stuffing_tb, bsError_tb);
initial
begin
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
$stop;
end
endmodule | module bitstuffing_TB; |
reg samplePoint_tb, canRX_tb, bsOnOff_tb;
wire stuffing_tb, bsError_tb;
bitstuffing dut(samplePoint_tb, canRX_tb, bsOnOff_tb, stuffing_tb, bsError_tb);
initial
begin
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b1; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b0; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
samplePoint_tb = 1'b1; canRX_tb = 1'b0; bsOnOff_tb = 1'b1; #5
$stop;
end
endmodule | 0 |
3,918 | data/full_repos/permissive/107735152/src/datarate.v | 107,735,152 | datarate.v | v | 12 | 81 | [] | [] | [] | [(1, 12)] | null | data/verilator_xmls/6abe8c69-657a-465e-929f-8a59dc008073.xml | null | 2,116 | module | module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);
input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;
wire switch;
assign switch = edl & brs & brsStop;
assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;
endmodule | module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT); |
input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;
wire switch;
assign switch = edl & brs & brsStop;
assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;
endmodule | 0 |
3,919 | data/full_repos/permissive/107735152/src/datarate_TB.v | 107,735,152 | datarate_TB.v | v | 56 | 111 | [] | [] | [] | null | line:54: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:12: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; samplePointFD_tb = 1\'b0; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b0; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; samplePointFD_tb = 1\'b0; edl_tb = 1\'b0; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b1; samplePointFD_tb = 1\'b0; edl_tb = 1\'b1; brs_tb = 1\'b0; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b1; brs_tb = 1\'b1; brsStop_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/datarate_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n samplePoint_tb = 1\'b0; samplePointFD_tb = 1\'b1; edl_tb = 1\'b0; brs_tb = 1\'b0; brsStop_tb = 1\'b0; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/datarate_TB.v:6: Cannot find file containing module: \'datarate\'\n datarate dut(samplePoint_tb, samplePointFD_tb, edl_tb, brs_tb, brsStop_tb, samplePointOUT_tb);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate.v\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate.sv\n datarate\n datarate.v\n datarate.sv\n obj_dir/datarate\n obj_dir/datarate.v\n obj_dir/datarate.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,117 | module | module datarate_TB;
reg samplePoint_tb, samplePointFD_tb, edl_tb, brs_tb, brsStop_tb;
wire samplePointOUT_tb;
datarate dut(samplePoint_tb, samplePointFD_tb, edl_tb, brs_tb, brsStop_tb, samplePointOUT_tb);
initial
begin
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b0; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b0; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b1; brs_tb = 1'b0; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
$stop;
end
endmodule | module datarate_TB; |
reg samplePoint_tb, samplePointFD_tb, edl_tb, brs_tb, brsStop_tb;
wire samplePointOUT_tb;
datarate dut(samplePoint_tb, samplePointFD_tb, edl_tb, brs_tb, brsStop_tb, samplePointOUT_tb);
initial
begin
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b0; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b0; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b1; samplePointFD_tb = 1'b0; edl_tb = 1'b1; brs_tb = 1'b0; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b1; brs_tb = 1'b1; brsStop_tb = 1'b1; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
samplePoint_tb = 1'b0; samplePointFD_tb = 1'b1; edl_tb = 1'b0; brs_tb = 1'b0; brsStop_tb = 1'b0; #5
$stop;
end
endmodule | 0 |
3,920 | data/full_repos/permissive/107735152/src/decoderTop.v | 107,735,152 | decoderTop.v | v | 14 | 102 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/107735152/src/decoderTop.v:10: Cannot find file containing module: 'datarate'\n datarate dt (samplePoint, samplePointFD, edl, brs, brsStop, samplePointFromDatarate);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate.v\n data/full_repos/permissive/107735152/src,data/full_repos/permissive/107735152/datarate.sv\n datarate\n datarate.v\n datarate.sv\n obj_dir/datarate\n obj_dir/datarate.v\n obj_dir/datarate.sv\n%Error: data/full_repos/permissive/107735152/src/decoderTop.v:11: Cannot find file containing module: 'bitstuffing'\n bitstuffing bt (samplePointFromDatarate, canRX, bsOnOff, stuffing, bsError);\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,118 | module | module decoderTop (samplePoint, samplePointFD, edl, brs, brsStop, canRX, bsOnOff, stuffing, bsError);
input wire samplePoint, samplePointFD, edl, brs, brsStop, canRX, bsOnOff;
output wire stuffing, bsError;
wire samplePointFromDatarate;
datarate dt (samplePoint, samplePointFD, edl, brs, brsStop, samplePointFromDatarate);
bitstuffing bt (samplePointFromDatarate, canRX, bsOnOff, stuffing, bsError);
endmodule | module decoderTop (samplePoint, samplePointFD, edl, brs, brsStop, canRX, bsOnOff, stuffing, bsError); |
input wire samplePoint, samplePointFD, edl, brs, brsStop, canRX, bsOnOff;
output wire stuffing, bsError;
wire samplePointFromDatarate;
datarate dt (samplePoint, samplePointFD, edl, brs, brsStop, samplePointFromDatarate);
bitstuffing bt (samplePointFromDatarate, canRX, bsOnOff, stuffing, bsError);
endmodule | 0 |
3,921 | data/full_repos/permissive/107735152/src/error/crcCalc.v | 107,735,152 | crcCalc.v | v | 36 | 94 | [] | [] | [] | null | line:5: before: "," | null | 1: b"%Error: data/full_repos/permissive/107735152/src/error/crcCalc.v:20: syntax error, unexpected end, expecting ';'\n end\n ^~~\n%Error: Cannot continue\n" | 2,119 | module | module crcCalculation(input reset, samplePoint, canRX, isStuff,CRCcalc_on, output CRCresult);
reg [4:0]CRCtype;
reg [9:0]CRClength;
parameter crc0, crc15, crc17, crc21;
initial conter = 9'd0;
always @ (posedge samplePoint or posedge reset) begin
if ( (reset == 1) && (CRCcalc_on == 1) )
begin
CRClength = 0;
case(CRCtype)
crc0:
conter <= 9'd0;
crc15:
if (CRClength < 15)
begin
CRClength = CRClength +1
end
crc17:
if (CRClength < 17)
begin
CRClength = CRClength +1
end
crc21:
if (CRClength < 21)
begin
CRClength = CRClength +1
end
endmodule | module crcCalculation(input reset, samplePoint, canRX, isStuff,CRCcalc_on, output CRCresult); |
reg [4:0]CRCtype;
reg [9:0]CRClength;
parameter crc0, crc15, crc17, crc21;
initial conter = 9'd0;
always @ (posedge samplePoint or posedge reset) begin
if ( (reset == 1) && (CRCcalc_on == 1) )
begin
CRClength = 0;
case(CRCtype)
crc0:
conter <= 9'd0;
crc15:
if (CRClength < 15)
begin
CRClength = CRClength +1
end
crc17:
if (CRClength < 17)
begin
CRClength = CRClength +1
end
crc21:
if (CRClength < 21)
begin
CRClength = CRClength +1
end
endmodule | 0 |
3,922 | data/full_repos/permissive/107735152/src/error/error.v | 107,735,152 | error.v | v | 78 | 102 | [] | [] | [] | null | line:60: before: "$" | null | 1: b"%Error: data/full_repos/permissive/107735152/src/error/error.v:35: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n )\n ^\n%Error: data/full_repos/permissive/107735152/src/error/error.v:39: syntax error, unexpected ';', expecting ',' or ':'\n interframe <= 1'b1;\n ^\n%Error: data/full_repos/permissive/107735152/src/error/error.v:72: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: Cannot continue\n" | 2,120 | module | module error(reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe);
input wire reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, canRX;
output wire erro, interframe;
reg [3:0]stateRead;
reg [4:0]counter = 0;
initial erro = 1'b1;
parameter reset = 0;
parameter state = 0;
parameter stateAux = 1;
always @ (posedge samplePoint or posedge reset) begin
if(reset)
begin
stateRead <= state;
crcErro <= 1'b1;
counter <= counter + 1;
end
else
if (~reset)
begin
case(stateRead)
state :
begin
if( (eofErro == 1'b0) ||
(stuffErro == 1'b0) ||
(crcErro == 1'b0) ||
)
begin
stateRead <= stateAux;
end
interframe <= 1'b1;
if(overloadFlag == 1'b0)
begin
stateRead <= stateAux;
end
end
stateAux :
begin
stateRead <= state;
end
overloadFlag:
if (canRX == 0)
begin
if (count == 4)
begin
counter <= counter + 1;
end
else
begin
counter <= counter + 1;
end
end
else
if (canRX == 1)
begin
counter <= 0;
state <= overloadFlag;
end
endcase
end
end
endmodule | module error(reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe); |
input wire reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, canRX;
output wire erro, interframe;
reg [3:0]stateRead;
reg [4:0]counter = 0;
initial erro = 1'b1;
parameter reset = 0;
parameter state = 0;
parameter stateAux = 1;
always @ (posedge samplePoint or posedge reset) begin
if(reset)
begin
stateRead <= state;
crcErro <= 1'b1;
counter <= counter + 1;
end
else
if (~reset)
begin
case(stateRead)
state :
begin
if( (eofErro == 1'b0) ||
(stuffErro == 1'b0) ||
(crcErro == 1'b0) ||
)
begin
stateRead <= stateAux;
end
interframe <= 1'b1;
if(overloadFlag == 1'b0)
begin
stateRead <= stateAux;
end
end
stateAux :
begin
stateRead <= state;
end
overloadFlag:
if (canRX == 0)
begin
if (count == 4)
begin
counter <= counter + 1;
end
else
begin
counter <= counter + 1;
end
end
else
if (canRX == 1)
begin
counter <= 0;
state <= overloadFlag;
end
endcase
end
end
endmodule | 0 |
3,923 | data/full_repos/permissive/107735152/src/error/error_overload_block.v | 107,735,152 | error_overload_block.v | v | 50 | 108 | [] | [] | [] | null | line:28: before: ")" | null | 1: b"%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:28: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n )\n ^\n%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:32: syntax error, unexpected ';', expecting ',' or ':'\n interframe <= 1'b1;\n ^\n%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:45: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: Cannot continue\n" | 2,121 | module | module error(input reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe);
reg [3:0]stateRead;
initial erro = 1'b1;
parameter reset = 0;
parameter state = 0;
parameter stateAux = 1;
always @ (posedge samplePoint or posedge reset) begin
if(reset)
begin
stateRead <= state;
end
else
if (~reset)
begin
case(stateRead)
state :
begin
if( (eofErro == 1'b0) ||
(stuffErro == 1'b0) ||
(crcErro == 1'b0) ||
)
begin
stateRead <= stateAux;
end
interframe <= 1'b1;
if(overloadFlag == 1'b0)
begin
stateRead <= stateAux;
end
end
stateAux :
begin
stateRead <= state;
end
endcase
end
end
endmodule | module error(input reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe); |
reg [3:0]stateRead;
initial erro = 1'b1;
parameter reset = 0;
parameter state = 0;
parameter stateAux = 1;
always @ (posedge samplePoint or posedge reset) begin
if(reset)
begin
stateRead <= state;
end
else
if (~reset)
begin
case(stateRead)
state :
begin
if( (eofErro == 1'b0) ||
(stuffErro == 1'b0) ||
(crcErro == 1'b0) ||
)
begin
stateRead <= stateAux;
end
interframe <= 1'b1;
if(overloadFlag == 1'b0)
begin
stateRead <= stateAux;
end
end
stateAux :
begin
stateRead <= state;
end
endcase
end
end
endmodule | 0 |
3,924 | data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v | 107,735,152 | error_overload_block_TB.v | v | 37 | 103 | [] | [] | [] | null | line:2: before: "_block_TB" | null | 1: b'%Error: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:9: syntax error, unexpected \'(\', expecting IDENTIFIER\nerror_overload_block(reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, erro, interframe);\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n #5 samplePoint = ~samplePoint;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b0; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b0; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b0; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/error/error_overload_block_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; stuffErro = 1\'b1; eofErro = 1\'b1; crcErro = 1\'b1; #5;\n ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n' | 2,122 | module | module error_overload_block_TB;
reg reset, samplePoint,
eofErro, crcErro, stuffErro, overloadFlag;
reg erro;
wire saida;
error_overload_block(reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, erro, interframe);
initial begin
reset = 1;
samplePoint = 0;
end
always
#5 samplePoint = ~samplePoint;
initial begin
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b0; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b0; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b0; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
$stop;
end
endmodule | module error_overload_block_TB; |
reg reset, samplePoint,
eofErro, crcErro, stuffErro, overloadFlag;
reg erro;
wire saida;
error_overload_block(reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, erro, interframe);
initial begin
reset = 1;
samplePoint = 0;
end
always
#5 samplePoint = ~samplePoint;
initial begin
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b0; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b0; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b0; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
reset = 1'b0; stuffErro = 1'b1; eofErro = 1'b1; crcErro = 1'b1; #5;
$stop;
end
endmodule | 0 |
3,925 | data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v | 107,735,152 | DatavsRemote_TB.v | v | 23 | 63 | [] | [] | [] | null | line:21: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:12: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b0; RTR_r1_tb = 1\'b0; #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:13: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b0; RTR_r1_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b1; RTR_r1_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b1; RTR_r1_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b0; RTR_r1_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b0; RTR_r1_tb = 1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b1; RTR_r1_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b1; RTR_r1_tb = 1\'b1; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:7: Cannot find file containing module: \'DatavsRemote\'\n DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote.sv\n DatavsRemote\n DatavsRemote.v\n DatavsRemote.sv\n obj_dir/DatavsRemote\n obj_dir/DatavsRemote.v\n obj_dir/DatavsRemote.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,124 | module | module DatavsRemote_TB;
reg RTR_SRR_tb, IDE_tb, RTR_r1_tb;
wire isRemote_tb;
DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);
initial
begin
RTR_SRR_tb = 1'b0; IDE_tb = 1'b0; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b0; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b1; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b1; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b0; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b0; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b1; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b1; RTR_r1_tb = 1'b1; #5
$stop;
end
endmodule | module DatavsRemote_TB; |
reg RTR_SRR_tb, IDE_tb, RTR_r1_tb;
wire isRemote_tb;
DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);
initial
begin
RTR_SRR_tb = 1'b0; IDE_tb = 1'b0; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b0; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b1; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b0; IDE_tb = 1'b1; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b0; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b0; RTR_r1_tb = 1'b1; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b1; RTR_r1_tb = 1'b0; #5
RTR_SRR_tb = 1'b1; IDE_tb = 1'b1; RTR_r1_tb = 1'b1; #5
$stop;
end
endmodule | 0 |
3,926 | data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v | 107,735,152 | framecontroller_tb.v | v | 54 | 230 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 reset_tb = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 CAN_RX_tb = messageTest[75];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5 sp_tb = !sp_tb;\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:13: Cannot find file containing module: \'framecontroller\'\n framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller.sv\n framecontroller\n framecontroller.v\n framecontroller.sv\n obj_dir/framecontroller\n obj_dir/framecontroller.v\n obj_dir/framecontroller.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,126 | module | module framecontroller_tb
(
);
reg [75:0] messageTest;
reg sp_tb, CAN_RX_tb, reset_tb,isStuff_tb, errorFlag_tb;
wire BSonoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb;
wire [1:0] CRCtype_tb;
framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );
initial
begin
$stop;
CAN_RX_tb = 1'b0;
sp_tb = 1'b0;
reset_tb = 1'b1;
messageTest = 76'b1100100100111010101010101010101010110001101010100101010101010101011111111111;
isStuff_tb = 1'b0;
errorFlag_tb = 1'b0;
#10 reset_tb = 1'b0;
end
always @(posedge sp_tb)
begin
if(messageTest != 0)
begin
#10 CAN_RX_tb = messageTest[75];
messageTest <= messageTest << 1;
end
else
begin
$stop;
end
end
always
#5 sp_tb = !sp_tb;
endmodule | module framecontroller_tb
(
); |
reg [75:0] messageTest;
reg sp_tb, CAN_RX_tb, reset_tb,isStuff_tb, errorFlag_tb;
wire BSonoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb;
wire [1:0] CRCtype_tb;
framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );
initial
begin
$stop;
CAN_RX_tb = 1'b0;
sp_tb = 1'b0;
reset_tb = 1'b1;
messageTest = 76'b1100100100111010101010101010101010110001101010100101010101010101011111111111;
isStuff_tb = 1'b0;
errorFlag_tb = 1'b0;
#10 reset_tb = 1'b0;
end
always @(posedge sp_tb)
begin
if(messageTest != 0)
begin
#10 CAN_RX_tb = messageTest[75];
messageTest <= messageTest << 1;
end
else
begin
$stop;
end
end
always
#5 sp_tb = !sp_tb;
endmodule | 0 |
3,927 | data/full_repos/permissive/107735152/src/framemaker/frameMakerTop.v | 107,735,152 | frameMakerTop.v | v | 11 | 103 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop.v:8: Cannot find file containing module: 'interFrameSpace'\n interFrameSpace ifs (samplePoint, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace.sv\n interFrameSpace\n interFrameSpace.v\n interFrameSpace.sv\n obj_dir/interFrameSpace\n obj_dir/interFrameSpace.v\n obj_dir/interFrameSpace.sv\n%Error: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop.v:9: Cannot find file containing module: 'overload'\n overload ov (samplePoint, canRX, isOverloadFromInterframe, isError, endOverload);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,127 | module | module frameMakerTop (samplePoint, canRX, frameReady, isError, endOverload, isStart);
input wire samplePoint, canRX, frameReady, isError;
output wire endOverload, isStart;
wire isOverloadFromInterframe;
interFrameSpace ifs (samplePoint, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);
overload ov (samplePoint, canRX, isOverloadFromInterframe, isError, endOverload);
endmodule | module frameMakerTop (samplePoint, canRX, frameReady, isError, endOverload, isStart); |
input wire samplePoint, canRX, frameReady, isError;
output wire endOverload, isStart;
wire isOverloadFromInterframe;
interFrameSpace ifs (samplePoint, canRX, frameReady, endOverload, isOverloadFromInterframe, isStart);
overload ov (samplePoint, canRX, isOverloadFromInterframe, isError, endOverload);
endmodule | 0 |
3,928 | data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v | 107,735,152 | frameMakerTop_TB.v | v | 72 | 102 | [] | [] | [] | null | line:68: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n #5 samplePoint_tb = ~samplePoint_tb;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b0; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b0; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:56: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:62: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:64: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/frameMakerTop_TB.v:6: Cannot find file containing module: \'frameMakerTop\'\n frameMakerTop dut(samplePoint_tb, canRX_tb, frameReady_tb, isError_tb, endOverload_tb, isStart_tb);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameMakerTop\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameMakerTop.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameMakerTop.sv\n frameMakerTop\n frameMakerTop.v\n frameMakerTop.sv\n obj_dir/frameMakerTop\n obj_dir/frameMakerTop.v\n obj_dir/frameMakerTop.sv\n%Error: Exiting due to 1 error(s), 41 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,128 | module | module frameMakerTop_TB ();
reg samplePoint_tb, canRX_tb, frameReady_tb, isError_tb;
wire endOverload_tb, isStart_tb;
frameMakerTop dut(samplePoint_tb, canRX_tb, frameReady_tb, isError_tb, endOverload_tb, isStart_tb);
initial
begin
samplePoint_tb = 1;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b0; frameReady_tb = 1'b0; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b0; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
$stop;
end
endmodule | module frameMakerTop_TB (); |
reg samplePoint_tb, canRX_tb, frameReady_tb, isError_tb;
wire endOverload_tb, isStart_tb;
frameMakerTop dut(samplePoint_tb, canRX_tb, frameReady_tb, isError_tb, endOverload_tb, isStart_tb);
initial
begin
samplePoint_tb = 1;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b0; frameReady_tb = 1'b0; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b0; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; isError_tb = 1'b0; #5
$stop;
end
endmodule | 0 |
3,929 | data/full_repos/permissive/107735152/src/framemaker/frameSize.v | 107,735,152 | frameSize.v | v | 35 | 57 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/968968c4-e7c3-4963-b990-2a14f4bd4425.xml | null | 2,129 | module | module frameSize
(
input sp, isStuff, reset,
output reg [9:0] size
);
initial begin
size <= 0;
end
always @ (posedge sp or posedge reset) begin
if (reset)
begin
size <= 10'b0;
end
else if (~isStuff)
begin
size <= size + 1;
end
end
endmodule | module frameSize
(
input sp, isStuff, reset,
output reg [9:0] size
); |
initial begin
size <= 0;
end
always @ (posedge sp or posedge reset) begin
if (reset)
begin
size <= 10'b0;
end
else if (~isStuff)
begin
size <= size + 1;
end
end
endmodule | 0 |
3,930 | data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v | 107,735,152 | frameSize_TB.v | v | 38 | 54 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b1; #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b1; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b1; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n sp_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/frameSize_TB.v:10: Cannot find file containing module: \'frameSize\'\n frameSize dut(sp_tb, isStuff_tb, reset_tb, size_tb);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameSize\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameSize.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameSize.sv\n frameSize\n frameSize.v\n frameSize.sv\n obj_dir/frameSize\n obj_dir/frameSize.v\n obj_dir/frameSize.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,130 | module | module frameSize_TB
(
);
reg sp_tb, isStuff_tb, reset_tb;
wire [9:0] size_tb;
frameSize dut(sp_tb, isStuff_tb, reset_tb, size_tb);
initial
begin
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b1; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
$stop;
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b1; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
$stop;
end
endmodule | module frameSize_TB
(
); |
reg sp_tb, isStuff_tb, reset_tb;
wire [9:0] size_tb;
frameSize dut(sp_tb, isStuff_tb, reset_tb, size_tb);
initial
begin
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b1; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
$stop;
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b1; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #5
sp_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #5
$stop;
end
endmodule | 0 |
3,931 | data/full_repos/permissive/107735152/src/framemaker/frameStorage.v | 107,735,152 | frameStorage.v | v | 28 | 57 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107735152/src/framemaker/frameStorage.v:23: Operator ADD expects 590 bits on the RHS, but RHS\'s VARREF \'CAN_RX\' generates 1 bits.\n : ... In instance frameStorage\n frame = frame + CAN_RX;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,131 | module | module frameStorage
(
input sp, CAN_RX, isStuff, reset,
output reg [589:0] frame
);
initial begin
frame = 0;
end
always @ (posedge sp or posedge reset) begin
if (reset)
begin
frame = 0;
end
else if (~isStuff)
begin
frame = frame << 1;
frame = frame + CAN_RX;
end
end
endmodule | module frameStorage
(
input sp, CAN_RX, isStuff, reset,
output reg [589:0] frame
); |
initial begin
frame = 0;
end
always @ (posedge sp or posedge reset) begin
if (reset)
begin
frame = 0;
end
else if (~isStuff)
begin
frame = frame << 1;
frame = frame + CAN_RX;
end
end
endmodule | 0 |
3,932 | data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v | 107,735,152 | frameStorage_TB.v | v | 37 | 69 | [] | [] | [] | [(1, 61)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b1; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b0; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b1; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b1; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n CAN_RX_tb = 1\'b1; isStuff_tb = 1\'b0; reset_tb =1\'b0; #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5 sp_tb = !sp_tb;\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/frameStorage_TB.v:10: Cannot find file containing module: \'frameStorage\'\n frameStorage dut(sp_tb, CAN_RX_tb, isStuff_tb, reset_tb, frame_tb);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameStorage\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameStorage.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/frameStorage.sv\n frameStorage\n frameStorage.v\n frameStorage.sv\n obj_dir/frameStorage\n obj_dir/frameStorage.v\n obj_dir/frameStorage.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,132 | module | module frameStorage_TB
(
);
reg sp_tb, CAN_RX_tb, isStuff_tb, reset_tb;
wire [589:0] frame_tb;
frameStorage dut(sp_tb, CAN_RX_tb, isStuff_tb, reset_tb, frame_tb);
initial
begin
sp_tb = 0;
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #10
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
$stop;
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b1; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
$stop;
end
always
#5 sp_tb = !sp_tb;
endmodule | module frameStorage_TB
(
); |
reg sp_tb, CAN_RX_tb, isStuff_tb, reset_tb;
wire [589:0] frame_tb;
frameStorage dut(sp_tb, CAN_RX_tb, isStuff_tb, reset_tb, frame_tb);
initial
begin
sp_tb = 0;
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #10
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b0; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b1; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
$stop;
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b1; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
CAN_RX_tb = 1'b1; isStuff_tb = 1'b0; reset_tb =1'b0; #10
$stop;
end
always
#5 sp_tb = !sp_tb;
endmodule | 0 |
3,933 | data/full_repos/permissive/107735152/src/framemaker/interFrameSpace.v | 107,735,152 | interFrameSpace.v | v | 91 | 94 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/a614fa6c-bf3d-43b7-8487-377bcc8983d6.xml | null | 2,133 | module | module interFrameSpace (samplePoint, canRX, frameReady, endOverload, isOverload, isStart);
input wire samplePoint, canRX, frameReady, endOverload;
output wire isOverload, isStart;
parameter bit1_intermission = 0, bit2_intermission = 1, bit3_intermission = 2, bus_idle = 3;
reg [2:0]state = bus_idle;
reg isOverload0 = 0, isStart0 = 0, hey0 = 0;
assign isOverload = isOverload0;
assign isStart = isStart0;
always @ (posedge samplePoint) begin
if (frameReady == 0)begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end
if (isOverload) begin
isOverload0 <= 0;
end
if (frameReady == 1 && endOverload == 1) begin
if (canRX == 1) begin
state <= bit2_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
end
if (frameReady == 1 && endOverload == 0) begin
case (state)
bit1_intermission:
if (canRX == 1) begin
state <= bit2_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
bit2_intermission:
if (canRX == 1) begin
state <= bit3_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
bit3_intermission:
if (canRX == 1) begin
state <= bus_idle;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 1;
end
bus_idle:
if (canRX == 1) begin
state <= bus_idle;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 1;
end
endcase
end
end
endmodule | module interFrameSpace (samplePoint, canRX, frameReady, endOverload, isOverload, isStart); |
input wire samplePoint, canRX, frameReady, endOverload;
output wire isOverload, isStart;
parameter bit1_intermission = 0, bit2_intermission = 1, bit3_intermission = 2, bus_idle = 3;
reg [2:0]state = bus_idle;
reg isOverload0 = 0, isStart0 = 0, hey0 = 0;
assign isOverload = isOverload0;
assign isStart = isStart0;
always @ (posedge samplePoint) begin
if (frameReady == 0)begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end
if (isOverload) begin
isOverload0 <= 0;
end
if (frameReady == 1 && endOverload == 1) begin
if (canRX == 1) begin
state <= bit2_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
end
if (frameReady == 1 && endOverload == 0) begin
case (state)
bit1_intermission:
if (canRX == 1) begin
state <= bit2_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
bit2_intermission:
if (canRX == 1) begin
state <= bit3_intermission;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 1;
isStart0 <= 0;
end
bit3_intermission:
if (canRX == 1) begin
state <= bus_idle;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 1;
end
bus_idle:
if (canRX == 1) begin
state <= bus_idle;
isOverload0 <= 0;
isStart0 <= 0;
end else begin
state <= bit1_intermission;
isOverload0 <= 0;
isStart0 <= 1;
end
endcase
end
end
endmodule | 0 |
3,934 | data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v | 107,735,152 | interFrameSpace_TB.v | v | 62 | 128 | [] | [] | [] | null | line:59: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 samplePoint_tb = ~samplePoint_tb;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b0; endOverload_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b0; endOverload_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; endOverload_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; frameReady_tb = 1\'b1; endOverload_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; endOverload_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; frameReady_tb = 1\'b1; endOverload_tb = 1\'b0; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/interFrameSpace_TB.v:5: Cannot find file containing module: \'interFrameSpace\'\n interFrameSpace dut(samplePoint_tb, canRX_tb, frameReady_tb, endOverload_tb, isOverload_tb, isStart_tb);\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/interFrameSpace.sv\n interFrameSpace\n interFrameSpace.v\n interFrameSpace.sv\n obj_dir/interFrameSpace\n obj_dir/interFrameSpace.v\n obj_dir/interFrameSpace.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,134 | module | module interFrameSpace_TB ();
reg samplePoint_tb, canRX_tb, frameReady_tb, endOverload_tb;
wire isOverload_tb, isStart_tb;
interFrameSpace dut(samplePoint_tb, canRX_tb, frameReady_tb, endOverload_tb, isOverload_tb, isStart_tb);
initial
begin
samplePoint_tb = 0;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b1; frameReady_tb = 1'b0; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b0; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
$stop;
end
endmodule | module interFrameSpace_TB (); |
reg samplePoint_tb, canRX_tb, frameReady_tb, endOverload_tb;
wire isOverload_tb, isStart_tb;
interFrameSpace dut(samplePoint_tb, canRX_tb, frameReady_tb, endOverload_tb, isOverload_tb, isStart_tb);
initial
begin
samplePoint_tb = 0;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b1; frameReady_tb = 1'b0; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b0; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b1; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
canRX_tb = 1'b0; frameReady_tb = 1'b1; endOverload_tb = 1'b0; #5
$stop;
end
endmodule | 0 |
3,935 | data/full_repos/permissive/107735152/src/framemaker/overload_TB.v | 107,735,152 | overload_TB.v | v | 71 | 112 | [] | [] | [] | null | line:69: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 samplePoint_tb = ~samplePoint_tb;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:56: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b1; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:62: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:64: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:66: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n canRX_tb = 1\'b0; isOverload_tb = 1\'b1; isError_tb = 1\'b0; #5\n ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/overload_TB.v:5: Cannot find file containing module: \'overload\'\n overload dut(samplePoint_tb, canRX_tb, isOverload_tb, isError_tb, endOverload_tb);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/overload\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/overload.v\n data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/overload.sv\n overload\n overload.v\n overload.sv\n obj_dir/overload\n obj_dir/overload.v\n obj_dir/overload.sv\n%Error: Exiting due to 1 error(s), 33 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,136 | module | module overload_TB();
reg samplePoint_tb, canRX_tb, isOverload_tb, isError_tb;
wire endOverload_tb;
overload dut(samplePoint_tb, canRX_tb, isOverload_tb, isError_tb, endOverload_tb);
initial
begin
samplePoint_tb = 0;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
$stop;
end
endmodule | module overload_TB(); |
reg samplePoint_tb, canRX_tb, isOverload_tb, isError_tb;
wire endOverload_tb;
overload dut(samplePoint_tb, canRX_tb, isOverload_tb, isError_tb, endOverload_tb);
initial
begin
samplePoint_tb = 0;
end
always
#5 samplePoint_tb = ~samplePoint_tb;
initial
begin
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b1; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
canRX_tb = 1'b0; isOverload_tb = 1'b1; isError_tb = 1'b0; #5
$stop;
end
endmodule | 0 |
3,936 | data/full_repos/permissive/107757225/reg_16.sv | 107,757,225 | reg_16.sv | sv | 19 | 60 | [] | [] | [] | [(1, 29)] | null | data/verilator_xmls/c8767f1e-f767-4ef8-b8a3-5b4fcb34074f.xml | null | 2,138 | module | module reg_16 (
input logic clk,
input logic reset,
input logic load,
input logic [15:0] din,
output logic [15:0] dout
);
always_ff @(posedge clk)
begin
if(reset) begin
dout <= 16'b0;
end
else if(load) begin
dout <= din;
end
end
endmodule | module reg_16 (
input logic clk,
input logic reset,
input logic load,
input logic [15:0] din,
output logic [15:0] dout
); |
always_ff @(posedge clk)
begin
if(reset) begin
dout <= 16'b0;
end
else if(load) begin
dout <= din;
end
end
endmodule | 0 |
3,937 | data/full_repos/permissive/107757225/testbench.sv | 107,757,225 | testbench.sv | sv | 65 | 62 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:38: Unsupported: Ignoring delay on this delayed statement.\n #1 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:48: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:51: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:52: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:53: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:54: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #2 DUT.cont = 1;\n ^\n%Error: data/full_repos/permissive/107757225/testbench.sv:46: Can\'t find definition of \'reset\' in dotted variable: \'DUT.reset\'\n DUT.reset = 1;\n ^~~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:47: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:48: Can\'t find definition of \'reset\' in dotted variable: \'DUT.reset\'\n #2 DUT.reset = 0;\n ^~~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:50: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:51: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 0;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:52: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:53: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 0;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:54: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:55: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 0;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:56: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:57: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 0;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:58: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 1;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:59: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 0;\n ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:60: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n #2 DUT.cont = 1;\n ^~~~\n%Error: Exiting due to 14 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,140 | module | module testbench ( input a );
timeunit 10ns;
timeprecision 1ns;
logic [3:0] KEY;
logic CLOCK_50;
logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire [15:0] SRAM_DQ;
logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N;
logic [19:0] SRAM_ADDR;
toplevel DUT(
.KEY (KEY),
.CLOCK_50 (CLOCK_50),
.HEX0 (HEX0),
.HEX1 (HEX1),
.HEX2 (HEX2),
.HEX3 (HEX3),
.HEX4 (HEX4),
.HEX5 (HEX5),
.HEX6 (HEX6),
.HEX7 (HEX7),
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_OE_N (SRAM_OE_N),
.SRAM_WE_N (SRAM_WE_N)
);
always begin : CLOCK_GENERATION
#1 CLOCK_50 = ~CLOCK_50;
end
initial begin: CLOCK_INITIALIZATION
CLOCK_50 = 0;
end
initial begin: TEST_VECTORS
DUT.reset = 1;
DUT.cont = 1;
#2 DUT.reset = 0;
DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
end
endmodule | module testbench ( input a ); |
timeunit 10ns;
timeprecision 1ns;
logic [3:0] KEY;
logic CLOCK_50;
logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire [15:0] SRAM_DQ;
logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N;
logic [19:0] SRAM_ADDR;
toplevel DUT(
.KEY (KEY),
.CLOCK_50 (CLOCK_50),
.HEX0 (HEX0),
.HEX1 (HEX1),
.HEX2 (HEX2),
.HEX3 (HEX3),
.HEX4 (HEX4),
.HEX5 (HEX5),
.HEX6 (HEX6),
.HEX7 (HEX7),
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_OE_N (SRAM_OE_N),
.SRAM_WE_N (SRAM_WE_N)
);
always begin : CLOCK_GENERATION
#1 CLOCK_50 = ~CLOCK_50;
end
initial begin: CLOCK_INITIALIZATION
CLOCK_50 = 0;
end
initial begin: TEST_VECTORS
DUT.reset = 1;
DUT.cont = 1;
#2 DUT.reset = 0;
DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
#2 DUT.cont = 0;
#2 DUT.cont = 1;
end
endmodule | 0 |
3,938 | data/full_repos/permissive/107757225/timer.sv | 107,757,225 | timer.sv | sv | 52 | 60 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/timer.sv:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'timer\'\nmodule timer(\n ^~~~~\n : ... Top module \'mux\'\nmodule mux(\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 2,141 | module | module timer(
input logic Clk, Reset,
output logic [3:0] arrows
);
logic [3:0][3:0] array;
assign array = {4'b0000, 4'b0100 , 4'b1111 , 4'b0000};
int count = 1;
always_ff @(posedge Clk)
begin
count += 1;
if(count % 50000000 == 0)
begin
arrows = array[1];
count = 1;
end
end
endmodule | module timer(
input logic Clk, Reset,
output logic [3:0] arrows
); |
logic [3:0][3:0] array;
assign array = {4'b0000, 4'b0100 , 4'b1111 , 4'b0000};
int count = 1;
always_ff @(posedge Clk)
begin
count += 1;
if(count % 50000000 == 0)
begin
arrows = array[1];
count = 1;
end
end
endmodule | 0 |
3,939 | data/full_repos/permissive/107757225/timer.sv | 107,757,225 | timer.sv | sv | 52 | 60 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/timer.sv:38: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'timer\'\nmodule timer(\n ^~~~~\n : ... Top module \'mux\'\nmodule mux(\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 2,141 | module | module mux(
input logic sel,
input logic [3:0] d0, d1,
output logic [3:0] y
);
always_comb
begin
if(sel == 1'b0)
y = 4'b0;
else
y = d1;
end
endmodule | module mux(
input logic sel,
input logic [3:0] d0, d1,
output logic [3:0] y
); |
always_comb
begin
if(sel == 1'b0)
y = 4'b0;
else
y = d1;
end
endmodule | 0 |
3,940 | data/full_repos/permissive/107757225/toplevel.sv | 107,757,225 | toplevel.sv | sv | 211 | 80 | [] | [] | [] | null | line:93: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/toplevel.sv:206: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'toplevel\'\nmodule toplevel (\n ^~~~~~~~\n : ... Top module \'sync\'\nmodule sync (input logic Clk, d, output logic q );\n ^~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:65: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_0 ( .In0 (sram_data_out[3:0]), .Out0(HEX0) );\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver.v\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver.sv\n HexDriver\n HexDriver.v\n HexDriver.sv\n obj_dir/HexDriver\n obj_dir/HexDriver.v\n obj_dir/HexDriver.sv\n%Error: data/full_repos/permissive/107757225/toplevel.sv:66: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_1 ( .In0 (sram_data_out[7:4]), .Out0(HEX1) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:67: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_2 ( .In0 (sram_data_out[11:8]), .Out0(HEX2) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:68: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_3 ( .In0 (sram_data_out[15:12]), .Out0(HEX3) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:70: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_4 ( .In0 (SRAM_ADDR[3:0]), .Out0(HEX4) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:71: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_5 ( .In0 (SRAM_ADDR[7:4]), .Out0(HEX5) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:72: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_6 ( .In0 (SRAM_ADDR[11:8]), .Out0(HEX6) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:73: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_7 ( .In0 (SRAM_ADDR[15:12]), .Out0(HEX7) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:75: Cannot find file containing module: \'keyboard\'\nkeyboard keyboard_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:92: Cannot find file containing module: \'audio_driver\'\naudio_driver audio_driver_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:103: Cannot find file containing module: \'square_wave\'\nsquare_wave sq_inst (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:109: Cannot find file containing module: \'sram_reading_fsm\'\nsram_reading_fsm sram_reading_fsm_inst(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:118: Cannot find file containing module: \'reg_16\'\nreg_16 sram_data(\n^~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:123: Cannot find file containing module: \'ClkDivider\'\nClkDivider clk_divider_inst(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:128: Cannot find file containing module: \'aud_xck_divider\'\naud_xck_divider aud_xck_divider_inst(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:146: Cannot find file containing module: \'timer\'\ntimer counter(.Clk(Clk), .Reset(reset), .arrows(arrows));\n^~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:149: Cannot find file containing module: \'vga_controller\'\nvga_controller vga_controller_inst(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:161: Cannot find file containing module: \'color_mapper\'\ncolor_mapper color_mapper_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:174: Cannot find file containing module: \'ball\'\nball ball_inst(\n^~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:184: Cannot find file containing module: \'receptor\'\nreceptor receptor_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:192: Cannot find file containing module: \'arrow\'\narrow arrow_inst(\n^~~~~\n%Error: Exiting due to 21 error(s), 1 warning(s)\n' | 2,142 | module | module toplevel (
input logic [3:0] KEY,
input logic CLOCK_50,
input logic PS2_KBCLK, PS2_KBDAT,
output logic [7:0] VGA_R, VGA_G, VGA_B,
output logic VGA_CLK, VGA_SYNC_N, VGA_BLANK_N, VGA_VS, VGA_HS,
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
output logic [9:0] LEDG,
output logic AUD_DACDAT, I2C_SCLK, AUD_XCK,
inout I2C_SDAT,
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT,
output logic [31:0] ADCDATA,
input logic [15:0] SRAM_DQ,
output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
output logic [19:0] SRAM_ADDR
);
logic start, cont;
assign start = ~KEY[2];
assign cont = ~KEY[3];
logic [15:0] audio_data;
logic [15:0] sram_data_out;
logic sram_data_load;
logic Clk, reset;
assign Clk = CLOCK_50;
always_ff @ (posedge Clk) begin
reset <= ~(KEY[0]);
end
always_ff @ (posedge Clk) begin
if(reset)
VGA_CLK <= 1'b0;
else
VGA_CLK <= ~VGA_CLK;
end
logic [7:0] keycode;
logic keypress;
assign LEDG[8] = keypress;
assign LEDG[7:0] = keycode;
HexDriver hex_driver_0 ( .In0 (sram_data_out[3:0]), .Out0(HEX0) );
HexDriver hex_driver_1 ( .In0 (sram_data_out[7:4]), .Out0(HEX1) );
HexDriver hex_driver_2 ( .In0 (sram_data_out[11:8]), .Out0(HEX2) );
HexDriver hex_driver_3 ( .In0 (sram_data_out[15:12]), .Out0(HEX3) );
HexDriver hex_driver_4 ( .In0 (SRAM_ADDR[3:0]), .Out0(HEX4) );
HexDriver hex_driver_5 ( .In0 (SRAM_ADDR[7:4]), .Out0(HEX5) );
HexDriver hex_driver_6 ( .In0 (SRAM_ADDR[11:8]), .Out0(HEX6) );
HexDriver hex_driver_7 ( .In0 (SRAM_ADDR[15:12]), .Out0(HEX7) );
keyboard keyboard_inst(
.Clk (Clk),
.psClk (PS2_KBCLK), .psData(PS2_KBDAT),
.reset (reset),
.keyCode(keycode),
.press (keypress)
);
assign AUD_XCK = CLOCK_50;
logic clk_div, xck_divider;
logic [23:0] dac_left, dac_right;
audio_driver audio_driver_inst(
.CLOCK_50, .reset,
.dac_left( $signed(sram_data_out) ), .dac_right( $signed(sram_data_out) ),
.FPGA_I2C_SCLK(I2C_SCLK), .FPGA_I2C_SDAT(I2C_SDAT), .AUD_DACLRCK,
.AUD_ADCLRCK, .AUD_BCLK, .AUD_ADCDAT, .AUD_DACDAT
);
logic sq_wv;
square_wave sq_inst (
.clk(Clk),
.rst(reset),
.dac_out(sq_wv)
);
sram_reading_fsm sram_reading_fsm_inst(
.Clk, .reset,
.SRAM_CE_N, .SRAM_UB_N, .SRAM_LB_N, .SRAM_OE_N, .SRAM_WE_N,
.SRAM_ADDR,
.sram_data_load,
.start, .cont(clk_div)
);
reg_16 sram_data(
.clk(Clk), .reset,
.load (sram_data_load), .din(SRAM_DQ), .dout (sram_data_out)
);
ClkDivider clk_divider_inst(
.clk(Clk), .rst(reset),
.clk_div
);
aud_xck_divider aud_xck_divider_inst(
.clk (Clk), .rst (reset),
.clk_div(xck_divider)
);
logic [9:0] DrawX, DrawY;
logic ball, background, receptor_background;
logic [3:0] receptor, display_arrow;
logic [3:0] display_signal;
logic [3:0] arrows;
timer counter(.Clk(Clk), .Reset(reset), .arrows(arrows));
vga_controller vga_controller_inst(
.Clk (Clk),
.Reset (reset),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS),
.VGA_CLK (VGA_CLK),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N (VGA_SYNC_N),
.DrawX (DrawX),
.DrawY (DrawY)
);
color_mapper color_mapper_inst(
.is_ball(ball),
.is_receptor(receptor),
.is_background(background),
.is_receptor_background(receptor_background),
.display_arrow(display_arrow),
.DrawX (DrawX),
.DrawY (DrawY),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B)
);
ball ball_inst(
.Clk (Clk),
.Reset (reset),
.frame_clk (VGA_VS),
.DrawX (DrawX),
.DrawY (DrawY),
.keycode (keycode[7:0]),
.is_ball (ball)
);
receptor receptor_inst(
.is_receptor (receptor),
.is_receptor_background(receptor_background),
.is_background (background),
.keycode (keycode[7:0]),
.DrawX(DrawX), .DrawY(DrawY)
);
arrow arrow_inst(
.Clk (Clk),
.reset (reset),
.frame_clk (VGA_VS),
.display_signal(display_signal),
.display_arrow(display_arrow),
.DrawX (DrawX), .DrawY (DrawY)
);
endmodule | module toplevel (
input logic [3:0] KEY,
input logic CLOCK_50,
input logic PS2_KBCLK, PS2_KBDAT,
output logic [7:0] VGA_R, VGA_G, VGA_B,
output logic VGA_CLK, VGA_SYNC_N, VGA_BLANK_N, VGA_VS, VGA_HS,
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
output logic [9:0] LEDG,
output logic AUD_DACDAT, I2C_SCLK, AUD_XCK,
inout I2C_SDAT,
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT,
output logic [31:0] ADCDATA,
input logic [15:0] SRAM_DQ,
output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
output logic [19:0] SRAM_ADDR
); |
logic start, cont;
assign start = ~KEY[2];
assign cont = ~KEY[3];
logic [15:0] audio_data;
logic [15:0] sram_data_out;
logic sram_data_load;
logic Clk, reset;
assign Clk = CLOCK_50;
always_ff @ (posedge Clk) begin
reset <= ~(KEY[0]);
end
always_ff @ (posedge Clk) begin
if(reset)
VGA_CLK <= 1'b0;
else
VGA_CLK <= ~VGA_CLK;
end
logic [7:0] keycode;
logic keypress;
assign LEDG[8] = keypress;
assign LEDG[7:0] = keycode;
HexDriver hex_driver_0 ( .In0 (sram_data_out[3:0]), .Out0(HEX0) );
HexDriver hex_driver_1 ( .In0 (sram_data_out[7:4]), .Out0(HEX1) );
HexDriver hex_driver_2 ( .In0 (sram_data_out[11:8]), .Out0(HEX2) );
HexDriver hex_driver_3 ( .In0 (sram_data_out[15:12]), .Out0(HEX3) );
HexDriver hex_driver_4 ( .In0 (SRAM_ADDR[3:0]), .Out0(HEX4) );
HexDriver hex_driver_5 ( .In0 (SRAM_ADDR[7:4]), .Out0(HEX5) );
HexDriver hex_driver_6 ( .In0 (SRAM_ADDR[11:8]), .Out0(HEX6) );
HexDriver hex_driver_7 ( .In0 (SRAM_ADDR[15:12]), .Out0(HEX7) );
keyboard keyboard_inst(
.Clk (Clk),
.psClk (PS2_KBCLK), .psData(PS2_KBDAT),
.reset (reset),
.keyCode(keycode),
.press (keypress)
);
assign AUD_XCK = CLOCK_50;
logic clk_div, xck_divider;
logic [23:0] dac_left, dac_right;
audio_driver audio_driver_inst(
.CLOCK_50, .reset,
.dac_left( $signed(sram_data_out) ), .dac_right( $signed(sram_data_out) ),
.FPGA_I2C_SCLK(I2C_SCLK), .FPGA_I2C_SDAT(I2C_SDAT), .AUD_DACLRCK,
.AUD_ADCLRCK, .AUD_BCLK, .AUD_ADCDAT, .AUD_DACDAT
);
logic sq_wv;
square_wave sq_inst (
.clk(Clk),
.rst(reset),
.dac_out(sq_wv)
);
sram_reading_fsm sram_reading_fsm_inst(
.Clk, .reset,
.SRAM_CE_N, .SRAM_UB_N, .SRAM_LB_N, .SRAM_OE_N, .SRAM_WE_N,
.SRAM_ADDR,
.sram_data_load,
.start, .cont(clk_div)
);
reg_16 sram_data(
.clk(Clk), .reset,
.load (sram_data_load), .din(SRAM_DQ), .dout (sram_data_out)
);
ClkDivider clk_divider_inst(
.clk(Clk), .rst(reset),
.clk_div
);
aud_xck_divider aud_xck_divider_inst(
.clk (Clk), .rst (reset),
.clk_div(xck_divider)
);
logic [9:0] DrawX, DrawY;
logic ball, background, receptor_background;
logic [3:0] receptor, display_arrow;
logic [3:0] display_signal;
logic [3:0] arrows;
timer counter(.Clk(Clk), .Reset(reset), .arrows(arrows));
vga_controller vga_controller_inst(
.Clk (Clk),
.Reset (reset),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS),
.VGA_CLK (VGA_CLK),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N (VGA_SYNC_N),
.DrawX (DrawX),
.DrawY (DrawY)
);
color_mapper color_mapper_inst(
.is_ball(ball),
.is_receptor(receptor),
.is_background(background),
.is_receptor_background(receptor_background),
.display_arrow(display_arrow),
.DrawX (DrawX),
.DrawY (DrawY),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B)
);
ball ball_inst(
.Clk (Clk),
.Reset (reset),
.frame_clk (VGA_VS),
.DrawX (DrawX),
.DrawY (DrawY),
.keycode (keycode[7:0]),
.is_ball (ball)
);
receptor receptor_inst(
.is_receptor (receptor),
.is_receptor_background(receptor_background),
.is_background (background),
.keycode (keycode[7:0]),
.DrawX(DrawX), .DrawY(DrawY)
);
arrow arrow_inst(
.Clk (Clk),
.reset (reset),
.frame_clk (VGA_VS),
.display_signal(display_signal),
.display_arrow(display_arrow),
.DrawX (DrawX), .DrawY (DrawY)
);
endmodule | 0 |
3,941 | data/full_repos/permissive/107757225/toplevel.sv | 107,757,225 | toplevel.sv | sv | 211 | 80 | [] | [] | [] | null | line:93: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/toplevel.sv:206: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'toplevel\'\nmodule toplevel (\n ^~~~~~~~\n : ... Top module \'sync\'\nmodule sync (input logic Clk, d, output logic q );\n ^~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:65: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_0 ( .In0 (sram_data_out[3:0]), .Out0(HEX0) );\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver.v\n data/full_repos/permissive/107757225,data/full_repos/permissive/107757225/HexDriver.sv\n HexDriver\n HexDriver.v\n HexDriver.sv\n obj_dir/HexDriver\n obj_dir/HexDriver.v\n obj_dir/HexDriver.sv\n%Error: data/full_repos/permissive/107757225/toplevel.sv:66: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_1 ( .In0 (sram_data_out[7:4]), .Out0(HEX1) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:67: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_2 ( .In0 (sram_data_out[11:8]), .Out0(HEX2) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:68: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_3 ( .In0 (sram_data_out[15:12]), .Out0(HEX3) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:70: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_4 ( .In0 (SRAM_ADDR[3:0]), .Out0(HEX4) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:71: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_5 ( .In0 (SRAM_ADDR[7:4]), .Out0(HEX5) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:72: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_6 ( .In0 (SRAM_ADDR[11:8]), .Out0(HEX6) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:73: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_driver_7 ( .In0 (SRAM_ADDR[15:12]), .Out0(HEX7) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:75: Cannot find file containing module: \'keyboard\'\nkeyboard keyboard_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:92: Cannot find file containing module: \'audio_driver\'\naudio_driver audio_driver_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:103: Cannot find file containing module: \'square_wave\'\nsquare_wave sq_inst (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:109: Cannot find file containing module: \'sram_reading_fsm\'\nsram_reading_fsm sram_reading_fsm_inst(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:118: Cannot find file containing module: \'reg_16\'\nreg_16 sram_data(\n^~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:123: Cannot find file containing module: \'ClkDivider\'\nClkDivider clk_divider_inst(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:128: Cannot find file containing module: \'aud_xck_divider\'\naud_xck_divider aud_xck_divider_inst(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:146: Cannot find file containing module: \'timer\'\ntimer counter(.Clk(Clk), .Reset(reset), .arrows(arrows));\n^~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:149: Cannot find file containing module: \'vga_controller\'\nvga_controller vga_controller_inst(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:161: Cannot find file containing module: \'color_mapper\'\ncolor_mapper color_mapper_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:174: Cannot find file containing module: \'ball\'\nball ball_inst(\n^~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:184: Cannot find file containing module: \'receptor\'\nreceptor receptor_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/107757225/toplevel.sv:192: Cannot find file containing module: \'arrow\'\narrow arrow_inst(\n^~~~~\n%Error: Exiting due to 21 error(s), 1 warning(s)\n' | 2,142 | module | module sync (input logic Clk, d, output logic q );
always_ff @ (posedge Clk)
begin
q <= d;
end
endmodule | module sync (input logic Clk, d, output logic q ); |
always_ff @ (posedge Clk)
begin
q <= d;
end
endmodule | 0 |
3,942 | data/full_repos/permissive/107757225/audio/clock_divider.sv | 107,757,225 | clock_divider.sv | sv | 71 | 48 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/audio/clock_divider.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ClkDivider\'\nmodule ClkDivider (\n ^~~~~~~~~~\n : ... Top module \'aud_xck_divider\'\nmodule aud_xck_divider (\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 2,144 | module | module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 3000;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule | module ClkDivider (
input clk,
input rst,
output reg clk_div
); |
localparam constantNumber = 3000;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule | 0 |
3,943 | data/full_repos/permissive/107757225/audio/clock_divider.sv | 107,757,225 | clock_divider.sv | sv | 71 | 48 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/audio/clock_divider.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ClkDivider\'\nmodule ClkDivider (\n ^~~~~~~~~~\n : ... Top module \'aud_xck_divider\'\nmodule aud_xck_divider (\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 2,144 | module | module aud_xck_divider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 3;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule | module aud_xck_divider (
input clk,
input rst,
output reg clk_div
); |
localparam constantNumber = 3;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule | 0 |
3,944 | data/full_repos/permissive/107757225/audio/square-wave.sv | 107,757,225 | square-wave.sv | sv | 24 | 97 | [] | [] | [] | [(3, 22)] | null | data/verilator_xmls/7655614e-c32f-4f08-a8e5-4b6b76136bfb.xml | null | 2,145 | module | module square_wave(clk,rst,dac_out);
input clk;
input rst;
output reg dac_out;
reg [11:0] counter;
always @(posedge clk)
begin
if (rst == 1'b1 || counter == 12'd3999)
counter <= 0;
else
counter <= counter + 1'b1;
if (rst == 1'b0 && counter < 12'd2000)
dac_out = 1'b1;
else
dac_out = 1'b0;
end
endmodule | module square_wave(clk,rst,dac_out); |
input clk;
input rst;
output reg dac_out;
reg [11:0] counter;
always @(posedge clk)
begin
if (rst == 1'b1 || counter == 12'd3999)
counter <= 0;
else
counter <= counter + 1'b1;
if (rst == 1'b0 && counter < 12'd2000)
dac_out = 1'b1;
else
dac_out = 1'b0;
end
endmodule | 0 |
3,945 | data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv | 107,757,225 | sram_reading_fsm.sv | sv | 114 | 102 | [] | [] | [] | null | line:24: before: "logic" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv:21: Output port connection \'dout\' expects 16 bits on the pin connection, but pin connection\'s REPLICATE generates 20 bits.\n : ... In instance sram_reading_fsm\n .load (sram_reg_load), .dout({4\'b0, SRAM_ADDR[15:0]})\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,146 | module | module sram_reading_fsm (
input Clk,
input reset,
input start, cont,
output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
output logic [19:0] SRAM_ADDR,
output logic sram_data_load
);
logic sram_reg_load;
counter_reg sram_reg(
.clk(Clk), .reset(reset),
.load (sram_reg_load), .dout({4'b0, SRAM_ADDR[15:0]})
);
enum logic [2:0] {
halted,
reading_sample_1,
reading_sample_2,
reading_sample_3,
done
} state, next_state;
always_ff @ (posedge Clk)
begin
if (reset)
state <= halted;
else
state <= next_state;
end
always_comb
begin
next_state = state;
unique case (state)
halted :
if (cont)
next_state = reading_sample_1;
reading_sample_1:
next_state = reading_sample_2;
reading_sample_2:
next_state = reading_sample_3;
reading_sample_3:
if(~cont)
next_state = done;
done:
next_state = halted;
default : ;
endcase
SRAM_OE_N = 1'b1;
SRAM_WE_N = 1'b1;
sram_reg_load = 1'b0;
sram_data_load = 1'b0;
SRAM_CE_N = 1'b0;
SRAM_UB_N = 1'b0;
SRAM_LB_N = 1'b0;
case (state)
reading_sample_1:
begin
SRAM_OE_N = 1'b0;
end
reading_sample_2:
begin
SRAM_OE_N = 1'b0;
end
reading_sample_3:
begin
SRAM_OE_N = 1'b0;
sram_data_load = 1'b1;
end
done:
sram_reg_load = 1'b1;
default: ;
endcase
end
endmodule | module sram_reading_fsm (
input Clk,
input reset,
input start, cont,
output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
output logic [19:0] SRAM_ADDR,
output logic sram_data_load
); |
logic sram_reg_load;
counter_reg sram_reg(
.clk(Clk), .reset(reset),
.load (sram_reg_load), .dout({4'b0, SRAM_ADDR[15:0]})
);
enum logic [2:0] {
halted,
reading_sample_1,
reading_sample_2,
reading_sample_3,
done
} state, next_state;
always_ff @ (posedge Clk)
begin
if (reset)
state <= halted;
else
state <= next_state;
end
always_comb
begin
next_state = state;
unique case (state)
halted :
if (cont)
next_state = reading_sample_1;
reading_sample_1:
next_state = reading_sample_2;
reading_sample_2:
next_state = reading_sample_3;
reading_sample_3:
if(~cont)
next_state = done;
done:
next_state = halted;
default : ;
endcase
SRAM_OE_N = 1'b1;
SRAM_WE_N = 1'b1;
sram_reg_load = 1'b0;
sram_data_load = 1'b0;
SRAM_CE_N = 1'b0;
SRAM_UB_N = 1'b0;
SRAM_LB_N = 1'b0;
case (state)
reading_sample_1:
begin
SRAM_OE_N = 1'b0;
end
reading_sample_2:
begin
SRAM_OE_N = 1'b0;
end
reading_sample_3:
begin
SRAM_OE_N = 1'b0;
sram_data_load = 1'b1;
end
done:
sram_reg_load = 1'b1;
default: ;
endcase
end
endmodule | 0 |
3,946 | data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv | 107,757,225 | sram_reading_fsm.sv | sv | 114 | 102 | [] | [] | [] | null | line:24: before: "logic" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv:21: Output port connection \'dout\' expects 16 bits on the pin connection, but pin connection\'s REPLICATE generates 20 bits.\n : ... In instance sram_reading_fsm\n .load (sram_reg_load), .dout({4\'b0, SRAM_ADDR[15:0]})\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,146 | module | module counter_reg (
input logic clk,
input logic reset,
input logic load,
output logic [15:0] dout
);
always_ff @(posedge clk)
begin
if(reset) begin
dout <= 16'b0;
end
else if(load) begin
dout <= dout+1;
end
end
endmodule | module counter_reg (
input logic clk,
input logic reset,
input logic load,
output logic [15:0] dout
); |
always_ff @(posedge clk)
begin
if(reset) begin
dout <= 16'b0;
end
else if(load) begin
dout <= dout+1;
end
end
endmodule | 0 |
3,947 | data/full_repos/permissive/107757225/audio/test_memory.sv | 107,757,225 | test_memory.sv | sv | 195 | 90 | [] | [] | [] | null | line:188: before: "integer" | data/verilator_xmls/5561fd02-23cb-4e0f-9bfb-2b2e05e355bd.xml | null | 2,147 | module | module test_memory ( input Clk,
input reset,
input [19:0] SRAM_ADDR,
input SRAM_CE_N,
SRAM_UB_N,
SRAM_LB_N,
SRAM_OE_N,
SRAM_WE_N
);
parameter size = 256;
logic [15:0] mem [size-1:0];
always_ff @ (posedge Clk or posedge reset)
begin
if(reset)
begin
mem[0] <= 16'hf3ff;
mem[1] <= 16'h0000;
mem[2] <= 16'hf0ff;
mem[3] <= 16'h0000;
mem[4] <= 16'hfbff;
mem[5] <= 16'hf1ff;
mem[6] <= 16'hffff;
mem[7] <= 16'hffff;
mem[8] <= 16'hf9ff;
mem[9] <= 16'hf7ff;
mem[10] <= 16'hf7ff;
mem[11] <= 16'hf3ff;
mem[12] <= 16'hffff;
mem[13] <= 16'hfdff;
mem[14] <= 16'hfbff;
mem[15] <= 16'hf9ff;
mem[16] <= 16'hfbff;
mem[17] <= 16'hf9ff;
mem[18] <= 16'hffff;
mem[19] <= 16'hfbff;
mem[20] <= 16'hfdff;
mem[21] <= 16'hf9ff;
mem[22] <= 16'hfdff;
mem[23] <= 16'hf2ff;
mem[24] <= 16'hffff;
mem[25] <= 16'hffff;
mem[26] <= 16'hfbff;
mem[27] <= 16'hfbff;
mem[28] <= 16'h0200;
mem[29] <= 16'hf5ff;
mem[30] <= 16'hfbff;
mem[31] <= 16'hffff;
mem[32] <= 16'hfbff;
mem[33] <= 16'hf9ff;
mem[34] <= 16'hf5ff;
mem[35] <= 16'h0000;
mem[36] <= 16'hf9ff;
mem[37] <= 16'hfdff;
mem[38] <= 16'hf9ff;
mem[39] <= 16'hf9ff;
mem[40] <= 16'hf9ff;
mem[41] <= 16'h0000;
mem[42] <= 16'hf7ff;
mem[43] <= 16'hf5ff;
mem[44] <= 16'hffff;
mem[45] <= 16'hf2ff;
mem[46] <= 16'h0000;
mem[47] <= 16'hffff;
mem[48] <= 16'hfbff;
mem[49] <= 16'hffff;
mem[50] <= 16'hf5ff;
mem[51] <= 16'hffff;
mem[52] <= 16'hf3ff;
mem[53] <= 16'h0300;
mem[54] <= 16'hfbff;
mem[55] <= 16'hf5ff;
mem[56] <= 16'hffff;
mem[57] <= 16'hf9ff;
mem[58] <= 16'hfbff;
mem[59] <= 16'hf7ff;
mem[60] <= 16'hffff;
mem[61] <= 16'hfbff;
mem[62] <= 16'hfdff;
mem[63] <= 16'hffff;
mem[64] <= 16'hf2ff;
mem[65] <= 16'hfdff;
mem[66] <= 16'hfbff;
mem[67] <= 16'hf9ff;
mem[68] <= 16'hf7ff;
mem[69] <= 16'hf9ff;
mem[70] <= 16'hf7ff;
mem[71] <= 16'hfdff;
mem[72] <= 16'hfdff;
mem[73] <= 16'hf9ff;
mem[74] <= 16'hffff;
mem[75] <= 16'hfbff;
mem[76] <= 16'hffff;
mem[77] <= 16'hf7ff;
mem[78] <= 16'hfdff;
mem[79] <= 16'hf9ff;
mem[80] <= 16'hf0ff;
mem[81] <= 16'h0700;
mem[82] <= 16'hf9ff;
mem[83] <= 16'hfbff;
mem[84] <= 16'hfbff;
mem[85] <= 16'hfdff;
mem[86] <= 16'hf9ff;
mem[87] <= 16'hf9ff;
mem[88] <= 16'hf9ff;
mem[89] <= 16'h0300;
mem[90] <= 16'hfdff;
mem[91] <= 16'hfdff;
mem[92] <= 16'hfdff;
mem[93] <= 16'hffff;
mem[94] <= 16'hffff;
mem[95] <= 16'hf9ff;
mem[96] <= 16'hfbff;
mem[97] <= 16'h0200;
mem[98] <= 16'hffff;
mem[99] <= 16'hffff;
mem[100] <= 16'h0000;
mem[101] <= 16'h0200;
mem[102] <= 16'hffff;
mem[103] <= 16'hfdff;
mem[104] <= 16'h0400;
mem[105] <= 16'hfdff;
mem[106] <= 16'hfdff;
mem[107] <= 16'h0000;
mem[108] <= 16'hfbff;
mem[109] <= 16'hfdff;
mem[110] <= 16'hfdff;
mem[111] <= 16'h0200;
mem[112] <= 16'hf2ff;
mem[113] <= 16'h0500;
mem[114] <= 16'hf7ff;
mem[115] <= 16'h0700;
mem[116] <= 16'hf9ff;
mem[117] <= 16'hf9ff;
mem[118] <= 16'h0700;
mem[119] <= 16'hf9ff;
mem[120] <= 16'h0200;
mem[121] <= 16'h0200;
mem[122] <= 16'hfbff;
mem[123] <= 16'hfbff;
mem[124] <= 16'h0700;
mem[125] <= 16'hfdff;
mem[126] <= 16'h0300;
mem[127] <= 16'hf9ff;
mem[128] <= 16'h0400;
mem[129] <= 16'hfdff;
mem[130] <= 16'hfdff;
mem[131] <= 16'h0900;
mem[132] <= 16'hf7ff;
mem[133] <= 16'h0500;
mem[134] <= 16'h0300;
mem[135] <= 16'hfdff;
mem[136] <= 16'h0200;
mem[137] <= 16'hfdff;
mem[138] <= 16'hfdff;
mem[139] <= 16'h0400;
mem[140] <= 16'hffff;
mem[141] <= 16'h0500;
mem[142] <= 16'hfbff;
mem[143] <= 16'hfdff;
mem[144] <= 16'h0900;
mem[145] <= 16'h0200;
mem[146] <= 16'h0200;
mem[147] <= 16'hffff;
mem[148] <= 16'h0200;
mem[149] <= 16'h0300;
mem[150] <= 16'h0000;
mem[151] <= 16'h0d00;
mem[152] <= 16'hfdff;
mem[153] <= 16'hfdff;
mem[154] <= 16'h0000;
mem[155] <= 16'h0500;
for (integer i = 156; i <= size - 1; i = i + 1)
begin
mem[i] <= 16'h0;
end
end
end
endmodule | module test_memory ( input Clk,
input reset,
input [19:0] SRAM_ADDR,
input SRAM_CE_N,
SRAM_UB_N,
SRAM_LB_N,
SRAM_OE_N,
SRAM_WE_N
); |
parameter size = 256;
logic [15:0] mem [size-1:0];
always_ff @ (posedge Clk or posedge reset)
begin
if(reset)
begin
mem[0] <= 16'hf3ff;
mem[1] <= 16'h0000;
mem[2] <= 16'hf0ff;
mem[3] <= 16'h0000;
mem[4] <= 16'hfbff;
mem[5] <= 16'hf1ff;
mem[6] <= 16'hffff;
mem[7] <= 16'hffff;
mem[8] <= 16'hf9ff;
mem[9] <= 16'hf7ff;
mem[10] <= 16'hf7ff;
mem[11] <= 16'hf3ff;
mem[12] <= 16'hffff;
mem[13] <= 16'hfdff;
mem[14] <= 16'hfbff;
mem[15] <= 16'hf9ff;
mem[16] <= 16'hfbff;
mem[17] <= 16'hf9ff;
mem[18] <= 16'hffff;
mem[19] <= 16'hfbff;
mem[20] <= 16'hfdff;
mem[21] <= 16'hf9ff;
mem[22] <= 16'hfdff;
mem[23] <= 16'hf2ff;
mem[24] <= 16'hffff;
mem[25] <= 16'hffff;
mem[26] <= 16'hfbff;
mem[27] <= 16'hfbff;
mem[28] <= 16'h0200;
mem[29] <= 16'hf5ff;
mem[30] <= 16'hfbff;
mem[31] <= 16'hffff;
mem[32] <= 16'hfbff;
mem[33] <= 16'hf9ff;
mem[34] <= 16'hf5ff;
mem[35] <= 16'h0000;
mem[36] <= 16'hf9ff;
mem[37] <= 16'hfdff;
mem[38] <= 16'hf9ff;
mem[39] <= 16'hf9ff;
mem[40] <= 16'hf9ff;
mem[41] <= 16'h0000;
mem[42] <= 16'hf7ff;
mem[43] <= 16'hf5ff;
mem[44] <= 16'hffff;
mem[45] <= 16'hf2ff;
mem[46] <= 16'h0000;
mem[47] <= 16'hffff;
mem[48] <= 16'hfbff;
mem[49] <= 16'hffff;
mem[50] <= 16'hf5ff;
mem[51] <= 16'hffff;
mem[52] <= 16'hf3ff;
mem[53] <= 16'h0300;
mem[54] <= 16'hfbff;
mem[55] <= 16'hf5ff;
mem[56] <= 16'hffff;
mem[57] <= 16'hf9ff;
mem[58] <= 16'hfbff;
mem[59] <= 16'hf7ff;
mem[60] <= 16'hffff;
mem[61] <= 16'hfbff;
mem[62] <= 16'hfdff;
mem[63] <= 16'hffff;
mem[64] <= 16'hf2ff;
mem[65] <= 16'hfdff;
mem[66] <= 16'hfbff;
mem[67] <= 16'hf9ff;
mem[68] <= 16'hf7ff;
mem[69] <= 16'hf9ff;
mem[70] <= 16'hf7ff;
mem[71] <= 16'hfdff;
mem[72] <= 16'hfdff;
mem[73] <= 16'hf9ff;
mem[74] <= 16'hffff;
mem[75] <= 16'hfbff;
mem[76] <= 16'hffff;
mem[77] <= 16'hf7ff;
mem[78] <= 16'hfdff;
mem[79] <= 16'hf9ff;
mem[80] <= 16'hf0ff;
mem[81] <= 16'h0700;
mem[82] <= 16'hf9ff;
mem[83] <= 16'hfbff;
mem[84] <= 16'hfbff;
mem[85] <= 16'hfdff;
mem[86] <= 16'hf9ff;
mem[87] <= 16'hf9ff;
mem[88] <= 16'hf9ff;
mem[89] <= 16'h0300;
mem[90] <= 16'hfdff;
mem[91] <= 16'hfdff;
mem[92] <= 16'hfdff;
mem[93] <= 16'hffff;
mem[94] <= 16'hffff;
mem[95] <= 16'hf9ff;
mem[96] <= 16'hfbff;
mem[97] <= 16'h0200;
mem[98] <= 16'hffff;
mem[99] <= 16'hffff;
mem[100] <= 16'h0000;
mem[101] <= 16'h0200;
mem[102] <= 16'hffff;
mem[103] <= 16'hfdff;
mem[104] <= 16'h0400;
mem[105] <= 16'hfdff;
mem[106] <= 16'hfdff;
mem[107] <= 16'h0000;
mem[108] <= 16'hfbff;
mem[109] <= 16'hfdff;
mem[110] <= 16'hfdff;
mem[111] <= 16'h0200;
mem[112] <= 16'hf2ff;
mem[113] <= 16'h0500;
mem[114] <= 16'hf7ff;
mem[115] <= 16'h0700;
mem[116] <= 16'hf9ff;
mem[117] <= 16'hf9ff;
mem[118] <= 16'h0700;
mem[119] <= 16'hf9ff;
mem[120] <= 16'h0200;
mem[121] <= 16'h0200;
mem[122] <= 16'hfbff;
mem[123] <= 16'hfbff;
mem[124] <= 16'h0700;
mem[125] <= 16'hfdff;
mem[126] <= 16'h0300;
mem[127] <= 16'hf9ff;
mem[128] <= 16'h0400;
mem[129] <= 16'hfdff;
mem[130] <= 16'hfdff;
mem[131] <= 16'h0900;
mem[132] <= 16'hf7ff;
mem[133] <= 16'h0500;
mem[134] <= 16'h0300;
mem[135] <= 16'hfdff;
mem[136] <= 16'h0200;
mem[137] <= 16'hfdff;
mem[138] <= 16'hfdff;
mem[139] <= 16'h0400;
mem[140] <= 16'hffff;
mem[141] <= 16'h0500;
mem[142] <= 16'hfbff;
mem[143] <= 16'hfdff;
mem[144] <= 16'h0900;
mem[145] <= 16'h0200;
mem[146] <= 16'h0200;
mem[147] <= 16'hffff;
mem[148] <= 16'h0200;
mem[149] <= 16'h0300;
mem[150] <= 16'h0000;
mem[151] <= 16'h0d00;
mem[152] <= 16'hfdff;
mem[153] <= 16'hfdff;
mem[154] <= 16'h0000;
mem[155] <= 16'h0500;
for (integer i = 156; i <= size - 1; i = i + 1)
begin
mem[i] <= 16'h0;
end
end
end
endmodule | 0 |
3,948 | data/full_repos/permissive/107757225/audio/audio-altera/DE2_115_Audio.v | 107,757,225 | DE2_115_Audio.v | v | 607 | 96 | [] | [] | [] | [(44, 606)] | null | null | 1: b"%Error: data/full_repos/permissive/107757225/audio/audio-altera/DE2_115_Audio.v:461: Cannot find file containing module: 'audio_nios'\naudio_nios nios_audio_ins(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios\n data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios.v\n data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios.sv\n audio_nios\n audio_nios.v\n audio_nios.sv\n obj_dir/audio_nios\n obj_dir/audio_nios.v\n obj_dir/audio_nios.sv\n%Error: Exiting due to 1 error(s)\n" | 2,149 | module | module DE2_115_Audio(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
SMA_CLKIN,
SMA_CLKOUT,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
EEP_I2C_SCLK,
EEP_I2C_SDAT,
I2C_SCLK,
I2C_SDAT,
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
IRDA_RXD,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
GPIO,
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
HSMC_RX_D_P,
HSMC_TX_D_P,
EX_IO
);
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input ENETCLK_25;
input SMA_CLKIN;
output SMA_CLKOUT;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output LCD_BLON;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
input UART_CTS;
output UART_RTS;
input UART_RXD;
output UART_TXD;
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_N;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output EEP_I2C_SCLK;
inout EEP_I2C_SDAT;
output I2C_SCLK;
inout I2C_SDAT;
output ENET0_GTX_CLK;
input ENET0_INT_N;
output ENET0_MDC;
input ENET0_MDIO;
output ENET0_RST_N;
input ENET0_RX_CLK;
input ENET0_RX_COL;
input ENET0_RX_CRS;
input [3:0] ENET0_RX_DATA;
input ENET0_RX_DV;
input ENET0_RX_ER;
input ENET0_TX_CLK;
output [3:0] ENET0_TX_DATA;
output ENET0_TX_EN;
output ENET0_TX_ER;
input ENET0_LINK100;
output ENET1_GTX_CLK;
input ENET1_INT_N;
output ENET1_MDC;
input ENET1_MDIO;
output ENET1_RST_N;
input ENET1_RX_CLK;
input ENET1_RX_COL;
input ENET1_RX_CRS;
input [3:0] ENET1_RX_DATA;
input ENET1_RX_DV;
input ENET1_RX_ER;
input ENET1_TX_CLK;
output [3:0] ENET1_TX_DATA;
output ENET1_TX_EN;
output ENET1_TX_ER;
input ENET1_LINK100;
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
inout [15:0] OTG_DATA;
output [1:0] OTG_ADDR;
output OTG_CS_N;
output OTG_WR_N;
output OTG_RD_N;
input OTG_INT;
output OTG_RST_N;
input IRDA_RXD;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [31:0] DRAM_DQ;
output [3:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
output [22:0] FL_ADDR;
output FL_CE_N;
inout [7:0] FL_DQ;
output FL_OE_N;
output FL_RST_N;
input FL_RY;
output FL_WE_N;
output FL_WP_N;
inout [35:0] GPIO;
input HSMC_CLKIN_P1;
input HSMC_CLKIN_P2;
input HSMC_CLKIN0;
output HSMC_CLKOUT_P1;
output HSMC_CLKOUT_P2;
output HSMC_CLKOUT0;
inout [3:0] HSMC_D;
input [16:0] HSMC_RX_D_P;
output [16:0] HSMC_TX_D_P;
inout [6:0] EX_IO;
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
wire HEX6P;
wire HEX7P;
wire reset_n;
assign reset_n = 1'b1;
audio_nios nios_audio_ins(
.clk_clk(CLOCK_50),
.reset_reset_n(reset_n),
.altpll_c3_clk(),
.altpll_c1_clk(DRAM_CLK),
.audio_conduit_end_ADCDAT(AUD_ADCDAT),
.audio_conduit_end_ADCLRC(AUD_ADCLRCK),
.audio_conduit_end_BCLK(AUD_BCLK),
.audio_conduit_end_DACDAT(AUD_DACDAT),
.audio_conduit_end_DACLRC(AUD_DACLRCK),
.audio_conduit_end_XCK (AUD_XCK),
.epp_i2c_scl_external_connection_export(EEP_I2C_SCLK),
.epp_i2c_sda_external_connection_export(EEP_I2C_SDAT),
.i2c_scl_external_connection_export(I2C_SCLK),
.i2c_sda_external_connection_export(I2C_SDAT),
.key_external_connection_export(KEY),
.lcd_external_E(LCD_EN),
.lcd_external_RS(LCD_RS),
.lcd_external_RW(LCD_RW),
.lcd_external_data(LCD_DATA),
.sdram_wire_addr(DRAM_ADDR),
.sdram_wire_ba(DRAM_BA),
.sdram_wire_cas_n(DRAM_CAS_N),
.sdram_wire_cke(DRAM_CKE),
.sdram_wire_cs_n(DRAM_CS_N),
.sdram_wire_dq(DRAM_DQ),
.sdram_wire_dqm(DRAM_DQM),
.sdram_wire_ras_n(DRAM_RAS_N),
.sdram_wire_we_n(DRAM_WE_N),
.seg7_conduit_end_export({
HEX7P, HEX7, HEX6P, HEX6,
HEX5P, HEX5, HEX4P, HEX4,
HEX3P, HEX3, HEX2P, HEX2,
HEX1P, HEX1, HEX0P, HEX0}),
.sram_conduit_end_ADDR(SRAM_ADDR),
.sram_conduit_end_CE_n(SRAM_CE_N),
.sram_conduit_end_DQ(SRAM_DQ),
.sram_conduit_end_LB_n(SRAM_LB_N),
.sram_conduit_end_OE_n(SRAM_OE_N),
.sram_conduit_end_UB_n(SRAM_UB_N),
.sram_conduit_end_WE_n(SRAM_WE_N),
.sw_external_connection_export(SW),
.pio_0_external_connection_export({LEDG,LEDR[17:1]}),
.tri_state_bridge_flash_bridge_0_out_address_to_the_cfi_flash (FL_ADDR),
.tri_state_bridge_flash_bridge_0_out_read_n_to_the_cfi_flash(FL_OE_N),
.tri_state_bridge_flash_bridge_0_out_select_n_to_the_cfi_flash(FL_CE_N),
.tri_state_bridge_flash_bridge_0_out_tri_state_bridge_flash_data(FL_DQ),
.tri_state_bridge_flash_bridge_0_out_write_n_to_the_cfi_flash(FL_WE_N),
.sd_clk_external_connection_export(SD_CLK),
.sd_cmd_external_connection_export(SD_CMD),
.sd_dat_external_connection_export(SD_DAT),
.sd_wp_n_external_connection_export (SD_WP_N)
);
assign FL_RST_N = reset_n;
assign FL_WP_N = 1'b1;
assign LCD_BLON = 0;
assign LCD_ON = 1'b1;
wire io_dir;
wire action;
assign io_dir = KEY[0] & action;
assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;
assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
assign HSMC_TX_D_P = HSMC_RX_D_P;
assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
assign ENET0_GTX_CLK = ENET0_INT_N;
assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;
assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;
assign ENET1_GTX_CLK = ENET1_INT_N;
assign ENET1_MDC = ENET1_RX_COL;
assign ENET1_RST_N = ENET1_RX_CRS;
assign ENET1_TX_DATA = ENET1_RX_DATA;
assign ENET1_TX_EN = ENET1_RX_ER;
assign ENET1_TX_ER = ENET1_TX_CLK;
assign TD_RESET_N = TD_VS;
assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);
assign PS2_CLK = PS2_DAT;
assign PS2_CLK2 = PS2_DAT2;
endmodule | module DE2_115_Audio(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
SMA_CLKIN,
SMA_CLKOUT,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
EEP_I2C_SCLK,
EEP_I2C_SDAT,
I2C_SCLK,
I2C_SDAT,
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
IRDA_RXD,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
GPIO,
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
HSMC_RX_D_P,
HSMC_TX_D_P,
EX_IO
); |
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input ENETCLK_25;
input SMA_CLKIN;
output SMA_CLKOUT;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output LCD_BLON;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
input UART_CTS;
output UART_RTS;
input UART_RXD;
output UART_TXD;
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_N;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output EEP_I2C_SCLK;
inout EEP_I2C_SDAT;
output I2C_SCLK;
inout I2C_SDAT;
output ENET0_GTX_CLK;
input ENET0_INT_N;
output ENET0_MDC;
input ENET0_MDIO;
output ENET0_RST_N;
input ENET0_RX_CLK;
input ENET0_RX_COL;
input ENET0_RX_CRS;
input [3:0] ENET0_RX_DATA;
input ENET0_RX_DV;
input ENET0_RX_ER;
input ENET0_TX_CLK;
output [3:0] ENET0_TX_DATA;
output ENET0_TX_EN;
output ENET0_TX_ER;
input ENET0_LINK100;
output ENET1_GTX_CLK;
input ENET1_INT_N;
output ENET1_MDC;
input ENET1_MDIO;
output ENET1_RST_N;
input ENET1_RX_CLK;
input ENET1_RX_COL;
input ENET1_RX_CRS;
input [3:0] ENET1_RX_DATA;
input ENET1_RX_DV;
input ENET1_RX_ER;
input ENET1_TX_CLK;
output [3:0] ENET1_TX_DATA;
output ENET1_TX_EN;
output ENET1_TX_ER;
input ENET1_LINK100;
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
inout [15:0] OTG_DATA;
output [1:0] OTG_ADDR;
output OTG_CS_N;
output OTG_WR_N;
output OTG_RD_N;
input OTG_INT;
output OTG_RST_N;
input IRDA_RXD;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [31:0] DRAM_DQ;
output [3:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
output [22:0] FL_ADDR;
output FL_CE_N;
inout [7:0] FL_DQ;
output FL_OE_N;
output FL_RST_N;
input FL_RY;
output FL_WE_N;
output FL_WP_N;
inout [35:0] GPIO;
input HSMC_CLKIN_P1;
input HSMC_CLKIN_P2;
input HSMC_CLKIN0;
output HSMC_CLKOUT_P1;
output HSMC_CLKOUT_P2;
output HSMC_CLKOUT0;
inout [3:0] HSMC_D;
input [16:0] HSMC_RX_D_P;
output [16:0] HSMC_TX_D_P;
inout [6:0] EX_IO;
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
wire HEX6P;
wire HEX7P;
wire reset_n;
assign reset_n = 1'b1;
audio_nios nios_audio_ins(
.clk_clk(CLOCK_50),
.reset_reset_n(reset_n),
.altpll_c3_clk(),
.altpll_c1_clk(DRAM_CLK),
.audio_conduit_end_ADCDAT(AUD_ADCDAT),
.audio_conduit_end_ADCLRC(AUD_ADCLRCK),
.audio_conduit_end_BCLK(AUD_BCLK),
.audio_conduit_end_DACDAT(AUD_DACDAT),
.audio_conduit_end_DACLRC(AUD_DACLRCK),
.audio_conduit_end_XCK (AUD_XCK),
.epp_i2c_scl_external_connection_export(EEP_I2C_SCLK),
.epp_i2c_sda_external_connection_export(EEP_I2C_SDAT),
.i2c_scl_external_connection_export(I2C_SCLK),
.i2c_sda_external_connection_export(I2C_SDAT),
.key_external_connection_export(KEY),
.lcd_external_E(LCD_EN),
.lcd_external_RS(LCD_RS),
.lcd_external_RW(LCD_RW),
.lcd_external_data(LCD_DATA),
.sdram_wire_addr(DRAM_ADDR),
.sdram_wire_ba(DRAM_BA),
.sdram_wire_cas_n(DRAM_CAS_N),
.sdram_wire_cke(DRAM_CKE),
.sdram_wire_cs_n(DRAM_CS_N),
.sdram_wire_dq(DRAM_DQ),
.sdram_wire_dqm(DRAM_DQM),
.sdram_wire_ras_n(DRAM_RAS_N),
.sdram_wire_we_n(DRAM_WE_N),
.seg7_conduit_end_export({
HEX7P, HEX7, HEX6P, HEX6,
HEX5P, HEX5, HEX4P, HEX4,
HEX3P, HEX3, HEX2P, HEX2,
HEX1P, HEX1, HEX0P, HEX0}),
.sram_conduit_end_ADDR(SRAM_ADDR),
.sram_conduit_end_CE_n(SRAM_CE_N),
.sram_conduit_end_DQ(SRAM_DQ),
.sram_conduit_end_LB_n(SRAM_LB_N),
.sram_conduit_end_OE_n(SRAM_OE_N),
.sram_conduit_end_UB_n(SRAM_UB_N),
.sram_conduit_end_WE_n(SRAM_WE_N),
.sw_external_connection_export(SW),
.pio_0_external_connection_export({LEDG,LEDR[17:1]}),
.tri_state_bridge_flash_bridge_0_out_address_to_the_cfi_flash (FL_ADDR),
.tri_state_bridge_flash_bridge_0_out_read_n_to_the_cfi_flash(FL_OE_N),
.tri_state_bridge_flash_bridge_0_out_select_n_to_the_cfi_flash(FL_CE_N),
.tri_state_bridge_flash_bridge_0_out_tri_state_bridge_flash_data(FL_DQ),
.tri_state_bridge_flash_bridge_0_out_write_n_to_the_cfi_flash(FL_WE_N),
.sd_clk_external_connection_export(SD_CLK),
.sd_cmd_external_connection_export(SD_CMD),
.sd_dat_external_connection_export(SD_DAT),
.sd_wp_n_external_connection_export (SD_WP_N)
);
assign FL_RST_N = reset_n;
assign FL_WP_N = 1'b1;
assign LCD_BLON = 0;
assign LCD_ON = 1'b1;
wire io_dir;
wire action;
assign io_dir = KEY[0] & action;
assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;
assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
assign HSMC_TX_D_P = HSMC_RX_D_P;
assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
assign ENET0_GTX_CLK = ENET0_INT_N;
assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;
assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;
assign ENET1_GTX_CLK = ENET1_INT_N;
assign ENET1_MDC = ENET1_RX_COL;
assign ENET1_RST_N = ENET1_RX_CRS;
assign ENET1_TX_DATA = ENET1_RX_DATA;
assign ENET1_TX_EN = ENET1_RX_ER;
assign ENET1_TX_ER = ENET1_TX_CLK;
assign TD_RESET_N = TD_VS;
assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);
assign PS2_CLK = PS2_DAT;
assign PS2_CLK2 = PS2_DAT2;
endmodule | 0 |
3,949 | data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v | 107,757,225 | AUDIO_ADC.v | v | 139 | 80 | [] | [] | [] | [(1, 137)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:73: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n : ... In instance AUDIO_ADC\n bit_index = DATA_WIDTH;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:89: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n : ... In instance AUDIO_ADC\n bit_index = DATA_WIDTH;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:99: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'bit_index\' generates 5 bits.\n : ... In instance AUDIO_ADC\n if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))\n ^~\n%Error: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:122: Cannot find file containing module: \'audio_fifo\'\naudio_fifo adc_fifo(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.v\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.sv\n audio_fifo\n audio_fifo.v\n audio_fifo.sv\n obj_dir/audio_fifo\n obj_dir/audio_fifo.v\n obj_dir/audio_fifo.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 2,174 | module | module AUDIO_ADC(
clk,
reset,
read,
readdata,
empty,
clear,
bclk,
adclrc,
adcdat
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input read;
output [(DATA_WIDTH-1):0] readdata;
output empty;
input clear;
input bclk;
input adclrc;
input adcdat;
reg [4:0] bit_index;
reg valid_bit;
reg reg_adc_left;
reg [(DATA_WIDTH-1):0] reg_adc_serial_data;
reg [(DATA_WIDTH-1):0] adcfifo_writedata;
reg adcfifo_write;
wire adcfifo_full;
reg wait_one_clk;
wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk)
begin
if (reset || clear)
begin
bit_index = DATA_WIDTH;
reg_adc_left = is_left_ch;
adcfifo_write = 1'b0;
valid_bit = 0;
end
else
begin
if (adcfifo_write)
adcfifo_write = 1'b0;
if (reg_adc_left ^ is_left_ch)
begin
reg_adc_left = is_left_ch;
valid_bit = 1'b1;
wait_one_clk = 1'b1;
if (reg_adc_left)
bit_index = DATA_WIDTH;
end
if (valid_bit && wait_one_clk)
wait_one_clk = 1'b0;
else if (valid_bit && !wait_one_clk)
begin
bit_index = bit_index - 1'b1;
reg_adc_serial_data[bit_index] = adcdat;
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
begin
if (bit_index == 0 && !adcfifo_full)
begin
adcfifo_writedata = reg_adc_serial_data;
adcfifo_write = 1'b1;
end
valid_bit = 0;
end
end
end
end
audio_fifo adc_fifo(
.wrclk(bclk),
.wrreq(adcfifo_write),
.data(adcfifo_writedata),
.wrfull(adcfifo_full),
.aclr(clear),
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdempty(empty)
);
endmodule | module AUDIO_ADC(
clk,
reset,
read,
readdata,
empty,
clear,
bclk,
adclrc,
adcdat
); |
parameter DATA_WIDTH = 32;
input clk;
input reset;
input read;
output [(DATA_WIDTH-1):0] readdata;
output empty;
input clear;
input bclk;
input adclrc;
input adcdat;
reg [4:0] bit_index;
reg valid_bit;
reg reg_adc_left;
reg [(DATA_WIDTH-1):0] reg_adc_serial_data;
reg [(DATA_WIDTH-1):0] adcfifo_writedata;
reg adcfifo_write;
wire adcfifo_full;
reg wait_one_clk;
wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk)
begin
if (reset || clear)
begin
bit_index = DATA_WIDTH;
reg_adc_left = is_left_ch;
adcfifo_write = 1'b0;
valid_bit = 0;
end
else
begin
if (adcfifo_write)
adcfifo_write = 1'b0;
if (reg_adc_left ^ is_left_ch)
begin
reg_adc_left = is_left_ch;
valid_bit = 1'b1;
wait_one_clk = 1'b1;
if (reg_adc_left)
bit_index = DATA_WIDTH;
end
if (valid_bit && wait_one_clk)
wait_one_clk = 1'b0;
else if (valid_bit && !wait_one_clk)
begin
bit_index = bit_index - 1'b1;
reg_adc_serial_data[bit_index] = adcdat;
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
begin
if (bit_index == 0 && !adcfifo_full)
begin
adcfifo_writedata = reg_adc_serial_data;
adcfifo_write = 1'b1;
end
valid_bit = 0;
end
end
end
end
audio_fifo adc_fifo(
.wrclk(bclk),
.wrreq(adcfifo_write),
.data(adcfifo_writedata),
.wrfull(adcfifo_full),
.aclr(clear),
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdempty(empty)
);
endmodule | 0 |
3,950 | data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v | 107,757,225 | AUDIO_DAC.v | v | 147 | 80 | [] | [] | [] | [(1, 143)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:99: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n : ... In instance AUDIO_DAC\n bit_index = DATA_WIDTH;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:109: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'bit_index\' generates 5 bits.\n : ... In instance AUDIO_DAC\n if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))\n ^~\n%Error: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:128: Cannot find file containing module: \'audio_fifo\'\naudio_fifo dac_fifo(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.v\n data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.sv\n audio_fifo\n audio_fifo.v\n audio_fifo.sv\n obj_dir/audio_fifo\n obj_dir/audio_fifo.v\n obj_dir/audio_fifo.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 2,175 | module | module AUDIO_DAC(
clk,
reset,
write,
writedata,
full,
clear,
bclk,
daclrc,
dacdat
);
parameter DATA_WIDTH = 32;
input clk;
input reset;
input write;
input [(DATA_WIDTH-1):0] writedata;
output full;
input clear;
input bclk;
input daclrc;
output dacdat;
reg request_bit;
reg bit_to_dac;
reg [4:0] bit_index;
reg dac_is_left;
reg [(DATA_WIDTH-1):0] data_to_dac;
reg [(DATA_WIDTH-1):0] shift_data_to_dac;
wire dacfifo_empty;
wire dacfifo_read;
wire [(DATA_WIDTH-1):0] dacfifo_readdata;
wire is_left_ch;
assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;
always @ (negedge is_left_ch)
begin
if (dacfifo_empty)
data_to_dac = 0;
else
data_to_dac = dacfifo_readdata;
end
assign is_left_ch = ~daclrc;
always @ (negedge bclk)
begin
if (reset || clear)
begin
request_bit = 0;
bit_index = 0;
dac_is_left = is_left_ch;
bit_to_dac = 1'b0;
end
else
begin
if (dac_is_left ^ is_left_ch)
begin
dac_is_left = is_left_ch;
request_bit = 1;
if (dac_is_left)
begin
shift_data_to_dac = data_to_dac;
bit_index = DATA_WIDTH;
end
end
if (request_bit)
begin
bit_index = bit_index - 1'b1;
bit_to_dac = shift_data_to_dac[bit_index];
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
request_bit = 0;
end
else
bit_to_dac = 1'b0;
end
end
assign dacdat = bit_to_dac;
audio_fifo dac_fifo(
.wrclk(clk),
.wrreq(write),
.data(writedata),
.wrfull(full),
.aclr(clear),
.rdclk(is_left_ch),
.rdreq(dacfifo_read),
.q(dacfifo_readdata),
.rdempty(dacfifo_empty)
);
endmodule | module AUDIO_DAC(
clk,
reset,
write,
writedata,
full,
clear,
bclk,
daclrc,
dacdat
); |
parameter DATA_WIDTH = 32;
input clk;
input reset;
input write;
input [(DATA_WIDTH-1):0] writedata;
output full;
input clear;
input bclk;
input daclrc;
output dacdat;
reg request_bit;
reg bit_to_dac;
reg [4:0] bit_index;
reg dac_is_left;
reg [(DATA_WIDTH-1):0] data_to_dac;
reg [(DATA_WIDTH-1):0] shift_data_to_dac;
wire dacfifo_empty;
wire dacfifo_read;
wire [(DATA_WIDTH-1):0] dacfifo_readdata;
wire is_left_ch;
assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;
always @ (negedge is_left_ch)
begin
if (dacfifo_empty)
data_to_dac = 0;
else
data_to_dac = dacfifo_readdata;
end
assign is_left_ch = ~daclrc;
always @ (negedge bclk)
begin
if (reset || clear)
begin
request_bit = 0;
bit_index = 0;
dac_is_left = is_left_ch;
bit_to_dac = 1'b0;
end
else
begin
if (dac_is_left ^ is_left_ch)
begin
dac_is_left = is_left_ch;
request_bit = 1;
if (dac_is_left)
begin
shift_data_to_dac = data_to_dac;
bit_index = DATA_WIDTH;
end
end
if (request_bit)
begin
bit_index = bit_index - 1'b1;
bit_to_dac = shift_data_to_dac[bit_index];
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
request_bit = 0;
end
else
bit_to_dac = 1'b0;
end
end
assign dacdat = bit_to_dac;
audio_fifo dac_fifo(
.wrclk(clk),
.wrreq(write),
.data(writedata),
.wrfull(full),
.aclr(clear),
.rdclk(is_left_ch),
.rdreq(dacfifo_read),
.q(dacfifo_readdata),
.rdempty(dacfifo_empty)
);
endmodule | 0 |
3,951 | data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_CLOCK/TERASIC_CLOCK_COUNT.v | 107,757,225 | TERASIC_CLOCK_COUNT.v | v | 110 | 55 | [] | [] | [] | [(1, 108)] | null | data/verilator_xmls/bb4f27c0-1d27-4a49-83f8-ccc73651d152.xml | null | 2,228 | module | module TERASIC_CLOCK_COUNT(
s_clk_in,
s_reset_in,
s_address_in,
s_read_in,
s_readdata_out,
s_write_in,
s_writedata_in,
CLK_1,
CLK_2
);
`define REG_START 2'b00
`define REG_READ_CLK1 2'b01
`define REG_READ_CLK2 2'b10
input s_clk_in;
input s_reset_in;
input [1:0] s_address_in;
input s_read_in;
output [31:0] s_readdata_out;
input s_write_in;
input [31:0] s_writedata_in;
input CLK_1;
input CLK_2;
reg [31:0] s_readdata_out;
reg counting_now;
reg [15:0] cnt_down;
reg [15:0] clk1_cnt_latched;
reg [15:0] clk2_cnt_latched;
always @ (posedge s_clk_in or posedge s_reset_in)
begin
if (s_reset_in)
cnt_down <= 0;
else if (s_write_in && s_address_in == `REG_START)
begin
cnt_down <= s_writedata_in[15:0];
counting_now <= (s_writedata_in == 0)?1'b0:1'b1;
end
else if (cnt_down > 1)
cnt_down <= cnt_down - 1;
else
counting_now <= 1'b0;
end
always @ (posedge s_clk_in or posedge s_reset_in)
begin
if (s_reset_in)
s_readdata_out <= 0;
else if (s_read_in && s_address_in == `REG_START)
s_readdata_out <= {31'h0, counting_now};
else if (s_read_in && s_address_in == `REG_READ_CLK1)
s_readdata_out <= {16'h0000, clk1_cnt_latched};
else if (s_read_in && s_address_in == `REG_READ_CLK2)
s_readdata_out <= {16'h0000, clk2_cnt_latched};
end
reg [15:0] clk1_cnt;
reg [15:0] clk2_cnt;
always @ (posedge CLK_1)
begin
if (counting_now)
begin
clk1_cnt <= clk1_cnt + 1;
clk1_cnt_latched <= 0;
end
else if (clk1_cnt != 0)
begin
clk1_cnt_latched <= clk1_cnt;
clk1_cnt <= 0;
end
end
always @ (posedge CLK_2)
begin
if (counting_now)
begin
clk2_cnt <= clk2_cnt + 1;
clk2_cnt_latched <= 0;
end
else if (clk2_cnt != 0)
begin
clk2_cnt_latched <= clk2_cnt;
clk2_cnt <= 0;
end
end
endmodule | module TERASIC_CLOCK_COUNT(
s_clk_in,
s_reset_in,
s_address_in,
s_read_in,
s_readdata_out,
s_write_in,
s_writedata_in,
CLK_1,
CLK_2
); |
`define REG_START 2'b00
`define REG_READ_CLK1 2'b01
`define REG_READ_CLK2 2'b10
input s_clk_in;
input s_reset_in;
input [1:0] s_address_in;
input s_read_in;
output [31:0] s_readdata_out;
input s_write_in;
input [31:0] s_writedata_in;
input CLK_1;
input CLK_2;
reg [31:0] s_readdata_out;
reg counting_now;
reg [15:0] cnt_down;
reg [15:0] clk1_cnt_latched;
reg [15:0] clk2_cnt_latched;
always @ (posedge s_clk_in or posedge s_reset_in)
begin
if (s_reset_in)
cnt_down <= 0;
else if (s_write_in && s_address_in == `REG_START)
begin
cnt_down <= s_writedata_in[15:0];
counting_now <= (s_writedata_in == 0)?1'b0:1'b1;
end
else if (cnt_down > 1)
cnt_down <= cnt_down - 1;
else
counting_now <= 1'b0;
end
always @ (posedge s_clk_in or posedge s_reset_in)
begin
if (s_reset_in)
s_readdata_out <= 0;
else if (s_read_in && s_address_in == `REG_START)
s_readdata_out <= {31'h0, counting_now};
else if (s_read_in && s_address_in == `REG_READ_CLK1)
s_readdata_out <= {16'h0000, clk1_cnt_latched};
else if (s_read_in && s_address_in == `REG_READ_CLK2)
s_readdata_out <= {16'h0000, clk2_cnt_latched};
end
reg [15:0] clk1_cnt;
reg [15:0] clk2_cnt;
always @ (posedge CLK_1)
begin
if (counting_now)
begin
clk1_cnt <= clk1_cnt + 1;
clk1_cnt_latched <= 0;
end
else if (clk1_cnt != 0)
begin
clk1_cnt_latched <= clk1_cnt;
clk1_cnt <= 0;
end
end
always @ (posedge CLK_2)
begin
if (counting_now)
begin
clk2_cnt <= clk2_cnt + 1;
clk2_cnt_latched <= 0;
end
else if (clk2_cnt != 0)
begin
clk2_cnt_latched <= clk2_cnt;
clk2_cnt <= 0;
end
end
endmodule | 0 |
3,952 | data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_ISP1362/ISP1362_IF.v | 107,757,225 | ISP1362_IF.v | v | 84 | 170 | [] | [] | [] | [(1, 84)] | null | data/verilator_xmls/c33cc117-505c-4f9c-a8e3-c7f98e4c107d.xml | null | 2,229 | module | module ISP1362_IF(
avs_hc_writedata_iDATA,
avs_hc_readdata_oDATA,
avs_hc_address_iADDR,
avs_hc_read_n_iRD_N,
avs_hc_write_n_iWR_N,
avs_hc_chipselect_n_iCS_N,
avs_hc_reset_n_iRST_N,
avs_hc_clk_iCLK,
avs_hc_irq_n_oINT0_N,
avs_dc_writedata_iDATA,
avs_dc_readdata_oDATA,
avs_dc_address_iADDR,
avs_dc_read_n_iRD_N,
avs_dc_write_n_iWR_N,
avs_dc_chipselect_n_iCS_N,
avs_dc_reset_n_iRST_N,
avs_dc_clk_iCLK,
avs_dc_irq_n_oINT0_N,
USB_DATA,
USB_ADDR,
USB_RD_N,
USB_WR_N,
USB_CS_N,
USB_RST_N,
USB_INT0,
USB_INT1
);
input [15:0] avs_hc_writedata_iDATA;
input avs_hc_address_iADDR;
input avs_hc_read_n_iRD_N;
input avs_hc_write_n_iWR_N;
input avs_hc_chipselect_n_iCS_N;
input avs_hc_reset_n_iRST_N;
input avs_hc_clk_iCLK;
output [15:0] avs_hc_readdata_oDATA;
output avs_hc_irq_n_oINT0_N;
input [15:0] avs_dc_writedata_iDATA;
input avs_dc_address_iADDR;
input avs_dc_read_n_iRD_N;
input avs_dc_write_n_iWR_N;
input avs_dc_chipselect_n_iCS_N;
input avs_dc_reset_n_iRST_N;
input avs_dc_clk_iCLK;
output [15:0] avs_dc_readdata_oDATA;
output avs_dc_irq_n_oINT0_N;
inout [15:0] USB_DATA;
output [1:0] USB_ADDR;
output USB_RD_N;
output USB_WR_N;
output USB_CS_N;
output USB_RST_N;
input USB_INT0;
input USB_INT1;
assign USB_DATA = avs_dc_chipselect_n_iCS_N ? (avs_hc_write_n_iWR_N ? 16'hzzzz : avs_hc_writedata_iDATA) : (avs_dc_write_n_iWR_N ? 16'hzzzz : avs_dc_writedata_iDATA) ;
assign avs_hc_readdata_oDATA = avs_hc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign avs_dc_readdata_oDATA = avs_dc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign USB_ADDR = avs_dc_chipselect_n_iCS_N? {1'b0,avs_hc_address_iADDR} : {1'b1,avs_dc_address_iADDR};
assign USB_CS_N = avs_hc_chipselect_n_iCS_N & avs_dc_chipselect_n_iCS_N;
assign USB_WR_N = avs_dc_chipselect_n_iCS_N? avs_hc_write_n_iWR_N : avs_dc_write_n_iWR_N;
assign USB_RD_N = avs_dc_chipselect_n_iCS_N? avs_hc_read_n_iRD_N : avs_dc_read_n_iRD_N;
assign USB_RST_N = avs_dc_chipselect_n_iCS_N? avs_hc_reset_n_iRST_N: avs_dc_reset_n_iRST_N;
assign avs_hc_irq_n_oINT0_N = USB_INT0;
assign avs_dc_irq_n_oINT0_N = USB_INT1;
endmodule | module ISP1362_IF(
avs_hc_writedata_iDATA,
avs_hc_readdata_oDATA,
avs_hc_address_iADDR,
avs_hc_read_n_iRD_N,
avs_hc_write_n_iWR_N,
avs_hc_chipselect_n_iCS_N,
avs_hc_reset_n_iRST_N,
avs_hc_clk_iCLK,
avs_hc_irq_n_oINT0_N,
avs_dc_writedata_iDATA,
avs_dc_readdata_oDATA,
avs_dc_address_iADDR,
avs_dc_read_n_iRD_N,
avs_dc_write_n_iWR_N,
avs_dc_chipselect_n_iCS_N,
avs_dc_reset_n_iRST_N,
avs_dc_clk_iCLK,
avs_dc_irq_n_oINT0_N,
USB_DATA,
USB_ADDR,
USB_RD_N,
USB_WR_N,
USB_CS_N,
USB_RST_N,
USB_INT0,
USB_INT1
); |
input [15:0] avs_hc_writedata_iDATA;
input avs_hc_address_iADDR;
input avs_hc_read_n_iRD_N;
input avs_hc_write_n_iWR_N;
input avs_hc_chipselect_n_iCS_N;
input avs_hc_reset_n_iRST_N;
input avs_hc_clk_iCLK;
output [15:0] avs_hc_readdata_oDATA;
output avs_hc_irq_n_oINT0_N;
input [15:0] avs_dc_writedata_iDATA;
input avs_dc_address_iADDR;
input avs_dc_read_n_iRD_N;
input avs_dc_write_n_iWR_N;
input avs_dc_chipselect_n_iCS_N;
input avs_dc_reset_n_iRST_N;
input avs_dc_clk_iCLK;
output [15:0] avs_dc_readdata_oDATA;
output avs_dc_irq_n_oINT0_N;
inout [15:0] USB_DATA;
output [1:0] USB_ADDR;
output USB_RD_N;
output USB_WR_N;
output USB_CS_N;
output USB_RST_N;
input USB_INT0;
input USB_INT1;
assign USB_DATA = avs_dc_chipselect_n_iCS_N ? (avs_hc_write_n_iWR_N ? 16'hzzzz : avs_hc_writedata_iDATA) : (avs_dc_write_n_iWR_N ? 16'hzzzz : avs_dc_writedata_iDATA) ;
assign avs_hc_readdata_oDATA = avs_hc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign avs_dc_readdata_oDATA = avs_dc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign USB_ADDR = avs_dc_chipselect_n_iCS_N? {1'b0,avs_hc_address_iADDR} : {1'b1,avs_dc_address_iADDR};
assign USB_CS_N = avs_hc_chipselect_n_iCS_N & avs_dc_chipselect_n_iCS_N;
assign USB_WR_N = avs_dc_chipselect_n_iCS_N? avs_hc_write_n_iWR_N : avs_dc_write_n_iWR_N;
assign USB_RD_N = avs_dc_chipselect_n_iCS_N? avs_hc_read_n_iRD_N : avs_dc_read_n_iRD_N;
assign USB_RST_N = avs_dc_chipselect_n_iCS_N? avs_hc_reset_n_iRST_N: avs_dc_reset_n_iRST_N;
assign avs_hc_irq_n_oINT0_N = USB_INT0;
assign avs_dc_irq_n_oINT0_N = USB_INT1;
endmodule | 0 |
3,953 | data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG/TERASIC_VPG.v | 107,757,225 | TERASIC_VPG.v | v | 231 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG/TERASIC_VPG.v:2: Cannot find include file: .\\vga_time_generator.v\n`include ".\\vga_time_generator.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG,data/full_repos/permissive/107757225/.\\vga_time_generator.v\n data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG,data/full_repos/permissive/107757225/.\\vga_time_generator.v.v\n data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG,data/full_repos/permissive/107757225/.\\vga_time_generator.v.sv\n .\\vga_time_generator.v\n .\\vga_time_generator.v.v\n .\\vga_time_generator.v.sv\n obj_dir/.\\vga_time_generator.v\n obj_dir/.\\vga_time_generator.v.v\n obj_dir/.\\vga_time_generator.v.sv\n%Error: Exiting due to 1 error(s)\n' | 2,232 | module | module TERASIC_VPG(
clk,
reset_n,
s_cs_n,
s_write,
s_writedata,
s_read,
s_readdata,
vga_clk,
vga_hs,
vga_vs,
vga_de,
vga_r,
vga_g,
vga_b
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 24;
parameter READY_LATENCY = 0;
parameter MAX_CHANNEL = 0;
parameter H_DISP = 640;
parameter H_FPORCH = 16;
parameter H_SYNC = 96;
parameter H_BPORCH = 48;
parameter V_DISP = 480;
parameter V_FPORCH = 10;
parameter V_SYNC = 2;
parameter V_BPORCH = 33;
`define STATE_IDLE 0
`define STATE_WAIT_SOP 1
`define STATE_WAIT_EOF 2
`define STATE_STREAMING 3
`define PAT_SCALE 3'd0
`define PAT_RED 3'd1
`define PAT_GREEN 3'd2
`define PAT_BLUE 3'd3
`define PAT_WHITE 3'd4
`define PAT_BLACK 3'd5
input clk;
input reset_n;
input s_cs_n;
input s_write;
input [7:0] s_writedata;
input s_read;
output reg [7:0] s_readdata;
input vga_clk;
output reg vga_hs;
output reg vga_vs;
output reg vga_de;
output reg [7:0] vga_r;
output reg [7:0] vga_g;
output reg [7:0] vga_b;
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
vga_pattern <= `PAT_SCALE;
else if (!s_cs_n & s_write)
vga_pattern <= s_writedata;
else if (!s_cs_n & s_read)
s_readdata <= vga_pattern;
end
wire pix_hs;
wire pix_vs;
wire pix_de;
wire [11:0] pix_x;
wire [11:0] pix_y;
vga_time_generator vga_time_generator_instance(
.clk (vga_clk),
.reset_n (reset_n),
.h_disp (H_DISP),
.h_fporch (H_FPORCH),
.h_sync (H_SYNC),
.h_bporch (H_BPORCH),
.v_disp (V_DISP),
.v_fporch (V_FPORCH),
.v_sync (V_SYNC),
.v_bporch (V_BPORCH),
.hs_polarity(1'b0),
.vs_polarity(1'b0),
.frame_interlaced(1'b0),
.vga_hs (pix_hs),
.vga_vs (pix_vs),
.vga_de (pix_de),
.pixel_x (pix_x),
.pixel_y ( pix_y),
.pixel_i_odd_frame()
);
reg [2:0] vga_pattern;
reg vga_hs_1;
reg vga_vs_1;
reg vga_de_1;
reg [23:0] vga_data_1;
wire [7:0] video_scale;
assign video_scale = pix_x[7:0];
always @ (posedge vga_clk)
begin
vga_hs_1 <= pix_hs;
vga_vs_1 <= pix_vs;
vga_de_1 <= pix_de;
end
always @ (posedge vga_clk)
begin
if (!pix_de)
vga_data_1 <= 24'h000000;
else if (vga_pattern == `PAT_SCALE)
begin
if (pix_y < V_DISP/4)
vga_data_1 <= {8'h00,8'h00,video_scale} ;
else if (pix_y < V_DISP/2)
vga_data_1 <= {8'h00,video_scale,8'h00} ;
else if (pix_y < V_DISP*3/4)
vga_data_1 <= {video_scale,8'h00,8'h00} ;
else
vga_data_1 <= {video_scale,video_scale,video_scale} ;
end
else if (vga_pattern == `PAT_RED)
vga_data_1 <= {8'h00,8'h00,8'hFF} ;
else if (vga_pattern == `PAT_GREEN)
vga_data_1 <= {8'h00,8'hFF,8'h00} ;
else if (vga_pattern == `PAT_BLUE)
vga_data_1 <= {8'hFF,8'h00,8'h00} ;
else if (vga_pattern == `PAT_WHITE)
vga_data_1 <= {8'hFF,8'hFF,8'hFF} ;
else if (vga_pattern == `PAT_BLACK)
vga_data_1 <= {8'h00,8'h00,8'h00} ;
end
always @ (posedge vga_clk)
begin
{vga_b,vga_g,vga_r} <= vga_data_1;
vga_hs <= vga_hs_1;
vga_vs <= vga_vs_1;
vga_de <= vga_de_1;
end
endmodule | module TERASIC_VPG(
clk,
reset_n,
s_cs_n,
s_write,
s_writedata,
s_read,
s_readdata,
vga_clk,
vga_hs,
vga_vs,
vga_de,
vga_r,
vga_g,
vga_b
); |
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 24;
parameter READY_LATENCY = 0;
parameter MAX_CHANNEL = 0;
parameter H_DISP = 640;
parameter H_FPORCH = 16;
parameter H_SYNC = 96;
parameter H_BPORCH = 48;
parameter V_DISP = 480;
parameter V_FPORCH = 10;
parameter V_SYNC = 2;
parameter V_BPORCH = 33;
`define STATE_IDLE 0
`define STATE_WAIT_SOP 1
`define STATE_WAIT_EOF 2
`define STATE_STREAMING 3
`define PAT_SCALE 3'd0
`define PAT_RED 3'd1
`define PAT_GREEN 3'd2
`define PAT_BLUE 3'd3
`define PAT_WHITE 3'd4
`define PAT_BLACK 3'd5
input clk;
input reset_n;
input s_cs_n;
input s_write;
input [7:0] s_writedata;
input s_read;
output reg [7:0] s_readdata;
input vga_clk;
output reg vga_hs;
output reg vga_vs;
output reg vga_de;
output reg [7:0] vga_r;
output reg [7:0] vga_g;
output reg [7:0] vga_b;
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
vga_pattern <= `PAT_SCALE;
else if (!s_cs_n & s_write)
vga_pattern <= s_writedata;
else if (!s_cs_n & s_read)
s_readdata <= vga_pattern;
end
wire pix_hs;
wire pix_vs;
wire pix_de;
wire [11:0] pix_x;
wire [11:0] pix_y;
vga_time_generator vga_time_generator_instance(
.clk (vga_clk),
.reset_n (reset_n),
.h_disp (H_DISP),
.h_fporch (H_FPORCH),
.h_sync (H_SYNC),
.h_bporch (H_BPORCH),
.v_disp (V_DISP),
.v_fporch (V_FPORCH),
.v_sync (V_SYNC),
.v_bporch (V_BPORCH),
.hs_polarity(1'b0),
.vs_polarity(1'b0),
.frame_interlaced(1'b0),
.vga_hs (pix_hs),
.vga_vs (pix_vs),
.vga_de (pix_de),
.pixel_x (pix_x),
.pixel_y ( pix_y),
.pixel_i_odd_frame()
);
reg [2:0] vga_pattern;
reg vga_hs_1;
reg vga_vs_1;
reg vga_de_1;
reg [23:0] vga_data_1;
wire [7:0] video_scale;
assign video_scale = pix_x[7:0];
always @ (posedge vga_clk)
begin
vga_hs_1 <= pix_hs;
vga_vs_1 <= pix_vs;
vga_de_1 <= pix_de;
end
always @ (posedge vga_clk)
begin
if (!pix_de)
vga_data_1 <= 24'h000000;
else if (vga_pattern == `PAT_SCALE)
begin
if (pix_y < V_DISP/4)
vga_data_1 <= {8'h00,8'h00,video_scale} ;
else if (pix_y < V_DISP/2)
vga_data_1 <= {8'h00,video_scale,8'h00} ;
else if (pix_y < V_DISP*3/4)
vga_data_1 <= {video_scale,8'h00,8'h00} ;
else
vga_data_1 <= {video_scale,video_scale,video_scale} ;
end
else if (vga_pattern == `PAT_RED)
vga_data_1 <= {8'h00,8'h00,8'hFF} ;
else if (vga_pattern == `PAT_GREEN)
vga_data_1 <= {8'h00,8'hFF,8'h00} ;
else if (vga_pattern == `PAT_BLUE)
vga_data_1 <= {8'hFF,8'h00,8'h00} ;
else if (vga_pattern == `PAT_WHITE)
vga_data_1 <= {8'hFF,8'hFF,8'hFF} ;
else if (vga_pattern == `PAT_BLACK)
vga_data_1 <= {8'h00,8'h00,8'h00} ;
end
always @ (posedge vga_clk)
begin
{vga_b,vga_g,vga_r} <= vga_data_1;
vga_hs <= vga_hs_1;
vga_vs <= vga_vs_1;
vga_de <= vga_de_1;
end
endmodule | 0 |
3,954 | data/full_repos/permissive/107757225/audio/audio-altera/ip/TERASIC_VPG/vga_time_generator.v | 107,757,225 | vga_time_generator.v | v | 359 | 81 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/6fb22b5c-2a78-4427-baf2-6f6c38a5fc5e.xml | null | 2,233 | module | module vga_time_generator(
clk,
reset_n,
h_disp,
h_fporch,
h_sync,
h_bporch,
v_disp,
v_fporch,
v_sync,
v_bporch,
hs_polarity,
vs_polarity,
frame_interlaced,
vga_hs,
vga_vs,
vga_de,
pixel_i_odd_frame,
pixel_x,
pixel_y
);
input clk;
input reset_n;
input [11:0] h_disp;
input [11:0] h_fporch;
input [11:0] h_sync;
input [11:0] h_bporch;
input [11:0] v_disp;
input [11:0] v_fporch;
input [11:0] v_sync;
input [11:0] v_bporch;
input hs_polarity;
input vs_polarity;
input frame_interlaced;
output reg vga_hs;
output reg vga_vs;
output vga_de;
output reg pixel_i_odd_frame;
output reg [11:0] pixel_x;
output reg [11:0] pixel_y;
reg [11:0] h_total;
reg [11:0] h_total_half;
reg [11:0] h_pixel_start;
reg [11:0] h_pixel_end;
reg h_sync_polarity;
reg vga_h_de;
wire h_de;
wire [11:0] h_valid_pixel_count;
wire h_last_pixel;
assign h_de = (h_counter >= h_pixel_start && h_counter < h_pixel_end)?1'b1:1'b0;
assign h_valid_pixel_count = h_counter - h_pixel_start;
assign h_last_pixel = (h_counter+1 == h_total)?1'b1:1'b0;
reg [11:0]h_counter;
reg [11:0] h_cur_disp;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
h_counter <= 12'h000;
vga_hs <= hs_polarity?1'b1:1'b0;
vga_h_de <= 1'b0;
pixel_x <= 12'hfff;
h_cur_disp <= 0;
end
else if (h_cur_disp != h_disp)
begin
h_cur_disp <= h_disp;
h_total <= h_disp+h_fporch+h_sync+h_bporch;
h_total_half <= (h_disp+h_fporch+h_sync+h_bporch ) >> 1;
h_pixel_start <= h_sync+h_bporch;
h_pixel_end <= h_sync+h_bporch+h_disp;
h_sync_polarity <= hs_polarity;
h_counter <= 12'h000;
vga_hs <= hs_polarity?1'b1:1'b0;
vga_h_de <= 1'b0;
pixel_x <= 12'hfff;
end
else
begin
if (!h_last_pixel)
h_counter <= h_counter+1'b1;
else
h_counter <= 0;
if (h_counter < h_sync)
vga_hs <= h_sync_polarity?1'b1:1'b0;
else
vga_hs <= h_sync_polarity?1'b0:1'b1;
pixel_x <= (h_de)?h_valid_pixel_count:12'hfff;
vga_h_de <= h_de;
end
end
reg vga_v_de;
reg [11:0]v_total;
reg [11:0]v_pixel_start;
reg [11:0]v_pixel_end;
reg v_sync_polarity;
reg v_interlaced;
reg gen_field1_sync;
reg f0_to_f1;
wire [11:0] v_field_total;
wire [11:0] v_field_disp;
wire [11:0] v_valid_line_count;
wire v_de;
assign v_de = (v_counter >= v_pixel_start && v_counter < v_pixel_end)?1'b1:1'b0;
assign v_valid_line_count = v_counter - v_pixel_start;
assign v_field_disp = (frame_interlaced)?(v_disp >> 1):v_disp;
assign v_field_total = v_sync+v_bporch+v_field_disp+v_fporch;
reg [11:0] v_counter;
reg [11:0] v_cur_disp;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
v_counter <= 12'h000;
vga_vs <= vs_polarity?1'b1:1'b0;
vga_v_de <= 1'b0;
pixel_y <= 12'hfff;
pixel_i_odd_frame <= 1'b0;
v_cur_disp <= 0;
end
else if (v_cur_disp != v_disp)
begin
v_cur_disp <= v_disp;
v_pixel_start <= v_sync+v_bporch;
v_pixel_end <= v_sync+v_bporch+v_field_disp;
v_total <= v_field_total;
v_sync_polarity <= vs_polarity;
v_interlaced <= frame_interlaced;
f0_to_f1 <= 1'b0;
v_counter <= 12'h000;
vga_vs <= vs_polarity?1'b1:1'b0;
vga_v_de <= 1'b0;
pixel_y <= 12'hfff;
pixel_i_odd_frame <= 1'b0;
end
else if (h_counter == 0 && f0_to_f1)
f0_to_f1 <= 1'b0;
else if (h_counter == h_total_half && (f0_to_f1 || pixel_i_odd_frame))
begin
if (f0_to_f1)
pixel_i_odd_frame <= 1'b1;
else
begin
if (v_counter < v_sync)
vga_vs <= v_sync_polarity?1'b1:1'b0;
else
vga_vs <= v_sync_polarity?1'b0:1'b1;
end
end
else if (h_counter == 0)
begin
if (v_counter+1 < v_total)
v_counter <= v_counter+1'b1;
else
begin
v_counter <= 0;
if (v_interlaced)
begin
if (pixel_i_odd_frame)
pixel_i_odd_frame <= 1'b0;
else
f0_to_f1 <= 1'b1;
end
end
if (!pixel_i_odd_frame)
begin
if (v_counter < v_sync)
vga_vs <= v_sync_polarity?1'b1:1'b0;
else
vga_vs <= v_sync_polarity?1'b0:1'b1;
end
vga_v_de <= v_de;
if (!v_de)
pixel_y <= 12'hfff;
else if (!v_interlaced)
pixel_y <= v_valid_line_count;
else if (pixel_i_odd_frame)
pixel_y <= (v_valid_line_count << 1) + 1;
else
pixel_y <= v_valid_line_count << 1;
end
end
assign vga_de = vga_h_de & vga_v_de;
endmodule | module vga_time_generator(
clk,
reset_n,
h_disp,
h_fporch,
h_sync,
h_bporch,
v_disp,
v_fporch,
v_sync,
v_bporch,
hs_polarity,
vs_polarity,
frame_interlaced,
vga_hs,
vga_vs,
vga_de,
pixel_i_odd_frame,
pixel_x,
pixel_y
); |
input clk;
input reset_n;
input [11:0] h_disp;
input [11:0] h_fporch;
input [11:0] h_sync;
input [11:0] h_bporch;
input [11:0] v_disp;
input [11:0] v_fporch;
input [11:0] v_sync;
input [11:0] v_bporch;
input hs_polarity;
input vs_polarity;
input frame_interlaced;
output reg vga_hs;
output reg vga_vs;
output vga_de;
output reg pixel_i_odd_frame;
output reg [11:0] pixel_x;
output reg [11:0] pixel_y;
reg [11:0] h_total;
reg [11:0] h_total_half;
reg [11:0] h_pixel_start;
reg [11:0] h_pixel_end;
reg h_sync_polarity;
reg vga_h_de;
wire h_de;
wire [11:0] h_valid_pixel_count;
wire h_last_pixel;
assign h_de = (h_counter >= h_pixel_start && h_counter < h_pixel_end)?1'b1:1'b0;
assign h_valid_pixel_count = h_counter - h_pixel_start;
assign h_last_pixel = (h_counter+1 == h_total)?1'b1:1'b0;
reg [11:0]h_counter;
reg [11:0] h_cur_disp;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
h_counter <= 12'h000;
vga_hs <= hs_polarity?1'b1:1'b0;
vga_h_de <= 1'b0;
pixel_x <= 12'hfff;
h_cur_disp <= 0;
end
else if (h_cur_disp != h_disp)
begin
h_cur_disp <= h_disp;
h_total <= h_disp+h_fporch+h_sync+h_bporch;
h_total_half <= (h_disp+h_fporch+h_sync+h_bporch ) >> 1;
h_pixel_start <= h_sync+h_bporch;
h_pixel_end <= h_sync+h_bporch+h_disp;
h_sync_polarity <= hs_polarity;
h_counter <= 12'h000;
vga_hs <= hs_polarity?1'b1:1'b0;
vga_h_de <= 1'b0;
pixel_x <= 12'hfff;
end
else
begin
if (!h_last_pixel)
h_counter <= h_counter+1'b1;
else
h_counter <= 0;
if (h_counter < h_sync)
vga_hs <= h_sync_polarity?1'b1:1'b0;
else
vga_hs <= h_sync_polarity?1'b0:1'b1;
pixel_x <= (h_de)?h_valid_pixel_count:12'hfff;
vga_h_de <= h_de;
end
end
reg vga_v_de;
reg [11:0]v_total;
reg [11:0]v_pixel_start;
reg [11:0]v_pixel_end;
reg v_sync_polarity;
reg v_interlaced;
reg gen_field1_sync;
reg f0_to_f1;
wire [11:0] v_field_total;
wire [11:0] v_field_disp;
wire [11:0] v_valid_line_count;
wire v_de;
assign v_de = (v_counter >= v_pixel_start && v_counter < v_pixel_end)?1'b1:1'b0;
assign v_valid_line_count = v_counter - v_pixel_start;
assign v_field_disp = (frame_interlaced)?(v_disp >> 1):v_disp;
assign v_field_total = v_sync+v_bporch+v_field_disp+v_fporch;
reg [11:0] v_counter;
reg [11:0] v_cur_disp;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
v_counter <= 12'h000;
vga_vs <= vs_polarity?1'b1:1'b0;
vga_v_de <= 1'b0;
pixel_y <= 12'hfff;
pixel_i_odd_frame <= 1'b0;
v_cur_disp <= 0;
end
else if (v_cur_disp != v_disp)
begin
v_cur_disp <= v_disp;
v_pixel_start <= v_sync+v_bporch;
v_pixel_end <= v_sync+v_bporch+v_field_disp;
v_total <= v_field_total;
v_sync_polarity <= vs_polarity;
v_interlaced <= frame_interlaced;
f0_to_f1 <= 1'b0;
v_counter <= 12'h000;
vga_vs <= vs_polarity?1'b1:1'b0;
vga_v_de <= 1'b0;
pixel_y <= 12'hfff;
pixel_i_odd_frame <= 1'b0;
end
else if (h_counter == 0 && f0_to_f1)
f0_to_f1 <= 1'b0;
else if (h_counter == h_total_half && (f0_to_f1 || pixel_i_odd_frame))
begin
if (f0_to_f1)
pixel_i_odd_frame <= 1'b1;
else
begin
if (v_counter < v_sync)
vga_vs <= v_sync_polarity?1'b1:1'b0;
else
vga_vs <= v_sync_polarity?1'b0:1'b1;
end
end
else if (h_counter == 0)
begin
if (v_counter+1 < v_total)
v_counter <= v_counter+1'b1;
else
begin
v_counter <= 0;
if (v_interlaced)
begin
if (pixel_i_odd_frame)
pixel_i_odd_frame <= 1'b0;
else
f0_to_f1 <= 1'b1;
end
end
if (!pixel_i_odd_frame)
begin
if (v_counter < v_sync)
vga_vs <= v_sync_polarity?1'b1:1'b0;
else
vga_vs <= v_sync_polarity?1'b0:1'b1;
end
vga_v_de <= v_de;
if (!v_de)
pixel_y <= 12'hfff;
else if (!v_interlaced)
pixel_y <= v_valid_line_count;
else if (pixel_i_odd_frame)
pixel_y <= (v_valid_line_count << 1) + 1;
else
pixel_y <= v_valid_line_count << 1;
end
end
assign vga_de = vga_h_de & vga_v_de;
endmodule | 0 |
3,955 | data/full_repos/permissive/107757225/audio/audio-uw/Altera_UP_I2C_AV_Auto_Initialize.v | 107,757,225 | Altera_UP_I2C_AV_Auto_Initialize.v | v | 329 | 81 | [] | [] | [] | [(8, 327)] | null | data/verilator_xmls/70eeaaf4-0735-49de-bcf9-127787ad581d.xml | null | 2,239 | module | module Altera_UP_I2C_AV_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
);
parameter MIN_ROM_ADDRESS = 6'h00;
parameter MAX_ROM_ADDRESS = 6'h32;
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 3'h0,
AUTO_STATE_1_SEND_START_BIT = 3'h1,
AUTO_STATE_2_TRANSFER_BYTE_1 = 3'h2,
AUTO_STATE_3_TRANSFER_BYTE_2 = 3'h3,
AUTO_STATE_4_WAIT = 3'h4,
AUTO_STATE_5_SEND_STOP_BIT = 3'h5,
AUTO_STATE_6_INCREASE_COUNTER = 3'h6,
AUTO_STATE_7_DONE = 3'h7;
wire change_state;
wire finished_auto_init;
reg [5:0] rom_address_counter;
reg [25:0] rom_data;
reg [2:0] ns_i2c_auto_init;
reg [2:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_DONE;
else if (rom_data[25] == 1'b1)
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1;
end
AUTO_STATE_3_TRANSFER_BYTE_2:
begin
if ((change_state == 1'b1) && (rom_data[24] == 1'b1))
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
else if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
end
AUTO_STATE_4_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
end
AUTO_STATE_5_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
end
AUTO_STATE_6_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_7_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_7_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= rom_data[23:16];
else if (s_i2c_auto_init == AUTO_STATE_0_CHECK_STATUS)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_1)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_2)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_2)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_5_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 6'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_7_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {10'h334, 7'h0, AUD_LINE_IN_LC};
1 : rom_data <= {10'h334, 7'h1, AUD_LINE_IN_RC};
2 : rom_data <= {10'h334, 7'h2, AUD_LINE_OUT_LC};
3 : rom_data <= {10'h334, 7'h3, AUD_LINE_OUT_RC};
4 : rom_data <= {10'h334, 7'h4, AUD_ADC_PATH};
5 : rom_data <= {10'h334, 7'h5, AUD_DAC_PATH};
6 : rom_data <= {10'h334, 7'h6, AUD_POWER};
7 : rom_data <= {10'h334, 7'h7, AUD_DATA_FORMAT};
8 : rom_data <= {10'h334, 7'h8, AUD_SAMPLE_CTRL};
9 : rom_data <= {10'h334, 7'h9, AUD_SET_ACTIVE};
10 : rom_data <= 26'h3401500;
11 : rom_data <= 26'h3401741;
12 : rom_data <= 26'h3403a16;
13 : rom_data <= 26'h3405004;
14 : rom_data <= 26'h340c305;
15 : rom_data <= 26'h340c480;
16 : rom_data <= 26'h3400e80;
17 : rom_data <= 26'h3405020;
18 : rom_data <= 26'h3405218;
19 : rom_data <= 26'h34058ed;
20 : rom_data <= 26'h34077c5;
21 : rom_data <= 26'h3407c93;
22 : rom_data <= 26'h3407d00;
23 : rom_data <= 26'h340d048;
24 : rom_data <= 26'h340d5a0;
25 : rom_data <= 26'h340d7ea;
26 : rom_data <= 26'h340e43e;
27 : rom_data <= 26'h340ea0f;
28 : rom_data <= 26'h3403112;
29 : rom_data <= 26'h3403281;
30 : rom_data <= 26'h3403384;
31 : rom_data <= 26'h34037A0;
32 : rom_data <= 26'h340e580;
33 : rom_data <= 26'h340e603;
34 : rom_data <= 26'h340e785;
35 : rom_data <= 26'h3405000;
36 : rom_data <= 26'h3405100;
37 : rom_data <= 26'h3400070;
38 : rom_data <= 26'h3401010;
39 : rom_data <= 26'h3400482;
40 : rom_data <= 26'h3400860;
41 : rom_data <= 26'h3400a18;
42 : rom_data <= 26'h3401100;
43 : rom_data <= 26'h3402b00;
44 : rom_data <= 26'h3402c8c;
45 : rom_data <= 26'h3402df2;
46 : rom_data <= 26'h3402eee;
47 : rom_data <= 26'h3402ff4;
48 : rom_data <= 26'h34030d2;
49 : rom_data <= 26'h3400e05;
default : rom_data <= 26'h1000000;
endcase
end
endmodule | module Altera_UP_I2C_AV_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
); |
parameter MIN_ROM_ADDRESS = 6'h00;
parameter MAX_ROM_ADDRESS = 6'h32;
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 3'h0,
AUTO_STATE_1_SEND_START_BIT = 3'h1,
AUTO_STATE_2_TRANSFER_BYTE_1 = 3'h2,
AUTO_STATE_3_TRANSFER_BYTE_2 = 3'h3,
AUTO_STATE_4_WAIT = 3'h4,
AUTO_STATE_5_SEND_STOP_BIT = 3'h5,
AUTO_STATE_6_INCREASE_COUNTER = 3'h6,
AUTO_STATE_7_DONE = 3'h7;
wire change_state;
wire finished_auto_init;
reg [5:0] rom_address_counter;
reg [25:0] rom_data;
reg [2:0] ns_i2c_auto_init;
reg [2:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_DONE;
else if (rom_data[25] == 1'b1)
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1;
end
AUTO_STATE_3_TRANSFER_BYTE_2:
begin
if ((change_state == 1'b1) && (rom_data[24] == 1'b1))
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
else if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2;
end
AUTO_STATE_4_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
end
AUTO_STATE_5_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
end
AUTO_STATE_6_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_7_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_7_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= rom_data[23:16];
else if (s_i2c_auto_init == AUTO_STATE_0_CHECK_STATUS)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_1)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_2)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_2)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_5_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 6'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_7_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {10'h334, 7'h0, AUD_LINE_IN_LC};
1 : rom_data <= {10'h334, 7'h1, AUD_LINE_IN_RC};
2 : rom_data <= {10'h334, 7'h2, AUD_LINE_OUT_LC};
3 : rom_data <= {10'h334, 7'h3, AUD_LINE_OUT_RC};
4 : rom_data <= {10'h334, 7'h4, AUD_ADC_PATH};
5 : rom_data <= {10'h334, 7'h5, AUD_DAC_PATH};
6 : rom_data <= {10'h334, 7'h6, AUD_POWER};
7 : rom_data <= {10'h334, 7'h7, AUD_DATA_FORMAT};
8 : rom_data <= {10'h334, 7'h8, AUD_SAMPLE_CTRL};
9 : rom_data <= {10'h334, 7'h9, AUD_SET_ACTIVE};
10 : rom_data <= 26'h3401500;
11 : rom_data <= 26'h3401741;
12 : rom_data <= 26'h3403a16;
13 : rom_data <= 26'h3405004;
14 : rom_data <= 26'h340c305;
15 : rom_data <= 26'h340c480;
16 : rom_data <= 26'h3400e80;
17 : rom_data <= 26'h3405020;
18 : rom_data <= 26'h3405218;
19 : rom_data <= 26'h34058ed;
20 : rom_data <= 26'h34077c5;
21 : rom_data <= 26'h3407c93;
22 : rom_data <= 26'h3407d00;
23 : rom_data <= 26'h340d048;
24 : rom_data <= 26'h340d5a0;
25 : rom_data <= 26'h340d7ea;
26 : rom_data <= 26'h340e43e;
27 : rom_data <= 26'h340ea0f;
28 : rom_data <= 26'h3403112;
29 : rom_data <= 26'h3403281;
30 : rom_data <= 26'h3403384;
31 : rom_data <= 26'h34037A0;
32 : rom_data <= 26'h340e580;
33 : rom_data <= 26'h340e603;
34 : rom_data <= 26'h340e785;
35 : rom_data <= 26'h3405000;
36 : rom_data <= 26'h3405100;
37 : rom_data <= 26'h3400070;
38 : rom_data <= 26'h3401010;
39 : rom_data <= 26'h3400482;
40 : rom_data <= 26'h3400860;
41 : rom_data <= 26'h3400a18;
42 : rom_data <= 26'h3401100;
43 : rom_data <= 26'h3402b00;
44 : rom_data <= 26'h3402c8c;
45 : rom_data <= 26'h3402df2;
46 : rom_data <= 26'h3402eee;
47 : rom_data <= 26'h3402ff4;
48 : rom_data <= 26'h34030d2;
49 : rom_data <= 26'h3400e05;
default : rom_data <= 26'h1000000;
endcase
end
endmodule | 0 |
3,956 | data/full_repos/permissive/107757225/audio/audio-uw/Altera_UP_I2C_DC_Auto_Initialize.v | 107,757,225 | Altera_UP_I2C_DC_Auto_Initialize.v | v | 328 | 81 | [] | [] | [] | [(8, 326)] | null | data/verilator_xmls/f20e0831-44bb-4cc7-8a80-0a1259bdb87c.xml | null | 2,240 | module | module Altera_UP_I2C_DC_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
);
parameter DC_ROW_START = 16'h000C;
parameter DC_COLUMN_START = 16'h001E;
parameter DC_ROW_WIDTH = 16'h0400;
parameter DC_COLUMN_WIDTH = 16'h0500;
parameter DC_H_BLANK_B = 16'h018C;
parameter DC_V_BLANK_B = 16'h0032;
parameter DC_H_BLANK_A = 16'h00C6;
parameter DC_V_BLANK_A = 16'h0019;
parameter DC_SHUTTER_WIDTH = 16'h0432;
parameter DC_ROW_SPEED = 16'h0011;
parameter DC_EXTRA_DELAY = 16'h0000;
parameter DC_SHUTTER_DELAY = 16'h0000;
parameter DC_RESET = 16'h0008;
parameter DC_FRAME_VALID = 16'h0000;
parameter DC_READ_MODE_B = 16'h0200;
parameter DC_READ_MODE_A = 16'h040C;
parameter DC_DARK_COL_ROW = 16'h0129;
parameter DC_FLASH = 16'h0608;
parameter DC_GREEN_GAIN_1 = 16'h0020;
parameter DC_BLUE_GAIN = 16'h0020;
parameter DC_RED_GAIN = 16'h0020;
parameter DC_GREEN_GAIN_2 = 16'h0020;
parameter DC_GLOBAL_GAIN = 16'h0020;
parameter DC_CONTEXT_CTRL = 16'h000B;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 4'h0,
AUTO_STATE_1_SEND_START_BIT = 4'h1,
AUTO_STATE_2_TRANSFER_BYTE_0 = 4'h2,
AUTO_STATE_3_TRANSFER_BYTE_1 = 4'h3,
AUTO_STATE_4_TRANSFER_BYTE_2 = 4'h4,
AUTO_STATE_5_WAIT = 4'h5,
AUTO_STATE_6_SEND_STOP_BIT = 4'h6,
AUTO_STATE_7_INCREASE_COUNTER = 4'h7,
AUTO_STATE_8_DONE = 4'h8;
localparam MIN_ROM_ADDRESS = 5'h00;
localparam MAX_ROM_ADDRESS = 5'h18;
wire change_state;
wire finished_auto_init;
reg [4:0] rom_address_counter;
reg [25:0] rom_data;
reg [3:0] ns_i2c_auto_init;
reg [3:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_8_DONE;
else if (rom_data[25] == 1'b1)
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_0:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
end
AUTO_STATE_3_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_4_TRANSFER_BYTE_2;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_4_TRANSFER_BYTE_2:
begin
if ((change_state == 1'b1) && (rom_data[24] == 1'b1))
ns_i2c_auto_init = AUTO_STATE_5_WAIT;
else if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_4_TRANSFER_BYTE_2;
end
AUTO_STATE_5_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_6_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_5_WAIT;
end
AUTO_STATE_6_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_6_SEND_STOP_BIT;
end
AUTO_STATE_7_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_8_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_8_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= 8'hBA;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
data_out <= rom_data[23:16];
else if (s_i2c_auto_init == AUTO_STATE_0_CHECK_STATUS)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_4_TRANSFER_BYTE_2)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_4_TRANSFER_BYTE_2)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_6_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_7_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_7_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 5'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_8_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {10'h201, DC_ROW_START};
1 : rom_data <= {10'h002, DC_COLUMN_START};
2 : rom_data <= {10'h003, DC_ROW_WIDTH};
3 : rom_data <= {10'h004, DC_COLUMN_WIDTH};
4 : rom_data <= {10'h005, DC_H_BLANK_B};
5 : rom_data <= {10'h006, DC_V_BLANK_B};
6 : rom_data <= {10'h007, DC_H_BLANK_A};
7 : rom_data <= {10'h008, DC_V_BLANK_A};
8 : rom_data <= {10'h009, DC_SHUTTER_WIDTH};
9 : rom_data <= {10'h00A, DC_ROW_SPEED};
10 : rom_data <= {10'h00B, DC_EXTRA_DELAY};
11 : rom_data <= {10'h00C, DC_SHUTTER_DELAY};
12 : rom_data <= {10'h10D, DC_RESET};
13 : rom_data <= {10'h21F, DC_FRAME_VALID};
14 : rom_data <= {10'h020, DC_READ_MODE_B};
15 : rom_data <= {10'h021, DC_READ_MODE_A};
16 : rom_data <= {10'h022, DC_DARK_COL_ROW};
17 : rom_data <= {10'h123, DC_FLASH};
18 : rom_data <= {10'h22B, DC_GREEN_GAIN_1};
19 : rom_data <= {10'h02C, DC_BLUE_GAIN};
20 : rom_data <= {10'h02D, DC_RED_GAIN};
21 : rom_data <= {10'h02E, DC_GREEN_GAIN_2};
22 : rom_data <= {10'h12F, DC_GLOBAL_GAIN};
23 : rom_data <= {10'h3C8, DC_CONTEXT_CTRL};
default : rom_data <= 26'h1000000;
endcase
end
endmodule | module Altera_UP_I2C_DC_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
); |
parameter DC_ROW_START = 16'h000C;
parameter DC_COLUMN_START = 16'h001E;
parameter DC_ROW_WIDTH = 16'h0400;
parameter DC_COLUMN_WIDTH = 16'h0500;
parameter DC_H_BLANK_B = 16'h018C;
parameter DC_V_BLANK_B = 16'h0032;
parameter DC_H_BLANK_A = 16'h00C6;
parameter DC_V_BLANK_A = 16'h0019;
parameter DC_SHUTTER_WIDTH = 16'h0432;
parameter DC_ROW_SPEED = 16'h0011;
parameter DC_EXTRA_DELAY = 16'h0000;
parameter DC_SHUTTER_DELAY = 16'h0000;
parameter DC_RESET = 16'h0008;
parameter DC_FRAME_VALID = 16'h0000;
parameter DC_READ_MODE_B = 16'h0200;
parameter DC_READ_MODE_A = 16'h040C;
parameter DC_DARK_COL_ROW = 16'h0129;
parameter DC_FLASH = 16'h0608;
parameter DC_GREEN_GAIN_1 = 16'h0020;
parameter DC_BLUE_GAIN = 16'h0020;
parameter DC_RED_GAIN = 16'h0020;
parameter DC_GREEN_GAIN_2 = 16'h0020;
parameter DC_GLOBAL_GAIN = 16'h0020;
parameter DC_CONTEXT_CTRL = 16'h000B;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 4'h0,
AUTO_STATE_1_SEND_START_BIT = 4'h1,
AUTO_STATE_2_TRANSFER_BYTE_0 = 4'h2,
AUTO_STATE_3_TRANSFER_BYTE_1 = 4'h3,
AUTO_STATE_4_TRANSFER_BYTE_2 = 4'h4,
AUTO_STATE_5_WAIT = 4'h5,
AUTO_STATE_6_SEND_STOP_BIT = 4'h6,
AUTO_STATE_7_INCREASE_COUNTER = 4'h7,
AUTO_STATE_8_DONE = 4'h8;
localparam MIN_ROM_ADDRESS = 5'h00;
localparam MAX_ROM_ADDRESS = 5'h18;
wire change_state;
wire finished_auto_init;
reg [4:0] rom_address_counter;
reg [25:0] rom_data;
reg [3:0] ns_i2c_auto_init;
reg [3:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_8_DONE;
else if (rom_data[25] == 1'b1)
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_0:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
end
AUTO_STATE_3_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_4_TRANSFER_BYTE_2;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_4_TRANSFER_BYTE_2:
begin
if ((change_state == 1'b1) && (rom_data[24] == 1'b1))
ns_i2c_auto_init = AUTO_STATE_5_WAIT;
else if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_4_TRANSFER_BYTE_2;
end
AUTO_STATE_5_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_6_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_5_WAIT;
end
AUTO_STATE_6_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_6_SEND_STOP_BIT;
end
AUTO_STATE_7_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_8_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_8_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= 8'hBA;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
data_out <= rom_data[23:16];
else if (s_i2c_auto_init == AUTO_STATE_0_CHECK_STATUS)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_out <= rom_data[15: 8];
else if (s_i2c_auto_init == AUTO_STATE_4_TRANSFER_BYTE_2)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_4_TRANSFER_BYTE_2)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_6_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_7_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_7_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 5'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_8_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {10'h201, DC_ROW_START};
1 : rom_data <= {10'h002, DC_COLUMN_START};
2 : rom_data <= {10'h003, DC_ROW_WIDTH};
3 : rom_data <= {10'h004, DC_COLUMN_WIDTH};
4 : rom_data <= {10'h005, DC_H_BLANK_B};
5 : rom_data <= {10'h006, DC_V_BLANK_B};
6 : rom_data <= {10'h007, DC_H_BLANK_A};
7 : rom_data <= {10'h008, DC_V_BLANK_A};
8 : rom_data <= {10'h009, DC_SHUTTER_WIDTH};
9 : rom_data <= {10'h00A, DC_ROW_SPEED};
10 : rom_data <= {10'h00B, DC_EXTRA_DELAY};
11 : rom_data <= {10'h00C, DC_SHUTTER_DELAY};
12 : rom_data <= {10'h10D, DC_RESET};
13 : rom_data <= {10'h21F, DC_FRAME_VALID};
14 : rom_data <= {10'h020, DC_READ_MODE_B};
15 : rom_data <= {10'h021, DC_READ_MODE_A};
16 : rom_data <= {10'h022, DC_DARK_COL_ROW};
17 : rom_data <= {10'h123, DC_FLASH};
18 : rom_data <= {10'h22B, DC_GREEN_GAIN_1};
19 : rom_data <= {10'h02C, DC_BLUE_GAIN};
20 : rom_data <= {10'h02D, DC_RED_GAIN};
21 : rom_data <= {10'h02E, DC_GREEN_GAIN_2};
22 : rom_data <= {10'h12F, DC_GLOBAL_GAIN};
23 : rom_data <= {10'h3C8, DC_CONTEXT_CTRL};
default : rom_data <= 26'h1000000;
endcase
end
endmodule | 0 |
3,957 | data/full_repos/permissive/107757225/audio/audio-uw/Altera_UP_I2C_LCM_Auto_Initialize.v | 107,757,225 | Altera_UP_I2C_LCM_Auto_Initialize.v | v | 310 | 81 | [] | [] | [] | [(8, 308)] | null | data/verilator_xmls/1eecdc9e-ba48-4fff-8b6e-0f74b14ee086.xml | null | 2,241 | module | module Altera_UP_I2C_LCM_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
data_size,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
);
parameter LCM_INPUT_FORMAT_UB = 8'h00;
parameter LCM_INPUT_FORMAT_LB = 8'h01;
parameter LCM_POWER = 8'h3F;
parameter LCM_DIRECTION_AND_PHASE = 8'h17;
parameter LCM_HORIZONTAL_START_POSITION = 8'h18;
parameter LCM_VERTICAL_START_POSITION = 8'h08;
parameter LCM_ENB_NEGATIVE_POSITION = 8'h00;
parameter LCM_GAIN_OF_CONTRAST = 8'h20;
parameter LCM_R_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_B_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_OFFSET_OF_BRIGHTNESS = 8'h10;
parameter LCM_VCOM_HIGH_LEVEL = 8'h3F;
parameter LCM_VCOM_LOW_LEVEL = 8'h3F;
parameter LCM_PCD_HIGH_LEVEL = 8'h2F;
parameter LCM_PCD_LOW_LEVEL = 8'h2F;
parameter LCM_GAMMA_CORRECTION_0 = 8'h98;
parameter LCM_GAMMA_CORRECTION_1 = 8'h9A;
parameter LCM_GAMMA_CORRECTION_2 = 8'hA9;
parameter LCM_GAMMA_CORRECTION_3 = 8'h99;
parameter LCM_GAMMA_CORRECTION_4 = 8'h08;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg [2:0] data_size;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 3'h0,
AUTO_STATE_1_SEND_START_BIT = 3'h1,
AUTO_STATE_2_TRANSFER_BYTE_0 = 3'h2,
AUTO_STATE_3_TRANSFER_BYTE_1 = 3'h3,
AUTO_STATE_4_WAIT = 3'h4,
AUTO_STATE_5_SEND_STOP_BIT = 3'h5,
AUTO_STATE_6_INCREASE_COUNTER = 3'h6,
AUTO_STATE_7_DONE = 3'h7;
localparam MIN_ROM_ADDRESS = 5'h00;
localparam MAX_ROM_ADDRESS = 5'h14;
wire change_state;
wire finished_auto_init;
reg [4:0] rom_address_counter;
reg [13:0] rom_data;
reg [2:0] ns_i2c_auto_init;
reg [2:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_DONE;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_0:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
end
AUTO_STATE_3_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_4_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
end
AUTO_STATE_5_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
end
AUTO_STATE_6_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_7_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_7_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= {1'b0, rom_data[13: 8], 1'b0};
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_size <= 3'h0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_size <= 3'h6;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_size <= 3'h7;
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_5_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 5'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_7_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {6'h02, LCM_INPUT_FORMAT_UB};
1 : rom_data <= {6'h03, LCM_INPUT_FORMAT_LB};
2 : rom_data <= {6'h04, LCM_POWER};
3 : rom_data <= {6'h05, LCM_DIRECTION_AND_PHASE};
4 : rom_data <= {6'h06, LCM_HORIZONTAL_START_POSITION};
5 : rom_data <= {6'h07, LCM_VERTICAL_START_POSITION};
6 : rom_data <= {6'h08, LCM_ENB_NEGATIVE_POSITION};
7 : rom_data <= {6'h09, LCM_GAIN_OF_CONTRAST};
8 : rom_data <= {6'h0A, LCM_R_GAIN_OF_SUB_CONTRAST};
9 : rom_data <= {6'h0B, LCM_B_GAIN_OF_SUB_CONTRAST};
10 : rom_data <= {6'h0C, LCM_OFFSET_OF_BRIGHTNESS};
11 : rom_data <= {6'h10, LCM_VCOM_HIGH_LEVEL};
12 : rom_data <= {6'h11, LCM_VCOM_LOW_LEVEL};
13 : rom_data <= {6'h12, LCM_PCD_HIGH_LEVEL};
14 : rom_data <= {6'h13, LCM_PCD_LOW_LEVEL};
15 : rom_data <= {6'h14, LCM_GAMMA_CORRECTION_0};
16 : rom_data <= {6'h15, LCM_GAMMA_CORRECTION_1};
17 : rom_data <= {6'h16, LCM_GAMMA_CORRECTION_2};
18 : rom_data <= {6'h17, LCM_GAMMA_CORRECTION_3};
19 : rom_data <= {6'h18, LCM_GAMMA_CORRECTION_4};
default : rom_data <= 14'h0000;
endcase
end
endmodule | module Altera_UP_I2C_LCM_Auto_Initialize (
clk,
reset,
clear_error,
ack,
transfer_complete,
data_out,
data_size,
transfer_data,
send_start_bit,
send_stop_bit,
auto_init_complete,
auto_init_error
); |
parameter LCM_INPUT_FORMAT_UB = 8'h00;
parameter LCM_INPUT_FORMAT_LB = 8'h01;
parameter LCM_POWER = 8'h3F;
parameter LCM_DIRECTION_AND_PHASE = 8'h17;
parameter LCM_HORIZONTAL_START_POSITION = 8'h18;
parameter LCM_VERTICAL_START_POSITION = 8'h08;
parameter LCM_ENB_NEGATIVE_POSITION = 8'h00;
parameter LCM_GAIN_OF_CONTRAST = 8'h20;
parameter LCM_R_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_B_GAIN_OF_SUB_CONTRAST = 8'h20;
parameter LCM_OFFSET_OF_BRIGHTNESS = 8'h10;
parameter LCM_VCOM_HIGH_LEVEL = 8'h3F;
parameter LCM_VCOM_LOW_LEVEL = 8'h3F;
parameter LCM_PCD_HIGH_LEVEL = 8'h2F;
parameter LCM_PCD_LOW_LEVEL = 8'h2F;
parameter LCM_GAMMA_CORRECTION_0 = 8'h98;
parameter LCM_GAMMA_CORRECTION_1 = 8'h9A;
parameter LCM_GAMMA_CORRECTION_2 = 8'hA9;
parameter LCM_GAMMA_CORRECTION_3 = 8'h99;
parameter LCM_GAMMA_CORRECTION_4 = 8'h08;
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
output reg [7:0] data_out;
output reg [2:0] data_size;
output reg transfer_data;
output reg send_start_bit;
output reg send_stop_bit;
output auto_init_complete;
output reg auto_init_error;
localparam AUTO_STATE_0_CHECK_STATUS = 3'h0,
AUTO_STATE_1_SEND_START_BIT = 3'h1,
AUTO_STATE_2_TRANSFER_BYTE_0 = 3'h2,
AUTO_STATE_3_TRANSFER_BYTE_1 = 3'h3,
AUTO_STATE_4_WAIT = 3'h4,
AUTO_STATE_5_SEND_STOP_BIT = 3'h5,
AUTO_STATE_6_INCREASE_COUNTER = 3'h6,
AUTO_STATE_7_DONE = 3'h7;
localparam MIN_ROM_ADDRESS = 5'h00;
localparam MAX_ROM_ADDRESS = 5'h14;
wire change_state;
wire finished_auto_init;
reg [4:0] rom_address_counter;
reg [13:0] rom_data;
reg [2:0] ns_i2c_auto_init;
reg [2:0] s_i2c_auto_init;
always @(posedge clk)
begin
if (reset == 1'b1)
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end
always @(*)
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
case (s_i2c_auto_init)
AUTO_STATE_0_CHECK_STATUS:
begin
if (finished_auto_init == 1'b1)
ns_i2c_auto_init = AUTO_STATE_7_DONE;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_1_SEND_START_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
else
ns_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT;
end
AUTO_STATE_2_TRANSFER_BYTE_0:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
else
ns_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_0;
end
AUTO_STATE_3_TRANSFER_BYTE_1:
begin
if (change_state == 1'b1)
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
else
ns_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_1;
end
AUTO_STATE_4_WAIT:
begin
if (transfer_complete == 1'b0)
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init = AUTO_STATE_4_WAIT;
end
AUTO_STATE_5_SEND_STOP_BIT:
begin
if (transfer_complete == 1'b1)
ns_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT;
end
AUTO_STATE_6_INCREASE_COUNTER:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
AUTO_STATE_7_DONE:
begin
ns_i2c_auto_init = AUTO_STATE_7_DONE;
end
default:
begin
ns_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS;
end
endcase
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out <= 8'h00;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_out <= {1'b0, rom_data[13: 8], 1'b0};
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_out <= rom_data[ 7: 0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_size <= 3'h0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
data_size <= 3'h6;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
data_size <= 3'h7;
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_data <= 1'b0;
else if (transfer_complete == 1'b1)
transfer_data <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_2_TRANSFER_BYTE_0)
transfer_data <= 1'b1;
else if (s_i2c_auto_init == AUTO_STATE_3_TRANSFER_BYTE_1)
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_start_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_start_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_1_SEND_START_BIT)
send_start_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
send_stop_bit <= 1'b0;
else if (transfer_complete == 1'b1)
send_stop_bit <= 1'b0;
else if (s_i2c_auto_init == AUTO_STATE_5_SEND_STOP_BIT)
send_stop_bit <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
auto_init_error <= 1'b0;
else if (clear_error == 1'b1)
auto_init_error <= 1'b0;
else if ((s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER) & ack)
auto_init_error <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
rom_address_counter <= MIN_ROM_ADDRESS;
else if (s_i2c_auto_init == AUTO_STATE_6_INCREASE_COUNTER)
rom_address_counter <= rom_address_counter + 5'h01;
end
assign auto_init_complete = (s_i2c_auto_init == AUTO_STATE_7_DONE);
assign change_state = transfer_complete & transfer_data;
assign finished_auto_init = (rom_address_counter == MAX_ROM_ADDRESS);
always @(*)
begin
case (rom_address_counter)
0 : rom_data <= {6'h02, LCM_INPUT_FORMAT_UB};
1 : rom_data <= {6'h03, LCM_INPUT_FORMAT_LB};
2 : rom_data <= {6'h04, LCM_POWER};
3 : rom_data <= {6'h05, LCM_DIRECTION_AND_PHASE};
4 : rom_data <= {6'h06, LCM_HORIZONTAL_START_POSITION};
5 : rom_data <= {6'h07, LCM_VERTICAL_START_POSITION};
6 : rom_data <= {6'h08, LCM_ENB_NEGATIVE_POSITION};
7 : rom_data <= {6'h09, LCM_GAIN_OF_CONTRAST};
8 : rom_data <= {6'h0A, LCM_R_GAIN_OF_SUB_CONTRAST};
9 : rom_data <= {6'h0B, LCM_B_GAIN_OF_SUB_CONTRAST};
10 : rom_data <= {6'h0C, LCM_OFFSET_OF_BRIGHTNESS};
11 : rom_data <= {6'h10, LCM_VCOM_HIGH_LEVEL};
12 : rom_data <= {6'h11, LCM_VCOM_LOW_LEVEL};
13 : rom_data <= {6'h12, LCM_PCD_HIGH_LEVEL};
14 : rom_data <= {6'h13, LCM_PCD_LOW_LEVEL};
15 : rom_data <= {6'h14, LCM_GAMMA_CORRECTION_0};
16 : rom_data <= {6'h15, LCM_GAMMA_CORRECTION_1};
17 : rom_data <= {6'h16, LCM_GAMMA_CORRECTION_2};
18 : rom_data <= {6'h17, LCM_GAMMA_CORRECTION_3};
19 : rom_data <= {6'h18, LCM_GAMMA_CORRECTION_4};
default : rom_data <= 14'h0000;
endcase
end
endmodule | 0 |
3,958 | data/full_repos/permissive/107757225/audio/audio-uw/Altera_UP_Slow_Clock_Generator.v | 107,757,225 | Altera_UP_Slow_Clock_Generator.v | v | 154 | 81 | [] | [] | [] | [(13, 152)] | null | data/verilator_xmls/100845b9-c5d4-465d-9e7c-f6359a7a5f25.xml | null | 2,242 | module | module Altera_UP_Slow_Clock_Generator (
clk,
reset,
enable_clk,
new_clk,
rising_edge,
falling_edge,
middle_of_high_level,
middle_of_low_level
);
parameter COUNTER_BITS = 10;
parameter COUNTER_INC = 10'h001;
input clk;
input reset;
input enable_clk;
output reg new_clk;
output reg rising_edge;
output reg falling_edge;
output reg middle_of_high_level;
output reg middle_of_low_level;
reg [COUNTER_BITS:1] clk_counter;
always @(posedge clk)
begin
if (reset == 1'b1)
clk_counter <= {COUNTER_BITS{1'b0}};
else if (enable_clk == 1'b1)
clk_counter <= clk_counter + COUNTER_INC;
end
always @(posedge clk)
begin
if (reset == 1'b1)
new_clk <= 1'b0;
else
new_clk <= clk_counter[COUNTER_BITS];
end
always @(posedge clk)
begin
if (reset == 1'b1)
rising_edge <= 1'b0;
else
rising_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & ~new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
falling_edge <= 1'b0;
else
falling_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_high_level <= 1'b0;
else
middle_of_high_level <=
clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_low_level <= 1'b0;
else
middle_of_low_level <=
~clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
endmodule | module Altera_UP_Slow_Clock_Generator (
clk,
reset,
enable_clk,
new_clk,
rising_edge,
falling_edge,
middle_of_high_level,
middle_of_low_level
); |
parameter COUNTER_BITS = 10;
parameter COUNTER_INC = 10'h001;
input clk;
input reset;
input enable_clk;
output reg new_clk;
output reg rising_edge;
output reg falling_edge;
output reg middle_of_high_level;
output reg middle_of_low_level;
reg [COUNTER_BITS:1] clk_counter;
always @(posedge clk)
begin
if (reset == 1'b1)
clk_counter <= {COUNTER_BITS{1'b0}};
else if (enable_clk == 1'b1)
clk_counter <= clk_counter + COUNTER_INC;
end
always @(posedge clk)
begin
if (reset == 1'b1)
new_clk <= 1'b0;
else
new_clk <= clk_counter[COUNTER_BITS];
end
always @(posedge clk)
begin
if (reset == 1'b1)
rising_edge <= 1'b0;
else
rising_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & ~new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
falling_edge <= 1'b0;
else
falling_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_high_level <= 1'b0;
else
middle_of_high_level <=
clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_low_level <= 1'b0;
else
middle_of_low_level <=
~clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
endmodule | 0 |
3,959 | data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv | 107,757,225 | audio_driver.sv | sv | 152 | 189 | [] | [] | [] | [(48, 149)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:95: Unsupported: Ignoring delay on this delayed statement.\n #(40690); \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:119: Cannot find file containing module: \'audio_and_video_config\'\n audio_and_video_config cfg(\n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config\n data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config.v\n data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config.sv\n audio_and_video_config\n audio_and_video_config.v\n audio_and_video_config.sv\n obj_dir/audio_and_video_config\n obj_dir/audio_and_video_config.v\n obj_dir/audio_and_video_config.sv\n%Error: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:129: Cannot find file containing module: \'audio_codec\'\n audio_codec codec(\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,246 | module | module audio_driver (CLOCK_50, reset, dac_left, dac_right, adc_left, adc_right, advance, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);
input CLOCK_50;
input reset;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
output AUD_XCK;
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
input AUD_ADCDAT;
output AUD_DACDAT;
input [23:0] dac_left, dac_right;
output [23:0] adc_left, adc_right;
output advance;
wire read_ready, write_ready;
reg write;
wire read;
reg w1, w2;
assign read = write;
assign advance = write;
always @(posedge CLOCK_50) begin
if (reset) begin
w1 <= 0;
w2 <= 0;
write <= 0;
end else begin
w1 <= write_ready & read_ready & !w2;
w2 <= w1;
write <= w1 & !w2;
end
end
wire locked;
`ifdef DOING_SIMULATION
reg AUD_XCK;
initial AUD_XCK = 0;
always begin
#(40690);
AUD_XCK = ~AUD_XCK;
end
`else
`endif
audio_and_video_config cfg(
CLOCK_50,
reset,
FPGA_I2C_SDAT,
FPGA_I2C_SCLK
);
audio_codec codec(
CLOCK_50,
reset,
read, write,
dac_left, dac_right,
AUD_ADCDAT,
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
read_ready, write_ready,
adc_left, adc_right,
AUD_DACDAT
);
endmodule | module audio_driver (CLOCK_50, reset, dac_left, dac_right, adc_left, adc_right, advance, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT); |
input CLOCK_50;
input reset;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
output AUD_XCK;
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
input AUD_ADCDAT;
output AUD_DACDAT;
input [23:0] dac_left, dac_right;
output [23:0] adc_left, adc_right;
output advance;
wire read_ready, write_ready;
reg write;
wire read;
reg w1, w2;
assign read = write;
assign advance = write;
always @(posedge CLOCK_50) begin
if (reset) begin
w1 <= 0;
w2 <= 0;
write <= 0;
end else begin
w1 <= write_ready & read_ready & !w2;
w2 <= w1;
write <= w1 & !w2;
end
end
wire locked;
`ifdef DOING_SIMULATION
reg AUD_XCK;
initial AUD_XCK = 0;
always begin
#(40690);
AUD_XCK = ~AUD_XCK;
end
`else
`endif
audio_and_video_config cfg(
CLOCK_50,
reset,
FPGA_I2C_SDAT,
FPGA_I2C_SCLK
);
audio_codec codec(
CLOCK_50,
reset,
read, write,
dac_left, dac_right,
AUD_ADCDAT,
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
read_ready, write_ready,
adc_left, adc_right,
AUD_DACDAT
);
endmodule | 0 |
3,960 | data/full_repos/permissive/107757225/audio/pll/audio/pll/audio_bb.v | 107,757,225 | audio_bb.v | v | 11 | 32 | [] | [] | [] | [(2, 10)] | null | data/verilator_xmls/54253515-bbb1-439f-a602-82b842653d80.xml | null | 2,250 | module | module audio (
clk_clk,
reset_reset_n,
pll_clk_out_18mhz_clk);
input clk_clk;
input reset_reset_n;
output pll_clk_out_18mhz_clk;
endmodule | module audio (
clk_clk,
reset_reset_n,
pll_clk_out_18mhz_clk); |
input clk_clk;
input reset_reset_n;
output pll_clk_out_18mhz_clk;
endmodule | 0 |
3,961 | data/full_repos/permissive/107757225/ECE385-HelperTools/PNG To Hex/On-Chip Memory/ram.sv | 107,757,225 | ram.sv | sv | 33 | 56 | [] | [] | [] | [(7, 32)] | null | null | 1: b'%Error: Cannot find file containing module: To\n ... Looked in:\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.v\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.sv\n To\n To.v\n To.sv\n obj_dir/To\n obj_dir/To.v\n obj_dir/To.sv\n%Error: Cannot find file containing module: Hex/On-Chip\n%Error: Cannot find file containing module: Memory,data/full_repos/permissive/107757225\n%Error: Cannot find file containing module: data/full_repos/permissive/107757225/ECE385-HelperTools/PNG\n%Error: Cannot find file containing module: Memory/ram.sv\n%Error: Exiting due to 5 error(s)\n' | 2,256 | module | module frameRAM
(
input [4:0] data_In,
input [18:0] write_address, read_address,
input we, Clk,
output logic [4:0] data_Out
);
logic [2:0] mem [0:399];
initial
begin
end
always_ff @ (posedge Clk) begin
if (we)
mem[write_address] <= data_In;
data_Out<= mem[read_address];
end
endmodule | module frameRAM
(
input [4:0] data_In,
input [18:0] write_address, read_address,
input we, Clk,
output logic [4:0] data_Out
); |
logic [2:0] mem [0:399];
initial
begin
end
always_ff @ (posedge Clk) begin
if (we)
mem[write_address] <= data_In;
data_Out<= mem[read_address];
end
endmodule | 0 |
3,962 | data/full_repos/permissive/107757225/ECE385-HelperTools/PNG To Hex/On-Chip Memory/sprite_bytes/tetris_I.sv | 107,757,225 | tetris_I.sv | sv | 411 | 125 | [] | [] | [] | null | line:42: before: "[" | null | 1: b'%Error: Cannot find file containing module: To\n ... Looked in:\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.v\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.sv\n To\n To.v\n To.sv\n obj_dir/To\n obj_dir/To.v\n obj_dir/To.sv\n%Error: Cannot find file containing module: Hex/On-Chip\n%Error: Cannot find file containing module: Memory/sprite_bytes,data/full_repos/permissive/107757225\n%Error: Cannot find file containing module: data/full_repos/permissive/107757225/ECE385-HelperTools/PNG\n%Error: Cannot find file containing module: Memory/sprite_bytes/tetris_I.sv\n%Error: Exiting due to 5 error(s)\n' | 2,260 | module | module tetris_I(input [9:0] SpriteX, SpriteY,
output [7:0] SpriteR, SpriteG, SpriteB);
logic [9:0] X_Index, Y_Index;
assign X_Index = SpriteX % 10'd8;
assign Y_Index = SpriteY % 10'd8;
logic [9:0] SpriteTableR;
parameter bit [7:0] SpritePaletteR[2:0] = '{8'd49, 8'd16, 8'd66};
always_comb
begin
SpriteTableR = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_2_2[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableR_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_0_1[7:0][7:0] = '{'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_0_2[7:0][3:0] = '{'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableR_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_1_1[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_1_2[7:0][3:0] = '{'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableR_2_0[3:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd1,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_2_1[3:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_2_2[3:0][3:0] = '{'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0}};
logic [9:0] SpriteTableG;
parameter bit [7:0] SpritePaletteG[6:0] = '{8'd33, 8'd58, 8'd253, 8'd220, 8'd189, 8'd157, 8'd123};
always_comb
begin
SpriteTableG = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_2_2[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableG_0_0[7:0][7:0] = '{'{3'd0,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd5,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd5,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6}};
parameter bit [2:0] SpriteTableG_0_1[7:0][7:0] = '{'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd4,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd5,3'd4,3'd5,3'd6,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_0_2[7:0][3:0] = '{'{3'd0,3'd3,3'd4,3'd5},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd0,3'd3,3'd5,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd0,3'd4,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd1,3'd0,3'd1,3'd1},
'{3'd1,3'd1,3'd1,3'd1}};
parameter bit [2:0] SpriteTableG_1_0[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd5},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd5,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_1_1[7:0][7:0] = '{'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_1_2[7:0][3:0] = '{'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd1,3'd1,3'd1,3'd1},
'{3'd1,3'd1,3'd1,3'd1}};
parameter bit [2:0] SpriteTableG_2_0[3:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd0,3'd3,3'd3,3'd3,3'd0},
'{3'd4,3'd5,3'd5,3'd0,3'd5,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0}};
parameter bit [2:0] SpriteTableG_2_1[3:0][7:0] = '{'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0}};
parameter bit [2:0] SpriteTableG_2_2[3:0][3:0] = '{'{3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0},
'{3'd1,3'd1,3'd0,3'd1}};
logic [9:0] SpriteTableB;
parameter bit [7:0] SpritePaletteB[4:0] = '{8'd38, 8'd64, 8'd255, 8'd226, 8'd191};
always_comb
begin
SpriteTableB = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_2_2[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableB_0_0[7:0][7:0] = '{'{3'd0,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4}};
parameter bit [2:0] SpriteTableB_0_1[7:0][7:0] = '{'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd4,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_0_2[7:0][3:0] = '{'{3'd0,3'd2,3'd3,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd4,3'd3},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd1,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableB_1_0[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd2},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd2,3'd3},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd2,3'd3,3'd4},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_1_1[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_1_2[7:0][3:0] = '{'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableB_2_0[3:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd0,3'd2,3'd2,3'd2,3'd0},
'{3'd2,3'd3,3'd3,3'd0,3'd3,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0}};
parameter bit [2:0] SpriteTableB_2_1[3:0][7:0] = '{'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0}};
parameter bit [2:0] SpriteTableB_2_2[3:0][3:0] = '{'{3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0},
'{3'd3,3'd4,3'd2,3'd0},
'{3'd0,3'd0,3'd0,3'd1}};
assign SpriteR = SpritePaletteR[SpriteTableR];
assign SpriteG = SpritePaletteG[SpriteTableG];
assign SpriteB = SpritePaletteB[SpriteTableB];
endmodule | module tetris_I(input [9:0] SpriteX, SpriteY,
output [7:0] SpriteR, SpriteG, SpriteB); |
logic [9:0] X_Index, Y_Index;
assign X_Index = SpriteX % 10'd8;
assign Y_Index = SpriteY % 10'd8;
logic [9:0] SpriteTableR;
parameter bit [7:0] SpritePaletteR[2:0] = '{8'd49, 8'd16, 8'd66};
always_comb
begin
SpriteTableR = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableR = SpriteTableR_2_2[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableR_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd0,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd0,2'd0},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_0_1[7:0][7:0] = '{'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_0_2[7:0][3:0] = '{'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableR_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_1_1[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_1_2[7:0][3:0] = '{'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableR_2_0[3:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd1,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_2_1[3:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1}};
parameter bit [1:0] SpriteTableR_2_2[3:0][3:0] = '{'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0}};
logic [9:0] SpriteTableG;
parameter bit [7:0] SpritePaletteG[6:0] = '{8'd33, 8'd58, 8'd253, 8'd220, 8'd189, 8'd157, 8'd123};
always_comb
begin
SpriteTableG = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableG = SpriteTableG_2_2[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableG_0_0[7:0][7:0] = '{'{3'd0,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd5,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd4,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd5,3'd4,3'd4},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6}};
parameter bit [2:0] SpriteTableG_0_1[7:0][7:0] = '{'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd4,3'd4,3'd4,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd4,3'd5,3'd6},
'{3'd0,3'd3,3'd5,3'd5,3'd4,3'd5,3'd6,3'd6},
'{3'd0,3'd3,3'd5,3'd4,3'd5,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_0_2[7:0][3:0] = '{'{3'd0,3'd3,3'd4,3'd5},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd0,3'd3,3'd5,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd0,3'd4,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd1,3'd0,3'd1,3'd1},
'{3'd1,3'd1,3'd1,3'd1}};
parameter bit [2:0] SpriteTableG_1_0[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd5},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd5,3'd6},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd5,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_1_1[7:0][7:0] = '{'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6,3'd6}};
parameter bit [2:0] SpriteTableG_1_2[7:0][3:0] = '{'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd6,3'd6,3'd6,3'd6},
'{3'd1,3'd1,3'd1,3'd1},
'{3'd1,3'd1,3'd1,3'd1}};
parameter bit [2:0] SpriteTableG_2_0[3:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd0,3'd3,3'd3,3'd3,3'd0},
'{3'd4,3'd5,3'd5,3'd0,3'd5,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0}};
parameter bit [2:0] SpriteTableG_2_1[3:0][7:0] = '{'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0,3'd6,3'd6,3'd5,3'd0}};
parameter bit [2:0] SpriteTableG_2_2[3:0][3:0] = '{'{3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0},
'{3'd6,3'd6,3'd5,3'd0},
'{3'd1,3'd1,3'd0,3'd1}};
logic [9:0] SpriteTableB;
parameter bit [7:0] SpritePaletteB[4:0] = '{8'd38, 8'd64, 8'd255, 8'd226, 8'd191};
always_comb
begin
SpriteTableB = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd20 && SpriteY >= 10'd16 && SpriteY < 10'd20)
begin
SpriteTableB = SpriteTableB_2_2[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableB_0_0[7:0][7:0] = '{'{3'd0,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4}};
parameter bit [2:0] SpriteTableB_0_1[7:0][7:0] = '{'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd3,3'd4,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd3,3'd3,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_0_2[7:0][3:0] = '{'{3'd0,3'd2,3'd3,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd2,3'd4,3'd3},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd1,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableB_1_0[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2,3'd2},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd2},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd2,3'd3},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd2,3'd3,3'd4},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_1_1[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableB_1_2[7:0][3:0] = '{'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd3,3'd3,3'd3,3'd3},
'{3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableB_2_0[3:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd0,3'd2,3'd2,3'd2,3'd0},
'{3'd2,3'd3,3'd3,3'd0,3'd3,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0}};
parameter bit [2:0] SpriteTableB_2_1[3:0][7:0] = '{'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0,3'd4,3'd4,3'd3,3'd0}};
parameter bit [2:0] SpriteTableB_2_2[3:0][3:0] = '{'{3'd4,3'd4,3'd3,3'd0},
'{3'd4,3'd4,3'd3,3'd0},
'{3'd3,3'd4,3'd2,3'd0},
'{3'd0,3'd0,3'd0,3'd1}};
assign SpriteR = SpritePaletteR[SpriteTableR];
assign SpriteG = SpritePaletteG[SpriteTableG];
assign SpriteB = SpritePaletteB[SpriteTableB];
endmodule | 0 |
3,963 | data/full_repos/permissive/107757225/ECE385-HelperTools/PNG To Hex/On-Chip Memory/sprite_bytes/up.sv | 107,757,225 | up.sv | sv | 741 | 125 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: To\n ... Looked in:\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.v\n data/full_repos/permissive/107757225/ECE385-HelperTools/PNG/To.sv\n To\n To.v\n To.sv\n obj_dir/To\n obj_dir/To.v\n obj_dir/To.sv\n%Error: Cannot find file containing module: Hex/On-Chip\n%Error: Cannot find file containing module: Memory/sprite_bytes,data/full_repos/permissive/107757225\n%Error: Cannot find file containing module: data/full_repos/permissive/107757225/ECE385-HelperTools/PNG\n%Error: Cannot find file containing module: Memory/sprite_bytes/up.sv\n%Error: Exiting due to 5 error(s)\n' | 2,261 | module | module up(input [9:0] SpriteX, SpriteY,
output [7:0] SpriteR, SpriteG, SpriteB);
logic [9:0] X_Index, Y_Index;
assign X_Index = SpriteX % 10'd8;
assign Y_Index = SpriteY % 10'd8;
logic [9:0] SpriteTableR;
parameter bit [7:0] SpritePaletteR[4:0] = '{8'd240, 8'd121, 8'd69, 8'd16, 8'd34};
always_comb
begin
SpriteTableR = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_3_3[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableR_0_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_0_1[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4},
'{3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4},
'{3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd1,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3}};
parameter bit [2:0] SpriteTableR_0_2[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_0_3[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_1_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4},
'{3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4},
'{3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_1[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_2[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_3[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_2_0[7:0][7:0] = '{'{3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd3,3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd3,3'd2,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd3,3'd2,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd3,3'd2,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2}};
parameter bit [2:0] SpriteTableR_2_1[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_2_2[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3}};
parameter bit [2:0] SpriteTableR_2_3[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3}};
parameter bit [2:0] SpriteTableR_3_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_3_1[7:0][7:0] = '{'{3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd3,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd3,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd3,3'd1,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd3,3'd1,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd3,3'd1,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd1,3'd0},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd1}};
parameter bit [2:0] SpriteTableR_3_2[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_3_3[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
logic [9:0] SpriteTableG;
parameter bit [7:0] SpritePaletteG[2:0] = '{8'd255, 8'd207, 8'd177};
always_comb
begin
SpriteTableG = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_3_3[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableG_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_0_1[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_0_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_0_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_1[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_2[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_3[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_0[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_1[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_2[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_3[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_3_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_3_1[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd1,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd1,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd1,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd1}};
parameter bit [1:0] SpriteTableG_3_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_3_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
logic [9:0] SpriteTableB;
parameter bit [7:0] SpritePaletteB[3:0] = '{8'd243, 8'd146, 8'd104, 8'd65};
always_comb
begin
SpriteTableB = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_3_3[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableB_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_0_1[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_0_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_0_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_1[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_2[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_3[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_0[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd2,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd2,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd2,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd2,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd2}};
parameter bit [1:0] SpriteTableB_2_1[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_2[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_3[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_3_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_3_1[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd1,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd1,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd1,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd1}};
parameter bit [1:0] SpriteTableB_3_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_3_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
assign SpriteR = SpritePaletteR[SpriteTableR];
assign SpriteG = SpritePaletteG[SpriteTableG];
assign SpriteB = SpritePaletteB[SpriteTableB];
endmodule | module up(input [9:0] SpriteX, SpriteY,
output [7:0] SpriteR, SpriteG, SpriteB); |
logic [9:0] X_Index, Y_Index;
assign X_Index = SpriteX % 10'd8;
assign Y_Index = SpriteY % 10'd8;
logic [9:0] SpriteTableR;
parameter bit [7:0] SpritePaletteR[4:0] = '{8'd240, 8'd121, 8'd69, 8'd16, 8'd34};
always_comb
begin
SpriteTableR = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableR = SpriteTableR_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableR = SpriteTableR_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableR = SpriteTableR_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableR = SpriteTableR_3_3[Y_Index][X_Index];
end
end
parameter bit [2:0] SpriteTableR_0_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_0_1[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4},
'{3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4},
'{3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd1,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3}};
parameter bit [2:0] SpriteTableR_0_2[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_0_3[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_1_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4},
'{3'd0,3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4},
'{3'd0,3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4},
'{3'd0,3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4},
'{3'd0,3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd1,3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_1[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_2[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_1_3[7:0][7:0] = '{'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd3,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_2_0[7:0][7:0] = '{'{3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd3,3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd3,3'd2,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd3,3'd2,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd3,3'd2,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd2}};
parameter bit [2:0] SpriteTableR_2_1[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4}};
parameter bit [2:0] SpriteTableR_2_2[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3}};
parameter bit [2:0] SpriteTableR_2_3[7:0][7:0] = '{'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd4,3'd3}};
parameter bit [2:0] SpriteTableR_3_0[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_3_1[7:0][7:0] = '{'{3'd2,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd3,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd3,3'd1,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd3,3'd1,3'd0,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd3,3'd1,3'd0,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd3,3'd1,3'd0,3'd0},
'{3'd4,3'd4,3'd4,3'd4,3'd4,3'd3,3'd1,3'd0},
'{3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd3,3'd1}};
parameter bit [2:0] SpriteTableR_3_2[7:0][7:0] = '{'{3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1,3'd1},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
parameter bit [2:0] SpriteTableR_3_3[7:0][7:0] = '{'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0},
'{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}};
logic [9:0] SpriteTableG;
parameter bit [7:0] SpritePaletteG[2:0] = '{8'd255, 8'd207, 8'd177};
always_comb
begin
SpriteTableG = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableG = SpriteTableG_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableG = SpriteTableG_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableG = SpriteTableG_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableG = SpriteTableG_3_3[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableG_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_0_1[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_0_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_0_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd0,2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd1,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_1[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_2[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_1_3[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_0[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_1[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_2[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_2_3[7:0][7:0] = '{'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2}};
parameter bit [1:0] SpriteTableG_3_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_3_1[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd1,2'd0,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd1,2'd0,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd1,2'd0},
'{2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd2,2'd1}};
parameter bit [1:0] SpriteTableG_3_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableG_3_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
logic [9:0] SpriteTableB;
parameter bit [7:0] SpritePaletteB[3:0] = '{8'd243, 8'd146, 8'd104, 8'd65};
always_comb
begin
SpriteTableB = 10'd0;
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_0_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_0_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_0_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd0 && SpriteX < 10'd8 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_0_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_1_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_1_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_1_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd8 && SpriteX < 10'd16 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_1_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_2_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_2_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_2_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd16 && SpriteX < 10'd24 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_2_3[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd0 && SpriteY < 10'd8)
begin
SpriteTableB = SpriteTableB_3_0[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd8 && SpriteY < 10'd16)
begin
SpriteTableB = SpriteTableB_3_1[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd16 && SpriteY < 10'd24)
begin
SpriteTableB = SpriteTableB_3_2[Y_Index][X_Index];
end
else
if(SpriteX >= 10'd24 && SpriteX < 10'd32 && SpriteY >= 10'd24 && SpriteY < 10'd32)
begin
SpriteTableB = SpriteTableB_3_3[Y_Index][X_Index];
end
end
parameter bit [1:0] SpriteTableB_0_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_0_1[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_0_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_0_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_1_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd0,2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd1,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_1[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_2[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_1_3[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_0[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd2,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd2,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd2,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd2,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd2,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd2}};
parameter bit [1:0] SpriteTableB_2_1[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_2[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_2_3[7:0][7:0] = '{'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3}};
parameter bit [1:0] SpriteTableB_3_0[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_3_1[7:0][7:0] = '{'{2'd2,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd1,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd1,2'd0,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd1,2'd0,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd1,2'd0,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd1,2'd0},
'{2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd3,2'd1}};
parameter bit [1:0] SpriteTableB_3_2[7:0][7:0] = '{'{2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1,2'd1},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
parameter bit [1:0] SpriteTableB_3_3[7:0][7:0] = '{'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0},
'{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}};
assign SpriteR = SpritePaletteR[SpriteTableR];
assign SpriteG = SpritePaletteG[SpriteTableG];
assign SpriteB = SpritePaletteB[SpriteTableB];
endmodule | 0 |
3,964 | data/full_repos/permissive/107757225/ps2_kb/11_reg.sv | 107,757,225 | 11_reg.sv | sv | 27 | 76 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/b3a70f95-2006-48dc-81f0-fe51b000ece8.xml | null | 2,263 | module | module reg_11 (input logic Clk, Reset, Shift_In, Load, Shift_En,
input logic [10:0] D,
output logic Shift_Out,
output logic [10:0] Data_Out);
always_ff @ (posedge Clk or posedge Load or posedge Reset)
begin
if (Reset)
Data_Out <= 11'h0;
else if (Load)
Data_Out <= D;
else if (Shift_En)
Data_Out <= {Shift_In,Data_Out[10:1]};
end
assign Shift_Out = Data_Out[0];
endmodule | module reg_11 (input logic Clk, Reset, Shift_In, Load, Shift_En,
input logic [10:0] D,
output logic Shift_Out,
output logic [10:0] Data_Out); |
always_ff @ (posedge Clk or posedge Load or posedge Reset)
begin
if (Reset)
Data_Out <= 11'h0;
else if (Load)
Data_Out <= D;
else if (Shift_En)
Data_Out <= {Shift_In,Data_Out[10:1]};
end
assign Shift_Out = Data_Out[0];
endmodule | 0 |
3,965 | data/full_repos/permissive/107757225/ps2_kb/Dreg.sv | 107,757,225 | Dreg.sv | sv | 24 | 76 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/09f24a76-ed84-4545-ae28-4b9f58f350f3.xml | null | 2,264 | module | module Dreg ( input Clk, Load, Reset, D,
output logic Q );
always @ (posedge Clk or posedge Reset )
begin
Q = Q;
if (Reset)
Q = 1'b0;
else if (Load)
Q = D;
end
endmodule | module Dreg ( input Clk, Load, Reset, D,
output logic Q ); |
always @ (posedge Clk or posedge Reset )
begin
Q = Q;
if (Reset)
Q = 1'b0;
else if (Load)
Q = D;
end
endmodule | 0 |
3,966 | data/full_repos/permissive/107757225/ps2_kb/keyboard.sv | 107,757,225 | keyboard.sv | sv | 135 | 122 | [] | [] | [] | null | line:37: before: "+" | null | 1: b"%Error: data/full_repos/permissive/107757225/ps2_kb/keyboard.sv:99: Cannot find file containing module: 'Dreg'\n Dreg Dreg_instance1 ( .*,\n ^~~~\n ... Looked in:\n data/full_repos/permissive/107757225/ps2_kb,data/full_repos/permissive/107757225/Dreg\n data/full_repos/permissive/107757225/ps2_kb,data/full_repos/permissive/107757225/Dreg.v\n data/full_repos/permissive/107757225/ps2_kb,data/full_repos/permissive/107757225/Dreg.sv\n Dreg\n Dreg.v\n Dreg.sv\n obj_dir/Dreg\n obj_dir/Dreg.v\n obj_dir/Dreg.sv\n%Error: data/full_repos/permissive/107757225/ps2_kb/keyboard.sv:104: Cannot find file containing module: 'Dreg'\n Dreg Dreg_instance2 ( .*,\n ^~~~\n%Error: data/full_repos/permissive/107757225/ps2_kb/keyboard.sv:110: Cannot find file containing module: 'reg_11'\n reg_11 reg_B(\n ^~~~~~\n%Error: data/full_repos/permissive/107757225/ps2_kb/keyboard.sv:121: Cannot find file containing module: 'reg_11'\n reg_11 reg_A(\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 2,265 | module | module keyboard(
input logic Clk, psClk, psData, reset,
output logic [7:0] keyCode,
output logic press
);
logic Q1, Q2, en, enable, shiftout1, shiftout2, Press;
logic [4:0] Count;
logic [10:0] Byte_1, Byte_2;
logic [7:0] Data, Typematic_Keycode;
logic [9:0] counter;
always@(posedge Clk or posedge reset)
begin
if(reset)
begin
counter = 10'b0000000000;
enable = 1'b1;
end
else if (counter == 10'b0111111111)
begin
counter = 10'b0000000000;
enable = 1'b1;
end
else
begin
counter += 1'b1;
enable = 1'b0;
end
end
always@(posedge Clk)
begin
if(enable==1)
begin
if((reset)|| (Count==5'b01011))
Count <= 5'b00000;
else if(Q1==0 && Q2==1)
begin
Count += 1'b1;
en = 1'b1;
end
end
end
always@(posedge Clk)
begin
if(Count == 5'd11)
begin
if (Byte_2[9:2] == 8'hE0)
begin
end
else if (Byte_2[9:2] == 8'hF0)
begin
end
else if (Byte_1[9:2] == 8'hF0)
begin
Data = 8'b0;
Press = 1'b0;
if (Data == Typematic_Keycode)
Typematic_Keycode = 8'h00;
end
else if (Byte_1[9:2] != 8'hF0)
begin
Data = Byte_2[9:2];
Press = 1'b1;
Typematic_Keycode = Data;
end
end
end
Dreg Dreg_instance1 ( .*,
.Load(enable),
.Reset(reset),
.D(psClk),
.Q(Q1) );
Dreg Dreg_instance2 ( .*,
.Load(enable),
.Reset(reset),
.D(Q1),
.Q(Q2) );
reg_11 reg_B(
.Clk(psClk),
.Reset(reset),
.Shift_In(psData),
.Load(1'b0),
.Shift_En(en),
.D(11'd0),
.Shift_Out(shiftout2),
.Data_Out(Byte_2)
);
reg_11 reg_A(
.Clk(psClk),
.Reset(reset),
.Shift_In(shiftout2),
.Load(1'b0),
.Shift_En(en),
.D(11'd0),
.Shift_Out(shiftout1),
.Data_Out(Byte_1)
);
assign keyCode=Data;
assign press=Press;
endmodule | module keyboard(
input logic Clk, psClk, psData, reset,
output logic [7:0] keyCode,
output logic press
); |
logic Q1, Q2, en, enable, shiftout1, shiftout2, Press;
logic [4:0] Count;
logic [10:0] Byte_1, Byte_2;
logic [7:0] Data, Typematic_Keycode;
logic [9:0] counter;
always@(posedge Clk or posedge reset)
begin
if(reset)
begin
counter = 10'b0000000000;
enable = 1'b1;
end
else if (counter == 10'b0111111111)
begin
counter = 10'b0000000000;
enable = 1'b1;
end
else
begin
counter += 1'b1;
enable = 1'b0;
end
end
always@(posedge Clk)
begin
if(enable==1)
begin
if((reset)|| (Count==5'b01011))
Count <= 5'b00000;
else if(Q1==0 && Q2==1)
begin
Count += 1'b1;
en = 1'b1;
end
end
end
always@(posedge Clk)
begin
if(Count == 5'd11)
begin
if (Byte_2[9:2] == 8'hE0)
begin
end
else if (Byte_2[9:2] == 8'hF0)
begin
end
else if (Byte_1[9:2] == 8'hF0)
begin
Data = 8'b0;
Press = 1'b0;
if (Data == Typematic_Keycode)
Typematic_Keycode = 8'h00;
end
else if (Byte_1[9:2] != 8'hF0)
begin
Data = Byte_2[9:2];
Press = 1'b1;
Typematic_Keycode = Data;
end
end
end
Dreg Dreg_instance1 ( .*,
.Load(enable),
.Reset(reset),
.D(psClk),
.Q(Q1) );
Dreg Dreg_instance2 ( .*,
.Load(enable),
.Reset(reset),
.D(Q1),
.Q(Q2) );
reg_11 reg_B(
.Clk(psClk),
.Reset(reset),
.Shift_In(psData),
.Load(1'b0),
.Shift_En(en),
.D(11'd0),
.Shift_Out(shiftout2),
.Data_Out(Byte_2)
);
reg_11 reg_A(
.Clk(psClk),
.Reset(reset),
.Shift_In(shiftout2),
.Load(1'b0),
.Shift_En(en),
.D(11'd0),
.Shift_Out(shiftout1),
.Data_Out(Byte_1)
);
assign keyCode=Data;
assign press=Press;
endmodule | 0 |
3,967 | data/full_repos/permissive/107757225/vga/arrow.sv | 107,757,225 | arrow.sv | sv | 147 | 127 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:38: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'DrawX\' generates 10 bits.\n : ... In instance arrow\nassign DistX = DrawX - arrow_1_pos_x;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:38: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'arrow_1_pos_x\' generates 10 bits.\n : ... In instance arrow\nassign DistX = DrawX - arrow_1_pos_x;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:39: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\nassign DistY = DrawY - arrow_1_pos_y;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:39: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'arrow_1_pos_y\' generates 10 bits.\n : ... In instance arrow\nassign DistY = DrawY - arrow_1_pos_y;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:71: Operator ASSIGNDLY expects 480 bits on the Assign RHS, but Assign RHS\'s CONST \'479\'h0\' generates 479 bits.\n : ... In instance arrow\n arrow0_heights <= 479\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:72: Operator ASSIGNDLY expects 480 bits on the Assign RHS, but Assign RHS\'s CONST \'479\'h0\' generates 479 bits.\n : ... In instance arrow\n arrow1_heights <= 479\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:73: Operator ASSIGNDLY expects 480 bits on the Assign RHS, but Assign RHS\'s CONST \'479\'h0\' generates 479 bits.\n : ... In instance arrow\n arrow2_heights <= 479\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:74: Operator ASSIGNDLY expects 480 bits on the Assign RHS, but Assign RHS\'s CONST \'479\'h0\' generates 479 bits.\n : ... In instance arrow\n arrow3_heights <= 479\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:117: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance arrow\n display_arrow = 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:121: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d256 && DrawX < 10\'d288 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:121: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d256 && DrawX < 10\'d288 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:124: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d288 && DrawX < 10\'d320 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:124: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d288 && DrawX < 10\'d320 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:127: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d320 && DrawX < 10\'d352 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:127: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d320 && DrawX < 10\'d352 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:130: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d352 && DrawX < 10\'d384 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/arrow.sv:130: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance arrow\n if (DrawX >= 10\'d352 && DrawX < 10\'d384 && DrawY <= (n+16) && DrawY >= (n-16))\n ^~\n%Error: Exiting due to 17 warning(s)\n' | 2,266 | module | module arrow (
input logic Clk, reset, frame_clk,
input [9:0] DrawX, DrawY,
input [3:0] display_signal,
output logic [3:0] display_arrow
);
parameter [9:0] arrow_1_center_x = 272;
parameter [9:0] arrow_2_center_x = 304;
parameter [9:0] arrow_3_center_x = 336;
parameter [9:0] arrow_4_center_x = 368;
parameter [9:0] arrow_start_center_y = 480-16;
parameter [9:0] arrow_speed = -2;
logic [9:0] arrow_1_pos_x, arrow_1_pos_y, arrow_1_motion_y;
logic [9:0] arrow_1_pos_x_in, arrow_1_pos_y_in, arrow_1_motion_y_in;
logic [479:0] arrow0_heights, arrow1_heights, arrow2_heights, arrow3_heights;
int DistX, DistY, Size;
assign DistX = DrawX - arrow_1_pos_x;
assign DistY = DrawY - arrow_1_pos_y;
assign Size = 16;
logic frame_clk_delayed;
logic frame_clk_rising_edge;
always_ff @ (posedge Clk)
begin
frame_clk_delayed <= frame_clk;
end
assign frame_clk_rising_edge = (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
always_ff @ (posedge Clk)
begin
if(reset)
begin
arrow_1_pos_x <= arrow_1_center_x;
arrow_1_pos_y <= arrow_start_center_y;
arrow_1_motion_y <= 10'b0;
end
else if(frame_clk_rising_edge)
begin
arrow_1_pos_x <= arrow_1_pos_x_in;
arrow_1_pos_y <= arrow_1_pos_y_in;
arrow_1_motion_y <= arrow_1_motion_y_in;
end
end
always_ff @ (posedge Clk)
begin
if(reset)
begin
arrow0_heights <= 479'b0;
arrow1_heights <= 479'b0;
arrow2_heights <= 479'b0;
arrow3_heights <= 479'b0;
end
else if(frame_clk_rising_edge)
begin
for(int i=2; i<480; i++)
begin
arrow0_heights[i-2] <= arrow0_heights[i];
arrow0_heights[i] <= 1'b0;
arrow1_heights[i-2] <= arrow1_heights[i];
arrow1_heights[i] <= 1'b0;
arrow2_heights[i-2] <= arrow2_heights[i];
arrow2_heights[i] <= 1'b0;
arrow3_heights[i-2] <= arrow3_heights[i];
arrow3_heights[i] <= 1'b0;
end
arrow0_heights[0] <= 1'b0;
arrow1_heights[0] <= 1'b0;
arrow2_heights[0] <= 1'b0;
arrow3_heights[0] <= 1'b0;
if(display_signal[0])
begin
arrow0_heights[479] <= 1'b1;
end
if(display_signal[1])
begin
arrow1_heights[479] <= 1'b1;
end
if(display_signal[2])
begin
arrow2_heights[479] <= 1'b1;
end
if(display_signal[3])
begin
arrow3_heights[479] <= 1'b1;
end
end
end
always_comb
begin
display_arrow = 1'b0;
for(int n=0; n<480;n++)
begin
if (arrow0_heights[n] == 1'b1)
if (DrawX >= 10'd256 && DrawX < 10'd288 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[0] = 1'b1;
if (arrow1_heights[n] == 1'b1)
if (DrawX >= 10'd288 && DrawX < 10'd320 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[1] = 1'b1;
if (arrow2_heights[n] == 1'b1)
if (DrawX >= 10'd320 && DrawX < 10'd352 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[2] = 1'b1;
if (arrow3_heights[n] == 1'b1)
if (DrawX >= 10'd352 && DrawX < 10'd384 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[3] = 1'b1;
end
end
endmodule | module arrow (
input logic Clk, reset, frame_clk,
input [9:0] DrawX, DrawY,
input [3:0] display_signal,
output logic [3:0] display_arrow
); |
parameter [9:0] arrow_1_center_x = 272;
parameter [9:0] arrow_2_center_x = 304;
parameter [9:0] arrow_3_center_x = 336;
parameter [9:0] arrow_4_center_x = 368;
parameter [9:0] arrow_start_center_y = 480-16;
parameter [9:0] arrow_speed = -2;
logic [9:0] arrow_1_pos_x, arrow_1_pos_y, arrow_1_motion_y;
logic [9:0] arrow_1_pos_x_in, arrow_1_pos_y_in, arrow_1_motion_y_in;
logic [479:0] arrow0_heights, arrow1_heights, arrow2_heights, arrow3_heights;
int DistX, DistY, Size;
assign DistX = DrawX - arrow_1_pos_x;
assign DistY = DrawY - arrow_1_pos_y;
assign Size = 16;
logic frame_clk_delayed;
logic frame_clk_rising_edge;
always_ff @ (posedge Clk)
begin
frame_clk_delayed <= frame_clk;
end
assign frame_clk_rising_edge = (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
always_ff @ (posedge Clk)
begin
if(reset)
begin
arrow_1_pos_x <= arrow_1_center_x;
arrow_1_pos_y <= arrow_start_center_y;
arrow_1_motion_y <= 10'b0;
end
else if(frame_clk_rising_edge)
begin
arrow_1_pos_x <= arrow_1_pos_x_in;
arrow_1_pos_y <= arrow_1_pos_y_in;
arrow_1_motion_y <= arrow_1_motion_y_in;
end
end
always_ff @ (posedge Clk)
begin
if(reset)
begin
arrow0_heights <= 479'b0;
arrow1_heights <= 479'b0;
arrow2_heights <= 479'b0;
arrow3_heights <= 479'b0;
end
else if(frame_clk_rising_edge)
begin
for(int i=2; i<480; i++)
begin
arrow0_heights[i-2] <= arrow0_heights[i];
arrow0_heights[i] <= 1'b0;
arrow1_heights[i-2] <= arrow1_heights[i];
arrow1_heights[i] <= 1'b0;
arrow2_heights[i-2] <= arrow2_heights[i];
arrow2_heights[i] <= 1'b0;
arrow3_heights[i-2] <= arrow3_heights[i];
arrow3_heights[i] <= 1'b0;
end
arrow0_heights[0] <= 1'b0;
arrow1_heights[0] <= 1'b0;
arrow2_heights[0] <= 1'b0;
arrow3_heights[0] <= 1'b0;
if(display_signal[0])
begin
arrow0_heights[479] <= 1'b1;
end
if(display_signal[1])
begin
arrow1_heights[479] <= 1'b1;
end
if(display_signal[2])
begin
arrow2_heights[479] <= 1'b1;
end
if(display_signal[3])
begin
arrow3_heights[479] <= 1'b1;
end
end
end
always_comb
begin
display_arrow = 1'b0;
for(int n=0; n<480;n++)
begin
if (arrow0_heights[n] == 1'b1)
if (DrawX >= 10'd256 && DrawX < 10'd288 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[0] = 1'b1;
if (arrow1_heights[n] == 1'b1)
if (DrawX >= 10'd288 && DrawX < 10'd320 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[1] = 1'b1;
if (arrow2_heights[n] == 1'b1)
if (DrawX >= 10'd320 && DrawX < 10'd352 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[2] = 1'b1;
if (arrow3_heights[n] == 1'b1)
if (DrawX >= 10'd352 && DrawX < 10'd384 && DrawY <= (n+16) && DrawY >= (n-16))
display_arrow[3] = 1'b1;
end
end
endmodule | 0 |
3,968 | data/full_repos/permissive/107757225/vga/ball.sv | 107,757,225 | ball.sv | sv | 131 | 111 | [] | [] | [] | null | line:24: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/vga/ball.sv:25: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'DrawX\' generates 10 bits.\n : ... In instance ball\n assign DistX = DrawX - Ball_X_Pos;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/ball.sv:25: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'Ball_X_Pos\' generates 10 bits.\n : ... In instance ball\n assign DistX = DrawX - Ball_X_Pos;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/ball.sv:26: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'DrawY\' generates 10 bits.\n : ... In instance ball\n assign DistY = DrawY - Ball_Y_Pos;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/ball.sv:26: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'Ball_Y_Pos\' generates 10 bits.\n : ... In instance ball\n assign DistY = DrawY - Ball_Y_Pos;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/vga/ball.sv:27: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ball_Size\' generates 10 bits.\n : ... In instance ball\n assign Size = Ball_Size;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 2,267 | module | module ball ( input Clk, Reset,
frame_clk,
input [9:0] DrawX, DrawY,
input [7:0] keycode,
output logic is_ball
);
parameter [9:0] Ball_X_Center=320;
parameter [9:0] Ball_Y_Center=240;
parameter [9:0] Ball_X_Min=0;
parameter [9:0] Ball_X_Max=639;
parameter [9:0] Ball_Y_Min=0;
parameter [9:0] Ball_Y_Max=479;
parameter [9:0] Ball_X_Step=1;
parameter [9:0] Ball_Y_Step=1;
parameter [9:0] Ball_Size=4;
logic [9:0] Ball_X_Pos, Ball_X_Motion, Ball_Y_Pos, Ball_Y_Motion;
logic [9:0] Ball_X_Pos_in, Ball_X_Motion_in, Ball_Y_Pos_in, Ball_Y_Motion_in;
int DistX, DistY, Size;
assign DistX = DrawX - Ball_X_Pos;
assign DistY = DrawY - Ball_Y_Pos;
assign Size = Ball_Size;
logic frame_clk_delayed;
logic frame_clk_rising_edge;
always_ff @ (posedge Clk) begin
frame_clk_delayed <= frame_clk;
end
assign frame_clk_rising_edge = (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
always_ff @ (posedge Clk)
begin
if (Reset)
begin
Ball_X_Pos <= Ball_X_Center;
Ball_Y_Pos <= Ball_Y_Center;
Ball_X_Motion <= 10'd0;
Ball_Y_Motion <= Ball_Y_Step;
end
else if (frame_clk_rising_edge)
begin
Ball_X_Pos <= Ball_X_Pos_in;
Ball_Y_Pos <= Ball_Y_Pos_in;
Ball_X_Motion <= Ball_X_Motion_in;
Ball_Y_Motion <= Ball_Y_Motion_in;
end
end
always_comb
begin
Ball_X_Pos_in = Ball_X_Pos + Ball_X_Motion;
Ball_Y_Pos_in = Ball_Y_Pos + Ball_Y_Motion;
Ball_X_Motion_in = Ball_X_Motion;
Ball_Y_Motion_in = Ball_Y_Motion;
if( Ball_X_Pos + Ball_Size >= Ball_X_Max )
begin
Ball_Y_Motion_in = 10'b0;
Ball_X_Motion_in = (~(Ball_X_Step) + 1'b1);
end
else if ( Ball_X_Pos <= Ball_X_Min + Ball_Size )
begin
Ball_Y_Motion_in = 10'b0;
Ball_X_Motion_in = Ball_X_Step;
end
if( Ball_Y_Pos - Ball_Size >= Ball_Y_Max )
begin
Ball_X_Motion_in = 10'b0;
Ball_Y_Motion_in = (~(Ball_Y_Step) + 1'b1);
end
else if ( Ball_Y_Pos <= Ball_Y_Min + Ball_Size )
begin
Ball_X_Motion_in = 10'b0;
Ball_Y_Motion_in = Ball_Y_Step;
end
if ( ( DistX*DistX + DistY*DistY) <= (Size * Size) )
is_ball = 1'b0;
else
is_ball = 1'b0;
end
endmodule | module ball ( input Clk, Reset,
frame_clk,
input [9:0] DrawX, DrawY,
input [7:0] keycode,
output logic is_ball
); |
parameter [9:0] Ball_X_Center=320;
parameter [9:0] Ball_Y_Center=240;
parameter [9:0] Ball_X_Min=0;
parameter [9:0] Ball_X_Max=639;
parameter [9:0] Ball_Y_Min=0;
parameter [9:0] Ball_Y_Max=479;
parameter [9:0] Ball_X_Step=1;
parameter [9:0] Ball_Y_Step=1;
parameter [9:0] Ball_Size=4;
logic [9:0] Ball_X_Pos, Ball_X_Motion, Ball_Y_Pos, Ball_Y_Motion;
logic [9:0] Ball_X_Pos_in, Ball_X_Motion_in, Ball_Y_Pos_in, Ball_Y_Motion_in;
int DistX, DistY, Size;
assign DistX = DrawX - Ball_X_Pos;
assign DistY = DrawY - Ball_Y_Pos;
assign Size = Ball_Size;
logic frame_clk_delayed;
logic frame_clk_rising_edge;
always_ff @ (posedge Clk) begin
frame_clk_delayed <= frame_clk;
end
assign frame_clk_rising_edge = (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
always_ff @ (posedge Clk)
begin
if (Reset)
begin
Ball_X_Pos <= Ball_X_Center;
Ball_Y_Pos <= Ball_Y_Center;
Ball_X_Motion <= 10'd0;
Ball_Y_Motion <= Ball_Y_Step;
end
else if (frame_clk_rising_edge)
begin
Ball_X_Pos <= Ball_X_Pos_in;
Ball_Y_Pos <= Ball_Y_Pos_in;
Ball_X_Motion <= Ball_X_Motion_in;
Ball_Y_Motion <= Ball_Y_Motion_in;
end
end
always_comb
begin
Ball_X_Pos_in = Ball_X_Pos + Ball_X_Motion;
Ball_Y_Pos_in = Ball_Y_Pos + Ball_Y_Motion;
Ball_X_Motion_in = Ball_X_Motion;
Ball_Y_Motion_in = Ball_Y_Motion;
if( Ball_X_Pos + Ball_Size >= Ball_X_Max )
begin
Ball_Y_Motion_in = 10'b0;
Ball_X_Motion_in = (~(Ball_X_Step) + 1'b1);
end
else if ( Ball_X_Pos <= Ball_X_Min + Ball_Size )
begin
Ball_Y_Motion_in = 10'b0;
Ball_X_Motion_in = Ball_X_Step;
end
if( Ball_Y_Pos - Ball_Size >= Ball_Y_Max )
begin
Ball_X_Motion_in = 10'b0;
Ball_Y_Motion_in = (~(Ball_Y_Step) + 1'b1);
end
else if ( Ball_Y_Pos <= Ball_Y_Min + Ball_Size )
begin
Ball_X_Motion_in = 10'b0;
Ball_Y_Motion_in = Ball_Y_Step;
end
if ( ( DistX*DistX + DistY*DistY) <= (Size * Size) )
is_ball = 1'b0;
else
is_ball = 1'b0;
end
endmodule | 0 |
3,969 | data/full_repos/permissive/107757225/vga/color_mapper.sv | 107,757,225 | color_mapper.sv | sv | 90 | 103 | [] | [] | [] | [(2, 90)] | null | data/verilator_xmls/6471a132-47d1-426a-aa14-2b587b9a09eb.xml | null | 2,268 | module | module color_mapper (
input is_ball, is_background, is_receptor_background,
input [3:0] is_receptor, display_arrow,
input [9:0] DrawX, DrawY,
output logic [7:0] VGA_R, VGA_G, VGA_B
);
logic [7:0] Red, Green, Blue;
assign VGA_R = Red;
assign VGA_G = Green;
assign VGA_B = Blue;
always_comb
begin
if (is_ball == 1'b1)
begin
Red = 8'hff;
Green = 8'hff;
Blue = 8'hff;
end
else if ( display_arrow[0] )
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if ( display_arrow[1])
begin
Red = 8'h00; Green = 8'h55; Blue = 8'h00;
end
else if ( display_arrow[2])
begin
Red = 8'h00; Green = 8'h00; Blue = 8'h55;
end
else if ( display_arrow[3])
begin
Red = 8'h40; Green = 8'h40; Blue = 8'h40;
end
else if (is_receptor[0] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[1] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[2] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[3] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor_background == 1'b1)
begin
Red = 8'h55; Green = 8'h55; Blue = 8'h55;
end
else if (is_background == 1'b1)
begin
Red = 8'h00; Green = 8'h00; Blue = 8'h00;
end
else
begin
Red = 8'h05; Green = 8'h4b;
Blue = 8'h7f - {1'b0, DrawX[9:3]};
end
end
endmodule | module color_mapper (
input is_ball, is_background, is_receptor_background,
input [3:0] is_receptor, display_arrow,
input [9:0] DrawX, DrawY,
output logic [7:0] VGA_R, VGA_G, VGA_B
); |
logic [7:0] Red, Green, Blue;
assign VGA_R = Red;
assign VGA_G = Green;
assign VGA_B = Blue;
always_comb
begin
if (is_ball == 1'b1)
begin
Red = 8'hff;
Green = 8'hff;
Blue = 8'hff;
end
else if ( display_arrow[0] )
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if ( display_arrow[1])
begin
Red = 8'h00; Green = 8'h55; Blue = 8'h00;
end
else if ( display_arrow[2])
begin
Red = 8'h00; Green = 8'h00; Blue = 8'h55;
end
else if ( display_arrow[3])
begin
Red = 8'h40; Green = 8'h40; Blue = 8'h40;
end
else if (is_receptor[0] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[1] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[2] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor[3] == 1'b1)
begin
Red = 8'h55; Green = 8'h00; Blue = 8'h00;
end
else if (is_receptor_background == 1'b1)
begin
Red = 8'h55; Green = 8'h55; Blue = 8'h55;
end
else if (is_background == 1'b1)
begin
Red = 8'h00; Green = 8'h00; Blue = 8'h00;
end
else
begin
Red = 8'h05; Green = 8'h4b;
Blue = 8'h7f - {1'b0, DrawX[9:3]};
end
end
endmodule | 0 |
3,970 | data/full_repos/permissive/107757225/vga/receptor.sv | 107,757,225 | receptor.sv | sv | 42 | 59 | [] | [] | [] | [(2, 41)] | null | data/verilator_xmls/3356db24-3828-4372-8863-577bca89318c.xml | null | 2,269 | module | module receptor(
output logic [3:0] is_receptor,
output logic is_background, is_receptor_background,
input logic [7:0] keycode,
input logic [9:0] DrawX, DrawY
);
always_comb begin
is_background = 1'b0;
is_receptor_background = 1'b0;
if ( DrawX >= 10'd256 && DrawX <= 10'd383 )
is_background = 1'b1;
if ( DrawY >= 10'd30 && DrawY <= 10'd79 )
if ( DrawX >= 10'd256 && DrawX <= 10'd383 )
is_receptor_background = 1'b1;
end
always_comb begin
is_receptor[3:0] = 4'b0;
if ( DrawY >= 10'd30 && DrawY <= 10'd79 )
begin
if ( DrawX >= 10'd256 && DrawX <= 10'd287 )
if ( keycode == 8'h34 )
is_receptor[0] = 1'b1;
if ( DrawX >= 10'd288 && DrawX <= 10'd319 )
if ( keycode == 8'h33 )
is_receptor[1] = 1'b1;
if ( DrawX >= 10'd320 && DrawX <= 10'd351 )
if ( keycode == 8'h35 )
is_receptor[2] = 1'b1;
if ( DrawX >= 10'd352 && DrawX <= 10'd383 )
if ( keycode == 8'h3b )
is_receptor[3] = 1'b1;
end
end
endmodule | module receptor(
output logic [3:0] is_receptor,
output logic is_background, is_receptor_background,
input logic [7:0] keycode,
input logic [9:0] DrawX, DrawY
); |
always_comb begin
is_background = 1'b0;
is_receptor_background = 1'b0;
if ( DrawX >= 10'd256 && DrawX <= 10'd383 )
is_background = 1'b1;
if ( DrawY >= 10'd30 && DrawY <= 10'd79 )
if ( DrawX >= 10'd256 && DrawX <= 10'd383 )
is_receptor_background = 1'b1;
end
always_comb begin
is_receptor[3:0] = 4'b0;
if ( DrawY >= 10'd30 && DrawY <= 10'd79 )
begin
if ( DrawX >= 10'd256 && DrawX <= 10'd287 )
if ( keycode == 8'h34 )
is_receptor[0] = 1'b1;
if ( DrawX >= 10'd288 && DrawX <= 10'd319 )
if ( keycode == 8'h33 )
is_receptor[1] = 1'b1;
if ( DrawX >= 10'd320 && DrawX <= 10'd351 )
if ( keycode == 8'h35 )
is_receptor[2] = 1'b1;
if ( DrawX >= 10'd352 && DrawX <= 10'd383 )
if ( keycode == 8'h3b )
is_receptor[3] = 1'b1;
end
end
endmodule | 0 |
3,971 | data/full_repos/permissive/107757225/vga/vga_controller.sv | 107,757,225 | vga_controller.sv | sv | 77 | 125 | [] | [] | [] | [(2, 77)] | null | data/verilator_xmls/24c5337f-62d5-4111-97f3-ab663221230c.xml | null | 2,271 | module | module vga_controller (input Clk,
Reset,
output logic VGA_HS,
VGA_VS,
input VGA_CLK,
output logic VGA_BLANK_N,
VGA_SYNC_N,
output logic [9:0] DrawX,
DrawY
);
parameter [9:0] H_TOTAL = 10'd800;
parameter [9:0] V_TOTAL = 10'd525;
logic VGA_HS_in, VGA_VS_in, VGA_BLANK_N_in;
logic [9:0] h_counter, v_counter;
logic [9:0] h_counter_in, v_counter_in;
assign VGA_SYNC_N = 1'b0;
assign DrawX = h_counter;
assign DrawY = v_counter;
always_ff @ (posedge VGA_CLK)
begin
if (Reset)
begin
VGA_HS <= 1'b0;
VGA_VS <= 1'b0;
VGA_BLANK_N <= 1'b0;
h_counter <= 10'd0;
v_counter <= 10'd0;
end
else
begin
VGA_HS <= VGA_HS_in;
VGA_VS <= VGA_VS_in;
VGA_BLANK_N <= VGA_BLANK_N_in;
h_counter <= h_counter_in;
v_counter <= v_counter_in;
end
end
always_comb
begin
h_counter_in = h_counter + 10'd1;
v_counter_in = v_counter;
if(h_counter + 10'd1 == H_TOTAL)
begin
h_counter_in = 10'd0;
if(v_counter + 10'd1 == V_TOTAL)
v_counter_in = 10'd0;
else
v_counter_in = v_counter + 10'd1;
end
VGA_HS_in = 1'b1;
if(h_counter_in >= 10'd656 && h_counter_in < 10'd752)
VGA_HS_in = 1'b0;
VGA_VS_in = 1'b1;
if(v_counter_in >= 10'd490 && v_counter_in < 10'd492)
VGA_VS_in = 1'b0;
VGA_BLANK_N_in = 1'b0;
if(h_counter_in < 10'd640 && v_counter_in < 10'd480)
VGA_BLANK_N_in = 1'b1;
end
endmodule | module vga_controller (input Clk,
Reset,
output logic VGA_HS,
VGA_VS,
input VGA_CLK,
output logic VGA_BLANK_N,
VGA_SYNC_N,
output logic [9:0] DrawX,
DrawY
); |
parameter [9:0] H_TOTAL = 10'd800;
parameter [9:0] V_TOTAL = 10'd525;
logic VGA_HS_in, VGA_VS_in, VGA_BLANK_N_in;
logic [9:0] h_counter, v_counter;
logic [9:0] h_counter_in, v_counter_in;
assign VGA_SYNC_N = 1'b0;
assign DrawX = h_counter;
assign DrawY = v_counter;
always_ff @ (posedge VGA_CLK)
begin
if (Reset)
begin
VGA_HS <= 1'b0;
VGA_VS <= 1'b0;
VGA_BLANK_N <= 1'b0;
h_counter <= 10'd0;
v_counter <= 10'd0;
end
else
begin
VGA_HS <= VGA_HS_in;
VGA_VS <= VGA_VS_in;
VGA_BLANK_N <= VGA_BLANK_N_in;
h_counter <= h_counter_in;
v_counter <= v_counter_in;
end
end
always_comb
begin
h_counter_in = h_counter + 10'd1;
v_counter_in = v_counter;
if(h_counter + 10'd1 == H_TOTAL)
begin
h_counter_in = 10'd0;
if(v_counter + 10'd1 == V_TOTAL)
v_counter_in = 10'd0;
else
v_counter_in = v_counter + 10'd1;
end
VGA_HS_in = 1'b1;
if(h_counter_in >= 10'd656 && h_counter_in < 10'd752)
VGA_HS_in = 1'b0;
VGA_VS_in = 1'b1;
if(v_counter_in >= 10'd490 && v_counter_in < 10'd492)
VGA_VS_in = 1'b0;
VGA_BLANK_N_in = 1'b0;
if(h_counter_in < 10'd640 && v_counter_in < 10'd480)
VGA_BLANK_N_in = 1'b1;
end
endmodule | 0 |
3,972 | data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v | 108,010,874 | Verilog-145-234.v | v | 76 | 119 | [] | [] | [] | null | line:74: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:61: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:65: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("VerilogDM-145-234.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:66: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,Verilog_145_234);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:68: Unsupported or unknown PLI call: $monitor\n $monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7); \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:74: Unsupported: Ignoring delay on this delayed statement.\n #2000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,272 | module | module Verilog_145_234;
reg clk;
reg reset;
wire [15:0] pc_out;
wire [15:0] alu_result,reg1,reg2,reg3,reg4,reg7;
VerilogDM_145_234 uut (
.clk(clk),
.reset(reset),
.pc_out(pc_out),
.alu_result(alu_result),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.reg4(reg4),
.reg7(reg7)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
$dumpfile("VerilogDM-145-234.vcd");
$dumpvars(0,Verilog_145_234);
$monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7);
reset = 1;
#100;
reset = 0;
#2000 $finish;
end
endmodule | module Verilog_145_234; |
reg clk;
reg reset;
wire [15:0] pc_out;
wire [15:0] alu_result,reg1,reg2,reg3,reg4,reg7;
VerilogDM_145_234 uut (
.clk(clk),
.reset(reset),
.pc_out(pc_out),
.alu_result(alu_result),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.reg4(reg4),
.reg7(reg7)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
$dumpfile("VerilogDM-145-234.vcd");
$dumpvars(0,Verilog_145_234);
$monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7);
reset = 1;
#100;
reset = 0;
#2000 $finish;
end
endmodule | 1 |
3,990 | data/full_repos/permissive/108139968/Part A/LEDdecoder.v | 108,139,968 | LEDdecoder.v | v | 48 | 42 | [] | [] | [] | [(1, 47)] | null | null | 1: b'%Error: Cannot find file containing module: A,data/full_repos/permissive/108139968\n ... Looked in:\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968.v\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968.sv\n A,data/full_repos/permissive/108139968\n A,data/full_repos/permissive/108139968.v\n A,data/full_repos/permissive/108139968.sv\n obj_dir/A,data/full_repos/permissive/108139968\n obj_dir/A,data/full_repos/permissive/108139968.v\n obj_dir/A,data/full_repos/permissive/108139968.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/108139968/Part\n%Error: Cannot find file containing module: A/LEDdecoder.v\n%Error: Exiting due to 3 error(s)\n' | 2,276 | module | module LEDdecoder (char, LED);
input [3:0]char;
output [6:0]LED;
wire [3:0]char;
reg [6:0]LED;
always @ (char)
begin
case(char)
4'b0000: LED <= 7'b0000001;
4'b0001: LED <= 7'b1001111;
4'b0010: LED <= 7'b0010010;
4'b0011: LED <= 7'b0000110;
4'b0100: LED <= 7'b1001100;
4'b0101: LED <= 7'b0100100;
4'b0110: LED <= 7'b0100000;
4'b0111: LED <= 7'b0001111;
4'b1000: LED <= 7'b0000000;
4'b1001: LED <= 7'b0001100;
4'b1010: LED <= 7'b0001000;
4'b1011: LED <= 7'b1100000;
4'b1100: LED <= 7'b0110001;
4'b1101: LED <= 7'b1000010;
4'b1110: LED <= 7'b0110000;
4'b1111: LED <= 7'b0111000;
default: LED <= 7'b1111111;
endcase
end
endmodule | module LEDdecoder (char, LED); |
input [3:0]char;
output [6:0]LED;
wire [3:0]char;
reg [6:0]LED;
always @ (char)
begin
case(char)
4'b0000: LED <= 7'b0000001;
4'b0001: LED <= 7'b1001111;
4'b0010: LED <= 7'b0010010;
4'b0011: LED <= 7'b0000110;
4'b0100: LED <= 7'b1001100;
4'b0101: LED <= 7'b0100100;
4'b0110: LED <= 7'b0100000;
4'b0111: LED <= 7'b0001111;
4'b1000: LED <= 7'b0000000;
4'b1001: LED <= 7'b0001100;
4'b1010: LED <= 7'b0001000;
4'b1011: LED <= 7'b1100000;
4'b1100: LED <= 7'b0110001;
4'b1101: LED <= 7'b1000010;
4'b1110: LED <= 7'b0110000;
4'b1111: LED <= 7'b0111000;
default: LED <= 7'b1111111;
endcase
end
endmodule | 0 |
3,991 | data/full_repos/permissive/108139968/Part A/LEDdecoder_tb.v | 108,139,968 | LEDdecoder_tb.v | v | 49 | 109 | [] | [] | [] | [(1, 49)] | null | null | 1: b'%Error: Cannot find file containing module: A,data/full_repos/permissive/108139968\n ... Looked in:\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968.v\n data/full_repos/permissive/108139968/Part/A,data/full_repos/permissive/108139968.sv\n A,data/full_repos/permissive/108139968\n A,data/full_repos/permissive/108139968.v\n A,data/full_repos/permissive/108139968.sv\n obj_dir/A,data/full_repos/permissive/108139968\n obj_dir/A,data/full_repos/permissive/108139968.v\n obj_dir/A,data/full_repos/permissive/108139968.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/108139968/Part\n%Error: Cannot find file containing module: A/LEDdecoder_tb.v\n%Error: Exiting due to 3 error(s)\n' | 2,277 | module | module LEDdecoder_tb();
reg [3:0]char;
wire [6:0]LED;
LEDdecoder DUT (
.char (char),
.LED (LED)
);
initial begin
char = 4'b0000;
#32
char = 4'b0001;
#32
char = 4'b0010;
#32
char = 4'b0011;
#32
char = 4'b0100;
#32
char = 4'b0101;
#32
char = 4'b0110;
#32
char = 4'b0111;
#32
char = 4'b1000;
#32
char = 4'b1001;
#32
char = 4'b1010;
#32
char = 4'b1011;
#32
char = 4'b1100;
#32
char = 4'b1101;
#32
char = 4'b1110;
#32
char = 4'b1111;
#32
char = 4'bXXXX;
end
endmodule | module LEDdecoder_tb(); |
reg [3:0]char;
wire [6:0]LED;
LEDdecoder DUT (
.char (char),
.LED (LED)
);
initial begin
char = 4'b0000;
#32
char = 4'b0001;
#32
char = 4'b0010;
#32
char = 4'b0011;
#32
char = 4'b0100;
#32
char = 4'b0101;
#32
char = 4'b0110;
#32
char = 4'b0111;
#32
char = 4'b1000;
#32
char = 4'b1001;
#32
char = 4'b1010;
#32
char = 4'b1011;
#32
char = 4'b1100;
#32
char = 4'b1101;
#32
char = 4'b1110;
#32
char = 4'b1111;
#32
char = 4'bXXXX;
end
endmodule | 0 |
3,992 | data/full_repos/permissive/108160296/hdl/axi_ethernet_bridge.v | 108,160,296 | axi_ethernet_bridge.v | v | 160 | 104 | [] | [] | [] | [(3, 159)] | null | data/verilator_xmls/5227a429-0aa5-4be2-9633-0da86a052e7c.xml | null | 2,278 | module | module axi_ethernet_bridge #
(
parameter integer C_TDATA_WIDTH = 32
)
(
input wire aclk,
input wire aresetn,
output wire [7:0] debug_bus,
output reg s_axis_txd_tready,
input wire [C_TDATA_WIDTH-1 : 0] s_axis_txd_tdata,
input wire [(C_TDATA_WIDTH/8)-1 : 0] s_axis_txd_tkeep,
input wire s_axis_txd_tlast,
input wire s_axis_txd_tvalid,
output wire s_axis_txs_tready,
input wire [C_TDATA_WIDTH-1 : 0] s_axis_txs_tdata,
input wire [(C_TDATA_WIDTH/8)-1 : 0] s_axis_txs_tkeep,
input wire s_axis_txs_tlast,
input wire s_axis_txs_tvalid,
input wire m_axis_txc_tready,
output wire [C_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output wire [(C_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
output reg m_axis_txc_tvalid,
output reg m_axis_txd_tvalid,
output wire [C_TDATA_WIDTH-1 : 0] m_axis_txd_tdata,
output wire [(C_TDATA_WIDTH/8)-1 : 0] m_axis_txd_tkeep,
output wire m_axis_txd_tlast,
input wire m_axis_txd_tready
);
localparam NB_DELAY = 0.2;
localparam A_DELAY = 1;
parameter WAIT_CTRL_READY = 4'h0;
parameter CTRL_WD_0 = 4'h1;
parameter CTRL_WD_1 = 4'h2;
parameter CTRL_WD_2 = 4'h3;
parameter DATA_STREAM_0 = 4'h4;
parameter DATA_STREAM_1 = 4'h5;
reg [3:0] state, state_next;
reg [2:0] counter, counter_next;
wire counter_stop;
reg [C_TDATA_WIDTH+(C_TDATA_WIDTH/8)+1:0] status, status_next;
wire [C_TDATA_WIDTH+(C_TDATA_WIDTH/8)+1:0] status_port;
wire [2:0] counter_plus1;
reg s_txd_tlast_r, s_txd_tlast_next;
assign m_axis_txd_tdata = s_axis_txd_tdata;
assign m_axis_txd_tkeep = s_axis_txd_tkeep;
assign m_axis_txd_tlast = s_axis_txd_tlast;
assign m_axis_txc_tdata = (state == CTRL_WD_0) ? {4'ha,28'h0} : {32'h0};
assign m_axis_txc_tkeep = 4'hf;
assign s_axis_txs_tready = 1'b1;
assign counter_plus1 = counter + 1'b1;
assign counter_stop = ((counter == 3'h3) && m_axis_txc_tready);
assign status_port = {s_axis_txs_tdata,s_axis_txs_tkeep,s_axis_txs_tvalid,s_axis_txs_tlast};
always @(*) begin : TXC
state_next = state;
status_next = status_port;
m_axis_txc_tlast = 1'b0;
m_axis_txc_tvalid = 1'b0;
m_axis_txd_tvalid = 1'b0;
s_axis_txd_tready = 1'b0;
s_txd_tlast_next = s_txd_tlast_r;
case(state)
WAIT_CTRL_READY: begin
s_txd_tlast_next = 1'b0;
if (m_axis_txc_tready) begin
state_next = CTRL_WD_0;
end
end
CTRL_WD_0: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready) begin
state_next = CTRL_WD_1;
end
end
CTRL_WD_1: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready && counter_stop) begin
state_next = CTRL_WD_2;
end
end
CTRL_WD_2: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready) begin
m_axis_txc_tlast = 1'b1;
state_next = DATA_STREAM_0;
end
end
DATA_STREAM_0: begin
m_axis_txd_tvalid = s_axis_txd_tvalid;
s_axis_txd_tready = m_axis_txd_tready;
if (s_axis_txd_tlast && m_axis_txd_tready) begin
state_next = DATA_STREAM_1;
end
end
DATA_STREAM_1: begin
m_axis_txd_tvalid = s_axis_txd_tvalid;
s_axis_txd_tready = m_axis_txd_tready;
if (m_axis_txc_tready) begin
state_next = WAIT_CTRL_READY;
end
end
endcase
end
always @(*) begin: COUNTER
counter_next = counter;
case (state)
CTRL_WD_1: begin
if (m_axis_txc_tready) begin
counter_next = counter_plus1;
end
end
default: begin
counter_next = 3'h0;
end
endcase
end
always @(posedge aclk) begin
if(~aresetn) begin
state <= #NB_DELAY WAIT_CTRL_READY;
counter <= #NB_DELAY 3'b0;
status <= #NB_DELAY 38'b0;
s_txd_tlast_r <= #NB_DELAY 1'b0;
end
else begin
state <= #NB_DELAY state_next;
counter <= #NB_DELAY counter_next;
status <= #NB_DELAY status_next;
s_txd_tlast_r <= #NB_DELAY s_txd_tlast_next;
end
end
endmodule | module axi_ethernet_bridge #
(
parameter integer C_TDATA_WIDTH = 32
)
(
input wire aclk,
input wire aresetn,
output wire [7:0] debug_bus,
output reg s_axis_txd_tready,
input wire [C_TDATA_WIDTH-1 : 0] s_axis_txd_tdata,
input wire [(C_TDATA_WIDTH/8)-1 : 0] s_axis_txd_tkeep,
input wire s_axis_txd_tlast,
input wire s_axis_txd_tvalid,
output wire s_axis_txs_tready,
input wire [C_TDATA_WIDTH-1 : 0] s_axis_txs_tdata,
input wire [(C_TDATA_WIDTH/8)-1 : 0] s_axis_txs_tkeep,
input wire s_axis_txs_tlast,
input wire s_axis_txs_tvalid,
input wire m_axis_txc_tready,
output wire [C_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output wire [(C_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
output reg m_axis_txc_tvalid,
output reg m_axis_txd_tvalid,
output wire [C_TDATA_WIDTH-1 : 0] m_axis_txd_tdata,
output wire [(C_TDATA_WIDTH/8)-1 : 0] m_axis_txd_tkeep,
output wire m_axis_txd_tlast,
input wire m_axis_txd_tready
); |
localparam NB_DELAY = 0.2;
localparam A_DELAY = 1;
parameter WAIT_CTRL_READY = 4'h0;
parameter CTRL_WD_0 = 4'h1;
parameter CTRL_WD_1 = 4'h2;
parameter CTRL_WD_2 = 4'h3;
parameter DATA_STREAM_0 = 4'h4;
parameter DATA_STREAM_1 = 4'h5;
reg [3:0] state, state_next;
reg [2:0] counter, counter_next;
wire counter_stop;
reg [C_TDATA_WIDTH+(C_TDATA_WIDTH/8)+1:0] status, status_next;
wire [C_TDATA_WIDTH+(C_TDATA_WIDTH/8)+1:0] status_port;
wire [2:0] counter_plus1;
reg s_txd_tlast_r, s_txd_tlast_next;
assign m_axis_txd_tdata = s_axis_txd_tdata;
assign m_axis_txd_tkeep = s_axis_txd_tkeep;
assign m_axis_txd_tlast = s_axis_txd_tlast;
assign m_axis_txc_tdata = (state == CTRL_WD_0) ? {4'ha,28'h0} : {32'h0};
assign m_axis_txc_tkeep = 4'hf;
assign s_axis_txs_tready = 1'b1;
assign counter_plus1 = counter + 1'b1;
assign counter_stop = ((counter == 3'h3) && m_axis_txc_tready);
assign status_port = {s_axis_txs_tdata,s_axis_txs_tkeep,s_axis_txs_tvalid,s_axis_txs_tlast};
always @(*) begin : TXC
state_next = state;
status_next = status_port;
m_axis_txc_tlast = 1'b0;
m_axis_txc_tvalid = 1'b0;
m_axis_txd_tvalid = 1'b0;
s_axis_txd_tready = 1'b0;
s_txd_tlast_next = s_txd_tlast_r;
case(state)
WAIT_CTRL_READY: begin
s_txd_tlast_next = 1'b0;
if (m_axis_txc_tready) begin
state_next = CTRL_WD_0;
end
end
CTRL_WD_0: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready) begin
state_next = CTRL_WD_1;
end
end
CTRL_WD_1: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready && counter_stop) begin
state_next = CTRL_WD_2;
end
end
CTRL_WD_2: begin
m_axis_txc_tvalid = 1'b1;
if (m_axis_txc_tready) begin
m_axis_txc_tlast = 1'b1;
state_next = DATA_STREAM_0;
end
end
DATA_STREAM_0: begin
m_axis_txd_tvalid = s_axis_txd_tvalid;
s_axis_txd_tready = m_axis_txd_tready;
if (s_axis_txd_tlast && m_axis_txd_tready) begin
state_next = DATA_STREAM_1;
end
end
DATA_STREAM_1: begin
m_axis_txd_tvalid = s_axis_txd_tvalid;
s_axis_txd_tready = m_axis_txd_tready;
if (m_axis_txc_tready) begin
state_next = WAIT_CTRL_READY;
end
end
endcase
end
always @(*) begin: COUNTER
counter_next = counter;
case (state)
CTRL_WD_1: begin
if (m_axis_txc_tready) begin
counter_next = counter_plus1;
end
end
default: begin
counter_next = 3'h0;
end
endcase
end
always @(posedge aclk) begin
if(~aresetn) begin
state <= #NB_DELAY WAIT_CTRL_READY;
counter <= #NB_DELAY 3'b0;
status <= #NB_DELAY 38'b0;
s_txd_tlast_r <= #NB_DELAY 1'b0;
end
else begin
state <= #NB_DELAY state_next;
counter <= #NB_DELAY counter_next;
status <= #NB_DELAY status_next;
s_txd_tlast_r <= #NB_DELAY s_txd_tlast_next;
end
end
endmodule | 1 |
3,995 | data/full_repos/permissive/108164888/main/code/test_bench.v | 108,164,888 | test_bench.v | v | 55 | 85 | [] | [] | [] | [(25, 53)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108164888/main/code/test_bench.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108164888/main/code/test_bench.v:35: Cannot find file containing module: \'ReductionModulo\'\n ReductionModulo uut (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo\n data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo.v\n data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo.sv\n ReductionModulo\n ReductionModulo.v\n ReductionModulo.sv\n obj_dir/ReductionModulo\n obj_dir/ReductionModulo.v\n obj_dir/ReductionModulo.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,281 | module | module test_bench;
reg [31:0] number;
reg [31:0] m;
wire [31:0] result;
ReductionModulo uut (
.number(number),
.m(m),
.result(result)
);
initial begin
number = 13;
m = 3;
#100;
end
endmodule | module test_bench; |
reg [31:0] number;
reg [31:0] m;
wire [31:0] result;
ReductionModulo uut (
.number(number),
.m(m),
.result(result)
);
initial begin
number = 13;
m = 3;
#100;
end
endmodule | 1 |
3,996 | data/full_repos/permissive/108195533/alu.v | 108,195,533 | alu.v | v | 21 | 102 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/652c5a31-1271-4926-b31d-f19a249177d2.xml | null | 2,282 | module | module alu #(parameter DATA_WIDTH=16, parameter ALU_CON_WIDTH=3)(operandA, operandB, aluCon, result);
input [DATA_WIDTH-1:0] operandA, operandB;
input [ALU_CON_WIDTH-1:0] aluCon;
output reg [DATA_WIDTH-1:0] result;
always @(*) begin
case(aluCon)
'd0: result = operandA + operandB;
'd1: result = operandA - operandB;
'd2: result = operandA & operandB;
'd3: result = operandA | operandB;
'd4: result = operandA ^ operandB;
'd5: result = operandA << operandB;
'd6: result = operandA >> operandB;
'd7: result = operandA >>> operandB;
default: result=operandA;
endcase
end
endmodule | module alu #(parameter DATA_WIDTH=16, parameter ALU_CON_WIDTH=3)(operandA, operandB, aluCon, result); |
input [DATA_WIDTH-1:0] operandA, operandB;
input [ALU_CON_WIDTH-1:0] aluCon;
output reg [DATA_WIDTH-1:0] result;
always @(*) begin
case(aluCon)
'd0: result = operandA + operandB;
'd1: result = operandA - operandB;
'd2: result = operandA & operandB;
'd3: result = operandA | operandB;
'd4: result = operandA ^ operandB;
'd5: result = operandA << operandB;
'd6: result = operandA >> operandB;
'd7: result = operandA >>> operandB;
default: result=operandA;
endcase
end
endmodule | 0 |
3,997 | data/full_repos/permissive/108195533/DE2_TOP.v | 108,195,533 | DE2_TOP.v | v | 214 | 103 | [] | [] | [] | [(1, 213)] | null | null | 1: b"%Error: data/full_repos/permissive/108195533/DE2_TOP.v:57: Cannot find file containing module: 'IF_stage'\nIF_stage #(.MEM_WIDTH(ADDR_WIDTH), .WIDTH(INST_WIDTH), .OFF_WIDTH(OFF_WIDTH))\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/IF_stage\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/IF_stage.v\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/IF_stage.sv\n IF_stage\n IF_stage.v\n IF_stage.sv\n obj_dir/IF_stage\n obj_dir/IF_stage.v\n obj_dir/IF_stage.sv\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:71: Cannot find file containing module: 'ID_stage'\nID_stage #(.ALU_CON_WIDTH(ALU_CON_WIDTH), .WIDTH(INST_WIDTH), .DATA_WIDTH(DATA_WIDTH),\n^~~~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:91: Cannot find file containing module: 'registerFile'\nregisterFile #(.RF_WIDTH(RF_WIDTH), .DATA_WIDTH(DATA_WIDTH))\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:107: Cannot find file containing module: 'opMux'\nopMux opMux1\n^~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:115: Cannot find file containing module: 'opMux'\nopMux opMux2\n^~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:126: Cannot find file containing module: 'EX_stage'\nEX_stage #(.RF_WIDTH(RF_WIDTH), .ALU_CON_WIDTH(ALU_CON_WIDTH), .DATA_WIDTH(DATA_WIDTH),\n^~~~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:149: Cannot find file containing module: 'MEM_stage'\nMEM_stage #(.DATA_WIDTH(DATA_WIDTH), .MID_WIDTH(DATA_WIDTH+RF_WIDTH+2))\n^~~~~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:167: Cannot find file containing module: 'WB_stage'\nWB_stage #(.DATA_WIDTH(DATA_WIDTH), .RF_WIDTH(RF_WIDTH))\n^~~~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:184: Cannot find file containing module: 'hazard'\nhazard hz (\n^~~~~~\n%Error: data/full_repos/permissive/108195533/DE2_TOP.v:197: Cannot find file containing module: 'forwarding'\nforwarding fw (\n^~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n" | 2,283 | module | module mips_top(clk, reset);
input clk, reset;
parameter INST_WIDTH=16;
parameter DATA_WIDTH=16;
parameter OFF_WIDTH=6;
parameter ADDR_WIDTH=8;
parameter ALU_CON_WIDTH=3;
parameter RF_WIDTH=3;
parameter opForwardSelWidth=2;
wire forSel;
wire [ADDR_WIDTH-1:0] addr;
wire [INST_WIDTH-1:0] IFout, IDout, EXout, MEMout, WBout;
wire [ALU_CON_WIDTH-1:0] aluCon;
wire [DATA_WIDTH-1:0] aluResEX, aluResMEM, aluResWB;
wire RFWriteEnID, RFWriteEnEX, RFWriteEnMEM, RFWriteEnWB;
wire [RF_WIDTH-1:0] op1ID, op2ID;
wire [opForwardSelWidth-1:0] opSel1, opSel2;
wire MEMWriteEnID, MEMWriteEnEX;
wire LDSelID, LDSelEX, LDSelMEM;
wire [RF_WIDTH-1:0] writeAddrID, writeAddrEX, writeAddrMEM, writeAddrWB;
wire [DATA_WIDTH-1:0] testRFData;
wire [OFF_WIDTH-1:0] offset;
wire [DATA_WIDTH-1:0] MEMReadData;
wire [DATA_WIDTH-1:0] dataMEM;
wire jump;
assign forSel=1'b0;
wire [DATA_WIDTH-1:0] operandA, operandB, operandBEX;
wire [DATA_WIDTH-1:0] operandAID, operandBID;
wire operandSel;
wire stallFor, stallHaz, stall;
assign stall = forSel?stallFor:stallHaz;
IF_stage #(.MEM_WIDTH(ADDR_WIDTH), .WIDTH(INST_WIDTH), .OFF_WIDTH(OFF_WIDTH))
IF
(.clk(clk),
.stall(stall),
.reset(reset),
.addr(addr),
.instr(IFout),
.jump(jump),
.jumpOffset(offset));
ID_stage #(.ALU_CON_WIDTH(ALU_CON_WIDTH), .WIDTH(INST_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.OFF_WIDTH(OFF_WIDTH), .RF_WIDTH(RF_WIDTH))
ID
(.clk(clk),
.reset(reset),
.instrIn(IFout),
.instrReg(IDout),
.aluCon(aluCon),
.RFWriteEn(RFWriteEnID),
.operandSel(operandSel),
.stall(stall),
.offset(offset),
.jump(jump),
.operandA(operandAID),
.MEMWriteEn(MEMWriteEnID),
.LDSel(LDSelID),
.op1(op1ID),
.op2(op2ID),
.RFWriteAddr(writeAddrID));
registerFile #(.RF_WIDTH(RF_WIDTH), .DATA_WIDTH(DATA_WIDTH))
RF
(.clk(clk),
.reset(reset),
.readAddr1(op1ID),
.readAddr2(op2ID),
.readAddr3(op2ID),
.readData1(operandA),
.readData2(operandB),
.readData3(testRFData),
.writeEn(RFWriteEnWB),
.writeAddr(writeAddrWB),
.writeData(aluResWB));
assign dataMEM = LDSelMEM?MEMReadData:aluResMEM;
opMux opMux1
(.selOp(opSel1),
.dataID(operandA),
.dataEX(aluResEX),
.dataMEM(dataMEM),
.dataWB(aluResWB),
.dataOUT(operandAID));
opMux opMux2
(.selOp(opSel2),
.dataID(operandB),
.dataEX(aluResEX),
.dataMEM(dataMEM),
.dataWB(aluResWB),
.dataOUT(operandBID));
EX_stage #(.RF_WIDTH(RF_WIDTH), .ALU_CON_WIDTH(ALU_CON_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.MID_WIDTH(RF_WIDTH+3), .OFF_WIDTH(OFF_WIDTH))
EX
(.clk(clk),
.reset(reset),
.instrIn(IDout),
.instrOut(EXout),
.aluCon(aluCon),
.aluRes(aluResEX),
.midSignalIn({RFWriteEnID, MEMWriteEnID, LDSelID, writeAddrID}),
.midSignalOut({RFWriteEnEX, MEMWriteEnEX, LDSelEX, writeAddrEX}),
.operandA(operandAID),
.operandB(operandBID),
.operandBReg(operandBEX),
.operandSel(operandSel),
.offset(offset));
MEM_stage #(.DATA_WIDTH(DATA_WIDTH), .MID_WIDTH(DATA_WIDTH+RF_WIDTH+2))
MEM
(.clk(clk),
.reset(reset),
.instrIn(EXout),
.instrOut(MEMout),
.midSignalIn({RFWriteEnEX, aluResEX[DATA_WIDTH-1:0], LDSelEX, writeAddrEX}),
.midSignalOut({RFWriteEnMEM, aluResMEM[DATA_WIDTH-1:0], LDSelMEM, writeAddrMEM}),
.addr(aluResEX),
.readData(MEMReadData),
.writeData(operandBEX),
.writeEn(MEMWriteEnEX));
WB_stage #(.DATA_WIDTH(DATA_WIDTH), .RF_WIDTH(RF_WIDTH))
WB
(.clk(clk),
.reset(reset),
.instrIn(MEMout),
.instrOut(WBout),
.RFWriteEnIn(RFWriteEnMEM),
.RFWriteEnOut(RFWriteEnWB),
.aluResIn(aluResMEM),
.aluResOut(aluResWB),
.writeAddrIn(writeAddrMEM),
.writeAddrOut(writeAddrWB),
.LDSel(LDSelMEM),
.MEMReadData(MEMReadData));
hazard hz (
.op1(op1ID),
.op2(op2ID),
.rfWriteAddrMem(writeAddrMEM),
.rfWriteAddrEx(writeAddrEX),
.rfWriteAddrWb(writeAddrWB),
.memWriteEn(RFWriteEnMEM),
.exWriteEn(RFWriteEnEX),
.wbWriteEn(RFWriteEnWB),
.stall(stallHaz)
);
forwarding fw (
.en(forSel),
.op1(op1ID),
.op2(op2ID),
.rfWriteAddrMem(writeAddrMEM),
.rfWriteAddrEx(writeAddrEX),
.rfWriteAddrWb(writeAddrWB),
.memWriteEn(RFWriteEnMEM),
.exWriteEn(RFWriteEnEX),
.wbWriteEn(RFWriteEnWB),
.stall(stallFor),
.selOp1(opSel1),
.selOp2(opSel2),
.isLoadInEx(LDSelEX)
);
endmodule | module mips_top(clk, reset); |
input clk, reset;
parameter INST_WIDTH=16;
parameter DATA_WIDTH=16;
parameter OFF_WIDTH=6;
parameter ADDR_WIDTH=8;
parameter ALU_CON_WIDTH=3;
parameter RF_WIDTH=3;
parameter opForwardSelWidth=2;
wire forSel;
wire [ADDR_WIDTH-1:0] addr;
wire [INST_WIDTH-1:0] IFout, IDout, EXout, MEMout, WBout;
wire [ALU_CON_WIDTH-1:0] aluCon;
wire [DATA_WIDTH-1:0] aluResEX, aluResMEM, aluResWB;
wire RFWriteEnID, RFWriteEnEX, RFWriteEnMEM, RFWriteEnWB;
wire [RF_WIDTH-1:0] op1ID, op2ID;
wire [opForwardSelWidth-1:0] opSel1, opSel2;
wire MEMWriteEnID, MEMWriteEnEX;
wire LDSelID, LDSelEX, LDSelMEM;
wire [RF_WIDTH-1:0] writeAddrID, writeAddrEX, writeAddrMEM, writeAddrWB;
wire [DATA_WIDTH-1:0] testRFData;
wire [OFF_WIDTH-1:0] offset;
wire [DATA_WIDTH-1:0] MEMReadData;
wire [DATA_WIDTH-1:0] dataMEM;
wire jump;
assign forSel=1'b0;
wire [DATA_WIDTH-1:0] operandA, operandB, operandBEX;
wire [DATA_WIDTH-1:0] operandAID, operandBID;
wire operandSel;
wire stallFor, stallHaz, stall;
assign stall = forSel?stallFor:stallHaz;
IF_stage #(.MEM_WIDTH(ADDR_WIDTH), .WIDTH(INST_WIDTH), .OFF_WIDTH(OFF_WIDTH))
IF
(.clk(clk),
.stall(stall),
.reset(reset),
.addr(addr),
.instr(IFout),
.jump(jump),
.jumpOffset(offset));
ID_stage #(.ALU_CON_WIDTH(ALU_CON_WIDTH), .WIDTH(INST_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.OFF_WIDTH(OFF_WIDTH), .RF_WIDTH(RF_WIDTH))
ID
(.clk(clk),
.reset(reset),
.instrIn(IFout),
.instrReg(IDout),
.aluCon(aluCon),
.RFWriteEn(RFWriteEnID),
.operandSel(operandSel),
.stall(stall),
.offset(offset),
.jump(jump),
.operandA(operandAID),
.MEMWriteEn(MEMWriteEnID),
.LDSel(LDSelID),
.op1(op1ID),
.op2(op2ID),
.RFWriteAddr(writeAddrID));
registerFile #(.RF_WIDTH(RF_WIDTH), .DATA_WIDTH(DATA_WIDTH))
RF
(.clk(clk),
.reset(reset),
.readAddr1(op1ID),
.readAddr2(op2ID),
.readAddr3(op2ID),
.readData1(operandA),
.readData2(operandB),
.readData3(testRFData),
.writeEn(RFWriteEnWB),
.writeAddr(writeAddrWB),
.writeData(aluResWB));
assign dataMEM = LDSelMEM?MEMReadData:aluResMEM;
opMux opMux1
(.selOp(opSel1),
.dataID(operandA),
.dataEX(aluResEX),
.dataMEM(dataMEM),
.dataWB(aluResWB),
.dataOUT(operandAID));
opMux opMux2
(.selOp(opSel2),
.dataID(operandB),
.dataEX(aluResEX),
.dataMEM(dataMEM),
.dataWB(aluResWB),
.dataOUT(operandBID));
EX_stage #(.RF_WIDTH(RF_WIDTH), .ALU_CON_WIDTH(ALU_CON_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.MID_WIDTH(RF_WIDTH+3), .OFF_WIDTH(OFF_WIDTH))
EX
(.clk(clk),
.reset(reset),
.instrIn(IDout),
.instrOut(EXout),
.aluCon(aluCon),
.aluRes(aluResEX),
.midSignalIn({RFWriteEnID, MEMWriteEnID, LDSelID, writeAddrID}),
.midSignalOut({RFWriteEnEX, MEMWriteEnEX, LDSelEX, writeAddrEX}),
.operandA(operandAID),
.operandB(operandBID),
.operandBReg(operandBEX),
.operandSel(operandSel),
.offset(offset));
MEM_stage #(.DATA_WIDTH(DATA_WIDTH), .MID_WIDTH(DATA_WIDTH+RF_WIDTH+2))
MEM
(.clk(clk),
.reset(reset),
.instrIn(EXout),
.instrOut(MEMout),
.midSignalIn({RFWriteEnEX, aluResEX[DATA_WIDTH-1:0], LDSelEX, writeAddrEX}),
.midSignalOut({RFWriteEnMEM, aluResMEM[DATA_WIDTH-1:0], LDSelMEM, writeAddrMEM}),
.addr(aluResEX),
.readData(MEMReadData),
.writeData(operandBEX),
.writeEn(MEMWriteEnEX));
WB_stage #(.DATA_WIDTH(DATA_WIDTH), .RF_WIDTH(RF_WIDTH))
WB
(.clk(clk),
.reset(reset),
.instrIn(MEMout),
.instrOut(WBout),
.RFWriteEnIn(RFWriteEnMEM),
.RFWriteEnOut(RFWriteEnWB),
.aluResIn(aluResMEM),
.aluResOut(aluResWB),
.writeAddrIn(writeAddrMEM),
.writeAddrOut(writeAddrWB),
.LDSel(LDSelMEM),
.MEMReadData(MEMReadData));
hazard hz (
.op1(op1ID),
.op2(op2ID),
.rfWriteAddrMem(writeAddrMEM),
.rfWriteAddrEx(writeAddrEX),
.rfWriteAddrWb(writeAddrWB),
.memWriteEn(RFWriteEnMEM),
.exWriteEn(RFWriteEnEX),
.wbWriteEn(RFWriteEnWB),
.stall(stallHaz)
);
forwarding fw (
.en(forSel),
.op1(op1ID),
.op2(op2ID),
.rfWriteAddrMem(writeAddrMEM),
.rfWriteAddrEx(writeAddrEX),
.rfWriteAddrWb(writeAddrWB),
.memWriteEn(RFWriteEnMEM),
.exWriteEn(RFWriteEnEX),
.wbWriteEn(RFWriteEnWB),
.stall(stallFor),
.selOp1(opSel1),
.selOp2(opSel2),
.isLoadInEx(LDSelEX)
);
endmodule | 0 |
3,998 | data/full_repos/permissive/108195533/EX_stage.v | 108,195,533 | EX_stage.v | v | 64 | 143 | [] | [] | [] | [(1, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/108195533/EX_stage.v:48: Cannot find file containing module: 'signExtend'\n signExtend SE(offsetReg, offSS);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend.v\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend.sv\n signExtend\n signExtend.v\n signExtend.sv\n obj_dir/signExtend\n obj_dir/signExtend.v\n obj_dir/signExtend.sv\n%Error: data/full_repos/permissive/108195533/EX_stage.v:50: Cannot find file containing module: 'alu'\n alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));\n ^~~\n%Error: Exiting due to 2 error(s)\n" | 2,284 | module | module EX_stage
#(parameter RF_WIDTH=3, parameter WIDTH=16, parameter ALU_CON_WIDTH=3, parameter DATA_WIDTH=16, parameter MID_WIDTH=1, parameter OFF_WIDTH=6)
(clk, reset, instrIn, instrOut, aluCon, aluRes, midSignalIn, midSignalOut, operandA, operandB, operandBReg, operandSel, offset);
input clk, reset;
input [WIDTH-1:0] instrIn;
input [ALU_CON_WIDTH-1:0] aluCon;
input [OFF_WIDTH-1:0] offset;
reg [OFF_WIDTH-1:0] offsetReg;
input operandSel;
reg operandSelReg;
always @(posedge clk)
operandSelReg <= operandSel;
output reg[WIDTH-1:0] instrOut;
output [DATA_WIDTH-1:0] aluRes;
input [MID_WIDTH-1:0] midSignalIn;
output reg [MID_WIDTH-1:0] midSignalOut;
always @(posedge clk) begin
if(reset)
midSignalOut <= {MID_WIDTH{1'b0}};
else
midSignalOut <= midSignalIn;
end
reg [ALU_CON_WIDTH-1:0] aluConReg;
input [DATA_WIDTH-1:0] operandA, operandB;
reg [DATA_WIDTH-1:0] operandAReg;
output reg [DATA_WIDTH-1:0] operandBReg;
always @(posedge clk) begin
operandAReg <= operandA;
operandBReg <= operandB;
end
always @(posedge clk)
aluConReg<=aluCon;
wire [DATA_WIDTH-1:0] operandBSelected;
wire [DATA_WIDTH-1:0] offSS;
signExtend SE(offsetReg, offSS);
assign operandBSelected = operandSelReg?offSS:operandBReg;
alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
always@(posedge clk)
offsetReg <= offset;
endmodule | module EX_stage
#(parameter RF_WIDTH=3, parameter WIDTH=16, parameter ALU_CON_WIDTH=3, parameter DATA_WIDTH=16, parameter MID_WIDTH=1, parameter OFF_WIDTH=6)
(clk, reset, instrIn, instrOut, aluCon, aluRes, midSignalIn, midSignalOut, operandA, operandB, operandBReg, operandSel, offset); |
input clk, reset;
input [WIDTH-1:0] instrIn;
input [ALU_CON_WIDTH-1:0] aluCon;
input [OFF_WIDTH-1:0] offset;
reg [OFF_WIDTH-1:0] offsetReg;
input operandSel;
reg operandSelReg;
always @(posedge clk)
operandSelReg <= operandSel;
output reg[WIDTH-1:0] instrOut;
output [DATA_WIDTH-1:0] aluRes;
input [MID_WIDTH-1:0] midSignalIn;
output reg [MID_WIDTH-1:0] midSignalOut;
always @(posedge clk) begin
if(reset)
midSignalOut <= {MID_WIDTH{1'b0}};
else
midSignalOut <= midSignalIn;
end
reg [ALU_CON_WIDTH-1:0] aluConReg;
input [DATA_WIDTH-1:0] operandA, operandB;
reg [DATA_WIDTH-1:0] operandAReg;
output reg [DATA_WIDTH-1:0] operandBReg;
always @(posedge clk) begin
operandAReg <= operandA;
operandBReg <= operandB;
end
always @(posedge clk)
aluConReg<=aluCon;
wire [DATA_WIDTH-1:0] operandBSelected;
wire [DATA_WIDTH-1:0] offSS;
signExtend SE(offsetReg, offSS);
assign operandBSelected = operandSelReg?offSS:operandBReg;
alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
always@(posedge clk)
offsetReg <= offset;
endmodule | 0 |
3,999 | data/full_repos/permissive/108195533/forwarding.v | 108,195,533 | forwarding.v | v | 49 | 124 | [] | [] | [] | [(1, 48)] | null | data/verilator_xmls/6c92f78c-1f7c-4114-861b-d2b3993d5576.xml | null | 2,285 | module | module forwarding#(parameter rfWidth= 3, parameter opForwardSelWidth=2)
(en, op1, op2, rfWriteAddrEx, rfWriteAddrMem, rfWriteAddrWb,
exWriteEn, memWriteEn, wbWriteEn, stall, selOp1, selOp2, isLoadInEx);
parameter IDSEL=2'd0;
parameter EXSEL=2'd1;
parameter MEMSEL=2'd2;
parameter WBSEL=2'd3;
input en;
input isLoadInEx;
input [rfWidth-1:0]op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb;
input exWriteEn, memWriteEn, wbWriteEn;
output reg stall;
output reg[opForwardSelWidth-1:0] selOp1;
output reg[opForwardSelWidth-1:0] selOp2;
always @(*) begin
stall = 1'b0;
if(isLoadInEx && (((op1==rfWriteAddrEx && exWriteEn) && op1!=3'b0) || ((op2==rfWriteAddrEx && exWriteEn) && op2!=3'b0)) )
stall = 1'b1;
end
always @(*) begin
selOp1 = IDSEL;
if(en && op1!=3'b0) begin
if(op1==rfWriteAddrEx && exWriteEn)
selOp1 = EXSEL;
else if(op1==rfWriteAddrMem && memWriteEn)
selOp1 = MEMSEL;
else if(op1== rfWriteAddrWb && wbWriteEn)
selOp1 = WBSEL;
end
end
always @(*) begin
selOp2 = IDSEL;
if(en && op2!=3'b0) begin
if(op2==rfWriteAddrEx && exWriteEn)
selOp2 = EXSEL;
else if(op2==rfWriteAddrMem && memWriteEn)
selOp2 = MEMSEL;
else if(op2== rfWriteAddrWb && wbWriteEn)
selOp2 = WBSEL;
end
end
endmodule | module forwarding#(parameter rfWidth= 3, parameter opForwardSelWidth=2)
(en, op1, op2, rfWriteAddrEx, rfWriteAddrMem, rfWriteAddrWb,
exWriteEn, memWriteEn, wbWriteEn, stall, selOp1, selOp2, isLoadInEx); |
parameter IDSEL=2'd0;
parameter EXSEL=2'd1;
parameter MEMSEL=2'd2;
parameter WBSEL=2'd3;
input en;
input isLoadInEx;
input [rfWidth-1:0]op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb;
input exWriteEn, memWriteEn, wbWriteEn;
output reg stall;
output reg[opForwardSelWidth-1:0] selOp1;
output reg[opForwardSelWidth-1:0] selOp2;
always @(*) begin
stall = 1'b0;
if(isLoadInEx && (((op1==rfWriteAddrEx && exWriteEn) && op1!=3'b0) || ((op2==rfWriteAddrEx && exWriteEn) && op2!=3'b0)) )
stall = 1'b1;
end
always @(*) begin
selOp1 = IDSEL;
if(en && op1!=3'b0) begin
if(op1==rfWriteAddrEx && exWriteEn)
selOp1 = EXSEL;
else if(op1==rfWriteAddrMem && memWriteEn)
selOp1 = MEMSEL;
else if(op1== rfWriteAddrWb && wbWriteEn)
selOp1 = WBSEL;
end
end
always @(*) begin
selOp2 = IDSEL;
if(en && op2!=3'b0) begin
if(op2==rfWriteAddrEx && exWriteEn)
selOp2 = EXSEL;
else if(op2==rfWriteAddrMem && memWriteEn)
selOp2 = MEMSEL;
else if(op2== rfWriteAddrWb && wbWriteEn)
selOp2 = WBSEL;
end
end
endmodule | 0 |
4,000 | data/full_repos/permissive/108195533/hazard.v | 108,195,533 | hazard.v | v | 14 | 134 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/2962f42e-68bb-41cd-8292-e50e42140f85.xml | null | 2,286 | module | module hazard#(parameter rfWidth= 3)(op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb,exWriteEn,memWriteEn,wbWriteEn,stall);
input [rfWidth-1:0]op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb;
input exWriteEn, memWriteEn, wbWriteEn;
output reg stall;
always @(*)
begin
stall=0;
if((((op1==rfWriteAddrEx && exWriteEn) || (op1==rfWriteAddrMem && memWriteEn) || (op1== rfWriteAddrWb && wbWriteEn)) && op1!=3'b0) ||
(((op2==rfWriteAddrEx && exWriteEn) || (op2==rfWriteAddrMem && memWriteEn) || (op2== rfWriteAddrWb && wbWriteEn)) && op2!=3'b0))
stall=1;
end
endmodule | module hazard#(parameter rfWidth= 3)(op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb,exWriteEn,memWriteEn,wbWriteEn,stall); |
input [rfWidth-1:0]op1,op2,rfWriteAddrEx,rfWriteAddrMem,rfWriteAddrWb;
input exWriteEn, memWriteEn, wbWriteEn;
output reg stall;
always @(*)
begin
stall=0;
if((((op1==rfWriteAddrEx && exWriteEn) || (op1==rfWriteAddrMem && memWriteEn) || (op1== rfWriteAddrWb && wbWriteEn)) && op1!=3'b0) ||
(((op2==rfWriteAddrEx && exWriteEn) || (op2==rfWriteAddrMem && memWriteEn) || (op2== rfWriteAddrWb && wbWriteEn)) && op2!=3'b0))
stall=1;
end
endmodule | 0 |
4,001 | data/full_repos/permissive/108195533/ID_stage.v | 108,195,533 | ID_stage.v | v | 89 | 138 | [] | [] | [] | null | line:2: before: "," | null | 1: b"%Error: data/full_repos/permissive/108195533/ID_stage.v:2: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'WIDTH'\n : ... In instance ID_stage\n #(parameter ALU_CON_WIDTH=3, parameter WIDTH, parameter DATA_WIDTH=16, parameter OFF_WIDTH=6, parameter RF_WIDTH=3)\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 2,287 | module | module ID_stage
#(parameter ALU_CON_WIDTH=3, parameter WIDTH, parameter DATA_WIDTH=16, parameter OFF_WIDTH=6, parameter RF_WIDTH=3)
(clk, reset, stall, instrIn, instrReg, aluCon, RFWriteEn, MEMWriteEn, operandSel, offset, jump, operandA, LDSel, op1, op2, RFWriteAddr);
input clk, reset;
input stall;
input [WIDTH-1:0] instrIn;
output reg[WIDTH-1:0] instrReg;
output reg[ALU_CON_WIDTH-1:0] aluCon;
output reg RFWriteEn;
output reg MEMWriteEn;
output [RF_WIDTH-1:0] RFWriteAddr;
output reg jump;
reg jumpPrev;
output [OFF_WIDTH-1:0] offset;
input [DATA_WIDTH-1:0] operandA;
wire [3:0] opcode;
assign offset = instrReg[5:0];
assign RFWriteAddr = instrReg[11:9];
always @(*) begin
jump = 1'b0;
if(opcode==4'b1100 && operandA==16'b0 && !jumpPrev && !stall)
jump = 1'b1;
end
always @(posedge clk) begin
if(reset)
jumpPrev <= 1'b0;
else if(!stall)
jumpPrev <= jump;
end
output LDSel;
assign LDSel=(opcode=='d10);
output operandSel;
assign operandSel=(opcode=='d9 || opcode=='d10 || opcode=='d11);
output [RF_WIDTH-1:0] op1, op2;
assign op1 = instrReg[08:06];
assign op2 = (opcode=='d11)?instrReg[11:09]:instrReg[05:03];
assign opcode = instrReg[15:12];
always@(posedge clk) begin
if(reset)
instrReg <= {WIDTH{1'b0}};
else begin
if(!stall)
instrReg <= instrIn;
end
end
always@(*) begin
case(opcode)
'd0: aluCon='d0;
'd1: aluCon='d0;
'd2: aluCon='d1;
'd3: aluCon='d2;
'd4: aluCon='d3;
'd5: aluCon='d4;
'd6: aluCon='d5;
'd7: aluCon='d6;
'd8: aluCon='d7;
'd9: aluCon='d0;
'd10: aluCon='d0;
'd11: aluCon='d0;
default: aluCon='d0;
endcase
end
always@(*) begin
RFWriteEn = 1'b0;
if(((4'd1<=opcode && opcode<=4'd9) || opcode==4'd6 || opcode=='d10) && !stall && !jumpPrev)
RFWriteEn = 1'b1;
end
always @(*) begin
MEMWriteEn = 1'b0;
if(opcode=='d11 && !stall && !jumpPrev)
MEMWriteEn=1'b1;
end
endmodule | module ID_stage
#(parameter ALU_CON_WIDTH=3, parameter WIDTH, parameter DATA_WIDTH=16, parameter OFF_WIDTH=6, parameter RF_WIDTH=3)
(clk, reset, stall, instrIn, instrReg, aluCon, RFWriteEn, MEMWriteEn, operandSel, offset, jump, operandA, LDSel, op1, op2, RFWriteAddr); |
input clk, reset;
input stall;
input [WIDTH-1:0] instrIn;
output reg[WIDTH-1:0] instrReg;
output reg[ALU_CON_WIDTH-1:0] aluCon;
output reg RFWriteEn;
output reg MEMWriteEn;
output [RF_WIDTH-1:0] RFWriteAddr;
output reg jump;
reg jumpPrev;
output [OFF_WIDTH-1:0] offset;
input [DATA_WIDTH-1:0] operandA;
wire [3:0] opcode;
assign offset = instrReg[5:0];
assign RFWriteAddr = instrReg[11:9];
always @(*) begin
jump = 1'b0;
if(opcode==4'b1100 && operandA==16'b0 && !jumpPrev && !stall)
jump = 1'b1;
end
always @(posedge clk) begin
if(reset)
jumpPrev <= 1'b0;
else if(!stall)
jumpPrev <= jump;
end
output LDSel;
assign LDSel=(opcode=='d10);
output operandSel;
assign operandSel=(opcode=='d9 || opcode=='d10 || opcode=='d11);
output [RF_WIDTH-1:0] op1, op2;
assign op1 = instrReg[08:06];
assign op2 = (opcode=='d11)?instrReg[11:09]:instrReg[05:03];
assign opcode = instrReg[15:12];
always@(posedge clk) begin
if(reset)
instrReg <= {WIDTH{1'b0}};
else begin
if(!stall)
instrReg <= instrIn;
end
end
always@(*) begin
case(opcode)
'd0: aluCon='d0;
'd1: aluCon='d0;
'd2: aluCon='d1;
'd3: aluCon='d2;
'd4: aluCon='d3;
'd5: aluCon='d4;
'd6: aluCon='d5;
'd7: aluCon='d6;
'd8: aluCon='d7;
'd9: aluCon='d0;
'd10: aluCon='d0;
'd11: aluCon='d0;
default: aluCon='d0;
endcase
end
always@(*) begin
RFWriteEn = 1'b0;
if(((4'd1<=opcode && opcode<=4'd9) || opcode==4'd6 || opcode=='d10) && !stall && !jumpPrev)
RFWriteEn = 1'b1;
end
always @(*) begin
MEMWriteEn = 1'b0;
if(opcode=='d11 && !stall && !jumpPrev)
MEMWriteEn=1'b1;
end
endmodule | 0 |
4,002 | data/full_repos/permissive/108195533/IF_stage.v | 108,195,533 | IF_stage.v | v | 22 | 131 | [] | [] | [] | null | line:1: before: "," | null | 1: b"%Error: data/full_repos/permissive/108195533/IF_stage.v:1: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'WIDTH'\n : ... In instance IF_stage\nmodule IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset);\n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 2,288 | module | module IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset);
input clk, reset, jump, stall;
output [WIDTH-1:0] instr;
wire [WIDTH-1:0] instrRead;
output [MEM_WIDTH-1:0] addr;
input [OFF_WIDTH-1:0] jumpOffset;
wire [MEM_WIDTH-1:0] jumpAddress;
signExtend SE(.offset(jumpOffset), .fixed(jumpAddress));
PC pcIF(.clk(clk), .reset(reset), .PCOut(addr), .PCIn(jumpAddress), .load(jump), .en(~stall));
instrMem memIF(.addr(addr), .instr(instrRead));
assign instr = instrRead;
endmodule | module IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset); |
input clk, reset, jump, stall;
output [WIDTH-1:0] instr;
wire [WIDTH-1:0] instrRead;
output [MEM_WIDTH-1:0] addr;
input [OFF_WIDTH-1:0] jumpOffset;
wire [MEM_WIDTH-1:0] jumpAddress;
signExtend SE(.offset(jumpOffset), .fixed(jumpAddress));
PC pcIF(.clk(clk), .reset(reset), .PCOut(addr), .PCIn(jumpAddress), .load(jump), .en(~stall));
instrMem memIF(.addr(addr), .instr(instrRead));
assign instr = instrRead;
endmodule | 0 |
4,003 | data/full_repos/permissive/108195533/instrMem.v | 108,195,533 | instrMem.v | v | 15 | 74 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/db1ea4b1-8875-41c0-a847-b0872dc13e6f.xml | null | 2,289 | module | module instrMem#(parameter MEM_WIDTH=8, parameter WIDTH=16)(addr, instr);
input [MEM_WIDTH-1:0] addr;
output reg[WIDTH-1:0] instr;
reg [WIDTH-1:0] memory [2**MEM_WIDTH-1:0];
initial $readmemb("instructions", memory);
always@(*)
begin
instr = memory[addr];
end
endmodule | module instrMem#(parameter MEM_WIDTH=8, parameter WIDTH=16)(addr, instr); |
input [MEM_WIDTH-1:0] addr;
output reg[WIDTH-1:0] instr;
reg [WIDTH-1:0] memory [2**MEM_WIDTH-1:0];
initial $readmemb("instructions", memory);
always@(*)
begin
instr = memory[addr];
end
endmodule | 0 |
4,004 | data/full_repos/permissive/108195533/memory.v | 108,195,533 | memory.v | v | 28 | 112 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/7ec663c0-c5e2-4071-838f-a0539ed41141.xml | null | 2,290 | module | module memory#(parameter MEM_WIDTH=8, parameter DATA_WIDTH=16)(clk, reset, addr, readData, writeData, writeEn);
input clk, reset;
input writeEn;
input [MEM_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] readData;
input [DATA_WIDTH-1:0] writeData;
reg [DATA_WIDTH-1:0] mem [0:2**MEM_WIDTH-1];
assign readData = mem[addr];
integer i;
always @(posedge clk) begin
if(reset) begin
for (i=0; i<2**MEM_WIDTH; i=i+1)
mem[i] <= {DATA_WIDTH{1'b0}};
end
else if(writeEn==1) begin
mem[addr] <= writeData;
end
end
endmodule | module memory#(parameter MEM_WIDTH=8, parameter DATA_WIDTH=16)(clk, reset, addr, readData, writeData, writeEn); |
input clk, reset;
input writeEn;
input [MEM_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] readData;
input [DATA_WIDTH-1:0] writeData;
reg [DATA_WIDTH-1:0] mem [0:2**MEM_WIDTH-1];
assign readData = mem[addr];
integer i;
always @(posedge clk) begin
if(reset) begin
for (i=0; i<2**MEM_WIDTH; i=i+1)
mem[i] <= {DATA_WIDTH{1'b0}};
end
else if(writeEn==1) begin
mem[addr] <= writeData;
end
end
endmodule | 0 |
4,005 | data/full_repos/permissive/108195533/MEM_stage.v | 108,195,533 | MEM_stage.v | v | 56 | 138 | [] | [] | [] | [(1, 54)] | null | null | 1: b"%Error: data/full_repos/permissive/108195533/MEM_stage.v:52: Cannot find file containing module: 'memory'\n memory mem(.clk(clk), .reset(reset), .addr(addrReg[MEM_WIDTH-1:0]), .readData(readData), .writeData(writeDataReg), .writeEn(writeEnReg));\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/memory\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/memory.v\n data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/memory.sv\n memory\n memory.v\n memory.sv\n obj_dir/memory\n obj_dir/memory.v\n obj_dir/memory.sv\n%Error: Exiting due to 1 error(s)\n" | 2,291 | module | module MEM_stage
#(parameter WIDTH=16, parameter DATA_WIDTH=16, parameter MID_WIDTH=1)
(clk, reset, instrIn, instrOut, midSignalIn, midSignalOut, addr, writeData, readData, writeEn);
parameter MEM_WIDTH = 8;
input clk, reset;
input [WIDTH-1:0] instrIn;
output reg[WIDTH-1:0] instrOut;
input [DATA_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] addrReg;
output [DATA_WIDTH-1:0] readData;
input [DATA_WIDTH-1:0] writeData;
input writeEn;
reg [DATA_WIDTH-1:0] writeDataReg;
reg writeEnReg;
always @(posedge clk) begin
writeDataReg <= writeData;
end
input [MID_WIDTH-1:0] midSignalIn;
output reg [MID_WIDTH-1:0] midSignalOut;
always @(posedge clk) begin
if(reset)
writeEnReg <= 1'b0;
else
writeEnReg <= writeEn;
end
always @(posedge clk) begin
if(reset)
midSignalOut <= {MID_WIDTH{1'b0}};
else
midSignalOut <= midSignalIn;
end
always@(posedge clk) begin
addrReg <= addr;
end
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
memory mem(.clk(clk), .reset(reset), .addr(addrReg[MEM_WIDTH-1:0]), .readData(readData), .writeData(writeDataReg), .writeEn(writeEnReg));
endmodule | module MEM_stage
#(parameter WIDTH=16, parameter DATA_WIDTH=16, parameter MID_WIDTH=1)
(clk, reset, instrIn, instrOut, midSignalIn, midSignalOut, addr, writeData, readData, writeEn); |
parameter MEM_WIDTH = 8;
input clk, reset;
input [WIDTH-1:0] instrIn;
output reg[WIDTH-1:0] instrOut;
input [DATA_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] addrReg;
output [DATA_WIDTH-1:0] readData;
input [DATA_WIDTH-1:0] writeData;
input writeEn;
reg [DATA_WIDTH-1:0] writeDataReg;
reg writeEnReg;
always @(posedge clk) begin
writeDataReg <= writeData;
end
input [MID_WIDTH-1:0] midSignalIn;
output reg [MID_WIDTH-1:0] midSignalOut;
always @(posedge clk) begin
if(reset)
writeEnReg <= 1'b0;
else
writeEnReg <= writeEn;
end
always @(posedge clk) begin
if(reset)
midSignalOut <= {MID_WIDTH{1'b0}};
else
midSignalOut <= midSignalIn;
end
always@(posedge clk) begin
addrReg <= addr;
end
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
memory mem(.clk(clk), .reset(reset), .addr(addrReg[MEM_WIDTH-1:0]), .readData(readData), .writeData(writeDataReg), .writeEn(writeEnReg));
endmodule | 0 |
4,006 | data/full_repos/permissive/108195533/opMux.v | 108,195,533 | opMux.v | v | 25 | 81 | [] | [] | [] | [(1, 24)] | null | data/verilator_xmls/a92fd3c9-f58b-4433-a11b-ba3f6e2d403d.xml | null | 2,292 | module | module opMux
#(parameter rfWidth= 3, parameter opForwardSelWidth=2, parameter DATA_WIDTH=16)
(selOp, dataID, dataEX, dataMEM, dataWB, dataOUT);
parameter IDSEL=2'd0;
parameter EXSEL=2'd1;
parameter MEMSEL=2'd2;
parameter WBSEL=2'd3;
input [DATA_WIDTH-1:0] dataID, dataEX, dataMEM, dataWB;
input [opForwardSelWidth-1:0] selOp;
output reg[DATA_WIDTH-1:0] dataOUT;
always @(*) begin
case(selOp)
IDSEL: dataOUT=dataID;
EXSEL: dataOUT=dataEX;
MEMSEL: dataOUT=dataMEM;
WBSEL: dataOUT=dataWB;
default: dataOUT=dataID;
endcase
end
endmodule | module opMux
#(parameter rfWidth= 3, parameter opForwardSelWidth=2, parameter DATA_WIDTH=16)
(selOp, dataID, dataEX, dataMEM, dataWB, dataOUT); |
parameter IDSEL=2'd0;
parameter EXSEL=2'd1;
parameter MEMSEL=2'd2;
parameter WBSEL=2'd3;
input [DATA_WIDTH-1:0] dataID, dataEX, dataMEM, dataWB;
input [opForwardSelWidth-1:0] selOp;
output reg[DATA_WIDTH-1:0] dataOUT;
always @(*) begin
case(selOp)
IDSEL: dataOUT=dataID;
EXSEL: dataOUT=dataEX;
MEMSEL: dataOUT=dataMEM;
WBSEL: dataOUT=dataWB;
default: dataOUT=dataID;
endcase
end
endmodule | 0 |
4,007 | data/full_repos/permissive/108195533/PC.v | 108,195,533 | PC.v | v | 22 | 70 | [] | [] | [] | [(1, 21)] | null | data/verilator_xmls/6242881e-fbe4-4c53-9b45-9de4e0dc3a04.xml | null | 2,293 | module | module PC#(parameter MEM_WIDTH=8)(clk, reset, PCOut, PCIn, load, en);
input clk, reset, load, en;
input [MEM_WIDTH-1:0] PCIn;
output [MEM_WIDTH-1:0] PCOut;
reg [MEM_WIDTH-1:0] count;
assign PCOut = count;
always@(posedge clk)
begin
if(reset)
count <= {MEM_WIDTH{1'b0}};
else if(en) begin
if(load)
count <= count+PCIn;
else
count <= count + 1;
end
end
endmodule | module PC#(parameter MEM_WIDTH=8)(clk, reset, PCOut, PCIn, load, en); |
input clk, reset, load, en;
input [MEM_WIDTH-1:0] PCIn;
output [MEM_WIDTH-1:0] PCOut;
reg [MEM_WIDTH-1:0] count;
assign PCOut = count;
always@(posedge clk)
begin
if(reset)
count <= {MEM_WIDTH{1'b0}};
else if(en) begin
if(load)
count <= count+PCIn;
else
count <= count + 1;
end
end
endmodule | 0 |
4,008 | data/full_repos/permissive/108195533/registerFile.v | 108,195,533 | registerFile.v | v | 41 | 69 | [] | [] | [] | [(1, 40)] | null | data/verilator_xmls/dee5de03-c83f-4209-92c6-de2d855e05e1.xml | null | 2,294 | module | module registerFile #(parameter RF_WIDTH=3, parameter DATA_WIDTH=16)
(clk,
reset,
readAddr1,
readAddr2,
readAddr3,
readData1,
readData2,
readData3,
writeEn,
writeAddr,
writeData);
input clk, reset, writeEn;
input [RF_WIDTH-1:0] readAddr1, readAddr2, readAddr3, writeAddr;
input [DATA_WIDTH-1:0] writeData;
output [DATA_WIDTH-1:0] readData1, readData2, readData3;
reg [DATA_WIDTH-1:0] mem [2**RF_WIDTH-1:0];
assign readData1 = mem[readAddr1];
assign readData2 = mem[readAddr2];
assign readData3 = mem[readAddr3];
integer i;
always @(posedge clk) begin
if(reset) begin
for (i=0; i<2**RF_WIDTH; i=i+1)
mem[i] <= {DATA_WIDTH{1'b0}};
end
else if(writeEn && writeAddr!='d0) begin
mem[writeAddr]<=writeData;
end
end
endmodule | module registerFile #(parameter RF_WIDTH=3, parameter DATA_WIDTH=16)
(clk,
reset,
readAddr1,
readAddr2,
readAddr3,
readData1,
readData2,
readData3,
writeEn,
writeAddr,
writeData); |
input clk, reset, writeEn;
input [RF_WIDTH-1:0] readAddr1, readAddr2, readAddr3, writeAddr;
input [DATA_WIDTH-1:0] writeData;
output [DATA_WIDTH-1:0] readData1, readData2, readData3;
reg [DATA_WIDTH-1:0] mem [2**RF_WIDTH-1:0];
assign readData1 = mem[readAddr1];
assign readData2 = mem[readAddr2];
assign readData3 = mem[readAddr3];
integer i;
always @(posedge clk) begin
if(reset) begin
for (i=0; i<2**RF_WIDTH; i=i+1)
mem[i] <= {DATA_WIDTH{1'b0}};
end
else if(writeEn && writeAddr!='d0) begin
mem[writeAddr]<=writeData;
end
end
endmodule | 0 |
4,009 | data/full_repos/permissive/108195533/segDecoder.v | 108,195,533 | segDecoder.v | v | 48 | 30 | [] | [] | [] | [(1, 47)] | null | data/verilator_xmls/b6e22f30-0b20-4aea-9842-29562c92481c.xml | null | 2,295 | module | module segDecoder(num, segs);
input [3:0] num;
output [7:0] segs;
reg [7:0] decode;
assign segs = ~decode;
always @(*)
begin
case(num)
'd0:
decode = 'h3F;
'd1:
decode = 'h06;
'd2:
decode = 'h5B;
'd3:
decode = 'h4F;
'd4:
decode = 'h66;
'd5:
decode = 'h6D;
'd6:
decode = 'h7D;
'd7:
decode = 'h07;
'd8:
decode = 'h7F;
'd9:
decode = 'h6F;
'd10:
decode = 'h77;
'd11:
decode = 'h7C;
'd12:
decode = 'h39;
'd13:
decode = 'h5E;
'd14:
decode = 'h79;
'd15:
decode = 'h71;
default:
decode = 'hFF;
endcase
end
endmodule | module segDecoder(num, segs); |
input [3:0] num;
output [7:0] segs;
reg [7:0] decode;
assign segs = ~decode;
always @(*)
begin
case(num)
'd0:
decode = 'h3F;
'd1:
decode = 'h06;
'd2:
decode = 'h5B;
'd3:
decode = 'h4F;
'd4:
decode = 'h66;
'd5:
decode = 'h6D;
'd6:
decode = 'h7D;
'd7:
decode = 'h07;
'd8:
decode = 'h7F;
'd9:
decode = 'h6F;
'd10:
decode = 'h77;
'd11:
decode = 'h7C;
'd12:
decode = 'h39;
'd13:
decode = 'h5E;
'd14:
decode = 'h79;
'd15:
decode = 'h71;
default:
decode = 'hFF;
endcase
end
endmodule | 0 |
4,010 | data/full_repos/permissive/108195533/signExtend.v | 108,195,533 | signExtend.v | v | 10 | 84 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/4eacd4f2-0d70-4a60-ab6a-6a0799720bb5.xml | null | 2,296 | module | module signExtend #(parameter DATA_WIDTH=16, parameter OFF_WIDTH=6)(offset, fixed);
input [OFF_WIDTH-1:0] offset;
output reg [DATA_WIDTH-1:0] fixed;
always @(*) begin
fixed = {{(DATA_WIDTH-OFF_WIDTH){offset[OFF_WIDTH-1]}},offset[OFF_WIDTH-1:0]};
end
endmodule | module signExtend #(parameter DATA_WIDTH=16, parameter OFF_WIDTH=6)(offset, fixed); |
input [OFF_WIDTH-1:0] offset;
output reg [DATA_WIDTH-1:0] fixed;
always @(*) begin
fixed = {{(DATA_WIDTH-OFF_WIDTH){offset[OFF_WIDTH-1]}},offset[OFF_WIDTH-1:0]};
end
endmodule | 0 |
4,011 | data/full_repos/permissive/108195533/tb.v | 108,195,533 | tb.v | v | 25 | 30 | [] | [] | [] | null | line:9: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108195533/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108195533/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 10 rst =1\'b0;\n ^\n%Error: data/full_repos/permissive/108195533/tb.v:13: Can\'t find definition of \'stall\' in dotted variable: \'uut.stall\'\n if(uut.stall)\n ^~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,297 | module | module tb;
reg clk, rst;
integer clkNum=0, stallNum=0;
mips_top uut(clk, rst);
initial begin
clk=1'b0;
repeat(2000) begin
#5 clk = !clk;
if(clk) begin
clkNum=clkNum+1;
if(uut.stall)
stallNum = stallNum+1;
end
end
end
initial begin
rst=1'b1;
# 10 rst =1'b0;
end
endmodule | module tb; |
reg clk, rst;
integer clkNum=0, stallNum=0;
mips_top uut(clk, rst);
initial begin
clk=1'b0;
repeat(2000) begin
#5 clk = !clk;
if(clk) begin
clkNum=clkNum+1;
if(uut.stall)
stallNum = stallNum+1;
end
end
end
initial begin
rst=1'b1;
# 10 rst =1'b0;
end
endmodule | 0 |
4,012 | data/full_repos/permissive/108195533/WB_stage.v | 108,195,533 | WB_stage.v | v | 51 | 129 | [] | [] | [] | [(1, 50)] | null | data/verilator_xmls/557f2fe3-89e8-4d30-8d91-73f2e5ca86e1.xml | null | 2,298 | module | module WB_stage
#(parameter WIDTH=16, parameter DATA_WIDTH=16, parameter RF_WIDTH=3)
(clk, reset, instrIn, instrOut, writeAddrIn, writeAddrOut, RFWriteEnIn, RFWriteEnOut, aluResIn, aluResOut, MEMReadData, LDSel);
input clk, reset;
input [WIDTH-1:0] instrIn;
input [RF_WIDTH-1:0] writeAddrIn;
output reg[WIDTH-1:0] instrOut;
input LDSel;
output [DATA_WIDTH-1:0] aluResOut;
reg [DATA_WIDTH-1:0] aluResReg;
assign aluResOut = aluResReg;
output reg [RF_WIDTH-1:0] writeAddrOut;
input [DATA_WIDTH-1:0] aluResIn;
input [DATA_WIDTH-1:0] MEMReadData;
input RFWriteEnIn;
output reg RFWriteEnOut;
always @(posedge clk) begin
if(reset)
RFWriteEnOut <= 1'b0;
else
RFWriteEnOut <= RFWriteEnIn;
end
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
always@(posedge clk)
writeAddrOut <= writeAddrIn;
always @(posedge clk) begin
if(LDSel == 1)
aluResReg <= MEMReadData;
else
aluResReg <= aluResIn;
end
endmodule | module WB_stage
#(parameter WIDTH=16, parameter DATA_WIDTH=16, parameter RF_WIDTH=3)
(clk, reset, instrIn, instrOut, writeAddrIn, writeAddrOut, RFWriteEnIn, RFWriteEnOut, aluResIn, aluResOut, MEMReadData, LDSel); |
input clk, reset;
input [WIDTH-1:0] instrIn;
input [RF_WIDTH-1:0] writeAddrIn;
output reg[WIDTH-1:0] instrOut;
input LDSel;
output [DATA_WIDTH-1:0] aluResOut;
reg [DATA_WIDTH-1:0] aluResReg;
assign aluResOut = aluResReg;
output reg [RF_WIDTH-1:0] writeAddrOut;
input [DATA_WIDTH-1:0] aluResIn;
input [DATA_WIDTH-1:0] MEMReadData;
input RFWriteEnIn;
output reg RFWriteEnOut;
always @(posedge clk) begin
if(reset)
RFWriteEnOut <= 1'b0;
else
RFWriteEnOut <= RFWriteEnIn;
end
always@(posedge clk) begin
if(reset)
instrOut <= {WIDTH{1'b0}};
else
instrOut <= instrIn;
end
always@(posedge clk)
writeAddrOut <= writeAddrIn;
always @(posedge clk) begin
if(LDSel == 1)
aluResReg <= MEMReadData;
else
aluResReg <= aluResIn;
end
endmodule | 0 |
4,013 | data/full_repos/permissive/108216748/LPN_PUF_complete_test/lib/xilinx.com_user_tlast_gen_1.0/tlast_gen.v | 108,216,748 | tlast_gen.v | v | 78 | 83 | [] | [] | [] | [(29, 76)] | null | data/verilator_xmls/ad186917-a3e7-4e22-9c64-06a71ea9bd4f.xml | null | 2,299 | module | module tlast_gen
#(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
)
(
input aclk,
input resetn,
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [TDATA_WIDTH-1:0] m_axis_tdata
);
wire new_sample;
reg [$clog2(MAX_PKT_LENGTH):0] cnt = 0;
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
assign new_sample = s_axis_tvalid & s_axis_tready;
always @ (posedge aclk) begin
if (~resetn | (m_axis_tlast & new_sample))
cnt <= 0;
else
if (new_sample)
cnt <= cnt + 1'b1;
end
assign m_axis_tlast = (cnt == pkt_length-1);
endmodule | module tlast_gen
#(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
)
(
input aclk,
input resetn,
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [TDATA_WIDTH-1:0] m_axis_tdata
); |
wire new_sample;
reg [$clog2(MAX_PKT_LENGTH):0] cnt = 0;
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
assign new_sample = s_axis_tvalid & s_axis_tready;
always @ (posedge aclk) begin
if (~resetn | (m_axis_tlast & new_sample))
cnt <= 0;
else
if (new_sample)
cnt <= cnt + 1'b1;
end
assign m_axis_tlast = (cnt == pkt_length-1);
endmodule | 10 |
4,014 | data/full_repos/permissive/108216748/system/sha2.v | 108,216,748 | sha2.v | v | 85 | 83 | [] | [] | [] | [(4, 25), (29, 36), (40, 47), (51, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha2.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha2_round\'\nmodule sha2_round #(\n ^~~~~~~~~~\n : ... Top module \'Ch\'\nmodule Ch #(parameter WORDSIZE=0) (\n ^~\n : ... Top module \'Maj\'\nmodule Maj #(parameter WORDSIZE=0) (\n ^~~\n : ... Top module \'W_machine\'\nmodule W_machine #(parameter WORDSIZE=1) (\n ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:41: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Maj\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Ch\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Kj, Wj,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;\n ^\n%Error: Exiting due to 11 warning(s)\n' | 2,307 | module | module sha2_round #(
parameter WORDSIZE=0
) (
input [WORDSIZE-1:0] Kj, Wj,
input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,
input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,
output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out
);
wire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;
wire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;
assign a_out = T1 + T2;
assign b_out = a_in;
assign c_out = b_in;
assign d_out = c_in;
assign e_out = d_in + T1;
assign f_out = e_in;
assign g_out = f_in;
assign h_out = g_in;
endmodule | module sha2_round #(
parameter WORDSIZE=0
) (
input [WORDSIZE-1:0] Kj, Wj,
input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,
input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,
output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out
); |
wire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;
wire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;
assign a_out = T1 + T2;
assign b_out = a_in;
assign c_out = b_in;
assign d_out = c_in;
assign e_out = d_in + T1;
assign f_out = e_in;
assign g_out = f_in;
assign h_out = g_in;
endmodule | 10 |
4,015 | data/full_repos/permissive/108216748/system/sha2.v | 108,216,748 | sha2.v | v | 85 | 83 | [] | [] | [] | [(4, 25), (29, 36), (40, 47), (51, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha2.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha2_round\'\nmodule sha2_round #(\n ^~~~~~~~~~\n : ... Top module \'Ch\'\nmodule Ch #(parameter WORDSIZE=0) (\n ^~\n : ... Top module \'Maj\'\nmodule Maj #(parameter WORDSIZE=0) (\n ^~~\n : ... Top module \'W_machine\'\nmodule W_machine #(parameter WORDSIZE=1) (\n ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:41: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Maj\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Ch\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Kj, Wj,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;\n ^\n%Error: Exiting due to 11 warning(s)\n' | 2,307 | module | module Ch #(parameter WORDSIZE=0) (
input wire [WORDSIZE-1:0] x, y, z,
output wire [WORDSIZE-1:0] Ch
);
assign Ch = ((x & y) ^ (~x & z));
endmodule | module Ch #(parameter WORDSIZE=0) (
input wire [WORDSIZE-1:0] x, y, z,
output wire [WORDSIZE-1:0] Ch
); |
assign Ch = ((x & y) ^ (~x & z));
endmodule | 10 |
4,016 | data/full_repos/permissive/108216748/system/sha2.v | 108,216,748 | sha2.v | v | 85 | 83 | [] | [] | [] | [(4, 25), (29, 36), (40, 47), (51, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha2.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha2_round\'\nmodule sha2_round #(\n ^~~~~~~~~~\n : ... Top module \'Ch\'\nmodule Ch #(parameter WORDSIZE=0) (\n ^~\n : ... Top module \'Maj\'\nmodule Maj #(parameter WORDSIZE=0) (\n ^~~\n : ... Top module \'W_machine\'\nmodule W_machine #(parameter WORDSIZE=1) (\n ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:41: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Maj\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Ch\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Kj, Wj,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;\n ^\n%Error: Exiting due to 11 warning(s)\n' | 2,307 | module | module Maj #(parameter WORDSIZE=0) (
input wire [WORDSIZE-1:0] x, y, z,
output wire [WORDSIZE-1:0] Maj
);
assign Maj = (x & y) ^ (x & z) ^ (y & z);
endmodule | module Maj #(parameter WORDSIZE=0) (
input wire [WORDSIZE-1:0] x, y, z,
output wire [WORDSIZE-1:0] Maj
); |
assign Maj = (x & y) ^ (x & z) ^ (y & z);
endmodule | 10 |
4,017 | data/full_repos/permissive/108216748/system/sha2.v | 108,216,748 | sha2.v | v | 85 | 83 | [] | [] | [] | [(4, 25), (29, 36), (40, 47), (51, 84)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha2.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha2_round\'\nmodule sha2_round #(\n ^~~~~~~~~~\n : ... Top module \'Ch\'\nmodule Ch #(parameter WORDSIZE=0) (\n ^~\n : ... Top module \'Maj\'\nmodule Maj #(parameter WORDSIZE=0) (\n ^~~\n : ... Top module \'W_machine\'\nmodule W_machine #(parameter WORDSIZE=1) (\n ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:41: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Maj\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [WORDSIZE-1:0] x, y, z,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [WORDSIZE-1:0] Ch\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Kj, Wj,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;\n ^\n%Error: Exiting due to 11 warning(s)\n' | 2,307 | module | module W_machine #(parameter WORDSIZE=1) (
input clk,
input en,
input [WORDSIZE*16-1:0] M,
input M_valid,
output [WORDSIZE-1:0] W_tm2, W_tm15,
input [WORDSIZE-1:0] s1_Wtm2, s0_Wtm15,
output [WORDSIZE-1:0] W
);
reg [WORDSIZE*16-1:0] W_stack_q;
assign W_tm2 = W_stack_q[WORDSIZE*2-1:WORDSIZE*1];
assign W_tm15 = W_stack_q[WORDSIZE*15-1:WORDSIZE*14];
wire [WORDSIZE-1:0] W_tm7 = W_stack_q[WORDSIZE*7-1:WORDSIZE*6];
wire [WORDSIZE-1:0] W_tm16 = W_stack_q[WORDSIZE*16-1:WORDSIZE*15];
wire [WORDSIZE-1:0] Wt_next = s1_Wtm2 + W_tm7 + s0_Wtm15 + W_tm16;
wire [WORDSIZE*16-1:0] W_stack_d = {W_stack_q[WORDSIZE*15-1:0], Wt_next};
assign W = W_stack_q[WORDSIZE*16-1:WORDSIZE*15];
always @(posedge clk)
begin
if (en == 0)
W_stack_q <= W_stack_q;
else if (M_valid) begin
W_stack_q <= M;
end else begin
W_stack_q <= W_stack_d;
end
end
endmodule | module W_machine #(parameter WORDSIZE=1) (
input clk,
input en,
input [WORDSIZE*16-1:0] M,
input M_valid,
output [WORDSIZE-1:0] W_tm2, W_tm15,
input [WORDSIZE-1:0] s1_Wtm2, s0_Wtm15,
output [WORDSIZE-1:0] W
); |
reg [WORDSIZE*16-1:0] W_stack_q;
assign W_tm2 = W_stack_q[WORDSIZE*2-1:WORDSIZE*1];
assign W_tm15 = W_stack_q[WORDSIZE*15-1:WORDSIZE*14];
wire [WORDSIZE-1:0] W_tm7 = W_stack_q[WORDSIZE*7-1:WORDSIZE*6];
wire [WORDSIZE-1:0] W_tm16 = W_stack_q[WORDSIZE*16-1:WORDSIZE*15];
wire [WORDSIZE-1:0] Wt_next = s1_Wtm2 + W_tm7 + s0_Wtm15 + W_tm16;
wire [WORDSIZE*16-1:0] W_stack_d = {W_stack_q[WORDSIZE*15-1:0], Wt_next};
assign W = W_stack_q[WORDSIZE*16-1:WORDSIZE*15];
always @(posedge clk)
begin
if (en == 0)
W_stack_q <= W_stack_q;
else if (M_valid) begin
W_stack_q <= M;
end else begin
W_stack_q <= W_stack_d;
end
end
endmodule | 10 |
4,018 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_block (
input clk, rst,
input [255:0] H_in,
input [511:0] M_in,
input input_valid,
input en,
output [255:0] H_out,
output output_valid
);
reg [6:0] round;
wire [31:0] a_in = H_in[255:224], b_in = H_in[223:192], c_in = H_in[191:160], d_in = H_in[159:128];
wire [31:0] e_in = H_in[127:96], f_in = H_in[95:64], g_in = H_in[63:32], h_in = H_in[31:0];
reg [31:0] a_q, b_q, c_q, d_q, e_q, f_q, g_q, h_q;
wire [31:0] a_d, b_d, c_d, d_d, e_d, f_d, g_d, h_d;
wire [31:0] W_tm2, W_tm15, s1_Wtm2, s0_Wtm15, Wj, Kj;
assign H_out = {
a_in + a_q, b_in + b_q, c_in + c_q, d_in + d_q, e_in + e_q, f_in + f_q, g_in + g_q, h_in + h_q
};
assign output_valid = round == 64;
always @(posedge clk)
begin
if (en == 0)
begin
a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
round <= round;
end
else if (input_valid) begin
a_q <= a_in; b_q <= b_in; c_q <= c_in; d_q <= d_in;
e_q <= e_in; f_q <= f_in; g_q <= g_in; h_q <= h_in;
round <= 0;
end
else if (round == 64)
begin
a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
round <= round;
end
else begin
a_q <= a_d; b_q <= b_d; c_q <= c_d; d_q <= d_d;
e_q <= e_d; f_q <= f_d; g_q <= g_d; h_q <= h_d;
round <= round + 1;
end
end
sha256_round sha256_round (
.Kj(Kj), .Wj(Wj),
.a_in(a_q), .b_in(b_q), .c_in(c_q), .d_in(d_q),
.e_in(e_q), .f_in(f_q), .g_in(g_q), .h_in(h_q),
.a_out(a_d), .b_out(b_d), .c_out(c_d), .d_out(d_d),
.e_out(e_d), .f_out(f_d), .g_out(g_d), .h_out(h_d)
);
sha256_s0 sha256_s0 (.x(W_tm15), .s0(s0_Wtm15));
sha256_s1 sha256_s1 (.x(W_tm2), .s1(s1_Wtm2));
W_machine #(.WORDSIZE(32)) W_machine (
.clk(clk),
.en(en),
.M(M_in), .M_valid(input_valid),
.W_tm2(W_tm2), .W_tm15(W_tm15),
.s1_Wtm2(s1_Wtm2), .s0_Wtm15(s0_Wtm15),
.W(Wj)
);
sha256_K_machine sha256_K_machine (
.clk(clk), .rst(input_valid), .en(en), .K(Kj)
);
endmodule | module sha256_block (
input clk, rst,
input [255:0] H_in,
input [511:0] M_in,
input input_valid,
input en,
output [255:0] H_out,
output output_valid
); |
reg [6:0] round;
wire [31:0] a_in = H_in[255:224], b_in = H_in[223:192], c_in = H_in[191:160], d_in = H_in[159:128];
wire [31:0] e_in = H_in[127:96], f_in = H_in[95:64], g_in = H_in[63:32], h_in = H_in[31:0];
reg [31:0] a_q, b_q, c_q, d_q, e_q, f_q, g_q, h_q;
wire [31:0] a_d, b_d, c_d, d_d, e_d, f_d, g_d, h_d;
wire [31:0] W_tm2, W_tm15, s1_Wtm2, s0_Wtm15, Wj, Kj;
assign H_out = {
a_in + a_q, b_in + b_q, c_in + c_q, d_in + d_q, e_in + e_q, f_in + f_q, g_in + g_q, h_in + h_q
};
assign output_valid = round == 64;
always @(posedge clk)
begin
if (en == 0)
begin
a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
round <= round;
end
else if (input_valid) begin
a_q <= a_in; b_q <= b_in; c_q <= c_in; d_q <= d_in;
e_q <= e_in; f_q <= f_in; g_q <= g_in; h_q <= h_in;
round <= 0;
end
else if (round == 64)
begin
a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
round <= round;
end
else begin
a_q <= a_d; b_q <= b_d; c_q <= c_d; d_q <= d_d;
e_q <= e_d; f_q <= f_d; g_q <= g_d; h_q <= h_d;
round <= round + 1;
end
end
sha256_round sha256_round (
.Kj(Kj), .Wj(Wj),
.a_in(a_q), .b_in(b_q), .c_in(c_q), .d_in(d_q),
.e_in(e_q), .f_in(f_q), .g_in(g_q), .h_in(h_q),
.a_out(a_d), .b_out(b_d), .c_out(c_d), .d_out(d_d),
.e_out(e_d), .f_out(f_d), .g_out(g_d), .h_out(h_d)
);
sha256_s0 sha256_s0 (.x(W_tm15), .s0(s0_Wtm15));
sha256_s1 sha256_s1 (.x(W_tm2), .s1(s1_Wtm2));
W_machine #(.WORDSIZE(32)) W_machine (
.clk(clk),
.en(en),
.M(M_in), .M_valid(input_valid),
.W_tm2(W_tm2), .W_tm15(W_tm15),
.s1_Wtm2(s1_Wtm2), .s0_Wtm15(s0_Wtm15),
.W(Wj)
);
sha256_K_machine sha256_K_machine (
.clk(clk), .rst(input_valid), .en(en), .K(Kj)
);
endmodule | 10 |
4,019 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_round (
input [31:0] Kj, Wj,
input [31:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,
output [31:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out
);
wire [31:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e;
Ch #(.WORDSIZE(32)) Ch (
.x(e_in), .y(f_in), .z(g_in), .Ch(Ch_e_f_g)
);
Maj #(.WORDSIZE(32)) Maj (
.x(a_in), .y(b_in), .z(c_in), .Maj(Maj_a_b_c)
);
sha256_S0 S0 (
.x(a_in), .S0(S0_a)
);
sha256_S1 S1 (
.x(e_in), .S1(S1_e)
);
sha2_round #(.WORDSIZE(32)) sha256_round_inner (
.Kj(Kj), .Wj(Wj),
.a_in(a_in), .b_in(b_in), .c_in(c_in), .d_in(d_in),
.e_in(e_in), .f_in(f_in), .g_in(g_in), .h_in(h_in),
.Ch_e_f_g(Ch_e_f_g), .Maj_a_b_c(Maj_a_b_c), .S0_a(S0_a), .S1_e(S1_e),
.a_out(a_out), .b_out(b_out), .c_out(c_out), .d_out(d_out),
.e_out(e_out), .f_out(f_out), .g_out(g_out), .h_out(h_out)
);
endmodule | module sha256_round (
input [31:0] Kj, Wj,
input [31:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,
output [31:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out
); |
wire [31:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e;
Ch #(.WORDSIZE(32)) Ch (
.x(e_in), .y(f_in), .z(g_in), .Ch(Ch_e_f_g)
);
Maj #(.WORDSIZE(32)) Maj (
.x(a_in), .y(b_in), .z(c_in), .Maj(Maj_a_b_c)
);
sha256_S0 S0 (
.x(a_in), .S0(S0_a)
);
sha256_S1 S1 (
.x(e_in), .S1(S1_e)
);
sha2_round #(.WORDSIZE(32)) sha256_round_inner (
.Kj(Kj), .Wj(Wj),
.a_in(a_in), .b_in(b_in), .c_in(c_in), .d_in(d_in),
.e_in(e_in), .f_in(f_in), .g_in(g_in), .h_in(h_in),
.Ch_e_f_g(Ch_e_f_g), .Maj_a_b_c(Maj_a_b_c), .S0_a(S0_a), .S1_e(S1_e),
.a_out(a_out), .b_out(b_out), .c_out(c_out), .d_out(d_out),
.e_out(e_out), .f_out(f_out), .g_out(g_out), .h_out(h_out)
);
endmodule | 10 |
4,020 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_S0 (
input wire [31:0] x,
output wire [31:0] S0
);
assign S0 = ({x[1:0], x[31:2]} ^ {x[12:0], x[31:13]} ^ {x[21:0], x[31:22]});
endmodule | module sha256_S0 (
input wire [31:0] x,
output wire [31:0] S0
); |
assign S0 = ({x[1:0], x[31:2]} ^ {x[12:0], x[31:13]} ^ {x[21:0], x[31:22]});
endmodule | 10 |
4,021 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_S1 (
input wire [31:0] x,
output wire [31:0] S1
);
assign S1 = ({x[5:0], x[31:6]} ^ {x[10:0], x[31:11]} ^ {x[24:0], x[31:25]});
endmodule | module sha256_S1 (
input wire [31:0] x,
output wire [31:0] S1
); |
assign S1 = ({x[5:0], x[31:6]} ^ {x[10:0], x[31:11]} ^ {x[24:0], x[31:25]});
endmodule | 10 |
4,022 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_s0 (
input wire [31:0] x,
output wire [31:0] s0
);
assign s0 = ({x[6:0], x[31:7]} ^ {x[17:0], x[31:18]} ^ (x >> 3));
endmodule | module sha256_s0 (
input wire [31:0] x,
output wire [31:0] s0
); |
assign s0 = ({x[6:0], x[31:7]} ^ {x[17:0], x[31:18]} ^ (x >> 3));
endmodule | 10 |
4,023 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_s1 (
input wire [31:0] x,
output wire [31:0] s1
);
assign s1 = ({x[16:0], x[31:17]} ^ {x[18:0], x[31:19]} ^ (x >> 10));
endmodule | module sha256_s1 (
input wire [31:0] x,
output wire [31:0] s1
); |
assign s1 = ({x[16:0], x[31:17]} ^ {x[18:0], x[31:19]} ^ (x >> 10));
endmodule | 10 |
4,024 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_K_machine (
input clk,
input rst,
input en,
output [31:0] K
);
reg [2047:0] rom_q;
wire [2047:0] rom_d = { rom_q[2015:0], rom_q[2047:2016] };
assign K = rom_q[2047:2016];
always @(posedge clk)
begin
if (rst) begin
rom_q <= {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
end
else if (en == 0)
begin
rom_q <= rom_q;
end
else begin
rom_q <= rom_d;
end
end
endmodule | module sha256_K_machine (
input clk,
input rst,
input en,
output [31:0] K
); |
reg [2047:0] rom_q;
wire [2047:0] rom_d = { rom_q[2015:0], rom_q[2047:2016] };
assign K = rom_q[2047:2016];
always @(posedge clk)
begin
if (rst) begin
rom_q <= {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
end
else if (en == 0)
begin
rom_q <= rom_q;
end
else begin
rom_q <= rom_d;
end
end
endmodule | 10 |
4,025 | data/full_repos/permissive/108216748/system/sha256.v | 108,216,748 | sha256.v | v | 215 | 100 | [] | [] | [] | null | line:18: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sha256_block\'\nmodule sha256_block (\n ^~~~~~~~~~~~\n : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n ... Looked in:\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n Ch\n Ch.v\n Ch.sv\n obj_dir/Ch\n obj_dir/Ch.v\n obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 2,308 | module | module sha256_H_0(
output [255:0] H_0
);
assign H_0 = {
32'h6A09E667, 32'hBB67AE85, 32'h3C6EF372, 32'hA54FF53A,
32'h510E527F, 32'h9B05688C, 32'h1F83D9AB, 32'h5BE0CD19
};
endmodule | module sha256_H_0(
output [255:0] H_0
); |
assign H_0 = {
32'h6A09E667, 32'hBB67AE85, 32'h3C6EF372, 32'hA54FF53A,
32'h510E527F, 32'h9B05688C, 32'h1F83D9AB, 32'h5BE0CD19
};
endmodule | 10 |
4,063 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);
input SwitchClk_10, reset;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
output [31:0] CurrentPC;
wire [31:0] ShowNum, PCAddFour, Instruction, ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData;
wire [31:0] BranchAddr, ALUResult, ReadData2toEXMEM, MemData;
wire [27:0] JumpAddr_28;
wire PCWrite, BranchMuxSignal, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc;
wire IFIDWrite, IDEXFlush1, Zero, IFIDFlush, IDEXFlush2, EXMEMFlush;
wire [1:0] ALUOp;
wire [4:0] RegDstAddr;
reg [31:0] IFID_PC, IFID_Instruction, IDEX_JumpAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32;
reg [31:0] EXMEM_JumpAddr, EXMEM_BranchAddr, EXMEM_ALUResult, EXMEM_ReadData2, MEMWB_MemData, MEMWB_ALUData;
reg [1:0] IDEX_WB, EXMEM_WB, MEMWB_WB;
reg [4:0] IDEX_MEM, IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_MEM, EXMEM_RegDst, MEMWB_RegDst;
reg [3:0] IDEX_EX;
reg EXMEM_Zero;
reg [31:0] CurrentPC;
always @(PCAddFour)
CurrentPC=PCAddFour-4;
IFStage M_IF(PCAddFour, Instruction, PCWrite, EXMEM_MEM[0], EXMEM_JumpAddr, BranchMuxSignal, EXMEM_BranchAddr, SwitchClk_10, reset);
IDStage M_ID(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFIDWrite, IDEXFlush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, IFID_Instruction, MEMWB_RegDst, WriteData, MEMWB_WB[1], IDEX_Rt, IDEX_MEM[1], SwitchClk_10, reset);
EXStage M_EX(BranchAddr, Zero, ALUResult, ReadData2toEXMEM, RegDstAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_WB[1], MEMWB_RegDst, MEMWB_WB[1], IDEX_EX);
MEMStage M_MEM(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_WB[0], MEMWB_RegDst, SwitchClk_10, reset);
WBStage M_WB(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_WB[0]);
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
IFID_PC<=0;
IFID_Instruction<=0;
end
else if (IFIDFlush==1) begin
IFID_PC<=0;
IFID_Instruction<=0;
end
else if (IFIDWrite==0) begin
IFID_PC<=IFID_PC;
IFID_Instruction<=IFID_Instruction;
end
else begin
IFID_PC<=PCAddFour;
IFID_Instruction<=Instruction;
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else if (IDEXFlush1==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else if (IDEXFlush2==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else begin
IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28};
IDEX_PC<=IFID_PC;
IDEX_ReadData1<=ReadData1;
IDEX_ReadData2<=ReadData2;
IDEX_Immediate_32<=Immediate_32;
IDEX_WB<={RegWrite, MemtoReg};
IDEX_MEM<={Branch, BranchN, MemWrite, MemRead, Jump};
IDEX_Rt<=IFID_Instruction[20:16];
IDEX_Rd<=IFID_Instruction[15:11];
IDEX_Rs<=IFID_Instruction[25:21];
IDEX_EX<={RegDst, ALUSrc, ALUOp};
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
EXMEM_JumpAddr<=0;
EXMEM_BranchAddr<=0;
EXMEM_ALUResult<=0;
EXMEM_ReadData2<=0;
EXMEM_WB<=0;
EXMEM_MEM<=0;
EXMEM_RegDst<=0;
EXMEM_Zero<=0;
end
else if (EXMEMFlush==1) begin
EXMEM_JumpAddr<=0;
EXMEM_BranchAddr<=0;
EXMEM_ALUResult<=0;
EXMEM_ReadData2<=0;
EXMEM_WB<=0;
EXMEM_MEM<=0;
EXMEM_RegDst<=0;
EXMEM_Zero<=0;
end
else begin
EXMEM_JumpAddr<=IDEX_JumpAddr;
EXMEM_BranchAddr<=BranchAddr;
EXMEM_ALUResult<=ALUResult;
EXMEM_ReadData2<=ReadData2toEXMEM;
EXMEM_WB<=IDEX_WB;
EXMEM_MEM<=IDEX_MEM;
EXMEM_RegDst<=RegDstAddr;
EXMEM_Zero<=Zero;
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
MEMWB_MemData<=0;
MEMWB_ALUData<=0;
MEMWB_WB<=0;
MEMWB_RegDst<=0;
end
else begin
MEMWB_MemData<=MemData;
MEMWB_ALUData<=EXMEM_ALUResult;
MEMWB_WB<=EXMEM_WB;
MEMWB_RegDst<=EXMEM_RegDst;
end
end
endmodule | module Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset); |
input SwitchClk_10, reset;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
output [31:0] CurrentPC;
wire [31:0] ShowNum, PCAddFour, Instruction, ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData;
wire [31:0] BranchAddr, ALUResult, ReadData2toEXMEM, MemData;
wire [27:0] JumpAddr_28;
wire PCWrite, BranchMuxSignal, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc;
wire IFIDWrite, IDEXFlush1, Zero, IFIDFlush, IDEXFlush2, EXMEMFlush;
wire [1:0] ALUOp;
wire [4:0] RegDstAddr;
reg [31:0] IFID_PC, IFID_Instruction, IDEX_JumpAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32;
reg [31:0] EXMEM_JumpAddr, EXMEM_BranchAddr, EXMEM_ALUResult, EXMEM_ReadData2, MEMWB_MemData, MEMWB_ALUData;
reg [1:0] IDEX_WB, EXMEM_WB, MEMWB_WB;
reg [4:0] IDEX_MEM, IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_MEM, EXMEM_RegDst, MEMWB_RegDst;
reg [3:0] IDEX_EX;
reg EXMEM_Zero;
reg [31:0] CurrentPC;
always @(PCAddFour)
CurrentPC=PCAddFour-4;
IFStage M_IF(PCAddFour, Instruction, PCWrite, EXMEM_MEM[0], EXMEM_JumpAddr, BranchMuxSignal, EXMEM_BranchAddr, SwitchClk_10, reset);
IDStage M_ID(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFIDWrite, IDEXFlush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, IFID_Instruction, MEMWB_RegDst, WriteData, MEMWB_WB[1], IDEX_Rt, IDEX_MEM[1], SwitchClk_10, reset);
EXStage M_EX(BranchAddr, Zero, ALUResult, ReadData2toEXMEM, RegDstAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_WB[1], MEMWB_RegDst, MEMWB_WB[1], IDEX_EX);
MEMStage M_MEM(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_WB[0], MEMWB_RegDst, SwitchClk_10, reset);
WBStage M_WB(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_WB[0]);
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
IFID_PC<=0;
IFID_Instruction<=0;
end
else if (IFIDFlush==1) begin
IFID_PC<=0;
IFID_Instruction<=0;
end
else if (IFIDWrite==0) begin
IFID_PC<=IFID_PC;
IFID_Instruction<=IFID_Instruction;
end
else begin
IFID_PC<=PCAddFour;
IFID_Instruction<=Instruction;
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else if (IDEXFlush1==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else if (IDEXFlush2==1) begin
IDEX_JumpAddr<=0;
IDEX_PC<=0;
IDEX_ReadData1<=0;
IDEX_ReadData2<=0;
IDEX_Immediate_32<=0;
IDEX_WB<=0;
IDEX_MEM<=0;
IDEX_Rt<=0;
IDEX_Rd<=0;
IDEX_Rs<=0;
IDEX_EX<=0;
end
else begin
IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28};
IDEX_PC<=IFID_PC;
IDEX_ReadData1<=ReadData1;
IDEX_ReadData2<=ReadData2;
IDEX_Immediate_32<=Immediate_32;
IDEX_WB<={RegWrite, MemtoReg};
IDEX_MEM<={Branch, BranchN, MemWrite, MemRead, Jump};
IDEX_Rt<=IFID_Instruction[20:16];
IDEX_Rd<=IFID_Instruction[15:11];
IDEX_Rs<=IFID_Instruction[25:21];
IDEX_EX<={RegDst, ALUSrc, ALUOp};
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
EXMEM_JumpAddr<=0;
EXMEM_BranchAddr<=0;
EXMEM_ALUResult<=0;
EXMEM_ReadData2<=0;
EXMEM_WB<=0;
EXMEM_MEM<=0;
EXMEM_RegDst<=0;
EXMEM_Zero<=0;
end
else if (EXMEMFlush==1) begin
EXMEM_JumpAddr<=0;
EXMEM_BranchAddr<=0;
EXMEM_ALUResult<=0;
EXMEM_ReadData2<=0;
EXMEM_WB<=0;
EXMEM_MEM<=0;
EXMEM_RegDst<=0;
EXMEM_Zero<=0;
end
else begin
EXMEM_JumpAddr<=IDEX_JumpAddr;
EXMEM_BranchAddr<=BranchAddr;
EXMEM_ALUResult<=ALUResult;
EXMEM_ReadData2<=ReadData2toEXMEM;
EXMEM_WB<=IDEX_WB;
EXMEM_MEM<=IDEX_MEM;
EXMEM_RegDst<=RegDstAddr;
EXMEM_Zero<=Zero;
end
end
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) begin
MEMWB_MemData<=0;
MEMWB_ALUData<=0;
MEMWB_WB<=0;
MEMWB_RegDst<=0;
end
else begin
MEMWB_MemData<=MemData;
MEMWB_ALUData<=EXMEM_ALUResult;
MEMWB_WB<=EXMEM_WB;
MEMWB_RegDst<=EXMEM_RegDst;
end
end
endmodule | 0 |
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