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4,207 | data/full_repos/permissive/109209652/verilog/ov7670.v | 109,209,652 | ov7670.v | v | 154 | 77 | [] | [] | [] | [(9, 154)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/ov7670.v:80: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance ov7670\n row_buf_addr <= 10\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,407 | module | module ov7670(
input clk_50,
input reset,
output reg xclk,
input pclk,
input vsync,
input href,
input [7:0] data,
output reg cam_rst,
output reg cam_pwdn,
output reg [7:0] value,
output reg [9:0] x_addr,
output reg [9:0] y_addr,
output reg [18:0] mem_addr,
output reg is_val
);
reg [7:0] pixel_temp;
reg [7:0] row_buf[319:0];
reg [8:0] row_buf_addr;
always@ (posedge clk_50) begin
if (reset == 1'b1) begin
xclk <= 1'b0;
end
else begin
xclk <= ~xclk;
end
end
always@ (posedge clk_50) begin
if (reset == 1'b1) begin
cam_rst <= 1'b0;
cam_pwdn <= 1'b1;
end
else begin
cam_rst <= 1'b1;
cam_pwdn <= 1'b0;
end
end
reg last_href;
reg is_y;
reg is_wr_row;
reg pixel_num;
always@ (posedge pclk) begin
if (vsync == 1'b1 && href == 1'b0 && last_href == 1'b0) begin
x_addr <= 10'b0;
y_addr <= 10'b0;
mem_addr <= 19'b0;
value <= 8'b0;
is_val <= 1'b0;
is_y <= 1'b0;
is_wr_row <= 0;
pixel_num <= 0;
pixel_temp <= 0;
row_buf_addr <= 10'd0;
end
else begin
if (href == 1'b1) begin
if (is_y) begin
pixel_num <= ~pixel_num;
if (pixel_num) begin
if (is_wr_row) begin
value <= (data >> 4) + (pixel_temp >> 4) + row_buf[row_buf_addr];
row_buf_addr <= row_buf_addr + 1;
is_val <= 1'b1;
mem_addr <= mem_addr + 1;
x_addr <= x_addr + 10'b1;
y_addr <= y_addr;
end
else begin
row_buf[row_buf_addr] <= (data >> 2) + (pixel_temp >> 2);
row_buf_addr <= row_buf_addr + 1;
is_val <= 1'b0;
end
end
else begin
pixel_temp <= data;
is_val <= 1'b0;
end
end
else begin
x_addr <= x_addr;
y_addr <= y_addr;
mem_addr <= mem_addr;
value <= 8'b0;
is_val <= 1'b0;
end
is_y <= ~is_y;
end
else begin
value <= 8'b0;
is_val <= 1'b0;
is_y <= 1'b0;
if (last_href == 1'b1) begin
x_addr <= 10'b0;
mem_addr <= mem_addr;
is_wr_row <= ~is_wr_row;
pixel_num <= 0;
row_buf_addr <= 0;
y_addr <= y_addr + 10'b1;
end
else begin
x_addr <= x_addr;
y_addr <= y_addr;
mem_addr <= mem_addr;
end
end
end
last_href <= href;
end
endmodule | module ov7670(
input clk_50,
input reset,
output reg xclk,
input pclk,
input vsync,
input href,
input [7:0] data,
output reg cam_rst,
output reg cam_pwdn,
output reg [7:0] value,
output reg [9:0] x_addr,
output reg [9:0] y_addr,
output reg [18:0] mem_addr,
output reg is_val
); |
reg [7:0] pixel_temp;
reg [7:0] row_buf[319:0];
reg [8:0] row_buf_addr;
always@ (posedge clk_50) begin
if (reset == 1'b1) begin
xclk <= 1'b0;
end
else begin
xclk <= ~xclk;
end
end
always@ (posedge clk_50) begin
if (reset == 1'b1) begin
cam_rst <= 1'b0;
cam_pwdn <= 1'b1;
end
else begin
cam_rst <= 1'b1;
cam_pwdn <= 1'b0;
end
end
reg last_href;
reg is_y;
reg is_wr_row;
reg pixel_num;
always@ (posedge pclk) begin
if (vsync == 1'b1 && href == 1'b0 && last_href == 1'b0) begin
x_addr <= 10'b0;
y_addr <= 10'b0;
mem_addr <= 19'b0;
value <= 8'b0;
is_val <= 1'b0;
is_y <= 1'b0;
is_wr_row <= 0;
pixel_num <= 0;
pixel_temp <= 0;
row_buf_addr <= 10'd0;
end
else begin
if (href == 1'b1) begin
if (is_y) begin
pixel_num <= ~pixel_num;
if (pixel_num) begin
if (is_wr_row) begin
value <= (data >> 4) + (pixel_temp >> 4) + row_buf[row_buf_addr];
row_buf_addr <= row_buf_addr + 1;
is_val <= 1'b1;
mem_addr <= mem_addr + 1;
x_addr <= x_addr + 10'b1;
y_addr <= y_addr;
end
else begin
row_buf[row_buf_addr] <= (data >> 2) + (pixel_temp >> 2);
row_buf_addr <= row_buf_addr + 1;
is_val <= 1'b0;
end
end
else begin
pixel_temp <= data;
is_val <= 1'b0;
end
end
else begin
x_addr <= x_addr;
y_addr <= y_addr;
mem_addr <= mem_addr;
value <= 8'b0;
is_val <= 1'b0;
end
is_y <= ~is_y;
end
else begin
value <= 8'b0;
is_val <= 1'b0;
is_y <= 1'b0;
if (last_href == 1'b1) begin
x_addr <= 10'b0;
mem_addr <= mem_addr;
is_wr_row <= ~is_wr_row;
pixel_num <= 0;
row_buf_addr <= 0;
y_addr <= y_addr + 10'b1;
end
else begin
x_addr <= x_addr;
y_addr <= y_addr;
mem_addr <= mem_addr;
end
end
end
last_href <= href;
end
endmodule | 1 |
4,209 | data/full_repos/permissive/109209652/verilog/stereovision.v | 109,209,652 | stereovision.v | v | 229 | 59 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:32: Cannot find file containing module: 'convolve'\n convolve #(3,row_sz,col_sz) my_convolver0(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109209652/verilog,data/full_repos/permissive/109209652/convolve\n data/full_repos/permissive/109209652/verilog,data/full_repos/permissive/109209652/convolve.v\n data/full_repos/permissive/109209652/verilog,data/full_repos/permissive/109209652/convolve.sv\n convolve\n convolve.v\n convolve.sv\n obj_dir/convolve\n obj_dir/convolve.v\n obj_dir/convolve.sv\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:57: Cannot find file containing module: 'convolve'\n convolve #(3,row_sz,col_sz) my_convolver1(\n ^~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:83: Cannot find file containing module: 'sp_census'\n sp_census #(row_sz,col_sz) my_census0(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:102: Cannot find file containing module: 'sp_census'\n sp_census #(row_sz,col_sz) my_census1(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:122: Cannot find file containing module: 'census_window'\n census_window #(3,row_sz,col_sz) my_wdw0(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:142: Cannot find file containing module: 'census_window'\n census_window #(3,row_sz,col_sz) my_wdw1(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/stereovision.v:162: Cannot find file containing module: 'correlate'\n correlate #(row_sz, col_sz) my_corr(\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 2,410 | module | module stereo(
input clk,
input reset,
input [7:0] census_thresh,
input [9:0] in_x,
input [9:0] in_y,
input [7:0] in_left,
input [7:0] in_right,
input in_is_val,
output [9:0] out_x,
output [9:0] out_y,
output [7:0] out_stereo,
output out_is_val,
input [1:0] debug_selector,
output [9:0] debug_out_x,
output [9:0] debug_out_y,
output [7:0] debug_out,
output debug_out_is_val
);
localparam row_sz = 447;
localparam col_sz = 370;
wire [7:0] conv0_val;
wire [9:0] conv0_x;
wire [9:0] conv0_y;
wire is_conv0_val;
convolve #(3,row_sz,col_sz) my_convolver0(
.clk(clk),
.reset(reset),
.in_val(in_left),
.in_x(in_x),
.in_y(in_y),
.is_in_val(in_is_val),
.out_val(conv0_val),
.out_x(conv0_x),
.out_y(conv0_y),
.is_out_val(is_conv0_val),
.kernel({8'h01, 8'h02, 8'h01,
8'h02, 8'h04, 8'h02,
8'h01, 8'h02, 8'h01})
);
wire [7:0] conv1_val;
wire [9:0] conv1_x;
wire [9:0] conv1_y;
wire is_conv1_val;
convolve #(3,row_sz,col_sz) my_convolver1(
.clk(clk),
.reset(reset),
.in_val(in_right),
.in_x(in_x),
.in_y(in_y),
.is_in_val(in_is_val),
.out_val(conv1_val),
.out_x(conv1_x),
.out_y(conv1_y),
.is_out_val(is_conv1_val),
.kernel({8'h01, 8'h02, 8'h01,
8'h02, 8'h04, 8'h02,
8'h01, 8'h02, 8'h01})
);
wire [7:0] cen0_val;
wire [9:0] cen0_x;
wire [9:0] cen0_y;
wire is_cen0_val;
sp_census #(row_sz,col_sz) my_census0(
.clk(clk),
.reset(reset),
.thresh(census_thresh),
.in_val(conv0_val),
.in_x(conv0_x),
.in_y(conv0_y),
.is_in_val(is_conv0_val),
.out_val(cen0_val),
.out_x(cen0_x),
.out_y(cen0_y),
.is_out_val(is_cen0_val)
);
wire [7:0] cen1_val;
wire [9:0] cen1_x;
wire [9:0] cen1_y;
wire is_cen1_val;
sp_census #(row_sz,col_sz) my_census1(
.clk(clk),
.reset(reset),
.thresh(census_thresh),
.in_val(conv1_val),
.in_x(conv1_x),
.in_y(conv1_y),
.is_in_val(is_conv1_val),
.out_val(cen1_val),
.out_x(cen1_x),
.out_y(cen1_y),
.is_out_val(is_cen1_val)
);
wire [71:0] wdw0_val;
wire [9:0] wdw0_x;
wire [9:0] wdw0_y;
wire is_wdw0_val;
census_window #(3,row_sz,col_sz) my_wdw0(
.clk(clk),
.reset(reset),
.in_val(cen0_val),
.in_x(cen0_x),
.in_y(cen0_y),
.is_in_val(is_cen0_val),
.out_val(wdw0_val),
.out_x(wdw0_x),
.out_y(wdw0_y),
.is_out_val(is_wdw0_val)
);
wire [71:0] wdw1_val;
wire [9:0] wdw1_x;
wire [9:0] wdw1_y;
wire is_wdw1_val;
census_window #(3,row_sz,col_sz) my_wdw1(
.clk(clk),
.reset(reset),
.in_val(cen1_val),
.in_x(cen1_x),
.in_y(cen1_y),
.is_in_val(is_cen1_val),
.out_val(wdw1_val),
.out_x(wdw1_x),
.out_y(wdw1_y),
.is_out_val(is_wdw1_val)
);
wire [9:0] corr_out_x;
wire [9:0] corr_out_y;
wire [5:0] disp_out_val;
wire is_disp_out_val;
correlate #(row_sz, col_sz) my_corr(
.clk(clk),
.reset(reset),
.left_bitvec(wdw0_val),
.right_bitvec(wdw1_val),
.bitvec_val(is_wdw0_val & is_wdw1_val),
.input_x(wdw0_x),
.input_y(wdw0_y),
.out_x(corr_out_x),
.out_y(corr_out_y),
.disparity_val(is_disp_out_val),
.disparity(disp_out_val)
);
assign out_x = corr_out_x;
assign out_y = corr_out_y;
assign out_stereo = {disp_out_val, 2'b0};
assign out_is_val = is_disp_out_val;
reg [9:0] debug_out_x_reg;
reg [9:0] debug_out_y_reg;
reg [7:0] debug_out_reg;
reg debug_out_is_val_reg;
assign debug_out_x = debug_out_x_reg;
assign debug_out_y = debug_out_y_reg;
assign debug_out = debug_out_reg;
assign debug_out_is_val = debug_out_is_val_reg;
always @(*) begin
case (debug_selector)
2'd0: begin
debug_out_x_reg = in_x;
debug_out_y_reg = in_y;
debug_out_reg = in_right;
debug_out_is_val_reg = in_is_val;
end
2'd1: begin
debug_out_x_reg = conv1_x;
debug_out_y_reg = conv1_y;
debug_out_reg = conv1_val;
debug_out_is_val_reg = is_conv1_val;
end
2'd2: begin
debug_out_x_reg = cen1_x;
debug_out_y_reg = cen1_y;
debug_out_reg = cen1_val;
debug_out_is_val_reg = is_cen1_val;
end
2'd3: begin
debug_out_x_reg = corr_out_x;
debug_out_y_reg = corr_out_y;
debug_out_reg = {disp_out_val, 2'b0};
debug_out_is_val_reg = is_disp_out_val;
end
default: begin
debug_out_x_reg = corr_out_x;
debug_out_y_reg = corr_out_y;
debug_out_reg = {disp_out_val, 2'b0};
debug_out_is_val_reg = is_disp_out_val;
end
endcase
end
endmodule | module stereo(
input clk,
input reset,
input [7:0] census_thresh,
input [9:0] in_x,
input [9:0] in_y,
input [7:0] in_left,
input [7:0] in_right,
input in_is_val,
output [9:0] out_x,
output [9:0] out_y,
output [7:0] out_stereo,
output out_is_val,
input [1:0] debug_selector,
output [9:0] debug_out_x,
output [9:0] debug_out_y,
output [7:0] debug_out,
output debug_out_is_val
); |
localparam row_sz = 447;
localparam col_sz = 370;
wire [7:0] conv0_val;
wire [9:0] conv0_x;
wire [9:0] conv0_y;
wire is_conv0_val;
convolve #(3,row_sz,col_sz) my_convolver0(
.clk(clk),
.reset(reset),
.in_val(in_left),
.in_x(in_x),
.in_y(in_y),
.is_in_val(in_is_val),
.out_val(conv0_val),
.out_x(conv0_x),
.out_y(conv0_y),
.is_out_val(is_conv0_val),
.kernel({8'h01, 8'h02, 8'h01,
8'h02, 8'h04, 8'h02,
8'h01, 8'h02, 8'h01})
);
wire [7:0] conv1_val;
wire [9:0] conv1_x;
wire [9:0] conv1_y;
wire is_conv1_val;
convolve #(3,row_sz,col_sz) my_convolver1(
.clk(clk),
.reset(reset),
.in_val(in_right),
.in_x(in_x),
.in_y(in_y),
.is_in_val(in_is_val),
.out_val(conv1_val),
.out_x(conv1_x),
.out_y(conv1_y),
.is_out_val(is_conv1_val),
.kernel({8'h01, 8'h02, 8'h01,
8'h02, 8'h04, 8'h02,
8'h01, 8'h02, 8'h01})
);
wire [7:0] cen0_val;
wire [9:0] cen0_x;
wire [9:0] cen0_y;
wire is_cen0_val;
sp_census #(row_sz,col_sz) my_census0(
.clk(clk),
.reset(reset),
.thresh(census_thresh),
.in_val(conv0_val),
.in_x(conv0_x),
.in_y(conv0_y),
.is_in_val(is_conv0_val),
.out_val(cen0_val),
.out_x(cen0_x),
.out_y(cen0_y),
.is_out_val(is_cen0_val)
);
wire [7:0] cen1_val;
wire [9:0] cen1_x;
wire [9:0] cen1_y;
wire is_cen1_val;
sp_census #(row_sz,col_sz) my_census1(
.clk(clk),
.reset(reset),
.thresh(census_thresh),
.in_val(conv1_val),
.in_x(conv1_x),
.in_y(conv1_y),
.is_in_val(is_conv1_val),
.out_val(cen1_val),
.out_x(cen1_x),
.out_y(cen1_y),
.is_out_val(is_cen1_val)
);
wire [71:0] wdw0_val;
wire [9:0] wdw0_x;
wire [9:0] wdw0_y;
wire is_wdw0_val;
census_window #(3,row_sz,col_sz) my_wdw0(
.clk(clk),
.reset(reset),
.in_val(cen0_val),
.in_x(cen0_x),
.in_y(cen0_y),
.is_in_val(is_cen0_val),
.out_val(wdw0_val),
.out_x(wdw0_x),
.out_y(wdw0_y),
.is_out_val(is_wdw0_val)
);
wire [71:0] wdw1_val;
wire [9:0] wdw1_x;
wire [9:0] wdw1_y;
wire is_wdw1_val;
census_window #(3,row_sz,col_sz) my_wdw1(
.clk(clk),
.reset(reset),
.in_val(cen1_val),
.in_x(cen1_x),
.in_y(cen1_y),
.is_in_val(is_cen1_val),
.out_val(wdw1_val),
.out_x(wdw1_x),
.out_y(wdw1_y),
.is_out_val(is_wdw1_val)
);
wire [9:0] corr_out_x;
wire [9:0] corr_out_y;
wire [5:0] disp_out_val;
wire is_disp_out_val;
correlate #(row_sz, col_sz) my_corr(
.clk(clk),
.reset(reset),
.left_bitvec(wdw0_val),
.right_bitvec(wdw1_val),
.bitvec_val(is_wdw0_val & is_wdw1_val),
.input_x(wdw0_x),
.input_y(wdw0_y),
.out_x(corr_out_x),
.out_y(corr_out_y),
.disparity_val(is_disp_out_val),
.disparity(disp_out_val)
);
assign out_x = corr_out_x;
assign out_y = corr_out_y;
assign out_stereo = {disp_out_val, 2'b0};
assign out_is_val = is_disp_out_val;
reg [9:0] debug_out_x_reg;
reg [9:0] debug_out_y_reg;
reg [7:0] debug_out_reg;
reg debug_out_is_val_reg;
assign debug_out_x = debug_out_x_reg;
assign debug_out_y = debug_out_y_reg;
assign debug_out = debug_out_reg;
assign debug_out_is_val = debug_out_is_val_reg;
always @(*) begin
case (debug_selector)
2'd0: begin
debug_out_x_reg = in_x;
debug_out_y_reg = in_y;
debug_out_reg = in_right;
debug_out_is_val_reg = in_is_val;
end
2'd1: begin
debug_out_x_reg = conv1_x;
debug_out_y_reg = conv1_y;
debug_out_reg = conv1_val;
debug_out_is_val_reg = is_conv1_val;
end
2'd2: begin
debug_out_x_reg = cen1_x;
debug_out_y_reg = cen1_y;
debug_out_reg = cen1_val;
debug_out_is_val_reg = is_cen1_val;
end
2'd3: begin
debug_out_x_reg = corr_out_x;
debug_out_y_reg = corr_out_y;
debug_out_reg = {disp_out_val, 2'b0};
debug_out_is_val_reg = is_disp_out_val;
end
default: begin
debug_out_x_reg = corr_out_x;
debug_out_y_reg = corr_out_y;
debug_out_reg = {disp_out_val, 2'b0};
debug_out_is_val_reg = is_disp_out_val;
end
endcase
end
endmodule | 1 |
4,213 | data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v | 109,209,652 | convolve.v | v | 191 | 139 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:62: Operator OR expects 1600 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance convolve\n is_buf_val <= (is_buf_val << 1) | 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:90: Cannot find file containing module: \'shift_reg\'\n shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.v\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.sv\n shift_reg\n shift_reg.v\n shift_reg.sv\n obj_dir/shift_reg\n obj_dir/shift_reg.v\n obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:80: Cannot find file containing module: \'shift_reg\'\n shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:149: Cannot find file containing module: \'convolve_mult\'\n convolve_mult my_mult(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 2,413 | module | module convolve #(parameter KRNL_SZ = 5, parameter ROW_SZ = 320, parameter COL_SZ = 240)(
input clk,
input reset,
input [7:0] in_val,
input [9:0] in_x,
input [9:0] in_y,
input is_in_val,
output [7:0] out_val,
output reg [9:0] out_x,
output reg [9:0] out_y,
output reg is_out_val,
input signed [(KRNL_SZ*KRNL_SZ*8)-1 : 0] kernel
);
reg [7:0] conv_r [(KRNL_SZ*KRNL_SZ)-1 : 0];
wire [7:0] carry_over_wires [KRNL_SZ-2 : 0];
reg [(ROW_SZ*KRNL_SZ)-1 : 0] is_buf_val;
reg [9:0] in_x_reg;
reg [9:0] in_y_reg;
always@ (posedge clk) begin
if (is_in_val) begin
in_x_reg <= in_x;
in_y_reg <= in_y;
end
end
wire [9:0] out_x_stg0;
wire [9:0] out_y_stg0;
assign out_x_stg0 = in_x_reg < (ROW_SZ-(KRNL_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(KRNL_SZ/2)-1) : in_x_reg - (ROW_SZ-(KRNL_SZ/2)-1);
assign out_y_stg0 = out_x <= (KRNL_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);
always@ (posedge clk) begin
if (reset) begin
is_buf_val <= 0;
end
else begin
if (is_in_val) begin
is_buf_val <= (is_buf_val << 1) | 1'b1;
end
end
end
wire is_out_val_stg0;
assign is_out_val_stg0 = is_in_val & is_buf_val[ROW_SZ*(KRNL_SZ/2) + (ROW_SZ-KRNL_SZ) + (KRNL_SZ/2)];
genvar i, j;
generate
for (i = 0; i < KRNL_SZ; i = i + 1) begin: SHIFT_BUF
wire [7:0] row_buf_sr_out;
if (i == KRNL_SZ-1) begin
shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(in_val),
.sr_out(row_buf_sr_out)
);
end
else begin
shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(carry_over_wires[i]),
.sr_out(row_buf_sr_out)
);
end
for (j = 0; j < KRNL_SZ; j = j + 1) begin: CONV_REGS
if (j == 0) begin
if(i != 0) begin
assign carry_over_wires[i-1] = conv_r[KRNL_SZ*i + j];
end
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
end
end
end
else if (j == KRNL_SZ-1) begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= row_buf_sr_out;
end
end
end
else begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
end
end
end
end
end
endgenerate
wire signed [15:0] mult [(KRNL_SZ*KRNL_SZ)-1 : 0];
reg signed [15:0] mult_reg [(KRNL_SZ*KRNL_SZ)-1 : 0];
genvar k, l;
generate
for (k = 0; k < KRNL_SZ; k = k + 1) begin: MULT_OUTER
for (l = 0; l < KRNL_SZ; l = l + 1) begin: MULT_INNER
convolve_mult my_mult(
.out(mult[KRNL_SZ*k + l]),
.a(conv_r[KRNL_SZ*k + l]),
.b(kernel[((KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l)*8 - 1) : (KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l - 1)*8])
);
always @(posedge clk) begin
mult_reg[KRNL_SZ*k + l] <= mult[KRNL_SZ*k + l];
end
end
end
endgenerate
integer sum_i;
always @(posedge clk) begin
if (reset) begin
out_x <= 0;
out_y <= 0;
is_out_val <= 0;
end
else begin
out_x <= out_x_stg0;
out_y <= out_y_stg0;
is_out_val <= is_out_val_stg0;
end
end
reg signed [15:0] conv_sum;
always@ (*) begin
conv_sum = 16'b0;
for(sum_i = 0; sum_i < (KRNL_SZ*KRNL_SZ); sum_i = sum_i + 1) begin
conv_sum = conv_sum + mult_reg[sum_i];
end
end
assign out_val = conv_sum[15] ? 8'd0 : conv_sum[11:4];
endmodule | module convolve #(parameter KRNL_SZ = 5, parameter ROW_SZ = 320, parameter COL_SZ = 240)(
input clk,
input reset,
input [7:0] in_val,
input [9:0] in_x,
input [9:0] in_y,
input is_in_val,
output [7:0] out_val,
output reg [9:0] out_x,
output reg [9:0] out_y,
output reg is_out_val,
input signed [(KRNL_SZ*KRNL_SZ*8)-1 : 0] kernel
); |
reg [7:0] conv_r [(KRNL_SZ*KRNL_SZ)-1 : 0];
wire [7:0] carry_over_wires [KRNL_SZ-2 : 0];
reg [(ROW_SZ*KRNL_SZ)-1 : 0] is_buf_val;
reg [9:0] in_x_reg;
reg [9:0] in_y_reg;
always@ (posedge clk) begin
if (is_in_val) begin
in_x_reg <= in_x;
in_y_reg <= in_y;
end
end
wire [9:0] out_x_stg0;
wire [9:0] out_y_stg0;
assign out_x_stg0 = in_x_reg < (ROW_SZ-(KRNL_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(KRNL_SZ/2)-1) : in_x_reg - (ROW_SZ-(KRNL_SZ/2)-1);
assign out_y_stg0 = out_x <= (KRNL_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);
always@ (posedge clk) begin
if (reset) begin
is_buf_val <= 0;
end
else begin
if (is_in_val) begin
is_buf_val <= (is_buf_val << 1) | 1'b1;
end
end
end
wire is_out_val_stg0;
assign is_out_val_stg0 = is_in_val & is_buf_val[ROW_SZ*(KRNL_SZ/2) + (ROW_SZ-KRNL_SZ) + (KRNL_SZ/2)];
genvar i, j;
generate
for (i = 0; i < KRNL_SZ; i = i + 1) begin: SHIFT_BUF
wire [7:0] row_buf_sr_out;
if (i == KRNL_SZ-1) begin
shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(in_val),
.sr_out(row_buf_sr_out)
);
end
else begin
shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(carry_over_wires[i]),
.sr_out(row_buf_sr_out)
);
end
for (j = 0; j < KRNL_SZ; j = j + 1) begin: CONV_REGS
if (j == 0) begin
if(i != 0) begin
assign carry_over_wires[i-1] = conv_r[KRNL_SZ*i + j];
end
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
end
end
end
else if (j == KRNL_SZ-1) begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= row_buf_sr_out;
end
end
end
else begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
end
end
end
end
end
endgenerate
wire signed [15:0] mult [(KRNL_SZ*KRNL_SZ)-1 : 0];
reg signed [15:0] mult_reg [(KRNL_SZ*KRNL_SZ)-1 : 0];
genvar k, l;
generate
for (k = 0; k < KRNL_SZ; k = k + 1) begin: MULT_OUTER
for (l = 0; l < KRNL_SZ; l = l + 1) begin: MULT_INNER
convolve_mult my_mult(
.out(mult[KRNL_SZ*k + l]),
.a(conv_r[KRNL_SZ*k + l]),
.b(kernel[((KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l)*8 - 1) : (KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l - 1)*8])
);
always @(posedge clk) begin
mult_reg[KRNL_SZ*k + l] <= mult[KRNL_SZ*k + l];
end
end
end
endgenerate
integer sum_i;
always @(posedge clk) begin
if (reset) begin
out_x <= 0;
out_y <= 0;
is_out_val <= 0;
end
else begin
out_x <= out_x_stg0;
out_y <= out_y_stg0;
is_out_val <= is_out_val_stg0;
end
end
reg signed [15:0] conv_sum;
always@ (*) begin
conv_sum = 16'b0;
for(sum_i = 0; sum_i < (KRNL_SZ*KRNL_SZ); sum_i = sum_i + 1) begin
conv_sum = conv_sum + mult_reg[sum_i];
end
end
assign out_val = conv_sum[15] ? 8'd0 : conv_sum[11:4];
endmodule | 1 |
4,214 | data/full_repos/permissive/109209652/verilog/convolve_census/convolve_mult.v | 109,209,652 | convolve_mult.v | v | 21 | 66 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/f6fba0fd-a186-4b1f-81a0-b802f7631124.xml | null | 2,414 | module | module convolve_mult (out, a, b);
output signed [15:0] out;
input [7:0] a;
input signed [7:0] b;
wire signed [15:0] out;
wire signed [17:0] mult_out;
wire signed [8:0] a_se;
wire signed [8:0] b_se;
assign a_se = {1'b0, a};
assign b_se = {b[7], b};
assign mult_out = a_se * b_se;
assign out = {mult_out[17], mult_out[14:0]};
endmodule | module convolve_mult (out, a, b); |
output signed [15:0] out;
input [7:0] a;
input signed [7:0] b;
wire signed [15:0] out;
wire signed [17:0] mult_out;
wire signed [8:0] a_se;
wire signed [8:0] b_se;
assign a_se = {1'b0, a};
assign b_se = {b[7], b};
assign mult_out = a_se * b_se;
assign out = {mult_out[17], mult_out[14:0]};
endmodule | 1 |
4,216 | data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v | 109,209,652 | sp_census.v | v | 146 | 131 | [] | [] | [] | [(2, 146)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:61: Operator OR expects 1600 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance sp_census\n is_buf_val <= (is_buf_val << 1) | 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:88: Cannot find file containing module: \'shift_reg\'\n shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.v\n data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.sv\n shift_reg\n shift_reg.v\n shift_reg.sv\n obj_dir/shift_reg\n obj_dir/shift_reg.v\n obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:78: Cannot find file containing module: \'shift_reg\'\n shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 2,416 | module | module sp_census #(parameter ROW_SZ = 320, parameter COL_SZ = 240)(
input clk,
input reset,
input [7:0] thresh,
input [7:0] in_val,
input [9:0] in_x,
input [9:0] in_y,
input is_in_val,
output [7:0] out_val,
output [9:0] out_x,
output [9:0] out_y,
output is_out_val
);
localparam CEN_SZ = 5;
reg [7:0] conv_r [(CEN_SZ*CEN_SZ)-1 : 0];
wire [7:0] carry_over_wires [CEN_SZ-2 : 0];
reg [(ROW_SZ*CEN_SZ)-1 : 0] is_buf_val;
reg [9:0] in_x_reg;
reg [9:0] in_y_reg;
always@ (posedge clk) begin
if (is_in_val) begin
in_x_reg <= in_x;
in_y_reg <= in_y;
end
end
reg [7:0] threshold;
always @(posedge clk) begin
threshold <= thresh;
end
assign out_x = in_x_reg < (ROW_SZ-(CEN_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(CEN_SZ/2)-1) : in_x_reg - (ROW_SZ-(CEN_SZ/2)-1);
assign out_y = out_x <= (CEN_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);
always@ (posedge clk) begin
if (reset) begin
is_buf_val <= 0;
end
else begin
if (is_in_val) begin
is_buf_val <= (is_buf_val << 1) | 1'b1;
end
end
end
assign is_out_val = is_in_val & is_buf_val[ROW_SZ*(CEN_SZ/2) + (ROW_SZ-CEN_SZ) + (CEN_SZ/2)];
genvar i, j;
generate
for (i = 0; i < CEN_SZ; i = i + 1) begin: SHIFT_BUF
wire [7:0] row_buf_sr_out;
if (i == CEN_SZ-1) begin
shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(in_val),
.sr_out(row_buf_sr_out)
);
end
else begin
shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(carry_over_wires[i]),
.sr_out(row_buf_sr_out)
);
end
for (j = 0; j < CEN_SZ; j = j + 1) begin: CONV_REGS
if (j == 0) begin
if(i != 0) begin
assign carry_over_wires[i-1] = conv_r[CEN_SZ*i + j];
end
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
end
end
end
else if (j == CEN_SZ-1) begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= row_buf_sr_out;
end
end
end
else begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
end
end
end
end
end
endgenerate
assign out_val[0] = (conv_r[CEN_SZ*0 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[1] = (conv_r[CEN_SZ*0 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[2] = (conv_r[CEN_SZ*0 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[3] = (conv_r[CEN_SZ*2 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[4] = (conv_r[CEN_SZ*2 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[5] = (conv_r[CEN_SZ*4 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[6] = (conv_r[CEN_SZ*4 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[7] = (conv_r[CEN_SZ*4 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
endmodule | module sp_census #(parameter ROW_SZ = 320, parameter COL_SZ = 240)(
input clk,
input reset,
input [7:0] thresh,
input [7:0] in_val,
input [9:0] in_x,
input [9:0] in_y,
input is_in_val,
output [7:0] out_val,
output [9:0] out_x,
output [9:0] out_y,
output is_out_val
); |
localparam CEN_SZ = 5;
reg [7:0] conv_r [(CEN_SZ*CEN_SZ)-1 : 0];
wire [7:0] carry_over_wires [CEN_SZ-2 : 0];
reg [(ROW_SZ*CEN_SZ)-1 : 0] is_buf_val;
reg [9:0] in_x_reg;
reg [9:0] in_y_reg;
always@ (posedge clk) begin
if (is_in_val) begin
in_x_reg <= in_x;
in_y_reg <= in_y;
end
end
reg [7:0] threshold;
always @(posedge clk) begin
threshold <= thresh;
end
assign out_x = in_x_reg < (ROW_SZ-(CEN_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(CEN_SZ/2)-1) : in_x_reg - (ROW_SZ-(CEN_SZ/2)-1);
assign out_y = out_x <= (CEN_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);
always@ (posedge clk) begin
if (reset) begin
is_buf_val <= 0;
end
else begin
if (is_in_val) begin
is_buf_val <= (is_buf_val << 1) | 1'b1;
end
end
end
assign is_out_val = is_in_val & is_buf_val[ROW_SZ*(CEN_SZ/2) + (ROW_SZ-CEN_SZ) + (CEN_SZ/2)];
genvar i, j;
generate
for (i = 0; i < CEN_SZ; i = i + 1) begin: SHIFT_BUF
wire [7:0] row_buf_sr_out;
if (i == CEN_SZ-1) begin
shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(in_val),
.sr_out(row_buf_sr_out)
);
end
else begin
shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
.clk(clk),
.shift(is_in_val),
.sr_in(carry_over_wires[i]),
.sr_out(row_buf_sr_out)
);
end
for (j = 0; j < CEN_SZ; j = j + 1) begin: CONV_REGS
if (j == 0) begin
if(i != 0) begin
assign carry_over_wires[i-1] = conv_r[CEN_SZ*i + j];
end
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
end
end
end
else if (j == CEN_SZ-1) begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= row_buf_sr_out;
end
end
end
else begin
always@ (posedge clk) begin
if (is_in_val) begin
conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
end
end
end
end
end
endgenerate
assign out_val[0] = (conv_r[CEN_SZ*0 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[1] = (conv_r[CEN_SZ*0 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[2] = (conv_r[CEN_SZ*0 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[3] = (conv_r[CEN_SZ*2 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[4] = (conv_r[CEN_SZ*2 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[5] = (conv_r[CEN_SZ*4 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[6] = (conv_r[CEN_SZ*4 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
assign out_val[7] = (conv_r[CEN_SZ*4 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
endmodule | 1 |
4,217 | data/full_repos/permissive/109209652/verilog/correlation/correlate.v | 109,209,652 | correlate.v | v | 307 | 92 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/correlation/correlate.v:79: Operator OR expects 64 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance correlate\n buffer_valid <= (buffer_valid << 1) | 1\'b1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/correlation/correlate.v:103: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance correlate\n temp_dval = temp_dval + xor_output[i];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,417 | module | module correlate #(parameter F_WIDTH = 320, parameter F_HEIGHT = 240)(
clk, reset,
left_bitvec, right_bitvec, bitvec_val,
input_x, input_y,
out_x, out_y,
disparity_val, disparity
);
localparam disp = 64;
localparam bv_len = 72;
input clk;
input reset;
input [bv_len-1:0] left_bitvec;
input [bv_len-1:0] right_bitvec;
input bitvec_val;
input [9:0] input_x;
input [9:0] input_y;
output reg [9:0] out_x;
output reg [9:0] out_y;
output reg disparity_val;
output reg [$clog2(disp)-1:0] disparity;
reg bitvec_val_reg;
reg [9:0] input_x_reg;
reg [9:0] input_y_reg;
always @(posedge clk) begin
if (bitvec_val) begin
input_x_reg <= input_x;
input_y_reg <= input_y;
end
end
reg [bv_len-1:0] left_buffer[disp-1:0];
reg [bv_len-1:0] right_buffer[disp-1:0];
reg [disp-1:0] buffer_valid;
genvar i;
generate
for (i = 0; i < disp-1; i = i + 1) begin: SHIFT_BUFFER
always @(posedge clk) begin
if (bitvec_val) begin
left_buffer[i] <= left_buffer[i+1];
right_buffer[i] <= right_buffer[i+1];
end
end
end
endgenerate
always @(posedge clk) begin
if (bitvec_val) begin
left_buffer[disp-1] <= left_bitvec;
right_buffer[disp-1] <= right_bitvec;
end
if (reset) begin
buffer_valid <= 0;
end
else begin
if (bitvec_val)
buffer_valid <= (buffer_valid << 1) | 1'b1;
end
end
parameter dval_width = $clog2(bv_len);
reg [dval_width-1:0] disparity_value[disp-1:0];
reg xor_sum_valid;
reg [9:0] xor_sum_x;
reg [9:0] xor_sum_y;
genvar j;
generate
for (j = 0; j < disp; j = j + 1) begin: XOR_AND_ADD
wire [bv_len-1:0] xor_output;
assign xor_output = left_buffer[j] ^ right_buffer[0];
integer i;
reg [dval_width-1:0] temp_dval;
always @(posedge clk) begin
temp_dval = 0;
for (i=0; i<bv_len; i=i+1)
temp_dval = temp_dval + xor_output[i];
disparity_value[j] <= temp_dval;
end
end
endgenerate
reg [$clog2(disp)-1:0] L1_disparity_idx[disp/2-1:0];
reg [dval_width-1:0] L1_disparity_val[disp/2-1:0];
reg L1_disp_valid;
reg [9:0] L1_disp_x;
reg [9:0] L1_disp_y;
genvar a;
generate
for (a = 0; a < disp/2; a = a + 1) begin: COMPARE_LEVEL1
always @(posedge clk) begin
if (disparity_value[a*2] < disparity_value[a*2+1]) begin
L1_disparity_idx[a] <= a*2;
L1_disparity_val[a] <= disparity_value[a*2];
end
else begin
L1_disparity_idx[a] <= a*2 + 1;
L1_disparity_val[a] <= disparity_value[a*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L2_disparity_idx[disp/4-1:0];
reg [dval_width-1:0] L2_disparity_val[disp/4-1:0];
reg L2_disp_valid;
reg [9:0] L2_disp_x;
reg [9:0] L2_disp_y;
genvar b;
generate
for (b = 0; b < disp/4; b = b + 1) begin: COMPARE_LEVEL2
always @(posedge clk) begin
if (L1_disparity_val[b*2] < L1_disparity_val[b*2+1]) begin
L2_disparity_idx[b] <= L1_disparity_idx[b*2];
L2_disparity_val[b] <= L1_disparity_val[b*2];
end
else begin
L2_disparity_idx[b] <= L1_disparity_idx[b*2+1];
L2_disparity_val[b] <= L1_disparity_val[b*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L3_disparity_idx[disp/8-1:0];
reg [dval_width-1:0] L3_disparity_val[disp/8-1:0];
reg L3_disp_valid;
reg [9:0] L3_disp_x;
reg [9:0] L3_disp_y;
genvar c;
generate
for (c = 0; c < disp/8; c = c + 1) begin: COMPARE_LEVEL3
always @(posedge clk) begin
if (L2_disparity_val[c*2] < L2_disparity_val[c*2+1]) begin
L3_disparity_idx[c] <= L2_disparity_idx[c*2];
L3_disparity_val[c] <= L2_disparity_val[c*2];
end
else begin
L3_disparity_idx[c] <= L2_disparity_idx[c*2+1];
L3_disparity_val[c] <= L2_disparity_val[c*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L4_disparity_idx[disp/16-1:0];
reg [dval_width-1:0] L4_disparity_val[disp/16-1:0];
reg L4_disp_valid;
reg [9:0] L4_disp_x;
reg [9:0] L4_disp_y;
genvar d;
generate
for (d = 0; d < disp/16; d = d + 1) begin: COMPARE_LEVEL4
always @(posedge clk) begin
if (L3_disparity_val[d*2] < L3_disparity_val[d*2+1]) begin
L4_disparity_idx[d] <= L3_disparity_idx[d*2];
L4_disparity_val[d] <= L3_disparity_val[d*2];
end
else begin
L4_disparity_idx[d] <= L3_disparity_idx[d*2+1];
L4_disparity_val[d] <= L3_disparity_val[d*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L5_disparity_idx[disp/32-1:0];
reg [dval_width-1:0] L5_disparity_val[disp/32-1:0];
reg L5_disp_valid;
reg [9:0] L5_disp_x;
reg [9:0] L5_disp_y;
genvar e;
generate
for (e = 0; e < disp/32; e = e + 1) begin: COMPARE_LEVEL5
always @(posedge clk) begin
if (L4_disparity_val[e*2] < L4_disparity_val[e*2+1]) begin
L5_disparity_idx[e] <= L4_disparity_idx[e*2];
L5_disparity_val[e] <= L4_disparity_val[e*2];
end
else begin
L5_disparity_idx[e] <= L4_disparity_idx[e*2+1];
L5_disparity_val[e] <= L4_disparity_val[e*2+1];
end
end
end
endgenerate
always @(posedge clk) begin
if (L5_disparity_val[0] < L5_disparity_val[1]) begin
disparity <= L5_disparity_idx[0];
end
else begin
disparity <= L5_disparity_idx[1];
end
end
always @(posedge clk) begin
if (reset) begin
bitvec_val_reg <= 0;
xor_sum_valid <= 0;
L1_disp_valid <= 0;
L2_disp_valid <= 0;
L3_disp_valid <= 0;
L4_disp_valid <= 0;
L5_disp_valid <= 0;
disparity_val <= 0;
end
else begin
bitvec_val_reg <= bitvec_val;
xor_sum_valid <= (&buffer_valid) & bitvec_val_reg;
L1_disp_valid <= xor_sum_valid;
L2_disp_valid <= L1_disp_valid;
L3_disp_valid <= L2_disp_valid;
L4_disp_valid <= L3_disp_valid;
L5_disp_valid <= L4_disp_valid;
disparity_val <= L5_disp_valid;
end
end
always @(posedge clk) begin
if (reset) begin
xor_sum_x <= 0;
xor_sum_y <= 0;
L1_disp_x <= 0;
L1_disp_y <= 0;
L2_disp_x <= 0;
L2_disp_y <= 0;
L3_disp_x <= 0;
L3_disp_y <= 0;
L4_disp_x <= 0;
L4_disp_y <= 0;
L5_disp_x <= 0;
L5_disp_y <= 0;
out_x <= 0;
out_y <= 0;
end
else begin
xor_sum_x <= input_x_reg < (disp - 1) ?
F_WIDTH - (disp - (input_x_reg + 1)) : input_x_reg - (disp - 1);
xor_sum_y <= input_x_reg < (disp - 1) ?
(input_y_reg == 0 ? F_HEIGHT - 1 : input_y_reg - 1) : input_y_reg;
L1_disp_x <= xor_sum_x;
L1_disp_y <= xor_sum_y;
L2_disp_x <= L1_disp_x;
L2_disp_y <= L1_disp_y;
L3_disp_x <= L2_disp_x;
L3_disp_y <= L2_disp_y;
L4_disp_x <= L3_disp_x;
L4_disp_y <= L3_disp_y;
L5_disp_x <= L4_disp_x;
L5_disp_y <= L4_disp_y;
out_x <= L5_disp_x;
out_y <= L5_disp_y;
end
end
endmodule | module correlate #(parameter F_WIDTH = 320, parameter F_HEIGHT = 240)(
clk, reset,
left_bitvec, right_bitvec, bitvec_val,
input_x, input_y,
out_x, out_y,
disparity_val, disparity
); |
localparam disp = 64;
localparam bv_len = 72;
input clk;
input reset;
input [bv_len-1:0] left_bitvec;
input [bv_len-1:0] right_bitvec;
input bitvec_val;
input [9:0] input_x;
input [9:0] input_y;
output reg [9:0] out_x;
output reg [9:0] out_y;
output reg disparity_val;
output reg [$clog2(disp)-1:0] disparity;
reg bitvec_val_reg;
reg [9:0] input_x_reg;
reg [9:0] input_y_reg;
always @(posedge clk) begin
if (bitvec_val) begin
input_x_reg <= input_x;
input_y_reg <= input_y;
end
end
reg [bv_len-1:0] left_buffer[disp-1:0];
reg [bv_len-1:0] right_buffer[disp-1:0];
reg [disp-1:0] buffer_valid;
genvar i;
generate
for (i = 0; i < disp-1; i = i + 1) begin: SHIFT_BUFFER
always @(posedge clk) begin
if (bitvec_val) begin
left_buffer[i] <= left_buffer[i+1];
right_buffer[i] <= right_buffer[i+1];
end
end
end
endgenerate
always @(posedge clk) begin
if (bitvec_val) begin
left_buffer[disp-1] <= left_bitvec;
right_buffer[disp-1] <= right_bitvec;
end
if (reset) begin
buffer_valid <= 0;
end
else begin
if (bitvec_val)
buffer_valid <= (buffer_valid << 1) | 1'b1;
end
end
parameter dval_width = $clog2(bv_len);
reg [dval_width-1:0] disparity_value[disp-1:0];
reg xor_sum_valid;
reg [9:0] xor_sum_x;
reg [9:0] xor_sum_y;
genvar j;
generate
for (j = 0; j < disp; j = j + 1) begin: XOR_AND_ADD
wire [bv_len-1:0] xor_output;
assign xor_output = left_buffer[j] ^ right_buffer[0];
integer i;
reg [dval_width-1:0] temp_dval;
always @(posedge clk) begin
temp_dval = 0;
for (i=0; i<bv_len; i=i+1)
temp_dval = temp_dval + xor_output[i];
disparity_value[j] <= temp_dval;
end
end
endgenerate
reg [$clog2(disp)-1:0] L1_disparity_idx[disp/2-1:0];
reg [dval_width-1:0] L1_disparity_val[disp/2-1:0];
reg L1_disp_valid;
reg [9:0] L1_disp_x;
reg [9:0] L1_disp_y;
genvar a;
generate
for (a = 0; a < disp/2; a = a + 1) begin: COMPARE_LEVEL1
always @(posedge clk) begin
if (disparity_value[a*2] < disparity_value[a*2+1]) begin
L1_disparity_idx[a] <= a*2;
L1_disparity_val[a] <= disparity_value[a*2];
end
else begin
L1_disparity_idx[a] <= a*2 + 1;
L1_disparity_val[a] <= disparity_value[a*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L2_disparity_idx[disp/4-1:0];
reg [dval_width-1:0] L2_disparity_val[disp/4-1:0];
reg L2_disp_valid;
reg [9:0] L2_disp_x;
reg [9:0] L2_disp_y;
genvar b;
generate
for (b = 0; b < disp/4; b = b + 1) begin: COMPARE_LEVEL2
always @(posedge clk) begin
if (L1_disparity_val[b*2] < L1_disparity_val[b*2+1]) begin
L2_disparity_idx[b] <= L1_disparity_idx[b*2];
L2_disparity_val[b] <= L1_disparity_val[b*2];
end
else begin
L2_disparity_idx[b] <= L1_disparity_idx[b*2+1];
L2_disparity_val[b] <= L1_disparity_val[b*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L3_disparity_idx[disp/8-1:0];
reg [dval_width-1:0] L3_disparity_val[disp/8-1:0];
reg L3_disp_valid;
reg [9:0] L3_disp_x;
reg [9:0] L3_disp_y;
genvar c;
generate
for (c = 0; c < disp/8; c = c + 1) begin: COMPARE_LEVEL3
always @(posedge clk) begin
if (L2_disparity_val[c*2] < L2_disparity_val[c*2+1]) begin
L3_disparity_idx[c] <= L2_disparity_idx[c*2];
L3_disparity_val[c] <= L2_disparity_val[c*2];
end
else begin
L3_disparity_idx[c] <= L2_disparity_idx[c*2+1];
L3_disparity_val[c] <= L2_disparity_val[c*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L4_disparity_idx[disp/16-1:0];
reg [dval_width-1:0] L4_disparity_val[disp/16-1:0];
reg L4_disp_valid;
reg [9:0] L4_disp_x;
reg [9:0] L4_disp_y;
genvar d;
generate
for (d = 0; d < disp/16; d = d + 1) begin: COMPARE_LEVEL4
always @(posedge clk) begin
if (L3_disparity_val[d*2] < L3_disparity_val[d*2+1]) begin
L4_disparity_idx[d] <= L3_disparity_idx[d*2];
L4_disparity_val[d] <= L3_disparity_val[d*2];
end
else begin
L4_disparity_idx[d] <= L3_disparity_idx[d*2+1];
L4_disparity_val[d] <= L3_disparity_val[d*2+1];
end
end
end
endgenerate
reg [$clog2(disp)-1:0] L5_disparity_idx[disp/32-1:0];
reg [dval_width-1:0] L5_disparity_val[disp/32-1:0];
reg L5_disp_valid;
reg [9:0] L5_disp_x;
reg [9:0] L5_disp_y;
genvar e;
generate
for (e = 0; e < disp/32; e = e + 1) begin: COMPARE_LEVEL5
always @(posedge clk) begin
if (L4_disparity_val[e*2] < L4_disparity_val[e*2+1]) begin
L5_disparity_idx[e] <= L4_disparity_idx[e*2];
L5_disparity_val[e] <= L4_disparity_val[e*2];
end
else begin
L5_disparity_idx[e] <= L4_disparity_idx[e*2+1];
L5_disparity_val[e] <= L4_disparity_val[e*2+1];
end
end
end
endgenerate
always @(posedge clk) begin
if (L5_disparity_val[0] < L5_disparity_val[1]) begin
disparity <= L5_disparity_idx[0];
end
else begin
disparity <= L5_disparity_idx[1];
end
end
always @(posedge clk) begin
if (reset) begin
bitvec_val_reg <= 0;
xor_sum_valid <= 0;
L1_disp_valid <= 0;
L2_disp_valid <= 0;
L3_disp_valid <= 0;
L4_disp_valid <= 0;
L5_disp_valid <= 0;
disparity_val <= 0;
end
else begin
bitvec_val_reg <= bitvec_val;
xor_sum_valid <= (&buffer_valid) & bitvec_val_reg;
L1_disp_valid <= xor_sum_valid;
L2_disp_valid <= L1_disp_valid;
L3_disp_valid <= L2_disp_valid;
L4_disp_valid <= L3_disp_valid;
L5_disp_valid <= L4_disp_valid;
disparity_val <= L5_disp_valid;
end
end
always @(posedge clk) begin
if (reset) begin
xor_sum_x <= 0;
xor_sum_y <= 0;
L1_disp_x <= 0;
L1_disp_y <= 0;
L2_disp_x <= 0;
L2_disp_y <= 0;
L3_disp_x <= 0;
L3_disp_y <= 0;
L4_disp_x <= 0;
L4_disp_y <= 0;
L5_disp_x <= 0;
L5_disp_y <= 0;
out_x <= 0;
out_y <= 0;
end
else begin
xor_sum_x <= input_x_reg < (disp - 1) ?
F_WIDTH - (disp - (input_x_reg + 1)) : input_x_reg - (disp - 1);
xor_sum_y <= input_x_reg < (disp - 1) ?
(input_y_reg == 0 ? F_HEIGHT - 1 : input_y_reg - 1) : input_y_reg;
L1_disp_x <= xor_sum_x;
L1_disp_y <= xor_sum_y;
L2_disp_x <= L1_disp_x;
L2_disp_y <= L1_disp_y;
L3_disp_x <= L2_disp_x;
L3_disp_y <= L2_disp_y;
L4_disp_x <= L3_disp_x;
L4_disp_y <= L3_disp_y;
L5_disp_x <= L4_disp_x;
L5_disp_y <= L4_disp_y;
out_x <= L5_disp_x;
out_y <= L5_disp_y;
end
end
endmodule | 1 |
4,220 | data/full_repos/permissive/109209652/verilog/modelsim/testbench.v | 109,209,652 | testbench.v | v | 211 | 59 | [] | [] | [] | null | line:209: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:208: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:42: Cannot find file containing module: \'cam_sim\'\n cam_sim #(0,row_sz,col_sz) my_cam0(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim\n data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim.v\n data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim.sv\n cam_sim\n cam_sim.v\n cam_sim.sv\n obj_dir/cam_sim\n obj_dir/cam_sim.v\n obj_dir/cam_sim.sv\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:58: Cannot find file containing module: \'cam_sim\'\n cam_sim #(1,row_sz,col_sz) my_cam1(\n ^~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:103: Cannot find file containing module: \'sp_census\'\n sp_census #(row_sz,col_sz) my_census0(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:121: Cannot find file containing module: \'sp_census\'\n sp_census #(row_sz,col_sz) my_census1(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:140: Cannot find file containing module: \'census_window\'\n census_window #(3,row_sz,col_sz) my_wdw0(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:160: Cannot find file containing module: \'census_window\'\n census_window #(3,row_sz,col_sz) my_wdw1(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:180: Cannot find file containing module: \'correlate\'\n correlate #(row_sz, col_sz) my_corr(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:197: Cannot find file containing module: \'vga_buf_sim\'\n vga_buf_sim my_vga(\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,420 | module | module testbench();
reg clk;
reg reset;
reg go;
initial begin
clk = 1'b0;
go = 1'b1;
reset = 1'b0;
#10
reset = 1'b1;
#30
reset = 1'b0;
end
always begin
#10
clk = !clk;
end
localparam row_sz = 450;
localparam col_sz = 375;
wire pclk0;
wire [7:0] cam0_val;
wire [9:0] cam0_x;
wire [9:0] cam0_y;
wire is_cam0_val;
cam_sim #(0,row_sz,col_sz) my_cam0(
.clk(clk),
.reset(reset),
.pclk(pclk0),
.value(cam0_val),
.x(cam0_x),
.y(cam0_y),
.is_val(is_cam0_val)
);
wire pclk1;
wire [7:0] cam1_val;
wire [9:0] cam1_x;
wire [9:0] cam1_y;
wire is_cam1_val;
cam_sim #(1,row_sz,col_sz) my_cam1(
.clk(clk),
.reset(reset),
.pclk(pclk1),
.value(cam1_val),
.x(cam1_x),
.y(cam1_y),
.is_val(is_cam1_val)
);
wire [7:0] cen0_val;
wire [9:0] cen0_x;
wire [9:0] cen0_y;
wire is_cen0_val;
sp_census #(row_sz,col_sz) my_census0(
.clk(pclk0),
.reset(reset),
.in_val(cam0_val),
.in_x(cam0_x),
.in_y(cam0_y),
.is_in_val(is_cam0_val),
.out_val(cen0_val),
.out_x(cen0_x),
.out_y(cen0_y),
.is_out_val(is_cen0_val)
);
wire [7:0] cen1_val;
wire [9:0] cen1_x;
wire [9:0] cen1_y;
wire is_cen1_val;
sp_census #(row_sz,col_sz) my_census1(
.clk(pclk1),
.reset(reset),
.in_val(cam1_val),
.in_x(cam1_x),
.in_y(cam1_y),
.is_in_val(is_cam1_val),
.out_val(cen1_val),
.out_x(cen1_x),
.out_y(cen1_y),
.is_out_val(is_cen1_val)
);
wire [71:0] wdw0_val;
wire [9:0] wdw0_x;
wire [9:0] wdw0_y;
wire is_wdw0_val;
census_window #(3,row_sz,col_sz) my_wdw0(
.clk(pclk0),
.reset(reset),
.in_val(cen0_val),
.in_x(cen0_x),
.in_y(cen0_y),
.is_in_val(is_cen0_val),
.out_val(wdw0_val),
.out_x(wdw0_x),
.out_y(wdw0_y),
.is_out_val(is_wdw0_val)
);
wire [71:0] wdw1_val;
wire [9:0] wdw1_x;
wire [9:0] wdw1_y;
wire is_wdw1_val;
census_window #(3,row_sz,col_sz) my_wdw1(
.clk(pclk1),
.reset(reset),
.in_val(cen1_val),
.in_x(cen1_x),
.in_y(cen1_y),
.is_in_val(is_cen1_val),
.out_val(wdw1_val),
.out_x(wdw1_x),
.out_y(wdw1_y),
.is_out_val(is_wdw1_val)
);
wire [9:0] out_x;
wire [9:0] out_y;
wire [5:0] disp_out_val;
wire is_disp_out_val;
correlate #(row_sz, col_sz) my_corr(
.clk(clk),
.reset(reset),
.left_bitvec(wdw0_val),
.right_bitvec(wdw1_val),
.bitvec_val(is_wdw0_val & is_wdw1_val),
.input_x(wdw0_x),
.input_y(wdw0_y),
.out_x(out_x),
.out_y(out_y),
.disparity_val(is_disp_out_val),
.disparity(disp_out_val)
);
vga_buf_sim my_vga(
.pclk(pclk0),
.reset(reset),
.value({disp_out_val, 2'b00}),
.x(out_x),
.y(out_y),
.is_val(is_disp_out_val)
);
initial begin
#100
$display("Yoooooooooo");
end
endmodule | module testbench(); |
reg clk;
reg reset;
reg go;
initial begin
clk = 1'b0;
go = 1'b1;
reset = 1'b0;
#10
reset = 1'b1;
#30
reset = 1'b0;
end
always begin
#10
clk = !clk;
end
localparam row_sz = 450;
localparam col_sz = 375;
wire pclk0;
wire [7:0] cam0_val;
wire [9:0] cam0_x;
wire [9:0] cam0_y;
wire is_cam0_val;
cam_sim #(0,row_sz,col_sz) my_cam0(
.clk(clk),
.reset(reset),
.pclk(pclk0),
.value(cam0_val),
.x(cam0_x),
.y(cam0_y),
.is_val(is_cam0_val)
);
wire pclk1;
wire [7:0] cam1_val;
wire [9:0] cam1_x;
wire [9:0] cam1_y;
wire is_cam1_val;
cam_sim #(1,row_sz,col_sz) my_cam1(
.clk(clk),
.reset(reset),
.pclk(pclk1),
.value(cam1_val),
.x(cam1_x),
.y(cam1_y),
.is_val(is_cam1_val)
);
wire [7:0] cen0_val;
wire [9:0] cen0_x;
wire [9:0] cen0_y;
wire is_cen0_val;
sp_census #(row_sz,col_sz) my_census0(
.clk(pclk0),
.reset(reset),
.in_val(cam0_val),
.in_x(cam0_x),
.in_y(cam0_y),
.is_in_val(is_cam0_val),
.out_val(cen0_val),
.out_x(cen0_x),
.out_y(cen0_y),
.is_out_val(is_cen0_val)
);
wire [7:0] cen1_val;
wire [9:0] cen1_x;
wire [9:0] cen1_y;
wire is_cen1_val;
sp_census #(row_sz,col_sz) my_census1(
.clk(pclk1),
.reset(reset),
.in_val(cam1_val),
.in_x(cam1_x),
.in_y(cam1_y),
.is_in_val(is_cam1_val),
.out_val(cen1_val),
.out_x(cen1_x),
.out_y(cen1_y),
.is_out_val(is_cen1_val)
);
wire [71:0] wdw0_val;
wire [9:0] wdw0_x;
wire [9:0] wdw0_y;
wire is_wdw0_val;
census_window #(3,row_sz,col_sz) my_wdw0(
.clk(pclk0),
.reset(reset),
.in_val(cen0_val),
.in_x(cen0_x),
.in_y(cen0_y),
.is_in_val(is_cen0_val),
.out_val(wdw0_val),
.out_x(wdw0_x),
.out_y(wdw0_y),
.is_out_val(is_wdw0_val)
);
wire [71:0] wdw1_val;
wire [9:0] wdw1_x;
wire [9:0] wdw1_y;
wire is_wdw1_val;
census_window #(3,row_sz,col_sz) my_wdw1(
.clk(pclk1),
.reset(reset),
.in_val(cen1_val),
.in_x(cen1_x),
.in_y(cen1_y),
.is_in_val(is_cen1_val),
.out_val(wdw1_val),
.out_x(wdw1_x),
.out_y(wdw1_y),
.is_out_val(is_wdw1_val)
);
wire [9:0] out_x;
wire [9:0] out_y;
wire [5:0] disp_out_val;
wire is_disp_out_val;
correlate #(row_sz, col_sz) my_corr(
.clk(clk),
.reset(reset),
.left_bitvec(wdw0_val),
.right_bitvec(wdw1_val),
.bitvec_val(is_wdw0_val & is_wdw1_val),
.input_x(wdw0_x),
.input_y(wdw0_y),
.out_x(out_x),
.out_y(out_y),
.disparity_val(is_disp_out_val),
.disparity(disp_out_val)
);
vga_buf_sim my_vga(
.pclk(pclk0),
.reset(reset),
.value({disp_out_val, 2'b00}),
.x(out_x),
.y(out_y),
.is_val(is_disp_out_val)
);
initial begin
#100
$display("Yoooooooooo");
end
endmodule | 1 |
4,223 | data/full_repos/permissive/109216392/src/cjg_clkgen.v | 109,216,392 | cjg_clkgen.v | v | 47 | 52 | [] | [] | [] | [(1, 46)] | null | null | 1: b"%Error: data/full_repos/permissive/109216392/src/cjg_clkgen.v:25: Cannot find file containing module: 'CLKBUFX4'\nCLKBUFX4 clk_p1_buf (\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4\n data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4.v\n data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4.sv\n CLKBUFX4\n CLKBUFX4.v\n CLKBUFX4.sv\n obj_dir/CLKBUFX4\n obj_dir/CLKBUFX4.v\n obj_dir/CLKBUFX4.sv\n%Error: data/full_repos/permissive/109216392/src/cjg_clkgen.v:31: Cannot find file containing module: 'CLKBUFX4'\nCLKBUFX4 clk_p2_buf (\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,425 | module | module cjg_clkgen (
input reset,
input clk,
output clk_p1,
output clk_p2,
input scan_in0,
input scan_en,
input test_mode,
output scan_out0
);
reg[1:0] clk_cnt;
wire pre_p1 = (~clk_cnt[1] & ~clk_cnt[0]);
wire pre_p2 = (clk_cnt[1] & ~clk_cnt[0]);
CLKBUFX4 clk_p1_buf (
.A(pre_p1),
.Y(clk_p1)
);
CLKBUFX4 clk_p2_buf (
.A(pre_p2),
.Y(clk_p2)
);
always @ (posedge clk, negedge reset) begin
if(~reset) begin
clk_cnt <= 2'h0;
end
else begin
clk_cnt <= clk_cnt + 1'b1;
end
end
endmodule | module cjg_clkgen (
input reset,
input clk,
output clk_p1,
output clk_p2,
input scan_in0,
input scan_en,
input test_mode,
output scan_out0
); |
reg[1:0] clk_cnt;
wire pre_p1 = (~clk_cnt[1] & ~clk_cnt[0]);
wire pre_p2 = (clk_cnt[1] & ~clk_cnt[0]);
CLKBUFX4 clk_p1_buf (
.A(pre_p1),
.Y(clk_p1)
);
CLKBUFX4 clk_p2_buf (
.A(pre_p2),
.Y(clk_p2)
);
always @ (posedge clk, negedge reset) begin
if(~reset) begin
clk_cnt <= 2'h0;
end
else begin
clk_cnt <= clk_cnt + 1'b1;
end
end
endmodule | 4 |
4,224 | data/full_repos/permissive/109216392/src/cjg_mem_stack.v | 109,216,392 | cjg_mem_stack.v | v | 43 | 70 | [] | [] | [] | null | line:44: before: "reg" | data/verilator_xmls/4900579a-f496-485e-b2f8-4193a9610373.xml | null | 2,427 | module | module cjg_mem_stack #(parameter WIDTH = 32, DEPTH = 32, ADDRW = 5) (
input clk,
input reset,
input [WIDTH-1:0] d,
input [ADDRW-1:0] addr,
input push,
input pop,
output reg [WIDTH-1:0] q,
input scan_in0,
input scan_en,
input test_mode,
output scan_out0
);
reg [WIDTH-1:0] stack [DEPTH-1:0];
integer i;
always @(posedge clk or negedge reset) begin
if (~reset) begin
q <= {WIDTH{1'b0}};
for (i=0; i < DEPTH; i=i+1) begin
stack[i] <= {WIDTH{1'b0}};
end
end
else begin
if (push) begin
stack[addr] <= d;
end
else begin
stack[addr] <= stack[addr];
end
q <= stack[addr];
end
end
endmodule | module cjg_mem_stack #(parameter WIDTH = 32, DEPTH = 32, ADDRW = 5) (
input clk,
input reset,
input [WIDTH-1:0] d,
input [ADDRW-1:0] addr,
input push,
input pop,
output reg [WIDTH-1:0] q,
input scan_in0,
input scan_en,
input test_mode,
output scan_out0
); |
reg [WIDTH-1:0] stack [DEPTH-1:0];
integer i;
always @(posedge clk or negedge reset) begin
if (~reset) begin
q <= {WIDTH{1'b0}};
for (i=0; i < DEPTH; i=i+1) begin
stack[i] <= {WIDTH{1'b0}};
end
end
else begin
if (push) begin
stack[addr] <= d;
end
else begin
stack[addr] <= stack[addr];
end
q <= stack[addr];
end
end
endmodule | 4 |
4,229 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module switch_2_2(
inData_0,
inData_1,
outData_0,
outData_1,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input ctrl, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = (!ctrl) ? wireIn[0] : wireIn[1];
assign wireOut[1] = (!ctrl) ? wireIn[1] : wireIn[0];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
endmodule | module switch_2_2(
inData_0,
inData_1,
outData_0,
outData_1,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input ctrl, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = (!ctrl) ? wireIn[0] : wireIn[1];
assign wireOut[1] = (!ctrl) ? wireIn[1] : wireIn[0];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
endmodule | 0 |
4,230 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module counter_8(
in_start,
counter_out,
clk,
rst
);
input in_start, clk, rst;
output [2:0] counter_out;
reg [2:0] counter_r;
reg status_couting;
assign counter_out = counter_r;
always@(posedge clk)
begin
if(rst) begin
counter_r <= 3'b0;
status_couting <= 1'b0;
end
else begin
if (status_couting == 1'b1)
counter_r <= counter_r + 1'b1;
if (counter_r[2:0] == 7) begin
status_couting <= 1'b0;
counter_r <= 3'b0;
end
if (in_start) begin
status_couting <= 1'b1;
counter_r <= 3'b0;
end
end
end
endmodule | module counter_8(
in_start,
counter_out,
clk,
rst
); |
input in_start, clk, rst;
output [2:0] counter_out;
reg [2:0] counter_r;
reg status_couting;
assign counter_out = counter_r;
always@(posedge clk)
begin
if(rst) begin
counter_r <= 3'b0;
status_couting <= 1'b0;
end
else begin
if (status_couting == 1'b1)
counter_r <= counter_r + 1'b1;
if (counter_r[2:0] == 7) begin
status_couting <= 1'b0;
counter_r <= 3'b0;
end
if (in_start) begin
status_couting <= 1'b1;
counter_r <= 3'b0;
end
end
end
endmodule | 0 |
4,231 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module block_ram_sp(
wen,
en,
clk,
addr,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr] <= din ;
dout <= ram[addr];
end
end
endmodule | module block_ram_sp(
wen,
en,
clk,
addr,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr] <= din ;
dout <= ram[addr];
end
end
endmodule | 0 |
4,232 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module dist_ram_sp(
wen,
clk,
addr,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr] <= din ;
end
assign dout = ram[addr];
endmodule | module dist_ram_sp(
wen,
clk,
addr,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr] <= din ;
end
assign dout = ram[addr];
endmodule | 0 |
4,233 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module block_ram_dp(
wen,
en,
clk,
addr_r,
addr_w,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr_w] <= din ;
dout <= ram[addr_r];
end
end
endmodule | module block_ram_dp(
wen,
en,
clk,
addr_r,
addr_w,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr_w] <= din ;
dout <= ram[addr_r];
end
end
endmodule | 0 |
4,234 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module dist_ram_dp(
wen,
clk,
addr_r,
addr_w,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr_w] <= din ;
end
assign dout = ram[addr_r];
endmodule | module dist_ram_dp(
wen,
clk,
addr_r,
addr_w,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 2;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr_w] <= din ;
end
assign dout = ram[addr_r];
endmodule | 0 |
4,235 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module switches_stage_st0_0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module switches_stage_st0_0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,236 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module wireCon_dp4_st0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[2];
assign wireOut[2] = wireIn[1];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module wireCon_dp4_st0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[2];
assign wireOut[2] = wireIn[1];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,237 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module switches_stage_st1_0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module switches_stage_st1_0_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,238 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module wireCon_dp4_st1_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign wireOut[2] = wireIn[2];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module wireCon_dp4_st1_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign wireOut[2] = wireIn[2];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,239 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module ingressStage_p4(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
counter_in,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
input [1:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
wire in_start_stage0;
wire con_in_start_stage0;
wire in_start_stage1;
wire con_in_start_stage1;
wire [DATA_WIDTH-1:0] wire_con_in_stage0[3:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage0[3:0];
wire [1:0] wire_ctrl_stage0;
switches_stage_st0_0_L switch_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]),
.outData_0(wire_con_in_stage0[0]), .outData_1(wire_con_in_stage0[1]), .outData_2(wire_con_in_stage0[2]), .outData_3(wire_con_in_stage0[3]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp4_st0_L wire_stage_0(
.inData_0(wire_con_in_stage0[0]), .inData_1(wire_con_in_stage0[1]), .inData_2(wire_con_in_stage0[2]), .inData_3(wire_con_in_stage0[3]),
.outData_0(wire_con_out_stage0[0]), .outData_1(wire_con_out_stage0[1]), .outData_2(wire_con_out_stage0[2]), .outData_3(wire_con_out_stage0[3]),
.in_start(con_in_start_stage0), .out_start(in_start_stage1), .clk(clk), .rst(rst));
wire [1:0] counter_w;
assign counter_w = counter_in;
assign wire_ctrl_stage0[0] = counter_w[1];
assign wire_ctrl_stage0[1] = counter_w[1];
wire [DATA_WIDTH-1:0] wire_con_in_stage1[3:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage1[3:0];
wire [1:0] wire_ctrl_stage1;
switches_stage_st1_0_L switch_stage_1(
.inData_0(wire_con_out_stage0[0]), .inData_1(wire_con_out_stage0[1]), .inData_2(wire_con_out_stage0[2]), .inData_3(wire_con_out_stage0[3]),
.outData_0(wire_con_in_stage1[0]), .outData_1(wire_con_in_stage1[1]), .outData_2(wire_con_in_stage1[2]), .outData_3(wire_con_in_stage1[3]),
.in_start(in_start_stage1), .out_start(con_in_start_stage1), .ctrl(wire_ctrl_stage1), .clk(clk), .rst(rst));
wireCon_dp4_st1_L wire_stage_1(
.inData_0(wire_con_in_stage1[0]), .inData_1(wire_con_in_stage1[1]), .inData_2(wire_con_in_stage1[2]), .inData_3(wire_con_in_stage1[3]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]),
.in_start(con_in_start_stage1), .out_start(out_start_w), .clk(clk), .rst(rst));
assign wire_ctrl_stage1[0] = counter_w[0];
assign wire_ctrl_stage1[1] = counter_w[0];
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = out_start_w;
endmodule | module ingressStage_p4(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
counter_in,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
input [1:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
wire in_start_stage0;
wire con_in_start_stage0;
wire in_start_stage1;
wire con_in_start_stage1;
wire [DATA_WIDTH-1:0] wire_con_in_stage0[3:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage0[3:0];
wire [1:0] wire_ctrl_stage0;
switches_stage_st0_0_L switch_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]),
.outData_0(wire_con_in_stage0[0]), .outData_1(wire_con_in_stage0[1]), .outData_2(wire_con_in_stage0[2]), .outData_3(wire_con_in_stage0[3]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp4_st0_L wire_stage_0(
.inData_0(wire_con_in_stage0[0]), .inData_1(wire_con_in_stage0[1]), .inData_2(wire_con_in_stage0[2]), .inData_3(wire_con_in_stage0[3]),
.outData_0(wire_con_out_stage0[0]), .outData_1(wire_con_out_stage0[1]), .outData_2(wire_con_out_stage0[2]), .outData_3(wire_con_out_stage0[3]),
.in_start(con_in_start_stage0), .out_start(in_start_stage1), .clk(clk), .rst(rst));
wire [1:0] counter_w;
assign counter_w = counter_in;
assign wire_ctrl_stage0[0] = counter_w[1];
assign wire_ctrl_stage0[1] = counter_w[1];
wire [DATA_WIDTH-1:0] wire_con_in_stage1[3:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage1[3:0];
wire [1:0] wire_ctrl_stage1;
switches_stage_st1_0_L switch_stage_1(
.inData_0(wire_con_out_stage0[0]), .inData_1(wire_con_out_stage0[1]), .inData_2(wire_con_out_stage0[2]), .inData_3(wire_con_out_stage0[3]),
.outData_0(wire_con_in_stage1[0]), .outData_1(wire_con_in_stage1[1]), .outData_2(wire_con_in_stage1[2]), .outData_3(wire_con_in_stage1[3]),
.in_start(in_start_stage1), .out_start(con_in_start_stage1), .ctrl(wire_ctrl_stage1), .clk(clk), .rst(rst));
wireCon_dp4_st1_L wire_stage_1(
.inData_0(wire_con_in_stage1[0]), .inData_1(wire_con_in_stage1[1]), .inData_2(wire_con_in_stage1[2]), .inData_3(wire_con_in_stage1[3]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]),
.in_start(con_in_start_stage1), .out_start(out_start_w), .clk(clk), .rst(rst));
assign wire_ctrl_stage1[0] = counter_w[0];
assign wire_ctrl_stage1[1] = counter_w[0];
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = out_start_w;
endmodule | 0 |
4,240 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module switches_stage_st0_0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module switches_stage_st0_0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,241 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module wireCon_dp4_st0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[2];
assign wireOut[2] = wireIn[1];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module wireCon_dp4_st0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[2];
assign wireOut[2] = wireIn[1];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,242 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module switches_stage_st1_0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module switches_stage_st1_0_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
switch_2_2 switch_inst_1(.inData_0(wireIn[2]), .inData_1(wireIn[3]), .outData_0(wireOut[2]), .outData_1(wireOut[3]), .ctrl(ctrl[1]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,243 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module wireCon_dp4_st1_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign wireOut[2] = wireIn[2];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | module wireCon_dp4_st1_R(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign wireOut[2] = wireIn[2];
assign wireOut[3] = wireIn[3];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = in_start;
endmodule | 0 |
4,244 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module egressStage_p4(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
counter_in,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
input [1:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
wire in_start_stage1;
wire con_in_start_stage1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_switch_in_stage1[3:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage1[3:0];
reg [1:0] wire_ctrl_stage1;
switches_stage_st1_0_R switch_stage_1(
.inData_0(wire_switch_in_stage1[0]), .inData_1(wire_switch_in_stage1[1]), .inData_2(wire_switch_in_stage1[2]), .inData_3(wire_switch_in_stage1[3]),
.outData_0(wire_switch_out_stage1[0]), .outData_1(wire_switch_out_stage1[1]), .outData_2(wire_switch_out_stage1[2]), .outData_3(wire_switch_out_stage1[3]),
.in_start(con_in_start_stage1), .out_start(in_start_stage0), .ctrl(wire_ctrl_stage1), .clk(clk), .rst(rst));
wireCon_dp4_st1_R wire_stage_1(
.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]),
.outData_0(wire_switch_in_stage1[0]), .outData_1(wire_switch_in_stage1[1]), .outData_2(wire_switch_in_stage1[2]), .outData_3(wire_switch_in_stage1[3]),
.in_start(in_start_stage1), .out_start(con_in_start_stage1), .clk(clk), .rst(rst));
wire [1:0] counter_w;
assign counter_w = counter_in;
always@(posedge clk)
begin
wire_ctrl_stage1[0] <= counter_w[0];
end
always@(posedge clk)
begin
wire_ctrl_stage1[1] <= counter_w[0];
end
wire [DATA_WIDTH-1:0] wire_switch_in_stage0[3:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage0[3:0];
reg [1:0] wire_ctrl_stage0;
switches_stage_st0_0_R switch_stage_0(
.inData_0(wire_switch_in_stage0[0]), .inData_1(wire_switch_in_stage0[1]), .inData_2(wire_switch_in_stage0[2]), .inData_3(wire_switch_in_stage0[3]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp4_st0_R wire_stage_0(
.inData_0(wire_switch_out_stage1[0]), .inData_1(wire_switch_out_stage1[1]), .inData_2(wire_switch_out_stage1[2]), .inData_3(wire_switch_out_stage1[3]),
.outData_0(wire_switch_in_stage0[0]), .outData_1(wire_switch_in_stage0[1]), .outData_2(wire_switch_in_stage0[2]), .outData_3(wire_switch_in_stage0[3]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .clk(clk), .rst(rst));
always@(posedge clk)
begin
wire_ctrl_stage0[0] <= counter_w[1];
end
always@(posedge clk)
begin
wire_ctrl_stage0[1] <= counter_w[1];
end
assign in_start_stage1 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = out_start_w;
endmodule | module egressStage_p4(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
counter_in,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
input [1:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
wire in_start_stage1;
wire con_in_start_stage1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_switch_in_stage1[3:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage1[3:0];
reg [1:0] wire_ctrl_stage1;
switches_stage_st1_0_R switch_stage_1(
.inData_0(wire_switch_in_stage1[0]), .inData_1(wire_switch_in_stage1[1]), .inData_2(wire_switch_in_stage1[2]), .inData_3(wire_switch_in_stage1[3]),
.outData_0(wire_switch_out_stage1[0]), .outData_1(wire_switch_out_stage1[1]), .outData_2(wire_switch_out_stage1[2]), .outData_3(wire_switch_out_stage1[3]),
.in_start(con_in_start_stage1), .out_start(in_start_stage0), .ctrl(wire_ctrl_stage1), .clk(clk), .rst(rst));
wireCon_dp4_st1_R wire_stage_1(
.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]),
.outData_0(wire_switch_in_stage1[0]), .outData_1(wire_switch_in_stage1[1]), .outData_2(wire_switch_in_stage1[2]), .outData_3(wire_switch_in_stage1[3]),
.in_start(in_start_stage1), .out_start(con_in_start_stage1), .clk(clk), .rst(rst));
wire [1:0] counter_w;
assign counter_w = counter_in;
always@(posedge clk)
begin
wire_ctrl_stage1[0] <= counter_w[0];
end
always@(posedge clk)
begin
wire_ctrl_stage1[1] <= counter_w[0];
end
wire [DATA_WIDTH-1:0] wire_switch_in_stage0[3:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage0[3:0];
reg [1:0] wire_ctrl_stage0;
switches_stage_st0_0_R switch_stage_0(
.inData_0(wire_switch_in_stage0[0]), .inData_1(wire_switch_in_stage0[1]), .inData_2(wire_switch_in_stage0[2]), .inData_3(wire_switch_in_stage0[3]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp4_st0_R wire_stage_0(
.inData_0(wire_switch_out_stage1[0]), .inData_1(wire_switch_out_stage1[1]), .inData_2(wire_switch_out_stage1[2]), .inData_3(wire_switch_out_stage1[3]),
.outData_0(wire_switch_in_stage0[0]), .outData_1(wire_switch_in_stage0[1]), .outData_2(wire_switch_in_stage0[2]), .outData_3(wire_switch_in_stage0[3]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .clk(clk), .rst(rst));
always@(posedge clk)
begin
wire_ctrl_stage0[0] <= counter_w[1];
end
always@(posedge clk)
begin
wire_ctrl_stage0[1] <= counter_w[1];
end
assign in_start_stage1 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign outData_2 = wireOut[2];
assign outData_3 = wireOut[3];
assign out_start = out_start_w;
endmodule | 0 |
4,245 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module mem_addr_gen_dp4_mem0_per0(
counter_in,
clk,
rst,
addr_out
);
input clk, rst;
input [1:0] counter_in;
output [1:0] addr_out;
wire [1:0] addr_a0;
assign addr_out[1:0] = addr_a0[1:0];
assign addr_a0 = counter_in[1:0];
endmodule | module mem_addr_gen_dp4_mem0_per0(
counter_in,
clk,
rst,
addr_out
); |
input clk, rst;
input [1:0] counter_in;
output [1:0] addr_out;
wire [1:0] addr_a0;
assign addr_out[1:0] = addr_a0[1:0];
assign addr_a0 = counter_in[1:0];
endmodule | 0 |
4,246 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module mem_addr_ctrl_dp4_per0(
in_start,
counter_in,
wen_out,
out_start,
mem_addr_out_0,
mem_addr_out_1,
mem_addr_out_2,
mem_addr_out_3,
clk,
rst
);
input in_start, clk, rst;
input [1:0] counter_in;
output [1:0] mem_addr_out_0;
output [1:0] mem_addr_out_1;
output [1:0] mem_addr_out_2;
output [1:0] mem_addr_out_3;
output wen_out;
output reg out_start;
reg [1:0] state;
reg flag;
wire [1:0] mem_addr_out_tmp_0;
wire [1:0] mem_addr_out_tmp_1;
wire [1:0] mem_addr_out_tmp_2;
wire [1:0] mem_addr_out_tmp_3;
wire [1:0] mem_addr_out_w;
wire [1:0] mem_addr_out_w_h;
mem_addr_gen_dp4_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in));
assign mem_addr_out_w_h = mem_addr_out_w[1:0];
assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[1],mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_1 = {mem_addr_out_w_h[1],~mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_2 = {~mem_addr_out_w_h[1],mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_3 = {~mem_addr_out_w_h[1],~mem_addr_out_w_h[0]};
assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in);
assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in);
assign mem_addr_out_2 = ((flag == 1'b0) ? mem_addr_out_tmp_2 : counter_in);
assign mem_addr_out_3 = ((flag == 1'b0) ? mem_addr_out_tmp_3 : counter_in);
assign wen_out = state[0];
always@(posedge clk)
begin
if(rst) begin
out_start <= 1'b0;
end
else begin
out_start <= (state == 2'b01) && (counter_in[1:0] == {2{1'b1}});
end
end
always@(posedge clk)
begin
if(rst) begin
state <= 2'b0;
flag <= 1'b0;
end
else begin
case (state)
2'b00: begin
if (in_start) begin
state <= 2'b01;
end
end
2'b01: begin
if (!in_start && counter_in == {2{1'b1}}) begin
state <= 2'b11;
end
if (counter_in == {2{1'b1}}) begin
flag <= !flag;
end
end
2'b11: begin
if (counter_in == {2{1'b1}}) begin
state <= 2'b00;
end
end
default: state <= 2'b00;
endcase
end
end
endmodule | module mem_addr_ctrl_dp4_per0(
in_start,
counter_in,
wen_out,
out_start,
mem_addr_out_0,
mem_addr_out_1,
mem_addr_out_2,
mem_addr_out_3,
clk,
rst
); |
input in_start, clk, rst;
input [1:0] counter_in;
output [1:0] mem_addr_out_0;
output [1:0] mem_addr_out_1;
output [1:0] mem_addr_out_2;
output [1:0] mem_addr_out_3;
output wen_out;
output reg out_start;
reg [1:0] state;
reg flag;
wire [1:0] mem_addr_out_tmp_0;
wire [1:0] mem_addr_out_tmp_1;
wire [1:0] mem_addr_out_tmp_2;
wire [1:0] mem_addr_out_tmp_3;
wire [1:0] mem_addr_out_w;
wire [1:0] mem_addr_out_w_h;
mem_addr_gen_dp4_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in));
assign mem_addr_out_w_h = mem_addr_out_w[1:0];
assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[1],mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_1 = {mem_addr_out_w_h[1],~mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_2 = {~mem_addr_out_w_h[1],mem_addr_out_w_h[0]};
assign mem_addr_out_tmp_3 = {~mem_addr_out_w_h[1],~mem_addr_out_w_h[0]};
assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in);
assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in);
assign mem_addr_out_2 = ((flag == 1'b0) ? mem_addr_out_tmp_2 : counter_in);
assign mem_addr_out_3 = ((flag == 1'b0) ? mem_addr_out_tmp_3 : counter_in);
assign wen_out = state[0];
always@(posedge clk)
begin
if(rst) begin
out_start <= 1'b0;
end
else begin
out_start <= (state == 2'b01) && (counter_in[1:0] == {2{1'b1}});
end
end
always@(posedge clk)
begin
if(rst) begin
state <= 2'b0;
flag <= 1'b0;
end
else begin
case (state)
2'b00: begin
if (in_start) begin
state <= 2'b01;
end
end
2'b01: begin
if (!in_start && counter_in == {2{1'b1}}) begin
state <= 2'b11;
end
if (counter_in == {2{1'b1}}) begin
flag <= !flag;
end
end
2'b11: begin
if (counter_in == {2{1'b1}}) begin
state <= 2'b00;
end
end
default: state <= 2'b00;
endcase
end
end
endmodule | 0 |
4,247 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module mem_stage_dp4_r(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
counter_in,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] counter_in;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output reg out_start;
wire [DATA_WIDTH-1:0] wire_in [3:0];
wire [DATA_WIDTH-1:0] wire_out [3:0];
wire wen_wire;
wire out_start_wire;
assign wire_in[0] = inData_0;
assign wire_in[1] = inData_1;
assign wire_in[2] = inData_2;
assign wire_in[3] = inData_3;
wire [1:0] addr_wire_0;
wire [1:0] addr_wire_1;
wire [1:0] addr_wire_2;
wire [1:0] addr_wire_3;
mem_addr_ctrl_dp4_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .mem_addr_out_2(addr_wire_2), .mem_addr_out_3(addr_wire_3), .clk(clk), .rst(rst));
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_2(.wen(wen_wire), .addr(addr_wire_2), .din(wire_in[2]), .dout(wire_out[2]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_3(.wen(wen_wire), .addr(addr_wire_3), .din(wire_in[3]), .dout(wire_out[3]), .clk(clk) );
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
outData_2 <= 0;
outData_3 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wire_out[0];
outData_1 <= wire_out[1];
outData_2 <= wire_out[2];
outData_3 <= wire_out[3];
out_start <= out_start_wire;
end
end
endmodule | module mem_stage_dp4_r(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
counter_in,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [2-1:0] counter_in;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output reg out_start;
wire [DATA_WIDTH-1:0] wire_in [3:0];
wire [DATA_WIDTH-1:0] wire_out [3:0];
wire wen_wire;
wire out_start_wire;
assign wire_in[0] = inData_0;
assign wire_in[1] = inData_1;
assign wire_in[2] = inData_2;
assign wire_in[3] = inData_3;
wire [1:0] addr_wire_0;
wire [1:0] addr_wire_1;
wire [1:0] addr_wire_2;
wire [1:0] addr_wire_3;
mem_addr_ctrl_dp4_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .mem_addr_out_2(addr_wire_2), .mem_addr_out_3(addr_wire_3), .clk(clk), .rst(rst));
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_2(.wen(wen_wire), .addr(addr_wire_2), .din(wire_in[2]), .dout(wire_out[2]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(2))
ram_inst_3(.wen(wen_wire), .addr(addr_wire_3), .din(wire_in[3]), .dout(wire_out[3]), .clk(clk) );
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
outData_2 <= 0;
outData_3 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wire_out[0];
outData_1 <= wire_out[1];
outData_2 <= wire_out[2];
outData_3 <= wire_out[3];
out_start <= out_start_wire;
end
end
endmodule | 0 |
4,248 | data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v | 109,231,608 | per_n16_p4_w8_idx0.v | v | 1,063 | 341 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 268), (271, 316), (319, 364), (367, 412), (415, 503), (506, 551), (554, 599), (602, 647), (650, 695), (698, 802), (805, 820), (823, 908), (911, 990), (993, 1061)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n : ... In instance per_dp4_0_r\n counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,448 | module | module per_dp4_0_r(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output reg out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
wire [DATA_WIDTH-1:0] wireOut_LB [3:0];
wire [DATA_WIDTH-1:0] wireIn_RB [3:0];
wire out_start_LB;
wire out_start_MemStage;
wire out_start_RB;
wire [1:0] counter_out_w;
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));
ingressStage_p4 ingressStage_p4_inst(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]), .outData_0(wireOut_LB[0]), .outData_1(wireOut_LB[1]), .outData_2(wireOut_LB[2]), .outData_3(wireOut_LB[3]), .in_start(in_start), .out_start(out_start_LB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
mem_stage_dp4_r mem_stage_dp4_r_inst(.inData_0(wireOut_LB[0]), .inData_1(wireOut_LB[1]), .inData_2(wireOut_LB[2]), .inData_3(wireOut_LB[3]), .outData_0(wireIn_RB[0]), .outData_1(wireIn_RB[1]), .outData_2(wireIn_RB[2]), .outData_3(wireIn_RB[3]), .in_start(out_start_LB), .out_start(out_start_MemStage), .clk(clk),
.counter_in(counter_out_w), .rst(rst));
egressStage_p4 egressStage_p4_inst(.inData_0(wireIn_RB[0]), .inData_1(wireIn_RB[1]), .inData_2(wireIn_RB[2]), .inData_3(wireIn_RB[3]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]), .in_start(out_start_MemStage), .out_start(out_start_RB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
outData_2 <= 0;
outData_3 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wireOut[0];
outData_1 <= wireOut[1];
outData_2 <= wireOut[2];
outData_3 <= wireOut[3];
out_start <= out_start_RB;
end
end
endmodule | module per_dp4_0_r(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1,
inData_2,
inData_3;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1,
outData_2,
outData_3;
output reg out_start;
wire [DATA_WIDTH-1:0] wireIn [3:0];
wire [DATA_WIDTH-1:0] wireOut [3:0];
wire [DATA_WIDTH-1:0] wireOut_LB [3:0];
wire [DATA_WIDTH-1:0] wireIn_RB [3:0];
wire out_start_LB;
wire out_start_MemStage;
wire out_start_RB;
wire [1:0] counter_out_w;
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireIn[2] = inData_2;
assign wireIn[3] = inData_3;
counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));
ingressStage_p4 ingressStage_p4_inst(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .inData_2(wireIn[2]), .inData_3(wireIn[3]), .outData_0(wireOut_LB[0]), .outData_1(wireOut_LB[1]), .outData_2(wireOut_LB[2]), .outData_3(wireOut_LB[3]), .in_start(in_start), .out_start(out_start_LB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
mem_stage_dp4_r mem_stage_dp4_r_inst(.inData_0(wireOut_LB[0]), .inData_1(wireOut_LB[1]), .inData_2(wireOut_LB[2]), .inData_3(wireOut_LB[3]), .outData_0(wireIn_RB[0]), .outData_1(wireIn_RB[1]), .outData_2(wireIn_RB[2]), .outData_3(wireIn_RB[3]), .in_start(out_start_LB), .out_start(out_start_MemStage), .clk(clk),
.counter_in(counter_out_w), .rst(rst));
egressStage_p4 egressStage_p4_inst(.inData_0(wireIn_RB[0]), .inData_1(wireIn_RB[1]), .inData_2(wireIn_RB[2]), .inData_3(wireIn_RB[3]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .outData_2(wireOut[2]), .outData_3(wireOut[3]), .in_start(out_start_MemStage), .out_start(out_start_RB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
outData_2 <= 0;
outData_3 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wireOut[0];
outData_1 <= wireOut[1];
outData_2 <= wireOut[2];
outData_3 <= wireOut[3];
out_start <= out_start_RB;
end
end
endmodule | 0 |
4,249 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module switch_2_2(
inData_0,
inData_1,
outData_0,
outData_1,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input ctrl, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = (!ctrl) ? wireIn[0] : wireIn[1];
assign wireOut[1] = (!ctrl) ? wireIn[1] : wireIn[0];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
endmodule | module switch_2_2(
inData_0,
inData_1,
outData_0,
outData_1,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input ctrl, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = (!ctrl) ? wireIn[0] : wireIn[1];
assign wireOut[1] = (!ctrl) ? wireIn[1] : wireIn[0];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
endmodule | 0 |
4,250 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module counter_64(
in_start,
counter_out,
clk,
rst
);
input in_start, clk, rst;
output [5:0] counter_out;
reg [5:0] counter_r;
reg status_couting;
assign counter_out = counter_r;
always@(posedge clk)
begin
if(rst) begin
counter_r <= 6'b0;
status_couting <= 1'b0;
end
else begin
if (status_couting == 1'b1)
counter_r <= counter_r + 1'b1;
if (counter_r[5:0] == 63) begin
status_couting <= 1'b0;
counter_r <= 6'b0;
end
if (in_start) begin
status_couting <= 1'b1;
counter_r <= 6'b0;
end
end
end
endmodule | module counter_64(
in_start,
counter_out,
clk,
rst
); |
input in_start, clk, rst;
output [5:0] counter_out;
reg [5:0] counter_r;
reg status_couting;
assign counter_out = counter_r;
always@(posedge clk)
begin
if(rst) begin
counter_r <= 6'b0;
status_couting <= 1'b0;
end
else begin
if (status_couting == 1'b1)
counter_r <= counter_r + 1'b1;
if (counter_r[5:0] == 63) begin
status_couting <= 1'b0;
counter_r <= 6'b0;
end
if (in_start) begin
status_couting <= 1'b1;
counter_r <= 6'b0;
end
end
end
endmodule | 0 |
4,251 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module block_ram_sp(
wen,
en,
clk,
addr,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr] <= din ;
dout <= ram[addr];
end
end
endmodule | module block_ram_sp(
wen,
en,
clk,
addr,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr] <= din ;
dout <= ram[addr];
end
end
endmodule | 0 |
4,252 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module dist_ram_sp(
wen,
clk,
addr,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr] <= din ;
end
assign dout = ram[addr];
endmodule | module dist_ram_sp(
wen,
clk,
addr,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr] <= din ;
end
assign dout = ram[addr];
endmodule | 0 |
4,253 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module block_ram_dp(
wen,
en,
clk,
addr_r,
addr_w,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr_w] <= din ;
dout <= ram[addr_r];
end
end
endmodule | module block_ram_dp(
wen,
en,
clk,
addr_r,
addr_w,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input en;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output reg [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(en) begin
if(wen)
ram[addr_w] <= din ;
dout <= ram[addr_r];
end
end
endmodule | 0 |
4,254 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module dist_ram_dp(
wen,
clk,
addr_r,
addr_w,
din,
dout
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr_w] <= din ;
end
assign dout = ram[addr_r];
endmodule | module dist_ram_dp(
wen,
clk,
addr_r,
addr_w,
din,
dout
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter RAM_SIZE = 1 << ADDR_WIDTH;
input wen, clk;
input [ADDR_WIDTH-1:0] addr_r;
input [ADDR_WIDTH-1:0] addr_w;
input [DATA_WIDTH-1:0] din;
output [DATA_WIDTH-1:0] dout;
reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];
always@(posedge clk)
begin
if(wen)
ram[addr_w] <= din ;
end
assign dout = ram[addr_r];
endmodule | 0 |
4,255 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module switches_stage_st0_0_L(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [1-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | module switches_stage_st0_0_L(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [1-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | 0 |
4,256 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module wireCon_dp2_st0_L(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | module wireCon_dp2_st0_L(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | 0 |
4,257 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module ingressStage_p2(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
counter_in,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
input [4:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_con_in_stage0[1:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage0[1:0];
wire [0:0] wire_ctrl_stage0;
switches_stage_st0_0_L switch_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]),
.outData_0(wire_con_in_stage0[0]), .outData_1(wire_con_in_stage0[1]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp2_st0_L wire_stage_0(
.inData_0(wire_con_in_stage0[0]), .inData_1(wire_con_in_stage0[1]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .clk(clk), .rst(rst));
wire [4:0] counter_w;
assign counter_w = counter_in;
assign wire_ctrl_stage0[0] = counter_w[4];
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = out_start_w;
endmodule | module ingressStage_p2(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
counter_in,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
input [4:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_con_in_stage0[1:0];
wire [DATA_WIDTH-1:0] wire_con_out_stage0[1:0];
wire [0:0] wire_ctrl_stage0;
switches_stage_st0_0_L switch_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]),
.outData_0(wire_con_in_stage0[0]), .outData_1(wire_con_in_stage0[1]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp2_st0_L wire_stage_0(
.inData_0(wire_con_in_stage0[0]), .inData_1(wire_con_in_stage0[1]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .clk(clk), .rst(rst));
wire [4:0] counter_w;
assign counter_w = counter_in;
assign wire_ctrl_stage0[0] = counter_w[4];
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = out_start_w;
endmodule | 0 |
4,258 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module switches_stage_st0_0_R(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
ctrl,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [1-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | module switches_stage_st0_0_R(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
ctrl,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [1-1:0] ctrl;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
switch_2_2 switch_inst_0(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .ctrl(ctrl[0]), .clk(clk), .rst(rst));
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | 0 |
4,259 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module wireCon_dp2_st0_R(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | module wireCon_dp2_st0_R(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
assign wireOut[0] = wireIn[0];
assign wireOut[1] = wireIn[1];
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = in_start;
endmodule | 0 |
4,260 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module egressStage_p2(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
counter_in,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
input [4:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_switch_in_stage0[1:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage0[1:0];
reg [0:0] wire_ctrl_stage0;
switches_stage_st0_0_R switch_stage_0(
.inData_0(wire_switch_in_stage0[0]), .inData_1(wire_switch_in_stage0[1]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp2_st0_R wire_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]),
.outData_0(wire_switch_in_stage0[0]), .outData_1(wire_switch_in_stage0[1]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .clk(clk), .rst(rst));
wire [4:0] counter_w;
assign counter_w = counter_in;
always@(posedge clk)
begin
wire_ctrl_stage0[0] <= counter_w[4];
end
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = out_start_w;
endmodule | module egressStage_p2(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
counter_in,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
input [4:0] counter_in;
output [DATA_WIDTH-1:0] outData_0,
outData_1;
output out_start;
wire out_start_w;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
wire in_start_stage0;
wire con_in_start_stage0;
wire [DATA_WIDTH-1:0] wire_switch_in_stage0[1:0];
wire [DATA_WIDTH-1:0] wire_switch_out_stage0[1:0];
reg [0:0] wire_ctrl_stage0;
switches_stage_st0_0_R switch_stage_0(
.inData_0(wire_switch_in_stage0[0]), .inData_1(wire_switch_in_stage0[1]),
.outData_0(wireOut[0]), .outData_1(wireOut[1]),
.in_start(con_in_start_stage0), .out_start(out_start_w), .ctrl(wire_ctrl_stage0), .clk(clk), .rst(rst));
wireCon_dp2_st0_R wire_stage_0(
.inData_0(wireIn[0]), .inData_1(wireIn[1]),
.outData_0(wire_switch_in_stage0[0]), .outData_1(wire_switch_in_stage0[1]),
.in_start(in_start_stage0), .out_start(con_in_start_stage0), .clk(clk), .rst(rst));
wire [4:0] counter_w;
assign counter_w = counter_in;
always@(posedge clk)
begin
wire_ctrl_stage0[0] <= counter_w[4];
end
assign in_start_stage0 = in_start;
assign outData_0 = wireOut[0];
assign outData_1 = wireOut[1];
assign out_start = out_start_w;
endmodule | 0 |
4,261 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module mem_addr_gen_dp2_mem0_per0(
counter_in,
clk,
rst,
addr_out
);
input clk, rst;
input [4:0] counter_in;
output [4:0] addr_out;
wire [3:0] word_counter_w [0:0];
wire [0:0] addr_a0;
assign addr_out[3:0] = {word_counter_w[0][0],word_counter_w[0][1],word_counter_w[0][2],word_counter_w[0][3]};
assign addr_out[4:4] = addr_a0[0:0];
assign word_counter_w[0] = counter_in[3:0];
assign addr_a0 = counter_in[4:4];
endmodule | module mem_addr_gen_dp2_mem0_per0(
counter_in,
clk,
rst,
addr_out
); |
input clk, rst;
input [4:0] counter_in;
output [4:0] addr_out;
wire [3:0] word_counter_w [0:0];
wire [0:0] addr_a0;
assign addr_out[3:0] = {word_counter_w[0][0],word_counter_w[0][1],word_counter_w[0][2],word_counter_w[0][3]};
assign addr_out[4:4] = addr_a0[0:0];
assign word_counter_w[0] = counter_in[3:0];
assign addr_a0 = counter_in[4:4];
endmodule | 0 |
4,262 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module mem_addr_ctrl_dp2_per0(
in_start,
counter_in,
wen_out,
out_start,
mem_addr_out_0,
mem_addr_out_1,
clk,
rst
);
input in_start, clk, rst;
input [4:0] counter_in;
output [4:0] mem_addr_out_0;
output [4:0] mem_addr_out_1;
output wen_out;
output reg out_start;
reg [1:0] state;
reg flag;
wire [4:0] mem_addr_out_tmp_0;
wire [4:0] mem_addr_out_tmp_1;
wire [4:0] mem_addr_out_w;
wire [0:0] mem_addr_out_w_h;
wire [3:0] mem_addr_out_w_l;
mem_addr_gen_dp2_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in));
assign mem_addr_out_w_h = mem_addr_out_w[4:4];
assign mem_addr_out_w_l = mem_addr_out_w[3:0];
assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[0],mem_addr_out_w_l};
assign mem_addr_out_tmp_1 = {~mem_addr_out_w_h[0],mem_addr_out_w_l};
assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in);
assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in);
assign wen_out = state[0];
always@(posedge clk)
begin
if(rst) begin
out_start <= 1'b0;
end
else begin
out_start <= (state == 2'b01) && (counter_in[4:0] == {5{1'b1}});
end
end
always@(posedge clk)
begin
if(rst) begin
state <= 2'b0;
flag <= 1'b0;
end
else begin
case (state)
2'b00: begin
if (in_start) begin
state <= 2'b01;
end
end
2'b01: begin
if (!in_start && counter_in == {5{1'b1}}) begin
state <= 2'b11;
end
if (counter_in == {5{1'b1}}) begin
flag <= !flag;
end
end
2'b11: begin
if (counter_in == {5{1'b1}}) begin
state <= 2'b00;
end
end
default: state <= 2'b00;
endcase
end
end
endmodule | module mem_addr_ctrl_dp2_per0(
in_start,
counter_in,
wen_out,
out_start,
mem_addr_out_0,
mem_addr_out_1,
clk,
rst
); |
input in_start, clk, rst;
input [4:0] counter_in;
output [4:0] mem_addr_out_0;
output [4:0] mem_addr_out_1;
output wen_out;
output reg out_start;
reg [1:0] state;
reg flag;
wire [4:0] mem_addr_out_tmp_0;
wire [4:0] mem_addr_out_tmp_1;
wire [4:0] mem_addr_out_w;
wire [0:0] mem_addr_out_w_h;
wire [3:0] mem_addr_out_w_l;
mem_addr_gen_dp2_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in));
assign mem_addr_out_w_h = mem_addr_out_w[4:4];
assign mem_addr_out_w_l = mem_addr_out_w[3:0];
assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[0],mem_addr_out_w_l};
assign mem_addr_out_tmp_1 = {~mem_addr_out_w_h[0],mem_addr_out_w_l};
assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in);
assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in);
assign wen_out = state[0];
always@(posedge clk)
begin
if(rst) begin
out_start <= 1'b0;
end
else begin
out_start <= (state == 2'b01) && (counter_in[4:0] == {5{1'b1}});
end
end
always@(posedge clk)
begin
if(rst) begin
state <= 2'b0;
flag <= 1'b0;
end
else begin
case (state)
2'b00: begin
if (in_start) begin
state <= 2'b01;
end
end
2'b01: begin
if (!in_start && counter_in == {5{1'b1}}) begin
state <= 2'b11;
end
if (counter_in == {5{1'b1}}) begin
flag <= !flag;
end
end
2'b11: begin
if (counter_in == {5{1'b1}}) begin
state <= 2'b00;
end
end
default: state <= 2'b00;
endcase
end
end
endmodule | 0 |
4,263 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module mem_stage_dp2_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
counter_in,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [5-1:0] counter_in;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1;
output reg out_start;
wire [DATA_WIDTH-1:0] wire_in [1:0];
wire [DATA_WIDTH-1:0] wire_out [1:0];
wire wen_wire;
wire out_start_wire;
assign wire_in[0] = inData_0;
assign wire_in[1] = inData_1;
wire [4:0] addr_wire_0;
wire [4:0] addr_wire_1;
mem_addr_ctrl_dp2_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .clk(clk), .rst(rst));
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5))
ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5))
ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wire_out[0];
outData_1 <= wire_out[1];
out_start <= out_start_wire;
end
end
endmodule | module mem_stage_dp2_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
counter_in,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [5-1:0] counter_in;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1;
output reg out_start;
wire [DATA_WIDTH-1:0] wire_in [1:0];
wire [DATA_WIDTH-1:0] wire_out [1:0];
wire wen_wire;
wire out_start_wire;
assign wire_in[0] = inData_0;
assign wire_in[1] = inData_1;
wire [4:0] addr_wire_0;
wire [4:0] addr_wire_1;
mem_addr_ctrl_dp2_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .clk(clk), .rst(rst));
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5))
ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );
dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5))
ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wire_out[0];
outData_1 <= wire_out[1];
out_start <= out_start_wire;
end
end
endmodule | 0 |
4,264 | data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v | 109,231,608 | per_n64_p2_w8_idx0.v | v | 696 | 243 | [] | [] | [] | [(29, 57), (60, 94), (97, 126), (129, 155), (158, 189), (192, 220), (223, 255), (258, 289), (292, 347), (350, 382), (385, 416), (419, 478), (481, 499), (502, 579), (582, 637), (640, 694)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'block_ram_sp\'\nmodule block_ram_sp(\n ^~~~~~~~~~~~\n : ... Top module \'block_ram_dp\'\nmodule block_ram_dp(\n ^~~~~~~~~~~~\n : ... Top module \'dist_ram_dp\'\nmodule dist_ram_dp(\n ^~~~~~~~~~~\n : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n : ... In instance per_dp2_0_r\n counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n' | 2,463 | module | module per_dp2_0_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
);
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1;
output reg out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
wire [DATA_WIDTH-1:0] wireOut_LB [1:0];
wire [DATA_WIDTH-1:0] wireIn_RB [1:0];
wire out_start_LB;
wire out_start_MemStage;
wire out_start_RB;
wire [4:0] counter_out_w;
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));
ingressStage_p2 ingressStage_p2_inst(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut_LB[0]), .outData_1(wireOut_LB[1]), .in_start(in_start), .out_start(out_start_LB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
mem_stage_dp2_r mem_stage_dp2_r_inst(.inData_0(wireOut_LB[0]), .inData_1(wireOut_LB[1]), .outData_0(wireIn_RB[0]), .outData_1(wireIn_RB[1]), .in_start(out_start_LB), .out_start(out_start_MemStage), .clk(clk),
.counter_in(counter_out_w), .rst(rst));
egressStage_p2 egressStage_p2_inst(.inData_0(wireIn_RB[0]), .inData_1(wireIn_RB[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .in_start(out_start_MemStage), .out_start(out_start_RB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wireOut[0];
outData_1 <= wireOut[1];
out_start <= out_start_RB;
end
end
endmodule | module per_dp2_0_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,
out_start,
clk,
rst
); |
parameter DATA_WIDTH = 8;
input in_start, clk, rst;
input [DATA_WIDTH-1:0] inData_0,
inData_1;
output reg [DATA_WIDTH-1:0] outData_0,
outData_1;
output reg out_start;
wire [DATA_WIDTH-1:0] wireIn [1:0];
wire [DATA_WIDTH-1:0] wireOut [1:0];
wire [DATA_WIDTH-1:0] wireOut_LB [1:0];
wire [DATA_WIDTH-1:0] wireIn_RB [1:0];
wire out_start_LB;
wire out_start_MemStage;
wire out_start_RB;
wire [4:0] counter_out_w;
assign wireIn[0] = inData_0;
assign wireIn[1] = inData_1;
counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));
ingressStage_p2 ingressStage_p2_inst(.inData_0(wireIn[0]), .inData_1(wireIn[1]), .outData_0(wireOut_LB[0]), .outData_1(wireOut_LB[1]), .in_start(in_start), .out_start(out_start_LB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
mem_stage_dp2_r mem_stage_dp2_r_inst(.inData_0(wireOut_LB[0]), .inData_1(wireOut_LB[1]), .outData_0(wireIn_RB[0]), .outData_1(wireIn_RB[1]), .in_start(out_start_LB), .out_start(out_start_MemStage), .clk(clk),
.counter_in(counter_out_w), .rst(rst));
egressStage_p2 egressStage_p2_inst(.inData_0(wireIn_RB[0]), .inData_1(wireIn_RB[1]), .outData_0(wireOut[0]), .outData_1(wireOut[1]), .in_start(out_start_MemStage), .out_start(out_start_RB), .counter_in(counter_out_w), .clk(clk), .rst(rst));
always@(posedge clk)
begin
if(rst) begin
outData_0 <= 0;
outData_1 <= 0;
out_start <= 1'b0;
end
else begin
outData_0 <= wireOut[0];
outData_1 <= wireOut[1];
out_start <= out_start_RB;
end
end
endmodule | 0 |
4,265 | data/full_repos/permissive/109231608/bitrev_files/per_testbench.v | 109,231,608 | per_testbench.v | v | 265 | 49 | [] | [] | [] | [(2, 72), (75, 156), (160, 265)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:111: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:124: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:125: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:134: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:204: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:221: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:222: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:235: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:250: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:75: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'per_p2_test\'\nmodule per_p2_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p4_test\'\nmodule per_p4_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p8_test\'\nmodule per_p8_test;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:176: Cannot find file containing module: \'per_dp8_888_r\'\n per_dp8_888_r per_instance(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.v\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.sv\n per_dp8_888_r\n per_dp8_888_r.v\n per_dp8_888_r.sv\n obj_dir/per_dp8_888_r\n obj_dir/per_dp8_888_r.v\n obj_dir/per_dp8_888_r.sv\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:236: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:237: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:239: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:240: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:241: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:242: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:243: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:252: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:253: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:254: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:255: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:256: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:257: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:258: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:91: Cannot find file containing module: \'per_dp4_0_r\'\n per_dp4_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:135: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:136: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:137: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:138: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:146: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:147: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:148: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:149: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:19: Cannot find file containing module: \'per_dp2_0_r\'\n per_dp2_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:54: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:55: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:64: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i+0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Error: Exiting due to 3 error(s), 44 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,470 | module | module per_p2_test;
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter N = 256;
parameter DP = 2;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp2_0_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = 0;
data_in[1] = 0;
ctrl_in = 1;
for(i=0; i<N/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 2*i;
data_in[1] = 2*i+1;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<N/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 2*i+0;
data_in[1] = 2*i+1;
ctrl_in = 0;
end
end
endmodule | module per_p2_test; |
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter N = 256;
parameter DP = 2;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp2_0_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = 0;
data_in[1] = 0;
ctrl_in = 1;
for(i=0; i<N/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 2*i;
data_in[1] = 2*i+1;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<N/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 2*i+0;
data_in[1] = 2*i+1;
ctrl_in = 0;
end
end
endmodule | 0 |
4,266 | data/full_repos/permissive/109231608/bitrev_files/per_testbench.v | 109,231,608 | per_testbench.v | v | 265 | 49 | [] | [] | [] | [(2, 72), (75, 156), (160, 265)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:111: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:124: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:125: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:134: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:204: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:221: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:222: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:235: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:250: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:75: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'per_p2_test\'\nmodule per_p2_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p4_test\'\nmodule per_p4_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p8_test\'\nmodule per_p8_test;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:176: Cannot find file containing module: \'per_dp8_888_r\'\n per_dp8_888_r per_instance(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.v\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.sv\n per_dp8_888_r\n per_dp8_888_r.v\n per_dp8_888_r.sv\n obj_dir/per_dp8_888_r\n obj_dir/per_dp8_888_r.v\n obj_dir/per_dp8_888_r.sv\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:236: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:237: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:239: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:240: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:241: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:242: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:243: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:252: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:253: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:254: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:255: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:256: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:257: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:258: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:91: Cannot find file containing module: \'per_dp4_0_r\'\n per_dp4_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:135: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:136: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:137: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:138: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:146: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:147: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:148: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:149: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:19: Cannot find file containing module: \'per_dp2_0_r\'\n per_dp2_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:54: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:55: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:64: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i+0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Error: Exiting due to 3 error(s), 44 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,470 | module | module per_p4_test;
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter SIZE = 256;
parameter DP = 4;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp4_0_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.inData_2(data_in[2]),
.inData_3(data_in[3]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.outData_2(data_out[2]),
.outData_3(data_out[3]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = 0;
data_in[1] = 0;
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 4*i;
data_in[1] = 4*i+1;
data_in[2] = 4*i+2;
data_in[3] = 4*i+3;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 4*i;
data_in[1] = 4*i+1;
data_in[2] = 4*i+2;
data_in[3] = 4*i+3;
ctrl_in = 0;
end
end
endmodule | module per_p4_test; |
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter SIZE = 256;
parameter DP = 4;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp4_0_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.inData_2(data_in[2]),
.inData_3(data_in[3]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.outData_2(data_out[2]),
.outData_3(data_out[3]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = 0;
data_in[1] = 0;
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 4*i;
data_in[1] = 4*i+1;
data_in[2] = 4*i+2;
data_in[3] = 4*i+3;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = 4*i;
data_in[1] = 4*i+1;
data_in[2] = 4*i+2;
data_in[3] = 4*i+3;
ctrl_in = 0;
end
end
endmodule | 0 |
4,267 | data/full_repos/permissive/109231608/bitrev_files/per_testbench.v | 109,231,608 | per_testbench.v | v | 265 | 49 | [] | [] | [] | [(2, 72), (75, 156), (160, 265)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:111: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:124: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:125: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:134: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:204: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:221: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:222: Unsupported: Ignoring delay on this delayed statement.\n #3.0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:235: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:250: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_TIME;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:75: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'per_p2_test\'\nmodule per_p2_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p4_test\'\nmodule per_p4_test;\n ^~~~~~~~~~~\n : ... Top module \'per_p8_test\'\nmodule per_p8_test;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:176: Cannot find file containing module: \'per_dp8_888_r\'\n per_dp8_888_r per_instance(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.v\n data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.sv\n per_dp8_888_r\n per_dp8_888_r.v\n per_dp8_888_r.sv\n obj_dir/per_dp8_888_r\n obj_dir/per_dp8_888_r.v\n obj_dir/per_dp8_888_r.sv\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:236: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:237: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:239: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:240: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:241: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:242: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:243: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p8_test\n data_in[0] = DP*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:252: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[1] = DP*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:253: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[2] = DP*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:254: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[3] = DP*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:255: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[4] = DP*i+4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:256: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[5] = DP*i+5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:257: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[6] = DP*i+6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:258: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p8_test\n data_in[7] = DP*i+7;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:91: Cannot find file containing module: \'per_dp4_0_r\'\n per_dp4_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:135: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:136: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:137: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:138: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:146: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p4_test\n data_in[0] = 4*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:147: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[1] = 4*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:148: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[2] = 4*i+2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:149: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p4_test\n data_in[3] = 4*i+3;\n ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:19: Cannot find file containing module: \'per_dp2_0_r\'\n per_dp2_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:54: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:55: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:64: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[0] = 2*i+0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance per_p2_test\n data_in[1] = 2*i+1;\n ^\n%Error: Exiting due to 3 error(s), 44 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,470 | module | module per_p8_test;
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter SIZE = 16;
parameter DP = 8;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp8_888_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.inData_2(data_in[2]),
.inData_3(data_in[3]),
.inData_4(data_in[4]),
.inData_5(data_in[5]),
.inData_6(data_in[6]),
.inData_7(data_in[7]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.outData_2(data_out[2]),
.outData_3(data_out[3]),
.outData_4(data_out[4]),
.outData_5(data_out[5]),
.outData_6(data_out[6]),
.outData_7(data_out[7]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
data_in[4] = {DATA_WIDTH{1'b0}};
data_in[5] = {DATA_WIDTH{1'b0}};
data_in[6] = {DATA_WIDTH{1'b0}};
data_in[7] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
data_in[4] = {DATA_WIDTH{1'b0}};
data_in[5] = {DATA_WIDTH{1'b0}};
data_in[6] = {DATA_WIDTH{1'b0}};
data_in[7] = {DATA_WIDTH{1'b0}};
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = DP*i;
data_in[1] = DP*i+1;
data_in[2] = DP*i+2;
data_in[3] = DP*i+3;
data_in[4] = DP*i+4;
data_in[5] = DP*i+5;
data_in[6] = DP*i+6;
data_in[7] = DP*i+7;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = DP*i;
data_in[1] = DP*i+1;
data_in[2] = DP*i+2;
data_in[3] = DP*i+3;
data_in[4] = DP*i+4;
data_in[5] = DP*i+5;
data_in[6] = DP*i+6;
data_in[7] = DP*i+7;
ctrl_in = 0;
end
end
endmodule | module per_p8_test; |
parameter CLOCK_TIME = 5.0;
parameter DATA_WIDTH = 16;
parameter SIZE = 16;
parameter DP = 8;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_in [DP-1:0];
reg ctrl_in;
wire [DATA_WIDTH-1:0] data_out [DP-1:0];
wire ctrl_out;
per_dp8_888_r per_instance(
.inData_0(data_in[0]),
.inData_1(data_in[1]),
.inData_2(data_in[2]),
.inData_3(data_in[3]),
.inData_4(data_in[4]),
.inData_5(data_in[5]),
.inData_6(data_in[6]),
.inData_7(data_in[7]),
.outData_0(data_out[0]),
.outData_1(data_out[1]),
.outData_2(data_out[2]),
.outData_3(data_out[3]),
.outData_4(data_out[4]),
.outData_5(data_out[5]),
.outData_6(data_out[6]),
.outData_7(data_out[7]),
.in_start(ctrl_in),
.out_start(ctrl_out),
.clk(clk),
.rst(rst)
);
integer i;
always #(CLOCK_TIME/2) clk=~clk;
initial begin
clk = 0;
rst = 1;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
data_in[4] = {DATA_WIDTH{1'b0}};
data_in[5] = {DATA_WIDTH{1'b0}};
data_in[6] = {DATA_WIDTH{1'b0}};
data_in[7] = {DATA_WIDTH{1'b0}};
ctrl_in = 0;
#100;
#3.0;
rst = 0;
data_in[0] = {DATA_WIDTH{1'b0}};
data_in[1] = {DATA_WIDTH{1'b0}};
data_in[2] = {DATA_WIDTH{1'b0}};
data_in[3] = {DATA_WIDTH{1'b0}};
data_in[4] = {DATA_WIDTH{1'b0}};
data_in[5] = {DATA_WIDTH{1'b0}};
data_in[6] = {DATA_WIDTH{1'b0}};
data_in[7] = {DATA_WIDTH{1'b0}};
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = DP*i;
data_in[1] = DP*i+1;
data_in[2] = DP*i+2;
data_in[3] = DP*i+3;
data_in[4] = DP*i+4;
data_in[5] = DP*i+5;
data_in[6] = DP*i+6;
data_in[7] = DP*i+7;
ctrl_in = 0;
end
ctrl_in = 1;
for(i=0; i<SIZE/DP; i=i+1)begin
#CLOCK_TIME;
data_in[0] = DP*i;
data_in[1] = DP*i+1;
data_in[2] = DP*i+2;
data_in[3] = DP*i+3;
data_in[4] = DP*i+4;
data_in[5] = DP*i+5;
data_in[6] = DP*i+6;
data_in[7] = DP*i+7;
ctrl_in = 0;
end
end
endmodule | 0 |
4,270 | data/full_repos/permissive/109394014/blocks/Flow/PxsSplit2.v | 109,394,014 | PxsSplit2.v | v | 35 | 83 | [] | ['gpl license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Flow/PxsSplit2.v:20: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Flow,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Flow,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Flow,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 2,474 | module | module PxsSplit2 (
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr1_o,
output reg [25:0] RGBStr2_o
);
always @(posedge px_clk)
begin
RGBStr1_o <= RGBStr_i;
RGBStr2_o <= RGBStr_i;
end
endmodule | module PxsSplit2 (
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr1_o,
output reg [25:0] RGBStr2_o
); |
always @(posedge px_clk)
begin
RGBStr1_o <= RGBStr_i;
RGBStr2_o <= RGBStr_i;
end
endmodule | 47 |
4,272 | data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v | 109,394,014 | PxsBouncingBall.v | v | 114 | 101 | [] | ['gpl license'] | [] | [(74, 166)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:59: Define or directive not defined: \'`XC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:59: Define or directive not defined: \'`YC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:65: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= RGBStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`VGA] <= RGBStr_i[`VGA];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:65: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= RGBStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:67: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= (\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`RGB] <= (\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:68: Define or directive not defined: \'`YC\'\n (RGBStr_i[`YC] > y_ball) && (RGBStr_i[`YC] < y_ball+SIZE_BALL) &&\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:68: Define or directive not defined: \'`YC\'\n (RGBStr_i[`YC] > y_ball) && (RGBStr_i[`YC] < y_ball+SIZE_BALL) &&\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:69: Define or directive not defined: \'`XC\'\n (RGBStr_i[`XC] > x_ball) && (RGBStr_i[`XC] < x_ball+SIZE_BALL)\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:69: Define or directive not defined: \'`XC\'\n (RGBStr_i[`XC] > x_ball) && (RGBStr_i[`XC] < x_ball+SIZE_BALL)\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsBouncingBall.v:70: Define or directive not defined: \'`RGB\'\n ) ? 3\'b101 : RGBStr_i[`RGB];\n ^~~~\n%Error: Exiting due to 14 error(s)\n' | 2,477 | module | module PxsBouncingBall #(
parameter SIZE_BALL = 16)
(
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
);
parameter border = 0;
parameter [9:0] x_ball_min = border;
parameter [9:0] x_ball_max = 640 - SIZE_BALL - border;
parameter [9:0] y_ball_min = border;
parameter [9:0] y_ball_max = 480 - SIZE_BALL - border;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
reg [4:0] speed;
reg dx,dy;
wire endframe;
reg [9:0] x_ball, y_ball;
reg [9:0] BX, BY;
reg [25:0] AuxStr1, AuxStr2;
reg Ball;
initial
begin
x_ball <= (640 - SIZE_BALL)/4;
y_ball <= (480 - SIZE_BALL)/2;
dx <=0;
dy <=0;
speed <= 1;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= RGBStr_i[`VGA];
RGBStr_o[`RGB] <= (
(RGBStr_i[`YC] > y_ball) && (RGBStr_i[`YC] < y_ball+SIZE_BALL) &&
(RGBStr_i[`XC] > x_ball) && (RGBStr_i[`XC] < x_ball+SIZE_BALL)
) ? 3'b101 : RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
if (x_ball>=x_ball_max || x_ball>=(VISIBLECOLS-speed-border) || x_ball<border || x_ball<speed)
begin
dx = ~ dx;
end
if (y_ball>=y_ball_max || y_ball>=(VISIBLEROWS-speed-border) || y_ball<border || y_ball<speed)
begin
dy = ~ dy;
end
if (dx==0)
x_ball = x_ball+speed;
else
x_ball = x_ball-speed;
if (dy==0)
y_ball = y_ball+speed;
else
y_ball = y_ball-speed;
end
end
endmodule | module PxsBouncingBall #(
parameter SIZE_BALL = 16)
(
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
); |
parameter border = 0;
parameter [9:0] x_ball_min = border;
parameter [9:0] x_ball_max = 640 - SIZE_BALL - border;
parameter [9:0] y_ball_min = border;
parameter [9:0] y_ball_max = 480 - SIZE_BALL - border;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
reg [4:0] speed;
reg dx,dy;
wire endframe;
reg [9:0] x_ball, y_ball;
reg [9:0] BX, BY;
reg [25:0] AuxStr1, AuxStr2;
reg Ball;
initial
begin
x_ball <= (640 - SIZE_BALL)/4;
y_ball <= (480 - SIZE_BALL)/2;
dx <=0;
dy <=0;
speed <= 1;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= RGBStr_i[`VGA];
RGBStr_o[`RGB] <= (
(RGBStr_i[`YC] > y_ball) && (RGBStr_i[`YC] < y_ball+SIZE_BALL) &&
(RGBStr_i[`XC] > x_ball) && (RGBStr_i[`XC] < x_ball+SIZE_BALL)
) ? 3'b101 : RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
if (x_ball>=x_ball_max || x_ball>=(VISIBLECOLS-speed-border) || x_ball<border || x_ball<speed)
begin
dx = ~ dx;
end
if (y_ball>=y_ball_max || y_ball>=(VISIBLEROWS-speed-border) || y_ball<border || y_ball<speed)
begin
dy = ~ dy;
end
if (dx==0)
x_ball = x_ball+speed;
else
x_ball = x_ball-speed;
if (dy==0)
y_ball = y_ball+speed;
else
y_ball = y_ball-speed;
end
end
endmodule | 47 |
4,276 | data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v | 109,394,014 | PxsLogoPattern.v | v | 136 | 83 | [] | ['gpl license'] | [] | [(79, 188)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:24: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:77: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:78: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:79: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=VGAStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:79: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`Active]<=VGAStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:79: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=VGAStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:85: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: Define or directive not defined: \'`YC\'\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:86: Define or directive not defined: \'`YC\'\n RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:87: Define or directive not defined: \'`Active\'\n RGBStr_o[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`Active]<=AuxStr1[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:87: Define or directive not defined: \'`Active\'\n RGBStr_o[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:89: Define or directive not defined: \'`Active\'\n if(AuxStr1[`Active])\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:89: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if(AuxStr1[`Active])\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:90: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<= pixel? ink: background;\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsLogoPattern.v:92: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<=black;\n ^~~~\n%Error: Exiting due to 35 error(s)\n' | 2,484 | module | module PxsLogoPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
);
`define addy 8:3
`define addx 18:13
`define addy2 9:4
`define addx2 19:14
parameter FILE_LOGO = "darthvaderlogo.list";
parameter width_logo = 64;
parameter height_logo = 64;
reg [0:0] logo [width_logo*height_logo-1:0];
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = black;
parameter background = white;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
wire [13:0] addr;
reg [9:0] x_img, y_img;
reg [22:0] AuxStr1;
reg pixel;
initial
begin
if (FILE_LOGO) $readmemh(FILE_LOGO, logo);
end
assign addr={VGAStr_i[`addy],VGAStr_i[`addx]};
always @(posedge px_clk)
begin
AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];
AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];
AuxStr1[`Active]<=VGAStr_i[`Active];
pixel <= logo [addr];
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];
RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];
RGBStr_o[`Active]<=AuxStr1[`Active];
if(AuxStr1[`Active])
RGBStr_o[`RGB]<= pixel? ink: background;
else
RGBStr_o[`RGB]<=black;
end
endmodule | module PxsLogoPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
); |
`define addy 8:3
`define addx 18:13
`define addy2 9:4
`define addx2 19:14
parameter FILE_LOGO = "darthvaderlogo.list";
parameter width_logo = 64;
parameter height_logo = 64;
reg [0:0] logo [width_logo*height_logo-1:0];
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = black;
parameter background = white;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
wire [13:0] addr;
reg [9:0] x_img, y_img;
reg [22:0] AuxStr1;
reg pixel;
initial
begin
if (FILE_LOGO) $readmemh(FILE_LOGO, logo);
end
assign addr={VGAStr_i[`addy],VGAStr_i[`addx]};
always @(posedge px_clk)
begin
AuxStr1[`HS]<=VGAStr_i[`HS]; AuxStr1[`VS]<=VGAStr_i[`VS];
AuxStr1[`XC]<=VGAStr_i[`XC]; AuxStr1[`YC]<=VGAStr_i[`YC];
AuxStr1[`Active]<=VGAStr_i[`Active];
pixel <= logo [addr];
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];
RGBStr_o[`XC]<=AuxStr1[`XC]; RGBStr_o[`YC]<=AuxStr1[`YC];
RGBStr_o[`Active]<=AuxStr1[`Active];
if(AuxStr1[`Active])
RGBStr_o[`RGB]<= pixel? ink: background;
else
RGBStr_o[`RGB]<=black;
end
endmodule | 47 |
4,278 | data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v | 109,394,014 | PxsScoreOverlay.v | v | 183 | 130 | [] | ['gpl license'] | [] | [(74, 235)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:119: Define or directive not defined: \'`XC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:119: Define or directive not defined: \'`YC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:131: Define or directive not defined: \'`XC\'\n x_imgTens <= RGBStr_i[`XC]-Sc1_TensX; \n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:131: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n x_imgTens <= RGBStr_i[`XC]-Sc1_TensX; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:132: Define or directive not defined: \'`XC\'\n x_imgOnes <= RGBStr_i[`XC]-Sc1_OnesX; \n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:132: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n x_imgOnes <= RGBStr_i[`XC]-Sc1_OnesX; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:133: Define or directive not defined: \'`YC\'\n y_imgTens <= RGBStr_i[`YC]-Sc1_TensY; \n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:133: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n y_imgTens <= RGBStr_i[`YC]-Sc1_TensY; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:134: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:135: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:136: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:136: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:136: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:137: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:137: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:137: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:144: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:145: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:146: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:146: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:146: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:147: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:147: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:147: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:161: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:161: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:161: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlay.v:161: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,486 | module | module PxsScoreOverlay(
input wire px_clk,
input wire [7:0] score,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
);
parameter FILE_NUMBERS = "numbers2b.list";
parameter width_number = 8;
parameter height_number = 8;
reg [0:0] Nums [10*height_number*width_number-1:0];
parameter Sc1_TensX = 128;
parameter Sc1_TensY = 8;
parameter DigitStride = 4;
parameter Sc1_OnesX = Sc1_TensX+width_number+DigitStride;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = white;
parameter background = black;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
wire [9:0] TensAddr, OnesAddr;
reg [9:0] addr;
wire endframe;
reg [9:0] x_imgTens, x_imgOnes, y_imgTens;
reg [25:0] AuxStr1, AuxStr2;
reg InTensDigit, InOnesDigit;
reg pixel;
initial
begin
if (FILE_NUMBERS) $readmemh(FILE_NUMBERS, Nums);
end
integer i;
reg [3:0] Tens, TensDigit;
reg [3:0] Ones, OnesDigit;
always @(score)
begin
Tens = 4'd0;
Ones = 4'd0;
for (i=7; i>=0; i=i-1)
begin
if (Tens>4)
Tens=Tens+4'd3;
if (Ones>4)
Ones=Ones+4'd3;
Tens = Tens <<1;
Tens[0]=Ones[3];
Ones = Ones <<1;
Ones[0] = score[i];
end
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
assign TensAddr = {TensDigit,y_imgTens[2:0],x_imgTens[2:0]};
assign OnesAddr = {OnesDigit,y_imgTens[2:0],x_imgOnes[2:0]};
always @(posedge px_clk)
begin
x_imgTens <= RGBStr_i[`XC]-Sc1_TensX;
x_imgOnes <= RGBStr_i[`XC]-Sc1_OnesX;
y_imgTens <= RGBStr_i[`YC]-Sc1_TensY;
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
InTensDigit<= (x_imgTens >= 0 && x_imgTens < width_number) && (y_imgTens >= 0 && y_imgTens < height_number);
InOnesDigit<= (x_imgOnes >= 0 && x_imgOnes < width_number) && (y_imgTens >= 0 && y_imgTens < height_number);
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
AuxStr2[`RGB]<=AuxStr1[`RGB];
if ((x_imgTens>= 0) && (x_imgTens < width_number) && (y_imgTens>= 0) && (y_imgTens < height_number))
addr <= TensAddr;
else
if ((x_imgOnes >= 0 && x_imgOnes < width_number) && (y_imgTens >= 0 && y_imgTens < height_number))
addr <= OnesAddr;
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if(InTensDigit || InOnesDigit)
RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr2[`RGB];
else
RGBStr_o[`RGB]<=AuxStr2[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
OnesDigit <= Ones;
TensDigit <= Tens;
end
end
endmodule | module PxsScoreOverlay(
input wire px_clk,
input wire [7:0] score,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
); |
parameter FILE_NUMBERS = "numbers2b.list";
parameter width_number = 8;
parameter height_number = 8;
reg [0:0] Nums [10*height_number*width_number-1:0];
parameter Sc1_TensX = 128;
parameter Sc1_TensY = 8;
parameter DigitStride = 4;
parameter Sc1_OnesX = Sc1_TensX+width_number+DigitStride;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = white;
parameter background = black;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
wire [9:0] TensAddr, OnesAddr;
reg [9:0] addr;
wire endframe;
reg [9:0] x_imgTens, x_imgOnes, y_imgTens;
reg [25:0] AuxStr1, AuxStr2;
reg InTensDigit, InOnesDigit;
reg pixel;
initial
begin
if (FILE_NUMBERS) $readmemh(FILE_NUMBERS, Nums);
end
integer i;
reg [3:0] Tens, TensDigit;
reg [3:0] Ones, OnesDigit;
always @(score)
begin
Tens = 4'd0;
Ones = 4'd0;
for (i=7; i>=0; i=i-1)
begin
if (Tens>4)
Tens=Tens+4'd3;
if (Ones>4)
Ones=Ones+4'd3;
Tens = Tens <<1;
Tens[0]=Ones[3];
Ones = Ones <<1;
Ones[0] = score[i];
end
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
assign TensAddr = {TensDigit,y_imgTens[2:0],x_imgTens[2:0]};
assign OnesAddr = {OnesDigit,y_imgTens[2:0],x_imgOnes[2:0]};
always @(posedge px_clk)
begin
x_imgTens <= RGBStr_i[`XC]-Sc1_TensX;
x_imgOnes <= RGBStr_i[`XC]-Sc1_OnesX;
y_imgTens <= RGBStr_i[`YC]-Sc1_TensY;
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
InTensDigit<= (x_imgTens >= 0 && x_imgTens < width_number) && (y_imgTens >= 0 && y_imgTens < height_number);
InOnesDigit<= (x_imgOnes >= 0 && x_imgOnes < width_number) && (y_imgTens >= 0 && y_imgTens < height_number);
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
AuxStr2[`RGB]<=AuxStr1[`RGB];
if ((x_imgTens>= 0) && (x_imgTens < width_number) && (y_imgTens>= 0) && (y_imgTens < height_number))
addr <= TensAddr;
else
if ((x_imgOnes >= 0 && x_imgOnes < width_number) && (y_imgTens >= 0 && y_imgTens < height_number))
addr <= OnesAddr;
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if(InTensDigit || InOnesDigit)
RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr2[`RGB];
else
RGBStr_o[`RGB]<=AuxStr2[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
OnesDigit <= Ones;
TensDigit <= Tens;
end
end
endmodule | 47 |
4,279 | data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v | 109,394,014 | PxsScoreOverlayLite.v | v | 136 | 97 | [] | ['gpl license'] | [] | [(90, 188)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:35: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Overlay,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:85: Define or directive not defined: \'`XC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:85: Define or directive not defined: \'`YC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:91: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:92: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:92: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:92: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:93: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:93: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:93: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:100: Define or directive not defined: \'`XC\'\n InScore1X <= (RGBStr_i[`XC]==Score1X)? 1 : ((RGBStr_i[`XC]==160)? 0 : InScore1X);\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:100: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n InScore1X <= (RGBStr_i[`XC]==Score1X)? 1 : ((RGBStr_i[`XC]==160)? 0 : InScore1X);\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:100: Define or directive not defined: \'`XC\'\n InScore1X <= (RGBStr_i[`XC]==Score1X)? 1 : ((RGBStr_i[`XC]==160)? 0 : InScore1X);\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:101: Define or directive not defined: \'`YC\'\n InScore1Y <= (RGBStr_i[`YC]==Score1Y)? 1 : ((RGBStr_i[`YC]==64)? 0 : InScore1Y);\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:101: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n InScore1Y <= (RGBStr_i[`YC]==Score1Y)? 1 : ((RGBStr_i[`YC]==64)? 0 : InScore1Y);\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:101: Define or directive not defined: \'`YC\'\n InScore1Y <= (RGBStr_i[`YC]==Score1Y)? 1 : ((RGBStr_i[`YC]==64)? 0 : InScore1Y);\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:109: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:113: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:113: Define or directive not defined: \'`YC\'\n RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:114: Define or directive not defined: \'`Active\'\n RGBStr_o[`Active]<=1;\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:114: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`Active]<=1;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:119: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr1[`RGB]; \n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:119: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr1[`RGB]; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:119: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr1[`RGB]; \n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:121: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`RGB]<=AuxStr1[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Overlay/PxsScoreOverlayLite.v:121: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: Exiting due to 40 error(s)\n' | 2,487 | module | module PxsScoreOverlayLite(
input wire px_clk,
input wire [7:0] score,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
);
parameter FILE_NUMBERS = "numbers2b.list";
parameter width_number = 8;
parameter height_number = 8;
reg [0:0] Nums [10*height_number*width_number-1:0];
parameter Score1X = 128;
parameter Score1Y = 32;
parameter DigitStride = 4;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = pink;
parameter background = black;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
reg [9:0] addr;
wire endframe;
reg [25:0] AuxStr1;
reg InScore1X, InScore1Y, InScore2X, InScore2Y;
reg pixel;
initial
begin
if (FILE_NUMBERS) $readmemh(FILE_NUMBERS, Nums);
end
reg [3:0] TensDigit, OnesDigit;
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
InScore1X <= (RGBStr_i[`XC]==Score1X)? 1 : ((RGBStr_i[`XC]==160)? 0 : InScore1X);
InScore1Y <= (RGBStr_i[`YC]==Score1Y)? 1 : ((RGBStr_i[`YC]==64)? 0 : InScore1Y);
addr <= {OnesDigit, RGBStr_i[7:5], RGBStr_i[17:15]};
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];
RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;
RGBStr_o[`Active]<=1;
if(InScore1X && InScore1Y)
RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr1[`RGB];
else
RGBStr_o[`RGB]<=AuxStr1[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
OnesDigit <= score[3:0];
TensDigit <= score[7:4];
end
end
endmodule | module PxsScoreOverlayLite(
input wire px_clk,
input wire [7:0] score,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
); |
parameter FILE_NUMBERS = "numbers2b.list";
parameter width_number = 8;
parameter height_number = 8;
reg [0:0] Nums [10*height_number*width_number-1:0];
parameter Score1X = 128;
parameter Score1Y = 32;
parameter DigitStride = 4;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = pink;
parameter background = black;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
reg [9:0] addr;
wire endframe;
reg [25:0] AuxStr1;
reg InScore1X, InScore1Y, InScore2X, InScore2Y;
reg pixel;
initial
begin
if (FILE_NUMBERS) $readmemh(FILE_NUMBERS, Nums);
end
reg [3:0] TensDigit, OnesDigit;
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
InScore1X <= (RGBStr_i[`XC]==Score1X)? 1 : ((RGBStr_i[`XC]==160)? 0 : InScore1X);
InScore1Y <= (RGBStr_i[`YC]==Score1Y)? 1 : ((RGBStr_i[`YC]==64)? 0 : InScore1Y);
addr <= {OnesDigit, RGBStr_i[7:5], RGBStr_i[17:15]};
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr1[`HS]; RGBStr_o[`VS]<=AuxStr1[`VS];
RGBStr_o[`XC]<=0; RGBStr_o[`YC]<=0;
RGBStr_o[`Active]<=1;
if(InScore1X && InScore1Y)
RGBStr_o[`RGB]<= Nums[addr]? ink: AuxStr1[`RGB];
else
RGBStr_o[`RGB]<=AuxStr1[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
OnesDigit <= score[3:0];
TensDigit <= score[7:4];
end
end
endmodule | 47 |
4,281 | data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v | 109,394,014 | PxsStrComp.v | v | 45 | 97 | [] | ['gpl license'] | [] | [(75, 97)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:20: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:35: Define or directive not defined: \'`HS\'\n assign HSync = VGA_SCA_RGB_Str_i[`HS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign HSync = VGA_SCA_RGB_Str_i[`HS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:36: Define or directive not defined: \'`VS\'\n assign VSync = VGA_SCA_RGB_Str_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VSync = VGA_SCA_RGB_Str_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:37: Define or directive not defined: \'`Active\'\n assign ActiveVideo = VGA_SCA_RGB_Str_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ActiveVideo = VGA_SCA_RGB_Str_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:38: Define or directive not defined: \'`XC\'\n assign XCoord = VGA_SCA_RGB_Str_i[`XC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign XCoord = VGA_SCA_RGB_Str_i[`XC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:39: Define or directive not defined: \'`YC\'\n assign YCoord = VGA_SCA_RGB_Str_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign YCoord = VGA_SCA_RGB_Str_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:40: Define or directive not defined: \'`R\'\n assign Red = VGA_SCA_RGB_Str_i[`R];\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign Red = VGA_SCA_RGB_Str_i[`R];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:41: Define or directive not defined: \'`G\'\n assign Green = VGA_SCA_RGB_Str_i[`G];\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign Green = VGA_SCA_RGB_Str_i[`G];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:42: Define or directive not defined: \'`B\'\n assign Blue = VGA_SCA_RGB_Str_i[`B];\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrComp.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign Blue = VGA_SCA_RGB_Str_i[`B];\n ^\n%Error: Exiting due to 17 error(s)\n' | 2,490 | module | module PxsStrComp (
input wire [25:0] VGA_SCA_RGB_Str_i,
output wire HSync,
output wire VSync,
output wire Red,
output wire Green,
output wire Blue,
output wire [9:0] XCoord,
output wire [9:0] YCoord,
output wire ActiveVideo
);
assign HSync = VGA_SCA_RGB_Str_i[`HS];
assign VSync = VGA_SCA_RGB_Str_i[`VS];
assign ActiveVideo = VGA_SCA_RGB_Str_i[`Active];
assign XCoord = VGA_SCA_RGB_Str_i[`XC];
assign YCoord = VGA_SCA_RGB_Str_i[`YC];
assign Red = VGA_SCA_RGB_Str_i[`R];
assign Green = VGA_SCA_RGB_Str_i[`G];
assign Blue = VGA_SCA_RGB_Str_i[`B];
endmodule | module PxsStrComp (
input wire [25:0] VGA_SCA_RGB_Str_i,
output wire HSync,
output wire VSync,
output wire Red,
output wire Green,
output wire Blue,
output wire [9:0] XCoord,
output wire [9:0] YCoord,
output wire ActiveVideo
); |
assign HSync = VGA_SCA_RGB_Str_i[`HS];
assign VSync = VGA_SCA_RGB_Str_i[`VS];
assign ActiveVideo = VGA_SCA_RGB_Str_i[`Active];
assign XCoord = VGA_SCA_RGB_Str_i[`XC];
assign YCoord = VGA_SCA_RGB_Str_i[`YC];
assign Red = VGA_SCA_RGB_Str_i[`R];
assign Green = VGA_SCA_RGB_Str_i[`G];
assign Blue = VGA_SCA_RGB_Str_i[`B];
endmodule | 47 |
4,282 | data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v | 109,394,014 | PxsStrJoin.v | v | 45 | 83 | [] | ['gpl license'] | [] | [(75, 97)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:20: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:35: Define or directive not defined: \'`HS\'\n assign VGAStr[`HS]= HSync;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`HS]= HSync;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:36: Define or directive not defined: \'`VS\'\n assign VGAStr[`VS]= VSync;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`VS]= VSync;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:37: Define or directive not defined: \'`Active\'\n assign VGAStr[`Active] = ActiveVideo;\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`Active] = ActiveVideo;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:38: Define or directive not defined: \'`XC\'\n assign VGAStr[`XC] = XCoord;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`XC] = XCoord;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:39: Define or directive not defined: \'`YC\'\n assign VGAStr[`YC] = YCoord;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`YC] = YCoord;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:40: Define or directive not defined: \'`R\'\n assign VGAStr[`R] = Red;\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`R] = Red;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:41: Define or directive not defined: \'`G\'\n assign VGAStr[`G] = Green;\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`G] = Green;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:42: Define or directive not defined: \'`B\'\n assign VGAStr[`B] = Blue;\n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrJoin.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign VGAStr[`B] = Blue;\n ^\n%Error: Exiting due to 17 error(s)\n' | 2,491 | module | module PxsStrJoin (
input wire HSync,
input wire VSync,
input wire Red,
input wire Green,
input wire Blue,
input wire [9:0] XCoord,
input wire [9:0] YCoord,
input wire ActiveVideo,
output wire [25:0] VGAStr
);
assign VGAStr[`HS]= HSync;
assign VGAStr[`VS]= VSync;
assign VGAStr[`Active] = ActiveVideo;
assign VGAStr[`XC] = XCoord;
assign VGAStr[`YC] = YCoord;
assign VGAStr[`R] = Red;
assign VGAStr[`G] = Green;
assign VGAStr[`B] = Blue;
endmodule | module PxsStrJoin (
input wire HSync,
input wire VSync,
input wire Red,
input wire Green,
input wire Blue,
input wire [9:0] XCoord,
input wire [9:0] YCoord,
input wire ActiveVideo,
output wire [25:0] VGAStr
); |
assign VGAStr[`HS]= HSync;
assign VGAStr[`VS]= VSync;
assign VGAStr[`Active] = ActiveVideo;
assign VGAStr[`XC] = XCoord;
assign VGAStr[`YC] = YCoord;
assign VGAStr[`R] = Red;
assign VGAStr[`G] = Green;
assign VGAStr[`B] = Blue;
endmodule | 47 |
4,283 | data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v | 109,394,014 | PxsStrVGAJoin.v | v | 42 | 83 | [] | [] | [] | [(79, 94)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:24: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Utils,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:35: Define or directive not defined: \'`HS\'\nassign VGAStr_o[`HS] = HSync;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign VGAStr_o[`HS] = HSync;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:36: Define or directive not defined: \'`VS\'\nassign VGAStr_o[`VS] = VSync;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign VGAStr_o[`VS] = VSync;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:37: Define or directive not defined: \'`Active\'\nassign VGAStr_o[`Active] = ActiveVideo;\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign VGAStr_o[`Active] = ActiveVideo;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:38: Define or directive not defined: \'`XC\'\nassign VGAStr_o[`XC] = XCoord;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign VGAStr_o[`XC] = XCoord;\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:39: Define or directive not defined: \'`YC\'\nassign VGAStr_o[`YC] = YCoord;\n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Utils/PxsStrVGAJoin.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign VGAStr_o[`YC] = YCoord;\n ^\n%Error: Exiting due to 11 error(s)\n' | 2,492 | module | module PxsStrVGAJoin (
input wire HSync,
input wire VSync,
input wire [9:0] XCoord,
input wire [9:0] YCoord,
input wire ActiveVideo,
output wire [22:0] VGAStr_o
);
assign VGAStr_o[`HS] = HSync;
assign VGAStr_o[`VS] = VSync;
assign VGAStr_o[`Active] = ActiveVideo;
assign VGAStr_o[`XC] = XCoord;
assign VGAStr_o[`YC] = YCoord;
endmodule | module PxsStrVGAJoin (
input wire HSync,
input wire VSync,
input wire [9:0] XCoord,
input wire [9:0] YCoord,
input wire ActiveVideo,
output wire [22:0] VGAStr_o
); |
assign VGAStr_o[`HS] = HSync;
assign VGAStr_o[`VS] = VSync;
assign VGAStr_o[`Active] = ActiveVideo;
assign VGAStr_o[`XC] = XCoord;
assign VGAStr_o[`YC] = YCoord;
endmodule | 47 |
4,287 | data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v | 109,394,014 | PxsColorBarsPattern.v | v | 44 | 83 | [] | [] | [] | [(74, 96)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:32: Define or directive not defined: \'`XC\'\nassign Xc = VGAStr_i[`XC]; \n ^~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign Xc = VGAStr_i[`XC]; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:36: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:36: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:37: Define or directive not defined: \'`Active\'\n if (VGAStr_i[`Active])\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if (VGAStr_i[`Active])\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:38: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= Xc[7:5]; \n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsColorBarsPattern.v:40: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= Black;\n ^~~~\n%Error: Exiting due to 10 error(s)\n' | 2,500 | module | module PxsColorBarsPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
);
parameter [3:0] Black=3'b000;
wire [9:0] Xc;
assign Xc = VGAStr_i[`XC];
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= VGAStr_i[`VGA];
if (VGAStr_i[`Active])
RGBStr_o[`RGB] <= Xc[7:5];
else
RGBStr_o[`RGB] <= Black;
end
endmodule | module PxsColorBarsPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
); |
parameter [3:0] Black=3'b000;
wire [9:0] Xc;
assign Xc = VGAStr_i[`XC];
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= VGAStr_i[`VGA];
if (VGAStr_i[`Active])
RGBStr_o[`RGB] <= Xc[7:5];
else
RGBStr_o[`RGB] <= Black;
end
endmodule | 47 |
4,289 | data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v | 109,394,014 | PxsXorPattern.v | v | 52 | 83 | [] | [] | [] | [(81, 104)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:26: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/blocks/Videogen,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:40: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:40: Define or directive not defined: \'`VGA\'\n RGBStr_o[`VGA] <= VGAStr_i[`VGA];\n ^~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:41: Define or directive not defined: \'`Active\'\n if (VGAStr_i[`Active])\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if (VGAStr_i[`Active])\n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:43: Define or directive not defined: \'`R\'\n RGBStr_o[`R] <= comp[3]; \n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:44: Define or directive not defined: \'`G\'\n RGBStr_o[`G] <= comp[3]; \n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`G] <= comp[3]; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:45: Define or directive not defined: \'`B\'\n RGBStr_o[`B] <= comp[4]; \n ^~\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`B] <= comp[4]; \n ^\n%Error: data/full_repos/permissive/109394014/blocks/Videogen/PxsXorPattern.v:48: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= 3\'b000;\n ^~~~\n%Error: Cannot continue\n' | 2,502 | module | module PxsXorPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
);
wire [9:0] comp;
assign comp = VGAStr_i[22:14] ^ VGAStr_i[12:4];
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= VGAStr_i[`VGA];
if (VGAStr_i[`Active])
begin
RGBStr_o[`R] <= comp[3];
RGBStr_o[`G] <= comp[3];
RGBStr_o[`B] <= comp[4];
end
else
RGBStr_o[`RGB] <= 3'b000;
end
endmodule | module PxsXorPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
); |
wire [9:0] comp;
assign comp = VGAStr_i[22:14] ^ VGAStr_i[12:4];
always @(posedge px_clk)
begin
RGBStr_o[`VGA] <= VGAStr_i[`VGA];
if (VGAStr_i[`Active])
begin
RGBStr_o[`R] <= comp[3];
RGBStr_o[`G] <= comp[3];
RGBStr_o[`B] <= comp[4];
end
else
RGBStr_o[`RGB] <= 3'b000;
end
endmodule | 47 |
4,291 | data/full_repos/permissive/109394014/examples/Bmp16ROM.v | 109,394,014 | Bmp16ROM.v | v | 55 | 83 | [] | ['gpl license'] | [] | [(23, 54)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109394014/examples/Bmp16ROM.v:45: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'BMPFILE\' generates 88 bits.\n : ... In instance Bmp16ROM\n if (BMPFILE) $readmemh(BMPFILE, bmps);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,504 | module | module Bmp16ROM (
input wire clk,
input wire [11:0] add,
output reg [3:0] pixel
);
parameter BMPFILE = "pacman.list";
parameter width = 16;
parameter height = 16;
parameter nsprites = 16;
reg [3:0] bmps [nsprites*width*height-1:0];
initial
begin
if (BMPFILE) $readmemh(BMPFILE, bmps);
end
always @(posedge clk)
begin
pixel <= bmps[add];
end
endmodule | module Bmp16ROM (
input wire clk,
input wire [11:0] add,
output reg [3:0] pixel
); |
parameter BMPFILE = "pacman.list";
parameter width = 16;
parameter height = 16;
parameter nsprites = 16;
reg [3:0] bmps [nsprites*width*height-1:0];
initial
begin
if (BMPFILE) $readmemh(BMPFILE, bmps);
end
always @(posedge clk)
begin
pixel <= bmps[add];
end
endmodule | 47 |
4,292 | data/full_repos/permissive/109394014/examples/DisplayGame.v | 109,394,014 | DisplayGame.v | v | 117 | 96 | [] | ['gpl license'] | [] | [(74, 169)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:61: Define or directive not defined: \'`XC\'\n assign sx = RGBStr_i[`XC]; \n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign sx = RGBStr_i[`XC]; \n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:62: Define or directive not defined: \'`YC\'\n assign sy = RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign sy = RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:75: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:76: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:77: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:77: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:77: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:78: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:78: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:78: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:83: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:84: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:85: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:85: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:87: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<= AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`RGB]<= AuxStr1[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:87: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<= AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:88: Define or directive not defined: \'`Active\'\n if (AuxStr1[`Active]) \n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if (AuxStr1[`Active]) \n ^\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:100: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:100: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:100: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:100: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:101: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:101: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/DisplayGame.v:101: Define or directive not defined: \'`YC\'\n RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,506 | module | module DisplayGame (
input wire px_clk,
input wire [25:0] RGBStr_i,
input wire [3:0] TabDat,
input wire [3:0] BmpDat,
output reg [10:0] TabAdd,
output reg [9:0] BmpAdd,
output reg [25:0] RGBStr_o
);
parameter Tab_width = 40;
parameter Tab_height = 30;
parameter Bmp_width = 16;
parameter Bmp_height =16;
parameter VISIBLECOLS = 640;
parameter VISIBLEROWS = 480;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
wire [9:0]sx;
wire [9:0]sy;
wire [5:0]TabX;
wire [4:0]TabY;
reg [3:0]BmpX;
reg [3:0]BmpY;
reg InTabX, InTabY, InTab;
reg [25:0]AuxStr1;
reg [25:0]AuxStr2;
assign sx = RGBStr_i[`XC];
assign sy = RGBStr_i[`YC];
assign TabX = sx[9:4];
assign TabY = sy[8:4];
always @(posedge px_clk)
begin
TabAdd <= TabY*Tab_width+TabX;
InTabX <= (sx==0)? 1: ((sx==Tab_width*Bmp_width) ? 0 : InTabX);
InTabY <= (sy==0)? 1: ((sy==Tab_height*Bmp_height) ? 0 : InTabY);
BmpX <= sx[3:0]; BmpY <= sy[3:0];
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
InTab <= InTabX && InTabY;
AuxStr2[`RGB]<= AuxStr1[`RGB];
if (AuxStr1[`Active])
begin
if(InTabX==1 && InTabY==1)
begin
BmpAdd<={TabDat[1:0],BmpY,BmpX};
end
end
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if (AuxStr2[`Active])
begin
if (InTab)
begin
RGBStr_o[`RGB]<= (BmpDat[2:0]==0)? AuxStr2[`RGB]: BmpDat[2:0];
end
end
else
begin
RGBStr_o[`RGB]<= AuxStr2[`RGB];
end
end
endmodule | module DisplayGame (
input wire px_clk,
input wire [25:0] RGBStr_i,
input wire [3:0] TabDat,
input wire [3:0] BmpDat,
output reg [10:0] TabAdd,
output reg [9:0] BmpAdd,
output reg [25:0] RGBStr_o
); |
parameter Tab_width = 40;
parameter Tab_height = 30;
parameter Bmp_width = 16;
parameter Bmp_height =16;
parameter VISIBLECOLS = 640;
parameter VISIBLEROWS = 480;
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
wire [9:0]sx;
wire [9:0]sy;
wire [5:0]TabX;
wire [4:0]TabY;
reg [3:0]BmpX;
reg [3:0]BmpY;
reg InTabX, InTabY, InTab;
reg [25:0]AuxStr1;
reg [25:0]AuxStr2;
assign sx = RGBStr_i[`XC];
assign sy = RGBStr_i[`YC];
assign TabX = sx[9:4];
assign TabY = sy[8:4];
always @(posedge px_clk)
begin
TabAdd <= TabY*Tab_width+TabX;
InTabX <= (sx==0)? 1: ((sx==Tab_width*Bmp_width) ? 0 : InTabX);
InTabY <= (sy==0)? 1: ((sy==Tab_height*Bmp_height) ? 0 : InTabY);
BmpX <= sx[3:0]; BmpY <= sy[3:0];
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
InTab <= InTabX && InTabY;
AuxStr2[`RGB]<= AuxStr1[`RGB];
if (AuxStr1[`Active])
begin
if(InTabX==1 && InTabY==1)
begin
BmpAdd<={TabDat[1:0],BmpY,BmpX};
end
end
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if (AuxStr2[`Active])
begin
if (InTab)
begin
RGBStr_o[`RGB]<= (BmpDat[2:0]==0)? AuxStr2[`RGB]: BmpDat[2:0];
end
end
else
begin
RGBStr_o[`RGB]<= AuxStr2[`RGB];
end
end
endmodule | 47 |
4,293 | data/full_repos/permissive/109394014/examples/GameTable.v | 109,394,014 | GameTable.v | v | 62 | 84 | [] | ['gpl license'] | [] | [(33, 60)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109394014/examples/GameTable.v:47: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'TABFILE\' generates 96 bits.\n : ... In instance GameTable\n if (TABFILE) $readmemh(TABFILE, mem);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,508 | module | module GameTable (clk, din, write_en, waddr, raddr, dout);
parameter rows = 30;
parameter cols = 40;
parameter addr_width = 11;
parameter nsprites = 4;
input [addr_width-1:0] waddr, raddr;
input [nsprites-1:0] din;
input write_en, clk;
output reg [nsprites-1:0] dout;
reg [nsprites-1:0] mem [(rows*cols)-1:0];
parameter TABFILE="inittab.list";
initial begin
if (TABFILE) $readmemh(TABFILE, mem);
end
always @(posedge clk)
begin
if (write_en)
mem[waddr] <= din;
end
always @(posedge clk)
begin
dout <= mem[raddr];
end
endmodule | module GameTable (clk, din, write_en, waddr, raddr, dout); |
parameter rows = 30;
parameter cols = 40;
parameter addr_width = 11;
parameter nsprites = 4;
input [addr_width-1:0] waddr, raddr;
input [nsprites-1:0] din;
input write_en, clk;
output reg [nsprites-1:0] dout;
reg [nsprites-1:0] mem [(rows*cols)-1:0];
parameter TABFILE="inittab.list";
initial begin
if (TABFILE) $readmemh(TABFILE, mem);
end
always @(posedge clk)
begin
if (write_en)
mem[waddr] <= din;
end
always @(posedge clk)
begin
dout <= mem[raddr];
end
endmodule | 47 |
4,294 | data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v | 109,394,014 | PxsCheckerBoard.v | v | 55 | 83 | [] | ['gpl license'] | [] | [(75, 107)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:20: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:36: Define or directive not defined: \'`XC\'\nassign X = VGA_SCA_Str_i[`XC]/XGridSize;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign X = VGA_SCA_Str_i[`XC]/XGridSize;\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:37: Define or directive not defined: \'`YC\'\nassign Y = VGA_SCA_Str_i[`YC]/YGridSize;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign Y = VGA_SCA_Str_i[`YC]/YGridSize;\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:46: Define or directive not defined: \'`RGB\'\n VGA_SCA_RGB_Str_o[`RGB] <= comp? White: Black; \n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`RGB] <= comp? White: Black; \n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:47: Define or directive not defined: \'`HS\'\n VGA_SCA_RGB_Str_o[`HS] <= VGA_SCA_Str_i[`HS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`HS] <= VGA_SCA_Str_i[`HS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:47: Define or directive not defined: \'`HS\'\n VGA_SCA_RGB_Str_o[`HS] <= VGA_SCA_Str_i[`HS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:48: Define or directive not defined: \'`VS\'\n VGA_SCA_RGB_Str_o[`VS] <= VGA_SCA_Str_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`VS] <= VGA_SCA_Str_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:48: Define or directive not defined: \'`VS\'\n VGA_SCA_RGB_Str_o[`VS] <= VGA_SCA_Str_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:49: Define or directive not defined: \'`XC\'\n VGA_SCA_RGB_Str_o[`XC] <= VGA_SCA_Str_i[`XC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`XC] <= VGA_SCA_Str_i[`XC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:49: Define or directive not defined: \'`XC\'\n VGA_SCA_RGB_Str_o[`XC] <= VGA_SCA_Str_i[`XC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:50: Define or directive not defined: \'`YC\'\n VGA_SCA_RGB_Str_o[`YC] <= VGA_SCA_Str_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`YC] <= VGA_SCA_Str_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:50: Define or directive not defined: \'`YC\'\n VGA_SCA_RGB_Str_o[`YC] <= VGA_SCA_Str_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:51: Define or directive not defined: \'`Active\'\n VGA_SCA_RGB_Str_o[`Active] <= VGA_SCA_Str_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n VGA_SCA_RGB_Str_o[`Active] <= VGA_SCA_Str_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsCheckerBoard.v:51: Define or directive not defined: \'`Active\'\n VGA_SCA_RGB_Str_o[`Active] <= VGA_SCA_Str_i[`Active];\n ^~~~~~~\n%Error: Exiting due to 22 error(s)\n' | 2,515 | module | module PxsCheckerBoard (
input wire px_clk,
input wire [22:0] VGA_SCA_Str_i,
output reg [25:0] VGA_SCA_RGB_Str_o
);
parameter [3:0] Black=3'b000;
parameter [3:0] White=3'b111;
parameter XGridSize = 64;
parameter YGridSize = 64;
wire comp, X0,Y0;
wire [9:0] X, Y;
assign X = VGA_SCA_Str_i[`XC]/XGridSize;
assign Y = VGA_SCA_Str_i[`YC]/YGridSize;
assign comp = X ^ Y;
always @(posedge px_clk)
begin
VGA_SCA_RGB_Str_o[`RGB] <= comp? White: Black;
VGA_SCA_RGB_Str_o[`HS] <= VGA_SCA_Str_i[`HS];
VGA_SCA_RGB_Str_o[`VS] <= VGA_SCA_Str_i[`VS];
VGA_SCA_RGB_Str_o[`XC] <= VGA_SCA_Str_i[`XC];
VGA_SCA_RGB_Str_o[`YC] <= VGA_SCA_Str_i[`YC];
VGA_SCA_RGB_Str_o[`Active] <= VGA_SCA_Str_i[`Active];
end
endmodule | module PxsCheckerBoard (
input wire px_clk,
input wire [22:0] VGA_SCA_Str_i,
output reg [25:0] VGA_SCA_RGB_Str_o
); |
parameter [3:0] Black=3'b000;
parameter [3:0] White=3'b111;
parameter XGridSize = 64;
parameter YGridSize = 64;
wire comp, X0,Y0;
wire [9:0] X, Y;
assign X = VGA_SCA_Str_i[`XC]/XGridSize;
assign Y = VGA_SCA_Str_i[`YC]/YGridSize;
assign comp = X ^ Y;
always @(posedge px_clk)
begin
VGA_SCA_RGB_Str_o[`RGB] <= comp? White: Black;
VGA_SCA_RGB_Str_o[`HS] <= VGA_SCA_Str_i[`HS];
VGA_SCA_RGB_Str_o[`VS] <= VGA_SCA_Str_i[`VS];
VGA_SCA_RGB_Str_o[`XC] <= VGA_SCA_Str_i[`XC];
VGA_SCA_RGB_Str_o[`YC] <= VGA_SCA_Str_i[`YC];
VGA_SCA_RGB_Str_o[`Active] <= VGA_SCA_Str_i[`Active];
end
endmodule | 47 |
4,295 | data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v | 109,394,014 | PxsColorBarsPattern.v | v | 49 | 83 | [] | [] | [] | [(74, 101)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:33: Define or directive not defined: \'`XC\'\nassign Xc = VGAStr_i[`XC]; \n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign Xc = VGAStr_i[`XC]; \n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:37: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS] <= VGAStr_i[`HS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS] <= VGAStr_i[`HS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:37: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS] <= VGAStr_i[`HS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:38: Define or directive not defined: \'`VS\'\n RGBStr_o[`VS] <= VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`VS] <= VGAStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:38: Define or directive not defined: \'`VS\'\n RGBStr_o[`VS] <= VGAStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:39: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC] <= VGAStr_i[`XC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`XC] <= VGAStr_i[`XC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:39: Define or directive not defined: \'`XC\'\n RGBStr_o[`XC] <= VGAStr_i[`XC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:40: Define or directive not defined: \'`YC\'\n RGBStr_o[`YC] <= VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`YC] <= VGAStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:40: Define or directive not defined: \'`YC\'\n RGBStr_o[`YC] <= VGAStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:41: Define or directive not defined: \'`Active\'\n RGBStr_o[`Active] <= VGAStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`Active] <= VGAStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:41: Define or directive not defined: \'`Active\'\n RGBStr_o[`Active] <= VGAStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:42: Define or directive not defined: \'`Active\'\n if (VGAStr_i[`Active])\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if (VGAStr_i[`Active])\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:43: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= Xc[7:5]; \n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsColorBarsPattern.v:45: Define or directive not defined: \'`RGB\'\n RGBStr_o[`RGB] <= Black;\n ^~~~\n%Error: Exiting due to 22 error(s)\n' | 2,516 | module | module PxsColorBarsPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
);
parameter [3:0] Black=3'b000;
parameter [3:0] White=3'b111;
wire [9:0] Xc;
assign Xc = VGAStr_i[`XC];
always @(posedge px_clk)
begin
RGBStr_o[`HS] <= VGAStr_i[`HS];
RGBStr_o[`VS] <= VGAStr_i[`VS];
RGBStr_o[`XC] <= VGAStr_i[`XC];
RGBStr_o[`YC] <= VGAStr_i[`YC];
RGBStr_o[`Active] <= VGAStr_i[`Active];
if (VGAStr_i[`Active])
RGBStr_o[`RGB] <= Xc[7:5];
else
RGBStr_o[`RGB] <= Black;
end
endmodule | module PxsColorBarsPattern (
input wire px_clk,
input wire [22:0] VGAStr_i,
output reg [25:0] RGBStr_o
); |
parameter [3:0] Black=3'b000;
parameter [3:0] White=3'b111;
wire [9:0] Xc;
assign Xc = VGAStr_i[`XC];
always @(posedge px_clk)
begin
RGBStr_o[`HS] <= VGAStr_i[`HS];
RGBStr_o[`VS] <= VGAStr_i[`VS];
RGBStr_o[`XC] <= VGAStr_i[`XC];
RGBStr_o[`YC] <= VGAStr_i[`YC];
RGBStr_o[`Active] <= VGAStr_i[`Active];
if (VGAStr_i[`Active])
RGBStr_o[`RGB] <= Xc[7:5];
else
RGBStr_o[`RGB] <= Black;
end
endmodule | 47 |
4,297 | data/full_repos/permissive/109394014/examples/PxsGameUpdate.v | 109,394,014 | PxsGameUpdate.v | v | 192 | 97 | [] | ['gpl license'] | [] | [(74, 238)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/examples/PxsGameUpdate.v:19: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 2,520 | module | module PxsGameUpdate (
input wire px_clk,
input wire rst,
input wire [25:0] RGBStr_i,
output reg write_en,
output reg [10:0] TabAdd,
output reg [3:0] TabDat
);
`define Active 0:0
`define VS 1:1
`define HS 2:2
`define YC 12:3
`define XC 22:13
`define RGB 25:23
parameter VISIBLECOLS=640;
parameter VISIBLEROWS=480;
parameter WAIT = 6'b000001,
RMV_PAC = 6'b000010,
RMV_GOHST = 6'b000100,
UPDT_PACMAN = 6'b001000,
UPDT_GOHST = 6'b010000,
WAIT_0 = 6'b100000;
reg [5:0]state, next_state;
reg [4:0] contframe;
reg [10:0] pospac;
reg close;
initial
begin
contframe <= 0;
pospac<=600;
state <= WAIT;
write_en<=0;
close<=0;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
if (rst)
contframe<=0;
else
if (endframe==1)
contframe <= (contframe == 25)? 0 : contframe+1;
end
always @(posedge contframe[4])
begin
pospac<=pospac-1;
close <= ~close;
end
always @(posedge px_clk)
if (rst) state = WAIT; else state = next_state;
always @(*) begin
next_state = state;
case (state)
WAIT: if (contframe==25) next_state = RMV_PAC;
else next_state = WAIT;
RMV_PAC: next_state = RMV_GOHST;
RMV_GOHST: next_state = UPDT_PACMAN;
UPDT_PACMAN: next_state = UPDT_GOHST;
UPDT_GOHST: next_state = WAIT_0;
WAIT_0: if(contframe==0) next_state = WAIT;
else next_state<= WAIT_0;
endcase
end
always @(state) begin
case (state)
WAIT: begin
write_en = 0;
end
RMV_PAC: begin
write_en = 1;
TabAdd = pospac;
TabDat = 0;
end
RMV_GOHST: begin
write_en = 1;
TabAdd = pospac-2;
TabDat = 0;
end
UPDT_PACMAN: begin
write_en = 1;
TabAdd = pospac-1;
if (close==0)
TabDat = 3;
else
TabDat = 2;
end
UPDT_GOHST: begin
write_en = 1;
TabAdd = pospac-3;
TabDat = 1;
end
WAIT_0: begin write_en = 0; end
default: begin
write_en = 0;
end
endcase
end
endmodule | module PxsGameUpdate (
input wire px_clk,
input wire rst,
input wire [25:0] RGBStr_i,
output reg write_en,
output reg [10:0] TabAdd,
output reg [3:0] TabDat
); |
`define Active 0:0
`define VS 1:1
`define HS 2:2
`define YC 12:3
`define XC 22:13
`define RGB 25:23
parameter VISIBLECOLS=640;
parameter VISIBLEROWS=480;
parameter WAIT = 6'b000001,
RMV_PAC = 6'b000010,
RMV_GOHST = 6'b000100,
UPDT_PACMAN = 6'b001000,
UPDT_GOHST = 6'b010000,
WAIT_0 = 6'b100000;
reg [5:0]state, next_state;
reg [4:0] contframe;
reg [10:0] pospac;
reg close;
initial
begin
contframe <= 0;
pospac<=600;
state <= WAIT;
write_en<=0;
close<=0;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
always @(posedge px_clk)
begin
if (rst)
contframe<=0;
else
if (endframe==1)
contframe <= (contframe == 25)? 0 : contframe+1;
end
always @(posedge contframe[4])
begin
pospac<=pospac-1;
close <= ~close;
end
always @(posedge px_clk)
if (rst) state = WAIT; else state = next_state;
always @(*) begin
next_state = state;
case (state)
WAIT: if (contframe==25) next_state = RMV_PAC;
else next_state = WAIT;
RMV_PAC: next_state = RMV_GOHST;
RMV_GOHST: next_state = UPDT_PACMAN;
UPDT_PACMAN: next_state = UPDT_GOHST;
UPDT_GOHST: next_state = WAIT_0;
WAIT_0: if(contframe==0) next_state = WAIT;
else next_state<= WAIT_0;
endcase
end
always @(state) begin
case (state)
WAIT: begin
write_en = 0;
end
RMV_PAC: begin
write_en = 1;
TabAdd = pospac;
TabDat = 0;
end
RMV_GOHST: begin
write_en = 1;
TabAdd = pospac-2;
TabDat = 0;
end
UPDT_PACMAN: begin
write_en = 1;
TabAdd = pospac-1;
if (close==0)
TabDat = 3;
else
TabDat = 2;
end
UPDT_GOHST: begin
write_en = 1;
TabAdd = pospac-3;
TabDat = 1;
end
WAIT_0: begin write_en = 0; end
default: begin
write_en = 0;
end
endcase
end
endmodule | 47 |
4,298 | data/full_repos/permissive/109394014/examples/PxsMoveLogo.v | 109,394,014 | PxsMoveLogo.v | v | 174 | 97 | [] | ['gpl license'] | [] | [(80, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:25: Cannot find include file: Pxs.vh\n`include "Pxs.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.v\n data/full_repos/permissive/109394014/examples,data/full_repos/permissive/109394014/Pxs.vh.sv\n Pxs.vh\n Pxs.vh.v\n Pxs.vh.sv\n obj_dir/Pxs.vh\n obj_dir/Pxs.vh.v\n obj_dir/Pxs.vh.sv\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:96: Define or directive not defined: \'`XC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:96: Define or directive not defined: \'`YC\'\n assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1\'b1 : 1\'b0 ;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:107: Define or directive not defined: \'`XC\'\n x_img <= RGBStr_i[`XC]-x_logo;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:107: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n x_img <= RGBStr_i[`XC]-x_logo;\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:108: Define or directive not defined: \'`YC\'\n y_img <= RGBStr_i[`YC]-y_logo;\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n y_img <= RGBStr_i[`YC]-y_logo;\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: Define or directive not defined: \'`HS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:109: Define or directive not defined: \'`VS\'\n AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: Define or directive not defined: \'`XC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:110: Define or directive not defined: \'`YC\'\n AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:111: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:111: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:111: Define or directive not defined: \'`Active\'\n AuxStr1[`Active]<=RGBStr_i[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:112: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:112: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:112: Define or directive not defined: \'`RGB\'\n AuxStr1[`RGB]<=RGBStr_i[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: Define or directive not defined: \'`HS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:120: Define or directive not defined: \'`VS\'\n AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: Define or directive not defined: \'`XC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:121: Define or directive not defined: \'`YC\'\n AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:122: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:122: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:122: Define or directive not defined: \'`Active\'\n AuxStr2[`Active]<=AuxStr1[`Active];\n ^~~~~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:123: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:123: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:123: Define or directive not defined: \'`RGB\'\n AuxStr2[`RGB]<=AuxStr1[`RGB];\n ^~~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: Define or directive not defined: \'`HS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^\n%Error: data/full_repos/permissive/109394014/examples/PxsMoveLogo.v:131: Define or directive not defined: \'`VS\'\n RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,523 | module | module PxsMoveLogo (
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
);
parameter FILE_LOGO = "logofpga.list";
parameter ALFA = 1'b0;
parameter width_logo = 96;
parameter height_logo = 80;
localparam Awidth = $clog2(width_logo*height_logo);
reg [0:0] logo [width_logo*height_logo-1:0];
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = white;
parameter background = white;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
parameter border = 240;
parameter [9:0] x_logo_min = border;
parameter [9:0] y_logo_min = border;
parameter [9:0] x_logo_max = VISIBLECOLS - width_logo - border;
parameter [9:0] y_logo_max = VISIBLEROWS - height_logo - border;
wire [Awidth-1:0] addr, addr2x;
reg [4:0] SPEED;
reg dx,dy;
wire endframe;
reg [9:0] x_logo, y_logo;
reg [9:0] x_img, y_img;
reg [25:0] AuxStr1, AuxStr2;
reg InLogo;
reg pixel;
reg [6:0] counter;
initial
begin
if (FILE_LOGO) $readmemb(FILE_LOGO, logo);
x_logo <=10;
y_logo <=(VISIBLEROWS - height_logo)/4;
dx <=0;
dy <=1;
SPEED <= 1;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
assign addr=y_img*width_logo+x_img;
always @(posedge px_clk)
begin
x_img <= RGBStr_i[`XC]-x_logo;
y_img <= RGBStr_i[`YC]-y_logo;
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
InLogo<= (x_img >= 0 && x_img < width_logo) && (y_img >= 0 && y_img < height_logo);
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
AuxStr2[`RGB]<=AuxStr1[`RGB];
pixel <= logo [addr];
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if(InLogo)
RGBStr_o[`RGB]<= pixel? ink: (ALFA? AuxStr2[`RGB]:background);
else
RGBStr_o[`RGB]<=AuxStr2[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
counter <= counter+1;
if (counter[0]==1)
begin
if (y_logo>=200 || y_logo<80)
dy = ~ dy;
if (dx==0)
x_logo = x_logo+2;
else
x_logo = x_logo-SPEED;
if (dy==0)
y_logo = y_logo+SPEED;
else
y_logo = y_logo-SPEED;
end
end
end
endmodule | module PxsMoveLogo (
input wire px_clk,
input wire [25:0] RGBStr_i,
output reg [25:0] RGBStr_o
); |
parameter FILE_LOGO = "logofpga.list";
parameter ALFA = 1'b0;
parameter width_logo = 96;
parameter height_logo = 80;
localparam Awidth = $clog2(width_logo*height_logo);
reg [0:0] logo [width_logo*height_logo-1:0];
parameter [2:0] black = 3'b000;
parameter [2:0] blue = 3'b001;
parameter [2:0] green = 3'b010;
parameter [2:0] white = 3'b111;
parameter [2:0] pink = 3'b101;
parameter ink = white;
parameter background = white;
parameter [9:0] VISIBLECOLS = 640;
parameter [9:0] VISIBLEROWS = 480;
parameter border = 240;
parameter [9:0] x_logo_min = border;
parameter [9:0] y_logo_min = border;
parameter [9:0] x_logo_max = VISIBLECOLS - width_logo - border;
parameter [9:0] y_logo_max = VISIBLEROWS - height_logo - border;
wire [Awidth-1:0] addr, addr2x;
reg [4:0] SPEED;
reg dx,dy;
wire endframe;
reg [9:0] x_logo, y_logo;
reg [9:0] x_img, y_img;
reg [25:0] AuxStr1, AuxStr2;
reg InLogo;
reg pixel;
reg [6:0] counter;
initial
begin
if (FILE_LOGO) $readmemb(FILE_LOGO, logo);
x_logo <=10;
y_logo <=(VISIBLEROWS - height_logo)/4;
dx <=0;
dy <=1;
SPEED <= 1;
end
assign endframe = (RGBStr_i[`XC]==VISIBLECOLS-1 && RGBStr_i[`YC]==VISIBLEROWS-1)? 1'b1 : 1'b0 ;
assign addr=y_img*width_logo+x_img;
always @(posedge px_clk)
begin
x_img <= RGBStr_i[`XC]-x_logo;
y_img <= RGBStr_i[`YC]-y_logo;
AuxStr1[`HS]<=RGBStr_i[`HS]; AuxStr1[`VS]<=RGBStr_i[`VS];
AuxStr1[`XC]<=RGBStr_i[`XC]; AuxStr1[`YC]<=RGBStr_i[`YC];
AuxStr1[`Active]<=RGBStr_i[`Active];
AuxStr1[`RGB]<=RGBStr_i[`RGB];
end
always @(posedge px_clk)
begin
InLogo<= (x_img >= 0 && x_img < width_logo) && (y_img >= 0 && y_img < height_logo);
AuxStr2[`HS]<=AuxStr1[`HS]; AuxStr2[`VS]<=AuxStr1[`VS];
AuxStr2[`XC]<=AuxStr1[`XC]; AuxStr2[`YC]<=AuxStr1[`YC];
AuxStr2[`Active]<=AuxStr1[`Active];
AuxStr2[`RGB]<=AuxStr1[`RGB];
pixel <= logo [addr];
end
always @(posedge px_clk)
begin
RGBStr_o[`HS]<=AuxStr2[`HS]; RGBStr_o[`VS]<=AuxStr2[`VS];
RGBStr_o[`XC]<=AuxStr2[`XC]; RGBStr_o[`YC]<=AuxStr2[`YC];
RGBStr_o[`Active]<=AuxStr2[`Active];
if(InLogo)
RGBStr_o[`RGB]<= pixel? ink: (ALFA? AuxStr2[`RGB]:background);
else
RGBStr_o[`RGB]<=AuxStr2[`RGB];
end
always @(posedge px_clk)
begin
if (endframe)
begin
counter <= counter+1;
if (counter[0]==1)
begin
if (y_logo>=200 || y_logo<80)
dy = ~ dy;
if (dx==0)
x_logo = x_logo+2;
else
x_logo = x_logo-SPEED;
if (dy==0)
y_logo = y_logo+SPEED;
else
y_logo = y_logo-SPEED;
end
end
end
endmodule | 47 |
4,302 | data/full_repos/permissive/109400221/hdl/nand/ACounter.v | 109,400,221 | ACounter.v | v | 100 | 83 | [] | [] | [] | [(51, 99)] | null | data/verilator_xmls/1754c78f-9cb2-43df-8ed6-22ba872f3e0d.xml | null | 2,536 | module | module ACounter(
clk,
Res,
Set835,
CntEn ,
CntOut,
TC2048,
TC3
);
input clk;
input Res;
input Set835;
input CntEn;
output [11:0] CntOut;
output reg TC2048;
output reg TC3;
reg [11:0] cnt_state;
always@(posedge clk)
if (Res)
cnt_state <= 0;
else if (Set835)
cnt_state <=12'h835;
else if (CntEn)
cnt_state <= cnt_state + 1;
always@(cnt_state)
if (cnt_state== 12'h7FF) begin
TC2048 <= 1;
TC3 <=0;
end else if (cnt_state[7:0] == 8'h40) begin
TC3 <= 1;
TC2048 <= 0;
end
else begin
TC3 <=0;
TC2048 <= 0;
end
assign CntOut = cnt_state;
endmodule | module ACounter(
clk,
Res,
Set835,
CntEn ,
CntOut,
TC2048,
TC3
); |
input clk;
input Res;
input Set835;
input CntEn;
output [11:0] CntOut;
output reg TC2048;
output reg TC3;
reg [11:0] cnt_state;
always@(posedge clk)
if (Res)
cnt_state <= 0;
else if (Set835)
cnt_state <=12'h835;
else if (CntEn)
cnt_state <= cnt_state + 1;
always@(cnt_state)
if (cnt_state== 12'h7FF) begin
TC2048 <= 1;
TC3 <=0;
end else if (cnt_state[7:0] == 8'h40) begin
TC3 <= 1;
TC2048 <= 0;
end
else begin
TC3 <=0;
TC2048 <= 0;
end
assign CntOut = cnt_state;
endmodule | 1 |
4,303 | data/full_repos/permissive/109400221/hdl/nand/ErrLoc.v | 109,400,221 | ErrLoc.v | v | 88 | 83 | [] | [] | [] | [(51, 87)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109400221/hdl/nand/ErrLoc.v:72: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance ErrLoc\n din <= 8\'h00;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,538 | module | module ErrLoc(
clk,
Res,
F_ecc_data ,
WrECC,
error_bv,
ECC_status
);
input clk;
input Res;
input [6:0] F_ecc_data ;
input WrECC ;
input error_bv;
output reg ECC_status;
wire check1,check2,check3;
reg [6:0] din;
always@(posedge clk)
if (Res)
din <= 8'h00;
else if (WrECC)
din <= F_ecc_data;
assign check1=din[6]^din[4]^din[2]^din[0];
assign check2=din[5]^din[4]^din[1]^din[0];
assign check3=din[3]^din[2]^din[1]^din[0];
always@(posedge clk)
if (Res)
ECC_status <= 1'h0;
else
ECC_status <= (check1 | check2 | check3 | error_bv);
endmodule | module ErrLoc(
clk,
Res,
F_ecc_data ,
WrECC,
error_bv,
ECC_status
); |
input clk;
input Res;
input [6:0] F_ecc_data ;
input WrECC ;
input error_bv;
output reg ECC_status;
wire check1,check2,check3;
reg [6:0] din;
always@(posedge clk)
if (Res)
din <= 8'h00;
else if (WrECC)
din <= F_ecc_data;
assign check1=din[6]^din[4]^din[2]^din[0];
assign check2=din[5]^din[4]^din[1]^din[0];
assign check3=din[3]^din[2]^din[1]^din[0];
always@(posedge clk)
if (Res)
ECC_status <= 1'h0;
else
ECC_status <= (check1 | check2 | check3 | error_bv);
endmodule | 1 |
4,305 | data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv | 109,400,221 | nfcm_top.sv | sv | 316 | 71 | [] | [] | [] | null | line:17: before: ";" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:18: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'nfcm_top\'\nmodule nfcm_top(\n ^~~~~~~~\n : ... Top module \'buffer_interface\'\nbuffer_interface.reader buff;\n^~~~~~~~~~~~~~~~\n : ... Top module \'flash_cmd_interface\'\nflash_cmd_interface.slave fc;\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:18: Unsupported: Interfaced port on top level module\nbuffer_interface.reader buff;\n ^~~~\n%Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:19: Unsupported: Interfaced port on top level module\nflash_cmd_interface.slave fc;\n ^~\n%Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:8: Input/output/inout declaration not found for port: \'fi\'\n fi,\n ^~\n%Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:18: Cannot find file containing interface: \'buffer_interface\'\nbuffer_interface.reader buff;\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:19: Cannot find file containing interface: \'flash_cmd_interface\'\nflash_cmd_interface.slave fc;\n^~~~~~~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/109400221/hdl/nand/nfcm_top.sv:18: ../V3LinkDot.cpp:2055: Unlinked interface\nbuffer_interface.reader buff;\n^~~~~~~~~~~~~~~~\n' | 2,545 | module | module nfcm_top(
fi,
buff,
PErr,
EErr,
RErr,
error_bv,
fc
);
flash_interface fi;
buffer_interface.reader buff;
flash_cmd_interface.slave fc;
output reg PErr ;
output reg EErr ;
output reg RErr ;
input error_bv ;
parameter HI= 1'b1;
parameter LO= 1'b0;
reg ires, res_t;
wire [7:0] FlashDataIn;
reg [7:0] FlashCmd;
reg [7:0] FlashDataOu;
wire [1:0] adc_sel;
wire [7:0] QA_1,QB_1;
wire [7:0] BF_data2flash, ECC_data;
wire Flash_BF_sel, Flash_BF_we, DIS, F_we;
wire rar_we;
reg [7:0] addr_data;
reg [7:0] rad_1;
reg [7:0] rad_2;
wire [7:0] cad_1;
wire [7:0] cad_2;
wire [1:0] amx_sel;
wire CntEn, tc3, tc2048, cnt_res, acnt_res;
wire [11:0] CntOut;
reg DOS;
wire t_start, t_done;
wire [2:0] t_cmd;
wire WCountRes, WCountCE;
reg TC4, TC8;
wire cmd_we ;
wire [7:0] cmd_reg;
wire SetPrErr, SetErErr,SetRrErr;
wire WrECC, WrECC_e, enEcc, Ecc_en,ecc_en_tfsm;
wire setDone, set835;
wire DOS_i;
reg [7:0] FlashDataOu_i ;
assign buff.BF_dou = QA_1;
assign BF_data2flash = QB_1;
assign cad_1 = CntOut[7:0];
assign cad_2 = {4'b0000,CntOut[11:8]};
assign acnt_res = (ires | cnt_res);
assign WrECC_e = WrECC & DIS;
assign Flash_BF_we = DIS & F_we;
assign Ecc_en = enEcc & ecc_en_tfsm;
ACounter addr_counter (
.clk(fc.clk),
.Res(acnt_res),
.Set835(set835),
.CntEn(CntEn),
.CntOut(CntOut),
.TC2048(tc2048),
.TC3(tc3)
);
TFSM tim_fsm(
.CLE(fi.CLE),
.ALE (fi.ALE),
.WE_n(fi.WE_n),
.RE_n(fi.RE_n),
.CE_n(fi.CE_n),
.DOS (DOS_i),
.DIS (DIS),
.cnt_en(CntEn),
.TC3(tc3),
.TC2048(tc2048),
.CLK(fc.clk),
.RES(ires),
.start(t_start),
.cmd_code(t_cmd),
.ecc_en(ecc_en_tfsm),
.Done(t_done)
);
MFSM main_fsm
(
.CLK ( fc.clk ),
.RES ( ires ),
.start ( fc.start),
.command(fc.cmd),
.setDone(setDone),
.R_nB (fi.R_nB),
.BF_sel( buff.BF_sel),
.mBF_sel ( Flash_BF_sel),
.BF_we( F_we),
.io_0( FlashDataIn[0]),
.t_start ( t_start),
.t_cmd ( t_cmd),
.t_done ( t_done),
.WrECC ( WrECC),
.EnEcc ( enEcc),
.AMX_sel ( amx_sel),
.cmd_reg ( cmd_reg),
.cmd_reg_we( cmd_we),
.RAR_we ( rar_we),
.set835 ( set835),
.cnt_res ( cnt_res),
.tc8 ( TC8),
.tc4 ( TC4),
.wCntRes( WCountRes),
.wCntCE ( WCountCE),
.SetPrErr ( SetPrErr),
.SetErErr ( SetErErr),
.ADC_sel ( adc_sel)
);
H_gen ecc_gen(
. clk( fc.clk),
. Res( acnt_res),
. Din( BF_data2flash[3:0]),
. EN (Ecc_en),
. eccByte ( ECC_data)
);
ErrLoc ecc_err_loc
(
.clk( fc.clk),
.Res (acnt_res),
.F_ecc_data (FlashDataIn[6:0]),
.WrECC (WrECC_e),
.error_bv (error_bv),
.ECC_status (SetRrErr)
);
always@(posedge fc.clk)
begin
res_t <= fi.rst;
ires <= res_t;
end
always@(posedge fc.clk)
if (rar_we) begin
rad_1=fc.RWA[7:0];
rad_2=fc.RWA[15:8];
end
always@(posedge fc.clk)
begin
FlashDataOu <= FlashDataOu_i;
DOS <= DOS_i;
end
always@(cad_1 or cad_2 or rad_1 or rad_2 or amx_sel)
begin
case (amx_sel)
2'b11 : addr_data <= rad_2;
2'b10 : addr_data <= rad_1;
2'b01 : addr_data <= cad_2;
default: addr_data <= cad_1;
endcase
end
always@(adc_sel or BF_data2flash or FlashCmd or addr_data or ECC_data)
begin
case (adc_sel)
2'b11 : FlashDataOu_i <= FlashCmd;
2'b10 : FlashDataOu_i <= addr_data;
2'b01 : FlashDataOu_i <= ECC_data;
default: FlashDataOu_i <= BF_data2flash;
endcase
end
reg [3:0] WC_tmp;
always@(posedge fc.clk)
begin
if ((ires ==1'b1) | (WCountRes ==1'b1))
WC_tmp<= 4'b0000;
else if (WCountCE ==1'b1)
WC_tmp<= WC_tmp + 1;
if (WC_tmp ==4'b0100) begin
TC4 <= 1'b1;
TC8 <= 1'b0;
end else if (WC_tmp ==4'b1000) begin
TC8<= 1'b1;
TC4 <=1'b0;
end else begin
TC4 <=1'b0;
TC8 <=1'b0;
end
end
always@(posedge fc.clk)
begin
if (ires)
FlashCmd <=8'b00000000;
else if (cmd_we)
FlashCmd <= cmd_reg;
end
always@(posedge fc.clk)
begin
if (ires)
fc.done <= 1'b0;
else if (setDone)
fc.done <=1'b1;
else if (fc.start)
fc.done <=1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
PErr <=1'b0;
else if (SetPrErr)
PErr <= 1'b1;
else if (fc.start)
PErr <= 1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
EErr <=1'b0;
else if (SetErErr)
EErr <=1'b1;
else if (fc.start)
EErr <= 1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
RErr <=1'b0;
else if (SetRrErr)
RErr <= 1'b1;
else if (fc.start)
RErr <= 1'b0;
end
assign FlashDataIn = fi.DIO;
assign fi.DIO =(DOS == 1'b1)?FlashDataOu:8'hzz;
endmodule | module nfcm_top(
fi,
buff,
PErr,
EErr,
RErr,
error_bv,
fc
); |
flash_interface fi;
buffer_interface.reader buff;
flash_cmd_interface.slave fc;
output reg PErr ;
output reg EErr ;
output reg RErr ;
input error_bv ;
parameter HI= 1'b1;
parameter LO= 1'b0;
reg ires, res_t;
wire [7:0] FlashDataIn;
reg [7:0] FlashCmd;
reg [7:0] FlashDataOu;
wire [1:0] adc_sel;
wire [7:0] QA_1,QB_1;
wire [7:0] BF_data2flash, ECC_data;
wire Flash_BF_sel, Flash_BF_we, DIS, F_we;
wire rar_we;
reg [7:0] addr_data;
reg [7:0] rad_1;
reg [7:0] rad_2;
wire [7:0] cad_1;
wire [7:0] cad_2;
wire [1:0] amx_sel;
wire CntEn, tc3, tc2048, cnt_res, acnt_res;
wire [11:0] CntOut;
reg DOS;
wire t_start, t_done;
wire [2:0] t_cmd;
wire WCountRes, WCountCE;
reg TC4, TC8;
wire cmd_we ;
wire [7:0] cmd_reg;
wire SetPrErr, SetErErr,SetRrErr;
wire WrECC, WrECC_e, enEcc, Ecc_en,ecc_en_tfsm;
wire setDone, set835;
wire DOS_i;
reg [7:0] FlashDataOu_i ;
assign buff.BF_dou = QA_1;
assign BF_data2flash = QB_1;
assign cad_1 = CntOut[7:0];
assign cad_2 = {4'b0000,CntOut[11:8]};
assign acnt_res = (ires | cnt_res);
assign WrECC_e = WrECC & DIS;
assign Flash_BF_we = DIS & F_we;
assign Ecc_en = enEcc & ecc_en_tfsm;
ACounter addr_counter (
.clk(fc.clk),
.Res(acnt_res),
.Set835(set835),
.CntEn(CntEn),
.CntOut(CntOut),
.TC2048(tc2048),
.TC3(tc3)
);
TFSM tim_fsm(
.CLE(fi.CLE),
.ALE (fi.ALE),
.WE_n(fi.WE_n),
.RE_n(fi.RE_n),
.CE_n(fi.CE_n),
.DOS (DOS_i),
.DIS (DIS),
.cnt_en(CntEn),
.TC3(tc3),
.TC2048(tc2048),
.CLK(fc.clk),
.RES(ires),
.start(t_start),
.cmd_code(t_cmd),
.ecc_en(ecc_en_tfsm),
.Done(t_done)
);
MFSM main_fsm
(
.CLK ( fc.clk ),
.RES ( ires ),
.start ( fc.start),
.command(fc.cmd),
.setDone(setDone),
.R_nB (fi.R_nB),
.BF_sel( buff.BF_sel),
.mBF_sel ( Flash_BF_sel),
.BF_we( F_we),
.io_0( FlashDataIn[0]),
.t_start ( t_start),
.t_cmd ( t_cmd),
.t_done ( t_done),
.WrECC ( WrECC),
.EnEcc ( enEcc),
.AMX_sel ( amx_sel),
.cmd_reg ( cmd_reg),
.cmd_reg_we( cmd_we),
.RAR_we ( rar_we),
.set835 ( set835),
.cnt_res ( cnt_res),
.tc8 ( TC8),
.tc4 ( TC4),
.wCntRes( WCountRes),
.wCntCE ( WCountCE),
.SetPrErr ( SetPrErr),
.SetErErr ( SetErErr),
.ADC_sel ( adc_sel)
);
H_gen ecc_gen(
. clk( fc.clk),
. Res( acnt_res),
. Din( BF_data2flash[3:0]),
. EN (Ecc_en),
. eccByte ( ECC_data)
);
ErrLoc ecc_err_loc
(
.clk( fc.clk),
.Res (acnt_res),
.F_ecc_data (FlashDataIn[6:0]),
.WrECC (WrECC_e),
.error_bv (error_bv),
.ECC_status (SetRrErr)
);
always@(posedge fc.clk)
begin
res_t <= fi.rst;
ires <= res_t;
end
always@(posedge fc.clk)
if (rar_we) begin
rad_1=fc.RWA[7:0];
rad_2=fc.RWA[15:8];
end
always@(posedge fc.clk)
begin
FlashDataOu <= FlashDataOu_i;
DOS <= DOS_i;
end
always@(cad_1 or cad_2 or rad_1 or rad_2 or amx_sel)
begin
case (amx_sel)
2'b11 : addr_data <= rad_2;
2'b10 : addr_data <= rad_1;
2'b01 : addr_data <= cad_2;
default: addr_data <= cad_1;
endcase
end
always@(adc_sel or BF_data2flash or FlashCmd or addr_data or ECC_data)
begin
case (adc_sel)
2'b11 : FlashDataOu_i <= FlashCmd;
2'b10 : FlashDataOu_i <= addr_data;
2'b01 : FlashDataOu_i <= ECC_data;
default: FlashDataOu_i <= BF_data2flash;
endcase
end
reg [3:0] WC_tmp;
always@(posedge fc.clk)
begin
if ((ires ==1'b1) | (WCountRes ==1'b1))
WC_tmp<= 4'b0000;
else if (WCountCE ==1'b1)
WC_tmp<= WC_tmp + 1;
if (WC_tmp ==4'b0100) begin
TC4 <= 1'b1;
TC8 <= 1'b0;
end else if (WC_tmp ==4'b1000) begin
TC8<= 1'b1;
TC4 <=1'b0;
end else begin
TC4 <=1'b0;
TC8 <=1'b0;
end
end
always@(posedge fc.clk)
begin
if (ires)
FlashCmd <=8'b00000000;
else if (cmd_we)
FlashCmd <= cmd_reg;
end
always@(posedge fc.clk)
begin
if (ires)
fc.done <= 1'b0;
else if (setDone)
fc.done <=1'b1;
else if (fc.start)
fc.done <=1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
PErr <=1'b0;
else if (SetPrErr)
PErr <= 1'b1;
else if (fc.start)
PErr <= 1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
EErr <=1'b0;
else if (SetErErr)
EErr <=1'b1;
else if (fc.start)
EErr <= 1'b0;
end
always@(posedge fc.clk)
begin
if (ires)
RErr <=1'b0;
else if (SetRrErr)
RErr <= 1'b1;
else if (fc.start)
RErr <= 1'b0;
end
assign FlashDataIn = fi.DIO;
assign fi.DIO =(DOS == 1'b1)?FlashDataOu:8'hzz;
endmodule | 1 |
4,310 | data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv | 109,400,221 | spi_protocoltb.sv | sv | 175 | 161 | [] | [] | [] | null | line:8: before: "package" | null | 1: b'%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:9: Unsupported: classes\nclass Packet;\n^~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:13: Unsupported: \'static\' class item\nstatic int count = 0; \n^~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint c {\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:16: syntax error, unexpected IDENTIFIER\nconstraint c {\n ^\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint d {SS < 10;}\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint e {NUMSLAVES < 32 ;}\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:58: syntax error, unexpected genvar\ngenvar i;\n^~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:96: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\nassert (p.randomize(D)) $display("randomization successful"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:166: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 2,552 | module | module SPItb #(
parameter data_width = 8,
parameter NUMSLAVES = 12,
parameter clkwidth = 100,
parameter SS = 10);
typedef logic [data_width-1:0] DTYPE;
import Randomize::*;
logic mainclk,reset;
DTYPE D;
DTYPE temp,j;
int S,passed,failed,total_tests;
int index;
bit Request;
bit Done;
genvar i;
SPIBus #(.DTYPE(DTYPE),.NUMSLAVES(NUMSLAVES)) SPI();
generate
for(i = 1'b0; i < NUMSLAVES; i=i+1'b1)
begin : loop
SPISlave #(.DTYPE(DTYPE),.ID(i)) Slave(SPI);
end : loop
endgenerate
SPIMaster #(.DTYPE(DTYPE),.clkwidth(clkwidth)) M1(SPI,D,S,Request,Done,mainclk,reset);
always @ (D)begin
temp = D;
$display("D=%d",temp);
end
always #clkwidth mainclk=~mainclk;
initial begin
Packet p;
p = new();
p.data_width = data_width;
reset = 1'b0;
mainclk=1'b0;
$display("In initial block. packetCount=%d",p.count);
passed=0;
failed=0;
total_tests=0;
for(int j=0; j<10; j=j+1) begin
$display("INSIDE J LOOP");
#200 Request = 0;
#100 Request = 1;
S = SS;
assert (p.randomize(D)) $display("randomization successful");
else $fatal(0, "Packet::randomize failed");
D = p.D;
wait(Done);
$display("clk=%b, MR = %b, SR %d = %b, Done=%b",SPI.SCLK,D,SS,SPItb.loop[SS].Slave.SR,Done);
if(((SPItb.loop[SS].Slave.SR) === temp)) begin
$display("TEST PASSED");
passed=passed+1;
end
else begin
$display("TEST FAILED");
failed=failed+1;
end
end
for(int z=0;z<6;z=z+1) begin
$display("INSIDE Z LOOP");
#200 Request = 0;
#100 Request = 1;
S = SS;
if(z==0) D = '0;
else if(z==1) D = '1;
else if(z==2) D = 'x;
else if(z==3) D = {(data_width/2){2'b10}};
else if(z==4) D = {(data_width/2){2'b01}};
else D = 'z;
wait(Done);
$display("clk=%b, MR = %b, SR %d = %b, Done=%b",SPI.SCLK,D,SS,SPItb.loop[SS].Slave.SR,Done);
if(((SPItb.loop[SS].Slave.SR) === temp))begin
$display("TEST PASSED");
passed=passed+1;
end
else begin
$display("TEST FAILED");
failed=failed+1;
end
end
$stop;
end
always@(M1.MR,Done,Request,SPI.SCLK,mainclk,SPItb.loop[SS].Slave.SR,reset)
$display($time," mainclk=%b, reset=%b, spi.sclk=%b, Request=%b, MR=%b, Done=%b, SR=%b",mainclk,reset,SPI.SCLK,Request,M1.MR,Done, SPItb.loop[SS].Slave.SR);
final begin
$display("NUMSLAVES=%d, datawidth=%d, SS=%d",NUMSLAVES,data_width,SS);
$display("total tests=%d, passed=%d, failed=%d",passed+failed,passed,failed);
if(failed==0) $display("TEST PASSED ! ! !");
else $display("TEST FAILED ! ! !");
end
endmodule | module SPItb #(
parameter data_width = 8,
parameter NUMSLAVES = 12,
parameter clkwidth = 100,
parameter SS = 10); |
typedef logic [data_width-1:0] DTYPE;
import Randomize::*;
logic mainclk,reset;
DTYPE D;
DTYPE temp,j;
int S,passed,failed,total_tests;
int index;
bit Request;
bit Done;
genvar i;
SPIBus #(.DTYPE(DTYPE),.NUMSLAVES(NUMSLAVES)) SPI();
generate
for(i = 1'b0; i < NUMSLAVES; i=i+1'b1)
begin : loop
SPISlave #(.DTYPE(DTYPE),.ID(i)) Slave(SPI);
end : loop
endgenerate
SPIMaster #(.DTYPE(DTYPE),.clkwidth(clkwidth)) M1(SPI,D,S,Request,Done,mainclk,reset);
always @ (D)begin
temp = D;
$display("D=%d",temp);
end
always #clkwidth mainclk=~mainclk;
initial begin
Packet p;
p = new();
p.data_width = data_width;
reset = 1'b0;
mainclk=1'b0;
$display("In initial block. packetCount=%d",p.count);
passed=0;
failed=0;
total_tests=0;
for(int j=0; j<10; j=j+1) begin
$display("INSIDE J LOOP");
#200 Request = 0;
#100 Request = 1;
S = SS;
assert (p.randomize(D)) $display("randomization successful");
else $fatal(0, "Packet::randomize failed");
D = p.D;
wait(Done);
$display("clk=%b, MR = %b, SR %d = %b, Done=%b",SPI.SCLK,D,SS,SPItb.loop[SS].Slave.SR,Done);
if(((SPItb.loop[SS].Slave.SR) === temp)) begin
$display("TEST PASSED");
passed=passed+1;
end
else begin
$display("TEST FAILED");
failed=failed+1;
end
end
for(int z=0;z<6;z=z+1) begin
$display("INSIDE Z LOOP");
#200 Request = 0;
#100 Request = 1;
S = SS;
if(z==0) D = '0;
else if(z==1) D = '1;
else if(z==2) D = 'x;
else if(z==3) D = {(data_width/2){2'b10}};
else if(z==4) D = {(data_width/2){2'b01}};
else D = 'z;
wait(Done);
$display("clk=%b, MR = %b, SR %d = %b, Done=%b",SPI.SCLK,D,SS,SPItb.loop[SS].Slave.SR,Done);
if(((SPItb.loop[SS].Slave.SR) === temp))begin
$display("TEST PASSED");
passed=passed+1;
end
else begin
$display("TEST FAILED");
failed=failed+1;
end
end
$stop;
end
always@(M1.MR,Done,Request,SPI.SCLK,mainclk,SPItb.loop[SS].Slave.SR,reset)
$display($time," mainclk=%b, reset=%b, spi.sclk=%b, Request=%b, MR=%b, Done=%b, SR=%b",mainclk,reset,SPI.SCLK,Request,M1.MR,Done, SPItb.loop[SS].Slave.SR);
final begin
$display("NUMSLAVES=%d, datawidth=%d, SS=%d",NUMSLAVES,data_width,SS);
$display("total tests=%d, passed=%d, failed=%d",passed+failed,passed,failed);
if(failed==0) $display("TEST PASSED ! ! !");
else $display("TEST FAILED ! ! !");
end
endmodule | 1 |
4,311 | data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv | 109,400,221 | spi_protocoltb.sv | sv | 175 | 161 | [] | [] | [] | null | line:8: before: "package" | null | 1: b'%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:9: Unsupported: classes\nclass Packet;\n^~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:13: Unsupported: \'static\' class item\nstatic int count = 0; \n^~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint c {\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:16: syntax error, unexpected IDENTIFIER\nconstraint c {\n ^\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint d {SS < 10;}\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\nconstraint e {NUMSLAVES < 32 ;}\n^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:58: syntax error, unexpected genvar\ngenvar i;\n^~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:96: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\nassert (p.randomize(D)) $display("randomization successful"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/109400221/hdl/spi/spi_protocoltb.sv:166: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 2,552 | module | module upTop;
import Randomize::*;
initial begin
Packet packet;
packet=new();
end
SPItb #(.data_width(16),.NUMSLAVES(10),.SS(2)) SPI_protocol();
endmodule | module upTop; |
import Randomize::*;
initial begin
Packet packet;
packet=new();
end
SPItb #(.data_width(16),.NUMSLAVES(10),.SS(2)) SPI_protocol();
endmodule | 1 |
4,328 | data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/MFSM.v | 109,400,221 | MFSM.v | v | 843 | 105 | [] | [] | [] | [(51, 842)] | null | data/verilator_xmls/53c7cad1-60ee-40a8-9791-cd40080184ac.xml | null | 2,559 | module | module MFSM(
CLK,
RES,
start,
command,
setDone,
R_nB,
BF_sel,
mBF_sel,
BF_we,
io_0,
t_start,
t_cmd,
t_done,
WrECC,
EnEcc,
AMX_sel,
cmd_reg,
cmd_reg_we,
RAR_we,
set835,
cnt_res,
tc8,
tc4,
wCntRes,
wCntCE,
SetPrErr,
SetErErr,
ADC_sel
);
input CLK;
input RES;
input start;
input [2:0] command;
input R_nB;
input BF_sel;
input io_0;
input t_done;
input tc8;
input tc4;
output reg setDone;
output mBF_sel;
output reg BF_we;
output reg t_start;
output reg [2:0] t_cmd;
output reg WrECC;
output reg EnEcc;
output reg [1:0] AMX_sel;
output reg [7:0] cmd_reg;
output reg cmd_reg_we;
output reg RAR_we;
output reg set835;
output reg cnt_res;
output reg wCntRes;
output reg wCntCE;
output reg SetPrErr;
output reg SetErErr;
output reg [1:0] ADC_sel;
parameter Init=0,S_ADS=1, S_RAR=2,
S_CmdL0=3,S_CmdL1=4,S_adL0=5,S_adL1=6, S_CmdL2=7, S_CmdL3=8,
S_WC0=9, S_WC1=10, S_wait=11, S_CmdL4=12, S_CmdL5=13, S_WC3=14, S_WC4=15, S_DR1=16, S_Done=17,
Sr_RAR=18, Sr_DnErr=19, Sr_CmdL0=20, Sr_CmdL1=21, Sr_AdL0=22, Sr_AdL1=23, Sr_AdL2=24,
Sr_AdL3=25, Sr_CmdL2=26, Sr_CmdL3=27, Sr_WC0=28, Sr_WC1=29, Sr_wait=30, Sr_RPA0=31,
Sr_CmdL4=32, Sr_CmdL5=33, Sr_AdL4=34, Sr_AdL5=35, Sr_CmdL6=36, Sr_CmdL7=37, Sr_WC2=38,Sr_RPA1=39,
Sr_wait1=40, Sr_wait2=41, Sr_WC3=42, Sr_Done=43,
Sw_RAR=44, Sw_CmdL0=45, Sw_CmdL1=46, Sw_AdL0=47, Sw_AdL1=48, Sw_AdL2=49, Sw_AdL3=50,Sw_WPA0=51,
Sw_CmdL2=52, Sw_CmdL3=53, Sw_AdL4=54, Sw_AdL5=55, Sw_WPA1=56,
Swait3=57, Sw_CmdL4=58, Sw_CmdL5=59, Sw_WC1=60, Sw_WC2=61, Sw_CmdL6=62,
Sw_CmdL7=63, Sw_DR1=64, Sw_Wait4=65, Sw_Wait5=66, Sw_done=67,
Srst_RAR=68, Srst_CmdL0=69, Srst_CmdL1=70,Srst_done=71,
Srid_RAR=72, Srid_CmdL0=73, Srid_CmdL1=74, Srid_AdL0=75,
Srid_Wait=76, Srid_DR1=78, Srid_DR2=79, Srid_DR3=80, Srid_DR4=81, Srid_done=82;
reg [7:0] NxST,CrST;
reg BF_sel_int;
parameter C0=4'b0000,
C1=4'b0001,
C3=4'b0011,
C5=4'b0101,
C6=4'b0110,
C7=4'b0111,
C8=4'b1000,
CD=4'b1101,
CE=4'b1110,
CF=4'b1111,
C9=4'b1001;
assign mBF_sel=BF_sel_int;
always@(posedge CLK)
if(start)
BF_sel_int<=BF_sel;
always@(posedge CLK)
CrST<=NxST;
always@(RES or command or start or R_nB or t_done or tc4 or tc8 or io_0 or CrST)
if(RES) begin
NxST <= Init;
setDone <= 0;
BF_we <= 0;
t_start <= 0;
t_cmd <= 3'b011;
WrECC <= 0;
EnEcc <= 0;
AMX_sel <= 2'b00;
cmd_reg <= 8'b00000000;
cmd_reg_we <= 0;
set835 <= 0;
cnt_res <= 0;
wCntRes <= 0;
wCntCE <= 0;
ADC_sel <=2'b11;
SetPrErr <= 0;
SetErErr <= 0;
RAR_we <= 0;
end else begin
setDone <= 0;
BF_we <= 0;
t_start <=0;
t_cmd <= 3'b011;
WrECC <= 0;
EnEcc <= 0;
AMX_sel <= 2'b00;
cmd_reg <= 8'b00000000;
cmd_reg_we <= 0;
set835 <= 0;
cnt_res <= 0;
wCntRes <= 0;
wCntCE <= 0;
ADC_sel <= 2'b11;
SetPrErr <= 0;
SetErErr <= 0;
RAR_we <= 0;
case(CrST)
Init:begin
if (start)
NxST <=S_ADS;
else
NxST <=Init;
end
S_ADS:begin
cnt_res <= 1;
if (command ==3'b100)
NxST <= S_RAR;
else if (command==3'b010)
NxST <= Sr_RAR;
else if (command==3'b001)
NxST <= Sw_RAR;
else if (command==3'b011)
NxST <= Srst_RAR;
else if (command==3'b101)
NxST <= Srid_RAR;
else begin
setDone <= 1;
NxST <= Init;
SetPrErr <=1;
SetErErr <= 1;
end
end
S_RAR:begin
RAR_we <= 1;
NxST <= S_CmdL0;
end
S_CmdL0:begin
cmd_reg <= {C6,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL1;
end
S_CmdL1:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done == 1)
NxST <= S_adL0;
else
NxST <= S_CmdL1;
end
S_adL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done == 1)
NxST <= S_adL1;
else
NxST <= S_adL0;
end
S_adL1:begin
t_start <=1;
t_cmd <= 3'b001;
ADC_sel <=2'b10;
AMX_sel <=2'b11;
if (t_done ==1)
NxST <= S_CmdL2;
else
NxST <= S_adL1;
end
S_CmdL2:begin
cmd_reg <= {CD,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL3;
end
S_CmdL3:begin
t_start <= 1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= S_WC0;
else
NxST <= S_CmdL3;
end
S_WC0:begin
wCntRes <=1;
NxST <= S_WC1;
end
S_WC1:begin
wCntCE <=1;
if (tc8 == 1)
NxST <= S_wait;
else
NxST <= S_WC1;
end
S_wait:begin
if (R_nB ==1)
NxST <= S_CmdL4;
else
NxST <= S_wait;
end
S_CmdL4:begin
cmd_reg <= {C7,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL5;
end
S_CmdL5:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= S_WC3;
else
NxST <= S_CmdL5;
end
S_WC3:begin
wCntRes <= 1;
NxST <= S_WC4;
end
S_WC4:begin
wCntCE <=1;
if (tc4 ==1)
NxST <= S_DR1;
else
NxST <= S_WC4;
end
S_DR1:begin
t_start <= 1;
t_cmd <= 3'b010;
if (t_done ==1)
NxST <= S_Done;
else
NxST <= S_DR1;
end
S_Done:begin
setDone <=1;
NxST <= Init;
if (io_0 == 1)
SetErErr <= 1;
else
SetErErr <= 0;
end
Sr_RAR:begin
RAR_we <= 1;
NxST <= Sr_CmdL0;
end
Sr_CmdL0:begin
cmd_reg <= {C0,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL1;
end
Sr_CmdL1:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sr_AdL0;
else
NxST <= Sr_CmdL1;
end
Sr_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done ==1)
NxST <= Sr_AdL1;
else
NxST <= Sr_AdL0;
end
Sr_AdL1:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done==1)
NxST <= Sr_AdL2;
else
NxST <= Sr_AdL1;
end
Sr_AdL2:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Sr_AdL3;
else
NxST <= Sr_AdL2;
end
Sr_AdL3:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b11;
if (t_done ==1)
NxST <= Sr_CmdL2;
else
NxST <= Sr_AdL3;
end
Sr_CmdL2:begin
cmd_reg <= {C3,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL3;
end
Sr_CmdL3:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sr_WC0;
else
NxST <= Sr_CmdL3;
end
Sr_WC0:begin
wCntRes <=1;
NxST <= Sr_WC1;
end
Sr_WC1:begin
wCntCE <= 1;
if (tc8 ==1)
NxST <= Sr_wait;
else
NxST <= Sr_WC1;
end
Sr_wait:begin
if (R_nB==0)
NxST <= Sr_wait;
else
NxST <= Sr_RPA0;
end
Sr_RPA0:begin
t_start <= 1;
t_cmd <= 3'b101;
BF_we <= 1;
if (t_done==1)begin
NxST <= Sr_CmdL4;
t_cmd <= 3'b000;
end else
NxST <= Sr_RPA0;
end
Sr_CmdL4:begin
cmd_reg <= {C0,C5};
cmd_reg_we <= 1;
set835 <= 1;
t_cmd <= 3'b000;
NxST <= Sr_CmdL5;
end
Sr_CmdL5:begin
t_start <= 1;
t_cmd <=3'b000;
if (t_done)
NxST <= Sr_AdL4;
else
NxST <= Sr_CmdL5;
end
Sr_AdL4:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done)
NxST <= Sr_AdL5;
else
NxST <= Sr_AdL4;
end
Sr_AdL5:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <=2'b10;
AMX_sel <=2'b01;
if (t_done)
NxST <= Sr_CmdL6;
else
NxST <= Sr_AdL5;
end
Sr_CmdL6:begin
cmd_reg <= {CE,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL7;
end
Sr_CmdL7:begin
t_start <= 1;
t_cmd <= 3'b000;
wCntRes <= 1;
if (t_done)
NxST <= Sr_RPA1;
else
NxST <= Sr_CmdL7;
end
Sr_RPA1:begin
t_start <= 1;
t_cmd <=3'b100;
WrECC <=1;
if (t_done) begin
NxST <= Sr_wait1;
t_cmd <= 3'b011;
end else
NxST <= Sr_RPA1;
end
Sr_wait1:begin
WrECC <=1;
NxST <= Sr_wait2;
end
Sr_wait2:begin
WrECC <= 1;
NxST <= Sr_WC3;
end
Sr_WC3:begin
WrECC <=1;
wCntCE <=1;
if (tc4 ==0)
NxST <= Sr_WC3;
else
NxST <= Sr_Done;
end
Sr_Done:begin
setDone <=1;
NxST <= Init;
end
Sw_RAR:begin
RAR_we <=1;
NxST <= Sw_CmdL0;
end
Sw_CmdL0:begin
cmd_reg <= {C8,C0};
cmd_reg_we <= 1;
NxST <= Sw_CmdL1;
end
Sw_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Sw_AdL0;
else
NxST <= Sw_CmdL1;
end
Sw_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done ==1)
NxST <= Sw_AdL1;
else
NxST <= Sw_AdL0;
end
Sw_AdL1:begin
t_start <=1;
t_cmd <=3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done ==1)
NxST <= Sw_AdL2;
else
NxST <= Sw_AdL1;
end
Sw_AdL2:begin
t_start <=1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Sw_AdL3;
else
NxST <= Sw_AdL2;
end
Sw_AdL3:begin
t_start<=1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b11;
if (t_done ==1)
NxST <= Sw_WPA0;
else
NxST <= Sw_AdL3;
end
Sw_WPA0:begin
t_start <=1;
t_cmd <= 3'b111;
ADC_sel <=2'b00;
if (t_done==1) begin
NxST <= Sw_CmdL2;
t_cmd <=3'b000;
end else
NxST <= Sw_WPA0;
end
Sw_CmdL2:begin
cmd_reg <= {C8,C5};
cmd_reg_we <= 1;
set835 <= 1;
t_cmd <= 3'b000;
NxST <= Sw_CmdL3;
end
Sw_CmdL3:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done)
NxST <= Sw_AdL4;
else
NxST <= Sw_CmdL3;
end
Sw_AdL4:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done)
NxST <= Sw_AdL5;
else
NxST <= Sw_AdL4;
end
Sw_AdL5:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done)
NxST <= Sw_WPA1;
else
NxST <= Sw_AdL5;
end
Sw_WPA1:begin
t_start <= 1;
t_cmd <= 3'b110;
ADC_sel <= 2'b01;
EnEcc <= 1;
if (t_done) begin
NxST <= Sw_CmdL4;
t_cmd <= 3'b000;
end else
NxST <= Sw_WPA1;
end
Sw_CmdL4:begin
cmd_reg <= {C1,C0};
t_cmd <= 3'b000;
cmd_reg_we <= 1;
NxST <= Sw_CmdL5;
end
Sw_CmdL5:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sw_WC1;
else
NxST <= Sw_CmdL5;
end
Sw_WC1:begin
wCntRes <=1;
NxST <= Sw_WC2;
end
Sw_WC2:begin
wCntCE <=1;
if (tc8 ==1)
NxST <= Swait3;
else
NxST <= Sw_WC2;
end
Swait3:begin
if (R_nB ==1)
NxST <= Sw_CmdL6;
else
NxST <= Swait3;
end
Sw_CmdL6:begin
cmd_reg <= {C7,C0};
cmd_reg_we <= 1;
NxST <= Sw_CmdL7;
end
Sw_CmdL7:begin
t_start <=1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sw_Wait4;
else
NxST <= Sw_CmdL7;
end
Sw_Wait4:begin
NxST <= Sw_Wait5;
end
Sw_Wait5:begin
NxST <= Sw_DR1;
end
Sw_DR1:begin
t_start <=1;
t_cmd <= 3'b010;
if (t_done ==1)
NxST <= Sw_done;
else
NxST <= Sw_DR1;
end
Sw_done:begin
setDone <= 1;
NxST <= Init;
if (io_0 ==1)
SetPrErr <=1;
else begin
SetPrErr <= 0;
end
end
Srst_RAR:begin
NxST <= Srst_CmdL0;
end
Srst_CmdL0:begin
cmd_reg <= {CF,CF};
cmd_reg_we <= 1;
NxST <= Srst_CmdL1;
end
Srst_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Srst_done;
else
NxST <= Srst_CmdL1;
end
Srst_done:begin
setDone <= 1;
NxST <= Init;
end
Srid_RAR:begin
RAR_we <=1;
NxST <= Srid_CmdL0;
end
Srid_CmdL0:begin
cmd_reg <= {C9,C0};
cmd_reg_we <= 1;
NxST <= Srid_CmdL1;
end
Srid_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Srid_AdL0;
else
NxST <= Srid_CmdL1;
end
Srid_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Srid_Wait;
else
NxST <= Srid_AdL0;
end
Srid_Wait:begin
wCntRes <=1;
NxST <= Srid_DR1;
end
Srid_DR1:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR2;
else
NxST <= Srid_DR1;
end
Srid_DR2:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR3;
else
NxST <= Srid_DR2;
end
Srid_DR3:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR4;
else
NxST <= Srid_DR3;
end
Srid_DR4:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_done;
else
NxST <= Srid_DR4;
end
Srid_done:begin
setDone <= 1;
NxST <= Init;
end
default:begin
NxST <= Init;
end
endcase
end
endmodule | module MFSM(
CLK,
RES,
start,
command,
setDone,
R_nB,
BF_sel,
mBF_sel,
BF_we,
io_0,
t_start,
t_cmd,
t_done,
WrECC,
EnEcc,
AMX_sel,
cmd_reg,
cmd_reg_we,
RAR_we,
set835,
cnt_res,
tc8,
tc4,
wCntRes,
wCntCE,
SetPrErr,
SetErErr,
ADC_sel
); |
input CLK;
input RES;
input start;
input [2:0] command;
input R_nB;
input BF_sel;
input io_0;
input t_done;
input tc8;
input tc4;
output reg setDone;
output mBF_sel;
output reg BF_we;
output reg t_start;
output reg [2:0] t_cmd;
output reg WrECC;
output reg EnEcc;
output reg [1:0] AMX_sel;
output reg [7:0] cmd_reg;
output reg cmd_reg_we;
output reg RAR_we;
output reg set835;
output reg cnt_res;
output reg wCntRes;
output reg wCntCE;
output reg SetPrErr;
output reg SetErErr;
output reg [1:0] ADC_sel;
parameter Init=0,S_ADS=1, S_RAR=2,
S_CmdL0=3,S_CmdL1=4,S_adL0=5,S_adL1=6, S_CmdL2=7, S_CmdL3=8,
S_WC0=9, S_WC1=10, S_wait=11, S_CmdL4=12, S_CmdL5=13, S_WC3=14, S_WC4=15, S_DR1=16, S_Done=17,
Sr_RAR=18, Sr_DnErr=19, Sr_CmdL0=20, Sr_CmdL1=21, Sr_AdL0=22, Sr_AdL1=23, Sr_AdL2=24,
Sr_AdL3=25, Sr_CmdL2=26, Sr_CmdL3=27, Sr_WC0=28, Sr_WC1=29, Sr_wait=30, Sr_RPA0=31,
Sr_CmdL4=32, Sr_CmdL5=33, Sr_AdL4=34, Sr_AdL5=35, Sr_CmdL6=36, Sr_CmdL7=37, Sr_WC2=38,Sr_RPA1=39,
Sr_wait1=40, Sr_wait2=41, Sr_WC3=42, Sr_Done=43,
Sw_RAR=44, Sw_CmdL0=45, Sw_CmdL1=46, Sw_AdL0=47, Sw_AdL1=48, Sw_AdL2=49, Sw_AdL3=50,Sw_WPA0=51,
Sw_CmdL2=52, Sw_CmdL3=53, Sw_AdL4=54, Sw_AdL5=55, Sw_WPA1=56,
Swait3=57, Sw_CmdL4=58, Sw_CmdL5=59, Sw_WC1=60, Sw_WC2=61, Sw_CmdL6=62,
Sw_CmdL7=63, Sw_DR1=64, Sw_Wait4=65, Sw_Wait5=66, Sw_done=67,
Srst_RAR=68, Srst_CmdL0=69, Srst_CmdL1=70,Srst_done=71,
Srid_RAR=72, Srid_CmdL0=73, Srid_CmdL1=74, Srid_AdL0=75,
Srid_Wait=76, Srid_DR1=78, Srid_DR2=79, Srid_DR3=80, Srid_DR4=81, Srid_done=82;
reg [7:0] NxST,CrST;
reg BF_sel_int;
parameter C0=4'b0000,
C1=4'b0001,
C3=4'b0011,
C5=4'b0101,
C6=4'b0110,
C7=4'b0111,
C8=4'b1000,
CD=4'b1101,
CE=4'b1110,
CF=4'b1111,
C9=4'b1001;
assign mBF_sel=BF_sel_int;
always@(posedge CLK)
if(start)
BF_sel_int<=BF_sel;
always@(posedge CLK)
CrST<=NxST;
always@(RES or command or start or R_nB or t_done or tc4 or tc8 or io_0 or CrST)
if(RES) begin
NxST <= Init;
setDone <= 0;
BF_we <= 0;
t_start <= 0;
t_cmd <= 3'b011;
WrECC <= 0;
EnEcc <= 0;
AMX_sel <= 2'b00;
cmd_reg <= 8'b00000000;
cmd_reg_we <= 0;
set835 <= 0;
cnt_res <= 0;
wCntRes <= 0;
wCntCE <= 0;
ADC_sel <=2'b11;
SetPrErr <= 0;
SetErErr <= 0;
RAR_we <= 0;
end else begin
setDone <= 0;
BF_we <= 0;
t_start <=0;
t_cmd <= 3'b011;
WrECC <= 0;
EnEcc <= 0;
AMX_sel <= 2'b00;
cmd_reg <= 8'b00000000;
cmd_reg_we <= 0;
set835 <= 0;
cnt_res <= 0;
wCntRes <= 0;
wCntCE <= 0;
ADC_sel <= 2'b11;
SetPrErr <= 0;
SetErErr <= 0;
RAR_we <= 0;
case(CrST)
Init:begin
if (start)
NxST <=S_ADS;
else
NxST <=Init;
end
S_ADS:begin
cnt_res <= 1;
if (command ==3'b100)
NxST <= S_RAR;
else if (command==3'b010)
NxST <= Sr_RAR;
else if (command==3'b001)
NxST <= Sw_RAR;
else if (command==3'b011)
NxST <= Srst_RAR;
else if (command==3'b101)
NxST <= Srid_RAR;
else begin
setDone <= 1;
NxST <= Init;
SetPrErr <=1;
SetErErr <= 1;
end
end
S_RAR:begin
RAR_we <= 1;
NxST <= S_CmdL0;
end
S_CmdL0:begin
cmd_reg <= {C6,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL1;
end
S_CmdL1:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done == 1)
NxST <= S_adL0;
else
NxST <= S_CmdL1;
end
S_adL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done == 1)
NxST <= S_adL1;
else
NxST <= S_adL0;
end
S_adL1:begin
t_start <=1;
t_cmd <= 3'b001;
ADC_sel <=2'b10;
AMX_sel <=2'b11;
if (t_done ==1)
NxST <= S_CmdL2;
else
NxST <= S_adL1;
end
S_CmdL2:begin
cmd_reg <= {CD,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL3;
end
S_CmdL3:begin
t_start <= 1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= S_WC0;
else
NxST <= S_CmdL3;
end
S_WC0:begin
wCntRes <=1;
NxST <= S_WC1;
end
S_WC1:begin
wCntCE <=1;
if (tc8 == 1)
NxST <= S_wait;
else
NxST <= S_WC1;
end
S_wait:begin
if (R_nB ==1)
NxST <= S_CmdL4;
else
NxST <= S_wait;
end
S_CmdL4:begin
cmd_reg <= {C7,C0};
cmd_reg_we <= 1;
NxST <= S_CmdL5;
end
S_CmdL5:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= S_WC3;
else
NxST <= S_CmdL5;
end
S_WC3:begin
wCntRes <= 1;
NxST <= S_WC4;
end
S_WC4:begin
wCntCE <=1;
if (tc4 ==1)
NxST <= S_DR1;
else
NxST <= S_WC4;
end
S_DR1:begin
t_start <= 1;
t_cmd <= 3'b010;
if (t_done ==1)
NxST <= S_Done;
else
NxST <= S_DR1;
end
S_Done:begin
setDone <=1;
NxST <= Init;
if (io_0 == 1)
SetErErr <= 1;
else
SetErErr <= 0;
end
Sr_RAR:begin
RAR_we <= 1;
NxST <= Sr_CmdL0;
end
Sr_CmdL0:begin
cmd_reg <= {C0,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL1;
end
Sr_CmdL1:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sr_AdL0;
else
NxST <= Sr_CmdL1;
end
Sr_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done ==1)
NxST <= Sr_AdL1;
else
NxST <= Sr_AdL0;
end
Sr_AdL1:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done==1)
NxST <= Sr_AdL2;
else
NxST <= Sr_AdL1;
end
Sr_AdL2:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Sr_AdL3;
else
NxST <= Sr_AdL2;
end
Sr_AdL3:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b11;
if (t_done ==1)
NxST <= Sr_CmdL2;
else
NxST <= Sr_AdL3;
end
Sr_CmdL2:begin
cmd_reg <= {C3,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL3;
end
Sr_CmdL3:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sr_WC0;
else
NxST <= Sr_CmdL3;
end
Sr_WC0:begin
wCntRes <=1;
NxST <= Sr_WC1;
end
Sr_WC1:begin
wCntCE <= 1;
if (tc8 ==1)
NxST <= Sr_wait;
else
NxST <= Sr_WC1;
end
Sr_wait:begin
if (R_nB==0)
NxST <= Sr_wait;
else
NxST <= Sr_RPA0;
end
Sr_RPA0:begin
t_start <= 1;
t_cmd <= 3'b101;
BF_we <= 1;
if (t_done==1)begin
NxST <= Sr_CmdL4;
t_cmd <= 3'b000;
end else
NxST <= Sr_RPA0;
end
Sr_CmdL4:begin
cmd_reg <= {C0,C5};
cmd_reg_we <= 1;
set835 <= 1;
t_cmd <= 3'b000;
NxST <= Sr_CmdL5;
end
Sr_CmdL5:begin
t_start <= 1;
t_cmd <=3'b000;
if (t_done)
NxST <= Sr_AdL4;
else
NxST <= Sr_CmdL5;
end
Sr_AdL4:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done)
NxST <= Sr_AdL5;
else
NxST <= Sr_AdL4;
end
Sr_AdL5:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <=2'b10;
AMX_sel <=2'b01;
if (t_done)
NxST <= Sr_CmdL6;
else
NxST <= Sr_AdL5;
end
Sr_CmdL6:begin
cmd_reg <= {CE,C0};
cmd_reg_we <= 1;
NxST <= Sr_CmdL7;
end
Sr_CmdL7:begin
t_start <= 1;
t_cmd <= 3'b000;
wCntRes <= 1;
if (t_done)
NxST <= Sr_RPA1;
else
NxST <= Sr_CmdL7;
end
Sr_RPA1:begin
t_start <= 1;
t_cmd <=3'b100;
WrECC <=1;
if (t_done) begin
NxST <= Sr_wait1;
t_cmd <= 3'b011;
end else
NxST <= Sr_RPA1;
end
Sr_wait1:begin
WrECC <=1;
NxST <= Sr_wait2;
end
Sr_wait2:begin
WrECC <= 1;
NxST <= Sr_WC3;
end
Sr_WC3:begin
WrECC <=1;
wCntCE <=1;
if (tc4 ==0)
NxST <= Sr_WC3;
else
NxST <= Sr_Done;
end
Sr_Done:begin
setDone <=1;
NxST <= Init;
end
Sw_RAR:begin
RAR_we <=1;
NxST <= Sw_CmdL0;
end
Sw_CmdL0:begin
cmd_reg <= {C8,C0};
cmd_reg_we <= 1;
NxST <= Sw_CmdL1;
end
Sw_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Sw_AdL0;
else
NxST <= Sw_CmdL1;
end
Sw_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done ==1)
NxST <= Sw_AdL1;
else
NxST <= Sw_AdL0;
end
Sw_AdL1:begin
t_start <=1;
t_cmd <=3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done ==1)
NxST <= Sw_AdL2;
else
NxST <= Sw_AdL1;
end
Sw_AdL2:begin
t_start <=1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Sw_AdL3;
else
NxST <= Sw_AdL2;
end
Sw_AdL3:begin
t_start<=1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b11;
if (t_done ==1)
NxST <= Sw_WPA0;
else
NxST <= Sw_AdL3;
end
Sw_WPA0:begin
t_start <=1;
t_cmd <= 3'b111;
ADC_sel <=2'b00;
if (t_done==1) begin
NxST <= Sw_CmdL2;
t_cmd <=3'b000;
end else
NxST <= Sw_WPA0;
end
Sw_CmdL2:begin
cmd_reg <= {C8,C5};
cmd_reg_we <= 1;
set835 <= 1;
t_cmd <= 3'b000;
NxST <= Sw_CmdL3;
end
Sw_CmdL3:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done)
NxST <= Sw_AdL4;
else
NxST <= Sw_CmdL3;
end
Sw_AdL4:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b00;
if (t_done)
NxST <= Sw_AdL5;
else
NxST <= Sw_AdL4;
end
Sw_AdL5:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b01;
if (t_done)
NxST <= Sw_WPA1;
else
NxST <= Sw_AdL5;
end
Sw_WPA1:begin
t_start <= 1;
t_cmd <= 3'b110;
ADC_sel <= 2'b01;
EnEcc <= 1;
if (t_done) begin
NxST <= Sw_CmdL4;
t_cmd <= 3'b000;
end else
NxST <= Sw_WPA1;
end
Sw_CmdL4:begin
cmd_reg <= {C1,C0};
t_cmd <= 3'b000;
cmd_reg_we <= 1;
NxST <= Sw_CmdL5;
end
Sw_CmdL5:begin
t_start <= 1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sw_WC1;
else
NxST <= Sw_CmdL5;
end
Sw_WC1:begin
wCntRes <=1;
NxST <= Sw_WC2;
end
Sw_WC2:begin
wCntCE <=1;
if (tc8 ==1)
NxST <= Swait3;
else
NxST <= Sw_WC2;
end
Swait3:begin
if (R_nB ==1)
NxST <= Sw_CmdL6;
else
NxST <= Swait3;
end
Sw_CmdL6:begin
cmd_reg <= {C7,C0};
cmd_reg_we <= 1;
NxST <= Sw_CmdL7;
end
Sw_CmdL7:begin
t_start <=1;
t_cmd <= 3'b000;
if (t_done ==1)
NxST <= Sw_Wait4;
else
NxST <= Sw_CmdL7;
end
Sw_Wait4:begin
NxST <= Sw_Wait5;
end
Sw_Wait5:begin
NxST <= Sw_DR1;
end
Sw_DR1:begin
t_start <=1;
t_cmd <= 3'b010;
if (t_done ==1)
NxST <= Sw_done;
else
NxST <= Sw_DR1;
end
Sw_done:begin
setDone <= 1;
NxST <= Init;
if (io_0 ==1)
SetPrErr <=1;
else begin
SetPrErr <= 0;
end
end
Srst_RAR:begin
NxST <= Srst_CmdL0;
end
Srst_CmdL0:begin
cmd_reg <= {CF,CF};
cmd_reg_we <= 1;
NxST <= Srst_CmdL1;
end
Srst_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Srst_done;
else
NxST <= Srst_CmdL1;
end
Srst_done:begin
setDone <= 1;
NxST <= Init;
end
Srid_RAR:begin
RAR_we <=1;
NxST <= Srid_CmdL0;
end
Srid_CmdL0:begin
cmd_reg <= {C9,C0};
cmd_reg_we <= 1;
NxST <= Srid_CmdL1;
end
Srid_CmdL1:begin
t_start <=1;
t_cmd <=3'b000;
if (t_done ==1)
NxST <= Srid_AdL0;
else
NxST <= Srid_CmdL1;
end
Srid_AdL0:begin
t_start <= 1;
t_cmd <= 3'b001;
ADC_sel <= 2'b10;
AMX_sel <= 2'b10;
if (t_done ==1)
NxST <= Srid_Wait;
else
NxST <= Srid_AdL0;
end
Srid_Wait:begin
wCntRes <=1;
NxST <= Srid_DR1;
end
Srid_DR1:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR2;
else
NxST <= Srid_DR1;
end
Srid_DR2:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR3;
else
NxST <= Srid_DR2;
end
Srid_DR3:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_DR4;
else
NxST <= Srid_DR3;
end
Srid_DR4:begin
t_start <=1;
t_cmd <= 3'b010;
BF_we <= 1;
if (t_done ==1)
NxST <= Srid_done;
else
NxST <= Srid_DR4;
end
Srid_done:begin
setDone <= 1;
NxST <= Init;
end
default:begin
NxST <= Init;
end
endcase
end
endmodule | 1 |
4,329 | data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v | 109,400,221 | nfcm_top.v | v | 416 | 83 | [] | [] | [] | [(57, 415)] | null | null | 1: b"%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:187: Cannot find file containing module: 'ebr_buffer'\nebr_buffer buff( \n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog,data/full_repos/permissive/109400221/ebr_buffer\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog,data/full_repos/permissive/109400221/ebr_buffer.v\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog,data/full_repos/permissive/109400221/ebr_buffer.sv\n ebr_buffer\n ebr_buffer.v\n ebr_buffer.sv\n obj_dir/ebr_buffer\n obj_dir/ebr_buffer.v\n obj_dir/ebr_buffer.sv\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:204: Cannot find file containing module: 'ACounter'\nACounter addr_counter (\n^~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:214: Cannot find file containing module: 'TFSM'\nTFSM tim_fsm(\n^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:233: Cannot find file containing module: 'MFSM'\nMFSM main_fsm\n^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:274: Cannot find file containing module: 'H_gen'\nH_gen ecc_gen(\n^~~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/nfcm_top.v:283: Cannot find file containing module: 'ErrLoc'\nErrLoc ecc_err_loc \n^~~~~~\n%Error: Exiting due to 6 error(s)\n" | 2,560 | module | module nfcm_top(
DIO,
CLE ,
ALE ,
WE_n,
RE_n,
CE_n,
R_nB,
CLK,
RES,
BF_sel ,
BF_ad ,
BF_din ,
BF_dou ,
BF_we ,
RWA ,
PErr,
EErr,
RErr,
nfc_cmd ,
nfc_strt,
nfc_done
);
inout [7:0] DIO;
output reg CLE;
output reg ALE;
output reg WE_n;
output reg RE_n;
output reg CE_n;
input R_nB;
input CLK ;
input RES ;
input BF_sel;
input [10:0] BF_ad;
input [7:0] BF_din;
input BF_we;
input [15:0] RWA;
output [7:0] BF_dou;
output reg PErr ;
output reg EErr ;
output reg RErr ;
input [2:0] nfc_cmd;
input nfc_strt;
output reg nfc_done;
parameter HI= 1'b1;
parameter LO= 1'b0;
reg ires, res_t;
wire [7:0] FlashDataIn;
reg [7:0] FlashCmd;
reg [7:0] FlashDataOu;
wire [1:0] adc_sel;
wire [7:0] QA_1,QB_1;
wire [7:0] BF_data2flash, ECC_data;
wire Flash_BF_sel, Flash_BF_we, DIS, F_we;
wire rar_we;
reg [7:0] addr_data;
reg [7:0] rad_1;
reg [7:0] rad_2;
wire [7:0] cad_1;
wire [7:0] cad_2;
wire [1:0] amx_sel;
wire CntEn, tc3, tc2048, cnt_res, acnt_res;
wire [11:0] CntOut;
reg DOS;
wire t_start, t_done;
wire [2:0] t_cmd;
wire WCountRes, WCountCE;
reg TC4, TC8;
wire cmd_we ;
wire [7:0] cmd_reg;
wire SetPrErr, SetErErr,SetRrErr;
wire WrECC, WrECC_e, enEcc, Ecc_en,ecc_en_tfsm;
wire setDone, set835;
wire ALE_i, CLE_i, WE_ni, CE_ni, RE_ni;
wire DOS_i;
reg [7:0] FlashDataOu_i ;
assign BF_dou = QA_1;
assign BF_data2flash = QB_1;
assign cad_1 = CntOut[7:0];
assign cad_2 = {4'b0000,CntOut[11:8]};
assign acnt_res = (ires | cnt_res);
assign WrECC_e = WrECC & DIS;
assign Flash_BF_we = DIS & F_we;
assign Ecc_en = enEcc & ecc_en_tfsm;
ebr_buffer buff(
.DataInA(BF_din),
.QA(QA_1),
.AddressA(BF_ad),
.ClockA(CLK),
.ClockEnA(BF_sel),
.WrA(BF_we),
.ResetA(LO),
.DataInB(FlashDataIn),
.QB(QB_1),
.AddressB(CntOut[10:0]),
.ClockB(CLK),
.ClockEnB(Flash_BF_sel),
.WrB(Flash_BF_we),
.ResetB(LO)
);
ACounter addr_counter (
.clk(CLK),
.Res(acnt_res),
.Set835(set835),
.CntEn(CntEn),
.CntOut(CntOut),
.TC2048(tc2048),
.TC3(tc3)
);
TFSM tim_fsm(
.CLE(CLE_i),
.ALE (ALE_i),
.WE_n(WE_ni),
.RE_n(RE_ni),
.CE_n(CE_ni),
.DOS (DOS_i),
.DIS (DIS),
.cnt_en(CntEn),
.TC3(tc3),
.TC2048(tc2048),
.CLK(CLK),
.RES(ires),
.start(t_start),
.cmd_code(t_cmd),
.ecc_en(ecc_en_tfsm),
.Done(t_done)
);
MFSM main_fsm
(
.CLK ( CLK ),
.RES ( ires ),
.start ( nfc_strt),
.command(nfc_cmd),
.setDone(setDone),
.R_nB (R_nB),
.BF_sel( BF_sel),
.mBF_sel ( Flash_BF_sel),
.BF_we( F_we),
.io_0( FlashDataIn[0]),
.t_start ( t_start),
.t_cmd ( t_cmd),
.t_done ( t_done),
.WrECC ( WrECC),
.EnEcc ( enEcc),
.AMX_sel ( amx_sel),
.cmd_reg ( cmd_reg),
.cmd_reg_we( cmd_we),
.RAR_we ( rar_we),
.set835 ( set835),
.cnt_res ( cnt_res),
.tc8 ( TC8),
.tc4 ( TC4),
.wCntRes( WCountRes),
.wCntCE ( WCountCE),
.SetPrErr ( SetPrErr),
.SetErErr ( SetErErr),
.ADC_sel ( adc_sel)
);
H_gen ecc_gen(
. clk( CLK),
. Res( acnt_res),
. Din( BF_data2flash[3:0]),
. EN (Ecc_en),
. eccByte ( ECC_data)
);
ErrLoc ecc_err_loc
(
.clk( CLK),
.Res (acnt_res),
.F_ecc_data (FlashDataIn[6:0]),
.WrECC (WrECC_e),
.ECC_status (SetRrErr)
);
always@(posedge CLK)
begin
res_t <= RES;
ires <= res_t;
end
always@(posedge CLK)
if (rar_we) begin
rad_1=RWA[7:0];
rad_2=RWA[15:8];
end
always@(posedge CLK)
begin
FlashDataOu <= FlashDataOu_i;
DOS <= DOS_i;
ALE <= ALE_i;
CLE <= CLE_i;
WE_n <= WE_ni;
CE_n <= CE_ni;
RE_n <= RE_ni;
end
always@(cad_1 or cad_2 or rad_1 or rad_2 or amx_sel)
begin
case (amx_sel)
2'b11 : addr_data <= rad_2;
2'b10 : addr_data <= rad_1;
2'b01 : addr_data <= cad_2;
default: addr_data <= cad_1;
endcase
end
always@(adc_sel or BF_data2flash or FlashCmd or addr_data or ECC_data)
begin
case (adc_sel)
2'b11 : FlashDataOu_i <= FlashCmd;
2'b10 : FlashDataOu_i <= addr_data;
2'b01 : FlashDataOu_i <= ECC_data;
default: FlashDataOu_i <= BF_data2flash;
endcase
end
reg [3:0] WC_tmp;
always@(posedge CLK)
begin
if ((ires ==1'b1) | (WCountRes ==1'b1))
WC_tmp<= 4'b0000;
else if (WCountCE ==1'b1)
WC_tmp<= WC_tmp + 1;
if (WC_tmp ==4'b0100) begin
TC4 <= 1'b1;
TC8 <= 1'b0;
end else if (WC_tmp ==4'b1000) begin
TC8<= 1'b1;
TC4 <=1'b0;
end else begin
TC4 <=1'b0;
TC8 <=1'b0;
end
end
always@(posedge CLK)
begin
if (ires)
FlashCmd <=8'b00000000;
else if (cmd_we)
FlashCmd <= cmd_reg;
end
always@(posedge CLK)
begin
if (ires)
nfc_done <= 1'b0;
else if (setDone)
nfc_done <=1'b1;
else if (nfc_strt)
nfc_done <=1'b0;
end
always@(posedge CLK)
begin
if (ires)
PErr <=1'b0;
else if (SetPrErr)
PErr <= 1'b1;
else if (nfc_strt)
PErr <= 1'b0;
end
always@(posedge CLK)
begin
if (ires)
EErr <=1'b0;
else if (SetErErr)
EErr <=1'b1;
else if (nfc_strt)
EErr <= 1'b0;
end
always@(posedge CLK)
begin
if (ires)
RErr <=1'b0;
else if (SetRrErr)
RErr <= 1'b1;
else if (nfc_strt)
RErr <= 1'b0;
end
assign FlashDataIn = DIO;
assign DIO =(DOS == 1'b1)?FlashDataOu:8'hzz;
endmodule | module nfcm_top(
DIO,
CLE ,
ALE ,
WE_n,
RE_n,
CE_n,
R_nB,
CLK,
RES,
BF_sel ,
BF_ad ,
BF_din ,
BF_dou ,
BF_we ,
RWA ,
PErr,
EErr,
RErr,
nfc_cmd ,
nfc_strt,
nfc_done
); |
inout [7:0] DIO;
output reg CLE;
output reg ALE;
output reg WE_n;
output reg RE_n;
output reg CE_n;
input R_nB;
input CLK ;
input RES ;
input BF_sel;
input [10:0] BF_ad;
input [7:0] BF_din;
input BF_we;
input [15:0] RWA;
output [7:0] BF_dou;
output reg PErr ;
output reg EErr ;
output reg RErr ;
input [2:0] nfc_cmd;
input nfc_strt;
output reg nfc_done;
parameter HI= 1'b1;
parameter LO= 1'b0;
reg ires, res_t;
wire [7:0] FlashDataIn;
reg [7:0] FlashCmd;
reg [7:0] FlashDataOu;
wire [1:0] adc_sel;
wire [7:0] QA_1,QB_1;
wire [7:0] BF_data2flash, ECC_data;
wire Flash_BF_sel, Flash_BF_we, DIS, F_we;
wire rar_we;
reg [7:0] addr_data;
reg [7:0] rad_1;
reg [7:0] rad_2;
wire [7:0] cad_1;
wire [7:0] cad_2;
wire [1:0] amx_sel;
wire CntEn, tc3, tc2048, cnt_res, acnt_res;
wire [11:0] CntOut;
reg DOS;
wire t_start, t_done;
wire [2:0] t_cmd;
wire WCountRes, WCountCE;
reg TC4, TC8;
wire cmd_we ;
wire [7:0] cmd_reg;
wire SetPrErr, SetErErr,SetRrErr;
wire WrECC, WrECC_e, enEcc, Ecc_en,ecc_en_tfsm;
wire setDone, set835;
wire ALE_i, CLE_i, WE_ni, CE_ni, RE_ni;
wire DOS_i;
reg [7:0] FlashDataOu_i ;
assign BF_dou = QA_1;
assign BF_data2flash = QB_1;
assign cad_1 = CntOut[7:0];
assign cad_2 = {4'b0000,CntOut[11:8]};
assign acnt_res = (ires | cnt_res);
assign WrECC_e = WrECC & DIS;
assign Flash_BF_we = DIS & F_we;
assign Ecc_en = enEcc & ecc_en_tfsm;
ebr_buffer buff(
.DataInA(BF_din),
.QA(QA_1),
.AddressA(BF_ad),
.ClockA(CLK),
.ClockEnA(BF_sel),
.WrA(BF_we),
.ResetA(LO),
.DataInB(FlashDataIn),
.QB(QB_1),
.AddressB(CntOut[10:0]),
.ClockB(CLK),
.ClockEnB(Flash_BF_sel),
.WrB(Flash_BF_we),
.ResetB(LO)
);
ACounter addr_counter (
.clk(CLK),
.Res(acnt_res),
.Set835(set835),
.CntEn(CntEn),
.CntOut(CntOut),
.TC2048(tc2048),
.TC3(tc3)
);
TFSM tim_fsm(
.CLE(CLE_i),
.ALE (ALE_i),
.WE_n(WE_ni),
.RE_n(RE_ni),
.CE_n(CE_ni),
.DOS (DOS_i),
.DIS (DIS),
.cnt_en(CntEn),
.TC3(tc3),
.TC2048(tc2048),
.CLK(CLK),
.RES(ires),
.start(t_start),
.cmd_code(t_cmd),
.ecc_en(ecc_en_tfsm),
.Done(t_done)
);
MFSM main_fsm
(
.CLK ( CLK ),
.RES ( ires ),
.start ( nfc_strt),
.command(nfc_cmd),
.setDone(setDone),
.R_nB (R_nB),
.BF_sel( BF_sel),
.mBF_sel ( Flash_BF_sel),
.BF_we( F_we),
.io_0( FlashDataIn[0]),
.t_start ( t_start),
.t_cmd ( t_cmd),
.t_done ( t_done),
.WrECC ( WrECC),
.EnEcc ( enEcc),
.AMX_sel ( amx_sel),
.cmd_reg ( cmd_reg),
.cmd_reg_we( cmd_we),
.RAR_we ( rar_we),
.set835 ( set835),
.cnt_res ( cnt_res),
.tc8 ( TC8),
.tc4 ( TC4),
.wCntRes( WCountRes),
.wCntCE ( WCountCE),
.SetPrErr ( SetPrErr),
.SetErErr ( SetErErr),
.ADC_sel ( adc_sel)
);
H_gen ecc_gen(
. clk( CLK),
. Res( acnt_res),
. Din( BF_data2flash[3:0]),
. EN (Ecc_en),
. eccByte ( ECC_data)
);
ErrLoc ecc_err_loc
(
.clk( CLK),
.Res (acnt_res),
.F_ecc_data (FlashDataIn[6:0]),
.WrECC (WrECC_e),
.ECC_status (SetRrErr)
);
always@(posedge CLK)
begin
res_t <= RES;
ires <= res_t;
end
always@(posedge CLK)
if (rar_we) begin
rad_1=RWA[7:0];
rad_2=RWA[15:8];
end
always@(posedge CLK)
begin
FlashDataOu <= FlashDataOu_i;
DOS <= DOS_i;
ALE <= ALE_i;
CLE <= CLE_i;
WE_n <= WE_ni;
CE_n <= CE_ni;
RE_n <= RE_ni;
end
always@(cad_1 or cad_2 or rad_1 or rad_2 or amx_sel)
begin
case (amx_sel)
2'b11 : addr_data <= rad_2;
2'b10 : addr_data <= rad_1;
2'b01 : addr_data <= cad_2;
default: addr_data <= cad_1;
endcase
end
always@(adc_sel or BF_data2flash or FlashCmd or addr_data or ECC_data)
begin
case (adc_sel)
2'b11 : FlashDataOu_i <= FlashCmd;
2'b10 : FlashDataOu_i <= addr_data;
2'b01 : FlashDataOu_i <= ECC_data;
default: FlashDataOu_i <= BF_data2flash;
endcase
end
reg [3:0] WC_tmp;
always@(posedge CLK)
begin
if ((ires ==1'b1) | (WCountRes ==1'b1))
WC_tmp<= 4'b0000;
else if (WCountCE ==1'b1)
WC_tmp<= WC_tmp + 1;
if (WC_tmp ==4'b0100) begin
TC4 <= 1'b1;
TC8 <= 1'b0;
end else if (WC_tmp ==4'b1000) begin
TC8<= 1'b1;
TC4 <=1'b0;
end else begin
TC4 <=1'b0;
TC8 <=1'b0;
end
end
always@(posedge CLK)
begin
if (ires)
FlashCmd <=8'b00000000;
else if (cmd_we)
FlashCmd <= cmd_reg;
end
always@(posedge CLK)
begin
if (ires)
nfc_done <= 1'b0;
else if (setDone)
nfc_done <=1'b1;
else if (nfc_strt)
nfc_done <=1'b0;
end
always@(posedge CLK)
begin
if (ires)
PErr <=1'b0;
else if (SetPrErr)
PErr <= 1'b1;
else if (nfc_strt)
PErr <= 1'b0;
end
always@(posedge CLK)
begin
if (ires)
EErr <=1'b0;
else if (SetErErr)
EErr <=1'b1;
else if (nfc_strt)
EErr <= 1'b0;
end
always@(posedge CLK)
begin
if (ires)
RErr <=1'b0;
else if (SetRrErr)
RErr <= 1'b1;
else if (nfc_strt)
RErr <= 1'b0;
end
assign FlashDataIn = DIO;
assign DIO =(DOS == 1'b1)?FlashDataOu:8'hzz;
endmodule | 1 |
4,330 | data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/TFSM.v | 109,400,221 | TFSM.v | v | 351 | 86 | [] | [] | [] | [(51, 349)] | null | data/verilator_xmls/580c363c-f65b-4a8a-97e8-b91082db43ad.xml | null | 2,561 | module | module TFSM(
CLE ,
ALE ,
WE_n,
RE_n,
CE_n,
DOS ,
DIS ,
cnt_en,
TC3,
TC2048,
CLK,
RES,
start,
cmd_code,
ecc_en,
Done
);
output reg CLE ;
output reg ALE ;
output reg WE_n;
output reg RE_n;
output reg CE_n;
output reg DOS ;
output reg DIS ;
output reg cnt_en;
input TC3 ;
input TC2048;
input CLK ;
input RES ;
input start;
input [2:0] cmd_code;
output reg Done;
output reg ecc_en;
parameter Init=0, S_Start=1, S_CE=2,
S_CLE=3, S_CmdOut=4, S_WaitCmd=5, DoneCmd=6, Finish=7,
S_ALE=8, S_ADout=9, WaitAd=10, DoneAd=11,
S_RE1=12, WaitR1=13, WaitR2=14, DoneR1=15,
S_RE=16, WaitR1m=17, WaitR2m=18, WaitR3m=19, S_DIS=20, FinishR=21,
S_WE=22, WaitW=23, WaitW1=24, WaitW2=25, S_nWE=26, FinishW=27;
reg [5:0] NxST, CrST;
reg Done_i;
wire TC;
reg [2:0] cmd_code_int;
assign TC = cmd_code_int[0]?TC2048:TC3;
always@(posedge CLK)
if (RES)
Done <=0;
else
Done <= Done_i;
always@(posedge CLK)
cmd_code_int <= cmd_code;
always@(posedge CLK)
CrST <= NxST;
always@(RES or TC or cmd_code_int or start or CrST)
if (RES) begin
NxST <= Init;
DIS <= 0;
DOS <= 0;
Done_i <=0;
ALE <= 0;
CLE <= 0;
WE_n <= 1;
RE_n <= 1;
CE_n <= 1;
cnt_en <=0;
ecc_en<=1'b0;
end else begin
DIS <= 0;
DOS <= 0;
Done_i <=0;
ALE <= 0;
CLE <= 0;
WE_n <= 1;
RE_n <= 1;
CE_n <= 1;
cnt_en <=0;
ecc_en<=1'b0;
case (CrST)
Init:begin
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_Start:begin
if (cmd_code_int==3'b011)
NxST <= Init;
else
NxST <= S_CE;
end
S_CE:begin
if (cmd_code_int==3'b000) begin
NxST <= S_CLE;
CE_n <= 0;
end else if (cmd_code_int ==3'b001) begin
NxST <= S_ALE;
CE_n <= 0;
end else if (cmd_code_int ==3'b010) begin
NxST <= S_RE1;
CE_n <= 0;
end else if (cmd_code_int[2:1]==2'b10) begin
NxST <= S_RE;
CE_n <= 0;
end else if (cmd_code_int[2:1] ==2'b11) begin
NxST <= S_WE;
CE_n <= 0;
end else
NxST <= Init;
end
S_CLE:begin
CE_n <=0;
CLE <= 1;
WE_n <=0;
NxST <= S_CmdOut;
end
S_CmdOut:begin
CE_n <=0;
CLE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= S_WaitCmd;
end
S_WaitCmd:begin
CE_n <=0;
CLE <= 1;
WE_n <=0;
DOS <= 1;
NxST <= DoneCmd;
end
DoneCmd:begin
Done_i <=1;
CE_n <= 0;
CLE <= 1;
DOS <= 1;
NxST <= Finish;
end
Finish:begin
DIS <=1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_ALE:begin
CE_n <=0;
ALE <= 1;
WE_n <= 0;
NxST <= S_ADout;
end
S_ADout:begin
CE_n <= 0;
ALE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= WaitAd;
end
WaitAd:begin
CE_n <= 0;
ALE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= DoneAd;
end
DoneAd:begin
Done_i <= 1;
CE_n <= 0;
ALE <= 1;
DOS <= 1;
NxST <= Finish;
end
S_RE1:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR1;
end
WaitR1:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR2;
end
WaitR2:begin
CE_n <= 0;
RE_n <= 0;
NxST <= DoneR1;
end
DoneR1:begin
Done_i <= 1;
cnt_en <=1;
NxST <= Finish;
end
S_RE:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR1m;
end
WaitR1m:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR2m;
end
WaitR2m:begin
CE_n <= 0;
RE_n <= 0;
NxST <= S_DIS;
end
S_DIS:begin
CE_n <=0;
if (TC ==0)
NxST <= WaitR3m;
else
NxST <= FinishR;
end
WaitR3m:begin
CE_n <=0;
cnt_en <=1;
DIS <=1;
NxST <= S_RE;
end
FinishR:begin
Done_i <=1;
cnt_en <=1;
DIS <=1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_WE:begin
CE_n <=0;
WE_n <=0;
DOS <=1;
NxST <= WaitW;
end
WaitW:begin
ecc_en<=1'b1;
CE_n <=0;
WE_n <= 0;
DOS <= 1;
NxST <= WaitW1;
end
WaitW1:begin
CE_n <=0;
WE_n <=0;
DOS <=1;
NxST <= S_nWE;
end
S_nWE:begin
CE_n <=0;
DOS <= 1;
if (TC ==0)
NxST <= WaitW2;
else
NxST <= FinishW;
end
WaitW2:begin
CE_n <= 0;
DOS <= 1;
cnt_en <= 1;
NxST <= S_WE;
end
FinishW:begin
Done_i <= 1;
cnt_en <= 1;
DOS <= 1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
default:
NxST <= Init;
endcase
end
endmodule | module TFSM(
CLE ,
ALE ,
WE_n,
RE_n,
CE_n,
DOS ,
DIS ,
cnt_en,
TC3,
TC2048,
CLK,
RES,
start,
cmd_code,
ecc_en,
Done
); |
output reg CLE ;
output reg ALE ;
output reg WE_n;
output reg RE_n;
output reg CE_n;
output reg DOS ;
output reg DIS ;
output reg cnt_en;
input TC3 ;
input TC2048;
input CLK ;
input RES ;
input start;
input [2:0] cmd_code;
output reg Done;
output reg ecc_en;
parameter Init=0, S_Start=1, S_CE=2,
S_CLE=3, S_CmdOut=4, S_WaitCmd=5, DoneCmd=6, Finish=7,
S_ALE=8, S_ADout=9, WaitAd=10, DoneAd=11,
S_RE1=12, WaitR1=13, WaitR2=14, DoneR1=15,
S_RE=16, WaitR1m=17, WaitR2m=18, WaitR3m=19, S_DIS=20, FinishR=21,
S_WE=22, WaitW=23, WaitW1=24, WaitW2=25, S_nWE=26, FinishW=27;
reg [5:0] NxST, CrST;
reg Done_i;
wire TC;
reg [2:0] cmd_code_int;
assign TC = cmd_code_int[0]?TC2048:TC3;
always@(posedge CLK)
if (RES)
Done <=0;
else
Done <= Done_i;
always@(posedge CLK)
cmd_code_int <= cmd_code;
always@(posedge CLK)
CrST <= NxST;
always@(RES or TC or cmd_code_int or start or CrST)
if (RES) begin
NxST <= Init;
DIS <= 0;
DOS <= 0;
Done_i <=0;
ALE <= 0;
CLE <= 0;
WE_n <= 1;
RE_n <= 1;
CE_n <= 1;
cnt_en <=0;
ecc_en<=1'b0;
end else begin
DIS <= 0;
DOS <= 0;
Done_i <=0;
ALE <= 0;
CLE <= 0;
WE_n <= 1;
RE_n <= 1;
CE_n <= 1;
cnt_en <=0;
ecc_en<=1'b0;
case (CrST)
Init:begin
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_Start:begin
if (cmd_code_int==3'b011)
NxST <= Init;
else
NxST <= S_CE;
end
S_CE:begin
if (cmd_code_int==3'b000) begin
NxST <= S_CLE;
CE_n <= 0;
end else if (cmd_code_int ==3'b001) begin
NxST <= S_ALE;
CE_n <= 0;
end else if (cmd_code_int ==3'b010) begin
NxST <= S_RE1;
CE_n <= 0;
end else if (cmd_code_int[2:1]==2'b10) begin
NxST <= S_RE;
CE_n <= 0;
end else if (cmd_code_int[2:1] ==2'b11) begin
NxST <= S_WE;
CE_n <= 0;
end else
NxST <= Init;
end
S_CLE:begin
CE_n <=0;
CLE <= 1;
WE_n <=0;
NxST <= S_CmdOut;
end
S_CmdOut:begin
CE_n <=0;
CLE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= S_WaitCmd;
end
S_WaitCmd:begin
CE_n <=0;
CLE <= 1;
WE_n <=0;
DOS <= 1;
NxST <= DoneCmd;
end
DoneCmd:begin
Done_i <=1;
CE_n <= 0;
CLE <= 1;
DOS <= 1;
NxST <= Finish;
end
Finish:begin
DIS <=1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_ALE:begin
CE_n <=0;
ALE <= 1;
WE_n <= 0;
NxST <= S_ADout;
end
S_ADout:begin
CE_n <= 0;
ALE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= WaitAd;
end
WaitAd:begin
CE_n <= 0;
ALE <= 1;
WE_n <= 0;
DOS <= 1;
NxST <= DoneAd;
end
DoneAd:begin
Done_i <= 1;
CE_n <= 0;
ALE <= 1;
DOS <= 1;
NxST <= Finish;
end
S_RE1:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR1;
end
WaitR1:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR2;
end
WaitR2:begin
CE_n <= 0;
RE_n <= 0;
NxST <= DoneR1;
end
DoneR1:begin
Done_i <= 1;
cnt_en <=1;
NxST <= Finish;
end
S_RE:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR1m;
end
WaitR1m:begin
CE_n <= 0;
RE_n <= 0;
NxST <= WaitR2m;
end
WaitR2m:begin
CE_n <= 0;
RE_n <= 0;
NxST <= S_DIS;
end
S_DIS:begin
CE_n <=0;
if (TC ==0)
NxST <= WaitR3m;
else
NxST <= FinishR;
end
WaitR3m:begin
CE_n <=0;
cnt_en <=1;
DIS <=1;
NxST <= S_RE;
end
FinishR:begin
Done_i <=1;
cnt_en <=1;
DIS <=1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
S_WE:begin
CE_n <=0;
WE_n <=0;
DOS <=1;
NxST <= WaitW;
end
WaitW:begin
ecc_en<=1'b1;
CE_n <=0;
WE_n <= 0;
DOS <= 1;
NxST <= WaitW1;
end
WaitW1:begin
CE_n <=0;
WE_n <=0;
DOS <=1;
NxST <= S_nWE;
end
S_nWE:begin
CE_n <=0;
DOS <= 1;
if (TC ==0)
NxST <= WaitW2;
else
NxST <= FinishW;
end
WaitW2:begin
CE_n <= 0;
DOS <= 1;
cnt_en <= 1;
NxST <= S_WE;
end
FinishW:begin
Done_i <= 1;
cnt_en <= 1;
DOS <= 1;
if (start)
NxST <= S_Start;
else
NxST <= Init;
end
default:
NxST <= Init;
endcase
end
endmodule | 1 |
4,332 | data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2/ebr_buffer.v | 109,400,221 | ebr_buffer.v | v | 172 | 318 | [] | [] | [] | null | line:30: before: "." | null | 1: b"%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2/ebr_buffer.v:28: Cannot find file containing module: 'VHI'\n VHI scuba_vhi_inst (.Z(scuba_vhi));\n ^~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2,data/full_repos/permissive/109400221/VHI\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2,data/full_repos/permissive/109400221/VHI.v\n data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2,data/full_repos/permissive/109400221/VHI.sv\n VHI\n VHI.v\n VHI.sv\n obj_dir/VHI\n obj_dir/VHI.v\n obj_dir/VHI.sv\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2/ebr_buffer.v:74: Cannot find file containing module: 'DP8KC'\n DP8KC ebr_buffer_0_0_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), \n ^~~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2/ebr_buffer.v:95: Cannot find file containing module: 'VLO'\n VLO scuba_vlo_inst (.Z(scuba_vlo));\n ^~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/source/verilog/ipexpress/xo2/ebr_buffer.v:141: Cannot find file containing module: 'DP8KC'\n DP8KC ebr_buffer_0_1_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo), \n ^~~~~\n%Error: Exiting due to 4 error(s)\n" | 2,563 | module | module ebr_buffer (DataInA, DataInB, AddressA, AddressB, ClockA, ClockB,
ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB);
input wire [7:0] DataInA;
input wire [7:0] DataInB;
input wire [10:0] AddressA;
input wire [10:0] AddressB;
input wire ClockA;
input wire ClockB;
input wire ClockEnA;
input wire ClockEnB;
input wire WrA;
input wire WrB;
input wire ResetA;
input wire ResetB;
output wire [7:0] QA;
output wire [7:0] QB;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
defparam ebr_buffer_0_0_1.INIT_DATA = "STATIC" ;
defparam ebr_buffer_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ebr_buffer_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.CSDECODE_B = "0b000" ;
defparam ebr_buffer_0_0_1.CSDECODE_A = "0b000" ;
defparam ebr_buffer_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam ebr_buffer_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam ebr_buffer_0_0_1.GSR = "DISABLED" ;
defparam ebr_buffer_0_0_1.RESETMODE = "ASYNC" ;
defparam ebr_buffer_0_0_1.REGMODE_B = "OUTREG" ;
defparam ebr_buffer_0_0_1.REGMODE_A = "OUTREG" ;
defparam ebr_buffer_0_0_1.DATA_WIDTH_B = 4 ;
defparam ebr_buffer_0_0_1.DATA_WIDTH_A = 4 ;
DP8KC ebr_buffer_0_0_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[3]), .DIA2(DataInA[2]),
.DIA1(DataInA[1]), .DIA0(DataInA[0]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[3]),
.DIB2(DataInB[2]), .DIB1(DataInB[1]), .DIB0(DataInB[0]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[3]), .DOA2(QA[2]), .DOA1(QA[1]),
.DOA0(QA[0]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[3]),
.DOB2(QB[2]), .DOB1(QB[1]), .DOB0(QB[0]))
;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam ebr_buffer_0_1_0.INIT_DATA = "STATIC" ;
defparam ebr_buffer_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ebr_buffer_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.CSDECODE_B = "0b000" ;
defparam ebr_buffer_0_1_0.CSDECODE_A = "0b000" ;
defparam ebr_buffer_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam ebr_buffer_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam ebr_buffer_0_1_0.GSR = "DISABLED" ;
defparam ebr_buffer_0_1_0.RESETMODE = "ASYNC" ;
defparam ebr_buffer_0_1_0.REGMODE_B = "OUTREG" ;
defparam ebr_buffer_0_1_0.REGMODE_A = "OUTREG" ;
defparam ebr_buffer_0_1_0.DATA_WIDTH_B = 4 ;
defparam ebr_buffer_0_1_0.DATA_WIDTH_A = 4 ;
DP8KC ebr_buffer_0_1_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[7]), .DIA2(DataInA[6]),
.DIA1(DataInA[5]), .DIA0(DataInA[4]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[7]),
.DIB2(DataInB[6]), .DIB1(DataInB[5]), .DIB0(DataInB[4]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[7]), .DOA2(QA[6]), .DOA1(QA[5]),
.DOA0(QA[4]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[7]),
.DOB2(QB[6]), .DOB1(QB[5]), .DOB0(QB[4]))
;
endmodule | module ebr_buffer (DataInA, DataInB, AddressA, AddressB, ClockA, ClockB,
ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB); |
input wire [7:0] DataInA;
input wire [7:0] DataInB;
input wire [10:0] AddressA;
input wire [10:0] AddressB;
input wire ClockA;
input wire ClockB;
input wire ClockEnA;
input wire ClockEnB;
input wire WrA;
input wire WrB;
input wire ResetA;
input wire ResetB;
output wire [7:0] QA;
output wire [7:0] QB;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
defparam ebr_buffer_0_0_1.INIT_DATA = "STATIC" ;
defparam ebr_buffer_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ebr_buffer_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_0_1.CSDECODE_B = "0b000" ;
defparam ebr_buffer_0_0_1.CSDECODE_A = "0b000" ;
defparam ebr_buffer_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam ebr_buffer_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam ebr_buffer_0_0_1.GSR = "DISABLED" ;
defparam ebr_buffer_0_0_1.RESETMODE = "ASYNC" ;
defparam ebr_buffer_0_0_1.REGMODE_B = "OUTREG" ;
defparam ebr_buffer_0_0_1.REGMODE_A = "OUTREG" ;
defparam ebr_buffer_0_0_1.DATA_WIDTH_B = 4 ;
defparam ebr_buffer_0_0_1.DATA_WIDTH_A = 4 ;
DP8KC ebr_buffer_0_0_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[3]), .DIA2(DataInA[2]),
.DIA1(DataInA[1]), .DIA0(DataInA[0]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[3]),
.DIB2(DataInB[2]), .DIB1(DataInB[1]), .DIB0(DataInB[0]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[3]), .DOA2(QA[2]), .DOA1(QA[1]),
.DOA0(QA[0]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[3]),
.DOB2(QB[2]), .DOB1(QB[1]), .DOB0(QB[0]))
;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam ebr_buffer_0_1_0.INIT_DATA = "STATIC" ;
defparam ebr_buffer_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ebr_buffer_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ebr_buffer_0_1_0.CSDECODE_B = "0b000" ;
defparam ebr_buffer_0_1_0.CSDECODE_A = "0b000" ;
defparam ebr_buffer_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam ebr_buffer_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam ebr_buffer_0_1_0.GSR = "DISABLED" ;
defparam ebr_buffer_0_1_0.RESETMODE = "ASYNC" ;
defparam ebr_buffer_0_1_0.REGMODE_B = "OUTREG" ;
defparam ebr_buffer_0_1_0.REGMODE_A = "OUTREG" ;
defparam ebr_buffer_0_1_0.DATA_WIDTH_B = 4 ;
defparam ebr_buffer_0_1_0.DATA_WIDTH_A = 4 ;
DP8KC ebr_buffer_0_1_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[7]), .DIA2(DataInA[6]),
.DIA1(DataInA[5]), .DIA0(DataInA[4]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[7]),
.DIB2(DataInB[6]), .DIB1(DataInB[5]), .DIB0(DataInB[4]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[7]), .DOA2(QA[6]), .DOA1(QA[5]),
.DOA0(QA[4]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[7]),
.DOB2(QB[6]), .DOB1(QB[5]), .DOB0(QB[4]))
;
endmodule | 1 |
4,334 | data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v | 109,400,221 | nfcm_tb.v | v | 372 | 84 | [] | [] | [] | null | line:106: before: ";" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #(period/2) clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:194: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:199: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:201: Unsupported: wait statements\n wait(nfc_done);\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:202: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:214: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:220: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:223: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:225: Unsupported: wait statements\n wait(nfc_done);\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:226: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:249: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:255: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:260: syntax error, unexpected \'@\'\n @(posedge clk) ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n #3; \n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:267: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:269: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:271: Unsupported: wait statements\n wait(nfc_done);\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:272: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:296: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:297: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:304: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:307: syntax error, unexpected \'@\'\n @(posedge clk) ; \n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:308: Unsupported: wait statements\n wait(nfc_done);\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:309: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:314: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:332: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:333: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:338: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:339: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:341: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:342: Unsupported: wait statements\n wait(nfc_done);\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:343: syntax error, unexpected \'@\'\n @(posedge clk) ;\n ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:357: syntax error, unexpected \'@\'\n @(posedge clk); \n ^\n%Error: Exiting due to 27 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,566 | module | module nfcm_tb();
reg clk,rst;
wire [7:0] DIO;
wire CLE;
wire ALE;
wire WE_n;
wire RE_n;
wire CE_n;
wire R_nB;
reg BF_sel;
reg [10:0] BF_ad;
reg [7:0] BF_din;
reg BF_we;
reg [15:0] RWA;
wire [7:0] BF_dou;
wire PErr ;
wire EErr ;
wire RErr ;
reg [2:0] nfc_cmd;
reg nfc_strt;
wire nfc_done;
reg[7:0] memory[0:2047];
reg [7:0] temp;
GSR GSR_INST(.GSR(1'b1));
PUR PUR_INST(.PUR(1'b1));
parameter period=16;
initial begin
clk <= 1'b0;
rst <= 1'b1;
BF_sel<=1'b0;
BF_ad<=0;
BF_din<=0;
BF_we<=0;
RWA<=0;
nfc_cmd<=3'b111;
nfc_strt<=1'b0;
temp<=8'h24;
#300;
rst<=1'b0;
kill_time;
kill_time;
reset_cycle;
kill_time;
kill_time;
erase_cycle(16'h1234);
kill_time;
kill_time;
write_cycle(16'h1234);
kill_time;
kill_time;
read_cycle(16'h1234);
kill_time;
kill_time;
read_id_cycle(16'h0000);
kill_time;
kill_time;
#1000;
$stop;
end
always
#(period/2) clk <= ~clk;
nfcm_top nfcm(
.DIO(DIO),
.CLE(CLE),
.ALE(ALE),
.WE_n(WE_n),
.RE_n(RE_n),
.CE_n(CE_n),
.R_nB(R_nB),
.CLK(clk),
.RES(rst),
.BF_sel(BF_sel),
.BF_ad (BF_ad ),
.BF_din(BF_din),
.BF_we (BF_we ),
.RWA (RWA ),
.BF_dou(BF_dou),
.PErr(PErr),
.EErr(EErr),
.RErr(RErr),
.nfc_cmd (nfc_cmd ),
.nfc_strt(nfc_strt),
.nfc_done(nfc_done)
);
flash_interface nand_flash(
.DIO(DIO),
.CLE(CLE),
.ALE(ALE),
.WE_n(WE_n),
.RE_n(RE_n),
.CE_n(CE_n),
.R_nB(R_nB),
.rst(rst)
);
task reset_cycle;
begin
@(posedge clk) ;
nfc_cmd=3'b011;
nfc_strt=1'b1;
@(posedge clk) ;
nfc_strt=1'b0;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
$display($time," %m \t \t << reset function over >>");
end
endtask
task erase_cycle;
input [15:0] address;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b100;
nfc_strt=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
if(EErr)
$display($time," %m \t \t << erase error >>");
else
$display($time," %m \t \t << erase no error >>");
end
endtask
task write_cycle;
input [15:0] address;
integer i;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b001;
nfc_strt=1'b1;
BF_sel=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
BF_ad=0;
for(i=0;i<2048;i=i+1) begin
@(posedge clk) ;
#3;
BF_we=1'b1;
memory[i]=$random % 256;
BF_din<=memory[i];
BF_ad<=#3 i;
end
@(posedge clk) ;
@(posedge clk) ;
#3;
BF_we=1'b0;
wait(nfc_done);
@(posedge clk) ;
#3;
nfc_cmd=3'b111;
BF_sel=1'b0;
if(PErr)
$display($time," %m \t \t << Writing error >>");
else
$display($time," %m \t \t << Writing no error >>");
end
endtask
task read_cycle;
input [15:0] address;
integer i;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b010;
nfc_strt=1'b1;
BF_sel=1'b1;
BF_we=1'b0;
BF_ad=#3 0;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
#3;
nfc_cmd=3'b111;
BF_ad<=#3 BF_ad+1;
for(i=0;i<2048;i=i+1) begin
@(posedge clk) ;
temp<=memory[i];
BF_ad<=#3 BF_ad+1;
end
if(RErr)
$display($time," %m \t \t << ecc error >>");
else
$display($time," %m \t \t << ecc no error >>");
end
endtask
task read_id_cycle;
input [15:0] address;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b101;
nfc_strt=1'b1;
BF_sel=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
$display($time," %m \t \t << read id function over >>");
end
endtask
task kill_time;
begin
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask
endmodule | module nfcm_tb(); |
reg clk,rst;
wire [7:0] DIO;
wire CLE;
wire ALE;
wire WE_n;
wire RE_n;
wire CE_n;
wire R_nB;
reg BF_sel;
reg [10:0] BF_ad;
reg [7:0] BF_din;
reg BF_we;
reg [15:0] RWA;
wire [7:0] BF_dou;
wire PErr ;
wire EErr ;
wire RErr ;
reg [2:0] nfc_cmd;
reg nfc_strt;
wire nfc_done;
reg[7:0] memory[0:2047];
reg [7:0] temp;
GSR GSR_INST(.GSR(1'b1));
PUR PUR_INST(.PUR(1'b1));
parameter period=16;
initial begin
clk <= 1'b0;
rst <= 1'b1;
BF_sel<=1'b0;
BF_ad<=0;
BF_din<=0;
BF_we<=0;
RWA<=0;
nfc_cmd<=3'b111;
nfc_strt<=1'b0;
temp<=8'h24;
#300;
rst<=1'b0;
kill_time;
kill_time;
reset_cycle;
kill_time;
kill_time;
erase_cycle(16'h1234);
kill_time;
kill_time;
write_cycle(16'h1234);
kill_time;
kill_time;
read_cycle(16'h1234);
kill_time;
kill_time;
read_id_cycle(16'h0000);
kill_time;
kill_time;
#1000;
$stop;
end
always
#(period/2) clk <= ~clk;
nfcm_top nfcm(
.DIO(DIO),
.CLE(CLE),
.ALE(ALE),
.WE_n(WE_n),
.RE_n(RE_n),
.CE_n(CE_n),
.R_nB(R_nB),
.CLK(clk),
.RES(rst),
.BF_sel(BF_sel),
.BF_ad (BF_ad ),
.BF_din(BF_din),
.BF_we (BF_we ),
.RWA (RWA ),
.BF_dou(BF_dou),
.PErr(PErr),
.EErr(EErr),
.RErr(RErr),
.nfc_cmd (nfc_cmd ),
.nfc_strt(nfc_strt),
.nfc_done(nfc_done)
);
flash_interface nand_flash(
.DIO(DIO),
.CLE(CLE),
.ALE(ALE),
.WE_n(WE_n),
.RE_n(RE_n),
.CE_n(CE_n),
.R_nB(R_nB),
.rst(rst)
);
task reset_cycle;
begin
@(posedge clk) ;
nfc_cmd=3'b011;
nfc_strt=1'b1;
@(posedge clk) ;
nfc_strt=1'b0;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
$display($time," %m \t \t << reset function over >>");
end
endtask
task erase_cycle;
input [15:0] address;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b100;
nfc_strt=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
if(EErr)
$display($time," %m \t \t << erase error >>");
else
$display($time," %m \t \t << erase no error >>");
end
endtask
task write_cycle;
input [15:0] address;
integer i;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b001;
nfc_strt=1'b1;
BF_sel=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
BF_ad=0;
for(i=0;i<2048;i=i+1) begin
@(posedge clk) ;
#3;
BF_we=1'b1;
memory[i]=$random % 256;
BF_din<=memory[i];
BF_ad<=#3 i;
end
@(posedge clk) ;
@(posedge clk) ;
#3;
BF_we=1'b0;
wait(nfc_done);
@(posedge clk) ;
#3;
nfc_cmd=3'b111;
BF_sel=1'b0;
if(PErr)
$display($time," %m \t \t << Writing error >>");
else
$display($time," %m \t \t << Writing no error >>");
end
endtask
task read_cycle;
input [15:0] address;
integer i;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b010;
nfc_strt=1'b1;
BF_sel=1'b1;
BF_we=1'b0;
BF_ad=#3 0;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
#3;
nfc_cmd=3'b111;
BF_ad<=#3 BF_ad+1;
for(i=0;i<2048;i=i+1) begin
@(posedge clk) ;
temp<=memory[i];
BF_ad<=#3 BF_ad+1;
end
if(RErr)
$display($time," %m \t \t << ecc error >>");
else
$display($time," %m \t \t << ecc no error >>");
end
endtask
task read_id_cycle;
input [15:0] address;
begin
@(posedge clk) ;
#3;
RWA=address;
nfc_cmd=3'b101;
nfc_strt=1'b1;
BF_sel=1'b1;
@(posedge clk) ;
#3;
nfc_strt=1'b0;
@(posedge clk) ;
wait(nfc_done);
@(posedge clk) ;
nfc_cmd=3'b111;
$display($time," %m \t \t << read id function over >>");
end
endtask
task kill_time;
begin
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask
endmodule | 1 |
4,335 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_pre.v | 109,400,221 | versatile_fifo_dptam_dw_pre.v | v | 89 | 75 | [] | [] | [] | [(5, 88)] | null | data/verilator_xmls/7796188d-0f57-4fb9-b39a-966e4f608dd0.xml | null | 2,568 | module | module versatile_fifo_dptam_dw(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
input [7:0] d_a;
output [7:0] q_a;
input [10:0] adr_a;
input we_a;
input clk_a;
output [7:0] q_b;
input [10:0] adr_b;
input [7:0] d_b;
input we_b;
input clk_b;
endmodule | module versatile_fifo_dptam_dw(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
); |
input [7:0] d_a;
output [7:0] q_a;
input [10:0] adr_a;
input we_a;
input clk_a;
output [7:0] q_b;
input [10:0] adr_b;
input [7:0] d_b;
input we_b;
input clk_b;
endmodule | 1 |
4,336 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v | 109,400,221 | versatile_fifo_dptam_dw_sim.v | v | 174 | 73 | [] | [] | [] | [(5, 173)] | null | null | 1: b"%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:58: Cannot find file containing module: 'INV'\n INV we_b_RNIB08 (.A(we_b), .Y(we_b_i));\n ^~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw,data/full_repos/permissive/109400221/INV\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw,data/full_repos/permissive/109400221/INV.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw,data/full_repos/permissive/109400221/INV.sv\n INV\n INV.v\n INV.sv\n obj_dir/INV\n obj_dir/INV.v\n obj_dir/INV.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:59: Cannot find file containing module: 'VCC'\n VCC VCC_i_0 (.Y(VCC_net_1));\n ^~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:60: Cannot find file containing module: 'RAM4K9'\n RAM4K9 ram_tile_0_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(\n ^~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:87: Cannot find file containing module: 'INV'\n INV we_a_RNIA08 (.A(we_a), .Y(we_a_i));\n ^~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:88: Cannot find file containing module: 'GND'\n GND GND_i_0 (.Y(GND_net_1));\n ^~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:89: Cannot find file containing module: 'RAM4K9'\n RAM4K9 ram_tile_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(\n ^~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:116: Cannot find file containing module: 'VCC'\n VCC VCC_i (.Y(VCC));\n ^~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:117: Cannot find file containing module: 'RAM4K9'\n RAM4K9 ram_tile_2_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(\n ^~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:144: Cannot find file containing module: 'RAM4K9'\n RAM4K9 ram_tile_1_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(\n ^~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v:171: Cannot find file containing module: 'GND'\n GND GND_i (.Y(GND));\n ^~~\n%Error: Exiting due to 10 error(s)\n" | 2,569 | module | module versatile_fifo_dptam_dw(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
input [7:0] d_a;
output [7:0] q_a;
input [10:0] adr_a;
input we_a;
input clk_a;
output [7:0] q_b;
input [10:0] adr_b;
input [7:0] d_b;
input we_b;
input clk_b;
wire VCC, GND, \ram_tile_2.DOUT0_SIG[2] ,
\ram_tile_2.DOUT0_SIG[3] , \ram_tile_2.DOUT0_SIG[4] ,
\ram_tile_2.DOUT0_SIG[5] , \ram_tile_2.DOUT0_SIG[6] ,
\ram_tile_2.DOUT0_SIG[7] , \ram_tile_2.DOUT0_SIG[8] ,
\ram_tile_2.DOUT1_SIG[2] , \ram_tile_2.DOUT1_SIG[3] ,
\ram_tile_2.DOUT1_SIG[4] , \ram_tile_2.DOUT1_SIG[5] ,
\ram_tile_2.DOUT1_SIG[6] , \ram_tile_2.DOUT1_SIG[7] ,
\ram_tile_2.DOUT1_SIG[8] , \ram_tile_1.DOUT0_SIG[2] ,
\ram_tile_1.DOUT0_SIG[3] , \ram_tile_1.DOUT0_SIG[4] ,
\ram_tile_1.DOUT0_SIG[5] , \ram_tile_1.DOUT0_SIG[6] ,
\ram_tile_1.DOUT0_SIG[7] , \ram_tile_1.DOUT0_SIG[8] ,
\ram_tile_1.DOUT1_SIG[2] , \ram_tile_1.DOUT1_SIG[3] ,
\ram_tile_1.DOUT1_SIG[4] , \ram_tile_1.DOUT1_SIG[5] ,
\ram_tile_1.DOUT1_SIG[6] , \ram_tile_1.DOUT1_SIG[7] ,
\ram_tile_1.DOUT1_SIG[8] , \ram_tile_0.DOUT0_SIG[2] ,
\ram_tile_0.DOUT0_SIG[3] , \ram_tile_0.DOUT0_SIG[4] ,
\ram_tile_0.DOUT0_SIG[5] , \ram_tile_0.DOUT0_SIG[6] ,
\ram_tile_0.DOUT0_SIG[7] , \ram_tile_0.DOUT0_SIG[8] ,
\ram_tile_0.DOUT1_SIG[2] , \ram_tile_0.DOUT1_SIG[3] ,
\ram_tile_0.DOUT1_SIG[4] , \ram_tile_0.DOUT1_SIG[5] ,
\ram_tile_0.DOUT1_SIG[6] , \ram_tile_0.DOUT1_SIG[7] ,
\ram_tile_0.DOUT1_SIG[8] , \ram_tile.DOUT0_SIG[2] ,
\ram_tile.DOUT0_SIG[3] , \ram_tile.DOUT0_SIG[4] ,
\ram_tile.DOUT0_SIG[5] , \ram_tile.DOUT0_SIG[6] ,
\ram_tile.DOUT0_SIG[7] , \ram_tile.DOUT0_SIG[8] ,
\ram_tile.DOUT1_SIG[2] , \ram_tile.DOUT1_SIG[3] ,
\ram_tile.DOUT1_SIG[4] , \ram_tile.DOUT1_SIG[5] ,
\ram_tile.DOUT1_SIG[6] , \ram_tile.DOUT1_SIG[7] ,
\ram_tile.DOUT1_SIG[8] , we_b_i, we_a_i, GND_net_1, VCC_net_1;
INV we_b_RNIB08 (.A(we_b), .Y(we_b_i));
VCC VCC_i_0 (.Y(VCC_net_1));
RAM4K9 ram_tile_0_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[3]), .DINA0(
d_b[2]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[3]), .DINB0(
d_a[2]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_0.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_0.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_0.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_0.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_0.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_0.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_0.DOUT0_SIG[2] ), .DOUTA1(q_b[3]), .DOUTA0(q_b[2]),
.DOUTB8(\ram_tile_0.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_0.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_0.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_0.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_0.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_0.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_0.DOUT1_SIG[2] ), .DOUTB1(q_a[3]), .DOUTB0(
q_a[2]));
INV we_a_RNIA08 (.A(we_a), .Y(we_a_i));
GND GND_i_0 (.Y(GND_net_1));
RAM4K9 ram_tile_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[1]), .DINA0(
d_b[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[1]), .DINB0(
d_a[0]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile.DOUT0_SIG[8] ), .DOUTA7(\ram_tile.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile.DOUT0_SIG[5] ), .DOUTA4(\ram_tile.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile.DOUT0_SIG[2] ), .DOUTA1(q_b[1]), .DOUTA0(q_b[0]),
.DOUTB8(\ram_tile.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile.DOUT1_SIG[7] ), .DOUTB6(\ram_tile.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile.DOUT1_SIG[4] ), .DOUTB3(\ram_tile.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile.DOUT1_SIG[2] ), .DOUTB1(q_a[1]), .DOUTB0(
q_a[0]));
VCC VCC_i (.Y(VCC));
RAM4K9 ram_tile_2_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[7]), .DINA0(
d_b[6]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[7]), .DINB0(
d_a[6]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_2.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_2.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_2.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_2.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_2.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_2.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_2.DOUT0_SIG[2] ), .DOUTA1(q_b[7]), .DOUTA0(q_b[6]),
.DOUTB8(\ram_tile_2.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_2.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_2.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_2.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_2.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_2.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_2.DOUT1_SIG[2] ), .DOUTB1(q_a[7]), .DOUTB0(
q_a[6]));
RAM4K9 ram_tile_1_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[5]), .DINA0(
d_b[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[5]), .DINB0(
d_a[4]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_1.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_1.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_1.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_1.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_1.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_1.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_1.DOUT0_SIG[2] ), .DOUTA1(q_b[5]), .DOUTA0(q_b[4]),
.DOUTB8(\ram_tile_1.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_1.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_1.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_1.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_1.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_1.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_1.DOUT1_SIG[2] ), .DOUTB1(q_a[5]), .DOUTB0(
q_a[4]));
GND GND_i (.Y(GND));
endmodule | module versatile_fifo_dptam_dw(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
); |
input [7:0] d_a;
output [7:0] q_a;
input [10:0] adr_a;
input we_a;
input clk_a;
output [7:0] q_b;
input [10:0] adr_b;
input [7:0] d_b;
input we_b;
input clk_b;
wire VCC, GND, \ram_tile_2.DOUT0_SIG[2] ,
\ram_tile_2.DOUT0_SIG[3] , \ram_tile_2.DOUT0_SIG[4] ,
\ram_tile_2.DOUT0_SIG[5] , \ram_tile_2.DOUT0_SIG[6] ,
\ram_tile_2.DOUT0_SIG[7] , \ram_tile_2.DOUT0_SIG[8] ,
\ram_tile_2.DOUT1_SIG[2] , \ram_tile_2.DOUT1_SIG[3] ,
\ram_tile_2.DOUT1_SIG[4] , \ram_tile_2.DOUT1_SIG[5] ,
\ram_tile_2.DOUT1_SIG[6] , \ram_tile_2.DOUT1_SIG[7] ,
\ram_tile_2.DOUT1_SIG[8] , \ram_tile_1.DOUT0_SIG[2] ,
\ram_tile_1.DOUT0_SIG[3] , \ram_tile_1.DOUT0_SIG[4] ,
\ram_tile_1.DOUT0_SIG[5] , \ram_tile_1.DOUT0_SIG[6] ,
\ram_tile_1.DOUT0_SIG[7] , \ram_tile_1.DOUT0_SIG[8] ,
\ram_tile_1.DOUT1_SIG[2] , \ram_tile_1.DOUT1_SIG[3] ,
\ram_tile_1.DOUT1_SIG[4] , \ram_tile_1.DOUT1_SIG[5] ,
\ram_tile_1.DOUT1_SIG[6] , \ram_tile_1.DOUT1_SIG[7] ,
\ram_tile_1.DOUT1_SIG[8] , \ram_tile_0.DOUT0_SIG[2] ,
\ram_tile_0.DOUT0_SIG[3] , \ram_tile_0.DOUT0_SIG[4] ,
\ram_tile_0.DOUT0_SIG[5] , \ram_tile_0.DOUT0_SIG[6] ,
\ram_tile_0.DOUT0_SIG[7] , \ram_tile_0.DOUT0_SIG[8] ,
\ram_tile_0.DOUT1_SIG[2] , \ram_tile_0.DOUT1_SIG[3] ,
\ram_tile_0.DOUT1_SIG[4] , \ram_tile_0.DOUT1_SIG[5] ,
\ram_tile_0.DOUT1_SIG[6] , \ram_tile_0.DOUT1_SIG[7] ,
\ram_tile_0.DOUT1_SIG[8] , \ram_tile.DOUT0_SIG[2] ,
\ram_tile.DOUT0_SIG[3] , \ram_tile.DOUT0_SIG[4] ,
\ram_tile.DOUT0_SIG[5] , \ram_tile.DOUT0_SIG[6] ,
\ram_tile.DOUT0_SIG[7] , \ram_tile.DOUT0_SIG[8] ,
\ram_tile.DOUT1_SIG[2] , \ram_tile.DOUT1_SIG[3] ,
\ram_tile.DOUT1_SIG[4] , \ram_tile.DOUT1_SIG[5] ,
\ram_tile.DOUT1_SIG[6] , \ram_tile.DOUT1_SIG[7] ,
\ram_tile.DOUT1_SIG[8] , we_b_i, we_a_i, GND_net_1, VCC_net_1;
INV we_b_RNIB08 (.A(we_b), .Y(we_b_i));
VCC VCC_i_0 (.Y(VCC_net_1));
RAM4K9 ram_tile_0_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[3]), .DINA0(
d_b[2]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[3]), .DINB0(
d_a[2]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_0.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_0.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_0.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_0.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_0.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_0.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_0.DOUT0_SIG[2] ), .DOUTA1(q_b[3]), .DOUTA0(q_b[2]),
.DOUTB8(\ram_tile_0.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_0.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_0.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_0.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_0.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_0.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_0.DOUT1_SIG[2] ), .DOUTB1(q_a[3]), .DOUTB0(
q_a[2]));
INV we_a_RNIA08 (.A(we_a), .Y(we_a_i));
GND GND_i_0 (.Y(GND_net_1));
RAM4K9 ram_tile_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[1]), .DINA0(
d_b[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[1]), .DINB0(
d_a[0]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile.DOUT0_SIG[8] ), .DOUTA7(\ram_tile.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile.DOUT0_SIG[5] ), .DOUTA4(\ram_tile.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile.DOUT0_SIG[2] ), .DOUTA1(q_b[1]), .DOUTA0(q_b[0]),
.DOUTB8(\ram_tile.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile.DOUT1_SIG[7] ), .DOUTB6(\ram_tile.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile.DOUT1_SIG[4] ), .DOUTB3(\ram_tile.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile.DOUT1_SIG[2] ), .DOUTB1(q_a[1]), .DOUTB0(
q_a[0]));
VCC VCC_i (.Y(VCC));
RAM4K9 ram_tile_2_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[7]), .DINA0(
d_b[6]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[7]), .DINB0(
d_a[6]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_2.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_2.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_2.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_2.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_2.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_2.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_2.DOUT0_SIG[2] ), .DOUTA1(q_b[7]), .DOUTA0(q_b[6]),
.DOUTB8(\ram_tile_2.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_2.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_2.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_2.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_2.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_2.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_2.DOUT1_SIG[2] ), .DOUTB1(q_a[7]), .DOUTB0(
q_a[6]));
RAM4K9 ram_tile_1_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9(
adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6(
adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3(
adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0(
adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9(
adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6(
adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3(
adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0(
adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[5]), .DINA0(
d_b[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[5]), .DINB0(
d_a[4]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1(
GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND),
.BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA(
clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8(
\ram_tile_1.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_1.DOUT0_SIG[7] ),
.DOUTA6(\ram_tile_1.DOUT0_SIG[6] ), .DOUTA5(
\ram_tile_1.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_1.DOUT0_SIG[4] ),
.DOUTA3(\ram_tile_1.DOUT0_SIG[3] ), .DOUTA2(
\ram_tile_1.DOUT0_SIG[2] ), .DOUTA1(q_b[5]), .DOUTA0(q_b[4]),
.DOUTB8(\ram_tile_1.DOUT1_SIG[8] ), .DOUTB7(
\ram_tile_1.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_1.DOUT1_SIG[6] ),
.DOUTB5(\ram_tile_1.DOUT1_SIG[5] ), .DOUTB4(
\ram_tile_1.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_1.DOUT1_SIG[3] ),
.DOUTB2(\ram_tile_1.DOUT1_SIG[2] ), .DOUTB1(q_a[5]), .DOUTB0(
q_a[4]));
GND GND_i (.Y(GND));
endmodule | 1 |
4,344 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v | 109,400,221 | sd_fifo_tx_filler.v | v | 127 | 68 | [] | [] | [] | [(91, 212)] | null | null | 1: b'%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v:1: Cannot find include file: sd_defines.v\n`include "sd_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v.sv\n sd_defines.v\n sd_defines.v.v\n sd_defines.v.sv\n obj_dir/sd_defines.v\n obj_dir/sd_defines.v.v\n obj_dir/sd_defines.v.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v:98: Define or directive not defined: \'`MEM_OFFSET\'\n offset<=offset+`MEM_OFFSET; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n offset<=offset+`MEM_OFFSET; \n ^\n%Error: Exiting due to 3 error(s)\n' | 2,591 | module | module sd_fifo_tx_filler
(
input clk,
input rst,
output [31:0] m_wb_adr_o,
output reg m_wb_we_o,
input [31:0] m_wb_dat_i,
output reg m_wb_cyc_o,
output reg m_wb_stb_o,
input m_wb_ack_i,
output reg [2:0] m_wb_cti_o,
output reg [1:0] m_wb_bte_o,
input en,
input [31:0] adr,
input sd_clk,
output [31:0] dat_o,
input rd,
output empty,
output fe
);
reg reset_tx_fifo;
reg [31:0] din;
reg wr_tx;
reg [8:0] we;
reg [8:0] offset;
wire [5:0]mem_empt;
sd_tx_fifo Tx_Fifo (
.d ( din ),
.wr ( wr_tx ),
.wclk (clk),
.q ( dat_o),
.rd (rd),
.full (fe),
.empty (empty),
.mem_empt (mem_empt),
.rclk (sd_clk),
.rst (rst | reset_tx_fifo)
);
assign m_wb_adr_o = adr+offset;
reg first;
reg ackd;
reg delay;
always @(posedge clk or posedge rst )begin
if (rst) begin
offset <=0;
we <= 8'h1;
m_wb_we_o <=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
wr_tx<=0;
ackd <=1;
delay<=0;
reset_tx_fifo<=1;
first<=1;
din<=0;
m_wb_bte_o <= 2'b00;
m_wb_cti_o <= 3'b000;
end
else if (en) begin
reset_tx_fifo<=0;
if (m_wb_ack_i) begin
wr_tx <=1;
din <=m_wb_dat_i;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
delay<=~ delay;
end
else begin
wr_tx <=0;
end
if (delay)begin
offset<=offset+`MEM_OFFSET;
ackd<=~ackd;
delay<=~ delay;
wr_tx <=0;
end
if ( !m_wb_ack_i & !fe & ackd ) begin
m_wb_we_o <=0;
m_wb_cyc_o <= 1;
m_wb_stb_o <= 1;
ackd<=0;
end
end
else begin
offset <=0;
reset_tx_fifo<=1;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
m_wb_we_o <=0;
end
end
endmodule | module sd_fifo_tx_filler
(
input clk,
input rst,
output [31:0] m_wb_adr_o,
output reg m_wb_we_o,
input [31:0] m_wb_dat_i,
output reg m_wb_cyc_o,
output reg m_wb_stb_o,
input m_wb_ack_i,
output reg [2:0] m_wb_cti_o,
output reg [1:0] m_wb_bte_o,
input en,
input [31:0] adr,
input sd_clk,
output [31:0] dat_o,
input rd,
output empty,
output fe
); |
reg reset_tx_fifo;
reg [31:0] din;
reg wr_tx;
reg [8:0] we;
reg [8:0] offset;
wire [5:0]mem_empt;
sd_tx_fifo Tx_Fifo (
.d ( din ),
.wr ( wr_tx ),
.wclk (clk),
.q ( dat_o),
.rd (rd),
.full (fe),
.empty (empty),
.mem_empt (mem_empt),
.rclk (sd_clk),
.rst (rst | reset_tx_fifo)
);
assign m_wb_adr_o = adr+offset;
reg first;
reg ackd;
reg delay;
always @(posedge clk or posedge rst )begin
if (rst) begin
offset <=0;
we <= 8'h1;
m_wb_we_o <=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
wr_tx<=0;
ackd <=1;
delay<=0;
reset_tx_fifo<=1;
first<=1;
din<=0;
m_wb_bte_o <= 2'b00;
m_wb_cti_o <= 3'b000;
end
else if (en) begin
reset_tx_fifo<=0;
if (m_wb_ack_i) begin
wr_tx <=1;
din <=m_wb_dat_i;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
delay<=~ delay;
end
else begin
wr_tx <=0;
end
if (delay)begin
offset<=offset+`MEM_OFFSET;
ackd<=~ackd;
delay<=~ delay;
wr_tx <=0;
end
if ( !m_wb_ack_i & !fe & ackd ) begin
m_wb_we_o <=0;
m_wb_cyc_o <= 1;
m_wb_stb_o <= 1;
ackd<=0;
end
end
else begin
offset <=0;
reset_tx_fifo<=1;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
m_wb_we_o <=0;
end
end
endmodule | 1 |
4,345 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v | 109,400,221 | sd_rx_fifo.v | v | 122 | 160 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:1: Cannot find include file: sd_defines.v\n`include "sd_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/sd_defines.v.sv\n sd_defines.v\n sd_defines.v.v\n sd_defines.v.sv\n obj_dir/sd_defines.v\n obj_dir/sd_defines.v.v\n obj_dir/sd_defines.v.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:2: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:16: Define or directive not defined: \'`FIFO_RX_MEM_DEPTH\'\n reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1]; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:17: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:83: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:86: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_i <= `FIFO_RX_MEM_ADR_SIZE\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:89: Define or directive not defined: \'`FIFO_RX_MEM_DEPTH\'\n if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:90: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0; \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:91: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:91: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:94: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE\'h1;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:98: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_o <= `FIFO_RX_MEM_ADR_SIZE\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:102: Define or directive not defined: \'`FIFO_RX_MEM_DEPTH\'\n if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:103: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:104: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:104: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:107: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE\'h1;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:116: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:116: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:116: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:116: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_rx_fifo.v:120: Define or directive not defined: \'`FIFO_RX_MEM_ADR_SIZE\'\n assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n' | 2,592 | module | module sd_rx_fifo
(
input [4-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [1:0] mem_empt,
input rclk,
input rst
);
reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1];
reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
reg [8-1:0] we;
reg [4*(8)-1:0] tmp;
reg ft;
always @ (posedge wclk or posedge rst)
if (rst)
we <= 8'h1;
else
if (wr)
we <= {we[8-2:0],we[8-1]};
always @ (posedge wclk or posedge rst)
if (rst) begin
tmp <= {4*(8-1){1'b0}};
ft<=0;
end
else
begin
`ifdef BIG_ENDIAN
if (wr & we[7]) begin
tmp[4*1-1:4*0] <= d;
ft<=1; end
if (wr & we[6])
tmp[4*2-1:4*1] <= d;
if (wr & we[5])
tmp[4*3-1:4*2] <= d;
if (wr & we[4])
tmp[4*4-1:4*3] <= d;
if (wr & we[3])
tmp[4*5-1:4*4] <= d;
if (wr & we[2])
tmp[4*6-1:4*5] <= d;
if (wr & we[1])
tmp[4*7-1:4*6] <= d;
if (wr & we[0])
tmp[4*8-1:4*7] <= d;
`endif
`ifdef LITTLE_ENDIAN
if (wr & we[0])
tmp[4*1-1:4*0] <= d;
if (wr & we[1])
tmp[4*2-1:4*1] <= d;
if (wr & we[2])
tmp[4*3-1:4*2] <= d;
if (wr & we[3])
tmp[4*4-1:4*3] <= d;
if (wr & we[4])
tmp[4*5-1:4*4] <= d;
if (wr & we[5])
tmp[4*6-1:4*5] <= d;
if (wr & we[6])
tmp[4*7-1:4*6] <= d;
if (wr & we[7]) begin
tmp[4*8-1:4*7] <= d;
ft<=1;
end
`endif
end
assign ram_we = wr & we[0] &ft;
assign ram_din = tmp;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (!empty & rd)
if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
endmodule | module sd_rx_fifo
(
input [4-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [1:0] mem_empt,
input rclk,
input rst
); |
reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1];
reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
reg [8-1:0] we;
reg [4*(8)-1:0] tmp;
reg ft;
always @ (posedge wclk or posedge rst)
if (rst)
we <= 8'h1;
else
if (wr)
we <= {we[8-2:0],we[8-1]};
always @ (posedge wclk or posedge rst)
if (rst) begin
tmp <= {4*(8-1){1'b0}};
ft<=0;
end
else
begin
`ifdef BIG_ENDIAN
if (wr & we[7]) begin
tmp[4*1-1:4*0] <= d;
ft<=1; end
if (wr & we[6])
tmp[4*2-1:4*1] <= d;
if (wr & we[5])
tmp[4*3-1:4*2] <= d;
if (wr & we[4])
tmp[4*4-1:4*3] <= d;
if (wr & we[3])
tmp[4*5-1:4*4] <= d;
if (wr & we[2])
tmp[4*6-1:4*5] <= d;
if (wr & we[1])
tmp[4*7-1:4*6] <= d;
if (wr & we[0])
tmp[4*8-1:4*7] <= d;
`endif
`ifdef LITTLE_ENDIAN
if (wr & we[0])
tmp[4*1-1:4*0] <= d;
if (wr & we[1])
tmp[4*2-1:4*1] <= d;
if (wr & we[2])
tmp[4*3-1:4*2] <= d;
if (wr & we[3])
tmp[4*4-1:4*3] <= d;
if (wr & we[4])
tmp[4*5-1:4*4] <= d;
if (wr & we[5])
tmp[4*6-1:4*5] <= d;
if (wr & we[6])
tmp[4*7-1:4*6] <= d;
if (wr & we[7]) begin
tmp[4*8-1:4*7] <= d;
ft<=1;
end
`endif
end
assign ram_we = wr & we[0] &ft;
assign ram_din = tmp;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (!empty & rd)
if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
endmodule | 1 |
4,347 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v | 109,400,221 | sd_tx_fifo.v | v | 73 | 161 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:2: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:3: Cannot find include file: sd_defines.v\n`include "sd_defines.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:18: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1]; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:19: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:30: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:34: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_i <= `FIFO_TX_MEM_ADR_SIZE\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:37: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:38: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0; \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:39: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:39: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:42: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE\'h1;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:47: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_o <= `FIFO_TX_MEM_ADR_SIZE\'h0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:51: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:52: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:53: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:53: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:56: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE\'h1;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:70: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n' | 2,594 | module | module sd_tx_fifo
(
input [32-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [5:0] mem_empt,
input rclk,
input rst
);
reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];
reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
assign ram_we = wr & ~full;
assign ram_din = d;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (!empty & rd) begin
if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
end
assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
endmodule | module sd_tx_fifo
(
input [32-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [5:0] mem_empt,
input rclk,
input rst
); |
reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];
reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
assign ram_we = wr & ~full;
assign ram_din = d;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (!empty & rd) begin
if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
end
assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
endmodule | 1 |
4,359 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_counter.v | 109,400,221 | sd_counter.v | v | 185 | 57 | [] | [] | [] | [(43, 184)] | null | data/verilator_xmls/800a0fdb-9c35-48b4-a671-aeeb938c8135.xml | null | 2,599 | module | module sd_counter
(
`ifdef CNT_TYPE_GRAY
output reg [`CNT_LENGTH:1] q,
`ifdef CNT_Q_BIN
output [`CNT_LENGTH:1] q_bin,
`endif
`else
`ifdef CNT_Q
output [`CNT_LENGTH:1] q,
`endif
`endif
`ifdef CNT_CLEAR
input clear,
`endif
`ifdef CNT_SET
input set,
`endif
`ifdef CNT_REW
input rew,
`endif
`ifdef CNT_CE
input cke,
`endif
`ifdef CNT_QNEXT
output [`CNT_LENGTH:1] q_next,
`endif
`ifdef CNT_Z
output z,
`endif
`ifdef CNT_ZQ
output reg zq,
`endif
input clk,
input rst
);
`ifdef CNT_SET
parameter set_value = `CNT_SET_VALUE;
`endif
`ifdef CNT_WRAP
parameter wrap_value = `CNT_WRAP_VALUE;
`endif
reg [`CNT_LENGTH:1] qi;
`ifdef CNT_QNEXT
`else
wire [`CNT_LENGTH:1] q_next;
`endif
`ifdef CNT_REW
wire [`CNT_LENGTH:1] q_next_fw;
wire [`CNT_LENGTH:1] q_next_rew;
`endif
`ifdef CNT_REW
`else
assign q_next =
`endif
`ifdef CNT_REW
assign q_next_fw =
`endif
`ifdef CNT_CLEAR
clear ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_SET
set ? set_value :
`endif
`ifdef CNT_WRAP
(qi == wrap_value) ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_TYPE_LFSR
{qi[8:1],~(q[`LFSR_LENGTH]^q[1])};
`else
qi + `CNT_LENGTH'd1;
`endif
`ifdef CNT_REW
assign q_next_rew =
`ifdef CNT_CLEAR
clear ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_SET
set ? set_value :
`endif
`ifdef CNT_WRAP
(qi == `CNT_LENGTH'd0) ? wrap_value :
`endif
`ifdef CNT_TYPE_LFSR
{~(q[1]^q[2]),qi[`CNT_LENGTH:2]};
`else
qi - `CNT_LENGTH'd1;
`endif
`endif
`ifdef CNT_REW
assign q_next = rew ? q_next_rew : q_next_fw;
`endif
always @ (posedge clk or posedge rst)
if (rst)
qi <= `CNT_LENGTH'd0;
else
`ifdef CNT_CE
if (cke)
`endif
qi <= q_next;
`ifdef CNT_Q
`ifdef CNT_TYPE_GRAY
always @ (posedge clk or posedge rst)
if (rst)
q <= `CNT_LENGTH'd0;
else
`ifdef CNT_CE
if (cke)
`endif
q <= (q_next>>1) ^ q_next;
`ifdef CNT_Q_BIN
assign q_bin = qi;
`endif
`else
assign q = q_next;
`endif
`endif
`ifdef CNT_Z
assign z = (q == `CNT_LENGTH'd0);
`endif
`ifdef CNT_ZQ
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
`ifdef CNT_CE
if (cke)
`endif
zq <= q_next == `CNT_LENGTH'd0;
`endif
endmodule | module sd_counter
(
`ifdef CNT_TYPE_GRAY
output reg [`CNT_LENGTH:1] q,
`ifdef CNT_Q_BIN
output [`CNT_LENGTH:1] q_bin,
`endif
`else
`ifdef CNT_Q
output [`CNT_LENGTH:1] q,
`endif
`endif
`ifdef CNT_CLEAR
input clear,
`endif
`ifdef CNT_SET
input set,
`endif
`ifdef CNT_REW
input rew,
`endif
`ifdef CNT_CE
input cke,
`endif
`ifdef CNT_QNEXT
output [`CNT_LENGTH:1] q_next,
`endif
`ifdef CNT_Z
output z,
`endif
`ifdef CNT_ZQ
output reg zq,
`endif
input clk,
input rst
); |
`ifdef CNT_SET
parameter set_value = `CNT_SET_VALUE;
`endif
`ifdef CNT_WRAP
parameter wrap_value = `CNT_WRAP_VALUE;
`endif
reg [`CNT_LENGTH:1] qi;
`ifdef CNT_QNEXT
`else
wire [`CNT_LENGTH:1] q_next;
`endif
`ifdef CNT_REW
wire [`CNT_LENGTH:1] q_next_fw;
wire [`CNT_LENGTH:1] q_next_rew;
`endif
`ifdef CNT_REW
`else
assign q_next =
`endif
`ifdef CNT_REW
assign q_next_fw =
`endif
`ifdef CNT_CLEAR
clear ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_SET
set ? set_value :
`endif
`ifdef CNT_WRAP
(qi == wrap_value) ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_TYPE_LFSR
{qi[8:1],~(q[`LFSR_LENGTH]^q[1])};
`else
qi + `CNT_LENGTH'd1;
`endif
`ifdef CNT_REW
assign q_next_rew =
`ifdef CNT_CLEAR
clear ? `CNT_LENGTH'd0 :
`endif
`ifdef CNT_SET
set ? set_value :
`endif
`ifdef CNT_WRAP
(qi == `CNT_LENGTH'd0) ? wrap_value :
`endif
`ifdef CNT_TYPE_LFSR
{~(q[1]^q[2]),qi[`CNT_LENGTH:2]};
`else
qi - `CNT_LENGTH'd1;
`endif
`endif
`ifdef CNT_REW
assign q_next = rew ? q_next_rew : q_next_fw;
`endif
always @ (posedge clk or posedge rst)
if (rst)
qi <= `CNT_LENGTH'd0;
else
`ifdef CNT_CE
if (cke)
`endif
qi <= q_next;
`ifdef CNT_Q
`ifdef CNT_TYPE_GRAY
always @ (posedge clk or posedge rst)
if (rst)
q <= `CNT_LENGTH'd0;
else
`ifdef CNT_CE
if (cke)
`endif
q <= (q_next>>1) ^ q_next;
`ifdef CNT_Q_BIN
assign q_bin = qi;
`endif
`else
assign q = q_next;
`endif
`endif
`ifdef CNT_Z
assign z = (q == `CNT_LENGTH'd0);
`endif
`ifdef CNT_ZQ
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
`ifdef CNT_CE
if (cke)
`endif
zq <= q_next == `CNT_LENGTH'd0;
`endif
endmodule | 1 |
4,361 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v | 109,400,221 | sd_data_phy.v | v | 445 | 152 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xe5 in position 74: invalid continuation byte | null | 1: b'%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:7: Cannot find include file: sd_defines.v\n`include "sd_defines.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_defines.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_defines.v.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_defines.v.sv\n sd_defines.v\n sd_defines.v.v\n sd_defines.v.sv\n obj_dir/sd_defines.v\n obj_dir/sd_defines.v.v\n obj_dir/sd_defines.v.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:99: Define or directive not defined: \'`BIT_BLOCK\'\n if (transf_cnt_write >= `BIT_BLOCK+2) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:130: Define or directive not defined: \'`BIT_BLOCK\'\n if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:262: Define or directive not defined: \'`BIT_BLOCK\'\n else if ( (transf_cnt_write>=2+2) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+2 )) begin \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:262: Define or directive not defined: \'`CRC_OFF\'\n else if ( (transf_cnt_write>=2+2) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+2 )) begin \n ^~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:280: Define or directive not defined: \'`BIT_BLOCK\'\n if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +2) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:280: Define or directive not defined: \'`CRC_OFF\'\n if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +2) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:284: Define or directive not defined: \'`BIT_BLOCK\'\n else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +2 & crc_cnt_write!=0) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:284: Define or directive not defined: \'`CRC_OFF\'\n else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +2 & crc_cnt_write!=0) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:294: Define or directive not defined: \'`BIT_BLOCK\'\n else if (transf_cnt_write==`BIT_BLOCK-2+2) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:378: Define or directive not defined: \'`BIT_BLOCK_REC\'\n if (transf_cnt_read<`BIT_BLOCK_REC) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:378: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (transf_cnt_read<`BIT_BLOCK_REC) begin\n ^\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:386: syntax error, unexpected else, expecting endcase\n else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin\n ^~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:386: Define or directive not defined: \'`BIT_BLOCK_REC\'\n else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:386: Define or directive not defined: \'`BIT_CRC_CYCLE\'\n else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:391: Define or directive not defined: \'`BIT_BLOCK_REC\'\n if (transf_cnt_read> `BIT_BLOCK_REC) begin \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:391: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (transf_cnt_read> `BIT_BLOCK_REC) begin \n ^\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_data_phy.v:412: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,602 | module | module sd_data_phy(
input sd_clk,
input rst,
output reg DAT_oe_o,
output reg[3:0] DAT_dat_o,
input [3:0] DAT_dat_i,
output [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input [3:4] fifo_full,
input [3:4] fifo_empty,
input [1:0] start_dat,
input fifo_acces
);
reg [5:0] in_buff_ptr_read;
reg [5:0] out_buff_ptr_read;
reg crc_ok;
reg [3:0] last_din_read;
reg [7:0] tmp_crc_token ;
reg[2:0] crc_read_count;
reg [3:0] crc_in_write;
reg crc_en_write;
reg crc_rst_write;
wire [15:0] crc_out_write [3:0];
reg [3:0] crc_in_read;
reg crc_en_read;
reg crc_rst_read;
wire [15:0] crc_out_read [3:0];
reg[7:0] next_out;
reg data_read_index;
reg [10:0] transf_cnt_write;
reg [10:0] transf_cnt_read;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 6'b000001;
parameter WRITE_DAT = 6'b000010;
parameter READ_CRC = 6'b000100;
parameter WRITE_CRC = 6'b001000;
parameter READ_WAIT = 6'b010000;
parameter READ_DAT = 6'b100000;
reg in_dat_buffer_empty;
reg [2:0] crc_status_token;
reg busy_int;
reg add_token;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
end
endgenerate
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
end
endgenerate
reg q_start_bit;
always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )
begin : FSM_COMBO
next_state = 0;
case(state)
IDLE: begin
if (start_dat == 2'b01)
next_state=WRITE_DAT;
else if (start_dat == 2'b10)
next_state=READ_WAIT;
else
next_state=IDLE;
end
WRITE_DAT: begin
if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
next_state= READ_CRC;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=WRITE_DAT;
end
READ_WAIT: begin
if (DAT_dat_i[0]== 0 )
next_state= READ_DAT;
else
next_state=READ_WAIT;
end
READ_CRC: begin
if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
next_state= WRITE_CRC;
else
next_state=READ_CRC;
end
WRITE_CRC: begin
next_state= IDLE;
end
READ_DAT: begin
if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty))
next_state= IDLE;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=READ_DAT;
end
endcase
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst ) begin
q_start_bit<=1;
end
else begin
q_start_bit <= DAT_dat_i[0];
end
end
always @ (posedge sd_clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
reg [4:0] crc_cnt_write;
reg [4:0]crc_cnt_read;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [7:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg data_send_index;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
reg read_byte_cnt;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
reg [3:0] in_dat_buffer [63:0];
always @ (negedge sd_clk or posedge rst )
begin
if (rst) begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
transf_cnt_write<=0;
crc_cnt_write<=15;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
read_byte_cnt<=0;
write_buf_0<=0;
write_buf_1<=0;
sd_re_o<=0;
sd_data_out<=0;
sd_adr_o_write<=0;
crc_in_write<=0;
DAT_dat_o<=0;
last_din<=0;
end
else begin
case(state)
IDLE: begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
crc_cnt_write<=16;
read_byte_cnt<=0;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
sd_re_o<=0;
transf_cnt_write<=0;
end
WRITE_DAT: begin
transf_cnt_write<=transf_cnt_write+1;
if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin
read_byte_cnt<=read_byte_cnt+1;
sd_re_o<=0;
case (read_byte_cnt)
0:begin
sd_adr_o_write <=2;
sd_re_o<=1;
end
1:begin
if (!in_buff_ptr)
write_buf_0<=sd_dat_i;
else
write_buf_1 <=sd_dat_i;
in_buff_ptr<=in_buff_ptr+1;
end
endcase
end
if (!out_buff_ptr)
sd_data_out<=write_buf_0;
else
sd_data_out<=write_buf_1;
if (transf_cnt_write==1+`BUFFER_OFFSET) begin
crc_rst_write<=0;
crc_en_write<=1;
last_din <=write_buf_0[3:0];
DAT_oe_o<=1;
DAT_dat_o<=0;
crc_in_write<= write_buf_0[3:0];
data_send_index<=1;
out_buff_ptr<=out_buff_ptr+1;
end
else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
DAT_oe_o<=1;
case (data_send_index)
0:begin
last_din <=sd_data_out[3:0];
crc_in_write <=sd_data_out[3:0];
out_buff_ptr<=out_buff_ptr+1;
end
1:begin
last_din <=sd_data_out[7:4];
crc_in_write <=sd_data_out[7:4];
end
endcase
data_send_index<=data_send_index+1;
DAT_dat_o<= last_din;
if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
crc_en_write<=0;
end
end
else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
crc_en_write<=0;
crc_cnt_write<=crc_cnt_write-1;
DAT_oe_o<=1;
DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
end
else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
DAT_oe_o<=1;
DAT_dat_o<=4'b1111;
end
else if (transf_cnt_write !=0) begin
DAT_oe_o<=0;
end
end
endcase
end
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst) begin
add_token<=0;
sd_adr_o_read<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=0;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=0;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
next_out<=0;
busy_int<=0;
sd_dat_o<=0;
end
else begin
case(state)
IDLE: begin
add_token<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=1;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=15;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
end
READ_DAT: begin
add_token<=1;
crc_rst_read<=0;
crc_en_read<=1;
if (fifo_acces) begin
if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
data_read_index<=~data_read_index;
case(data_read_index)
0: begin
sd_adr_o_read<=3;
sd_we_o<=0;
next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
end
1: begin
out_buff_ptr_read<=out_buff_ptr_read+2;
sd_dat_o<=next_out;
sd_we_o<=1;
end
endcase
end
else
in_dat_buffer_empty<=1;
end
if (transf_cnt_read<`BIT_BLOCK_REC) begin
in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
crc_in_read<=DAT_dat_i;
crc_ok<=1;
transf_cnt_read<=transf_cnt_read+1;
in_buff_ptr_read<=in_buff_ptr_read+1;
end
else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
transf_cnt_read<=transf_cnt_read+1;
crc_en_read<=0;
last_din_read <=DAT_dat_i;
if (transf_cnt_read> `BIT_BLOCK_REC) begin
crc_cnt_read <=crc_cnt_read-1;
if (crc_out_read[0][crc_cnt_read] != last_din[0])
crc_ok<=0;
if (crc_out_read[1][crc_cnt_read] != last_din[1])
crc_ok<=0;
if (crc_out_read[2][crc_cnt_read] != last_din[2])
crc_ok<=0;
if (crc_out_read[3][crc_cnt_read] != last_din[3])
crc_ok<=0;
if (crc_cnt_read==0) begin
end
end
end
end
READ_CRC: begin
if (crc_read_count<3'b111) begin
crc_read_count<=crc_read_count+1;
tmp_crc_token[crc_read_count] <= DAT_dat_i[0];
end
busy_int <=DAT_dat_i[0];
end
WRITE_CRC: begin
add_token<=1;
sd_adr_o_read<=3;
sd_we_o<=1;
sd_dat_o<=tmp_crc_token;
end
endcase
end
end
endmodule | module sd_data_phy(
input sd_clk,
input rst,
output reg DAT_oe_o,
output reg[3:0] DAT_dat_o,
input [3:0] DAT_dat_i,
output [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input [3:4] fifo_full,
input [3:4] fifo_empty,
input [1:0] start_dat,
input fifo_acces
); |
reg [5:0] in_buff_ptr_read;
reg [5:0] out_buff_ptr_read;
reg crc_ok;
reg [3:0] last_din_read;
reg [7:0] tmp_crc_token ;
reg[2:0] crc_read_count;
reg [3:0] crc_in_write;
reg crc_en_write;
reg crc_rst_write;
wire [15:0] crc_out_write [3:0];
reg [3:0] crc_in_read;
reg crc_en_read;
reg crc_rst_read;
wire [15:0] crc_out_read [3:0];
reg[7:0] next_out;
reg data_read_index;
reg [10:0] transf_cnt_write;
reg [10:0] transf_cnt_read;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 6'b000001;
parameter WRITE_DAT = 6'b000010;
parameter READ_CRC = 6'b000100;
parameter WRITE_CRC = 6'b001000;
parameter READ_WAIT = 6'b010000;
parameter READ_DAT = 6'b100000;
reg in_dat_buffer_empty;
reg [2:0] crc_status_token;
reg busy_int;
reg add_token;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
end
endgenerate
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
end
endgenerate
reg q_start_bit;
always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )
begin : FSM_COMBO
next_state = 0;
case(state)
IDLE: begin
if (start_dat == 2'b01)
next_state=WRITE_DAT;
else if (start_dat == 2'b10)
next_state=READ_WAIT;
else
next_state=IDLE;
end
WRITE_DAT: begin
if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
next_state= READ_CRC;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=WRITE_DAT;
end
READ_WAIT: begin
if (DAT_dat_i[0]== 0 )
next_state= READ_DAT;
else
next_state=READ_WAIT;
end
READ_CRC: begin
if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
next_state= WRITE_CRC;
else
next_state=READ_CRC;
end
WRITE_CRC: begin
next_state= IDLE;
end
READ_DAT: begin
if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty))
next_state= IDLE;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=READ_DAT;
end
endcase
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst ) begin
q_start_bit<=1;
end
else begin
q_start_bit <= DAT_dat_i[0];
end
end
always @ (posedge sd_clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
reg [4:0] crc_cnt_write;
reg [4:0]crc_cnt_read;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [7:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg data_send_index;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
reg read_byte_cnt;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
reg [3:0] in_dat_buffer [63:0];
always @ (negedge sd_clk or posedge rst )
begin
if (rst) begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
transf_cnt_write<=0;
crc_cnt_write<=15;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
read_byte_cnt<=0;
write_buf_0<=0;
write_buf_1<=0;
sd_re_o<=0;
sd_data_out<=0;
sd_adr_o_write<=0;
crc_in_write<=0;
DAT_dat_o<=0;
last_din<=0;
end
else begin
case(state)
IDLE: begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
crc_cnt_write<=16;
read_byte_cnt<=0;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
sd_re_o<=0;
transf_cnt_write<=0;
end
WRITE_DAT: begin
transf_cnt_write<=transf_cnt_write+1;
if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin
read_byte_cnt<=read_byte_cnt+1;
sd_re_o<=0;
case (read_byte_cnt)
0:begin
sd_adr_o_write <=2;
sd_re_o<=1;
end
1:begin
if (!in_buff_ptr)
write_buf_0<=sd_dat_i;
else
write_buf_1 <=sd_dat_i;
in_buff_ptr<=in_buff_ptr+1;
end
endcase
end
if (!out_buff_ptr)
sd_data_out<=write_buf_0;
else
sd_data_out<=write_buf_1;
if (transf_cnt_write==1+`BUFFER_OFFSET) begin
crc_rst_write<=0;
crc_en_write<=1;
last_din <=write_buf_0[3:0];
DAT_oe_o<=1;
DAT_dat_o<=0;
crc_in_write<= write_buf_0[3:0];
data_send_index<=1;
out_buff_ptr<=out_buff_ptr+1;
end
else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
DAT_oe_o<=1;
case (data_send_index)
0:begin
last_din <=sd_data_out[3:0];
crc_in_write <=sd_data_out[3:0];
out_buff_ptr<=out_buff_ptr+1;
end
1:begin
last_din <=sd_data_out[7:4];
crc_in_write <=sd_data_out[7:4];
end
endcase
data_send_index<=data_send_index+1;
DAT_dat_o<= last_din;
if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
crc_en_write<=0;
end
end
else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
crc_en_write<=0;
crc_cnt_write<=crc_cnt_write-1;
DAT_oe_o<=1;
DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
end
else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
DAT_oe_o<=1;
DAT_dat_o<=4'b1111;
end
else if (transf_cnt_write !=0) begin
DAT_oe_o<=0;
end
end
endcase
end
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst) begin
add_token<=0;
sd_adr_o_read<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=0;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=0;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
next_out<=0;
busy_int<=0;
sd_dat_o<=0;
end
else begin
case(state)
IDLE: begin
add_token<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=1;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=15;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
end
READ_DAT: begin
add_token<=1;
crc_rst_read<=0;
crc_en_read<=1;
if (fifo_acces) begin
if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
data_read_index<=~data_read_index;
case(data_read_index)
0: begin
sd_adr_o_read<=3;
sd_we_o<=0;
next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
end
1: begin
out_buff_ptr_read<=out_buff_ptr_read+2;
sd_dat_o<=next_out;
sd_we_o<=1;
end
endcase
end
else
in_dat_buffer_empty<=1;
end
if (transf_cnt_read<`BIT_BLOCK_REC) begin
in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
crc_in_read<=DAT_dat_i;
crc_ok<=1;
transf_cnt_read<=transf_cnt_read+1;
in_buff_ptr_read<=in_buff_ptr_read+1;
end
else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
transf_cnt_read<=transf_cnt_read+1;
crc_en_read<=0;
last_din_read <=DAT_dat_i;
if (transf_cnt_read> `BIT_BLOCK_REC) begin
crc_cnt_read <=crc_cnt_read-1;
if (crc_out_read[0][crc_cnt_read] != last_din[0])
crc_ok<=0;
if (crc_out_read[1][crc_cnt_read] != last_din[1])
crc_ok<=0;
if (crc_out_read[2][crc_cnt_read] != last_din[2])
crc_ok<=0;
if (crc_out_read[3][crc_cnt_read] != last_din[3])
crc_ok<=0;
if (crc_cnt_read==0) begin
end
end
end
end
READ_CRC: begin
if (crc_read_count<3'b111) begin
crc_read_count<=crc_read_count+1;
tmp_crc_token[crc_read_count] <= DAT_dat_i[0];
end
busy_int <=DAT_dat_i[0];
end
WRITE_CRC: begin
add_token<=1;
sd_adr_o_read<=3;
sd_we_o<=1;
sd_dat_o<=tmp_crc_token;
end
endcase
end
end
endmodule | 1 |
4,362 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v | 109,400,221 | sd_fifo.v | v | 197 | 127 | [] | [] | [] | [(2, 194)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:16: Little bit endian vector: MSB < LSB of bit range: 1:4\n output [1:4] fifo_full,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:17: Little bit endian vector: MSB < LSB of bit range: 1:4\n output [1:4] fifo_empty,\n ^\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:27: Cannot find file containing module: \'sd_counter\'\n sd_counter wptr1a\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_counter\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_counter.v\n data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog,data/full_repos/permissive/109400221/sd_counter.sv\n sd_counter\n sd_counter.v\n sd_counter.sv\n obj_dir/sd_counter\n obj_dir/sd_counter.v\n obj_dir/sd_counter.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:36: Cannot find file containing module: \'sd_counter\'\n sd_counter rptr1a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:45: Cannot find file containing module: \'versatile_fifo_async_cmp\'\n versatile_fifo_async_cmp\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:61: Cannot find file containing module: \'sd_counter\'\n sd_counter wptr2a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:70: Cannot find file containing module: \'sd_counter\'\n sd_counter rptr2a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:79: Cannot find file containing module: \'versatile_fifo_async_cmp\'\n versatile_fifo_async_cmp\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:95: Cannot find file containing module: \'sd_counter\'\n sd_counter wptr3a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:104: Cannot find file containing module: \'sd_counter\'\n sd_counter rptr3a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:113: Cannot find file containing module: \'versatile_fifo_async_cmp\'\n versatile_fifo_async_cmp\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:129: Cannot find file containing module: \'sd_counter\'\n sd_counter wptr4a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:138: Cannot find file containing module: \'sd_counter\'\n sd_counter rptr4a\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:147: Cannot find file containing module: \'versatile_fifo_async_cmp\'\n versatile_fifo_async_cmp\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/sd_fifo.v:179: Cannot find file containing module: \'versatile_fifo_dptam_dw\'\n versatile_fifo_dptam_dw\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s), 2 warning(s)\n' | 2,604 | module | module sd_fifo
(
input [1:0] wb_adr_i,
input [7:0] wb_dat_i,
output [7:0] wb_dat_o,
input wb_we_i,
input wb_re_i,
input wb_clk,
input [1:0] sd_adr_i,
input [7:0] sd_dat_i,
output [7:0] sd_dat_o,
input sd_we_i,
input sd_re_i,
input sd_clk,
output [1:4] fifo_full,
output [1:4] fifo_empty,
input rst
);
wire [8:0] wptr1, rptr1, wptr2, rptr2, wptr3, rptr3, wptr4, rptr4;
wire [8:0] wadr1, radr1, wadr2, radr2, wadr3, radr3, wadr4, radr4;
wire dpram_we_a, dpram_we_b;
wire [10:0] dpram_a_a, dpram_a_b;
sd_counter wptr1a
(
.q(wptr1),
.q_bin(wadr1),
.cke((wb_adr_i==2'd0) & wb_we_i & !fifo_full[1]),
.clk(wb_clk),
.rst(rst)
);
sd_counter rptr1a
(
.q(rptr1),
.q_bin(radr1),
.cke((sd_adr_i==2'd0) & sd_re_i & !fifo_empty[1]),
.clk(sd_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp1
(
.wptr(wptr1),
.rptr(rptr1),
.fifo_empty(fifo_empty[1]),
.fifo_full(fifo_full[1]),
.wclk(wb_clk),
.rclk(sd_clk),
.rst(rst)
);
sd_counter wptr2a
(
.q(wptr2),
.q_bin(wadr2),
.cke((sd_adr_i==2'd1) & sd_we_i & !fifo_full[2]),
.clk(sd_clk),
.rst(rst)
);
sd_counter rptr2a
(
.q(rptr2),
.q_bin(radr2),
.cke((wb_adr_i==2'd1) & wb_re_i & !fifo_empty[2]),
.clk(wb_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp2
(
.wptr(wptr2),
.rptr(rptr2),
.fifo_empty(fifo_empty[2]),
.fifo_full(fifo_full[2]),
.wclk(sd_clk),
.rclk(wb_clk),
.rst(rst)
);
sd_counter wptr3a
(
.q(wptr3),
.q_bin(wadr3),
.cke((wb_adr_i==2'd2) & wb_we_i & !fifo_full[3]),
.clk(wb_clk),
.rst(rst)
);
sd_counter rptr3a
(
.q(rptr3),
.q_bin(radr3),
.cke((sd_adr_i==2'd2) & sd_re_i & !fifo_empty[3]),
.clk(sd_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp3
(
.wptr(wptr3),
.rptr(rptr3),
.fifo_empty(fifo_empty[3]),
.fifo_full(fifo_full[3]),
.wclk(wb_clk),
.rclk(sd_clk),
.rst(rst)
);
sd_counter wptr4a
(
.q(wptr4),
.q_bin(wadr4),
.cke((sd_adr_i==2'd3) & sd_we_i & !fifo_full[4]),
.clk(sd_clk),
.rst(rst)
);
sd_counter rptr4a
(
.q(rptr4),
.q_bin(radr4),
.cke((wb_adr_i==2'd3) & wb_re_i & !fifo_empty[4]),
.clk(wb_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp4
(
.wptr(wptr4),
.rptr(rptr4),
.fifo_empty(fifo_empty[4]),
.fifo_full(fifo_full[4]),
.wclk(sd_clk),
.rclk(wb_clk),
.rst(rst)
);
assign dpram_we_a = ((wb_adr_i==2'd0) & !fifo_full[1]) ? wb_we_i :
((wb_adr_i==2'd2) & !fifo_full[3]) ? wb_we_i :
1'b0;
assign dpram_we_b = ((sd_adr_i==2'd1) & !fifo_full[2]) ? sd_we_i :
((sd_adr_i==2'd3) & !fifo_full[4]) ? sd_we_i :
1'b0;
assign dpram_a_a = (wb_adr_i==2'd0) ? {wb_adr_i,wadr1} :
(wb_adr_i==2'd1) ? {wb_adr_i,radr2} :
(wb_adr_i==2'd2) ? {wb_adr_i,wadr3} :
{wb_adr_i,radr4};
assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} :
(sd_adr_i==2'd1) ? {sd_adr_i,wadr2} :
(sd_adr_i==2'd2) ? {sd_adr_i,radr3} :
{sd_adr_i,wadr4};
versatile_fifo_dptam_dw
dpram
(
.d_a(wb_dat_i),
.q_a(wb_dat_o),
.adr_a(dpram_a_a),
.we_a(dpram_we_a),
.clk_a(wb_clk),
.q_b(sd_dat_o),
.adr_b(dpram_a_b),
.d_b(sd_dat_i),
.we_b(dpram_we_b),
.clk_b(sd_clk)
);
endmodule | module sd_fifo
(
input [1:0] wb_adr_i,
input [7:0] wb_dat_i,
output [7:0] wb_dat_o,
input wb_we_i,
input wb_re_i,
input wb_clk,
input [1:0] sd_adr_i,
input [7:0] sd_dat_i,
output [7:0] sd_dat_o,
input sd_we_i,
input sd_re_i,
input sd_clk,
output [1:4] fifo_full,
output [1:4] fifo_empty,
input rst
); |
wire [8:0] wptr1, rptr1, wptr2, rptr2, wptr3, rptr3, wptr4, rptr4;
wire [8:0] wadr1, radr1, wadr2, radr2, wadr3, radr3, wadr4, radr4;
wire dpram_we_a, dpram_we_b;
wire [10:0] dpram_a_a, dpram_a_b;
sd_counter wptr1a
(
.q(wptr1),
.q_bin(wadr1),
.cke((wb_adr_i==2'd0) & wb_we_i & !fifo_full[1]),
.clk(wb_clk),
.rst(rst)
);
sd_counter rptr1a
(
.q(rptr1),
.q_bin(radr1),
.cke((sd_adr_i==2'd0) & sd_re_i & !fifo_empty[1]),
.clk(sd_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp1
(
.wptr(wptr1),
.rptr(rptr1),
.fifo_empty(fifo_empty[1]),
.fifo_full(fifo_full[1]),
.wclk(wb_clk),
.rclk(sd_clk),
.rst(rst)
);
sd_counter wptr2a
(
.q(wptr2),
.q_bin(wadr2),
.cke((sd_adr_i==2'd1) & sd_we_i & !fifo_full[2]),
.clk(sd_clk),
.rst(rst)
);
sd_counter rptr2a
(
.q(rptr2),
.q_bin(radr2),
.cke((wb_adr_i==2'd1) & wb_re_i & !fifo_empty[2]),
.clk(wb_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp2
(
.wptr(wptr2),
.rptr(rptr2),
.fifo_empty(fifo_empty[2]),
.fifo_full(fifo_full[2]),
.wclk(sd_clk),
.rclk(wb_clk),
.rst(rst)
);
sd_counter wptr3a
(
.q(wptr3),
.q_bin(wadr3),
.cke((wb_adr_i==2'd2) & wb_we_i & !fifo_full[3]),
.clk(wb_clk),
.rst(rst)
);
sd_counter rptr3a
(
.q(rptr3),
.q_bin(radr3),
.cke((sd_adr_i==2'd2) & sd_re_i & !fifo_empty[3]),
.clk(sd_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp3
(
.wptr(wptr3),
.rptr(rptr3),
.fifo_empty(fifo_empty[3]),
.fifo_full(fifo_full[3]),
.wclk(wb_clk),
.rclk(sd_clk),
.rst(rst)
);
sd_counter wptr4a
(
.q(wptr4),
.q_bin(wadr4),
.cke((sd_adr_i==2'd3) & sd_we_i & !fifo_full[4]),
.clk(sd_clk),
.rst(rst)
);
sd_counter rptr4a
(
.q(rptr4),
.q_bin(radr4),
.cke((wb_adr_i==2'd3) & wb_re_i & !fifo_empty[4]),
.clk(wb_clk),
.rst(rst)
);
versatile_fifo_async_cmp
#
(
.ADDR_WIDTH(9)
)
cmp4
(
.wptr(wptr4),
.rptr(rptr4),
.fifo_empty(fifo_empty[4]),
.fifo_full(fifo_full[4]),
.wclk(sd_clk),
.rclk(wb_clk),
.rst(rst)
);
assign dpram_we_a = ((wb_adr_i==2'd0) & !fifo_full[1]) ? wb_we_i :
((wb_adr_i==2'd2) & !fifo_full[3]) ? wb_we_i :
1'b0;
assign dpram_we_b = ((sd_adr_i==2'd1) & !fifo_full[2]) ? sd_we_i :
((sd_adr_i==2'd3) & !fifo_full[4]) ? sd_we_i :
1'b0;
assign dpram_a_a = (wb_adr_i==2'd0) ? {wb_adr_i,wadr1} :
(wb_adr_i==2'd1) ? {wb_adr_i,radr2} :
(wb_adr_i==2'd2) ? {wb_adr_i,wadr3} :
{wb_adr_i,radr4};
assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} :
(sd_adr_i==2'd1) ? {sd_adr_i,wadr2} :
(sd_adr_i==2'd2) ? {sd_adr_i,radr3} :
{sd_adr_i,wadr4};
versatile_fifo_dptam_dw
dpram
(
.d_a(wb_dat_i),
.q_a(wb_dat_o),
.adr_a(dpram_a_a),
.we_a(dpram_we_a),
.clk_a(wb_clk),
.q_b(sd_dat_o),
.adr_b(dpram_a_b),
.d_b(sd_dat_i),
.we_b(dpram_we_b),
.clk_b(sd_clk)
);
endmodule | 1 |
4,363 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/versatile_fifo_async_cmp.v | 109,400,221 | versatile_fifo_async_cmp.v | v | 70 | 88 | [] | [] | [] | [(1, 69)] | null | data/verilator_xmls/c900a250-842b-4c7d-8d0e-332b19dc89d0.xml | null | 2,606 | module | module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty, fifo_full;
input wclk, rclk, rst;
reg direction, direction_set, direction_clr;
wire async_empty, async_full;
reg fifo_full2, fifo_empty2;
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule | module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty, fifo_full;
input wclk, rclk, rst;
reg direction, direction_set, direction_clr;
wire async_empty, async_full;
reg fifo_full2, fifo_empty2;
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule | 1 |
4,364 | data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_fifo/verilog/versatile_fifo_dptam_dw.v | 109,400,221 | versatile_fifo_dptam_dw.v | v | 47 | 50 | [] | [] | [] | [(1, 46)] | null | data/verilator_xmls/20a7423f-d10b-48e9-a666-d7a0d805da93.xml | null | 2,607 | module | module versatile_fifo_dptam_dw
(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 11;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output reg[(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk_a, clk_b;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
if (we_a) begin
ram[adr_a] <= d_a;
end
end
always @ (posedge clk_b)
begin
q_b <= ram[adr_b];
if (we_b)
begin
ram[adr_b] <= d_b;
end
end
endmodule | module versatile_fifo_dptam_dw
(
d_a,
q_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
d_b,
we_b,
clk_b
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 11;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output reg[(DATA_WIDTH-1):0] q_b;
input [(DATA_WIDTH-1):0] d_b;
output reg [(DATA_WIDTH-1):0] q_a;
input we_b;
input clk_a, clk_b;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
if (we_a) begin
ram[adr_a] <= d_a;
end
end
always @ (posedge clk_b)
begin
q_b <= ram[adr_b];
if (we_b)
begin
ram[adr_b] <= d_b;
end
end
endmodule | 1 |
4,365 | data/full_repos/permissive/109506234/model.v | 109,506,234 | model.v | v | 862 | 109 | [] | [] | [] | [(3, 279), (282, 592), (595, 860)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109506234/model.v:282: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'adder\'\nmodule adder(\n ^~~~~\n : ... Top module \'divider\'\nmodule divider(\n ^~~~~~~\n : ... Top module \'multiplier\'\nmodule multiplier(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:677: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:678: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:679: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:680: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:367: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:368: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:369: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:370: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:476: Operator SHIFTL expects 51 bits on the LHS, but LHS\'s VARREF \'a_m\' generates 24 bits.\n : ... In instance divider\n dividend <= a_m << 27;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:477: Operator ASSIGNDLY expects 51 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_m\' generates 24 bits.\n : ... In instance divider\n divisor <= b_m;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:85: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n a_m <= {a[22 : 0], 3\'d0}; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:86: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n b_m <= {b[22 : 0], 3\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:87: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:88: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:119: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:125: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:131: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= a_m[26:3];\n ^~\n%Error: Exiting due to 18 warning(s)\n' | 2,608 | module | module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack); |
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | 0 |
4,366 | data/full_repos/permissive/109506234/model.v | 109,506,234 | model.v | v | 862 | 109 | [] | [] | [] | [(3, 279), (282, 592), (595, 860)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109506234/model.v:282: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'adder\'\nmodule adder(\n ^~~~~\n : ... Top module \'divider\'\nmodule divider(\n ^~~~~~~\n : ... Top module \'multiplier\'\nmodule multiplier(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:677: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:678: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:679: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:680: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:367: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:368: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:369: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:370: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:476: Operator SHIFTL expects 51 bits on the LHS, but LHS\'s VARREF \'a_m\' generates 24 bits.\n : ... In instance divider\n dividend <= a_m << 27;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:477: Operator ASSIGNDLY expects 51 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_m\' generates 24 bits.\n : ... In instance divider\n divisor <= b_m;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:85: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n a_m <= {a[22 : 0], 3\'d0}; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:86: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n b_m <= {b[22 : 0], 3\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:87: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:88: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:119: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:125: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:131: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= a_m[26:3];\n ^~\n%Error: Exiting due to 18 warning(s)\n' | 2,608 | module | module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack); |
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | 0 |
4,367 | data/full_repos/permissive/109506234/model.v | 109,506,234 | model.v | v | 862 | 109 | [] | [] | [] | [(3, 279), (282, 592), (595, 860)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/109506234/model.v:282: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'adder\'\nmodule adder(\n ^~~~~\n : ... Top module \'divider\'\nmodule divider(\n ^~~~~~~\n : ... Top module \'multiplier\'\nmodule multiplier(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:677: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:678: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance multiplier\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:679: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:680: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance multiplier\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:367: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n a_m <= a[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:368: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n : ... In instance divider\n b_m <= b[22 : 0];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:369: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:370: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance divider\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:476: Operator SHIFTL expects 51 bits on the LHS, but LHS\'s VARREF \'a_m\' generates 24 bits.\n : ... In instance divider\n dividend <= a_m << 27;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:477: Operator ASSIGNDLY expects 51 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_m\' generates 24 bits.\n : ... In instance divider\n divisor <= b_m;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:85: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n a_m <= {a[22 : 0], 3\'d0}; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:86: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 26 bits.\n : ... In instance adder\n b_m <= {b[22 : 0], 3\'d0};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:87: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n a_e <= a[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:88: Operator SUB expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n : ... In instance adder\n b_e <= b[30 : 23] - 127;\n ^\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:119: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:125: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= b_m[26:3];\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109506234/model.v:131: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n : ... In instance adder\n z[22:0] <= a_m[26:3];\n ^~\n%Error: Exiting due to 18 warning(s)\n' | 2,608 | module | module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack); |
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule | 0 |
4,368 | data/full_repos/permissive/109506234/test.v | 109,506,234 | test.v | v | 90 | 91 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109506234/test.v:2: Cannot find include file: VerilogBM_120-120.v\n`include "VerilogBM_120-120.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.sv\n VerilogBM_120-120.v\n VerilogBM_120-120.v.v\n VerilogBM_120-120.v.sv\n obj_dir/VerilogBM_120-120.v\n obj_dir/VerilogBM_120-120.v.v\n obj_dir/VerilogBM_120-120.v.sv\n%Error: data/full_repos/permissive/109506234/test.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_add.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:24: Too many digits for 32 bit number: 01000001110010000000000000000000\n ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n ... Suggest adding a size to it.\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:25: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:33: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_div.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:34: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:41: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:48: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:49: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:53: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:61: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:62: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:67: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_mult.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:68: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:81: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:82: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:86: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: Exiting due to 17 error(s), 9 warning(s)\n' | 2,609 | module | module Verilog_120_120120();
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120_add.vcd");
$dumpvars(0,Verilog_120_120);
end
adder adder_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
endmodule | module Verilog_120_120120(); |
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120_add.vcd");
$dumpvars(0,Verilog_120_120);
end
adder adder_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
endmodule | 0 |
4,369 | data/full_repos/permissive/109506234/test.v | 109,506,234 | test.v | v | 90 | 91 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109506234/test.v:2: Cannot find include file: VerilogBM_120-120.v\n`include "VerilogBM_120-120.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.sv\n VerilogBM_120-120.v\n VerilogBM_120-120.v.v\n VerilogBM_120-120.v.sv\n obj_dir/VerilogBM_120-120.v\n obj_dir/VerilogBM_120-120.v.v\n obj_dir/VerilogBM_120-120.v.sv\n%Error: data/full_repos/permissive/109506234/test.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_add.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:24: Too many digits for 32 bit number: 01000001110010000000000000000000\n ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n ... Suggest adding a size to it.\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:25: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:33: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_div.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:34: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:41: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:48: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:49: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:53: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:61: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:62: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:67: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_mult.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:68: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:81: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:82: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:86: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: Exiting due to 17 error(s), 9 warning(s)\n' | 2,609 | module | module Verilog_120_120120();
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120_div.vcd");
$dumpvars(0,Verilog_120_120);
end
divider divider_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk);
end
endmodule | module Verilog_120_120120(); |
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120_div.vcd");
$dumpvars(0,Verilog_120_120);
end
divider divider_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk);
end
endmodule | 0 |
4,370 | data/full_repos/permissive/109506234/test.v | 109,506,234 | test.v | v | 90 | 91 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109506234/test.v:2: Cannot find include file: VerilogBM_120-120.v\n`include "VerilogBM_120-120.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.v\n data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.sv\n VerilogBM_120-120.v\n VerilogBM_120-120.v.v\n VerilogBM_120-120.v.sv\n obj_dir/VerilogBM_120-120.v\n obj_dir/VerilogBM_120-120.v.v\n obj_dir/VerilogBM_120-120.v.sv\n%Error: data/full_repos/permissive/109506234/test.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_add.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:24: Too many digits for 32 bit number: 01000001110010000000000000000000\n ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n ... Suggest adding a size to it.\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:25: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:33: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_div.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:34: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:41: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:48: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:49: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:53: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:61: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:62: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:67: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_mult.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:68: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:81: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:82: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:86: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: Exiting due to 17 error(s), 9 warning(s)\n' | 2,609 | module | module Verilog_120_120120();
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120.vcd");
$dumpvars(0,Verilog_120_120);
end
multiplier multiplier_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial
begin
$dumpfile("VerilogBM_120_120_mult.vcd");
$dumpvars(0,Verilog_120_120);
end
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk);
end
endmodule | module Verilog_120_120120(); |
reg input_a,input_b,clk,rst;
wire output_z;
initial
begin
$dumpfile("VerilogBM_120_120.vcd");
$dumpvars(0,Verilog_120_120);
end
multiplier multiplier_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial
begin
$dumpfile("VerilogBM_120_120_mult.vcd");
$dumpvars(0,Verilog_120_120);
end
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000;
input_b=00000000000000000000000000000000;
#1 input_a=01000001110010000000000000000000;
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk);
end
endmodule | 0 |
4,371 | data/full_repos/permissive/109594910/cpu.v | 109,594,910 | cpu.v | v | 132 | 158 | [] | [] | [] | [(1, 131)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109594910/cpu.v:111: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'alu_out\' generates 9 bits.\n : ... In instance cpu\n 5\'b0xxx0 : accu <= alu_out;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/109594910/cpu.v:112: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'alu_out\' generates 9 bits.\n : ... In instance cpu\n 5\'b0xxx1 : regs[rx] <= alu_out;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109594910/cpu.v:113: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'alu_out\' generates 9 bits.\n : ... In instance cpu\n 5\'b10000 : accu <= alu_out;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109594910/cpu.v:110: Operator CASE expects 5 bits on the Case expression, but Case expression\'s SEL generates 3 bits.\n : ... In instance cpu\n casez (ir[7:5])\n ^~~~~\n%Error: Exiting due to 4 warning(s)\n' | 2,610 | module | module cpu (
input clk,
input reset,
input [7:0] mem_data_in,
output [7:0] mem_data_out,
output [15:0] mem_addr_out,
output mem_read,
output mem_write,
input mem_done
);
reg [15:0] pc, nextpc;
reg [7:0] ir, accu;
reg [7:0] regs [7:0];
wire [7:0] reg_0 = regs[0];
wire [7:0] reg_1 = regs[1];
wire [7:0] reg_2 = regs[2];
wire [7:0] reg_3 = regs[3];
wire [7:0] reg_4 = regs[4];
wire [7:0] reg_5 = regs[5];
wire [7:0] reg_6 = regs[6];
wire [7:0] reg_7 = regs[7];
initial begin
pc <= 0;
ir <= 0;
nextpc <= 0;
alu_out <= 0;
accu <= 0;
regs[0] <= 0;
regs[1] <= 0;
regs[2] <= 0;
regs[3] <= 0;
regs[4] <= 0;
regs[5] <= 0;
regs[6] <= 0;
regs[7] <= 0;
phase <= 0;
maxphase <= 0;
nextphase <= 0;
Flags <= 8'h2a;
end
reg [2:0] rx;
reg [8:0] alu_out, alu_src1, alu_src2;
reg [7:0] Flags;
wire CFlag = Flags[0];
wire nCFlag = Flags[1];
wire NFlag = Flags[2];
wire nNFlag = Flags[3];
wire ZFlag = Flags[4];
wire nZFlag = Flags[5];
reg [7:0] next_Flags;
reg [1:0] phase, nextphase, maxphase;
reg [23:0] imm;
always @* begin
nextpc = reset ? 16'd0 : pc + 16'd1;
rx = ir[2:0];
alu_src1 = {1'b0, ir[3] ? regs[rx] : accu};
alu_src2 = {1'b0, ~ir[3] ? regs[rx] : accu};
case (ir[7:4])
4'h0 : alu_out = alu_src2;
4'h1 : alu_out = alu_src1 & alu_src2;
4'h2 : alu_out = alu_src1 | alu_src2;
4'h3 : alu_out = alu_src1 ^ alu_src2;
4'h4 : alu_out = alu_src1 + alu_src2;
4'h5 : alu_out = alu_src1 + alu_src2 + {8'b0, CFlag};
4'h6 : alu_out = alu_src1 - alu_src2;
4'h7 : alu_out = alu_src1 - alu_src2 - {8'b0, ~CFlag};
4'h8 : case (ir[3:0])
4'h0 : alu_out = {CFlag, accu + 8'h1};
4'h1 : alu_out = {CFlag, accu + 8'hff};
4'h2 : alu_out = {CFlag, accu[3:0], accu[7:4]};
4'h3 : alu_out = {CFlag, accu[0], accu[1], accu[2], accu[3], accu[4], accu[5], accu[6], accu[7]};
default : alu_out = 9'hX;
endcase
default : alu_out = 9'hX;
endcase
next_Flags = {Flags[7:6], |alu_out[7:0], ~|alu_out[7:0], ~alu_out[7], alu_out[7], ~alu_out[8], alu_out[8]};
maxphase = 0;
if (ir[7:4] == 4'hf) maxphase = 2;
if (phase != maxphase)
nextphase = phase + 1;
else
nextphase = 0;
end
always @(posedge clk) begin
if (reset) begin
pc <= 0;
ir <= 0;
nextpc <= 1;
end else begin
pc <= nextpc;
case (nextphase)
2'd0 : begin
ir <= mem_data_in;
imm <= 0;
Flags <= next_Flags;
casez (ir[7:5])
5'b0xxx0 : accu <= alu_out;
5'b0xxx1 : regs[rx] <= alu_out;
5'b10000 : accu <= alu_out;
5'b11110 : pc <= imm[15:0];
default : ;
endcase
end
2'd1 : imm[7:0] <= mem_data_in;
2'd2 : imm[15:8] <= mem_data_in;
2'd3 : imm[23:16] <= mem_data_in;
default : ;
endcase
phase <= nextphase;
end
end
assign mem_addr_out = pc;
assign mem_read = ~reset;
assign mem_write = 0;
endmodule | module cpu (
input clk,
input reset,
input [7:0] mem_data_in,
output [7:0] mem_data_out,
output [15:0] mem_addr_out,
output mem_read,
output mem_write,
input mem_done
); |
reg [15:0] pc, nextpc;
reg [7:0] ir, accu;
reg [7:0] regs [7:0];
wire [7:0] reg_0 = regs[0];
wire [7:0] reg_1 = regs[1];
wire [7:0] reg_2 = regs[2];
wire [7:0] reg_3 = regs[3];
wire [7:0] reg_4 = regs[4];
wire [7:0] reg_5 = regs[5];
wire [7:0] reg_6 = regs[6];
wire [7:0] reg_7 = regs[7];
initial begin
pc <= 0;
ir <= 0;
nextpc <= 0;
alu_out <= 0;
accu <= 0;
regs[0] <= 0;
regs[1] <= 0;
regs[2] <= 0;
regs[3] <= 0;
regs[4] <= 0;
regs[5] <= 0;
regs[6] <= 0;
regs[7] <= 0;
phase <= 0;
maxphase <= 0;
nextphase <= 0;
Flags <= 8'h2a;
end
reg [2:0] rx;
reg [8:0] alu_out, alu_src1, alu_src2;
reg [7:0] Flags;
wire CFlag = Flags[0];
wire nCFlag = Flags[1];
wire NFlag = Flags[2];
wire nNFlag = Flags[3];
wire ZFlag = Flags[4];
wire nZFlag = Flags[5];
reg [7:0] next_Flags;
reg [1:0] phase, nextphase, maxphase;
reg [23:0] imm;
always @* begin
nextpc = reset ? 16'd0 : pc + 16'd1;
rx = ir[2:0];
alu_src1 = {1'b0, ir[3] ? regs[rx] : accu};
alu_src2 = {1'b0, ~ir[3] ? regs[rx] : accu};
case (ir[7:4])
4'h0 : alu_out = alu_src2;
4'h1 : alu_out = alu_src1 & alu_src2;
4'h2 : alu_out = alu_src1 | alu_src2;
4'h3 : alu_out = alu_src1 ^ alu_src2;
4'h4 : alu_out = alu_src1 + alu_src2;
4'h5 : alu_out = alu_src1 + alu_src2 + {8'b0, CFlag};
4'h6 : alu_out = alu_src1 - alu_src2;
4'h7 : alu_out = alu_src1 - alu_src2 - {8'b0, ~CFlag};
4'h8 : case (ir[3:0])
4'h0 : alu_out = {CFlag, accu + 8'h1};
4'h1 : alu_out = {CFlag, accu + 8'hff};
4'h2 : alu_out = {CFlag, accu[3:0], accu[7:4]};
4'h3 : alu_out = {CFlag, accu[0], accu[1], accu[2], accu[3], accu[4], accu[5], accu[6], accu[7]};
default : alu_out = 9'hX;
endcase
default : alu_out = 9'hX;
endcase
next_Flags = {Flags[7:6], |alu_out[7:0], ~|alu_out[7:0], ~alu_out[7], alu_out[7], ~alu_out[8], alu_out[8]};
maxphase = 0;
if (ir[7:4] == 4'hf) maxphase = 2;
if (phase != maxphase)
nextphase = phase + 1;
else
nextphase = 0;
end
always @(posedge clk) begin
if (reset) begin
pc <= 0;
ir <= 0;
nextpc <= 1;
end else begin
pc <= nextpc;
case (nextphase)
2'd0 : begin
ir <= mem_data_in;
imm <= 0;
Flags <= next_Flags;
casez (ir[7:5])
5'b0xxx0 : accu <= alu_out;
5'b0xxx1 : regs[rx] <= alu_out;
5'b10000 : accu <= alu_out;
5'b11110 : pc <= imm[15:0];
default : ;
endcase
end
2'd1 : imm[7:0] <= mem_data_in;
2'd2 : imm[15:8] <= mem_data_in;
2'd3 : imm[23:16] <= mem_data_in;
default : ;
endcase
phase <= nextphase;
end
end
assign mem_addr_out = pc;
assign mem_read = ~reset;
assign mem_write = 0;
endmodule | 1 |
4,373 | data/full_repos/permissive/109594910/example-1k.v | 109,594,910 | example-1k.v | v | 38 | 95 | [] | [] | [] | null | line:13: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'rng\' generates 32 bits.\n : ... In instance top\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]}); \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 33 bits.\n : ... In instance top\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]}); \n ^~\n%Error: Exiting due to 2 warning(s)\n' | 2,612 | module | module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
localparam BITS = 5;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS-1:0] in);
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2])
rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5} = rng[11:7];
endmodule | module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
); |
localparam BITS = 5;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS-1:0] in);
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2])
rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5} = rng[11:7];
endmodule | 1 |
4,374 | data/full_repos/permissive/109594910/example-1k.v | 109,594,910 | example-1k.v | v | 38 | 95 | [] | [] | [] | null | line:13: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'rng\' generates 32 bits.\n : ... In instance top\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]}); \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 33 bits.\n : ... In instance top\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]}); \n ^~\n%Error: Exiting due to 2 warning(s)\n' | 2,612 | function | function [BITS-1:0] bin2gray(input [BITS-1:0] in);
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | function [BITS-1:0] bin2gray(input [BITS-1:0] in); |
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | 1 |
4,375 | data/full_repos/permissive/109594910/example-8k.v | 109,594,910 | example-8k.v | v | 68 | 114 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Error: data/full_repos/permissive/109594910/example-8k.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("top_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example-8k.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:54: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 30000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,613 | module | module top (
input clk,
input sel,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
localparam BITS = 8;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2]) rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
endmodule | module top (
input clk,
input sel,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
); |
localparam BITS = 8;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2]) rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
endmodule | 1 |
4,376 | data/full_repos/permissive/109594910/example-8k.v | 109,594,910 | example-8k.v | v | 68 | 114 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Error: data/full_repos/permissive/109594910/example-8k.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("top_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example-8k.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:54: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 30000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,613 | module | module top_tb;
reg sel = 0;
initial begin
$dumpfile("top_tb.vcd");
$dumpvars(0,top_tb);
# 10000 sel = 1;
# 10000 sel = 0;
# 30000 $finish;
end
reg clk = 0;
always #1 clk = !clk;
wire [7:0] LED;
top uut (clk, sel, LED);
endmodule | module top_tb; |
reg sel = 0;
initial begin
$dumpfile("top_tb.vcd");
$dumpvars(0,top_tb);
# 10000 sel = 1;
# 10000 sel = 0;
# 30000 $finish;
end
reg clk = 0;
always #1 clk = !clk;
wire [7:0] LED;
top uut (clk, sel, LED);
endmodule | 1 |
4,377 | data/full_repos/permissive/109594910/example-8k.v | 109,594,910 | example-8k.v | v | 68 | 114 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Error: data/full_repos/permissive/109594910/example-8k.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("top_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example-8k.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:54: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 30000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,613 | function | function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | function [BITS-1:0] bin2gray(input [BITS+1:0] in); |
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | 1 |
4,378 | data/full_repos/permissive/109594910/example_tb.v | 109,594,910 | example_tb.v | v | 23 | 99 | [] | [] | [] | null | line:11: before: "$" | null | 1: b'%Error: data/full_repos/permissive/109594910/example_tb.v:6: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("example_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example_tb.v:7: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n # 10000 sel = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n # 900000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n ^\n%Error: data/full_repos/permissive/109594910/example_tb.v:20: syntax error, unexpected \'=\', expecting \')\'\n top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,615 | module | module top_tb;
reg sel = 0;
initial begin
$dumpfile("example_tb.vcd");
$dumpvars(0,top_tb);
# 10000 sel = 1;
# 10000 sel = 0;
# 900000 $finish;
end
reg clk = 0;
always #1 clk = !clk;
wire [7:0] LED;
top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);
endmodule | module top_tb; |
reg sel = 0;
initial begin
$dumpfile("example_tb.vcd");
$dumpvars(0,top_tb);
# 10000 sel = 1;
# 10000 sel = 0;
# 900000 $finish;
end
reg clk = 0;
always #1 clk = !clk;
wire [7:0] LED;
top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);
endmodule | 1 |
4,380 | data/full_repos/permissive/109594910/vga.v | 109,594,910 | vga.v | v | 186 | 80 | [] | [] | [] | [(1, 185)] | null | null | 1: b"%Error: data/full_repos/permissive/109594910/vga.v:20: Duplicate declaration of signal: 'clk_vga'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire clk_vga;\n ^~~~~~~\n data/full_repos/permissive/109594910/vga.v:2: ... Location of original declaration\n input clk_vga,\n ^~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:21: Duplicate declaration of signal: 'vga_frame'\n reg [7:0] vga_frame = 0;\n ^~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:3: ... Location of original declaration\n output [7:0] vga_frame,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_r'\n wire [3:0] vga_r, vga_g, vga_b;\n ^~~~~\n data/full_repos/permissive/109594910/vga.v:4: ... Location of original declaration\n output [3:0] vga_r,\n ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_g'\n wire [3:0] vga_r, vga_g, vga_b;\n ^~~~~\n data/full_repos/permissive/109594910/vga.v:5: ... Location of original declaration\n output [3:0] vga_g,\n ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_b'\n wire [3:0] vga_r, vga_g, vga_b;\n ^~~~~\n data/full_repos/permissive/109594910/vga.v:6: ... Location of original declaration\n output [3:0] vga_b,\n ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_hs'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~\n data/full_repos/permissive/109594910/vga.v:7: ... Location of original declaration\n output vga_hs,\n ^~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_vs'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~\n data/full_repos/permissive/109594910/vga.v:8: ... Location of original declaration\n output vga_vs,\n ^~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_blank'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:9: ... Location of original declaration\n output vga_blank,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'fetch_cell'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:13: ... Location of original declaration\n output fetch_cell,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'fetch_font'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:14: ... Location of original declaration\n output fetch_font,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'load_nshift'\n wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift; \n ^~~~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:15: ... Location of original declaration\n output load_nshift,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:24: Duplicate declaration of signal: 'cell_addr'\n reg [11:0] cell_addr;\n ^~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:16: ... Location of original declaration\n output [11:0] cell_addr,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:69: Duplicate declaration of signal: 'hpos'\n reg [9:0] hpos = -hfp;\n ^~~~\n data/full_repos/permissive/109594910/vga.v:17: ... Location of original declaration\n output [9:0] hpos,\n ^~~~\n%Error: data/full_repos/permissive/109594910/vga.v:70: Duplicate declaration of signal: 'vpos'\n reg [9:0] vpos = -vfp;\n ^~~~\n data/full_repos/permissive/109594910/vga.v:18: ... Location of original declaration\n output [9:0] vpos\n ^~~~\n%Error: data/full_repos/permissive/109594910/vga.v:91: Duplicate declaration of signal: 'fetch_start'\n wire fetch_start = hpos == -10'd9;\n ^~~~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:12: ... Location of original declaration\n output fetch_start,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:93: Duplicate declaration of signal: 'fetch_first'\n wire fetch_first = vpos == 0;\n ^~~~~~~~~~~\n data/full_repos/permissive/109594910/vga.v:10: ... Location of original declaration\n output fetch_first,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:94: Duplicate declaration of signal: 'line_top'\n wire line_top = vpos[3:0] == 0;\n ^~~~~~~~\n data/full_repos/permissive/109594910/vga.v:11: ... Location of original declaration\n output line_top,\n ^~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 2,617 | module | module vga (
input clk_vga,
output [7:0] vga_frame,
output [3:0] vga_r,
output [3:0] vga_g,
output [3:0] vga_b,
output vga_hs,
output vga_vs,
output vga_blank,
output fetch_first,
output line_top,
output fetch_start,
output fetch_cell,
output fetch_font,
output load_nshift,
output [11:0] cell_addr,
output [9:0] hpos,
output [9:0] vpos
);
wire clk_vga;
reg [7:0] vga_frame = 0;
wire [3:0] vga_r, vga_g, vga_b;
wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;
reg [11:0] cell_addr;
localparam hfp = 10'd18;
localparam hsp = 10'd108;
localparam hbp = 10'd54;
localparam hactive = 10'd720;
localparam htotal = hactive + hfp + hsp + hbp;
localparam hend = hactive + hfp + hsp - 1;
localparam hstart = -hbp;
localparam vfp = 10'd13;
localparam vsp = 10'd2;
localparam vbp = 10'd34;
localparam vactive = 10'd400;
localparam vtotal = vactive + vfp + vsp + vbp;
localparam vend = vactive + vfp + vsp - 1;
localparam vstart = -vbp;
reg [9:0] hpos = -hfp;
reg [9:0] vpos = -vfp;
wire hblank_start = hpos == hactive - 1;
wire hblank_stop = hpos == -10'd1;
wire hsync_start = hpos == (hactive + hfp) - 1;
wire hsync_stop = hpos == (hactive + hfp + hsp) - 1;
wire hreset = hpos == hend;
wire vblank_start = vpos == vactive;
wire vblank_stop = vpos == 10'd0;
wire vsync_start = vpos == (vactive + vfp);
wire vsync_stop = vpos == vstart;
wire vreset = vpos == vend;
reg hblank=1;
reg vblank=1;
reg hsync=0;
reg vsync=0;
wire fetch_start = hpos == -10'd9;
wire fetch_stop = hpos == hactive - 9;
wire fetch_first = vpos == 0;
wire line_top = vpos[3:0] == 0;
reg fetching=0;
always@(posedge clk_vga) begin
if (hreset) begin
hpos <= hstart;
if (vreset) begin
vpos <= vstart;
vga_frame <= vga_frame + 1;
end else
vpos <= vpos + 1;
end else begin
hpos <= (hpos + 1);
end
end
always@(posedge clk_vga) begin
hblank <= hblank_start ? 1 : (hblank_stop ? 0 : hblank);
hsync <= hsync_start ? 1 : (hsync_stop ? 0 : hsync);
vblank <= vblank_start ? 1 : (vblank_stop ? 0 : vblank);
vsync <= vsync_start ? 1 : (vsync_stop ? 0 : vsync);
fetching <= fetch_start ? ~vblank : (fetch_stop ? 0 : fetching);
end
assign vga_hs = ~hsync;
assign vga_vs = vsync;
wire blank = vblank | hblank;
assign fetch_cell = fetching ? hpos[2:0] == 3'b000 : 0;
assign fetch_font = fetching ? hpos[2:0] == 3'b100 : 0;
assign load_nshift = fetching ? hpos[2:0] == 3'b111 : 0;
reg new_line;
reg [11:0] text_line_addr;
always @(posedge clk_vga) begin
new_line <= hreset;
if (new_line) begin
if (vpos == 0) begin
cell_addr <= 0;
text_line_addr <= 0;
end else if (line_top) begin
text_line_addr <= cell_addr;
end else begin
cell_addr <= text_line_addr;
end
end
if (fetch_cell)
cell_addr <= cell_addr + 1;
end
wire border = ((hpos == 0) || (hpos == hactive - 1) ||
(vpos == 0) || (vpos == vactive -1) ||
(hpos == hactive / 2) || (vpos == vactive / 2));
wire [3:0] rgbi = blank ? 4'h0 : (border ? 4'hf : hpos[8:5] ^ vpos[7:4]);
wire r = rgbi[2];
wire g = rgbi[1];
wire b = rgbi[0];
wire i = rgbi[3];
wire [7:0] rgbii = blank ? 8'h0 : (border ? 8'hff : hpos[8:1] - vpos[7:0]);
wire [1:0] bb = rgbii[1:0];
wire [1:0] gg = rgbii[3:2];
wire [1:0] rr = rgbii[5:4];
wire [1:0] ii = rgbii[7:6];
wire left = hpos < hactive /2;
assign vga_r = left?{rr[1], ii[1], rr[0], ii[0]}:{rr,ii};
assign vga_g = left?{gg[1], ii[1], gg[0], gg[0]}:{gg,ii};
assign vga_b = left?{bb[1], ii[1], bb[0], bb[0]}:{bb,ii};
assign vga_blank = blank;
endmodule | module vga (
input clk_vga,
output [7:0] vga_frame,
output [3:0] vga_r,
output [3:0] vga_g,
output [3:0] vga_b,
output vga_hs,
output vga_vs,
output vga_blank,
output fetch_first,
output line_top,
output fetch_start,
output fetch_cell,
output fetch_font,
output load_nshift,
output [11:0] cell_addr,
output [9:0] hpos,
output [9:0] vpos
); |
wire clk_vga;
reg [7:0] vga_frame = 0;
wire [3:0] vga_r, vga_g, vga_b;
wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;
reg [11:0] cell_addr;
localparam hfp = 10'd18;
localparam hsp = 10'd108;
localparam hbp = 10'd54;
localparam hactive = 10'd720;
localparam htotal = hactive + hfp + hsp + hbp;
localparam hend = hactive + hfp + hsp - 1;
localparam hstart = -hbp;
localparam vfp = 10'd13;
localparam vsp = 10'd2;
localparam vbp = 10'd34;
localparam vactive = 10'd400;
localparam vtotal = vactive + vfp + vsp + vbp;
localparam vend = vactive + vfp + vsp - 1;
localparam vstart = -vbp;
reg [9:0] hpos = -hfp;
reg [9:0] vpos = -vfp;
wire hblank_start = hpos == hactive - 1;
wire hblank_stop = hpos == -10'd1;
wire hsync_start = hpos == (hactive + hfp) - 1;
wire hsync_stop = hpos == (hactive + hfp + hsp) - 1;
wire hreset = hpos == hend;
wire vblank_start = vpos == vactive;
wire vblank_stop = vpos == 10'd0;
wire vsync_start = vpos == (vactive + vfp);
wire vsync_stop = vpos == vstart;
wire vreset = vpos == vend;
reg hblank=1;
reg vblank=1;
reg hsync=0;
reg vsync=0;
wire fetch_start = hpos == -10'd9;
wire fetch_stop = hpos == hactive - 9;
wire fetch_first = vpos == 0;
wire line_top = vpos[3:0] == 0;
reg fetching=0;
always@(posedge clk_vga) begin
if (hreset) begin
hpos <= hstart;
if (vreset) begin
vpos <= vstart;
vga_frame <= vga_frame + 1;
end else
vpos <= vpos + 1;
end else begin
hpos <= (hpos + 1);
end
end
always@(posedge clk_vga) begin
hblank <= hblank_start ? 1 : (hblank_stop ? 0 : hblank);
hsync <= hsync_start ? 1 : (hsync_stop ? 0 : hsync);
vblank <= vblank_start ? 1 : (vblank_stop ? 0 : vblank);
vsync <= vsync_start ? 1 : (vsync_stop ? 0 : vsync);
fetching <= fetch_start ? ~vblank : (fetch_stop ? 0 : fetching);
end
assign vga_hs = ~hsync;
assign vga_vs = vsync;
wire blank = vblank | hblank;
assign fetch_cell = fetching ? hpos[2:0] == 3'b000 : 0;
assign fetch_font = fetching ? hpos[2:0] == 3'b100 : 0;
assign load_nshift = fetching ? hpos[2:0] == 3'b111 : 0;
reg new_line;
reg [11:0] text_line_addr;
always @(posedge clk_vga) begin
new_line <= hreset;
if (new_line) begin
if (vpos == 0) begin
cell_addr <= 0;
text_line_addr <= 0;
end else if (line_top) begin
text_line_addr <= cell_addr;
end else begin
cell_addr <= text_line_addr;
end
end
if (fetch_cell)
cell_addr <= cell_addr + 1;
end
wire border = ((hpos == 0) || (hpos == hactive - 1) ||
(vpos == 0) || (vpos == vactive -1) ||
(hpos == hactive / 2) || (vpos == vactive / 2));
wire [3:0] rgbi = blank ? 4'h0 : (border ? 4'hf : hpos[8:5] ^ vpos[7:4]);
wire r = rgbi[2];
wire g = rgbi[1];
wire b = rgbi[0];
wire i = rgbi[3];
wire [7:0] rgbii = blank ? 8'h0 : (border ? 8'hff : hpos[8:1] - vpos[7:0]);
wire [1:0] bb = rgbii[1:0];
wire [1:0] gg = rgbii[3:2];
wire [1:0] rr = rgbii[5:4];
wire [1:0] ii = rgbii[7:6];
wire left = hpos < hactive /2;
assign vga_r = left?{rr[1], ii[1], rr[0], ii[0]}:{rr,ii};
assign vga_g = left?{gg[1], ii[1], gg[0], gg[0]}:{gg,ii};
assign vga_b = left?{bb[1], ii[1], bb[0], bb[0]}:{bb,ii};
assign vga_blank = blank;
endmodule | 1 |
4,382 | data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v | 109,594,910 | blink_100mhz_from_12mhz.v | v | 201 | 108 | [] | [] | [] | null | line:47: before: ")" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:21: Signal definition not found, creating implicitly: \'clk_100mhz\'\n : ... Suggested alternative: \'clk_12mhz\'\n always @(posedge clk_100mhz)\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:35: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE.v\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE.sv\n SB_PLL40_CORE\n SB_PLL40_CORE.v\n SB_PLL40_CORE.sv\n obj_dir/SB_PLL40_CORE\n obj_dir/SB_PLL40_CORE.v\n obj_dir/SB_PLL40_CORE.sv\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:85: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'rng\' generates 32 bits.\n : ... In instance blink_100mhz_from_12mhz\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});\n ^\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:85: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 33 bits.\n : ... In instance blink_100mhz_from_12mhz\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:88: Operator FUNCREF \'bin2gray\' expects 10 bits on the Function Argument, but Function Argument\'s SHIFTR generates 30 bits.\n : ... In instance blink_100mhz_from_12mhz\n assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:88: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance blink_100mhz_from_12mhz\n assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 2,619 | module | module blink_100mhz_from_12mhz (
input clk_12mhz,
input sel,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8,
output pin_c16,
output pin_d16
);
reg [24:0] ring = 25'hAAAAAA;
always @(posedge clk_100mhz)
ring <= ({ring[0],ring[24:1]});
wire f_feedback = ring[0];
wire pll_locked;
SB_PLL40_CORE #(
.FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b0000),
.FDA_RELATIVE(4'b0000),
.DIVR(4'b0000),
.DIVF(7'b0000011),
.DIVQ(3'b011),
.FILTER_RANGE(3'b001),
) uut (
.REFERENCECLK (clk_12mhz),
.PLLOUTGLOBAL (clk_100mhz),
.BYPASS (1'b0),
.RESETB (1'b1),
.EXTFEEDBACK (f_feedback),
.LOCK (pll_locked)
);
localparam BITS = 8;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk_100mhz)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2])
rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
reg [25:0] s_counter =0;
reg second = 0;
always @(posedge clk_100mhz) begin
if (s_counter == 50000000) begin
s_counter <= 1;
second <= ~second;
end
else
s_counter <= s_counter + 1;
end
assign LED8 = second;
reg [18:0] slow_counter = 0;
always @(posedge clk_12mhz) slow_counter <= slow_counter +1;
wire slow_signal = (slow_counter[18:9] == 0);
assign pin_c16 = slow_signal;
wire input_signal = slow_signal;
reg [2:0] input_sync = 0;
wire input_synced;
assign input_synced = input_sync[2];
always @(posedge clk_100mhz)
input_sync <= ({input_sync[1:0], input_signal});
reg [30:0] pulselen_counter = 0;
reg [30:0] last_pulselen = 0;
wire pulselen_valid = (last_pulselen != 0);
always @(posedge clk_100mhz) begin
if (input_synced)
pulselen_counter <= pulselen_counter + 1;
else
if (pulselen_counter > 0) begin
last_pulselen <= pulselen_counter;
pulselen_counter <= 0;
end
end
reg last_input = 0;
reg [31:0] cycle_counter = 0;
reg [31:0] last_cycle = 0;
wire cycle_valid = (last_cycle > 0);
wire [1:0] trig_check = ({last_input, input_synced});
always @(posedge clk_100mhz) begin
last_input <= input_synced;
if (trig_check == 2'b01) begin
last_cycle <= cycle_counter;
cycle_counter <= 0;
end else
cycle_counter <= cycle_counter +1;
end
reg [31:0] gen_counter = 0;
wire start_pulse = ((gen_counter >= last_cycle) ||(cycle_counter == 0));
always @(posedge clk_100mhz) begin
if (cycle_valid && pulselen_valid && (cycle_counter != 0)) begin
gen_counter <= (start_pulse)?(gen_counter-last_cycle):(gen_counter + 3);
end else gen_counter <= 0;
end
reg [30:0] gen_pulsectr = 0;
wire active = (gen_pulsectr > 0);
always @(posedge clk_100mhz) begin
if (start_pulse && ~active)
gen_pulsectr <= last_pulselen;
else
gen_pulsectr <= (active)?gen_pulsectr-1:0;
end
assign pin_d16 = active;
endmodule | module blink_100mhz_from_12mhz (
input clk_12mhz,
input sel,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8,
output pin_c16,
output pin_d16
); |
reg [24:0] ring = 25'hAAAAAA;
always @(posedge clk_100mhz)
ring <= ({ring[0],ring[24:1]});
wire f_feedback = ring[0];
wire pll_locked;
SB_PLL40_CORE #(
.FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b0000),
.FDA_RELATIVE(4'b0000),
.DIVR(4'b0000),
.DIVF(7'b0000011),
.DIVQ(3'b011),
.FILTER_RANGE(3'b001),
) uut (
.REFERENCECLK (clk_12mhz),
.PLLOUTGLOBAL (clk_100mhz),
.BYPASS (1'b0),
.RESETB (1'b1),
.EXTFEEDBACK (f_feedback),
.LOCK (pll_locked)
);
localparam BITS = 8;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction
reg [BITS+LOG2DELAY-1:0] counter = 0;
always@(posedge clk_100mhz)
counter <= counter + 1;
reg [31:0] rng = 32'h00010000;
always@(posedge counter[LOG2DELAY-2])
rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
reg [25:0] s_counter =0;
reg second = 0;
always @(posedge clk_100mhz) begin
if (s_counter == 50000000) begin
s_counter <= 1;
second <= ~second;
end
else
s_counter <= s_counter + 1;
end
assign LED8 = second;
reg [18:0] slow_counter = 0;
always @(posedge clk_12mhz) slow_counter <= slow_counter +1;
wire slow_signal = (slow_counter[18:9] == 0);
assign pin_c16 = slow_signal;
wire input_signal = slow_signal;
reg [2:0] input_sync = 0;
wire input_synced;
assign input_synced = input_sync[2];
always @(posedge clk_100mhz)
input_sync <= ({input_sync[1:0], input_signal});
reg [30:0] pulselen_counter = 0;
reg [30:0] last_pulselen = 0;
wire pulselen_valid = (last_pulselen != 0);
always @(posedge clk_100mhz) begin
if (input_synced)
pulselen_counter <= pulselen_counter + 1;
else
if (pulselen_counter > 0) begin
last_pulselen <= pulselen_counter;
pulselen_counter <= 0;
end
end
reg last_input = 0;
reg [31:0] cycle_counter = 0;
reg [31:0] last_cycle = 0;
wire cycle_valid = (last_cycle > 0);
wire [1:0] trig_check = ({last_input, input_synced});
always @(posedge clk_100mhz) begin
last_input <= input_synced;
if (trig_check == 2'b01) begin
last_cycle <= cycle_counter;
cycle_counter <= 0;
end else
cycle_counter <= cycle_counter +1;
end
reg [31:0] gen_counter = 0;
wire start_pulse = ((gen_counter >= last_cycle) ||(cycle_counter == 0));
always @(posedge clk_100mhz) begin
if (cycle_valid && pulselen_valid && (cycle_counter != 0)) begin
gen_counter <= (start_pulse)?(gen_counter-last_cycle):(gen_counter + 3);
end else gen_counter <= 0;
end
reg [30:0] gen_pulsectr = 0;
wire active = (gen_pulsectr > 0);
always @(posedge clk_100mhz) begin
if (start_pulse && ~active)
gen_pulsectr <= last_pulselen;
else
gen_pulsectr <= (active)?gen_pulsectr-1:0;
end
assign pin_d16 = active;
endmodule | 1 |
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