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4,383 | data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v | 109,594,910 | blink_100mhz_from_12mhz.v | v | 201 | 108 | [] | [] | [] | null | line:47: before: ")" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:21: Signal definition not found, creating implicitly: \'clk_100mhz\'\n : ... Suggested alternative: \'clk_12mhz\'\n always @(posedge clk_100mhz)\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:35: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE.v\n data/full_repos/permissive/109594910/examples,data/full_repos/permissive/109594910/SB_PLL40_CORE.sv\n SB_PLL40_CORE\n SB_PLL40_CORE.v\n SB_PLL40_CORE.sv\n obj_dir/SB_PLL40_CORE\n obj_dir/SB_PLL40_CORE.v\n obj_dir/SB_PLL40_CORE.sv\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:85: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'rng\' generates 32 bits.\n : ... In instance blink_100mhz_from_12mhz\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});\n ^\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:85: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 33 bits.\n : ... In instance blink_100mhz_from_12mhz\n rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});\n ^~\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:88: Operator FUNCREF \'bin2gray\' expects 10 bits on the Function Argument, but Function Argument\'s SHIFTR generates 30 bits.\n : ... In instance blink_100mhz_from_12mhz\n assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109594910/examples/blink_100mhz_from_12mhz.v:88: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance blink_100mhz_from_12mhz\n assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 2,619 | function | function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | function [BITS-1:0] bin2gray(input [BITS+1:0] in); |
integer i;
reg [BITS+1:0] temp;
begin
temp = in;
for (i=0; i<BITS; i=i+1)
bin2gray[i] = ^temp[i +: 2];
end
endfunction | 1 |
4,384 | data/full_repos/permissive/109608368/Hexdisplay.v | 109,608,368 | Hexdisplay.v | v | 54 | 72 | [] | ['general public license', 'free software foundation'] | [] | [(22, 53)] | null | data/verilator_xmls/205be9bd-3ec5-476d-a1a1-31a2d6f9ff33.xml | null | 2,624 | module | module Hexdisplay(out, in);
input [3:0] in;
output [6:0] out;
reg [6:0] num;
always @ (*)
begin
case (in[3:0])
4'b0000: num[6:0] = 7'b1000000;
4'b0001: num[6:0] = 7'b1111001;
4'b0010: num[6:0] = 7'b0100100;
4'b0011: num[6:0] = 7'b0110000;
4'b0100: num[6:0] = 7'b0011001;
4'b0101: num[6:0] = 7'b0010010;
4'b0110: num[6:0] = 7'b0000010;
4'b0111: num[6:0] = 7'b1111000;
4'b1000: num[6:0] = 7'b0000000;
4'b1001: num[6:0] = 7'b0010000;
4'b1010: num[6:0] = 7'b0001000;
4'b1011: num[6:0] = 7'b0000011;
4'b1100: num[6:0] = 7'b1000110;
4'b1101: num[6:0] = 7'b0100001;
4'b1110: num[6:0] = 7'b0000110;
4'b1111: num[6:0] = 7'b0001110;
default: num[6:0] = 7'b1111111;
endcase
end
assign out[6:0] = num[6:0];
endmodule | module Hexdisplay(out, in); |
input [3:0] in;
output [6:0] out;
reg [6:0] num;
always @ (*)
begin
case (in[3:0])
4'b0000: num[6:0] = 7'b1000000;
4'b0001: num[6:0] = 7'b1111001;
4'b0010: num[6:0] = 7'b0100100;
4'b0011: num[6:0] = 7'b0110000;
4'b0100: num[6:0] = 7'b0011001;
4'b0101: num[6:0] = 7'b0010010;
4'b0110: num[6:0] = 7'b0000010;
4'b0111: num[6:0] = 7'b1111000;
4'b1000: num[6:0] = 7'b0000000;
4'b1001: num[6:0] = 7'b0010000;
4'b1010: num[6:0] = 7'b0001000;
4'b1011: num[6:0] = 7'b0000011;
4'b1100: num[6:0] = 7'b1000110;
4'b1101: num[6:0] = 7'b0100001;
4'b1110: num[6:0] = 7'b0000110;
4'b1111: num[6:0] = 7'b0001110;
default: num[6:0] = 7'b1111111;
endcase
end
assign out[6:0] = num[6:0];
endmodule | 0 |
4,385 | data/full_repos/permissive/109608368/check/All_Check.v | 109,608,368 | All_Check.v | v | 929 | 144 | [] | ['general public license', 'free software foundation'] | [] | [(23, 928)] | null | null | 1: b"%Error: data/full_repos/permissive/109608368/check/All_Check.v:42: Cannot find file containing module: 'Checker'\n Checker row0_1(.a(memory[ROW_0+9'd1:ROW_0+9'd0]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/109608368/check,data/full_repos/permissive/109608368/Checker\n data/full_repos/permissive/109608368/check,data/full_repos/permissive/109608368/Checker.v\n data/full_repos/permissive/109608368/check,data/full_repos/permissive/109608368/Checker.sv\n Checker\n Checker.v\n Checker.sv\n obj_dir/Checker\n obj_dir/Checker.v\n obj_dir/Checker.sv\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:44: Cannot find file containing module: 'Checker'\n Checker row0_2(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:46: Cannot find file containing module: 'Checker'\n Checker row0_3(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:48: Cannot find file containing module: 'Checker'\n Checker row0_4(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:50: Cannot find file containing module: 'Checker'\n Checker row0_5(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:52: Cannot find file containing module: 'Checker'\n Checker row0_6(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:54: Cannot find file containing module: 'Checker'\n Checker row0_7(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:56: Cannot find file containing module: 'Checker'\n Checker row0_8(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:58: Cannot find file containing module: 'Checker'\n Checker row0_9(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:60: Cannot find file containing module: 'Checker'\n Checker row0_10(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:62: Cannot find file containing module: 'Checker'\n Checker row0_11(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:64: Cannot find file containing module: 'Checker'\n Checker row0_12(.a(memory[ROW_0+9'd31:ROW_0+9'd30]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:67: Cannot find file containing module: 'Summarize12'\n Summarize12 row0_sum(.check_ans(row_ans[23:0]), .out(row_sum[1:0]));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:71: Cannot find file containing module: 'Checker'\n Checker row1_1(.a(memory[ROW_1+9'd1:ROW_1+9'd0]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:73: Cannot find file containing module: 'Checker'\n Checker row1_2(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:75: Cannot find file containing module: 'Checker'\n Checker row1_3(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:77: Cannot find file containing module: 'Checker'\n Checker row1_4(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:79: Cannot find file containing module: 'Checker'\n Checker row1_5(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:81: Cannot find file containing module: 'Checker'\n Checker row1_6(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:83: Cannot find file containing module: 'Checker'\n Checker row1_7(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:85: Cannot find file containing module: 'Checker'\n Checker row1_8(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:87: Cannot find file containing module: 'Checker'\n Checker row1_9(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:89: Cannot find file containing module: 'Checker'\n Checker row1_10(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:91: Cannot find file containing module: 'Checker'\n Checker row1_11(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:93: Cannot find file containing module: 'Checker'\n Checker row1_12(.a(memory[ROW_1+9'd31:ROW_1+9'd30]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:96: Cannot find file containing module: 'Summarize12'\n Summarize12 row1_sum(.check_ans(row_ans[47:24]), .out(row_sum[3:2]));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:100: Cannot find file containing module: 'Checker'\n Checker row2_1(.a(memory[ROW_2+9'd1:ROW_2+9'd0]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:102: Cannot find file containing module: 'Checker'\n Checker row2_2(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:104: Cannot find file containing module: 'Checker'\n Checker row2_3(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:106: Cannot find file containing module: 'Checker'\n Checker row2_4(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:108: Cannot find file containing module: 'Checker'\n Checker row2_5(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:110: Cannot find file containing module: 'Checker'\n Checker row2_6(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:112: Cannot find file containing module: 'Checker'\n Checker row2_7(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:114: Cannot find file containing module: 'Checker'\n Checker row2_8(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:116: Cannot find file containing module: 'Checker'\n Checker row2_9(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:118: Cannot find file containing module: 'Checker'\n Checker row2_10(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:120: Cannot find file containing module: 'Checker'\n Checker row2_11(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:122: Cannot find file containing module: 'Checker'\n Checker row2_12(.a(memory[ROW_2+9'd31:ROW_2+9'd30]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:125: Cannot find file containing module: 'Summarize12'\n Summarize12 row2_sum(.check_ans(row_ans[71:48]), .out(row_sum[5:4]));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:129: Cannot find file containing module: 'Checker'\n Checker row3_1(.a(memory[ROW_3+9'd1:ROW_3+9'd0]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:131: Cannot find file containing module: 'Checker'\n Checker row3_2(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:133: Cannot find file containing module: 'Checker'\n Checker row3_3(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:135: Cannot find file containing module: 'Checker'\n Checker row3_4(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:137: Cannot find file containing module: 'Checker'\n Checker row3_5(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:139: Cannot find file containing module: 'Checker'\n Checker row3_6(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:141: Cannot find file containing module: 'Checker'\n Checker row3_7(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:143: Cannot find file containing module: 'Checker'\n Checker row3_8(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:145: Cannot find file containing module: 'Checker'\n Checker row3_9(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:147: Cannot find file containing module: 'Checker'\n Checker row3_10(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),\n ^~~~~~~\n%Error: data/full_repos/permissive/109608368/check/All_Check.v:149: Cannot find file containing module: 'Checker'\n Checker row3_11(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 2,625 | module | module All_Check(memory, ans);
input [511:0] memory;
output reg [1:0] ans;
wire [383:0] row_ans, col_ans;
wire [31:0] row_sum, col_sum;
localparam ROW_0 = 9'd0, ROW_1 = 9'd32, ROW_2 = 9'd64, ROW_3 = 9'd96, ROW_4 = 9'd128,
ROW_5 = 9'd160, ROW_6 = 9'd192, ROW_7 = 9'd224, ROW_8 = 9'd256, ROW_9 = 9'd288,
ROW_10 = 9'd320, ROW_11 = 9'd352, ROW_12 = 9'd384, ROW_13 = 9'd416,
ROW_14 = 9'd448, ROW_15 = 9'd480;
localparam COL_0 = 9'd0, COL_1 = 9'd2, COL_2 = 9'd4, COL_3 = 9'd6, COL_4 = 9'd8,
COL_5 = 9'd10, COL_6 = 9'd12, COL_7 = 9'd14, COL_8 = 9'd16, COL_9 = 9'd18,
COL_10 = 9'd20, COL_11 = 9'd22, COL_12 = 9'd24, COL_13 = 9'd26,
COL_14 = 9'd28, COL_15 = 9'd30;
Checker row0_1(.a(memory[ROW_0+9'd1:ROW_0+9'd0]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[1:0]));
Checker row0_2(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[3:2]));
Checker row0_3(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[5:4]));
Checker row0_4(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[7:6]));
Checker row0_5(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[9:8]));
Checker row0_6(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[11:10]));
Checker row0_7(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[13:12]));
Checker row0_8(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[15:14]));
Checker row0_9(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[17:16]));
Checker row0_10(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[19:18]));
Checker row0_11(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd29:ROW_0+9'd28]), .ans(row_ans[21:20]));
Checker row0_12(.a(memory[ROW_0+9'd31:ROW_0+9'd30]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd29:ROW_0+9'd28]), .ans(row_ans[23:22]));
Summarize12 row0_sum(.check_ans(row_ans[23:0]), .out(row_sum[1:0]));
Checker row1_1(.a(memory[ROW_1+9'd1:ROW_1+9'd0]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[25:24]));
Checker row1_2(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[27:26]));
Checker row1_3(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[29:28]));
Checker row1_4(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[31:30]));
Checker row1_5(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[33:32]));
Checker row1_6(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[35:34]));
Checker row1_7(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[37:36]));
Checker row1_8(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[39:38]));
Checker row1_9(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[41:40]));
Checker row1_10(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[43:42]));
Checker row1_11(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd29:ROW_1+9'd28]), .ans(row_ans[45:44]));
Checker row1_12(.a(memory[ROW_1+9'd31:ROW_1+9'd30]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd29:ROW_1+9'd28]), .ans(row_ans[47:46]));
Summarize12 row1_sum(.check_ans(row_ans[47:24]), .out(row_sum[3:2]));
Checker row2_1(.a(memory[ROW_2+9'd1:ROW_2+9'd0]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[49:48]));
Checker row2_2(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[51:50]));
Checker row2_3(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[53:52]));
Checker row2_4(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[55:54]));
Checker row2_5(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[57:56]));
Checker row2_6(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[59:58]));
Checker row2_7(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[61:60]));
Checker row2_8(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[63:62]));
Checker row2_9(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[65:64]));
Checker row2_10(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[67:66]));
Checker row2_11(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd29:ROW_2+9'd28]), .ans(row_ans[69:68]));
Checker row2_12(.a(memory[ROW_2+9'd31:ROW_2+9'd30]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd29:ROW_2+9'd28]), .ans(row_ans[71:70]));
Summarize12 row2_sum(.check_ans(row_ans[71:48]), .out(row_sum[5:4]));
Checker row3_1(.a(memory[ROW_3+9'd1:ROW_3+9'd0]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[73:72]));
Checker row3_2(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[75:74]));
Checker row3_3(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[77:76]));
Checker row3_4(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[79:78]));
Checker row3_5(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[81:80]));
Checker row3_6(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[83:82]));
Checker row3_7(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[85:84]));
Checker row3_8(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[87:86]));
Checker row3_9(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[89:88]));
Checker row3_10(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[91:90]));
Checker row3_11(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd29:ROW_3+9'd28]), .ans(row_ans[93:92]));
Checker row3_12(.a(memory[ROW_3+9'd31:ROW_3+9'd30]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd29:ROW_3+9'd28]), .ans(row_ans[95:94]));
Summarize12 row3_sum(.check_ans(row_ans[95:72]), .out(row_sum[7:6]));
Checker row4_1(.a(memory[ROW_4+9'd1:ROW_4+9'd0]), .b(memory[ROW_4+9'd3:ROW_4+9'd2]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[97:96]));
Checker row4_2(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd3:ROW_4+9'd2]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[99:98]));
Checker row4_3(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[101:100]));
Checker row4_4(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[103:102]));
Checker row4_5(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[105:104]));
Checker row4_6(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[107:106]));
Checker row4_7(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[109:108]));
Checker row4_8(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[111:110]));
Checker row4_9(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[113:112]));
Checker row4_10(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[115:114]));
Checker row4_11(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd29:ROW_4+9'd28]), .ans(row_ans[117:116]));
Checker row4_12(.a(memory[ROW_4+9'd31:ROW_4+9'd30]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd29:ROW_4+9'd28]), .ans(row_ans[119:118]));
Summarize12 row4_sum(.check_ans(row_ans[119:96]), .out(row_sum[9:8]));
Checker row5_1(.a(memory[ROW_5+9'd1:ROW_5+9'd0]), .b(memory[ROW_5+9'd3:ROW_5+9'd2]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[121:120]));
Checker row5_2(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd3:ROW_5+9'd2]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[123:122]));
Checker row5_3(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[125:124]));
Checker row5_4(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[127:126]));
Checker row5_5(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[129:128]));
Checker row5_6(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[131:130]));
Checker row5_7(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[133:132]));
Checker row5_8(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[135:134]));
Checker row5_9(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[137:136]));
Checker row5_10(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[139:138]));
Checker row5_11(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd29:ROW_5+9'd28]), .ans(row_ans[141:140]));
Checker row5_12(.a(memory[ROW_5+9'd31:ROW_5+9'd30]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd29:ROW_5+9'd28]), .ans(row_ans[143:142]));
Summarize12 row5_sum(.check_ans(row_ans[143:120]), .out(row_sum[11:10]));
Checker row6_1(.a(memory[ROW_6+9'd1:ROW_6+9'd0]), .b(memory[ROW_6+9'd3:ROW_6+9'd2]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[145:144]));
Checker row6_2(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd3:ROW_6+9'd2]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[147:146]));
Checker row6_3(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[149:148]));
Checker row6_4(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[151:150]));
Checker row6_5(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[153:152]));
Checker row6_6(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[155:154]));
Checker row6_7(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[157:156]));
Checker row6_8(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[159:158]));
Checker row6_9(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[161:160]));
Checker row6_10(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[163:162]));
Checker row6_11(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd29:ROW_6+9'd28]), .ans(row_ans[165:164]));
Checker row6_12(.a(memory[ROW_6+9'd31:ROW_6+9'd30]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd29:ROW_6+9'd28]), .ans(row_ans[167:166]));
Summarize12 row6_sum(.check_ans(row_ans[167:144]), .out(row_sum[13:12]));
Checker row7_1(.a(memory[ROW_7+9'd1:ROW_7+9'd0]), .b(memory[ROW_7+9'd3:ROW_7+9'd2]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[169:168]));
Checker row7_2(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd3:ROW_7+9'd2]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[171:170]));
Checker row7_3(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[173:172]));
Checker row7_4(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[175:174]));
Checker row7_5(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[177:176]));
Checker row7_6(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[179:178]));
Checker row7_7(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[181:180]));
Checker row7_8(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[183:182]));
Checker row7_9(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[185:184]));
Checker row7_10(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[187:186]));
Checker row7_11(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd29:ROW_7+9'd28]), .ans(row_ans[189:188]));
Checker row7_12(.a(memory[ROW_7+9'd31:ROW_7+9'd30]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd29:ROW_7+9'd28]), .ans(row_ans[191:190]));
Summarize12 row7_sum(.check_ans(row_ans[191:168]), .out(row_sum[15:14]));
Checker row8_1(.a(memory[ROW_8+9'd1:ROW_8+9'd0]), .b(memory[ROW_8+9'd3:ROW_8+9'd2]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[193:192]));
Checker row8_2(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd3:ROW_8+9'd2]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[195:194]));
Checker row8_3(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[197:196]));
Checker row8_4(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[199:198]));
Checker row8_5(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[201:200]));
Checker row8_6(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[203:202]));
Checker row8_7(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[205:204]));
Checker row8_8(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[207:206]));
Checker row8_9(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[209:208]));
Checker row8_10(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[211:210]));
Checker row8_11(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd29:ROW_8+9'd28]), .ans(row_ans[213:212]));
Checker row8_12(.a(memory[ROW_8+9'd31:ROW_8+9'd30]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd29:ROW_8+9'd28]), .ans(row_ans[215:214]));
Summarize12 row8_sum(.check_ans(row_ans[215:192]), .out(row_sum[17:16]));
Checker row9_1(.a(memory[ROW_9+9'd1:ROW_9+9'd0]), .b(memory[ROW_9+9'd3:ROW_9+9'd2]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[217:216]));
Checker row9_2(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd3:ROW_9+9'd2]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[219:218]));
Checker row9_3(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[221:220]));
Checker row9_4(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[223:222]));
Checker row9_5(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[225:224]));
Checker row9_6(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[227:226]));
Checker row9_7(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[229:228]));
Checker row9_8(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[231:230]));
Checker row9_9(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[233:232]));
Checker row9_10(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[235:234]));
Checker row9_11(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd29:ROW_9+9'd28]), .ans(row_ans[237:236]));
Checker row9_12(.a(memory[ROW_9+9'd31:ROW_9+9'd30]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd29:ROW_9+9'd28]), .ans(row_ans[239:238]));
Summarize12 row9_sum(.check_ans(row_ans[239:216]), .out(row_sum[19:18]));
Checker row10_1(.a(memory[ROW_10+9'd1:ROW_10+9'd0]), .b(memory[ROW_10+9'd3:ROW_10+9'd2]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[241:240]));
Checker row10_2(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd3:ROW_10+9'd2]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[243:242]));
Checker row10_3(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[245:244]));
Checker row10_4(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[247:246]));
Checker row10_5(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[249:248]));
Checker row10_6(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[251:250]));
Checker row10_7(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[253:252]));
Checker row10_8(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[255:254]));
Checker row10_9(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[257:256]));
Checker row10_10(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[259:258]));
Checker row10_11(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd29:ROW_10+9'd28]), .ans(row_ans[261:260]));
Checker row10_12(.a(memory[ROW_10+9'd31:ROW_10+9'd30]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd29:ROW_10+9'd28]), .ans(row_ans[263:262]));
Summarize12 row10_sum(.check_ans(row_ans[263:240]), .out(row_sum[21:20]));
Checker row11_1(.a(memory[ROW_11+9'd1:ROW_11+9'd0]), .b(memory[ROW_11+9'd3:ROW_11+9'd2]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[265:264]));
Checker row11_2(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd3:ROW_11+9'd2]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[267:266]));
Checker row11_3(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[269:268]));
Checker row11_4(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[271:270]));
Checker row11_5(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[273:272]));
Checker row11_6(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[275:274]));
Checker row11_7(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[277:276]));
Checker row11_8(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[279:278]));
Checker row11_9(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[281:280]));
Checker row11_10(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[283:282]));
Checker row11_11(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd29:ROW_11+9'd28]), .ans(row_ans[285:284]));
Checker row11_12(.a(memory[ROW_11+9'd31:ROW_11+9'd30]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd29:ROW_11+9'd28]), .ans(row_ans[287:286]));
Summarize12 row11_sum(.check_ans(row_ans[287:264]), .out(row_sum[23:22]));
Checker row12_1(.a(memory[ROW_12+9'd1:ROW_12+9'd0]), .b(memory[ROW_12+9'd3:ROW_12+9'd2]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[289:288]));
Checker row12_2(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd3:ROW_12+9'd2]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[291:290]));
Checker row12_3(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[293:292]));
Checker row12_4(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[295:294]));
Checker row12_5(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[297:296]));
Checker row12_6(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[299:298]));
Checker row12_7(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[301:300]));
Checker row12_8(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[303:302]));
Checker row12_9(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[305:304]));
Checker row12_10(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[307:306]));
Checker row12_11(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd29:ROW_12+9'd28]), .ans(row_ans[309:308]));
Checker row12_12(.a(memory[ROW_12+9'd31:ROW_12+9'd30]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd29:ROW_12+9'd28]), .ans(row_ans[311:310]));
Summarize12 row12_sum(.check_ans(row_ans[311:288]), .out(row_sum[25:24]));
Checker row13_1(.a(memory[ROW_13+9'd1:ROW_13+9'd0]), .b(memory[ROW_13+9'd3:ROW_13+9'd2]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[313:312]));
Checker row13_2(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd3:ROW_13+9'd2]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[315:314]));
Checker row13_3(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[317:316]));
Checker row13_4(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[319:318]));
Checker row13_5(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[321:320]));
Checker row13_6(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[323:322]));
Checker row13_7(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[325:324]));
Checker row13_8(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[327:326]));
Checker row13_9(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[329:328]));
Checker row13_10(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[331:330]));
Checker row13_11(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd29:ROW_13+9'd28]), .ans(row_ans[333:332]));
Checker row13_12(.a(memory[ROW_13+9'd31:ROW_13+9'd30]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd29:ROW_13+9'd28]), .ans(row_ans[335:334]));
Summarize12 row13_sum(.check_ans(row_ans[335:312]), .out(row_sum[27:26]));
Checker row14_1(.a(memory[ROW_14+9'd1:ROW_14+9'd0]), .b(memory[ROW_14+9'd3:ROW_14+9'd2]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[337:336]));
Checker row14_2(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd3:ROW_14+9'd2]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[339:338]));
Checker row14_3(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[341:340]));
Checker row14_4(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[343:342]));
Checker row14_5(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[345:344]));
Checker row14_6(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[347:346]));
Checker row14_7(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[349:348]));
Checker row14_8(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[351:350]));
Checker row14_9(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[353:352]));
Checker row14_10(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[355:354]));
Checker row14_11(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd29:ROW_14+9'd28]), .ans(row_ans[357:356]));
Checker row14_12(.a(memory[ROW_14+9'd31:ROW_14+9'd30]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd29:ROW_14+9'd28]), .ans(row_ans[359:358]));
Summarize12 row14_sum(.check_ans(row_ans[359:336]), .out(row_sum[29:28]));
Checker row15_1(.a(memory[ROW_15+9'd1:ROW_15+9'd0]), .b(memory[ROW_15+9'd3:ROW_15+9'd2]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[361:360]));
Checker row15_2(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd3:ROW_15+9'd2]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[363:362]));
Checker row15_3(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[365:364]));
Checker row15_4(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[367:366]));
Checker row15_5(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[369:368]));
Checker row15_6(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[371:370]));
Checker row15_7(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[373:372]));
Checker row15_8(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[375:374]));
Checker row15_9(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[377:376]));
Checker row15_10(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[379:378]));
Checker row15_11(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd29:ROW_15+9'd28]), .ans(row_ans[381:380]));
Checker row15_12(.a(memory[ROW_15+9'd31:ROW_15+9'd30]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd29:ROW_15+9'd28]), .ans(row_ans[383:382]));
Summarize12 row15_sum(.check_ans(row_ans[383:360]), .out(row_sum[31:30]));
Checker col0_1(.a(memory[COL_0+9'd1:COL_0+9'd0]), .b(memory[COL_0+9'd33:COL_0+9'd32]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[1:0]));
Checker col0_2(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd33:COL_0+9'd32]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[3:2]));
Checker col0_3(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[5:4]));
Checker col0_4(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[7:6]));
Checker col0_5(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[9:8]));
Checker col0_6(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[11:10]));
Checker col0_7(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[13:12]));
Checker col0_8(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[15:14]));
Checker col0_9(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[17:16]));
Checker col0_10(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[19:18]));
Checker col0_11(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd449:COL_0+9'd448]), .ans(col_ans[21:20]));
Checker col0_12(.a(memory[COL_0+9'd481:COL_0+9'd480]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd449:COL_0+9'd448]), .ans(col_ans[23:22]));
Summarize12 col0_sum(.check_ans(col_ans[23:0]), .out(col_sum[1:0]));
Checker col1_1(.a(memory[COL_1+9'd1:COL_1+9'd0]), .b(memory[COL_1+9'd33:COL_1+9'd32]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[25:24]));
Checker col1_2(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd33:COL_1+9'd32]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[27:26]));
Checker col1_3(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[29:28]));
Checker col1_4(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[31:30]));
Checker col1_5(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[33:32]));
Checker col1_6(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[35:34]));
Checker col1_7(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[37:36]));
Checker col1_8(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[39:38]));
Checker col1_9(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[41:40]));
Checker col1_10(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[43:42]));
Checker col1_11(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd449:COL_1+9'd448]), .ans(col_ans[45:44]));
Checker col1_12(.a(memory[COL_1+9'd481:COL_1+9'd480]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd449:COL_1+9'd448]), .ans(col_ans[47:46]));
Summarize12 col1_sum(.check_ans(col_ans[47:24]), .out(col_sum[3:2]));
Checker col2_1(.a(memory[COL_2+9'd1:COL_2+9'd0]), .b(memory[COL_2+9'd33:COL_2+9'd32]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[49:48]));
Checker col2_2(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd33:COL_2+9'd32]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[51:50]));
Checker col2_3(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[53:52]));
Checker col2_4(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[55:54]));
Checker col2_5(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[57:56]));
Checker col2_6(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[59:58]));
Checker col2_7(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[61:60]));
Checker col2_8(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[63:62]));
Checker col2_9(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[65:64]));
Checker col2_10(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[67:66]));
Checker col2_11(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd449:COL_2+9'd448]), .ans(col_ans[69:68]));
Checker col2_12(.a(memory[COL_2+9'd481:COL_2+9'd480]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd449:COL_2+9'd448]), .ans(col_ans[71:70]));
Summarize12 col2_sum(.check_ans(col_ans[71:48]), .out(col_sum[5:4]));
Checker col3_1(.a(memory[COL_3+9'd1:COL_3+9'd0]), .b(memory[COL_3+9'd33:COL_3+9'd32]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[73:72]));
Checker col3_2(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd33:COL_3+9'd32]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[75:74]));
Checker col3_3(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[77:76]));
Checker col3_4(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[79:78]));
Checker col3_5(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[81:80]));
Checker col3_6(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[83:82]));
Checker col3_7(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[85:84]));
Checker col3_8(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[87:86]));
Checker col3_9(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[89:88]));
Checker col3_10(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[91:90]));
Checker col3_11(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd449:COL_3+9'd448]), .ans(col_ans[93:92]));
Checker col3_12(.a(memory[COL_3+9'd481:COL_3+9'd480]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd449:COL_3+9'd448]), .ans(col_ans[95:94]));
Summarize12 col3_sum(.check_ans(col_ans[95:72]), .out(col_sum[7:6]));
Checker col4_1(.a(memory[COL_4+9'd1:COL_4+9'd0]), .b(memory[COL_4+9'd33:COL_4+9'd32]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[97:96]));
Checker col4_2(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd33:COL_4+9'd32]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[99:98]));
Checker col4_3(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[101:100]));
Checker col4_4(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[103:102]));
Checker col4_5(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[105:104]));
Checker col4_6(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[107:106]));
Checker col4_7(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[109:108]));
Checker col4_8(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[111:110]));
Checker col4_9(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[113:112]));
Checker col4_10(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[115:114]));
Checker col4_11(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd449:COL_4+9'd448]), .ans(col_ans[117:116]));
Checker col4_12(.a(memory[COL_4+9'd481:COL_4+9'd480]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd449:COL_4+9'd448]), .ans(col_ans[119:118]));
Summarize12 col4_sum(.check_ans(col_ans[119:96]), .out(col_sum[9:8]));
Checker col5_1(.a(memory[COL_5+9'd1:COL_5+9'd0]), .b(memory[COL_5+9'd33:COL_5+9'd32]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[121:120]));
Checker col5_2(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd33:COL_5+9'd32]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[123:122]));
Checker col5_3(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[125:124]));
Checker col5_4(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[127:126]));
Checker col5_5(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[129:128]));
Checker col5_6(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[131:130]));
Checker col5_7(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[133:132]));
Checker col5_8(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[135:134]));
Checker col5_9(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[137:136]));
Checker col5_10(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[139:138]));
Checker col5_11(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd449:COL_5+9'd448]), .ans(col_ans[141:140]));
Checker col5_12(.a(memory[COL_5+9'd481:COL_5+9'd480]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd449:COL_5+9'd448]), .ans(col_ans[143:142]));
Summarize12 col5_sum(.check_ans(col_ans[143:120]), .out(col_sum[11:10]));
Checker col6_1(.a(memory[COL_6+9'd1:COL_6+9'd0]), .b(memory[COL_6+9'd33:COL_6+9'd32]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[145:144]));
Checker col6_2(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd33:COL_6+9'd32]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[147:146]));
Checker col6_3(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[149:148]));
Checker col6_4(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[151:150]));
Checker col6_5(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[153:152]));
Checker col6_6(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[155:154]));
Checker col6_7(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[157:156]));
Checker col6_8(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[159:158]));
Checker col6_9(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[161:160]));
Checker col6_10(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[163:162]));
Checker col6_11(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd449:COL_6+9'd448]), .ans(col_ans[165:164]));
Checker col6_12(.a(memory[COL_6+9'd481:COL_6+9'd480]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd449:COL_6+9'd448]), .ans(col_ans[167:166]));
Summarize12 col6_sum(.check_ans(col_ans[167:144]), .out(col_sum[13:12]));
Checker col7_1(.a(memory[COL_7+9'd1:COL_7+9'd0]), .b(memory[COL_7+9'd33:COL_7+9'd32]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[169:168]));
Checker col7_2(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd33:COL_7+9'd32]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[171:170]));
Checker col7_3(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[173:172]));
Checker col7_4(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[175:174]));
Checker col7_5(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[177:176]));
Checker col7_6(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[179:178]));
Checker col7_7(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[181:180]));
Checker col7_8(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[183:182]));
Checker col7_9(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[185:184]));
Checker col7_10(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[187:186]));
Checker col7_11(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd449:COL_7+9'd448]), .ans(col_ans[189:188]));
Checker col7_12(.a(memory[COL_7+9'd481:COL_7+9'd480]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd449:COL_7+9'd448]), .ans(col_ans[191:190]));
Summarize12 col7_sum(.check_ans(col_ans[191:168]), .out(col_sum[15:14]));
Checker col8_1(.a(memory[COL_8+9'd1:COL_8+9'd0]), .b(memory[COL_8+9'd33:COL_8+9'd32]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[193:192]));
Checker col8_2(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd33:COL_8+9'd32]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[195:194]));
Checker col8_3(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[197:196]));
Checker col8_4(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[199:198]));
Checker col8_5(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[201:200]));
Checker col8_6(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[203:202]));
Checker col8_7(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[205:204]));
Checker col8_8(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[207:206]));
Checker col8_9(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[209:208]));
Checker col8_10(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[211:210]));
Checker col8_11(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd449:COL_8+9'd448]), .ans(col_ans[213:212]));
Checker col8_12(.a(memory[COL_8+9'd481:COL_8+9'd480]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd449:COL_8+9'd448]), .ans(col_ans[215:214]));
Summarize12 col8_sum(.check_ans(col_ans[215:192]), .out(col_sum[17:16]));
Checker col9_1(.a(memory[COL_9+9'd1:COL_9+9'd0]), .b(memory[COL_9+9'd33:COL_9+9'd32]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[217:216]));
Checker col9_2(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd33:COL_9+9'd32]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[219:218]));
Checker col9_3(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[221:220]));
Checker col9_4(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[223:222]));
Checker col9_5(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[225:224]));
Checker col9_6(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[227:226]));
Checker col9_7(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[229:228]));
Checker col9_8(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[231:230]));
Checker col9_9(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[233:232]));
Checker col9_10(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[235:234]));
Checker col9_11(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd449:COL_9+9'd448]), .ans(col_ans[237:236]));
Checker col9_12(.a(memory[COL_9+9'd481:COL_9+9'd480]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd449:COL_9+9'd448]), .ans(col_ans[239:238]));
Summarize12 col9_sum(.check_ans(col_ans[239:216]), .out(col_sum[19:18]));
Checker col10_1(.a(memory[COL_10+9'd1:COL_10+9'd0]), .b(memory[COL_10+9'd33:COL_10+9'd32]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[241:240]));
Checker col10_2(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd33:COL_10+9'd32]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[243:242]));
Checker col10_3(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[245:244]));
Checker col10_4(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[247:246]));
Checker col10_5(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[249:248]));
Checker col10_6(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[251:250]));
Checker col10_7(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[253:252]));
Checker col10_8(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[255:254]));
Checker col10_9(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[257:256]));
Checker col10_10(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[259:258]));
Checker col10_11(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd449:COL_10+9'd448]), .ans(col_ans[261:260]));
Checker col10_12(.a(memory[COL_10+9'd481:COL_10+9'd480]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd449:COL_10+9'd448]), .ans(col_ans[263:262]));
Summarize12 col10_sum(.check_ans(col_ans[263:240]), .out(col_sum[21:20]));
Checker col11_1(.a(memory[COL_11+9'd1:COL_11+9'd0]), .b(memory[COL_11+9'd33:COL_11+9'd32]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[265:264]));
Checker col11_2(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd33:COL_11+9'd32]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[267:266]));
Checker col11_3(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[269:268]));
Checker col11_4(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[271:270]));
Checker col11_5(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[273:272]));
Checker col11_6(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[275:274]));
Checker col11_7(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[277:276]));
Checker col11_8(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[279:278]));
Checker col11_9(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[281:280]));
Checker col11_10(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[283:282]));
Checker col11_11(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd449:COL_11+9'd448]), .ans(col_ans[285:284]));
Checker col11_12(.a(memory[COL_11+9'd481:COL_11+9'd480]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd449:COL_11+9'd448]), .ans(col_ans[287:286]));
Summarize12 col11_sum(.check_ans(col_ans[287:264]), .out(col_sum[23:22]));
Checker col12_1(.a(memory[COL_12+9'd1:COL_12+9'd0]), .b(memory[COL_12+9'd33:COL_12+9'd32]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[289:288]));
Checker col12_2(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd33:COL_12+9'd32]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[291:290]));
Checker col12_3(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[293:292]));
Checker col12_4(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[295:294]));
Checker col12_5(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[297:296]));
Checker col12_6(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[299:298]));
Checker col12_7(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[301:300]));
Checker col12_8(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[303:302]));
Checker col12_9(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[305:304]));
Checker col12_10(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[307:306]));
Checker col12_11(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd449:COL_12+9'd448]), .ans(col_ans[309:308]));
Checker col12_12(.a(memory[COL_12+9'd481:COL_12+9'd480]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd449:COL_12+9'd448]), .ans(col_ans[311:310]));
Summarize12 col12_sum(.check_ans(col_ans[311:288]), .out(col_sum[25:24]));
Checker col13_1(.a(memory[COL_13+9'd1:COL_13+9'd0]), .b(memory[COL_13+9'd33:COL_13+9'd32]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[313:312]));
Checker col13_2(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd33:COL_13+9'd32]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[315:314]));
Checker col13_3(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[317:316]));
Checker col13_4(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[319:318]));
Checker col13_5(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[321:320]));
Checker col13_6(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[323:322]));
Checker col13_7(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[325:324]));
Checker col13_8(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[327:326]));
Checker col13_9(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[329:328]));
Checker col13_10(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[331:330]));
Checker col13_11(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd449:COL_13+9'd448]), .ans(col_ans[333:332]));
Checker col13_12(.a(memory[COL_13+9'd481:COL_13+9'd480]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd449:COL_13+9'd448]), .ans(col_ans[335:334]));
Summarize12 col13_sum(.check_ans(col_ans[335:312]), .out(col_sum[27:26]));
Checker col14_1(.a(memory[COL_14+9'd1:COL_14+9'd0]), .b(memory[COL_14+9'd33:COL_14+9'd32]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[337:336]));
Checker col14_2(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd33:COL_14+9'd32]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[339:338]));
Checker col14_3(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[341:340]));
Checker col14_4(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[343:342]));
Checker col14_5(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[345:344]));
Checker col14_6(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[347:346]));
Checker col14_7(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[349:348]));
Checker col14_8(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[351:350]));
Checker col14_9(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[353:352]));
Checker col14_10(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[355:354]));
Checker col14_11(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd449:COL_14+9'd448]), .ans(col_ans[357:356]));
Checker col14_12(.a(memory[COL_14+9'd481:COL_14+9'd480]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd449:COL_14+9'd448]), .ans(col_ans[359:358]));
Summarize12 col14_sum(.check_ans(col_ans[359:336]), .out(col_sum[29:28]));
Checker col15_1(.a(memory[COL_15+9'd1:COL_15+9'd0]), .b(memory[COL_15+9'd33:COL_15+9'd32]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[361:360]));
Checker col15_2(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd33:COL_15+9'd32]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[363:362]));
Checker col15_3(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[365:364]));
Checker col15_4(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[367:366]));
Checker col15_5(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[369:368]));
Checker col15_6(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[370:370]));
Checker col15_7(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[373:372]));
Checker col15_8(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[375:374]));
Checker col15_9(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[377:376]));
Checker col15_10(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[379:378]));
Checker col15_11(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd449:COL_15+9'd448]), .ans(col_ans[381:380]));
Checker col15_12(.a(memory[COL_15+9'd481:COL_15+9'd480]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd449:COL_15+9'd448]), .ans(col_ans[383:382]));
Summarize12 col15_sum(.check_ans(col_ans[383:360]), .out(col_sum[31:30]));
wire [3:0] sum_board;
Summarize16 sum_rows(.check_ans(row_sum[31:0]), .out(sum_board[1:0]));
Summarize16 sum_cols(.check_ans(col_sum[31:0]), .out(sum_board[3:2]));
always@(*)
begin
if((sum_board[1:0] == 2'b00) && (sum_board[3:2] == 2'b00)) ans[1:0]=2'b00;
else if((sum_board[1:0] == 2'b10) || (sum_board[3:2] == 2'b10)) ans[1:0]=2'b10;
else ans[1:0]=2'b01;
end
endmodule | module All_Check(memory, ans); |
input [511:0] memory;
output reg [1:0] ans;
wire [383:0] row_ans, col_ans;
wire [31:0] row_sum, col_sum;
localparam ROW_0 = 9'd0, ROW_1 = 9'd32, ROW_2 = 9'd64, ROW_3 = 9'd96, ROW_4 = 9'd128,
ROW_5 = 9'd160, ROW_6 = 9'd192, ROW_7 = 9'd224, ROW_8 = 9'd256, ROW_9 = 9'd288,
ROW_10 = 9'd320, ROW_11 = 9'd352, ROW_12 = 9'd384, ROW_13 = 9'd416,
ROW_14 = 9'd448, ROW_15 = 9'd480;
localparam COL_0 = 9'd0, COL_1 = 9'd2, COL_2 = 9'd4, COL_3 = 9'd6, COL_4 = 9'd8,
COL_5 = 9'd10, COL_6 = 9'd12, COL_7 = 9'd14, COL_8 = 9'd16, COL_9 = 9'd18,
COL_10 = 9'd20, COL_11 = 9'd22, COL_12 = 9'd24, COL_13 = 9'd26,
COL_14 = 9'd28, COL_15 = 9'd30;
Checker row0_1(.a(memory[ROW_0+9'd1:ROW_0+9'd0]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[1:0]));
Checker row0_2(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd3:ROW_0+9'd2]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[3:2]));
Checker row0_3(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd5:ROW_0+9'd4]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[5:4]));
Checker row0_4(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd7:ROW_0+9'd6]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[7:6]));
Checker row0_5(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd9:ROW_0+9'd8]), .ans(row_ans[9:8]));
Checker row0_6(.a(memory[ROW_0+9'd11:ROW_0+9'd10]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[11:10]));
Checker row0_7(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd13:ROW_0+9'd12]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[13:12]));
Checker row0_8(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd15:ROW_0+9'd14]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[15:14]));
Checker row0_9(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd17:ROW_0+9'd16]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[17:16]));
Checker row0_10(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd19:ROW_0+9'd18]), .ans(row_ans[19:18]));
Checker row0_11(.a(memory[ROW_0+9'd21:ROW_0+9'd20]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd29:ROW_0+9'd28]), .ans(row_ans[21:20]));
Checker row0_12(.a(memory[ROW_0+9'd31:ROW_0+9'd30]), .b(memory[ROW_0+9'd23:ROW_0+9'd22]), .c(memory[ROW_0+9'd25:ROW_0+9'd24]),
.d(memory[ROW_0+9'd27:ROW_0+9'd26]), .e(memory[ROW_0+9'd29:ROW_0+9'd28]), .ans(row_ans[23:22]));
Summarize12 row0_sum(.check_ans(row_ans[23:0]), .out(row_sum[1:0]));
Checker row1_1(.a(memory[ROW_1+9'd1:ROW_1+9'd0]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[25:24]));
Checker row1_2(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd3:ROW_1+9'd2]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[27:26]));
Checker row1_3(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd5:ROW_1+9'd4]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[29:28]));
Checker row1_4(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd7:ROW_1+9'd6]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[31:30]));
Checker row1_5(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd9:ROW_1+9'd8]), .ans(row_ans[33:32]));
Checker row1_6(.a(memory[ROW_1+9'd11:ROW_1+9'd10]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[35:34]));
Checker row1_7(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd13:ROW_1+9'd12]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[37:36]));
Checker row1_8(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd15:ROW_1+9'd14]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[39:38]));
Checker row1_9(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd17:ROW_1+9'd16]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[41:40]));
Checker row1_10(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd19:ROW_1+9'd18]), .ans(row_ans[43:42]));
Checker row1_11(.a(memory[ROW_1+9'd21:ROW_1+9'd20]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd29:ROW_1+9'd28]), .ans(row_ans[45:44]));
Checker row1_12(.a(memory[ROW_1+9'd31:ROW_1+9'd30]), .b(memory[ROW_1+9'd23:ROW_1+9'd22]), .c(memory[ROW_1+9'd25:ROW_1+9'd24]),
.d(memory[ROW_1+9'd27:ROW_1+9'd26]), .e(memory[ROW_1+9'd29:ROW_1+9'd28]), .ans(row_ans[47:46]));
Summarize12 row1_sum(.check_ans(row_ans[47:24]), .out(row_sum[3:2]));
Checker row2_1(.a(memory[ROW_2+9'd1:ROW_2+9'd0]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[49:48]));
Checker row2_2(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd3:ROW_2+9'd2]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[51:50]));
Checker row2_3(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd5:ROW_2+9'd4]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[53:52]));
Checker row2_4(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd7:ROW_2+9'd6]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[55:54]));
Checker row2_5(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd9:ROW_2+9'd8]), .ans(row_ans[57:56]));
Checker row2_6(.a(memory[ROW_2+9'd11:ROW_2+9'd10]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[59:58]));
Checker row2_7(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd13:ROW_2+9'd12]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[61:60]));
Checker row2_8(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd15:ROW_2+9'd14]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[63:62]));
Checker row2_9(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd17:ROW_2+9'd16]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[65:64]));
Checker row2_10(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd19:ROW_2+9'd18]), .ans(row_ans[67:66]));
Checker row2_11(.a(memory[ROW_2+9'd21:ROW_2+9'd20]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd29:ROW_2+9'd28]), .ans(row_ans[69:68]));
Checker row2_12(.a(memory[ROW_2+9'd31:ROW_2+9'd30]), .b(memory[ROW_2+9'd23:ROW_2+9'd22]), .c(memory[ROW_2+9'd25:ROW_2+9'd24]),
.d(memory[ROW_2+9'd27:ROW_2+9'd26]), .e(memory[ROW_2+9'd29:ROW_2+9'd28]), .ans(row_ans[71:70]));
Summarize12 row2_sum(.check_ans(row_ans[71:48]), .out(row_sum[5:4]));
Checker row3_1(.a(memory[ROW_3+9'd1:ROW_3+9'd0]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[73:72]));
Checker row3_2(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd3:ROW_3+9'd2]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[75:74]));
Checker row3_3(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd5:ROW_3+9'd4]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[77:76]));
Checker row3_4(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd7:ROW_3+9'd6]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[79:78]));
Checker row3_5(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd9:ROW_3+9'd8]), .ans(row_ans[81:80]));
Checker row3_6(.a(memory[ROW_3+9'd11:ROW_3+9'd10]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[83:82]));
Checker row3_7(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd13:ROW_3+9'd12]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[85:84]));
Checker row3_8(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd15:ROW_3+9'd14]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[87:86]));
Checker row3_9(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd17:ROW_3+9'd16]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[89:88]));
Checker row3_10(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd19:ROW_3+9'd18]), .ans(row_ans[91:90]));
Checker row3_11(.a(memory[ROW_3+9'd21:ROW_3+9'd20]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd29:ROW_3+9'd28]), .ans(row_ans[93:92]));
Checker row3_12(.a(memory[ROW_3+9'd31:ROW_3+9'd30]), .b(memory[ROW_3+9'd23:ROW_3+9'd22]), .c(memory[ROW_3+9'd25:ROW_3+9'd24]),
.d(memory[ROW_3+9'd27:ROW_3+9'd26]), .e(memory[ROW_3+9'd29:ROW_3+9'd28]), .ans(row_ans[95:94]));
Summarize12 row3_sum(.check_ans(row_ans[95:72]), .out(row_sum[7:6]));
Checker row4_1(.a(memory[ROW_4+9'd1:ROW_4+9'd0]), .b(memory[ROW_4+9'd3:ROW_4+9'd2]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[97:96]));
Checker row4_2(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd3:ROW_4+9'd2]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[99:98]));
Checker row4_3(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd5:ROW_4+9'd4]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[101:100]));
Checker row4_4(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd7:ROW_4+9'd6]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[103:102]));
Checker row4_5(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd9:ROW_4+9'd8]), .ans(row_ans[105:104]));
Checker row4_6(.a(memory[ROW_4+9'd11:ROW_4+9'd10]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[107:106]));
Checker row4_7(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd13:ROW_4+9'd12]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[109:108]));
Checker row4_8(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd15:ROW_4+9'd14]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[111:110]));
Checker row4_9(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd17:ROW_4+9'd16]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[113:112]));
Checker row4_10(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd19:ROW_4+9'd18]), .ans(row_ans[115:114]));
Checker row4_11(.a(memory[ROW_4+9'd21:ROW_4+9'd20]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd29:ROW_4+9'd28]), .ans(row_ans[117:116]));
Checker row4_12(.a(memory[ROW_4+9'd31:ROW_4+9'd30]), .b(memory[ROW_4+9'd23:ROW_4+9'd22]), .c(memory[ROW_4+9'd25:ROW_4+9'd24]),
.d(memory[ROW_4+9'd27:ROW_4+9'd26]), .e(memory[ROW_4+9'd29:ROW_4+9'd28]), .ans(row_ans[119:118]));
Summarize12 row4_sum(.check_ans(row_ans[119:96]), .out(row_sum[9:8]));
Checker row5_1(.a(memory[ROW_5+9'd1:ROW_5+9'd0]), .b(memory[ROW_5+9'd3:ROW_5+9'd2]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[121:120]));
Checker row5_2(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd3:ROW_5+9'd2]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[123:122]));
Checker row5_3(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd5:ROW_5+9'd4]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[125:124]));
Checker row5_4(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd7:ROW_5+9'd6]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[127:126]));
Checker row5_5(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd9:ROW_5+9'd8]), .ans(row_ans[129:128]));
Checker row5_6(.a(memory[ROW_5+9'd11:ROW_5+9'd10]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[131:130]));
Checker row5_7(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd13:ROW_5+9'd12]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[133:132]));
Checker row5_8(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd15:ROW_5+9'd14]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[135:134]));
Checker row5_9(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd17:ROW_5+9'd16]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[137:136]));
Checker row5_10(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd19:ROW_5+9'd18]), .ans(row_ans[139:138]));
Checker row5_11(.a(memory[ROW_5+9'd21:ROW_5+9'd20]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd29:ROW_5+9'd28]), .ans(row_ans[141:140]));
Checker row5_12(.a(memory[ROW_5+9'd31:ROW_5+9'd30]), .b(memory[ROW_5+9'd23:ROW_5+9'd22]), .c(memory[ROW_5+9'd25:ROW_5+9'd24]),
.d(memory[ROW_5+9'd27:ROW_5+9'd26]), .e(memory[ROW_5+9'd29:ROW_5+9'd28]), .ans(row_ans[143:142]));
Summarize12 row5_sum(.check_ans(row_ans[143:120]), .out(row_sum[11:10]));
Checker row6_1(.a(memory[ROW_6+9'd1:ROW_6+9'd0]), .b(memory[ROW_6+9'd3:ROW_6+9'd2]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[145:144]));
Checker row6_2(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd3:ROW_6+9'd2]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[147:146]));
Checker row6_3(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd5:ROW_6+9'd4]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[149:148]));
Checker row6_4(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd7:ROW_6+9'd6]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[151:150]));
Checker row6_5(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd9:ROW_6+9'd8]), .ans(row_ans[153:152]));
Checker row6_6(.a(memory[ROW_6+9'd11:ROW_6+9'd10]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[155:154]));
Checker row6_7(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd13:ROW_6+9'd12]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[157:156]));
Checker row6_8(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd15:ROW_6+9'd14]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[159:158]));
Checker row6_9(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd17:ROW_6+9'd16]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[161:160]));
Checker row6_10(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd19:ROW_6+9'd18]), .ans(row_ans[163:162]));
Checker row6_11(.a(memory[ROW_6+9'd21:ROW_6+9'd20]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd29:ROW_6+9'd28]), .ans(row_ans[165:164]));
Checker row6_12(.a(memory[ROW_6+9'd31:ROW_6+9'd30]), .b(memory[ROW_6+9'd23:ROW_6+9'd22]), .c(memory[ROW_6+9'd25:ROW_6+9'd24]),
.d(memory[ROW_6+9'd27:ROW_6+9'd26]), .e(memory[ROW_6+9'd29:ROW_6+9'd28]), .ans(row_ans[167:166]));
Summarize12 row6_sum(.check_ans(row_ans[167:144]), .out(row_sum[13:12]));
Checker row7_1(.a(memory[ROW_7+9'd1:ROW_7+9'd0]), .b(memory[ROW_7+9'd3:ROW_7+9'd2]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[169:168]));
Checker row7_2(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd3:ROW_7+9'd2]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[171:170]));
Checker row7_3(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd5:ROW_7+9'd4]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[173:172]));
Checker row7_4(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd7:ROW_7+9'd6]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[175:174]));
Checker row7_5(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd9:ROW_7+9'd8]), .ans(row_ans[177:176]));
Checker row7_6(.a(memory[ROW_7+9'd11:ROW_7+9'd10]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[179:178]));
Checker row7_7(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd13:ROW_7+9'd12]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[181:180]));
Checker row7_8(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd15:ROW_7+9'd14]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[183:182]));
Checker row7_9(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd17:ROW_7+9'd16]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[185:184]));
Checker row7_10(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd19:ROW_7+9'd18]), .ans(row_ans[187:186]));
Checker row7_11(.a(memory[ROW_7+9'd21:ROW_7+9'd20]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd29:ROW_7+9'd28]), .ans(row_ans[189:188]));
Checker row7_12(.a(memory[ROW_7+9'd31:ROW_7+9'd30]), .b(memory[ROW_7+9'd23:ROW_7+9'd22]), .c(memory[ROW_7+9'd25:ROW_7+9'd24]),
.d(memory[ROW_7+9'd27:ROW_7+9'd26]), .e(memory[ROW_7+9'd29:ROW_7+9'd28]), .ans(row_ans[191:190]));
Summarize12 row7_sum(.check_ans(row_ans[191:168]), .out(row_sum[15:14]));
Checker row8_1(.a(memory[ROW_8+9'd1:ROW_8+9'd0]), .b(memory[ROW_8+9'd3:ROW_8+9'd2]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[193:192]));
Checker row8_2(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd3:ROW_8+9'd2]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[195:194]));
Checker row8_3(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd5:ROW_8+9'd4]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[197:196]));
Checker row8_4(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd7:ROW_8+9'd6]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[199:198]));
Checker row8_5(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd9:ROW_8+9'd8]), .ans(row_ans[201:200]));
Checker row8_6(.a(memory[ROW_8+9'd11:ROW_8+9'd10]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[203:202]));
Checker row8_7(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd13:ROW_8+9'd12]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[205:204]));
Checker row8_8(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd15:ROW_8+9'd14]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[207:206]));
Checker row8_9(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd17:ROW_8+9'd16]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[209:208]));
Checker row8_10(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd19:ROW_8+9'd18]), .ans(row_ans[211:210]));
Checker row8_11(.a(memory[ROW_8+9'd21:ROW_8+9'd20]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd29:ROW_8+9'd28]), .ans(row_ans[213:212]));
Checker row8_12(.a(memory[ROW_8+9'd31:ROW_8+9'd30]), .b(memory[ROW_8+9'd23:ROW_8+9'd22]), .c(memory[ROW_8+9'd25:ROW_8+9'd24]),
.d(memory[ROW_8+9'd27:ROW_8+9'd26]), .e(memory[ROW_8+9'd29:ROW_8+9'd28]), .ans(row_ans[215:214]));
Summarize12 row8_sum(.check_ans(row_ans[215:192]), .out(row_sum[17:16]));
Checker row9_1(.a(memory[ROW_9+9'd1:ROW_9+9'd0]), .b(memory[ROW_9+9'd3:ROW_9+9'd2]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[217:216]));
Checker row9_2(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd3:ROW_9+9'd2]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[219:218]));
Checker row9_3(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd5:ROW_9+9'd4]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[221:220]));
Checker row9_4(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd7:ROW_9+9'd6]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[223:222]));
Checker row9_5(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd9:ROW_9+9'd8]), .ans(row_ans[225:224]));
Checker row9_6(.a(memory[ROW_9+9'd11:ROW_9+9'd10]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[227:226]));
Checker row9_7(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd13:ROW_9+9'd12]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[229:228]));
Checker row9_8(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd15:ROW_9+9'd14]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[231:230]));
Checker row9_9(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd17:ROW_9+9'd16]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[233:232]));
Checker row9_10(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd19:ROW_9+9'd18]), .ans(row_ans[235:234]));
Checker row9_11(.a(memory[ROW_9+9'd21:ROW_9+9'd20]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd29:ROW_9+9'd28]), .ans(row_ans[237:236]));
Checker row9_12(.a(memory[ROW_9+9'd31:ROW_9+9'd30]), .b(memory[ROW_9+9'd23:ROW_9+9'd22]), .c(memory[ROW_9+9'd25:ROW_9+9'd24]),
.d(memory[ROW_9+9'd27:ROW_9+9'd26]), .e(memory[ROW_9+9'd29:ROW_9+9'd28]), .ans(row_ans[239:238]));
Summarize12 row9_sum(.check_ans(row_ans[239:216]), .out(row_sum[19:18]));
Checker row10_1(.a(memory[ROW_10+9'd1:ROW_10+9'd0]), .b(memory[ROW_10+9'd3:ROW_10+9'd2]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[241:240]));
Checker row10_2(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd3:ROW_10+9'd2]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[243:242]));
Checker row10_3(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd5:ROW_10+9'd4]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[245:244]));
Checker row10_4(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd7:ROW_10+9'd6]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[247:246]));
Checker row10_5(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd9:ROW_10+9'd8]), .ans(row_ans[249:248]));
Checker row10_6(.a(memory[ROW_10+9'd11:ROW_10+9'd10]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[251:250]));
Checker row10_7(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd13:ROW_10+9'd12]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[253:252]));
Checker row10_8(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd15:ROW_10+9'd14]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[255:254]));
Checker row10_9(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd17:ROW_10+9'd16]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[257:256]));
Checker row10_10(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd19:ROW_10+9'd18]), .ans(row_ans[259:258]));
Checker row10_11(.a(memory[ROW_10+9'd21:ROW_10+9'd20]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd29:ROW_10+9'd28]), .ans(row_ans[261:260]));
Checker row10_12(.a(memory[ROW_10+9'd31:ROW_10+9'd30]), .b(memory[ROW_10+9'd23:ROW_10+9'd22]), .c(memory[ROW_10+9'd25:ROW_10+9'd24]),
.d(memory[ROW_10+9'd27:ROW_10+9'd26]), .e(memory[ROW_10+9'd29:ROW_10+9'd28]), .ans(row_ans[263:262]));
Summarize12 row10_sum(.check_ans(row_ans[263:240]), .out(row_sum[21:20]));
Checker row11_1(.a(memory[ROW_11+9'd1:ROW_11+9'd0]), .b(memory[ROW_11+9'd3:ROW_11+9'd2]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[265:264]));
Checker row11_2(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd3:ROW_11+9'd2]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[267:266]));
Checker row11_3(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd5:ROW_11+9'd4]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[269:268]));
Checker row11_4(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd7:ROW_11+9'd6]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[271:270]));
Checker row11_5(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd9:ROW_11+9'd8]), .ans(row_ans[273:272]));
Checker row11_6(.a(memory[ROW_11+9'd11:ROW_11+9'd10]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[275:274]));
Checker row11_7(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd13:ROW_11+9'd12]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[277:276]));
Checker row11_8(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd15:ROW_11+9'd14]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[279:278]));
Checker row11_9(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd17:ROW_11+9'd16]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[281:280]));
Checker row11_10(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd19:ROW_11+9'd18]), .ans(row_ans[283:282]));
Checker row11_11(.a(memory[ROW_11+9'd21:ROW_11+9'd20]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd29:ROW_11+9'd28]), .ans(row_ans[285:284]));
Checker row11_12(.a(memory[ROW_11+9'd31:ROW_11+9'd30]), .b(memory[ROW_11+9'd23:ROW_11+9'd22]), .c(memory[ROW_11+9'd25:ROW_11+9'd24]),
.d(memory[ROW_11+9'd27:ROW_11+9'd26]), .e(memory[ROW_11+9'd29:ROW_11+9'd28]), .ans(row_ans[287:286]));
Summarize12 row11_sum(.check_ans(row_ans[287:264]), .out(row_sum[23:22]));
Checker row12_1(.a(memory[ROW_12+9'd1:ROW_12+9'd0]), .b(memory[ROW_12+9'd3:ROW_12+9'd2]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[289:288]));
Checker row12_2(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd3:ROW_12+9'd2]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[291:290]));
Checker row12_3(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd5:ROW_12+9'd4]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[293:292]));
Checker row12_4(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd7:ROW_12+9'd6]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[295:294]));
Checker row12_5(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd9:ROW_12+9'd8]), .ans(row_ans[297:296]));
Checker row12_6(.a(memory[ROW_12+9'd11:ROW_12+9'd10]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[299:298]));
Checker row12_7(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd13:ROW_12+9'd12]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[301:300]));
Checker row12_8(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd15:ROW_12+9'd14]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[303:302]));
Checker row12_9(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd17:ROW_12+9'd16]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[305:304]));
Checker row12_10(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd19:ROW_12+9'd18]), .ans(row_ans[307:306]));
Checker row12_11(.a(memory[ROW_12+9'd21:ROW_12+9'd20]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd29:ROW_12+9'd28]), .ans(row_ans[309:308]));
Checker row12_12(.a(memory[ROW_12+9'd31:ROW_12+9'd30]), .b(memory[ROW_12+9'd23:ROW_12+9'd22]), .c(memory[ROW_12+9'd25:ROW_12+9'd24]),
.d(memory[ROW_12+9'd27:ROW_12+9'd26]), .e(memory[ROW_12+9'd29:ROW_12+9'd28]), .ans(row_ans[311:310]));
Summarize12 row12_sum(.check_ans(row_ans[311:288]), .out(row_sum[25:24]));
Checker row13_1(.a(memory[ROW_13+9'd1:ROW_13+9'd0]), .b(memory[ROW_13+9'd3:ROW_13+9'd2]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[313:312]));
Checker row13_2(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd3:ROW_13+9'd2]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[315:314]));
Checker row13_3(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd5:ROW_13+9'd4]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[317:316]));
Checker row13_4(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd7:ROW_13+9'd6]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[319:318]));
Checker row13_5(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd9:ROW_13+9'd8]), .ans(row_ans[321:320]));
Checker row13_6(.a(memory[ROW_13+9'd11:ROW_13+9'd10]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[323:322]));
Checker row13_7(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd13:ROW_13+9'd12]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[325:324]));
Checker row13_8(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd15:ROW_13+9'd14]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[327:326]));
Checker row13_9(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd17:ROW_13+9'd16]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[329:328]));
Checker row13_10(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd19:ROW_13+9'd18]), .ans(row_ans[331:330]));
Checker row13_11(.a(memory[ROW_13+9'd21:ROW_13+9'd20]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd29:ROW_13+9'd28]), .ans(row_ans[333:332]));
Checker row13_12(.a(memory[ROW_13+9'd31:ROW_13+9'd30]), .b(memory[ROW_13+9'd23:ROW_13+9'd22]), .c(memory[ROW_13+9'd25:ROW_13+9'd24]),
.d(memory[ROW_13+9'd27:ROW_13+9'd26]), .e(memory[ROW_13+9'd29:ROW_13+9'd28]), .ans(row_ans[335:334]));
Summarize12 row13_sum(.check_ans(row_ans[335:312]), .out(row_sum[27:26]));
Checker row14_1(.a(memory[ROW_14+9'd1:ROW_14+9'd0]), .b(memory[ROW_14+9'd3:ROW_14+9'd2]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[337:336]));
Checker row14_2(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd3:ROW_14+9'd2]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[339:338]));
Checker row14_3(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd5:ROW_14+9'd4]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[341:340]));
Checker row14_4(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd7:ROW_14+9'd6]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[343:342]));
Checker row14_5(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd9:ROW_14+9'd8]), .ans(row_ans[345:344]));
Checker row14_6(.a(memory[ROW_14+9'd11:ROW_14+9'd10]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[347:346]));
Checker row14_7(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd13:ROW_14+9'd12]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[349:348]));
Checker row14_8(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd15:ROW_14+9'd14]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[351:350]));
Checker row14_9(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd17:ROW_14+9'd16]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[353:352]));
Checker row14_10(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd19:ROW_14+9'd18]), .ans(row_ans[355:354]));
Checker row14_11(.a(memory[ROW_14+9'd21:ROW_14+9'd20]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd29:ROW_14+9'd28]), .ans(row_ans[357:356]));
Checker row14_12(.a(memory[ROW_14+9'd31:ROW_14+9'd30]), .b(memory[ROW_14+9'd23:ROW_14+9'd22]), .c(memory[ROW_14+9'd25:ROW_14+9'd24]),
.d(memory[ROW_14+9'd27:ROW_14+9'd26]), .e(memory[ROW_14+9'd29:ROW_14+9'd28]), .ans(row_ans[359:358]));
Summarize12 row14_sum(.check_ans(row_ans[359:336]), .out(row_sum[29:28]));
Checker row15_1(.a(memory[ROW_15+9'd1:ROW_15+9'd0]), .b(memory[ROW_15+9'd3:ROW_15+9'd2]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[361:360]));
Checker row15_2(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd3:ROW_15+9'd2]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[363:362]));
Checker row15_3(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd5:ROW_15+9'd4]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[365:364]));
Checker row15_4(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd7:ROW_15+9'd6]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[367:366]));
Checker row15_5(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd9:ROW_15+9'd8]), .ans(row_ans[369:368]));
Checker row15_6(.a(memory[ROW_15+9'd11:ROW_15+9'd10]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[371:370]));
Checker row15_7(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd13:ROW_15+9'd12]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[373:372]));
Checker row15_8(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd15:ROW_15+9'd14]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[375:374]));
Checker row15_9(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd17:ROW_15+9'd16]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[377:376]));
Checker row15_10(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd19:ROW_15+9'd18]), .ans(row_ans[379:378]));
Checker row15_11(.a(memory[ROW_15+9'd21:ROW_15+9'd20]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd29:ROW_15+9'd28]), .ans(row_ans[381:380]));
Checker row15_12(.a(memory[ROW_15+9'd31:ROW_15+9'd30]), .b(memory[ROW_15+9'd23:ROW_15+9'd22]), .c(memory[ROW_15+9'd25:ROW_15+9'd24]),
.d(memory[ROW_15+9'd27:ROW_15+9'd26]), .e(memory[ROW_15+9'd29:ROW_15+9'd28]), .ans(row_ans[383:382]));
Summarize12 row15_sum(.check_ans(row_ans[383:360]), .out(row_sum[31:30]));
Checker col0_1(.a(memory[COL_0+9'd1:COL_0+9'd0]), .b(memory[COL_0+9'd33:COL_0+9'd32]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[1:0]));
Checker col0_2(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd33:COL_0+9'd32]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[3:2]));
Checker col0_3(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd65:COL_0+9'd64]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[5:4]));
Checker col0_4(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd97:COL_0+9'd96]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[7:6]));
Checker col0_5(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd129:COL_0+9'd128]), .ans(col_ans[9:8]));
Checker col0_6(.a(memory[COL_0+9'd161:COL_0+9'd160]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[11:10]));
Checker col0_7(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd193:COL_0+9'd192]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[13:12]));
Checker col0_8(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd225:COL_0+9'd224]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[15:14]));
Checker col0_9(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd257:COL_0+9'd256]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[17:16]));
Checker col0_10(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd289:COL_0+9'd288]), .ans(col_ans[19:18]));
Checker col0_11(.a(memory[COL_0+9'd321:COL_0+9'd320]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd449:COL_0+9'd448]), .ans(col_ans[21:20]));
Checker col0_12(.a(memory[COL_0+9'd481:COL_0+9'd480]), .b(memory[COL_0+9'd353:COL_0+9'd352]), .c(memory[COL_0+9'd385:COL_0+9'd384]),
.d(memory[COL_0+9'd417:COL_0+9'd416]), .e(memory[COL_0+9'd449:COL_0+9'd448]), .ans(col_ans[23:22]));
Summarize12 col0_sum(.check_ans(col_ans[23:0]), .out(col_sum[1:0]));
Checker col1_1(.a(memory[COL_1+9'd1:COL_1+9'd0]), .b(memory[COL_1+9'd33:COL_1+9'd32]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[25:24]));
Checker col1_2(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd33:COL_1+9'd32]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[27:26]));
Checker col1_3(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd65:COL_1+9'd64]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[29:28]));
Checker col1_4(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd97:COL_1+9'd96]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[31:30]));
Checker col1_5(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd129:COL_1+9'd128]), .ans(col_ans[33:32]));
Checker col1_6(.a(memory[COL_1+9'd161:COL_1+9'd160]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[35:34]));
Checker col1_7(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd193:COL_1+9'd192]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[37:36]));
Checker col1_8(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd225:COL_1+9'd224]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[39:38]));
Checker col1_9(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd257:COL_1+9'd256]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[41:40]));
Checker col1_10(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd289:COL_1+9'd288]), .ans(col_ans[43:42]));
Checker col1_11(.a(memory[COL_1+9'd321:COL_1+9'd320]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd449:COL_1+9'd448]), .ans(col_ans[45:44]));
Checker col1_12(.a(memory[COL_1+9'd481:COL_1+9'd480]), .b(memory[COL_1+9'd353:COL_1+9'd352]), .c(memory[COL_1+9'd385:COL_1+9'd384]),
.d(memory[COL_1+9'd417:COL_1+9'd416]), .e(memory[COL_1+9'd449:COL_1+9'd448]), .ans(col_ans[47:46]));
Summarize12 col1_sum(.check_ans(col_ans[47:24]), .out(col_sum[3:2]));
Checker col2_1(.a(memory[COL_2+9'd1:COL_2+9'd0]), .b(memory[COL_2+9'd33:COL_2+9'd32]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[49:48]));
Checker col2_2(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd33:COL_2+9'd32]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[51:50]));
Checker col2_3(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd65:COL_2+9'd64]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[53:52]));
Checker col2_4(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd97:COL_2+9'd96]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[55:54]));
Checker col2_5(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd129:COL_2+9'd128]), .ans(col_ans[57:56]));
Checker col2_6(.a(memory[COL_2+9'd161:COL_2+9'd160]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[59:58]));
Checker col2_7(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd193:COL_2+9'd192]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[61:60]));
Checker col2_8(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd225:COL_2+9'd224]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[63:62]));
Checker col2_9(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd257:COL_2+9'd256]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[65:64]));
Checker col2_10(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd289:COL_2+9'd288]), .ans(col_ans[67:66]));
Checker col2_11(.a(memory[COL_2+9'd321:COL_2+9'd320]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd449:COL_2+9'd448]), .ans(col_ans[69:68]));
Checker col2_12(.a(memory[COL_2+9'd481:COL_2+9'd480]), .b(memory[COL_2+9'd353:COL_2+9'd352]), .c(memory[COL_2+9'd385:COL_2+9'd384]),
.d(memory[COL_2+9'd417:COL_2+9'd416]), .e(memory[COL_2+9'd449:COL_2+9'd448]), .ans(col_ans[71:70]));
Summarize12 col2_sum(.check_ans(col_ans[71:48]), .out(col_sum[5:4]));
Checker col3_1(.a(memory[COL_3+9'd1:COL_3+9'd0]), .b(memory[COL_3+9'd33:COL_3+9'd32]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[73:72]));
Checker col3_2(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd33:COL_3+9'd32]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[75:74]));
Checker col3_3(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd65:COL_3+9'd64]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[77:76]));
Checker col3_4(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd97:COL_3+9'd96]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[79:78]));
Checker col3_5(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd129:COL_3+9'd128]), .ans(col_ans[81:80]));
Checker col3_6(.a(memory[COL_3+9'd161:COL_3+9'd160]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[83:82]));
Checker col3_7(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd193:COL_3+9'd192]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[85:84]));
Checker col3_8(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd225:COL_3+9'd224]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[87:86]));
Checker col3_9(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd257:COL_3+9'd256]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[89:88]));
Checker col3_10(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd289:COL_3+9'd288]), .ans(col_ans[91:90]));
Checker col3_11(.a(memory[COL_3+9'd321:COL_3+9'd320]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd449:COL_3+9'd448]), .ans(col_ans[93:92]));
Checker col3_12(.a(memory[COL_3+9'd481:COL_3+9'd480]), .b(memory[COL_3+9'd353:COL_3+9'd352]), .c(memory[COL_3+9'd385:COL_3+9'd384]),
.d(memory[COL_3+9'd417:COL_3+9'd416]), .e(memory[COL_3+9'd449:COL_3+9'd448]), .ans(col_ans[95:94]));
Summarize12 col3_sum(.check_ans(col_ans[95:72]), .out(col_sum[7:6]));
Checker col4_1(.a(memory[COL_4+9'd1:COL_4+9'd0]), .b(memory[COL_4+9'd33:COL_4+9'd32]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[97:96]));
Checker col4_2(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd33:COL_4+9'd32]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[99:98]));
Checker col4_3(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd65:COL_4+9'd64]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[101:100]));
Checker col4_4(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd97:COL_4+9'd96]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[103:102]));
Checker col4_5(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd129:COL_4+9'd128]), .ans(col_ans[105:104]));
Checker col4_6(.a(memory[COL_4+9'd161:COL_4+9'd160]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[107:106]));
Checker col4_7(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd193:COL_4+9'd192]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[109:108]));
Checker col4_8(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd225:COL_4+9'd224]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[111:110]));
Checker col4_9(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd257:COL_4+9'd256]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[113:112]));
Checker col4_10(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd289:COL_4+9'd288]), .ans(col_ans[115:114]));
Checker col4_11(.a(memory[COL_4+9'd321:COL_4+9'd320]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd449:COL_4+9'd448]), .ans(col_ans[117:116]));
Checker col4_12(.a(memory[COL_4+9'd481:COL_4+9'd480]), .b(memory[COL_4+9'd353:COL_4+9'd352]), .c(memory[COL_4+9'd385:COL_4+9'd384]),
.d(memory[COL_4+9'd417:COL_4+9'd416]), .e(memory[COL_4+9'd449:COL_4+9'd448]), .ans(col_ans[119:118]));
Summarize12 col4_sum(.check_ans(col_ans[119:96]), .out(col_sum[9:8]));
Checker col5_1(.a(memory[COL_5+9'd1:COL_5+9'd0]), .b(memory[COL_5+9'd33:COL_5+9'd32]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[121:120]));
Checker col5_2(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd33:COL_5+9'd32]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[123:122]));
Checker col5_3(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd65:COL_5+9'd64]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[125:124]));
Checker col5_4(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd97:COL_5+9'd96]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[127:126]));
Checker col5_5(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd129:COL_5+9'd128]), .ans(col_ans[129:128]));
Checker col5_6(.a(memory[COL_5+9'd161:COL_5+9'd160]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[131:130]));
Checker col5_7(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd193:COL_5+9'd192]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[133:132]));
Checker col5_8(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd225:COL_5+9'd224]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[135:134]));
Checker col5_9(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd257:COL_5+9'd256]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[137:136]));
Checker col5_10(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd289:COL_5+9'd288]), .ans(col_ans[139:138]));
Checker col5_11(.a(memory[COL_5+9'd321:COL_5+9'd320]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd449:COL_5+9'd448]), .ans(col_ans[141:140]));
Checker col5_12(.a(memory[COL_5+9'd481:COL_5+9'd480]), .b(memory[COL_5+9'd353:COL_5+9'd352]), .c(memory[COL_5+9'd385:COL_5+9'd384]),
.d(memory[COL_5+9'd417:COL_5+9'd416]), .e(memory[COL_5+9'd449:COL_5+9'd448]), .ans(col_ans[143:142]));
Summarize12 col5_sum(.check_ans(col_ans[143:120]), .out(col_sum[11:10]));
Checker col6_1(.a(memory[COL_6+9'd1:COL_6+9'd0]), .b(memory[COL_6+9'd33:COL_6+9'd32]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[145:144]));
Checker col6_2(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd33:COL_6+9'd32]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[147:146]));
Checker col6_3(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd65:COL_6+9'd64]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[149:148]));
Checker col6_4(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd97:COL_6+9'd96]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[151:150]));
Checker col6_5(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd129:COL_6+9'd128]), .ans(col_ans[153:152]));
Checker col6_6(.a(memory[COL_6+9'd161:COL_6+9'd160]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[155:154]));
Checker col6_7(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd193:COL_6+9'd192]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[157:156]));
Checker col6_8(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd225:COL_6+9'd224]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[159:158]));
Checker col6_9(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd257:COL_6+9'd256]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[161:160]));
Checker col6_10(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd289:COL_6+9'd288]), .ans(col_ans[163:162]));
Checker col6_11(.a(memory[COL_6+9'd321:COL_6+9'd320]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd449:COL_6+9'd448]), .ans(col_ans[165:164]));
Checker col6_12(.a(memory[COL_6+9'd481:COL_6+9'd480]), .b(memory[COL_6+9'd353:COL_6+9'd352]), .c(memory[COL_6+9'd385:COL_6+9'd384]),
.d(memory[COL_6+9'd417:COL_6+9'd416]), .e(memory[COL_6+9'd449:COL_6+9'd448]), .ans(col_ans[167:166]));
Summarize12 col6_sum(.check_ans(col_ans[167:144]), .out(col_sum[13:12]));
Checker col7_1(.a(memory[COL_7+9'd1:COL_7+9'd0]), .b(memory[COL_7+9'd33:COL_7+9'd32]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[169:168]));
Checker col7_2(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd33:COL_7+9'd32]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[171:170]));
Checker col7_3(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd65:COL_7+9'd64]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[173:172]));
Checker col7_4(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd97:COL_7+9'd96]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[175:174]));
Checker col7_5(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd129:COL_7+9'd128]), .ans(col_ans[177:176]));
Checker col7_6(.a(memory[COL_7+9'd161:COL_7+9'd160]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[179:178]));
Checker col7_7(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd193:COL_7+9'd192]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[181:180]));
Checker col7_8(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd225:COL_7+9'd224]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[183:182]));
Checker col7_9(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd257:COL_7+9'd256]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[185:184]));
Checker col7_10(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd289:COL_7+9'd288]), .ans(col_ans[187:186]));
Checker col7_11(.a(memory[COL_7+9'd321:COL_7+9'd320]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd449:COL_7+9'd448]), .ans(col_ans[189:188]));
Checker col7_12(.a(memory[COL_7+9'd481:COL_7+9'd480]), .b(memory[COL_7+9'd353:COL_7+9'd352]), .c(memory[COL_7+9'd385:COL_7+9'd384]),
.d(memory[COL_7+9'd417:COL_7+9'd416]), .e(memory[COL_7+9'd449:COL_7+9'd448]), .ans(col_ans[191:190]));
Summarize12 col7_sum(.check_ans(col_ans[191:168]), .out(col_sum[15:14]));
Checker col8_1(.a(memory[COL_8+9'd1:COL_8+9'd0]), .b(memory[COL_8+9'd33:COL_8+9'd32]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[193:192]));
Checker col8_2(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd33:COL_8+9'd32]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[195:194]));
Checker col8_3(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd65:COL_8+9'd64]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[197:196]));
Checker col8_4(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd97:COL_8+9'd96]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[199:198]));
Checker col8_5(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd129:COL_8+9'd128]), .ans(col_ans[201:200]));
Checker col8_6(.a(memory[COL_8+9'd161:COL_8+9'd160]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[203:202]));
Checker col8_7(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd193:COL_8+9'd192]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[205:204]));
Checker col8_8(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd225:COL_8+9'd224]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[207:206]));
Checker col8_9(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd257:COL_8+9'd256]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[209:208]));
Checker col8_10(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd289:COL_8+9'd288]), .ans(col_ans[211:210]));
Checker col8_11(.a(memory[COL_8+9'd321:COL_8+9'd320]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd449:COL_8+9'd448]), .ans(col_ans[213:212]));
Checker col8_12(.a(memory[COL_8+9'd481:COL_8+9'd480]), .b(memory[COL_8+9'd353:COL_8+9'd352]), .c(memory[COL_8+9'd385:COL_8+9'd384]),
.d(memory[COL_8+9'd417:COL_8+9'd416]), .e(memory[COL_8+9'd449:COL_8+9'd448]), .ans(col_ans[215:214]));
Summarize12 col8_sum(.check_ans(col_ans[215:192]), .out(col_sum[17:16]));
Checker col9_1(.a(memory[COL_9+9'd1:COL_9+9'd0]), .b(memory[COL_9+9'd33:COL_9+9'd32]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[217:216]));
Checker col9_2(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd33:COL_9+9'd32]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[219:218]));
Checker col9_3(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd65:COL_9+9'd64]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[221:220]));
Checker col9_4(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd97:COL_9+9'd96]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[223:222]));
Checker col9_5(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd129:COL_9+9'd128]), .ans(col_ans[225:224]));
Checker col9_6(.a(memory[COL_9+9'd161:COL_9+9'd160]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[227:226]));
Checker col9_7(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd193:COL_9+9'd192]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[229:228]));
Checker col9_8(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd225:COL_9+9'd224]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[231:230]));
Checker col9_9(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd257:COL_9+9'd256]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[233:232]));
Checker col9_10(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd289:COL_9+9'd288]), .ans(col_ans[235:234]));
Checker col9_11(.a(memory[COL_9+9'd321:COL_9+9'd320]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd449:COL_9+9'd448]), .ans(col_ans[237:236]));
Checker col9_12(.a(memory[COL_9+9'd481:COL_9+9'd480]), .b(memory[COL_9+9'd353:COL_9+9'd352]), .c(memory[COL_9+9'd385:COL_9+9'd384]),
.d(memory[COL_9+9'd417:COL_9+9'd416]), .e(memory[COL_9+9'd449:COL_9+9'd448]), .ans(col_ans[239:238]));
Summarize12 col9_sum(.check_ans(col_ans[239:216]), .out(col_sum[19:18]));
Checker col10_1(.a(memory[COL_10+9'd1:COL_10+9'd0]), .b(memory[COL_10+9'd33:COL_10+9'd32]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[241:240]));
Checker col10_2(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd33:COL_10+9'd32]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[243:242]));
Checker col10_3(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd65:COL_10+9'd64]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[245:244]));
Checker col10_4(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd97:COL_10+9'd96]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[247:246]));
Checker col10_5(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd129:COL_10+9'd128]), .ans(col_ans[249:248]));
Checker col10_6(.a(memory[COL_10+9'd161:COL_10+9'd160]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[251:250]));
Checker col10_7(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd193:COL_10+9'd192]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[253:252]));
Checker col10_8(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd225:COL_10+9'd224]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[255:254]));
Checker col10_9(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd257:COL_10+9'd256]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[257:256]));
Checker col10_10(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd289:COL_10+9'd288]), .ans(col_ans[259:258]));
Checker col10_11(.a(memory[COL_10+9'd321:COL_10+9'd320]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd449:COL_10+9'd448]), .ans(col_ans[261:260]));
Checker col10_12(.a(memory[COL_10+9'd481:COL_10+9'd480]), .b(memory[COL_10+9'd353:COL_10+9'd352]), .c(memory[COL_10+9'd385:COL_10+9'd384]),
.d(memory[COL_10+9'd417:COL_10+9'd416]), .e(memory[COL_10+9'd449:COL_10+9'd448]), .ans(col_ans[263:262]));
Summarize12 col10_sum(.check_ans(col_ans[263:240]), .out(col_sum[21:20]));
Checker col11_1(.a(memory[COL_11+9'd1:COL_11+9'd0]), .b(memory[COL_11+9'd33:COL_11+9'd32]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[265:264]));
Checker col11_2(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd33:COL_11+9'd32]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[267:266]));
Checker col11_3(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd65:COL_11+9'd64]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[269:268]));
Checker col11_4(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd97:COL_11+9'd96]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[271:270]));
Checker col11_5(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd129:COL_11+9'd128]), .ans(col_ans[273:272]));
Checker col11_6(.a(memory[COL_11+9'd161:COL_11+9'd160]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[275:274]));
Checker col11_7(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd193:COL_11+9'd192]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[277:276]));
Checker col11_8(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd225:COL_11+9'd224]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[279:278]));
Checker col11_9(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd257:COL_11+9'd256]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[281:280]));
Checker col11_10(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd289:COL_11+9'd288]), .ans(col_ans[283:282]));
Checker col11_11(.a(memory[COL_11+9'd321:COL_11+9'd320]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd449:COL_11+9'd448]), .ans(col_ans[285:284]));
Checker col11_12(.a(memory[COL_11+9'd481:COL_11+9'd480]), .b(memory[COL_11+9'd353:COL_11+9'd352]), .c(memory[COL_11+9'd385:COL_11+9'd384]),
.d(memory[COL_11+9'd417:COL_11+9'd416]), .e(memory[COL_11+9'd449:COL_11+9'd448]), .ans(col_ans[287:286]));
Summarize12 col11_sum(.check_ans(col_ans[287:264]), .out(col_sum[23:22]));
Checker col12_1(.a(memory[COL_12+9'd1:COL_12+9'd0]), .b(memory[COL_12+9'd33:COL_12+9'd32]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[289:288]));
Checker col12_2(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd33:COL_12+9'd32]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[291:290]));
Checker col12_3(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd65:COL_12+9'd64]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[293:292]));
Checker col12_4(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd97:COL_12+9'd96]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[295:294]));
Checker col12_5(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd129:COL_12+9'd128]), .ans(col_ans[297:296]));
Checker col12_6(.a(memory[COL_12+9'd161:COL_12+9'd160]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[299:298]));
Checker col12_7(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd193:COL_12+9'd192]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[301:300]));
Checker col12_8(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd225:COL_12+9'd224]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[303:302]));
Checker col12_9(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd257:COL_12+9'd256]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[305:304]));
Checker col12_10(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd289:COL_12+9'd288]), .ans(col_ans[307:306]));
Checker col12_11(.a(memory[COL_12+9'd321:COL_12+9'd320]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd449:COL_12+9'd448]), .ans(col_ans[309:308]));
Checker col12_12(.a(memory[COL_12+9'd481:COL_12+9'd480]), .b(memory[COL_12+9'd353:COL_12+9'd352]), .c(memory[COL_12+9'd385:COL_12+9'd384]),
.d(memory[COL_12+9'd417:COL_12+9'd416]), .e(memory[COL_12+9'd449:COL_12+9'd448]), .ans(col_ans[311:310]));
Summarize12 col12_sum(.check_ans(col_ans[311:288]), .out(col_sum[25:24]));
Checker col13_1(.a(memory[COL_13+9'd1:COL_13+9'd0]), .b(memory[COL_13+9'd33:COL_13+9'd32]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[313:312]));
Checker col13_2(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd33:COL_13+9'd32]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[315:314]));
Checker col13_3(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd65:COL_13+9'd64]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[317:316]));
Checker col13_4(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd97:COL_13+9'd96]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[319:318]));
Checker col13_5(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd129:COL_13+9'd128]), .ans(col_ans[321:320]));
Checker col13_6(.a(memory[COL_13+9'd161:COL_13+9'd160]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[323:322]));
Checker col13_7(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd193:COL_13+9'd192]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[325:324]));
Checker col13_8(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd225:COL_13+9'd224]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[327:326]));
Checker col13_9(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd257:COL_13+9'd256]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[329:328]));
Checker col13_10(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd289:COL_13+9'd288]), .ans(col_ans[331:330]));
Checker col13_11(.a(memory[COL_13+9'd321:COL_13+9'd320]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd449:COL_13+9'd448]), .ans(col_ans[333:332]));
Checker col13_12(.a(memory[COL_13+9'd481:COL_13+9'd480]), .b(memory[COL_13+9'd353:COL_13+9'd352]), .c(memory[COL_13+9'd385:COL_13+9'd384]),
.d(memory[COL_13+9'd417:COL_13+9'd416]), .e(memory[COL_13+9'd449:COL_13+9'd448]), .ans(col_ans[335:334]));
Summarize12 col13_sum(.check_ans(col_ans[335:312]), .out(col_sum[27:26]));
Checker col14_1(.a(memory[COL_14+9'd1:COL_14+9'd0]), .b(memory[COL_14+9'd33:COL_14+9'd32]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[337:336]));
Checker col14_2(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd33:COL_14+9'd32]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[339:338]));
Checker col14_3(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd65:COL_14+9'd64]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[341:340]));
Checker col14_4(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd97:COL_14+9'd96]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[343:342]));
Checker col14_5(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd129:COL_14+9'd128]), .ans(col_ans[345:344]));
Checker col14_6(.a(memory[COL_14+9'd161:COL_14+9'd160]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[347:346]));
Checker col14_7(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd193:COL_14+9'd192]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[349:348]));
Checker col14_8(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd225:COL_14+9'd224]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[351:350]));
Checker col14_9(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd257:COL_14+9'd256]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[353:352]));
Checker col14_10(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd289:COL_14+9'd288]), .ans(col_ans[355:354]));
Checker col14_11(.a(memory[COL_14+9'd321:COL_14+9'd320]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd449:COL_14+9'd448]), .ans(col_ans[357:356]));
Checker col14_12(.a(memory[COL_14+9'd481:COL_14+9'd480]), .b(memory[COL_14+9'd353:COL_14+9'd352]), .c(memory[COL_14+9'd385:COL_14+9'd384]),
.d(memory[COL_14+9'd417:COL_14+9'd416]), .e(memory[COL_14+9'd449:COL_14+9'd448]), .ans(col_ans[359:358]));
Summarize12 col14_sum(.check_ans(col_ans[359:336]), .out(col_sum[29:28]));
Checker col15_1(.a(memory[COL_15+9'd1:COL_15+9'd0]), .b(memory[COL_15+9'd33:COL_15+9'd32]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[361:360]));
Checker col15_2(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd33:COL_15+9'd32]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[363:362]));
Checker col15_3(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd65:COL_15+9'd64]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[365:364]));
Checker col15_4(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd97:COL_15+9'd96]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[367:366]));
Checker col15_5(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd129:COL_15+9'd128]), .ans(col_ans[369:368]));
Checker col15_6(.a(memory[COL_15+9'd161:COL_15+9'd160]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[370:370]));
Checker col15_7(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd193:COL_15+9'd192]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[373:372]));
Checker col15_8(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd225:COL_15+9'd224]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[375:374]));
Checker col15_9(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd257:COL_15+9'd256]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[377:376]));
Checker col15_10(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd289:COL_15+9'd288]), .ans(col_ans[379:378]));
Checker col15_11(.a(memory[COL_15+9'd321:COL_15+9'd320]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd449:COL_15+9'd448]), .ans(col_ans[381:380]));
Checker col15_12(.a(memory[COL_15+9'd481:COL_15+9'd480]), .b(memory[COL_15+9'd353:COL_15+9'd352]), .c(memory[COL_15+9'd385:COL_15+9'd384]),
.d(memory[COL_15+9'd417:COL_15+9'd416]), .e(memory[COL_15+9'd449:COL_15+9'd448]), .ans(col_ans[383:382]));
Summarize12 col15_sum(.check_ans(col_ans[383:360]), .out(col_sum[31:30]));
wire [3:0] sum_board;
Summarize16 sum_rows(.check_ans(row_sum[31:0]), .out(sum_board[1:0]));
Summarize16 sum_cols(.check_ans(col_sum[31:0]), .out(sum_board[3:2]));
always@(*)
begin
if((sum_board[1:0] == 2'b00) && (sum_board[3:2] == 2'b00)) ans[1:0]=2'b00;
else if((sum_board[1:0] == 2'b10) || (sum_board[3:2] == 2'b10)) ans[1:0]=2'b10;
else ans[1:0]=2'b01;
end
endmodule | 0 |
4,386 | data/full_repos/permissive/109608368/check/Checker.v | 109,608,368 | Checker.v | v | 38 | 100 | [] | ['general public license', 'free software foundation'] | [] | [(23, 37)] | null | data/verilator_xmls/352ad8e1-b86f-46a7-9b02-ee9b02099aa5.xml | null | 2,626 | module | module Checker(a, b, c, d, e, ans);
input [1:0] a,b,c,d,e;
output reg [1:0] ans;
always@(*)
begin
if((a==2'b01) && (b==2'b01) && (c==2'b01) && (d==2'b01) && (e==2'b01)) ans = 2'b01;
else if ((a==2'b10) && (b==2'b10) && (c==2'b10) && (d==2'b10) && (e==2'b10)) ans = 2'b10;
else ans = 2'b00;
end
endmodule | module Checker(a, b, c, d, e, ans); |
input [1:0] a,b,c,d,e;
output reg [1:0] ans;
always@(*)
begin
if((a==2'b01) && (b==2'b01) && (c==2'b01) && (d==2'b01) && (e==2'b01)) ans = 2'b01;
else if ((a==2'b10) && (b==2'b10) && (c==2'b10) && (d==2'b10) && (e==2'b10)) ans = 2'b10;
else ans = 2'b00;
end
endmodule | 0 |
4,387 | data/full_repos/permissive/109608368/check/Summarize12.v | 109,608,368 | Summarize12.v | v | 46 | 137 | [] | ['general public license', 'free software foundation'] | [] | [(23, 45)] | null | data/verilator_xmls/177ac7e2-f299-4a69-9016-bd9932ab677c.xml | null | 2,627 | module | module Summarize12(check_ans, out);
input [23:0] check_ans;
output reg [1:0] out;
always@(*)
begin
if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00) && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00)
&& (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00)
&& (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00))
out = 2'b00;
else if((check_ans[1:0] == 2'b01) || (check_ans[3:2] == 2'b01) || (check_ans[5:4] == 2'b01) || (check_ans[7:6] == 2'b01)
|| (check_ans[9:8] == 2'b01) || (check_ans[11:10] == 2'b01) || (check_ans[13:12] == 2'b01) || (check_ans[15:14] == 2'b01)
|| (check_ans[17:16] == 2'b01) || (check_ans[19:18] == 2'b01) || (check_ans[21:20] == 2'b01) || (check_ans[23:22] == 2'b01))
out = 2'b01;
else
out = 2'b10;
end
endmodule | module Summarize12(check_ans, out); |
input [23:0] check_ans;
output reg [1:0] out;
always@(*)
begin
if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00) && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00)
&& (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00)
&& (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00))
out = 2'b00;
else if((check_ans[1:0] == 2'b01) || (check_ans[3:2] == 2'b01) || (check_ans[5:4] == 2'b01) || (check_ans[7:6] == 2'b01)
|| (check_ans[9:8] == 2'b01) || (check_ans[11:10] == 2'b01) || (check_ans[13:12] == 2'b01) || (check_ans[15:14] == 2'b01)
|| (check_ans[17:16] == 2'b01) || (check_ans[19:18] == 2'b01) || (check_ans[21:20] == 2'b01) || (check_ans[23:22] == 2'b01))
out = 2'b01;
else
out = 2'b10;
end
endmodule | 0 |
4,388 | data/full_repos/permissive/109608368/memory/Enable_control.v | 109,608,368 | Enable_control.v | v | 33 | 107 | [] | ['general public license', 'free software foundation'] | [] | [(22, 32)] | null | data/verilator_xmls/ddec4607-72f3-4e03-8c64-8cadd3d3a7db.xml | null | 2,630 | module | module Enable_control(current_state, out);
input [1:0] current_state;
output reg out;
always@(*)
begin
if(current_state[1:0] != 2'b00) out <= 0;
else out <= 1;
end
endmodule | module Enable_control(current_state, out); |
input [1:0] current_state;
output reg out;
always@(*)
begin
if(current_state[1:0] != 2'b00) out <= 0;
else out <= 1;
end
endmodule | 0 |
4,389 | data/full_repos/permissive/109608368/memory/Enable_select.v | 109,608,368 | Enable_select.v | v | 55 | 101 | [] | ['general public license', 'free software foundation'] | [] | [(19, 54)] | null | data/verilator_xmls/8b39c1d4-5f0b-4858-9204-d13c90b479db.xml | null | 2,631 | module | module Enable_select(enable, select, out);
input [3:0] select;
input enable;
output [15:0] out;
reg [15:0] reg_out;
initial begin
reg_out[15:0] = 16'd0;
end
always @ (*)
begin
case (select[3:0])
4'd0: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0001 : 16'd0;
4'd1: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0010 : 16'd0;
4'd2: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0100 : 16'd0;
4'd3: reg_out[15:0] <= enable ? 16'b0000_0000_0000_1000 : 16'd0;
4'd4: reg_out[15:0] <= enable ? 16'b0000_0000_0001_0000 : 16'd0;
4'd5: reg_out[15:0] <= enable ? 16'b0000_0000_0010_0000 : 16'd0;
4'd6: reg_out[15:0] <= enable ? 16'b0000_0000_0100_0000 : 16'd0;
4'd7: reg_out[15:0] <= enable ? 16'b0000_0000_1000_0000 : 16'd0;
4'd8: reg_out[15:0] <= enable ? 16'b0000_0001_0000_0000 : 16'd0;
4'd9: reg_out[15:0] <= enable ? 16'b0000_0010_0000_0000 : 16'd0;
4'd10: reg_out[15:0] <= enable ? 16'b0000_0100_0000_0000 : 16'd0;
4'd11: reg_out[15:0] <= enable ? 16'b0000_1000_0000_0000 : 16'd0;
4'd12: reg_out[15:0] <= enable ? 16'b0001_0000_0000_0000 : 16'd0;
4'd13: reg_out[15:0] <= enable ? 16'b0010_0000_0000_0000 : 16'd0;
4'd14: reg_out[15:0] <= enable ? 16'b0100_0000_0000_0000 : 16'd0;
4'd15: reg_out[15:0] <= enable ? 16'b1000_0000_0000_0000 : 16'd0;
endcase
end
assign out[15:0] = reg_out[15:0];
endmodule | module Enable_select(enable, select, out); |
input [3:0] select;
input enable;
output [15:0] out;
reg [15:0] reg_out;
initial begin
reg_out[15:0] = 16'd0;
end
always @ (*)
begin
case (select[3:0])
4'd0: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0001 : 16'd0;
4'd1: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0010 : 16'd0;
4'd2: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0100 : 16'd0;
4'd3: reg_out[15:0] <= enable ? 16'b0000_0000_0000_1000 : 16'd0;
4'd4: reg_out[15:0] <= enable ? 16'b0000_0000_0001_0000 : 16'd0;
4'd5: reg_out[15:0] <= enable ? 16'b0000_0000_0010_0000 : 16'd0;
4'd6: reg_out[15:0] <= enable ? 16'b0000_0000_0100_0000 : 16'd0;
4'd7: reg_out[15:0] <= enable ? 16'b0000_0000_1000_0000 : 16'd0;
4'd8: reg_out[15:0] <= enable ? 16'b0000_0001_0000_0000 : 16'd0;
4'd9: reg_out[15:0] <= enable ? 16'b0000_0010_0000_0000 : 16'd0;
4'd10: reg_out[15:0] <= enable ? 16'b0000_0100_0000_0000 : 16'd0;
4'd11: reg_out[15:0] <= enable ? 16'b0000_1000_0000_0000 : 16'd0;
4'd12: reg_out[15:0] <= enable ? 16'b0001_0000_0000_0000 : 16'd0;
4'd13: reg_out[15:0] <= enable ? 16'b0010_0000_0000_0000 : 16'd0;
4'd14: reg_out[15:0] <= enable ? 16'b0100_0000_0000_0000 : 16'd0;
4'd15: reg_out[15:0] <= enable ? 16'b1000_0000_0000_0000 : 16'd0;
endcase
end
assign out[15:0] = reg_out[15:0];
endmodule | 0 |
4,390 | data/full_repos/permissive/109608368/memory/Memory_Read.v | 109,608,368 | Memory_Read.v | v | 76 | 101 | [] | ['general public license', 'free software foundation'] | [] | [(24, 75)] | null | null | 1: b"%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:39: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout0(.in(in[31:0]), .select(select[3:0]), .out(row_out[1:0]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Y_Coordinate_Select_Read\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Y_Coordinate_Select_Read.v\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Y_Coordinate_Select_Read.sv\n Y_Coordinate_Select_Read\n Y_Coordinate_Select_Read.v\n Y_Coordinate_Select_Read.sv\n obj_dir/Y_Coordinate_Select_Read\n obj_dir/Y_Coordinate_Select_Read.v\n obj_dir/Y_Coordinate_Select_Read.sv\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:41: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout1(.in(in[63:32]), .select(select[3:0]), .out(row_out[3:2]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:43: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout2(.in(in[95:64]), .select(select[3:0]), .out(row_out[5:4]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:45: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout3(.in(in[127:96]), .select(select[3:0]), .out(row_out[7:6]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:47: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout4(.in(in[159:128]), .select(select[3:0]), .out(row_out[9:8]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:49: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout5(.in(in[191:160]), .select(select[3:0]), .out(row_out[11:10]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:51: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout6(.in(in[223:192]), .select(select[3:0]), .out(row_out[13:12]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:53: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout7(.in(in[255:224]), .select(select[3:0]), .out(row_out[15:14]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:55: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout8(.in(in[287:256]), .select(select[3:0]), .out(row_out[17:16]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:57: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout9(.in(in[319:288]), .select(select[3:0]), .out(row_out[19:18]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:59: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout10(.in(in[351:320]), .select(select[3:0]), .out(row_out[21:20]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:61: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout11(.in(in[383:352]), .select(select[3:0]), .out(row_out[23:22]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:63: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout12(.in(in[415:384]), .select(select[3:0]), .out(row_out[25:24]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:65: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout13(.in(in[447:416]), .select(select[3:0]), .out(row_out[27:26]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:67: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout14(.in(in[479:448]), .select(select[3:0]), .out(row_out[29:28]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:69: Cannot find file containing module: 'Y_Coordinate_Select_Read'\n Y_Coordinate_Select_Read rowout15(.in(in[511:480]), .select(select[3:0]), .out(row_out[31:30]));\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Memory_Read.v:73: Cannot find file containing module: 'Select16to1'\n Select16to1 getDataFromRow(.in(row_out[31:0]), .select(select[7:4]), .out(out[1:0]));\n ^~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 2,632 | module | module Memory_Read(in, select, out);
output [1:0] out;
input [7:0] select;
input [511:0] in;
wire [31:0] row_out;
Y_Coordinate_Select_Read rowout0(.in(in[31:0]), .select(select[3:0]), .out(row_out[1:0]));
Y_Coordinate_Select_Read rowout1(.in(in[63:32]), .select(select[3:0]), .out(row_out[3:2]));
Y_Coordinate_Select_Read rowout2(.in(in[95:64]), .select(select[3:0]), .out(row_out[5:4]));
Y_Coordinate_Select_Read rowout3(.in(in[127:96]), .select(select[3:0]), .out(row_out[7:6]));
Y_Coordinate_Select_Read rowout4(.in(in[159:128]), .select(select[3:0]), .out(row_out[9:8]));
Y_Coordinate_Select_Read rowout5(.in(in[191:160]), .select(select[3:0]), .out(row_out[11:10]));
Y_Coordinate_Select_Read rowout6(.in(in[223:192]), .select(select[3:0]), .out(row_out[13:12]));
Y_Coordinate_Select_Read rowout7(.in(in[255:224]), .select(select[3:0]), .out(row_out[15:14]));
Y_Coordinate_Select_Read rowout8(.in(in[287:256]), .select(select[3:0]), .out(row_out[17:16]));
Y_Coordinate_Select_Read rowout9(.in(in[319:288]), .select(select[3:0]), .out(row_out[19:18]));
Y_Coordinate_Select_Read rowout10(.in(in[351:320]), .select(select[3:0]), .out(row_out[21:20]));
Y_Coordinate_Select_Read rowout11(.in(in[383:352]), .select(select[3:0]), .out(row_out[23:22]));
Y_Coordinate_Select_Read rowout12(.in(in[415:384]), .select(select[3:0]), .out(row_out[25:24]));
Y_Coordinate_Select_Read rowout13(.in(in[447:416]), .select(select[3:0]), .out(row_out[27:26]));
Y_Coordinate_Select_Read rowout14(.in(in[479:448]), .select(select[3:0]), .out(row_out[29:28]));
Y_Coordinate_Select_Read rowout15(.in(in[511:480]), .select(select[3:0]), .out(row_out[31:30]));
Select16to1 getDataFromRow(.in(row_out[31:0]), .select(select[7:4]), .out(out[1:0]));
endmodule | module Memory_Read(in, select, out); |
output [1:0] out;
input [7:0] select;
input [511:0] in;
wire [31:0] row_out;
Y_Coordinate_Select_Read rowout0(.in(in[31:0]), .select(select[3:0]), .out(row_out[1:0]));
Y_Coordinate_Select_Read rowout1(.in(in[63:32]), .select(select[3:0]), .out(row_out[3:2]));
Y_Coordinate_Select_Read rowout2(.in(in[95:64]), .select(select[3:0]), .out(row_out[5:4]));
Y_Coordinate_Select_Read rowout3(.in(in[127:96]), .select(select[3:0]), .out(row_out[7:6]));
Y_Coordinate_Select_Read rowout4(.in(in[159:128]), .select(select[3:0]), .out(row_out[9:8]));
Y_Coordinate_Select_Read rowout5(.in(in[191:160]), .select(select[3:0]), .out(row_out[11:10]));
Y_Coordinate_Select_Read rowout6(.in(in[223:192]), .select(select[3:0]), .out(row_out[13:12]));
Y_Coordinate_Select_Read rowout7(.in(in[255:224]), .select(select[3:0]), .out(row_out[15:14]));
Y_Coordinate_Select_Read rowout8(.in(in[287:256]), .select(select[3:0]), .out(row_out[17:16]));
Y_Coordinate_Select_Read rowout9(.in(in[319:288]), .select(select[3:0]), .out(row_out[19:18]));
Y_Coordinate_Select_Read rowout10(.in(in[351:320]), .select(select[3:0]), .out(row_out[21:20]));
Y_Coordinate_Select_Read rowout11(.in(in[383:352]), .select(select[3:0]), .out(row_out[23:22]));
Y_Coordinate_Select_Read rowout12(.in(in[415:384]), .select(select[3:0]), .out(row_out[25:24]));
Y_Coordinate_Select_Read rowout13(.in(in[447:416]), .select(select[3:0]), .out(row_out[27:26]));
Y_Coordinate_Select_Read rowout14(.in(in[479:448]), .select(select[3:0]), .out(row_out[29:28]));
Y_Coordinate_Select_Read rowout15(.in(in[511:480]), .select(select[3:0]), .out(row_out[31:30]));
Select16to1 getDataFromRow(.in(row_out[31:0]), .select(select[7:4]), .out(out[1:0]));
endmodule | 0 |
4,391 | data/full_repos/permissive/109608368/memory/PointInfor.v | 109,608,368 | PointInfor.v | v | 35 | 107 | [] | ['general public license', 'free software foundation'] | [] | [(23, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/109608368/memory/PointInfor.v:29: Cannot find file containing module: 'D_Flip_Flop'\n D_Flip_Flop first_bit(.d(d[1]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[1]));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/D_Flip_Flop\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/D_Flip_Flop.v\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/D_Flip_Flop.sv\n D_Flip_Flop\n D_Flip_Flop.v\n D_Flip_Flop.sv\n obj_dir/D_Flip_Flop\n obj_dir/D_Flip_Flop.v\n obj_dir/D_Flip_Flop.sv\n%Error: data/full_repos/permissive/109608368/memory/PointInfor.v:31: Cannot find file containing module: 'D_Flip_Flop'\n D_Flip_Flop second_bit(.d(d[0]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[0]));\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,634 | module | module PointInfor(d, clock, reset, write_enable, q);
input [1:0] d;
input clock, reset, write_enable;
output [1:0] q;
D_Flip_Flop first_bit(.d(d[1]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[1]));
D_Flip_Flop second_bit(.d(d[0]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[0]));
endmodule | module PointInfor(d, clock, reset, write_enable, q); |
input [1:0] d;
input clock, reset, write_enable;
output [1:0] q;
D_Flip_Flop first_bit(.d(d[1]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[1]));
D_Flip_Flop second_bit(.d(d[0]), .clock(clock), .write_enable(write_enable), .reset(reset), .q(q[0]));
endmodule | 0 |
4,392 | data/full_repos/permissive/109608368/memory/Select16to1.v | 109,608,368 | Select16to1.v | v | 55 | 98 | [] | ['general public license', 'free software foundation'] | [] | [(23, 54)] | null | data/verilator_xmls/ed6c2b03-a1c3-4db0-b0a1-d262e92210e6.xml | null | 2,635 | module | module Select16to1(in, select, out);
input [31:0] in;
input [3:0] select;
output [1:0] out;
reg [1:0] reg_out;
always @ (*)
begin
case (select[3:0])
4'd0: reg_out[1:0] <= in[1:0];
4'd1: reg_out[1:0] <= in[3:2];
4'd2: reg_out[1:0] <= in[5:4];
4'd3: reg_out[1:0] <= in[7:6];
4'd4: reg_out[1:0] <= in[9:8];
4'd5: reg_out[1:0] <= in[11:10];
4'd6: reg_out[1:0] <= in[13:12];
4'd7: reg_out[1:0] <= in[15:14];
4'd8: reg_out[1:0] <= in[17:16];
4'd9: reg_out[1:0] <= in[19:18];
4'd10: reg_out[1:0] <= in[21:20];
4'd11: reg_out[1:0] <= in[23:22];
4'd12: reg_out[1:0] <= in[25:24];
4'd13: reg_out[1:0] <= in[27:26];
4'd14: reg_out[1:0] <= in[29:28];
4'd15: reg_out[1:0] <= in[31:30];
endcase
end
assign out[1:0] = reg_out[1:0];
endmodule | module Select16to1(in, select, out); |
input [31:0] in;
input [3:0] select;
output [1:0] out;
reg [1:0] reg_out;
always @ (*)
begin
case (select[3:0])
4'd0: reg_out[1:0] <= in[1:0];
4'd1: reg_out[1:0] <= in[3:2];
4'd2: reg_out[1:0] <= in[5:4];
4'd3: reg_out[1:0] <= in[7:6];
4'd4: reg_out[1:0] <= in[9:8];
4'd5: reg_out[1:0] <= in[11:10];
4'd6: reg_out[1:0] <= in[13:12];
4'd7: reg_out[1:0] <= in[15:14];
4'd8: reg_out[1:0] <= in[17:16];
4'd9: reg_out[1:0] <= in[19:18];
4'd10: reg_out[1:0] <= in[21:20];
4'd11: reg_out[1:0] <= in[23:22];
4'd12: reg_out[1:0] <= in[25:24];
4'd13: reg_out[1:0] <= in[27:26];
4'd14: reg_out[1:0] <= in[29:28];
4'd15: reg_out[1:0] <= in[31:30];
endcase
end
assign out[1:0] = reg_out[1:0];
endmodule | 0 |
4,393 | data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v | 109,608,368 | Y_Coordinate_Select_Write.v | v | 78 | 123 | [] | ['general public license', 'free software foundation'] | [] | [(24, 77)] | null | null | 1: b"%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:37: Cannot find file containing module: 'Select1to16'\n Select1to16 transDataToPoint(.in(in[1:0]), .select(select[3:0]), .out(point_in[31:0]));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Select1to16\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Select1to16.v\n data/full_repos/permissive/109608368/memory,data/full_repos/permissive/109608368/Select1to16.sv\n Select1to16\n Select1to16.v\n Select1to16.sv\n obj_dir/Select1to16\n obj_dir/Select1to16.v\n obj_dir/Select1to16.sv\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:39: Cannot find file containing module: 'Enable_select'\n Enable_select enableEachPoint(.enable(write_enable), .select(select[3:0]), .out(enable[15:0]));\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:42: Cannot find file containing module: 'PointInfor'\n PointInfor point0(.d(point_in[1:0]), .clock(clock), .reset(reset), .write_enable(enable[0]), .q(data_out[1:0]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:44: Cannot find file containing module: 'PointInfor'\n PointInfor point1(.d(point_in[3:2]), .clock(clock), .reset(reset), .write_enable(enable[1]), .q(data_out[3:2]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:46: Cannot find file containing module: 'PointInfor'\n PointInfor point2(.d(point_in[5:4]), .clock(clock), .reset(reset), .write_enable(enable[2]), .q(data_out[5:4]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:48: Cannot find file containing module: 'PointInfor'\n PointInfor point3(.d(point_in[7:6]), .clock(clock), .reset(reset), .write_enable(enable[3]), .q(data_out[7:6]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:50: Cannot find file containing module: 'PointInfor'\n PointInfor point4(.d(point_in[9:8]), .clock(clock), .reset(reset), .write_enable(enable[4]), .q(data_out[9:8]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:52: Cannot find file containing module: 'PointInfor'\n PointInfor point5(.d(point_in[11:10]), .clock(clock), .reset(reset), .write_enable(enable[5]), .q(data_out[11:10]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:54: Cannot find file containing module: 'PointInfor'\n PointInfor point6(.d(point_in[13:12]), .clock(clock), .reset(reset), .write_enable(enable[6]), .q(data_out[13:12]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:56: Cannot find file containing module: 'PointInfor'\n PointInfor point7(.d(point_in[15:14]), .clock(clock), .reset(reset), .write_enable(enable[7]), .q(data_out[15:14]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:58: Cannot find file containing module: 'PointInfor'\n PointInfor point8(.d(point_in[17:16]), .clock(clock), .reset(reset), .write_enable(enable[8]), .q(data_out[17:16]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:60: Cannot find file containing module: 'PointInfor'\n PointInfor point9(.d(point_in[19:18]), .clock(clock), .reset(reset), .write_enable(enable[9]), .q(data_out[19:18]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:62: Cannot find file containing module: 'PointInfor'\n PointInfor point10(.d(point_in[21:20]), .clock(clock), .reset(reset), .write_enable(enable[10]), .q(data_out[21:20]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:64: Cannot find file containing module: 'PointInfor'\n PointInfor point11(.d(point_in[23:22]), .clock(clock), .reset(reset), .write_enable(enable[11]), .q(data_out[23:22]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:66: Cannot find file containing module: 'PointInfor'\n PointInfor point12(.d(point_in[25:24]), .clock(clock), .reset(reset), .write_enable(enable[12]), .q(data_out[25:24]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:68: Cannot find file containing module: 'PointInfor'\n PointInfor point13(.d(point_in[27:26]), .clock(clock), .reset(reset), .write_enable(enable[13]), .q(data_out[27:26]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:70: Cannot find file containing module: 'PointInfor'\n PointInfor point14(.d(point_in[29:28]), .clock(clock), .reset(reset), .write_enable(enable[14]), .q(data_out[29:28]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/memory/Y_Coordinate_Select_Write.v:72: Cannot find file containing module: 'PointInfor'\n PointInfor point15(.d(point_in[31:30]), .clock(clock), .reset(reset), .write_enable(enable[15]), .q(data_out[31:30]));\n ^~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n" | 2,638 | module | module Y_Coordinate_Select_Write(in, select, out, clock, reset, write_enable);
input [1:0] in;
input [3:0] select;
input clock, reset;
input write_enable;
output [31:0] out;
wire [31:0] data_out;
wire [31:0] point_in;
wire [15:0] enable;
Select1to16 transDataToPoint(.in(in[1:0]), .select(select[3:0]), .out(point_in[31:0]));
Enable_select enableEachPoint(.enable(write_enable), .select(select[3:0]), .out(enable[15:0]));
PointInfor point0(.d(point_in[1:0]), .clock(clock), .reset(reset), .write_enable(enable[0]), .q(data_out[1:0]));
PointInfor point1(.d(point_in[3:2]), .clock(clock), .reset(reset), .write_enable(enable[1]), .q(data_out[3:2]));
PointInfor point2(.d(point_in[5:4]), .clock(clock), .reset(reset), .write_enable(enable[2]), .q(data_out[5:4]));
PointInfor point3(.d(point_in[7:6]), .clock(clock), .reset(reset), .write_enable(enable[3]), .q(data_out[7:6]));
PointInfor point4(.d(point_in[9:8]), .clock(clock), .reset(reset), .write_enable(enable[4]), .q(data_out[9:8]));
PointInfor point5(.d(point_in[11:10]), .clock(clock), .reset(reset), .write_enable(enable[5]), .q(data_out[11:10]));
PointInfor point6(.d(point_in[13:12]), .clock(clock), .reset(reset), .write_enable(enable[6]), .q(data_out[13:12]));
PointInfor point7(.d(point_in[15:14]), .clock(clock), .reset(reset), .write_enable(enable[7]), .q(data_out[15:14]));
PointInfor point8(.d(point_in[17:16]), .clock(clock), .reset(reset), .write_enable(enable[8]), .q(data_out[17:16]));
PointInfor point9(.d(point_in[19:18]), .clock(clock), .reset(reset), .write_enable(enable[9]), .q(data_out[19:18]));
PointInfor point10(.d(point_in[21:20]), .clock(clock), .reset(reset), .write_enable(enable[10]), .q(data_out[21:20]));
PointInfor point11(.d(point_in[23:22]), .clock(clock), .reset(reset), .write_enable(enable[11]), .q(data_out[23:22]));
PointInfor point12(.d(point_in[25:24]), .clock(clock), .reset(reset), .write_enable(enable[12]), .q(data_out[25:24]));
PointInfor point13(.d(point_in[27:26]), .clock(clock), .reset(reset), .write_enable(enable[13]), .q(data_out[27:26]));
PointInfor point14(.d(point_in[29:28]), .clock(clock), .reset(reset), .write_enable(enable[14]), .q(data_out[29:28]));
PointInfor point15(.d(point_in[31:30]), .clock(clock), .reset(reset), .write_enable(enable[15]), .q(data_out[31:30]));
assign out[31:0] = data_out[31:0];
endmodule | module Y_Coordinate_Select_Write(in, select, out, clock, reset, write_enable); |
input [1:0] in;
input [3:0] select;
input clock, reset;
input write_enable;
output [31:0] out;
wire [31:0] data_out;
wire [31:0] point_in;
wire [15:0] enable;
Select1to16 transDataToPoint(.in(in[1:0]), .select(select[3:0]), .out(point_in[31:0]));
Enable_select enableEachPoint(.enable(write_enable), .select(select[3:0]), .out(enable[15:0]));
PointInfor point0(.d(point_in[1:0]), .clock(clock), .reset(reset), .write_enable(enable[0]), .q(data_out[1:0]));
PointInfor point1(.d(point_in[3:2]), .clock(clock), .reset(reset), .write_enable(enable[1]), .q(data_out[3:2]));
PointInfor point2(.d(point_in[5:4]), .clock(clock), .reset(reset), .write_enable(enable[2]), .q(data_out[5:4]));
PointInfor point3(.d(point_in[7:6]), .clock(clock), .reset(reset), .write_enable(enable[3]), .q(data_out[7:6]));
PointInfor point4(.d(point_in[9:8]), .clock(clock), .reset(reset), .write_enable(enable[4]), .q(data_out[9:8]));
PointInfor point5(.d(point_in[11:10]), .clock(clock), .reset(reset), .write_enable(enable[5]), .q(data_out[11:10]));
PointInfor point6(.d(point_in[13:12]), .clock(clock), .reset(reset), .write_enable(enable[6]), .q(data_out[13:12]));
PointInfor point7(.d(point_in[15:14]), .clock(clock), .reset(reset), .write_enable(enable[7]), .q(data_out[15:14]));
PointInfor point8(.d(point_in[17:16]), .clock(clock), .reset(reset), .write_enable(enable[8]), .q(data_out[17:16]));
PointInfor point9(.d(point_in[19:18]), .clock(clock), .reset(reset), .write_enable(enable[9]), .q(data_out[19:18]));
PointInfor point10(.d(point_in[21:20]), .clock(clock), .reset(reset), .write_enable(enable[10]), .q(data_out[21:20]));
PointInfor point11(.d(point_in[23:22]), .clock(clock), .reset(reset), .write_enable(enable[11]), .q(data_out[23:22]));
PointInfor point12(.d(point_in[25:24]), .clock(clock), .reset(reset), .write_enable(enable[12]), .q(data_out[25:24]));
PointInfor point13(.d(point_in[27:26]), .clock(clock), .reset(reset), .write_enable(enable[13]), .q(data_out[27:26]));
PointInfor point14(.d(point_in[29:28]), .clock(clock), .reset(reset), .write_enable(enable[14]), .q(data_out[29:28]));
PointInfor point15(.d(point_in[31:30]), .clock(clock), .reset(reset), .write_enable(enable[15]), .q(data_out[31:30]));
assign out[31:0] = data_out[31:0];
endmodule | 0 |
4,394 | data/full_repos/permissive/109608368/VGA_Package/llabs.v | 109,608,368 | llabs.v | v | 97 | 79 | [] | [] | [] | null | line:154: before: "." | null | 1: b'%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109608368/VGA_Package,data/full_repos/permissive/109608368/header.v\n data/full_repos/permissive/109608368/VGA_Package,data/full_repos/permissive/109608368/header.v.v\n data/full_repos/permissive/109608368/VGA_Package,data/full_repos/permissive/109608368/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:27: Define or directive not defined: \'`BOARD_SIZE_BITS\'\n input [`BOARD_SIZE_BITS - 1 : 0] board;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:28: Define or directive not defined: \'`WINNING_STATUS_BITS\'\n input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:29: Define or directive not defined: \'`BOARD_WIDTH_BITS\'\n input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:30: Define or directive not defined: \'`BOARD_HEIGHT_BITS\'\n input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:43: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n wire [`SCR_WIDTH_BITS - 1 : 0] x_co;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:44: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n wire [`SCR_HEIGHT_BITS - 1 : 0] y_co;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109608368/VGA_Package/llabs.v:45: Define or directive not defined: \'`COLOR_SIZE\'\n wire [`COLOR_SIZE - 1 : 0] color_output;\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 2,640 | module | module llabs(
Clck,
board,
gaming_status,
pointer_loc_x,
pointer_loc_y,
Reset,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input Clck, Reset;
input [`BOARD_SIZE_BITS - 1 : 0] board;
input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;
input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire [`SCR_WIDTH_BITS - 1 : 0] x_co;
wire [`SCR_HEIGHT_BITS - 1 : 0] y_co;
wire [`COLOR_SIZE - 1 : 0] color_output;
wire print_enable;
painter pt(
.board(board),
.winning_information(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_y),
.Clck(Clck),
.Reset(Reset),
.paint_x_co_all_dimension(x_co),
.paint_y_co_all_dimension(y_co),
.color_all_dimension_output(color_output),
.print_enable_all_dimension(print_enable)
);
vga_adapter VGA(
.resetn(Reset),
.clock(Clck),
.colour(color_output),
.x(x_co),
.y(y_co),
.plot(print_enable),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
endmodule | module llabs(
Clck,
board,
gaming_status,
pointer_loc_x,
pointer_loc_y,
Reset,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input Clck, Reset;
input [`BOARD_SIZE_BITS - 1 : 0] board;
input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;
input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire [`SCR_WIDTH_BITS - 1 : 0] x_co;
wire [`SCR_HEIGHT_BITS - 1 : 0] y_co;
wire [`COLOR_SIZE - 1 : 0] color_output;
wire print_enable;
painter pt(
.board(board),
.winning_information(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_y),
.Clck(Clck),
.Reset(Reset),
.paint_x_co_all_dimension(x_co),
.paint_y_co_all_dimension(y_co),
.color_all_dimension_output(color_output),
.print_enable_all_dimension(print_enable)
);
vga_adapter VGA(
.resetn(Reset),
.clock(Clck),
.colour(color_output),
.x(x_co),
.y(y_co),
.plot(print_enable),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
endmodule | 0 |
4,395 | data/full_repos/permissive/109846502/bcd2bin.v | 109,846,502 | bcd2bin.v | v | 29 | 83 | [] | [] | [] | [(21, 28)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/109846502/bcd2bin.v:26: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s VARREF \'N4\' generates 4 bits.\n : ... In instance bcd2bin\nassign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,646 | module | module bcd2bin(
input [3:0] N1, N2, N3, N4,
output [13:0] out
);
assign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;
endmodule | module bcd2bin(
input [3:0] N1, N2, N3, N4,
output [13:0] out
); |
assign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;
endmodule | 0 |
4,396 | data/full_repos/permissive/109846502/bcd2binTest.v | 109,846,502 | bcd2binTest.v | v | 83 | 81 | [] | [] | [] | [(25, 81)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/bcd2binTest.v:37: Cannot find file containing module: \'bcd2bin\'\n bcd2bin uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin.sv\n bcd2bin\n bcd2bin.v\n bcd2bin.sv\n obj_dir/bcd2bin\n obj_dir/bcd2bin.v\n obj_dir/bcd2bin.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,647 | module | module bcd2binTest;
reg [3:0] N1;
reg [3:0] N2;
reg [3:0] N3;
reg [3:0] N4;
wire [13:0] out;
bcd2bin uut (
.N1(N1),
.N2(N2),
.N3(N3),
.N4(N4),
.out(out)
);
initial begin
N1 = 4'd0;
N2 = 4'd0;
N3 = 4'd1;
N4 = 4'd2;
#10;
N1 = 4'd5;
N2 = 4'd4;
N3 = 4'd3;
N4 = 4'd2;
#10;
N1 = 4'd9;
N2 = 4'd9;
N3 = 4'd9;
N4 = 4'd9;
#10;
N1 = 4'd3;
N2 = 4'd5;
N3 = 4'd7;
N4 = 4'd9;
#10;
N1 = 4'd1;
N2 = 4'd0;
N3 = 4'd4;
N4 = 4'd0;
end
endmodule | module bcd2binTest; |
reg [3:0] N1;
reg [3:0] N2;
reg [3:0] N3;
reg [3:0] N4;
wire [13:0] out;
bcd2bin uut (
.N1(N1),
.N2(N2),
.N3(N3),
.N4(N4),
.out(out)
);
initial begin
N1 = 4'd0;
N2 = 4'd0;
N3 = 4'd1;
N4 = 4'd2;
#10;
N1 = 4'd5;
N2 = 4'd4;
N3 = 4'd3;
N4 = 4'd2;
#10;
N1 = 4'd9;
N2 = 4'd9;
N3 = 4'd9;
N4 = 4'd9;
#10;
N1 = 4'd3;
N2 = 4'd5;
N3 = 4'd7;
N4 = 4'd9;
#10;
N1 = 4'd1;
N2 = 4'd0;
N3 = 4'd4;
N4 = 4'd0;
end
endmodule | 0 |
4,397 | data/full_repos/permissive/109846502/bin2bcd.v | 109,846,502 | bin2bcd.v | v | 59 | 83 | [] | [] | [] | [(21, 58)] | null | data/verilator_xmls/3c386508-fe4d-42bc-a5b4-b80c6c9dd8fe.xml | null | 2,648 | module | module bin2bcd(
input [13:0] bin,
output reg [3:0] thousands, hundreds, tens, ones
);
integer i;
always @* begin
thousands = 4'd0;
hundreds = 4'd0;
tens = 4'd0;
ones = 4'd0;
for(i = 13; i >= 0; i = i-1) begin
if(thousands >= 5)
thousands = thousands + 3;
if(hundreds >= 5)
hundreds = hundreds + 3;
if(tens >= 5)
tens = tens + 3;
if(ones >= 5)
ones = ones + 3;
thousands = thousands << 1;
thousands[0] = hundreds[3];
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = bin[i];
end
end
endmodule | module bin2bcd(
input [13:0] bin,
output reg [3:0] thousands, hundreds, tens, ones
); |
integer i;
always @* begin
thousands = 4'd0;
hundreds = 4'd0;
tens = 4'd0;
ones = 4'd0;
for(i = 13; i >= 0; i = i-1) begin
if(thousands >= 5)
thousands = thousands + 3;
if(hundreds >= 5)
hundreds = hundreds + 3;
if(tens >= 5)
tens = tens + 3;
if(ones >= 5)
ones = ones + 3;
thousands = thousands << 1;
thousands[0] = hundreds[3];
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = bin[i];
end
end
endmodule | 0 |
4,398 | data/full_repos/permissive/109846502/bin2bcd_test.v | 109,846,502 | bin2bcd_test.v | v | 60 | 81 | [] | [] | [] | [(25, 58)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/bin2bcd_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bin2bcd_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/109846502/bin2bcd_test.v:37: Cannot find file containing module: \'bin2bcd\'\n bin2bcd uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bin2bcd\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bin2bcd.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bin2bcd.sv\n bin2bcd\n bin2bcd.v\n bin2bcd.sv\n obj_dir/bin2bcd\n obj_dir/bin2bcd.v\n obj_dir/bin2bcd.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,649 | module | module bin2bcd_test;
reg [13:0] bin;
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
bin2bcd uut (
.bin(bin),
.thousands(thousands),
.hundreds(hundreds),
.tens(tens),
.ones(ones)
);
initial begin
bin = 14'd0;
#100;
bin = 14'd9999;
#20
bin = 14'd10;
end
endmodule | module bin2bcd_test; |
reg [13:0] bin;
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
bin2bcd uut (
.bin(bin),
.thousands(thousands),
.hundreds(hundreds),
.tens(tens),
.ones(ones)
);
initial begin
bin = 14'd0;
#100;
bin = 14'd9999;
#20
bin = 14'd10;
end
endmodule | 0 |
4,399 | data/full_repos/permissive/109846502/Calkko.v | 109,846,502 | Calkko.v | v | 75 | 83 | [] | [] | [] | [(67, 119)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/Calkko.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/Calkko.v:34: Define or directive not defined: \'`S_OBL\'\nassign set = ST == `S_OBL;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign set = ST == `S_OBL;\n ^\n%Error: data/full_repos/permissive/109846502/Calkko.v:48: Define or directive not defined: \'`SL_ADD\'\n `SL_ADD:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:48: syntax error, unexpected \':\', expecting endcase\n `SL_ADD:\n ^\n%Error: data/full_repos/permissive/109846502/Calkko.v:50: Define or directive not defined: \'`SL_SUB\'\n `SL_SUB:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:52: Define or directive not defined: \'`SL_XOR\'\n `SL_XOR:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:54: Define or directive not defined: \'`SL_AND\'\n `SL_AND: \n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:56: Define or directive not defined: \'`SL_OR\'\n `SL_OR: binaryResult <= binaryA | binaryB;\n ^~~~~~\n%Error: Exiting due to 9 error(s)\n' | 2,650 | module | module Calkko(
input [3:0] A1,A2,A3,A4,
input [3:0] B1,B2,B3,B4,
input [1:0] ST,
input [2:0] ST_L,
output set,
output reg [15:0] number
);
wire [13:0] binaryA, binaryB;
reg [13:0] binaryResult;
assign set = ST == `S_OBL;
wire [3:0] BCD1, BCD2, BCD3, BCD4;
bcd2bin bikko( .N1(A1), .N2(A2), .N3(A3), .N4(A4), .out(binaryA));
bcd2bin akko( .N1(B1), .N2(B2), .N3(B3), .N4(B4), .out(binaryB));
bin2bcd resultto (.bin(binaryResult),
.thousands(BCD1), .hundreds(BCD2), .tens(BCD3), .ones(BCD4));
always @* begin
if(set) begin
case(ST_L)
`SL_ADD:
binaryResult <= binaryA + binaryB;
`SL_SUB:
binaryResult <= binaryA - binaryB;
`SL_XOR:
binaryResult <= binaryA ^ binaryB;
`SL_AND:
binaryResult <= binaryA & binaryB;
`SL_OR: binaryResult <= binaryA | binaryB;
default:
binaryResult <= 14'd0;
endcase
number[15:12] <= BCD4;
number[11:8] <= BCD3;
number [7:4] <= BCD2;
number[3:0] <= BCD1;
end
else
begin
number <= 16'd0;
binaryResult <= 14'd0;
end
end
endmodule | module Calkko(
input [3:0] A1,A2,A3,A4,
input [3:0] B1,B2,B3,B4,
input [1:0] ST,
input [2:0] ST_L,
output set,
output reg [15:0] number
); |
wire [13:0] binaryA, binaryB;
reg [13:0] binaryResult;
assign set = ST == `S_OBL;
wire [3:0] BCD1, BCD2, BCD3, BCD4;
bcd2bin bikko( .N1(A1), .N2(A2), .N3(A3), .N4(A4), .out(binaryA));
bcd2bin akko( .N1(B1), .N2(B2), .N3(B3), .N4(B4), .out(binaryB));
bin2bcd resultto (.bin(binaryResult),
.thousands(BCD1), .hundreds(BCD2), .tens(BCD3), .ones(BCD4));
always @* begin
if(set) begin
case(ST_L)
`SL_ADD:
binaryResult <= binaryA + binaryB;
`SL_SUB:
binaryResult <= binaryA - binaryB;
`SL_XOR:
binaryResult <= binaryA ^ binaryB;
`SL_AND:
binaryResult <= binaryA & binaryB;
`SL_OR: binaryResult <= binaryA | binaryB;
default:
binaryResult <= 14'd0;
endcase
number[15:12] <= BCD4;
number[11:8] <= BCD3;
number [7:4] <= BCD2;
number[3:0] <= BCD1;
end
else
begin
number <= 16'd0;
binaryResult <= 14'd0;
end
end
endmodule | 0 |
4,400 | data/full_repos/permissive/109846502/calkkoTest.v | 109,846,502 | calkkoTest.v | v | 99 | 81 | [] | [] | [] | [(70, 142)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/calkkoTest.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:62: Define or directive not defined: \'`S_OBL\'\n ST = `S_OBL;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST = `S_OBL;\n ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:75: Define or directive not defined: \'`SL_ADD\'\n ST_L = `SL_ADD;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_ADD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:76: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:77: Define or directive not defined: \'`SL_SUB\'\n ST_L = `SL_SUB;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_SUB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:79: Define or directive not defined: \'`SL_XOR\'\n ST_L = `SL_XOR;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_XOR;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:81: Define or directive not defined: \'`SL_OR\'\n ST_L = `SL_OR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_OR;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:82: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:83: Define or directive not defined: \'`SL_AND\'\n ST_L = `SL_AND;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_AND;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:89: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 13 error(s), 5 warning(s)\n' | 2,651 | module | module calkkoTest;
reg [3:0] A1;
reg [3:0] A2;
reg [3:0] A3;
reg [3:0] A4;
reg [3:0] B1;
reg [3:0] B2;
reg [3:0] B3;
reg [3:0] B4;
reg [1:0] ST;
reg [2:0] ST_L;
reg [3:0] OUT1, OUT2, OUT3, OUT4;
wire set;
wire [15:0] number;
Calkko uut (
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.ST(ST),
.ST_L(ST_L),
.set(set),
.number(number)
);
initial begin
ST = `S_OBL;
A1 = 4'd0;
A2 = 4'd0;
A3 = 4'd0;
A4 = 4'd5;
B1 = 4'd0;
B2 = 4'd0;
B3 = 4'd0;
B4 = 4'd1;
ST_L = `SL_ADD;
#10;
ST_L = `SL_SUB;
#10;
ST_L = `SL_XOR;
#10;
ST_L = `SL_OR;
#10;
ST_L = `SL_AND;
end
initial begin
forever begin
#1;
OUT1 <= number[3:0];
OUT2 <= number[7:4];
OUT3 <= number[11:8];
OUT4 <= number[15:12];
end
end
endmodule | module calkkoTest; |
reg [3:0] A1;
reg [3:0] A2;
reg [3:0] A3;
reg [3:0] A4;
reg [3:0] B1;
reg [3:0] B2;
reg [3:0] B3;
reg [3:0] B4;
reg [1:0] ST;
reg [2:0] ST_L;
reg [3:0] OUT1, OUT2, OUT3, OUT4;
wire set;
wire [15:0] number;
Calkko uut (
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.ST(ST),
.ST_L(ST_L),
.set(set),
.number(number)
);
initial begin
ST = `S_OBL;
A1 = 4'd0;
A2 = 4'd0;
A3 = 4'd0;
A4 = 4'd5;
B1 = 4'd0;
B2 = 4'd0;
B3 = 4'd0;
B4 = 4'd1;
ST_L = `SL_ADD;
#10;
ST_L = `SL_SUB;
#10;
ST_L = `SL_XOR;
#10;
ST_L = `SL_OR;
#10;
ST_L = `SL_AND;
end
initial begin
forever begin
#1;
OUT1 <= number[3:0];
OUT2 <= number[7:4];
OUT3 <= number[11:8];
OUT4 <= number[15:12];
end
end
endmodule | 0 |
4,401 | data/full_repos/permissive/109846502/clockDivider.v | 109,846,502 | clockDivider.v | v | 62 | 83 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/109846502/clockDivider.v:32: Signal definition not found, creating implicitly: \'comp\'\nassign comp = (cnt == (div - 1));\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,652 | module | module clockDivider
#(parameter div = 25000000)
(
input clk,
input rst,
output reg slow_clk
);
localparam nbits = clog2b(div);
reg [nbits-1:0] cnt;
assign comp = (cnt == (div - 1));
always @(posedge clk, posedge rst) begin
if(rst)
cnt <= {nbits{1'b0}};
else if(comp)
cnt <= {nbits{1'b0}};
else
cnt <= cnt + 1;
end
always @(posedge clk, posedge rst) begin
if(rst) slow_clk <= 1'b0;
else if(comp)
slow_clk <= 1'b1;
else
slow_clk <= 1'b0;
end
function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction
endmodule | module clockDivider
#(parameter div = 25000000)
(
input clk,
input rst,
output reg slow_clk
); |
localparam nbits = clog2b(div);
reg [nbits-1:0] cnt;
assign comp = (cnt == (div - 1));
always @(posedge clk, posedge rst) begin
if(rst)
cnt <= {nbits{1'b0}};
else if(comp)
cnt <= {nbits{1'b0}};
else
cnt <= cnt + 1;
end
always @(posedge clk, posedge rst) begin
if(rst) slow_clk <= 1'b0;
else if(comp)
slow_clk <= 1'b1;
else
slow_clk <= 1'b0;
end
function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction
endmodule | 0 |
4,402 | data/full_repos/permissive/109846502/clockDivider.v | 109,846,502 | clockDivider.v | v | 62 | 83 | [] | [] | [] | null | Syntax Error | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/109846502/clockDivider.v:32: Signal definition not found, creating implicitly: \'comp\'\nassign comp = (cnt == (div - 1));\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,652 | function | function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction | function integer clog2b; |
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction | 0 |
4,403 | data/full_repos/permissive/109846502/ctndek.v | 109,846,502 | ctndek.v | v | 52 | 83 | [] | [] | [] | [(21, 51)] | null | data/verilator_xmls/b3b9bfcd-560f-4394-bc68-4146c2bc31e9.xml | null | 2,653 | module | module ctndek(
input clk,
input rst,
input en,
output reg ovl,
output reg [3:0] out
);
always @(posedge clk, posedge rst)
begin
if(rst)
out <= 4'd0;
else if(en)
if(out == 4'd9)
out <= 4'd0;
else
out <= out + 1;
end
always @(posedge clk, posedge rst)
begin
if(rst)
ovl <= 1'b0;
else
if (out == 4'd9)
ovl <= 1'b1;
else
ovl <= 1'b0;
end
endmodule | module ctndek(
input clk,
input rst,
input en,
output reg ovl,
output reg [3:0] out
); |
always @(posedge clk, posedge rst)
begin
if(rst)
out <= 4'd0;
else if(en)
if(out == 4'd9)
out <= 4'd0;
else
out <= out + 1;
end
always @(posedge clk, posedge rst)
begin
if(rst)
ovl <= 1'b0;
else
if (out == 4'd9)
ovl <= 1'b1;
else
ovl <= 1'b0;
end
endmodule | 0 |
4,404 | data/full_repos/permissive/109846502/Decoder.v | 109,846,502 | Decoder.v | v | 110 | 107 | [] | [] | [] | [(71, 154)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/Decoder.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/Decoder.v:52: Define or directive not defined: \'`KEY_NONE\'\n CurrentKey <= `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n CurrentKey <= `KEY_NONE;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:67: Define or directive not defined: \'`KEY_NONE\'\n CurrentKey <= `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n CurrentKey <= `KEY_NONE;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:76: Define or directive not defined: \'`KEY_1\'\n 4\'b0111: CurrentKey <= `KEY_1;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b0111: CurrentKey <= `KEY_1;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:77: Define or directive not defined: \'`KEY_4\'\n 4\'b1011: CurrentKey <= `KEY_4;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1011: CurrentKey <= `KEY_4;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:78: Define or directive not defined: \'`KEY_7\'\n 4\'b1101: CurrentKey <= `KEY_7;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1101: CurrentKey <= `KEY_7;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:79: Define or directive not defined: \'`KEY_0\'\n 4\'b1110: CurrentKey <= `KEY_0;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1110: CurrentKey <= `KEY_0;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:83: Define or directive not defined: \'`KEY_2\'\n 4\'b0111: CurrentKey <= `KEY_2;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b0111: CurrentKey <= `KEY_2;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:84: Define or directive not defined: \'`KEY_5\'\n 4\'b1011: CurrentKey <= `KEY_5;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1011: CurrentKey <= `KEY_5;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:85: Define or directive not defined: \'`KEY_8\'\n 4\'b1101: CurrentKey <= `KEY_8;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1101: CurrentKey <= `KEY_8;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:86: Define or directive not defined: \'`KEY_F\'\n 4\'b1110: CurrentKey <= `KEY_F;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1110: CurrentKey <= `KEY_F;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:90: Define or directive not defined: \'`KEY_3\'\n 4\'b0111: CurrentKey <= `KEY_3;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b0111: CurrentKey <= `KEY_3;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:91: Define or directive not defined: \'`KEY_6\'\n 4\'b1011: CurrentKey <= `KEY_6;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1011: CurrentKey <= `KEY_6;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:92: Define or directive not defined: \'`KEY_9\'\n 4\'b1101: CurrentKey <= `KEY_9;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1101: CurrentKey <= `KEY_9;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:93: Define or directive not defined: \'`KEY_E\'\n 4\'b1110: CurrentKey <= `KEY_E;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1110: CurrentKey <= `KEY_E;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:97: Define or directive not defined: \'`KEY_A\'\n 4\'b0111: CurrentKey <= `KEY_A;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b0111: CurrentKey <= `KEY_A;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:98: Define or directive not defined: \'`KEY_B\'\n 4\'b1011: CurrentKey <= `KEY_B;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1011: CurrentKey <= `KEY_B;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:99: Define or directive not defined: \'`KEY_C\'\n 4\'b1101: CurrentKey <= `KEY_C;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1101: CurrentKey <= `KEY_C;\n ^\n%Error: data/full_repos/permissive/109846502/Decoder.v:100: Define or directive not defined: \'`KEY_D\'\n 4\'b1110: CurrentKey <= `KEY_D;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Decoder.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n 4\'b1110: CurrentKey <= `KEY_D;\n ^\n%Error: Exiting due to 37 error(s)\n' | 2,654 | module | module Decoder(
input clk,
input rst,
input [3:0] row,
output reg [3:0] Col,
output reg [4:0] DecodeOut
);
reg [2:0] Column;
reg [2:0] nextColumn;
reg state;
reg [4:0] CurrentKey;
always @(posedge clk, posedge rst) begin
if(rst)
begin
Column <= 3'd0;
nextColumn <= 3'd0;
state <= 1'b1;
CurrentKey <= `KEY_NONE;
end
else
begin
if(state) begin
Column <= nextColumn;
case(nextColumn)
3'd0: Col <= 4'b0111;
3'd1: Col <= 4'b1011;
3'd2: Col <= 4'b1101;
3'd3: Col <= 4'b1110;
3'd4:
begin
DecodeOut <= CurrentKey;
CurrentKey <= `KEY_NONE;
Column <= 3'd0;
end
endcase
end
else begin
case (Column)
3'd0:
case(row)
4'b0111: CurrentKey <= `KEY_1;
4'b1011: CurrentKey <= `KEY_4;
4'b1101: CurrentKey <= `KEY_7;
4'b1110: CurrentKey <= `KEY_0;
endcase
3'd1:
case(row)
4'b0111: CurrentKey <= `KEY_2;
4'b1011: CurrentKey <= `KEY_5;
4'b1101: CurrentKey <= `KEY_8;
4'b1110: CurrentKey <= `KEY_F;
endcase
3'd2:
case(row)
4'b0111: CurrentKey <= `KEY_3;
4'b1011: CurrentKey <= `KEY_6;
4'b1101: CurrentKey <= `KEY_9;
4'b1110: CurrentKey <= `KEY_E;
endcase
3'd3:
case(row)
4'b0111: CurrentKey <= `KEY_A;
4'b1011: CurrentKey <= `KEY_B;
4'b1101: CurrentKey <= `KEY_C;
4'b1110: CurrentKey <= `KEY_D;
endcase
endcase
nextColumn <= nextColumn + 1;
end
state <= ~state;
end
end
endmodule | module Decoder(
input clk,
input rst,
input [3:0] row,
output reg [3:0] Col,
output reg [4:0] DecodeOut
); |
reg [2:0] Column;
reg [2:0] nextColumn;
reg state;
reg [4:0] CurrentKey;
always @(posedge clk, posedge rst) begin
if(rst)
begin
Column <= 3'd0;
nextColumn <= 3'd0;
state <= 1'b1;
CurrentKey <= `KEY_NONE;
end
else
begin
if(state) begin
Column <= nextColumn;
case(nextColumn)
3'd0: Col <= 4'b0111;
3'd1: Col <= 4'b1011;
3'd2: Col <= 4'b1101;
3'd3: Col <= 4'b1110;
3'd4:
begin
DecodeOut <= CurrentKey;
CurrentKey <= `KEY_NONE;
Column <= 3'd0;
end
endcase
end
else begin
case (Column)
3'd0:
case(row)
4'b0111: CurrentKey <= `KEY_1;
4'b1011: CurrentKey <= `KEY_4;
4'b1101: CurrentKey <= `KEY_7;
4'b1110: CurrentKey <= `KEY_0;
endcase
3'd1:
case(row)
4'b0111: CurrentKey <= `KEY_2;
4'b1011: CurrentKey <= `KEY_5;
4'b1101: CurrentKey <= `KEY_8;
4'b1110: CurrentKey <= `KEY_F;
endcase
3'd2:
case(row)
4'b0111: CurrentKey <= `KEY_3;
4'b1011: CurrentKey <= `KEY_6;
4'b1101: CurrentKey <= `KEY_9;
4'b1110: CurrentKey <= `KEY_E;
endcase
3'd3:
case(row)
4'b0111: CurrentKey <= `KEY_A;
4'b1011: CurrentKey <= `KEY_B;
4'b1101: CurrentKey <= `KEY_C;
4'b1110: CurrentKey <= `KEY_D;
endcase
endcase
nextColumn <= nextColumn + 1;
end
state <= ~state;
end
end
endmodule | 0 |
4,405 | data/full_repos/permissive/109846502/enabler.v | 109,846,502 | enabler.v | v | 32 | 83 | [] | [] | [] | [(67, 76)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/enabler.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/enabler.v:28: Define or directive not defined: \'`S_WPR\'\nassign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/enabler.v:28: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nassign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);\n ^~\n%Error: data/full_repos/permissive/109846502/enabler.v:28: Define or directive not defined: \'`SL_A\'\nassign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);\n ^~~~~\n%Error: data/full_repos/permissive/109846502/enabler.v:28: Define or directive not defined: \'`SL_B\'\nassign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);\n ^~~~~\n%Error: Exiting due to 5 error(s)\n' | 2,656 | module | module enabler(
input [1:0] ST,
input [2:0] ST_L,
output en
);
assign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);
endmodule | module enabler(
input [1:0] ST,
input [2:0] ST_L,
output en
); |
assign en = ST == `S_WPR && (ST_L == `SL_A || ST_L == `SL_B);
endmodule | 0 |
4,406 | data/full_repos/permissive/109846502/KeyLedDisplay.v | 109,846,502 | KeyLedDisplay.v | v | 39 | 83 | [] | [] | [] | [(67, 83)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/KeyLedDisplay.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/KeyLedDisplay.v:29: Define or directive not defined: \'`S_WPR\'\n if(ST == `S_WPR)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/KeyLedDisplay.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(ST == `S_WPR)\n ^\n%Error: data/full_repos/permissive/109846502/KeyLedDisplay.v:31: Define or directive not defined: \'`SL_A\'\n if(ST_L == `SL_A)\n ^~~~~\n%Error: Exiting due to 4 error(s)\n' | 2,657 | module | module KeyLedDisplay(
input [1:0] ST,
input [2:0] ST_L,
output reg [6:0] segOut
);
always @*
if(ST == `S_WPR)
begin
if(ST_L == `SL_A)
segOut <= 7'd1;
else
segOut <= 7'd3;
end
else
segOut <= 7'd0;
endmodule | module KeyLedDisplay(
input [1:0] ST,
input [2:0] ST_L,
output reg [6:0] segOut
); |
always @*
if(ST == `S_WPR)
begin
if(ST_L == `SL_A)
segOut <= 7'd1;
else
segOut <= 7'd3;
end
else
segOut <= 7'd0;
endmodule | 0 |
4,407 | data/full_repos/permissive/109846502/kikko.v | 109,846,502 | kikko.v | v | 103 | 82 | [] | [] | [] | [(21, 102)] | null | null | 1: b"%Error: data/full_repos/permissive/109846502/kikko.v:41: Cannot find file containing module: 'clockDivider'\n clockDivider #(.div(div)) clokko(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/clockDivider\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/clockDivider.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/clockDivider.sv\n clockDivider\n clockDivider.v\n clockDivider.sv\n obj_dir/clockDivider\n obj_dir/clockDivider.v\n obj_dir/clockDivider.sv\n%Error: data/full_repos/permissive/109846502/kikko.v:47: Cannot find file containing module: 'Decoder'\n Decoder C0(\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/kikko.v:55: Cannot find file containing module: 'KeyLedDisplay'\n KeyLedDisplay display(.ST(ST), .ST_L(ST_L),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/kikko.v:60: Cannot find file containing module: 'StateMachine'\n StateMachine stateMachine(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/kikko.v:70: Cannot find file containing module: 'enabler'\n enabler enabled(\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/kikko.v:76: Cannot find file containing module: 'Calkko'\n Calkko Calkko(\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/kikko.v:86: Cannot find file containing module: 'Numerator'\n Numerator Numerator(\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 2,658 | module | module kikko
#(parameter div = 100)
(
input clk,
input rst,
input [3:0] row ,
output [3:0] col ,
output [1:0] ST,
output [2:0] ST_L,
output [3:0] A1,A2,A3,A4,
B1,B2,B3,B4,
output [6:0] leds,
output [1:0] index
);
wire [4:0] key;
wire [15:0] number;
clockDivider #(.div(div)) clokko(
.clk(clk),
.rst(rst),
.slow_clk(slow_clk)
);
Decoder C0(
.clk(slow_clk),
.rst(rst),
.row(row),
.Col(col),
.DecodeOut(key)
);
KeyLedDisplay display(.ST(ST), .ST_L(ST_L),
.segOut(leds));
StateMachine stateMachine(
.key(key),
.clk(slow_clk),
.rst(rst),
.end_obl(1'b1),
.ST(ST),
.index(index),
.ST_L(ST_L)
);
enabler enabled(
.ST(ST),
.ST_L(ST_L),
.en(enableWriting)
);
Calkko Calkko(
.A1(A1), .A2(A2), .A3(A3), .A4(A4),
.B1(B1), .B2(B2), .B3(B3), .B4(B4),
.ST(ST),
.ST_L(ST_L),
.set(set),
.number(number)
);
Numerator Numerator(
.index(index),
.enabled(enableWriting),
.key(key),
.ST_L(ST_L),
.clk(slow_clk),
.rst(rst),
.A1(A1), .A2(A2), .A3(A3), .A4(A4),
.B1(B1), .B2(B2), .B3(B3), .B4(B4),
.set(set),
.setVal(number)
);
endmodule | module kikko
#(parameter div = 100)
(
input clk,
input rst,
input [3:0] row ,
output [3:0] col ,
output [1:0] ST,
output [2:0] ST_L,
output [3:0] A1,A2,A3,A4,
B1,B2,B3,B4,
output [6:0] leds,
output [1:0] index
); |
wire [4:0] key;
wire [15:0] number;
clockDivider #(.div(div)) clokko(
.clk(clk),
.rst(rst),
.slow_clk(slow_clk)
);
Decoder C0(
.clk(slow_clk),
.rst(rst),
.row(row),
.Col(col),
.DecodeOut(key)
);
KeyLedDisplay display(.ST(ST), .ST_L(ST_L),
.segOut(leds));
StateMachine stateMachine(
.key(key),
.clk(slow_clk),
.rst(rst),
.end_obl(1'b1),
.ST(ST),
.index(index),
.ST_L(ST_L)
);
enabler enabled(
.ST(ST),
.ST_L(ST_L),
.en(enableWriting)
);
Calkko Calkko(
.A1(A1), .A2(A2), .A3(A3), .A4(A4),
.B1(B1), .B2(B2), .B3(B3), .B4(B4),
.ST(ST),
.ST_L(ST_L),
.set(set),
.number(number)
);
Numerator Numerator(
.index(index),
.enabled(enableWriting),
.key(key),
.ST_L(ST_L),
.clk(slow_clk),
.rst(rst),
.A1(A1), .A2(A2), .A3(A3), .A4(A4),
.B1(B1), .B2(B2), .B3(B3), .B4(B4),
.set(set),
.setVal(number)
);
endmodule | 0 |
4,408 | data/full_repos/permissive/109846502/kikkoTest.v | 109,846,502 | kikkoTest.v | v | 104 | 81 | [] | [] | [] | null | line:77: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/kikkoTest.v:67: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/kikkoTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n #105;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/kikkoTest.v:77: Unsupported: Ignoring delay on this delayed statement.\n repeat(200) #1 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/kikkoTest.v:85: Unsupported: Ignoring delay on this delayed statement.\n repeat(100) #1 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/kikkoTest.v:93: Unsupported: Ignoring delay on this delayed statement.\n repeat(100) #1 \n ^\n%Error: data/full_repos/permissive/109846502/kikkoTest.v:47: Cannot find file containing module: \'kikko\'\n kikko #(.div(2)) uut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/kikko\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/kikko.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/kikko.sv\n kikko\n kikko.v\n kikko.sv\n obj_dir/kikko\n obj_dir/kikko.v\n obj_dir/kikko.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,659 | module | module kikkoTest;
reg clk;
reg rst;
reg [3:0] row;
wire [1:0] ST;
wire [2:0] ST_L;
wire [3:0] A1;
wire [3:0] A2;
wire [3:0] A3;
wire [3:0] A4;
wire [3:0] B1;
wire [3:0] B2;
wire [3:0] B3;
wire [3:0] B4;
wire [3:0] col;
wire [6:0] leds;
kikko #(.div(2)) uut (
.clk(clk),
.rst(rst),
.row(row),
.col(col),
.ST(ST),
.ST_L(ST_L),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.leds(leds)
);
initial begin
clk = 1'b0;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#105;
rst = 1'b0;
end
initial begin
repeat(200) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1101;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1101;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
end
endmodule | module kikkoTest; |
reg clk;
reg rst;
reg [3:0] row;
wire [1:0] ST;
wire [2:0] ST_L;
wire [3:0] A1;
wire [3:0] A2;
wire [3:0] A3;
wire [3:0] A4;
wire [3:0] B1;
wire [3:0] B2;
wire [3:0] B3;
wire [3:0] B4;
wire [3:0] col;
wire [6:0] leds;
kikko #(.div(2)) uut (
.clk(clk),
.rst(rst),
.row(row),
.col(col),
.ST(ST),
.ST_L(ST_L),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.leds(leds)
);
initial begin
clk = 1'b0;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#105;
rst = 1'b0;
end
initial begin
repeat(200) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1101;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1101;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
end
endmodule | 0 |
4,409 | data/full_repos/permissive/109846502/LCD_dp.v | 109,846,502 | LCD_dp.v | v | 134 | 83 | [] | [] | [] | [(67, 179)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/LCD_dp.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:56: Define or directive not defined: \'`ASCII_BLANK\'\n mux_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mux_out = `ASCII_BLANK;\n ^\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:61: Define or directive not defined: \'`ASCII_BLANK\'\n default: mux_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n default: mux_out = `ASCII_BLANK;\n ^\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:81: Define or directive not defined: \'`SL_ADD\'\n `SL_ADD:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:81: syntax error, unexpected \':\', expecting endcase\n `SL_ADD:\n ^\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:83: Define or directive not defined: \'`ASCII_A\'\n 2\'d2: OP_out = `ASCII_A;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:84: Define or directive not defined: \'`ASCII_D\'\n 2\'d0, 2\'d1: OP_out = `ASCII_D;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:85: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:88: Define or directive not defined: \'`SL_SUB\'\n `SL_SUB:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:90: Define or directive not defined: \'`ASCII_S\'\n 2\'d2: OP_out = `ASCII_S;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:91: Define or directive not defined: \'`ASCII_U\'\n 2\'d1: OP_out = `ASCII_U;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:92: Define or directive not defined: \'`ASCII_B\'\n 2\'d0: OP_out = `ASCII_B;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:93: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:96: Define or directive not defined: \'`SL_AND\'\n `SL_AND:\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:98: Define or directive not defined: \'`ASCII_A\'\n 2\'d2: OP_out = `ASCII_A;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:99: Define or directive not defined: \'`ASCII_N\'\n 2\'d1: OP_out = `ASCII_N;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:100: Define or directive not defined: \'`ASCII_D\'\n 2\'d0: OP_out = `ASCII_D;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:101: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:104: Define or directive not defined: \'`SL_OR\'\n `SL_OR: \n ^~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:106: Define or directive not defined: \'`ASCII_O\'\n 2\'d1: OP_out = `ASCII_O;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:107: Define or directive not defined: \'`ASCII_R\'\n 2\'d0: OP_out = `ASCII_R;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:108: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:111: Define or directive not defined: \'`SL_XOR\'\n `SL_XOR: \n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:113: Define or directive not defined: \'`ASCII_X\'\n 2\'d2: OP_out = `ASCII_X;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:114: Define or directive not defined: \'`ASCII_O\'\n 2\'d1: OP_out = `ASCII_O;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:115: Define or directive not defined: \'`ASCII_R\'\n 2\'d0: OP_out = `ASCII_R;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:116: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109846502/LCD_dp.v:118: Define or directive not defined: \'`ASCII_BLANK\'\n default: OP_out = `ASCII_BLANK;\n ^~~~~~~~~~~~\n%Error: Cannot continue\n' | 2,660 | module | module LCD_dp(
input [1:0] init_sel, input data_sel, DB_sel,
input [1:0] state, input [2:0] statelocal, input [1:0] index,
input [3:0] A1, input [3:0] A2, input [3:0] A3, input [3:0] A4,
input [3:0] B1, input [3:0] B2, input [3:0] B3, input [3:0] B4,
input [1:0] inputIndex, input blink,
output reg [7:0] DB_out
);
localparam [5:0] clear = 6'd1;
localparam [5:0] displayOn = 6'b001110;
localparam [5:0] entryMode = 6'b000110;
localparam [5:0] functionSet = 6'b111000;
reg [5:0] init_out;
reg [7:0] mux_out;
reg [7:0] data_out;
reg [3:0] num_out;
reg [3:0] A_out;
reg [3:0] B_out;
reg [7:0] OP_out;
always @*
case(init_sel)
2'd0: init_out = clear;
2'd1: init_out = displayOn;
2'd2: init_out = entryMode;
2'd3: init_out = functionSet;
endcase
always @*
case(state)
2'd0:
begin
if((2'd3 - index) == inputIndex && blink)
mux_out = `ASCII_BLANK;
else
mux_out = {4'h3, num_out};
end
2'd1: mux_out = OP_out;
default: mux_out = `ASCII_BLANK;
endcase
always @*
case(statelocal)
3'd0: num_out = A_out;
3'd1: num_out = B_out;
default: num_out = A_out;
endcase
always @*
case(index)
2'd0: begin A_out = A4; B_out = B4; end
2'd1: begin A_out = A3; B_out = B3; end
2'd2: begin A_out = A2; B_out = B2; end
2'd3: begin A_out = A1; B_out = B1; end
endcase
always @*
case(statelocal)
`SL_ADD:
case(index)
2'd2: OP_out = `ASCII_A;
2'd0, 2'd1: OP_out = `ASCII_D;
default: OP_out = `ASCII_BLANK;
endcase
`SL_SUB:
case(index)
2'd2: OP_out = `ASCII_S;
2'd1: OP_out = `ASCII_U;
2'd0: OP_out = `ASCII_B;
default: OP_out = `ASCII_BLANK;
endcase
`SL_AND:
case(index)
2'd2: OP_out = `ASCII_A;
2'd1: OP_out = `ASCII_N;
2'd0: OP_out = `ASCII_D;
default: OP_out = `ASCII_BLANK;
endcase
`SL_OR:
case(index)
2'd1: OP_out = `ASCII_O;
2'd0: OP_out = `ASCII_R;
default: OP_out = `ASCII_BLANK;
endcase
`SL_XOR:
case(index)
2'd2: OP_out = `ASCII_X;
2'd1: OP_out = `ASCII_O;
2'd0: OP_out = `ASCII_R;
default: OP_out = `ASCII_BLANK;
endcase
default: OP_out = `ASCII_BLANK;
endcase
always @*
case(data_sel)
1'b0: data_out = init_out;
1'b1: data_out = mux_out;
endcase
always @*
case(DB_sel)
1'b0: DB_out = 8'hcc;
1'b1: DB_out = data_out;
endcase
endmodule | module LCD_dp(
input [1:0] init_sel, input data_sel, DB_sel,
input [1:0] state, input [2:0] statelocal, input [1:0] index,
input [3:0] A1, input [3:0] A2, input [3:0] A3, input [3:0] A4,
input [3:0] B1, input [3:0] B2, input [3:0] B3, input [3:0] B4,
input [1:0] inputIndex, input blink,
output reg [7:0] DB_out
); |
localparam [5:0] clear = 6'd1;
localparam [5:0] displayOn = 6'b001110;
localparam [5:0] entryMode = 6'b000110;
localparam [5:0] functionSet = 6'b111000;
reg [5:0] init_out;
reg [7:0] mux_out;
reg [7:0] data_out;
reg [3:0] num_out;
reg [3:0] A_out;
reg [3:0] B_out;
reg [7:0] OP_out;
always @*
case(init_sel)
2'd0: init_out = clear;
2'd1: init_out = displayOn;
2'd2: init_out = entryMode;
2'd3: init_out = functionSet;
endcase
always @*
case(state)
2'd0:
begin
if((2'd3 - index) == inputIndex && blink)
mux_out = `ASCII_BLANK;
else
mux_out = {4'h3, num_out};
end
2'd1: mux_out = OP_out;
default: mux_out = `ASCII_BLANK;
endcase
always @*
case(statelocal)
3'd0: num_out = A_out;
3'd1: num_out = B_out;
default: num_out = A_out;
endcase
always @*
case(index)
2'd0: begin A_out = A4; B_out = B4; end
2'd1: begin A_out = A3; B_out = B3; end
2'd2: begin A_out = A2; B_out = B2; end
2'd3: begin A_out = A1; B_out = B1; end
endcase
always @*
case(statelocal)
`SL_ADD:
case(index)
2'd2: OP_out = `ASCII_A;
2'd0, 2'd1: OP_out = `ASCII_D;
default: OP_out = `ASCII_BLANK;
endcase
`SL_SUB:
case(index)
2'd2: OP_out = `ASCII_S;
2'd1: OP_out = `ASCII_U;
2'd0: OP_out = `ASCII_B;
default: OP_out = `ASCII_BLANK;
endcase
`SL_AND:
case(index)
2'd2: OP_out = `ASCII_A;
2'd1: OP_out = `ASCII_N;
2'd0: OP_out = `ASCII_D;
default: OP_out = `ASCII_BLANK;
endcase
`SL_OR:
case(index)
2'd1: OP_out = `ASCII_O;
2'd0: OP_out = `ASCII_R;
default: OP_out = `ASCII_BLANK;
endcase
`SL_XOR:
case(index)
2'd2: OP_out = `ASCII_X;
2'd1: OP_out = `ASCII_O;
2'd0: OP_out = `ASCII_R;
default: OP_out = `ASCII_BLANK;
endcase
default: OP_out = `ASCII_BLANK;
endcase
always @*
case(data_sel)
1'b0: data_out = init_out;
1'b1: data_out = mux_out;
endcase
always @*
case(DB_sel)
1'b0: DB_out = 8'hcc;
1'b1: DB_out = data_out;
endcase
endmodule | 0 |
4,410 | data/full_repos/permissive/109846502/LCD_dp_tb.v | 109,846,502 | LCD_dp_tb.v | v | 138 | 81 | [] | [] | [] | null | line:133: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #2 init_sel = 2\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2 init_sel = 2\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #2 init_sel = 2\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #2 init_sel = 2\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #5 data_sel = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #5 DB_sel = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #5 state = 2\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #5 statelocal = 3\'d4; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #20 state = 2\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #20 state = 2\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #5 statelocal = 3\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n #5 index = 2\'d3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n #300 $finish;\n ^\n%Error: data/full_repos/permissive/109846502/LCD_dp_tb.v:47: Cannot find file containing module: \'LCD_dp\'\n LCD_dp uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp.sv\n LCD_dp\n LCD_dp.v\n LCD_dp.sv\n obj_dir/LCD_dp\n obj_dir/LCD_dp.v\n obj_dir/LCD_dp.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,661 | module | module LCD_dp_tb;
reg [1:0] init_sel;
reg data_sel;
reg DB_sel;
reg [1:0] state;
reg [2:0] statelocal;
reg [1:0] index;
reg [3:0] A1;
reg [3:0] A2;
reg [3:0] A3;
reg [3:0] A4;
reg [3:0] B1;
reg [3:0] B2;
reg [3:0] B3;
reg [3:0] B4;
wire [7:0] DB_out;
LCD_dp uut (
.init_sel(init_sel),
.data_sel(data_sel),
.DB_sel(DB_sel),
.state(state),
.statelocal(statelocal),
.index(index),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.DB_out(DB_out)
);
initial begin
init_sel = 0;
data_sel = 0;
DB_sel = 0;
state = 0;
statelocal = 0;
index = 0;
A1 = 0;
A2 = 0;
A3 = 0;
A4 = 0;
B1 = 0;
B2 = 0;
B3 = 0;
B4 = 0;
#100;
#2 init_sel = 2'd0;
#2 init_sel = 2'd1;
#2 init_sel = 2'd2;
#2 init_sel = 2'd3;
#5 data_sel = 1'b1;
#5 DB_sel = 1'b1;
#5 state = 2'd1;
statelocal = 3'd0;
index = 2'd0;
#5 index = 2'd1;
#5 index = 2'd2;
#5 index = 2'd3;
#5 statelocal = 3'd4;
index = 2'd0;
#5 index = 2'd1;
#20 state = 2'd2;
#20 state = 2'd0;
A1 = 4'd9;
A2 = 4'd3;
A3 = 4'd7;
A4 = 4'd1;
B1 = 4'd2;
B2 = 4'd4;
B3 = 4'd6;
B4 = 4'd8;
#5 statelocal = 3'd0;
index = 2'd0;
#5 index = 2'd1;
#5 index = 2'd2;
#5 index = 2'd3;
end
initial begin
#300 $finish;
end
endmodule | module LCD_dp_tb; |
reg [1:0] init_sel;
reg data_sel;
reg DB_sel;
reg [1:0] state;
reg [2:0] statelocal;
reg [1:0] index;
reg [3:0] A1;
reg [3:0] A2;
reg [3:0] A3;
reg [3:0] A4;
reg [3:0] B1;
reg [3:0] B2;
reg [3:0] B3;
reg [3:0] B4;
wire [7:0] DB_out;
LCD_dp uut (
.init_sel(init_sel),
.data_sel(data_sel),
.DB_sel(DB_sel),
.state(state),
.statelocal(statelocal),
.index(index),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.DB_out(DB_out)
);
initial begin
init_sel = 0;
data_sel = 0;
DB_sel = 0;
state = 0;
statelocal = 0;
index = 0;
A1 = 0;
A2 = 0;
A3 = 0;
A4 = 0;
B1 = 0;
B2 = 0;
B3 = 0;
B4 = 0;
#100;
#2 init_sel = 2'd0;
#2 init_sel = 2'd1;
#2 init_sel = 2'd2;
#2 init_sel = 2'd3;
#5 data_sel = 1'b1;
#5 DB_sel = 1'b1;
#5 state = 2'd1;
statelocal = 3'd0;
index = 2'd0;
#5 index = 2'd1;
#5 index = 2'd2;
#5 index = 2'd3;
#5 statelocal = 3'd4;
index = 2'd0;
#5 index = 2'd1;
#20 state = 2'd2;
#20 state = 2'd0;
A1 = 4'd9;
A2 = 4'd3;
A3 = 4'd7;
A4 = 4'd1;
B1 = 4'd2;
B2 = 4'd4;
B3 = 4'd6;
B4 = 4'd8;
#5 statelocal = 3'd0;
index = 2'd0;
#5 index = 2'd1;
#5 index = 2'd2;
#5 index = 2'd3;
end
initial begin
#300 $finish;
end
endmodule | 0 |
4,411 | data/full_repos/permissive/109846502/LCD_init_refresh.v | 109,846,502 | LCD_init_refresh.v | v | 117 | 100 | [] | [] | [] | [(21, 116)] | null | data/verilator_xmls/a28a50da-7a1b-44d1-9e1d-47f86b1c8c93.xml | null | 2,662 | module | module LCD_init_refresh(
input clk, rst,
input wr_finish, input lcd_enable, input [1:0] lcd_cnt, input mode,
output reg lcd_finish, output reg wr_enable, output reg [1:0] init_sel, output reg [1:0] mux_sel
);
reg [1:0] st, nst;
localparam
idle = 2'd0,
data = 2'd1,
data1 = 2'd2,
endlcd = 2'd3;
always @(posedge clk, posedge rst)
begin
if(rst) begin
st <= idle;
init_sel <= 2'd0;
mux_sel <= 2'd0;
end
else
begin
st <= nst;
case(st)
idle:
if(mode)
init_sel <= lcd_cnt;
else
mux_sel <= lcd_cnt;
endlcd:
if(mode)
begin
if(init_sel != 2'd0)
init_sel <= init_sel - 1;
end
else if (mux_sel != 2'd0)
mux_sel <= mux_sel - 1;
endcase
end
end
always @*
begin
lcd_finish = 1'b0;
wr_enable = 0;
case(st)
data:
wr_enable = 1'b1;
endlcd: begin
if(mode == 1'b1)
begin
if( init_sel == 2'd0)
lcd_finish = 1'b1;
end
else if(mux_sel == 2'd0)
lcd_finish = 1'b1;
end
endcase
end
always @*
case(st)
idle:
if(lcd_enable)
begin
nst <= data;
end
else
nst <= idle;
data:
nst <= data1;
data1:
if(wr_finish)
nst <= endlcd;
else
nst <= data1;
endlcd:
case(mode)
1'b0:
begin
if(mux_sel > 2'd0)
nst <= data;
else
nst <= idle;
end
1'b1:
if(init_sel > 2'd0)
nst <= data;
else
nst <= idle;
endcase
endcase
endmodule | module LCD_init_refresh(
input clk, rst,
input wr_finish, input lcd_enable, input [1:0] lcd_cnt, input mode,
output reg lcd_finish, output reg wr_enable, output reg [1:0] init_sel, output reg [1:0] mux_sel
); |
reg [1:0] st, nst;
localparam
idle = 2'd0,
data = 2'd1,
data1 = 2'd2,
endlcd = 2'd3;
always @(posedge clk, posedge rst)
begin
if(rst) begin
st <= idle;
init_sel <= 2'd0;
mux_sel <= 2'd0;
end
else
begin
st <= nst;
case(st)
idle:
if(mode)
init_sel <= lcd_cnt;
else
mux_sel <= lcd_cnt;
endlcd:
if(mode)
begin
if(init_sel != 2'd0)
init_sel <= init_sel - 1;
end
else if (mux_sel != 2'd0)
mux_sel <= mux_sel - 1;
endcase
end
end
always @*
begin
lcd_finish = 1'b0;
wr_enable = 0;
case(st)
data:
wr_enable = 1'b1;
endlcd: begin
if(mode == 1'b1)
begin
if( init_sel == 2'd0)
lcd_finish = 1'b1;
end
else if(mux_sel == 2'd0)
lcd_finish = 1'b1;
end
endcase
end
always @*
case(st)
idle:
if(lcd_enable)
begin
nst <= data;
end
else
nst <= idle;
data:
nst <= data1;
data1:
if(wr_finish)
nst <= endlcd;
else
nst <= data1;
endlcd:
case(mode)
1'b0:
begin
if(mux_sel > 2'd0)
nst <= data;
else
nst <= idle;
end
1'b1:
if(init_sel > 2'd0)
nst <= data;
else
nst <= idle;
endcase
endcase
endmodule | 0 |
4,412 | data/full_repos/permissive/109846502/LCD_init_refreshtb.v | 109,846,502 | LCD_init_refreshtb.v | v | 51 | 81 | [] | [] | [] | [(25, 49)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_init_refreshtb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109846502/LCD_init_refreshtb.v:32: Cannot find file containing module: \'LCD_init_refresh\'\n LCD_init_refresh uut (\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_init_refresh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_init_refresh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_init_refresh.sv\n LCD_init_refresh\n LCD_init_refresh.v\n LCD_init_refresh.sv\n obj_dir/LCD_init_refresh\n obj_dir/LCD_init_refresh.v\n obj_dir/LCD_init_refresh.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,663 | module | module LCD_init_refreshtb;
reg wr_finish;
reg lcd_enable;
LCD_init_refresh uut (
.wr_finish(wr_finish),
.lcd_enable(lcd_enable)
);
initial begin
wr_finish = 0;
lcd_enable = 0;
#100;
end
endmodule | module LCD_init_refreshtb; |
reg wr_finish;
reg lcd_enable;
LCD_init_refresh uut (
.wr_finish(wr_finish),
.lcd_enable(lcd_enable)
);
initial begin
wr_finish = 0;
lcd_enable = 0;
#100;
end
endmodule | 0 |
4,413 | data/full_repos/permissive/109846502/maintb.v | 109,846,502 | maintb.v | v | 62 | 81 | [] | [] | [] | [(25, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/maintb.v:51: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/maintb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20 rst = 1\'b0;\n ^\n%Error: data/full_repos/permissive/109846502/maintb.v:39: Cannot find file containing module: \'main\'\n main #(.div(2)) uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.sv\n main\n main.v\n main.sv\n obj_dir/main\n obj_dir/main.v\n obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,665 | module | module maintb;
reg rst;
reg clk;
reg en;
wire rw_out;
wire rs_out;
wire e_out;
wire [7:0] db_out;
main #(.div(2)) uut (
.rst(rst),
.clk(clk),
.rw_out(rw_out),
.rs_out(rs_out),
.e_out(e_out),
.db_out(db_out)
);
initial begin
en = 1'b1;
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#20 rst = 1'b0;
end
endmodule | module maintb; |
reg rst;
reg clk;
reg en;
wire rw_out;
wire rs_out;
wire e_out;
wire [7:0] db_out;
main #(.div(2)) uut (
.rst(rst),
.clk(clk),
.rw_out(rw_out),
.rs_out(rs_out),
.e_out(e_out),
.db_out(db_out)
);
initial begin
en = 1'b1;
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#20 rst = 1'b0;
end
endmodule | 0 |
4,414 | data/full_repos/permissive/109846502/main_controller.v | 109,846,502 | main_controller.v | v | 118 | 83 | [] | [] | [] | [(21, 117)] | null | null | 1: b"%Error: data/full_repos/permissive/109846502/main_controller.v:34: syntax error, unexpected ref, expecting IDENTIFIER\nref = 3'd4,\n^~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:87: syntax error, unexpected ref, expecting endcase\n ref:\n ^~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:96: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:108: syntax error, unexpected <=, expecting IDENTIFIER\n idle: nst <= init;\n ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:109: syntax error, unexpected <=, expecting IDENTIFIER\n init: nst <= lcd_finish ? addr : init;\n ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:110: syntax error, unexpected <=, expecting IDENTIFIER\n addr: nst <= addr1;\n ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:111: syntax error, unexpected <=, expecting IDENTIFIER\n addr1: nst <= lcd_finish ? ref : addr1;\n ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:113: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n ref1: nst <= lcd_finish ? addr : ref1;\n ^~~\n%Error: Cannot continue\n" | 2,666 | module | module main_controller(
input rst, clk,
input lcd_finish,
output reg mode,
output reg data_sel, db_sel, lcd_enable, reg_sel,
output reg [1:0] lcd_cnt
);
reg [2:0] st, nst;
localparam
idle = 3'd0,
init = 3'd1,
addr = 3'd2,
addr1 = 3'd3,
ref = 3'd4,
ref1 = 3'd5;
localparam
LCD_INIT = 1,
LCD_REF = 0,
REF_DATA_NO = 4;
always @(posedge clk, posedge rst)
begin
if(rst)
begin
st <= idle;
end
else
begin
st <= nst;
end
end
always @*
begin
lcd_enable = 1'b0;
db_sel = 1'b1;
lcd_cnt = 2'd3;
data_sel = 1'b0;
reg_sel = 1'b0;
data_sel = 1'b0;
mode = LCD_INIT;
case(st)
idle:
begin
lcd_enable = 1'b1;
end
init: begin
end
addr:
begin
lcd_enable = 1'b1;
db_sel = 1'b0;
lcd_cnt = 2'd0;
end
addr1:
begin
db_sel = 1'b0;
lcd_cnt = 2'd0;
end
ref:
begin
lcd_enable = 1'b1;
reg_sel = 1'b1;
data_sel = 1'b1;
mode = LCD_REF;
end
ref1:
begin
reg_sel = ~lcd_finish;
data_sel = 1'b1;
mode = LCD_REF;
end
endcase
end
always @* begin
nst <= idle;
case(st)
idle: nst <= init;
init: nst <= lcd_finish ? addr : init;
addr: nst <= addr1;
addr1: nst <= lcd_finish ? ref : addr1;
ref: nst <= ref1;
ref1: nst <= lcd_finish ? addr : ref1;
endcase
end
endmodule | module main_controller(
input rst, clk,
input lcd_finish,
output reg mode,
output reg data_sel, db_sel, lcd_enable, reg_sel,
output reg [1:0] lcd_cnt
); |
reg [2:0] st, nst;
localparam
idle = 3'd0,
init = 3'd1,
addr = 3'd2,
addr1 = 3'd3,
ref = 3'd4,
ref1 = 3'd5;
localparam
LCD_INIT = 1,
LCD_REF = 0,
REF_DATA_NO = 4;
always @(posedge clk, posedge rst)
begin
if(rst)
begin
st <= idle;
end
else
begin
st <= nst;
end
end
always @*
begin
lcd_enable = 1'b0;
db_sel = 1'b1;
lcd_cnt = 2'd3;
data_sel = 1'b0;
reg_sel = 1'b0;
data_sel = 1'b0;
mode = LCD_INIT;
case(st)
idle:
begin
lcd_enable = 1'b1;
end
init: begin
end
addr:
begin
lcd_enable = 1'b1;
db_sel = 1'b0;
lcd_cnt = 2'd0;
end
addr1:
begin
db_sel = 1'b0;
lcd_cnt = 2'd0;
end
ref:
begin
lcd_enable = 1'b1;
reg_sel = 1'b1;
data_sel = 1'b1;
mode = LCD_REF;
end
ref1:
begin
reg_sel = ~lcd_finish;
data_sel = 1'b1;
mode = LCD_REF;
end
endcase
end
always @* begin
nst <= idle;
case(st)
idle: nst <= init;
init: nst <= lcd_finish ? addr : init;
addr: nst <= addr1;
addr1: nst <= lcd_finish ? ref : addr1;
ref: nst <= ref1;
ref1: nst <= lcd_finish ? addr : ref1;
endcase
end
endmodule | 0 |
4,415 | data/full_repos/permissive/109846502/main_controllertb.v | 109,846,502 | main_controllertb.v | v | 52 | 81 | [] | [] | [] | [(25, 50)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:41: Unsupported: Ignoring delay on this delayed statement.\n forever #7 lcd_finish = ~lcd_finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #20 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:48: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/109846502/main_controllertb.v:33: Cannot find file containing module: \'main_controller\'\n main_controller uut (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller.sv\n main_controller\n main_controller.v\n main_controller.sv\n obj_dir/main_controller\n obj_dir/main_controller.v\n obj_dir/main_controller.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,667 | module | module main_controllertb;
reg rst;
reg clk;
reg lcd_finish;
main_controller uut (
.rst(rst),
.clk(clk),
.lcd_finish(lcd_finish)
);
initial begin
lcd_finish = 1'b1;
forever #7 lcd_finish = ~lcd_finish;
end
initial begin
clk = 1'b0;
rst = 1'b1;
#20 rst = 1'b0;
forever #1 clk = ~clk;
end
endmodule | module main_controllertb; |
reg rst;
reg clk;
reg lcd_finish;
main_controller uut (
.rst(rst),
.clk(clk),
.lcd_finish(lcd_finish)
);
initial begin
lcd_finish = 1'b1;
forever #7 lcd_finish = ~lcd_finish;
end
initial begin
clk = 1'b0;
rst = 1'b1;
#20 rst = 1'b0;
forever #1 clk = ~clk;
end
endmodule | 0 |
4,416 | data/full_repos/permissive/109846502/main_test.v | 109,846,502 | main_test.v | v | 92 | 81 | [] | [] | [] | null | line:65: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #105;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n repeat(200) #1 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n repeat(100) #1 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:81: Unsupported: Ignoring delay on this delayed statement.\n repeat(100) #1 \n ^\n%Error: data/full_repos/permissive/109846502/main_test.v:41: Cannot find file containing module: \'main\'\n main uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.sv\n main\n main.v\n main.sv\n obj_dir/main\n obj_dir/main.v\n obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,668 | module | module main_test;
reg rst;
reg clk;
reg [3:0] row;
wire [3:0] col;
wire rw_out;
wire rs_out;
wire e_out;
wire [7:0] db_out;
wire [6:0] leds;
main uut (
.rst(rst),
.clk(clk),
.row(row),
.col(col),
.rw_out(rw_out),
.rs_out(rs_out),
.e_out(e_out),
.db_out(db_out),
.leds(leds)
);
initial begin
clk = 1'b0;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#105;
rst = 1'b0;
end
initial begin
repeat(200) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1101;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1101;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
end
endmodule | module main_test; |
reg rst;
reg clk;
reg [3:0] row;
wire [3:0] col;
wire rw_out;
wire rs_out;
wire e_out;
wire [7:0] db_out;
wire [6:0] leds;
main uut (
.rst(rst),
.clk(clk),
.row(row),
.col(col),
.rw_out(rw_out),
.rs_out(rs_out),
.e_out(e_out),
.db_out(db_out),
.leds(leds)
);
initial begin
clk = 1'b0;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#105;
rst = 1'b0;
end
initial begin
repeat(200) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1101;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1111;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
repeat(100) #1
case(col)
4'b0111: row = 4'b1101;
4'b1011: row = 4'b1111;
4'b1101: row = 4'b1111;
4'b1110: row = 4'b1111;
endcase
end
endmodule | 0 |
4,417 | data/full_repos/permissive/109846502/Numerator.v | 109,846,502 | Numerator.v | v | 74 | 96 | [] | [] | [] | [(67, 118)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/Numerator.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`KEY_0\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n ^~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`KEY_9\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`SL_A\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`SL_B\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:62: Define or directive not defined: \'`SL_A\'\n 2\'d0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];\n ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:63: Define or directive not defined: \'`SL_A\'\n 2\'d1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];\n ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:64: Define or directive not defined: \'`SL_A\'\n 2\'d2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];\n ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:65: Define or directive not defined: \'`SL_A\'\n 2\'d3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];\n ^~~~~\n%Error: Cannot continue\n' | 2,669 | module | module Numerator(
input [1:0] index,
input enabled,
input [4:0] key,
input [2:0] ST_L,
input clk,
input rst,
output reg [3:0] A1,A2,A3,A4,B1,B2,B3,B4
,
input set,
input [15:0] setVal
);
always @(posedge clk, posedge rst)
begin
if(rst)
begin
A1 <= 4'd0;
A2 <= 4'd0;
A3 <= 4'd0;
A4 <= 4'd0;
B1 <= 4'd0;
B2 <= 4'd0;
B3 <= 4'd0;
B4 <= 4'd0;
end
else if(set) begin
A1 <= setVal[3:0];
A2 <= setVal[7:4];
A3 <= setVal[11:8];
A4 <= setVal[15:12];
B1 <= 4'd0;
B2 <= 4'd0;
B3 <= 4'd0;
B4 <= 4'd0;
end
else if(enabled == 1'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))
begin
case(index)
2'd0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];
2'd1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];
2'd2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];
2'd3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];
endcase
end
end
endmodule | module Numerator(
input [1:0] index,
input enabled,
input [4:0] key,
input [2:0] ST_L,
input clk,
input rst,
output reg [3:0] A1,A2,A3,A4,B1,B2,B3,B4
,
input set,
input [15:0] setVal
); |
always @(posedge clk, posedge rst)
begin
if(rst)
begin
A1 <= 4'd0;
A2 <= 4'd0;
A3 <= 4'd0;
A4 <= 4'd0;
B1 <= 4'd0;
B2 <= 4'd0;
B3 <= 4'd0;
B4 <= 4'd0;
end
else if(set) begin
A1 <= setVal[3:0];
A2 <= setVal[7:4];
A3 <= setVal[11:8];
A4 <= setVal[15:12];
B1 <= 4'd0;
B2 <= 4'd0;
B3 <= 4'd0;
B4 <= 4'd0;
end
else if(enabled == 1'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))
begin
case(index)
2'd0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];
2'd1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];
2'd2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];
2'd3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];
endcase
end
end
endmodule | 0 |
4,418 | data/full_repos/permissive/109846502/NumeratorTest.v | 109,846,502 | NumeratorTest.v | v | 129 | 81 | [] | [] | [] | [(70, 172)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/NumeratorTest.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:70: Unsupported: Ignoring delay on this delayed statement.\n #101;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:79: Define or directive not defined: \'`SL_A\'\n ST_L = `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_A;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n #120;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:83: Define or directive not defined: \'`KEY_3\'\n key = `KEY_3;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:84: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:86: Define or directive not defined: \'`KEY_5\'\n key = `KEY_5;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:87: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:90: Define or directive not defined: \'`KEY_1\'\n key = `KEY_1;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:92: Define or directive not defined: \'`KEY_5\'\n key = `KEY_5;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:94: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:96: Define or directive not defined: \'`KEY_0\'\n key = `KEY_0;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:98: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:99: Define or directive not defined: \'`SL_B\'\n ST_L = `SL_B;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L = `SL_B;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:101: Define or directive not defined: \'`KEY_3\'\n key = `KEY_3;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:102: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:104: Define or directive not defined: \'`KEY_5\'\n key = `KEY_5;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:108: Define or directive not defined: \'`KEY_1\'\n key = `KEY_1;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:109: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:110: Define or directive not defined: \'`KEY_5\'\n key = `KEY_5;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:110: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:112: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:114: Define or directive not defined: \'`KEY_0\'\n key = `KEY_0;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/NumeratorTest.v:114: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/NumeratorTest.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 25 error(s), 13 warning(s)\n' | 2,670 | module | module NumeratorTest;
reg [1:0] index;
reg enabled;
reg [4:0] key;
reg [2:0] ST_L;
reg clk;
reg rst;
reg set;
reg [15:0] setVal;
wire [3:0] A1;
wire [3:0] A2;
wire [3:0] A3;
wire [3:0] A4;
wire [3:0] B1;
wire [3:0] B2;
wire [3:0] B3;
wire [3:0] B4;
Numerator uut (
.index(index),
.enabled(enabled),
.key(key),
.ST_L(ST_L),
.clk(clk),
.rst(rst),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.set(set),
.setVal(setVal)
);
initial begin
rst = 1'b1;
clk = 1'b0;
#101;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
enabled = 1'b1;
set = 1'b0;
ST_L = `SL_A;
#120;
index = 2'd0;
key = `KEY_3;
#10;
index = 2'd1;
key = `KEY_5;
#10;
enabled = 1'b0;
index = 2'd2;
key = `KEY_1;
#10;
key = `KEY_5;
enabled = 1'b1;
#10;
index = 2'd3;
key = `KEY_0;
#20;
ST_L = `SL_B;
index = 2'd0;
key = `KEY_3;
#10;
index = 2'd1;
key = `KEY_5;
#10;
enabled = 1'b0;
index = 2'd2;
key = `KEY_1;
#10;
key = `KEY_5;
enabled = 1'b1;
#10;
index = 2'd3;
key = `KEY_0;
#100;
setVal[15:12] = 3'd5;
setVal[11:8] = 3'd4;
setVal[7:4] = 3'd3;
setVal[3:0] = 3'd2;
set = 1'b1;
end
endmodule | module NumeratorTest; |
reg [1:0] index;
reg enabled;
reg [4:0] key;
reg [2:0] ST_L;
reg clk;
reg rst;
reg set;
reg [15:0] setVal;
wire [3:0] A1;
wire [3:0] A2;
wire [3:0] A3;
wire [3:0] A4;
wire [3:0] B1;
wire [3:0] B2;
wire [3:0] B3;
wire [3:0] B4;
Numerator uut (
.index(index),
.enabled(enabled),
.key(key),
.ST_L(ST_L),
.clk(clk),
.rst(rst),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.B2(B2),
.B3(B3),
.B4(B4),
.set(set),
.setVal(setVal)
);
initial begin
rst = 1'b1;
clk = 1'b0;
#101;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
enabled = 1'b1;
set = 1'b0;
ST_L = `SL_A;
#120;
index = 2'd0;
key = `KEY_3;
#10;
index = 2'd1;
key = `KEY_5;
#10;
enabled = 1'b0;
index = 2'd2;
key = `KEY_1;
#10;
key = `KEY_5;
enabled = 1'b1;
#10;
index = 2'd3;
key = `KEY_0;
#20;
ST_L = `SL_B;
index = 2'd0;
key = `KEY_3;
#10;
index = 2'd1;
key = `KEY_5;
#10;
enabled = 1'b0;
index = 2'd2;
key = `KEY_1;
#10;
key = `KEY_5;
enabled = 1'b1;
#10;
index = 2'd3;
key = `KEY_0;
#100;
setVal[15:12] = 3'd5;
setVal[11:8] = 3'd4;
setVal[7:4] = 3'd3;
setVal[3:0] = 3'd2;
set = 1'b1;
end
endmodule | 0 |
4,419 | data/full_repos/permissive/109846502/redtb.v | 109,846,502 | redtb.v | v | 58 | 81 | [] | [] | [] | [(25, 56)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10; rst = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:47: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:53: Unsupported: Ignoring delay on this delayed statement.\n forever #15 en = ~en;\n ^\n%Error: data/full_repos/permissive/109846502/redtb.v:36: Cannot find file containing module: \'red\'\n red uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red.sv\n red\n red.v\n red.sv\n obj_dir/red\n obj_dir/red.v\n obj_dir/red.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,671 | module | module redtb;
reg clk;
reg rst;
reg en;
wire out;
red uut (
.clk(clk),
.rst(rst),
.en(en),
.out(out)
);
initial begin
clk = 1'b0;
rst = 1'b1;
#10; rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
en = 1'b0;
forever #15 en = ~en;
end
endmodule | module redtb; |
reg clk;
reg rst;
reg en;
wire out;
red uut (
.clk(clk),
.rst(rst),
.en(en),
.out(out)
);
initial begin
clk = 1'b0;
rst = 1'b1;
#10; rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
en = 1'b0;
forever #15 en = ~en;
end
endmodule | 0 |
4,420 | data/full_repos/permissive/109846502/reg.v | 109,846,502 | reg.v | v | 39 | 83 | [] | [] | [] | [(21, 38)] | null | data/verilator_xmls/58bfc0ef-8b53-490d-adc7-93cede6791aa.xml | null | 2,672 | module | module red( input clk, input rst, input en,
output out
);
reg[1:0] tmp;
always @(posedge clk, posedge rst)
begin
if(rst)
tmp <= 2'b0;
else begin
tmp[0] <= en;
tmp[1] <= tmp[0];
end
end
assign out = tmp[0] && ~tmp[1];
endmodule | module red( input clk, input rst, input en,
output out
); |
reg[1:0] tmp;
always @(posedge clk, posedge rst)
begin
if(rst)
tmp <= 2'b0;
else begin
tmp[0] <= en;
tmp[1] <= tmp[0];
end
end
assign out = tmp[0] && ~tmp[1];
endmodule | 0 |
4,421 | data/full_repos/permissive/109846502/StateMachine.v | 109,846,502 | StateMachine.v | v | 114 | 83 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/109846502/StateMachine.v:1: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: Define or directive not defined: \'`S_WPR\'\n ST <= `S_WPR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST <= `S_WPR;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: Define or directive not defined: \'`SL_A\'\n ST_L <= `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L <= `SL_A;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: Define or directive not defined: \'`S_GON\'\n `S_GON: begin\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: syntax error, unexpected \':\', expecting endcase\n `S_GON: begin\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`KEY_NONE\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_WPR\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_GON\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:55: Define or directive not defined: \'`S_WPR\'\n `S_WPR:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:56: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:57: Define or directive not defined: \'`KEY_A\'\n if(key == `KEY_A)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:59: Define or directive not defined: \'`S_GON\'\n ST <= `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_B\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: syntax error, unexpected else\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_0\'\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_9\'\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:65: Define or directive not defined: \'`S_GON\'\n ST <= `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: syntax error, unexpected else\n else if(key != `KEY_NONE)\n ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: Define or directive not defined: \'`KEY_NONE\'\n else if(key != `KEY_NONE)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:70: Define or directive not defined: \'`S_OP\'\n ST <= `S_OP;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: Define or directive not defined: \'`KEY_B\'\n `KEY_B:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: syntax error, unexpected \':\', expecting endcase\n `KEY_B:\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:74: Define or directive not defined: \'`SL_ADD\'\n ST_L <= `SL_ADD;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:75: Define or directive not defined: \'`KEY_C\'\n `KEY_C:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:76: Define or directive not defined: \'`SL_SUB\'\n ST_L <= `SL_SUB;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:77: Define or directive not defined: \'`KEY_D\'\n `KEY_D:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:78: Define or directive not defined: \'`SL_AND\'\n ST_L <= `SL_AND;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:79: Define or directive not defined: \'`KEY_E\'\n `KEY_E:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:80: Define or directive not defined: \'`SL_OR\'\n ST_L <= `SL_OR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:81: Define or directive not defined: \'`KEY_F\'\n `KEY_F:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:82: Define or directive not defined: \'`SL_XOR\'\n ST_L <= `SL_XOR;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:86: Define or directive not defined: \'`S_OP\'\n `S_OP: begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: syntax error, unexpected <=, expecting IDENTIFIER\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`KEY_NONE\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OBL\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OP\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:92: Define or directive not defined: \'`S_OBL\'\n `S_OBL:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:93: Define or directive not defined: \'`KEY_NONE\'\n if(key == `KEY_NONE && end_obl) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:94: Define or directive not defined: \'`S_WPR\'\n ST <= `S_WPR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:95: Define or directive not defined: \'`SL_A\'\n ST_L <= `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:98: Define or directive not defined: \'`S_OBL\'\n ST <= `S_OBL;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:105: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:108: syntax error, unexpected \'=\', expecting IDENTIFIER\n val = val >> 1;\n ^\n%Error: Cannot continue\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,673 | module | module StateMachine
#(parameter waiter = 10000)
(
input [4:0] key,
input clk,
input rst,
input end_obl,
output reg [1:0] ST,
output reg [1:0] index,
output reg [2:0] ST_L
);
localparam nbits = clog2b(waiter) + 1;
reg [nbits - 1:0] cnt;
assign comp = (cnt >= (waiter - 1));
always @(posedge clk, posedge rst)
begin
if(rst) begin
ST <= `S_WPR;
ST_L <= `SL_A;
index <= 2'd0;
end
else begin
case(ST)
`S_GON: begin
cnt <= cnt + 1;
if(comp) begin
ST <= key == `KEY_NONE ? `S_WPR : `S_GON;
cnt <= cnt <= {nbits{1'b0}};
end end
`S_WPR:
begin
if(key == `KEY_A)
begin
ST <= `S_GON;
ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;
index <= 2'd0;
end
else if(key >= `KEY_0 && key <= `KEY_9)
begin
ST <= `S_GON;
index <= index + 1;
end
else if(key != `KEY_NONE)
begin
ST <= `S_OP;
index <= 2'd0;
case(key)
`KEY_B:
ST_L <= `SL_ADD;
`KEY_C:
ST_L <= `SL_SUB;
`KEY_D:
ST_L <= `SL_AND;
`KEY_E:
ST_L <= `SL_OR;
`KEY_F:
ST_L <= `SL_XOR;
endcase
end
end
`S_OP: begin
cnt <= cnt + 1;
if(comp) begin
ST <= key == `KEY_NONE ? `S_OBL : `S_OP;
cnt <= cnt <= {nbits{1'b0}};
end end
`S_OBL:
if(key == `KEY_NONE && end_obl) begin
ST <= `S_WPR;
ST_L <= `SL_A;
end
else
ST <= `S_OBL;
endcase
end
end
function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction
endmodule | module StateMachine
#(parameter waiter = 10000)
(
input [4:0] key,
input clk,
input rst,
input end_obl,
output reg [1:0] ST,
output reg [1:0] index,
output reg [2:0] ST_L
); |
localparam nbits = clog2b(waiter) + 1;
reg [nbits - 1:0] cnt;
assign comp = (cnt >= (waiter - 1));
always @(posedge clk, posedge rst)
begin
if(rst) begin
ST <= `S_WPR;
ST_L <= `SL_A;
index <= 2'd0;
end
else begin
case(ST)
`S_GON: begin
cnt <= cnt + 1;
if(comp) begin
ST <= key == `KEY_NONE ? `S_WPR : `S_GON;
cnt <= cnt <= {nbits{1'b0}};
end end
`S_WPR:
begin
if(key == `KEY_A)
begin
ST <= `S_GON;
ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;
index <= 2'd0;
end
else if(key >= `KEY_0 && key <= `KEY_9)
begin
ST <= `S_GON;
index <= index + 1;
end
else if(key != `KEY_NONE)
begin
ST <= `S_OP;
index <= 2'd0;
case(key)
`KEY_B:
ST_L <= `SL_ADD;
`KEY_C:
ST_L <= `SL_SUB;
`KEY_D:
ST_L <= `SL_AND;
`KEY_E:
ST_L <= `SL_OR;
`KEY_F:
ST_L <= `SL_XOR;
endcase
end
end
`S_OP: begin
cnt <= cnt + 1;
if(comp) begin
ST <= key == `KEY_NONE ? `S_OBL : `S_OP;
cnt <= cnt <= {nbits{1'b0}};
end end
`S_OBL:
if(key == `KEY_NONE && end_obl) begin
ST <= `S_WPR;
ST_L <= `SL_A;
end
else
ST <= `S_OBL;
endcase
end
end
function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction
endmodule | 0 |
4,422 | data/full_repos/permissive/109846502/StateMachine.v | 109,846,502 | StateMachine.v | v | 114 | 83 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/109846502/StateMachine.v:1: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: Define or directive not defined: \'`S_WPR\'\n ST <= `S_WPR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST <= `S_WPR;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: Define or directive not defined: \'`SL_A\'\n ST_L <= `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ST_L <= `SL_A;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: Define or directive not defined: \'`S_GON\'\n `S_GON: begin\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: syntax error, unexpected \':\', expecting endcase\n `S_GON: begin\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`KEY_NONE\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_WPR\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_GON\'\n ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:55: Define or directive not defined: \'`S_WPR\'\n `S_WPR:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:56: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:57: Define or directive not defined: \'`KEY_A\'\n if(key == `KEY_A)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:59: Define or directive not defined: \'`S_GON\'\n ST <= `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_B\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: syntax error, unexpected else\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_0\'\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_9\'\n else if(key >= `KEY_0 && key <= `KEY_9)\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:65: Define or directive not defined: \'`S_GON\'\n ST <= `S_GON;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: syntax error, unexpected else\n else if(key != `KEY_NONE)\n ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: Define or directive not defined: \'`KEY_NONE\'\n else if(key != `KEY_NONE)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:70: Define or directive not defined: \'`S_OP\'\n ST <= `S_OP;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: Define or directive not defined: \'`KEY_B\'\n `KEY_B:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: syntax error, unexpected \':\', expecting endcase\n `KEY_B:\n ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:74: Define or directive not defined: \'`SL_ADD\'\n ST_L <= `SL_ADD;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:75: Define or directive not defined: \'`KEY_C\'\n `KEY_C:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:76: Define or directive not defined: \'`SL_SUB\'\n ST_L <= `SL_SUB;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:77: Define or directive not defined: \'`KEY_D\'\n `KEY_D:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:78: Define or directive not defined: \'`SL_AND\'\n ST_L <= `SL_AND;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:79: Define or directive not defined: \'`KEY_E\'\n `KEY_E:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:80: Define or directive not defined: \'`SL_OR\'\n ST_L <= `SL_OR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:81: Define or directive not defined: \'`KEY_F\'\n `KEY_F:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:82: Define or directive not defined: \'`SL_XOR\'\n ST_L <= `SL_XOR;\n ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:86: Define or directive not defined: \'`S_OP\'\n `S_OP: begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: syntax error, unexpected <=, expecting IDENTIFIER\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`KEY_NONE\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OBL\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OP\'\n ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:92: Define or directive not defined: \'`S_OBL\'\n `S_OBL:\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:93: Define or directive not defined: \'`KEY_NONE\'\n if(key == `KEY_NONE && end_obl) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:94: Define or directive not defined: \'`S_WPR\'\n ST <= `S_WPR;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:95: Define or directive not defined: \'`SL_A\'\n ST_L <= `SL_A;\n ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:98: Define or directive not defined: \'`S_OBL\'\n ST <= `S_OBL;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:105: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:108: syntax error, unexpected \'=\', expecting IDENTIFIER\n val = val >> 1;\n ^\n%Error: Cannot continue\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,673 | function | function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction | function integer clog2b; |
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
val = val >> 1;
end
endfunction | 0 |
4,423 | data/full_repos/permissive/109846502/StateMachineTest.v | 109,846,502 | StateMachineTest.v | v | 82 | 81 | [] | [] | [] | [(70, 125)] | null | null | 1: b'%Error: data/full_repos/permissive/109846502/StateMachineTest.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:56: Define or directive not defined: \'`KEY_NONE\'\n key = `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_NONE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:59: Define or directive not defined: \'`KEY_2\'\n key = `KEY_2;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:61: Define or directive not defined: \'`KEY_NONE\'\n key = `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_NONE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:63: Define or directive not defined: \'`KEY_A\'\n key = `KEY_A;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_A;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:65: Define or directive not defined: \'`KEY_NONE\'\n key = `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_NONE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:67: Define or directive not defined: \'`KEY_4\'\n key = `KEY_4;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:69: Define or directive not defined: \'`KEY_NONE\'\n key = `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_NONE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:71: Define or directive not defined: \'`KEY_D\'\n key = `KEY_D;\n ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_D;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/StateMachineTest.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:75: Define or directive not defined: \'`KEY_NONE\'\n key = `KEY_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachineTest.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n key = `KEY_NONE;\n ^\n%Error: Exiting due to 19 error(s), 11 warning(s)\n' | 2,674 | module | module StateMachineTest;
reg [4:0] key;
reg clk;
reg rst;
reg end_obl;
wire [1:0] ST;
wire [2:0] ST_L;
StateMachine uut (
.key(key),
.clk(clk),
.rst(rst),
.end_obl(end_obl),
.ST(ST),
.ST_L(ST_L)
);
initial begin
rst = 1'b1;
clk = 1'b0;
#100;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
key = `KEY_NONE;
end_obl = 1'b0;
#100;
key = `KEY_2;
#10;
key = `KEY_NONE;
#10;
key = `KEY_A;
#10;
key = `KEY_NONE;
#10;
key = `KEY_4;
#10;
key = `KEY_NONE;
#10;
key = `KEY_D;
#10;
end_obl = 1'b1;
#10;
key = `KEY_NONE;
end
endmodule | module StateMachineTest; |
reg [4:0] key;
reg clk;
reg rst;
reg end_obl;
wire [1:0] ST;
wire [2:0] ST_L;
StateMachine uut (
.key(key),
.clk(clk),
.rst(rst),
.end_obl(end_obl),
.ST(ST),
.ST_L(ST_L)
);
initial begin
rst = 1'b1;
clk = 1'b0;
#100;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
key = `KEY_NONE;
end_obl = 1'b0;
#100;
key = `KEY_2;
#10;
key = `KEY_NONE;
#10;
key = `KEY_A;
#10;
key = `KEY_NONE;
#10;
key = `KEY_4;
#10;
key = `KEY_NONE;
#10;
key = `KEY_D;
#10;
end_obl = 1'b1;
#10;
key = `KEY_NONE;
end
endmodule | 0 |
4,424 | data/full_repos/permissive/109846502/test.v | 109,846,502 | test.v | v | 35 | 83 | [] | [] | [] | [(21, 34)] | null | data/verilator_xmls/1f90e7cb-155d-478f-b736-2026ab2a3170.xml | null | 2,675 | module | module test(
input clk,
input rst,
output reg out
);
always @(posedge clk, posedge rst)
if(rst)
out <= 1'b0;
else
out <= ~out;
endmodule | module test(
input clk,
input rst,
output reg out
); |
always @(posedge clk, posedge rst)
if(rst)
out <= 1'b0;
else
out <= ~out;
endmodule | 0 |
4,425 | data/full_repos/permissive/109846502/testtb.v | 109,846,502 | testtb.v | v | 57 | 81 | [] | [] | [] | [(25, 55)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/testtb.v:45: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/testtb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 1\'b0;\n ^\n%Error: data/full_repos/permissive/109846502/testtb.v:35: Can\'t resolve module reference: \'test\'\n test uut (\n ^~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,676 | module | module testtb;
reg clk;
reg rst;
wire out;
test uut (
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#10 rst = 1'b0;
end
endmodule | module testtb; |
reg clk;
reg rst;
wire out;
test uut (
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
rst = 1'b1;
#10 rst = 1'b0;
end
endmodule | 0 |
4,426 | data/full_repos/permissive/109846502/write_cycle.v | 109,846,502 | write_cycle.v | v | 69 | 83 | [] | [] | [] | [(21, 68)] | null | data/verilator_xmls/9af39029-6677-495c-b8cc-9eebda829d0e.xml | null | 2,677 | module | module write_cycle(
input rst, clk,
input wr_enable, reg_sel,
output reg e_out, wr_finish,
output rs_out, rw_out
);
reg [1:0] st, nst;
localparam
idle = 2'd0,
init = 2'd1,
eout = 2'd2,
endwr = 2'd3;
always @(posedge clk, posedge rst)
begin
if(rst)
st <= idle;
else
st <= nst;
end
always @*
case(st)
idle: if(wr_enable) nst = init; else nst = idle;
init: nst =eout;
eout: nst = endwr;
endwr: nst = idle;
endcase
always @*
begin
wr_finish = 1'b0;
case(st)
idle: begin e_out = 1'b0; end
init: begin e_out = 1'b1; end
eout: begin e_out = 1'b1; end
endwr: begin
e_out = 1'b0;
wr_finish = 1'b1;
end
endcase
end
assign rw_out = 1'b0;
assign rs_out = reg_sel;
endmodule | module write_cycle(
input rst, clk,
input wr_enable, reg_sel,
output reg e_out, wr_finish,
output rs_out, rw_out
); |
reg [1:0] st, nst;
localparam
idle = 2'd0,
init = 2'd1,
eout = 2'd2,
endwr = 2'd3;
always @(posedge clk, posedge rst)
begin
if(rst)
st <= idle;
else
st <= nst;
end
always @*
case(st)
idle: if(wr_enable) nst = init; else nst = idle;
init: nst =eout;
eout: nst = endwr;
endwr: nst = idle;
endcase
always @*
begin
wr_finish = 1'b0;
case(st)
idle: begin e_out = 1'b0; end
init: begin e_out = 1'b1; end
eout: begin e_out = 1'b1; end
endwr: begin
e_out = 1'b0;
wr_finish = 1'b1;
end
endcase
end
assign rw_out = 1'b0;
assign rs_out = reg_sel;
endmodule | 0 |
4,427 | data/full_repos/permissive/109846502/write_cycletb.v | 109,846,502 | write_cycletb.v | v | 72 | 81 | [] | [] | [] | [(25, 70)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:56: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:61: Unsupported: Ignoring delay on this delayed statement.\n forever #25 reg_sel = ~reg_sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:66: Unsupported: Ignoring delay on this delayed statement.\n forever #25 wr_enable = ~wr_enable;\n ^\n%Error: data/full_repos/permissive/109846502/write_cycletb.v:40: Cannot find file containing module: \'write_cycle\'\n write_cycle uut (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle.v\n data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle.sv\n write_cycle\n write_cycle.v\n write_cycle.sv\n obj_dir/write_cycle\n obj_dir/write_cycle.v\n obj_dir/write_cycle.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,678 | module | module write_cycletb;
reg wr_enable;
reg reg_sel;
reg rst;
reg clk;
wire e_out;
wire rs_out;
wire rw_out;
wire wr_finish;
write_cycle uut (
.wr_enable(wr_enable),
.reg_sel(reg_sel),
.rst(rst),
.clk(clk),
.e_out(e_out),
.rs_out(rs_out),
.rw_out(rw_out),
.wr_finish(wr_finish)
);
initial begin
clk = 1'b0;
rst = 1'b1;
#1;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
reg_sel = 1'b1;
forever #25 reg_sel = ~reg_sel;
end
initial begin
wr_enable = 1'b1;
forever #25 wr_enable = ~wr_enable;
end
endmodule | module write_cycletb; |
reg wr_enable;
reg reg_sel;
reg rst;
reg clk;
wire e_out;
wire rs_out;
wire rw_out;
wire wr_finish;
write_cycle uut (
.wr_enable(wr_enable),
.reg_sel(reg_sel),
.rst(rst),
.clk(clk),
.e_out(e_out),
.rs_out(rs_out),
.rw_out(rw_out),
.wr_finish(wr_finish)
);
initial begin
clk = 1'b0;
rst = 1'b1;
#1;
rst = 1'b0;
forever #1 clk = ~clk;
end
initial begin
reg_sel = 1'b1;
forever #25 reg_sel = ~reg_sel;
end
initial begin
wr_enable = 1'b1;
forever #25 wr_enable = ~wr_enable;
end
endmodule | 0 |
4,429 | data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v | 109,936,328 | gpio_interface.v | v | 97 | 71 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:38: Define or directive not defined: \'`WORD_W\'\n localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:38: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:41: Define or directive not defined: \'`WORD_W\'\n localparam GPIO_W = WORD_COUNT * `WORD_W;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam GPIO_W = WORD_COUNT * `WORD_W;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:50: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:51: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:53: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] i_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:58: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:59: Define or directive not defined: \'`MEM_CODE_W\'\n output reg [`MEM_CODE_W - 1:0] o_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:64: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/gpio_interface.v:65: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] s_res_code;\n ^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n' | 2,684 | module | module gpio_interface(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code,
o_gpio_state
);
parameter ADDR_START = 0;
parameter BANK_COUNT = 1;
localparam WORD_COUNT = BANK_COUNT;
localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam ADDR_END = ADDR_START + ADDR_COUNT - 1;
localparam real R_ADDR_COUNT = ADDR_COUNT;
localparam GPIO_W = WORD_COUNT * `WORD_W;
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
output [GPIO_W - 1:0] o_gpio_state;
wire [`WORD_W - 1:0] s_res_rd_data;
wire [`MEM_CODE_W - 1:0] s_res_code;
readwrite_registers#(
.ADDR_START(ADDR_START),
.WORD_COUNT(WORD_COUNT)
) rw_reg(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(i_req_addr),
.i_req_wr_data(i_req_wr_data),
.i_req_wr_en(i_req_wr_en),
.i_req_count(i_req_count),
.o_res_rd_data(s_res_rd_data),
.o_res_code(s_res_code),
.o_exposed_mem(o_gpio_state)
);
always@(*) begin
if(i_req_addr >= ADDR_START && i_req_addr <= ADDR_END) begin
o_res_rd_data = s_res_rd_data;
o_res_code = s_res_code;
end else begin
o_res_rd_data = 'bz;
o_res_code = 'bz;
end
end
endmodule | module gpio_interface(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code,
o_gpio_state
); |
parameter ADDR_START = 0;
parameter BANK_COUNT = 1;
localparam WORD_COUNT = BANK_COUNT;
localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam ADDR_END = ADDR_START + ADDR_COUNT - 1;
localparam real R_ADDR_COUNT = ADDR_COUNT;
localparam GPIO_W = WORD_COUNT * `WORD_W;
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
output [GPIO_W - 1:0] o_gpio_state;
wire [`WORD_W - 1:0] s_res_rd_data;
wire [`MEM_CODE_W - 1:0] s_res_code;
readwrite_registers#(
.ADDR_START(ADDR_START),
.WORD_COUNT(WORD_COUNT)
) rw_reg(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(i_req_addr),
.i_req_wr_data(i_req_wr_data),
.i_req_wr_en(i_req_wr_en),
.i_req_count(i_req_count),
.o_res_rd_data(s_res_rd_data),
.o_res_code(s_res_code),
.o_exposed_mem(o_gpio_state)
);
always@(*) begin
if(i_req_addr >= ADDR_START && i_req_addr <= ADDR_END) begin
o_res_rd_data = s_res_rd_data;
o_res_code = s_res_code;
end else begin
o_res_rd_data = 'bz;
o_res_code = 'bz;
end
end
endmodule | 0 |
4,430 | data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v | 109,936,328 | instruction_memory.v | v | 51 | 79 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:25: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:26: Define or directive not defined: \'`INSTR_W\'\n output reg [`INSTR_W - 1:0] o_res_data;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:29: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] read_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:33: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:40: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:40: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: Define or directive not defined: \'`FUNCT3_ADD\'\n o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: Define or directive not defined: \'`OPCODE_ITYPE\'\n o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n ^~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n' | 2,685 | module | module instruction_memory(
clk,
i_req_addr,
o_res_data
);
parameter INSTR_MAX = 256;
parameter INSTR_FILE = "instr.txt";
parameter DUMP_INSTR = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input [`ADDR_W - 1:0] i_req_addr;
output reg [`INSTR_W - 1:0] o_res_data;
integer instr_file;
reg [`INSTR_W - 1:0] read_instr;
integer i;
integer fscanf_ret;
reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];
initial begin: load_instr
$readmemh(INSTR_FILE, r_mem, 0, INSTR_MAX - 1);
end
wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];
always@(posedge clk) begin
if(word_addr < INSTR_MAX) begin
o_res_data <= r_mem[word_addr];
end else begin
o_res_data <= `NOP;
end
end
endmodule | module instruction_memory(
clk,
i_req_addr,
o_res_data
); |
parameter INSTR_MAX = 256;
parameter INSTR_FILE = "instr.txt";
parameter DUMP_INSTR = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input [`ADDR_W - 1:0] i_req_addr;
output reg [`INSTR_W - 1:0] o_res_data;
integer instr_file;
reg [`INSTR_W - 1:0] read_instr;
integer i;
integer fscanf_ret;
reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];
initial begin: load_instr
$readmemh(INSTR_FILE, r_mem, 0, INSTR_MAX - 1);
end
wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];
always@(posedge clk) begin
if(word_addr < INSTR_MAX) begin
o_res_data <= r_mem[word_addr];
end else begin
o_res_data <= `NOP;
end
end
endmodule | 0 |
4,431 | data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v | 109,936,328 | memory_interface.v | v | 147 | 78 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:17: Define or directive not defined: \'`ADDR_W\'\n parameter WORD_COUNT = 1 << (`ADDR_W - 2);\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:26: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:27: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:29: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] i_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:32: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:33: Define or directive not defined: \'`MEM_CODE_W\'\n output reg [`MEM_CODE_W - 1:0] o_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:36: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:39: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 2 - 1:0] s_addr_aligned;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:42: Define or directive not defined: \'`ADDR_W\'\n assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:49: Unsupported or unknown PLI call: $dumpfile\n $dumpfile(DUMP_FILE);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:51: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, r_mem[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:67: Define or directive not defined: \'`MEM_COUNT_NONE\'\n end else if(i_req_count != `MEM_COUNT_NONE) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n end else if(i_req_count != `MEM_COUNT_NONE) begin\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:69: Define or directive not defined: \'`MEM_COUNT_HALF\'\n if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:70: Define or directive not defined: \'`MEM_COUNT_WORD\'\n (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:73: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:78: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:84: Define or directive not defined: \'`MEM_CODE_WRITE\'\n o_res_code <= `MEM_CODE_WRITE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:88: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:88: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE:\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:96: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:102: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:104: Define or directive not defined: \'`MEM_CODE_INVALID\'\n default: o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:111: Define or directive not defined: \'`MEM_CODE_READ\'\n o_res_code <= `MEM_CODE_READ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:115: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:115: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE:\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:124: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:131: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:133: Define or directive not defined: \'`MEM_CODE_INVALID\'\n default: o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:141: Define or directive not defined: \'`MEM_CODE_INVALID\'\n o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n' | 2,686 | module | module memory_interface(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code
);
parameter WORD_COUNT = 1 << (`ADDR_W - 2);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];
wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
wire [1:0] s_offset;
assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
assign s_offset = i_req_addr[1:0];
integer i;
initial begin
if(DUMP_VARS == 1) begin
$dumpfile(DUMP_FILE);
for(i = 0; i < WORD_COUNT; i = i + 1) begin
$dumpvars(0, r_mem[i]);
end
end
end
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < WORD_COUNT; i = i + 1) begin
r_mem[i] <= 0;
end
o_res_rd_data <= 0;
o_res_code <= 0;
end else if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned >= WORD_COUNT) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;
end else if(i_req_wr_en == 1) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_WRITE;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
endcase
`MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
default: o_res_rd_data <= 0;
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
default: o_res_rd_data <= 0;
endcase
`MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
end
endmodule | module memory_interface(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code
); |
parameter WORD_COUNT = 1 << (`ADDR_W - 2);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];
wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
wire [1:0] s_offset;
assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
assign s_offset = i_req_addr[1:0];
integer i;
initial begin
if(DUMP_VARS == 1) begin
$dumpfile(DUMP_FILE);
for(i = 0; i < WORD_COUNT; i = i + 1) begin
$dumpvars(0, r_mem[i]);
end
end
end
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < WORD_COUNT; i = i + 1) begin
r_mem[i] <= 0;
end
o_res_rd_data <= 0;
o_res_code <= 0;
end else if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned >= WORD_COUNT) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;
end else if(i_req_wr_en == 1) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_WRITE;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
endcase
`MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
default: o_res_rd_data <= 0;
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
default: o_res_rd_data <= 0;
endcase
`MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
end
endmodule | 0 |
4,432 | data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v | 109,936,328 | readonly_registers.v | v | 128 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:28: Define or directive not defined: \'`WORD_W\'\n localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:28: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:41: Define or directive not defined: \'`WORD_W\'\n input [WORD_COUNT * `WORD_W - 1:0] i_registers;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:43: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:44: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] i_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:50: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:51: Define or directive not defined: \'`MEM_CODE_W\'\n output reg [`MEM_CODE_W - 1:0] o_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:57: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:59: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 2 - 1:0] s_addr_aligned;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:60: Define or directive not defined: \'`ADDR_W\'\n assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: Define or directive not defined: \'`WORD_W\'\n assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: Define or directive not defined: \'`WORD_W\'\n assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:75: Define or directive not defined: \'`MEM_CODE_INVALID\'\n o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_res_code <= `MEM_CODE_INVALID;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:77: Define or directive not defined: \'`MEM_COUNT_NONE\'\n if(i_req_count != `MEM_COUNT_NONE) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(i_req_count != `MEM_COUNT_NONE) begin\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:79: Define or directive not defined: \'`MEM_COUNT_HALF\'\n if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:80: Define or directive not defined: \'`MEM_COUNT_WORD\'\n (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:83: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:88: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:93: Define or directive not defined: \'`MEM_CODE_READ\'\n o_res_code <= `MEM_CODE_READ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:96: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:96: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE: begin\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:99: syntax error, unexpected \'[\', expecting IDENTIFIER\n 0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:100: syntax error, unexpected \'[\', expecting IDENTIFIER\n 1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:101: syntax error, unexpected \'[\', expecting IDENTIFIER\n 2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:102: syntax error, unexpected \'[\', expecting IDENTIFIER\n 3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n default: o_res_rd_data[7:0] <= 0;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:107: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:110: syntax error, unexpected \'[\', expecting IDENTIFIER\n 0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:111: syntax error, unexpected \'[\', expecting IDENTIFIER\n 1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:112: syntax error, unexpected \'[\', expecting IDENTIFIER\n default: o_res_rd_data[15:0] <= 0;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:116: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:120: Define or directive not defined: \'`MEM_CODE_INVALID\'\n o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n' | 2,687 | module | module readonly_registers(
clk,
aresetn,
i_registers,
i_req_addr,
i_req_count,
o_res_rd_data,
o_res_code
);
parameter WORD_COUNT = 1;
parameter ADDR_START = 0;
localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam ADDR_END = ADDR_COUNT + ADDR_START - 1;
localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];
input clk;
input aresetn;
input [WORD_COUNT * `WORD_W - 1:0] i_registers;
input [`ADDR_W - 1:0] i_req_addr;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];
wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
wire [1:0] s_offset;
assign s_offset = i_req_addr[1:0];
genvar i;
generate
for(i = 0; i < WORD_COUNT; i = i + 1) begin: memory_remap
assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];
end
endgenerate
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end else begin
if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned > ADDR_END) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE: begin
o_res_rd_data[31:8] <= 0;
case(s_offset)
0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];
default: o_res_rd_data[7:0] <= 0;
endcase
end
`MEM_COUNT_HALF: begin
o_res_rd_data[31:15] <= 0;
case(s_offset[1])
0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];
1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];
default: o_res_rd_data[15:0] <= 0;
endcase
end
`MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];
default: begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
endcase
end
end
end
end
endmodule | module readonly_registers(
clk,
aresetn,
i_registers,
i_req_addr,
i_req_count,
o_res_rd_data,
o_res_code
); |
parameter WORD_COUNT = 1;
parameter ADDR_START = 0;
localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam ADDR_END = ADDR_COUNT + ADDR_START - 1;
localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];
input clk;
input aresetn;
input [WORD_COUNT * `WORD_W - 1:0] i_registers;
input [`ADDR_W - 1:0] i_req_addr;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];
wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
wire [1:0] s_offset;
assign s_offset = i_req_addr[1:0];
genvar i;
generate
for(i = 0; i < WORD_COUNT; i = i + 1) begin: memory_remap
assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];
end
endgenerate
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end else begin
if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned > ADDR_END) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE: begin
o_res_rd_data[31:8] <= 0;
case(s_offset)
0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];
default: o_res_rd_data[7:0] <= 0;
endcase
end
`MEM_COUNT_HALF: begin
o_res_rd_data[31:15] <= 0;
case(s_offset[1])
0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];
1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];
default: o_res_rd_data[15:0] <= 0;
endcase
end
`MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];
default: begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
endcase
end
end
end
end
endmodule | 0 |
4,433 | data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v | 109,936,328 | readwrite_registers.v | v | 167 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:23: Define or directive not defined: \'`ADDR_W\'\n parameter [`ADDR_W - 1:0] ADDR_START = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:30: Define or directive not defined: \'`WORD_W\'\n localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:30: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:33: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:33: Define or directive not defined: \'`ADDR_W\'\n localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:42: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:43: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:45: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] i_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:51: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:52: Define or directive not defined: \'`MEM_CODE_W\'\n output reg [`MEM_CODE_W - 1:0] o_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:53: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:53: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:56: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:56: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:61: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: Define or directive not defined: \'`WORD_W\'\n assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: Define or directive not defined: \'`WORD_W\'\n assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:90: Define or directive not defined: \'`MEM_COUNT_NONE\'\n end else if(i_req_count != `MEM_COUNT_NONE) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n end else if(i_req_count != `MEM_COUNT_NONE) begin\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:92: Define or directive not defined: \'`MEM_COUNT_HALF\'\n if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:93: Define or directive not defined: \'`MEM_COUNT_WORD\'\n (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:96: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_res_code <= `MEM_CODE_MISALIGNED;\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:101: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:107: Define or directive not defined: \'`MEM_CODE_WRITE\'\n o_res_code <= `MEM_CODE_WRITE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:111: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:111: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE:\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:119: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:125: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:127: Define or directive not defined: \'`MEM_CODE_INVALID\'\n default: o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:134: Define or directive not defined: \'`MEM_CODE_READ\'\n o_res_code <= `MEM_CODE_READ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:138: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:138: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE:\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:146: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:152: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:154: Define or directive not defined: \'`MEM_CODE_INVALID\'\n default: o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:162: Define or directive not defined: \'`MEM_CODE_INVALID\'\n o_res_code <= `MEM_CODE_INVALID;\n ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n' | 2,688 | module | module readwrite_registers(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code,
o_exposed_mem
);
parameter [`ADDR_W - 1:0] ADDR_START = 0;
parameter WORD_COUNT = 1;
localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;
localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;
wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];
wire [1:0] s_offset = i_req_addr[1:0];
reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];
genvar j;
generate
for(j = 0; j < WORD_COUNT; j = j + 1) begin: mem_assign
assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];
end
endgenerate
integer i;
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < ADDR_COUNT; i = i + 1) begin
r_mem[i] <= 0;
end
o_res_rd_data <= 0;
o_res_code <= 0;
end else if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned > ADDR_END) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;
end else if(i_req_wr_en == 1) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_WRITE;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
endcase
`MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
endcase
`MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
end
endmodule | module readwrite_registers(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code,
o_exposed_mem
); |
parameter [`ADDR_W - 1:0] ADDR_START = 0;
parameter WORD_COUNT = 1;
localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;
localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;
wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];
wire [1:0] s_offset = i_req_addr[1:0];
reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];
genvar j;
generate
for(j = 0; j < WORD_COUNT; j = j + 1) begin: mem_assign
assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];
end
endgenerate
integer i;
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < ADDR_COUNT; i = i + 1) begin
r_mem[i] <= 0;
end
o_res_rd_data <= 0;
o_res_code <= 0;
end else if(i_req_count != `MEM_COUNT_NONE) begin
if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
(i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_MISALIGNED;
end else if(s_addr_aligned > ADDR_END) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;
end else if(i_req_wr_en == 1) begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_WRITE;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
endcase
`MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_READ;
case(i_req_count)
`MEM_COUNT_BYTE:
case(s_offset)
0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
endcase
`MEM_COUNT_HALF:
case(s_offset)
0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
endcase
`MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];
default: o_res_code <= `MEM_CODE_INVALID;
endcase
end
end else begin
o_res_rd_data <= 0;
o_res_code <= `MEM_CODE_INVALID;
end
end
endmodule | 0 |
4,434 | data/full_repos/permissive/109936328/memory_peripheral/timer.v | 109,936,328 | timer.v | v | 154 | 78 | [] | [] | [] | null | line:58: before: "*" | null | 1: b"%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:21: Define or directive not defined: '`ADDR_W'\n parameter [`ADDR_W - 1:0] ADDR_START = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:35: Define or directive not defined: '`ADDR_W'\n input [`ADDR_W - 1:0] i_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:36: Define or directive not defined: '`WORD_W'\n input [`WORD_W - 1:0] i_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:38: Define or directive not defined: '`MEM_COUNT_W'\n input [`MEM_COUNT_W - 1:0] i_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:40: Define or directive not defined: '`WORD_W'\n output reg [`WORD_W - 1:0] o_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:41: Define or directive not defined: '`MEM_CODE_W'\n output reg [`MEM_CODE_W - 1:0] o_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:53: Define or directive not defined: '`WORD_W'\n wire [`WORD_W - 1:0] threshold;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:54: Define or directive not defined: '`WORD_W'\n wire [`WORD_W - 1:0] load_val;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:56: Define or directive not defined: '`WORD_W'\n wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: Define or directive not defined: '`WORD_W'\n assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: Define or directive not defined: '`WORD_W'\n assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: Define or directive not defined: '`WORD_W'\n assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: Define or directive not defined: '`WORD_W'\n assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:67: Define or directive not defined: '`WORD_W'\n reg [`WORD_W - 1:0] count;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:71: Define or directive not defined: '`WORD_W'\n wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:74: Define or directive not defined: '`WORD_W'\n {(`WORD_W - 1){1'b0}}, threshold_trigger \n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:77: Define or directive not defined: '`WORD_W'\n wire [`WORD_W - 1:0] s_rw_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:78: Define or directive not defined: '`MEM_CODE_W'\n wire [`MEM_CODE_W - 1:0] s_rw_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:80: Define or directive not defined: '`WORD_W'\n wire [`WORD_W - 1:0] s_ro_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:81: Define or directive not defined: '`MEM_CODE_W'\n wire [`MEM_CODE_W - 1:0] s_ro_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:139: Define or directive not defined: '`WORD_W'\n wire [`WORD_W - 2 - 1:0] word_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:140: Define or directive not defined: '`WORD_W'\n assign word_addr = i_req_addr[`WORD_W - 1:2];\n ^~~~~~~\n%Error: Exiting due to 24 error(s)\n" | 2,689 | module | module timer(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code
);
parameter [`ADDR_W - 1:0] ADDR_START = 0;
localparam RW_ADDR_START = ADDR_START;
localparam RW_ADDR_COUNT = 12;
localparam RW_ADDR_END = RW_ADDR_START + RW_ADDR_COUNT - 1;
localparam RW_WORD_COUNT = $ceil(RW_ADDR_COUNT / 4);
localparam RO_ADDR_START = RW_ADDR_END;
localparam RO_ADDR_COUNT = 8;
localparam RO_ADDR_END = RO_ADDR_START + RO_ADDR_COUNT - 1;
localparam RO_WORD_COUNT = $ceil(RO_ADDR_COUNT / 4);
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
wire en;
wire backward;
wire load;
wire threshold_en;
wire [`WORD_W - 1:0] threshold;
wire [`WORD_W - 1:0] load_val;
wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;
assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];
assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];
assign threshold_en = s_readwrite_data[0];
assign load = s_readwrite_data[1];
assign backward = s_readwrite_data[2];
assign en = s_readwrite_data[3];
reg [`WORD_W - 1:0] count;
wire threshold_trigger;
wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;
assign s_readonly_data = {
count,
{(`WORD_W - 1){1'b0}}, threshold_trigger
};
wire [`WORD_W - 1:0] s_rw_rd_data;
wire [`MEM_CODE_W - 1:0] s_rw_code;
wire [`WORD_W - 1:0] s_ro_rd_data;
wire [`MEM_CODE_W - 1:0] s_ro_code;
assign threshold_trigger = count == threshold && aresetn == 1 &&
threshold_en == 1;
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
count <= 0;
end else begin
if(load == 1) begin
count <= load_val;
end else if(en == 1) begin
if(backward == 0) begin
count <= count + 1;
end else begin
count <= count - 1;
end
end
end
end
readwrite_registers#(
.ADDR_START(RW_ADDR_START),
.WORD_COUNT(RW_WORD_COUNT)
) rw_reg(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(i_req_addr),
.i_req_wr_data(i_req_wr_data),
.i_req_wr_en(i_req_wr_en),
.i_req_count(i_req_count),
.o_res_rd_data(s_rw_rd_data),
.o_res_code(s_rw_code),
.o_exposed_mem(s_readwrite_data)
);
readonly_registers#(
.ADDR_START(RO_ADDR_START),
.WORD_COUNT(RO_WORD_COUNT)
) ro_reg(
.clk(clk),
.aresetn(aresetn),
.i_registers(s_readonly_data),
.i_req_addr(i_req_addr),
.i_req_count(i_req_count),
.o_res_rd_data(s_ro_rd_data),
.o_res_code(s_ro_code)
);
wire [`WORD_W - 2 - 1:0] word_addr;
assign word_addr = i_req_addr[`WORD_W - 1:2];
always@(*) begin: output_mux
if(word_addr >= RW_ADDR_START && word_addr <= RW_ADDR_END) begin
o_res_rd_data = s_rw_rd_data;
o_res_code = s_rw_code;
end else if(word_addr >= RO_ADDR_START && word_addr <= RO_ADDR_END) begin
o_res_rd_data = s_ro_rd_data;
o_res_code = s_ro_code;
end else begin
o_res_rd_data = 'bz;
o_res_code = 'bz;
end
end
endmodule | module timer(
clk,
aresetn,
i_req_addr,
i_req_wr_data,
i_req_wr_en,
i_req_count,
o_res_rd_data,
o_res_code
); |
parameter [`ADDR_W - 1:0] ADDR_START = 0;
localparam RW_ADDR_START = ADDR_START;
localparam RW_ADDR_COUNT = 12;
localparam RW_ADDR_END = RW_ADDR_START + RW_ADDR_COUNT - 1;
localparam RW_WORD_COUNT = $ceil(RW_ADDR_COUNT / 4);
localparam RO_ADDR_START = RW_ADDR_END;
localparam RO_ADDR_COUNT = 8;
localparam RO_ADDR_END = RO_ADDR_START + RO_ADDR_COUNT - 1;
localparam RO_WORD_COUNT = $ceil(RO_ADDR_COUNT / 4);
input clk;
input aresetn;
input [`ADDR_W - 1:0] i_req_addr;
input [`WORD_W - 1:0] i_req_wr_data;
input i_req_wr_en;
input [`MEM_COUNT_W - 1:0] i_req_count;
output reg [`WORD_W - 1:0] o_res_rd_data;
output reg [`MEM_CODE_W - 1:0] o_res_code;
wire en;
wire backward;
wire load;
wire threshold_en;
wire [`WORD_W - 1:0] threshold;
wire [`WORD_W - 1:0] load_val;
wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;
assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];
assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];
assign threshold_en = s_readwrite_data[0];
assign load = s_readwrite_data[1];
assign backward = s_readwrite_data[2];
assign en = s_readwrite_data[3];
reg [`WORD_W - 1:0] count;
wire threshold_trigger;
wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;
assign s_readonly_data = {
count,
{(`WORD_W - 1){1'b0}}, threshold_trigger
};
wire [`WORD_W - 1:0] s_rw_rd_data;
wire [`MEM_CODE_W - 1:0] s_rw_code;
wire [`WORD_W - 1:0] s_ro_rd_data;
wire [`MEM_CODE_W - 1:0] s_ro_code;
assign threshold_trigger = count == threshold && aresetn == 1 &&
threshold_en == 1;
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
count <= 0;
end else begin
if(load == 1) begin
count <= load_val;
end else if(en == 1) begin
if(backward == 0) begin
count <= count + 1;
end else begin
count <= count - 1;
end
end
end
end
readwrite_registers#(
.ADDR_START(RW_ADDR_START),
.WORD_COUNT(RW_WORD_COUNT)
) rw_reg(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(i_req_addr),
.i_req_wr_data(i_req_wr_data),
.i_req_wr_en(i_req_wr_en),
.i_req_count(i_req_count),
.o_res_rd_data(s_rw_rd_data),
.o_res_code(s_rw_code),
.o_exposed_mem(s_readwrite_data)
);
readonly_registers#(
.ADDR_START(RO_ADDR_START),
.WORD_COUNT(RO_WORD_COUNT)
) ro_reg(
.clk(clk),
.aresetn(aresetn),
.i_registers(s_readonly_data),
.i_req_addr(i_req_addr),
.i_req_count(i_req_count),
.o_res_rd_data(s_ro_rd_data),
.o_res_code(s_ro_code)
);
wire [`WORD_W - 2 - 1:0] word_addr;
assign word_addr = i_req_addr[`WORD_W - 1:2];
always@(*) begin: output_mux
if(word_addr >= RW_ADDR_START && word_addr <= RW_ADDR_END) begin
o_res_rd_data = s_rw_rd_data;
o_res_code = s_rw_code;
end else if(word_addr >= RO_ADDR_START && word_addr <= RO_ADDR_END) begin
o_res_rd_data = s_ro_rd_data;
o_res_code = s_ro_code;
end else begin
o_res_rd_data = 'bz;
o_res_code = 'bz;
end
end
endmodule | 0 |
4,435 | data/full_repos/permissive/109936328/pipeline/ex.v | 109,936,328 | ex.v | v | 217 | 65 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/ex.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:3: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:4: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:50: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:51: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:53: Define or directive not defined: \'`ALU_OP_W\'\n input [`ALU_OP_W - 1:0] i_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:55: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:56: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:57: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:59: Define or directive not defined: \'`MEM_OP_W\'\n input [`MEM_OP_W - 1:0] i_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:61: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:62: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:66: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:67: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:69: Define or directive not defined: \'`ALU_OP_W\'\n reg [`ALU_OP_W - 1:0] r_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:71: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:72: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:73: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:75: Define or directive not defined: \'`MEM_OP_W\'\n reg [`MEM_OP_W - 1:0] r_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:77: Define or directive not defined: \'`DEST_SRC_W\'\n reg [`DEST_SRC_W - 1:0] r_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:78: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] r_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:82: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:85: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:86: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:88: Define or directive not defined: \'`DEST_SRC_W\'\n output [`DEST_SRC_W - 1:0] o_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:89: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:91: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:93: Define or directive not defined: \'`MEM_OP_W\'\n output [`MEM_OP_W - 1:0] o_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:95: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:96: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:98: Define or directive not defined: \'`MEM_COUNT_W\'\n output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:101: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_branch_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:122: Define or directive not defined: \'`ALU_ADD\'\n r_alu_op <= `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n r_alu_op <= `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:128: Define or directive not defined: \'`MEM_OP_NOP\'\n r_mem_op <= `MEM_OP_NOP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n r_mem_op <= `MEM_OP_NOP;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:130: Define or directive not defined: \'`DEST_SRC_NONE\'\n r_dest_src <= `DEST_SRC_NONE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:130: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n r_dest_src <= `DEST_SRC_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:169: Define or directive not defined: \'`MEM_OP_WR_WORD\'\n `MEM_OP_WR_WORD: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:169: syntax error, unexpected \':\', expecting endcase\n `MEM_OP_WR_WORD: begin\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:170: Define or directive not defined: \'`MEM_COUNT_WORD\'\n o_mem_req_count = `MEM_COUNT_WORD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:174: Define or directive not defined: \'`MEM_OP_WR_HALF\'\n `MEM_OP_WR_HALF: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:174: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_OP_WR_HALF: begin\n ^~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:175: Define or directive not defined: \'`MEM_COUNT_HALF\'\n o_mem_req_count = `MEM_COUNT_HALF;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:179: Define or directive not defined: \'`MEM_OP_WR_BYTE\'\n `MEM_OP_WR_BYTE: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:179: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_OP_WR_BYTE: begin\n ^~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:180: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n o_mem_req_count = `MEM_COUNT_BYTE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:184: Define or directive not defined: \'`MEM_OP_RD_WORD\'\n `MEM_OP_RD_WORD: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:184: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_OP_RD_WORD: begin\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,690 | module | module ex(
clk,
clr,
stall,
i_pc,
i_instr,
i_alu_op,
i_alu_data_a,
i_alu_data_b,
i_imm,
i_mem_op,
i_dest_src,
i_dest_reg,
i_branch_op,
o_pc,
o_instr,
o_dest_src,
o_dest_reg,
o_alu_eval,
o_mem_op,
o_mem_req_addr,
o_mem_req_wr_data,
o_mem_req_wr_en,
o_mem_req_count,
o_branch,
o_branch_addr
);
input clk;
input clr;
input stall;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`ALU_OP_W - 1:0] i_alu_op;
input [`WORD_W - 1:0] i_alu_data_a;
input [`WORD_W - 1:0] i_alu_data_b;
input [`WORD_W - 1:0] i_imm;
input [`MEM_OP_W - 1:0] i_mem_op;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input i_branch_op;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`ALU_OP_W - 1:0] r_alu_op;
reg [`WORD_W - 1:0] r_alu_data_a;
reg [`WORD_W - 1:0] r_alu_data_b;
reg [`WORD_W - 1:0] r_imm;
reg [`MEM_OP_W - 1:0] r_mem_op;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg r_branch_op;
wire [`WORD_W - 1:0] s_alu_eval;
wire s_alu_zero;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
output [`WORD_W - 1:0] o_alu_eval;
output [`MEM_OP_W - 1:0] o_mem_op;
output [`ADDR_W - 1:0] o_mem_req_addr;
output [`WORD_W - 1:0] o_mem_req_wr_data;
output reg o_mem_req_wr_en;
output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;
output o_branch;
output [`ADDR_W - 1:0] o_branch_addr;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_src = r_dest_src;
assign o_dest_reg = r_dest_reg;
assign o_alu_eval = s_alu_eval;
assign o_mem_op = r_mem_op;
assign o_branch = s_alu_zero & r_branch_op;
assign o_branch_addr = r_pc + r_imm;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_alu_op <= `ALU_ADD;
r_alu_data_a <= 0;
r_alu_data_b <= 0;
r_imm <= 0;
r_mem_op <= `MEM_OP_NOP;
r_dest_src <= `DEST_SRC_NONE;
r_dest_reg <= 0;
r_branch_op <= 0;
end else if(stall == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
r_alu_op <= i_alu_op;
r_mem_op <= i_mem_op;
r_alu_data_a <= i_alu_data_a;
r_alu_data_b <= i_alu_data_b;
r_imm <= i_imm;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_branch_op <= i_branch_op;
end
end
alu comp(
.opp_a(r_alu_data_a),
.opp_b(r_alu_data_b),
.op(r_alu_op),
.eval(s_alu_eval),
.zero(s_alu_zero)
);
assign o_mem_req_addr = r_imm + r_alu_data_a;
assign o_mem_req_wr_data = r_alu_data_b;
always@(*) begin
case(r_mem_op)
`MEM_OP_WR_WORD: begin
o_mem_req_count = `MEM_COUNT_WORD;
o_mem_req_wr_en = 1;
end
`MEM_OP_WR_HALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 1;
end
`MEM_OP_WR_BYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 1;
end
`MEM_OP_RD_WORD: begin
o_mem_req_count = `MEM_COUNT_WORD;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_HALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_BYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_UHALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_UBYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 0;
end
default: begin
o_mem_req_count = `MEM_COUNT_NONE;
o_mem_req_wr_en = 0;
end
endcase
end
endmodule | module ex(
clk,
clr,
stall,
i_pc,
i_instr,
i_alu_op,
i_alu_data_a,
i_alu_data_b,
i_imm,
i_mem_op,
i_dest_src,
i_dest_reg,
i_branch_op,
o_pc,
o_instr,
o_dest_src,
o_dest_reg,
o_alu_eval,
o_mem_op,
o_mem_req_addr,
o_mem_req_wr_data,
o_mem_req_wr_en,
o_mem_req_count,
o_branch,
o_branch_addr
); |
input clk;
input clr;
input stall;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`ALU_OP_W - 1:0] i_alu_op;
input [`WORD_W - 1:0] i_alu_data_a;
input [`WORD_W - 1:0] i_alu_data_b;
input [`WORD_W - 1:0] i_imm;
input [`MEM_OP_W - 1:0] i_mem_op;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input i_branch_op;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`ALU_OP_W - 1:0] r_alu_op;
reg [`WORD_W - 1:0] r_alu_data_a;
reg [`WORD_W - 1:0] r_alu_data_b;
reg [`WORD_W - 1:0] r_imm;
reg [`MEM_OP_W - 1:0] r_mem_op;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg r_branch_op;
wire [`WORD_W - 1:0] s_alu_eval;
wire s_alu_zero;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
output [`WORD_W - 1:0] o_alu_eval;
output [`MEM_OP_W - 1:0] o_mem_op;
output [`ADDR_W - 1:0] o_mem_req_addr;
output [`WORD_W - 1:0] o_mem_req_wr_data;
output reg o_mem_req_wr_en;
output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;
output o_branch;
output [`ADDR_W - 1:0] o_branch_addr;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_src = r_dest_src;
assign o_dest_reg = r_dest_reg;
assign o_alu_eval = s_alu_eval;
assign o_mem_op = r_mem_op;
assign o_branch = s_alu_zero & r_branch_op;
assign o_branch_addr = r_pc + r_imm;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_alu_op <= `ALU_ADD;
r_alu_data_a <= 0;
r_alu_data_b <= 0;
r_imm <= 0;
r_mem_op <= `MEM_OP_NOP;
r_dest_src <= `DEST_SRC_NONE;
r_dest_reg <= 0;
r_branch_op <= 0;
end else if(stall == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
r_alu_op <= i_alu_op;
r_mem_op <= i_mem_op;
r_alu_data_a <= i_alu_data_a;
r_alu_data_b <= i_alu_data_b;
r_imm <= i_imm;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_branch_op <= i_branch_op;
end
end
alu comp(
.opp_a(r_alu_data_a),
.opp_b(r_alu_data_b),
.op(r_alu_op),
.eval(s_alu_eval),
.zero(s_alu_zero)
);
assign o_mem_req_addr = r_imm + r_alu_data_a;
assign o_mem_req_wr_data = r_alu_data_b;
always@(*) begin
case(r_mem_op)
`MEM_OP_WR_WORD: begin
o_mem_req_count = `MEM_COUNT_WORD;
o_mem_req_wr_en = 1;
end
`MEM_OP_WR_HALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 1;
end
`MEM_OP_WR_BYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 1;
end
`MEM_OP_RD_WORD: begin
o_mem_req_count = `MEM_COUNT_WORD;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_HALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_BYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_UHALF: begin
o_mem_req_count = `MEM_COUNT_HALF;
o_mem_req_wr_en = 0;
end
`MEM_OP_RD_UBYTE: begin
o_mem_req_count = `MEM_COUNT_BYTE;
o_mem_req_wr_en = 0;
end
default: begin
o_mem_req_count = `MEM_COUNT_NONE;
o_mem_req_wr_en = 0;
end
endcase
end
endmodule | 0 |
4,436 | data/full_repos/permissive/109936328/pipeline/fe.v | 109,936,328 | fe.v | v | 43 | 49 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/fe.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:20: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_branch_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:22: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W -1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:25: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:32: Define or directive not defined: \'`INSTR_W\'\n r_pc <= i_branch_addr + `INSTR_W / 8;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:32: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n r_pc <= i_branch_addr + `INSTR_W / 8;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:34: Define or directive not defined: \'`INSTR_W\'\n r_pc <= r_pc + `INSTR_W / 8;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:34: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n r_pc <= r_pc + `INSTR_W / 8;\n ^\n%Error: Exiting due to 8 error(s)\n' | 2,691 | module | module fe(
clk,
clr,
stall,
i_branch,
i_branch_addr,
o_pc,
o_instr_req
);
input clk;
input clr;
input stall;
input i_branch;
input [`ADDR_W - 1:0] i_branch_addr;
output [`ADDR_W -1:0] o_pc;
output o_instr_req;
reg [`ADDR_W - 1:0] r_pc;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
end else if(stall == 0) begin
if (i_branch == 1) begin
r_pc <= i_branch_addr + `INSTR_W / 8;
end else begin
r_pc <= r_pc + `INSTR_W / 8;
end
end
end
assign o_pc = i_branch ? i_branch_addr : r_pc;
assign o_instr_req = ~clr;
endmodule | module fe(
clk,
clr,
stall,
i_branch,
i_branch_addr,
o_pc,
o_instr_req
); |
input clk;
input clr;
input stall;
input i_branch;
input [`ADDR_W - 1:0] i_branch_addr;
output [`ADDR_W -1:0] o_pc;
output o_instr_req;
reg [`ADDR_W - 1:0] r_pc;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
end else if(stall == 0) begin
if (i_branch == 1) begin
r_pc <= i_branch_addr + `INSTR_W / 8;
end else begin
r_pc <= r_pc + `INSTR_W / 8;
end
end
end
assign o_pc = i_branch ? i_branch_addr : r_pc;
assign o_instr_req = ~clr;
endmodule | 0 |
4,437 | data/full_repos/permissive/109936328/pipeline/id.v | 109,936,328 | id.v | v | 279 | 70 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:70: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:71: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:73: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] s_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:75: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_ex_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:76: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_ex_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:77: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_ex_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:79: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_me_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:81: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:85: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:86: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:89: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:90: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:93: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:94: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:97: Define or directive not defined: \'`ALU_OP_W\'\n output [`ALU_OP_W - 1:0] o_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:100: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:101: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:103: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:105: Define or directive not defined: \'`MEM_OP_W\'\n output [`MEM_OP_W - 1:0] o_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:110: Define or directive not defined: \'`DEST_SRC_W\'\n output [`DEST_SRC_W - 1:0] o_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:111: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:112: Define or directive not defined: \'`INSTR_XPR_DEST\'\n assign o_dest_reg = `INSTR_XPR_DEST(s_instr);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:117: Define or directive not defined: \'`ALU_SRC_A_W\'\n wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:118: Define or directive not defined: \'`ALU_SRC_B_W\'\n wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:120: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] s_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:121: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] s_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`INSTR_XPR_A\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:126: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`INSTR_XPR_B\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:128: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:133: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_temp_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:134: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_temp_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: Define or directive not defined: \'`MEM_OP_NOP\'\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: Define or directive not defined: \'`DEST_SRC_NONE\'\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:212: Define or directive not defined: \'`WORD_W\'\n function [`WORD_W - 1:0] fwd_alu_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:213: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:214: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] reg_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: Define or directive not defined: \'`DEST_SRC_ALU\'\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:221: Define or directive not defined: \'`DEST_SRC_NONE\'\n i_me_dest_src != `DEST_SRC_NONE) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:236: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:239: Define or directive not defined: \'`DEST_SRC_MEM\'\n i_ex_dest_src == `DEST_SRC_MEM) begin\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,692 | module | module id(
clk,
clr,
stall,
rf_reset,
i_pc,
i_instr,
i_ex_alu_eval,
i_ex_dest_reg,
i_ex_dest_src,
i_me_dest_reg,
i_me_dest_src,
i_me_dest_data,
i_wb_dest_en,
i_wb_dest_reg,
i_wb_dest_data,
o_pc,
o_instr,
o_alu_op,
o_alu_data_a,
o_alu_data_b,
o_imm,
o_mem_op,
o_dest_src,
o_dest_reg,
o_branch_op,
o_mem_hazard
);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input clr;
input stall;
input rf_reset;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
wire [`INSTR_W - 1:0] s_instr;
input [`REG_IDX_W - 1:0] i_ex_dest_reg;
input [`DEST_SRC_W - 1:0] i_ex_dest_src;
input [`WORD_W - 1:0] i_ex_alu_eval;
input [`REG_IDX_W - 1:0] i_me_dest_reg;
input [`DEST_SRC_W - 1:0] i_me_dest_src;
input [`WORD_W - 1:0] i_me_dest_data;
input i_wb_dest_en;
input [`REG_IDX_W - 1:0] i_wb_dest_reg;
input [`WORD_W - 1:0] i_wb_dest_data;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
output [`ALU_OP_W - 1:0] o_alu_op;
output reg[`WORD_W - 1:0] o_alu_data_a;
output reg[`WORD_W - 1:0] o_alu_data_b;
output [`WORD_W - 1:0] o_imm;
output [`MEM_OP_W - 1:0] o_mem_op;
output o_branch_op;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
assign o_dest_reg = `INSTR_XPR_DEST(s_instr);
output o_mem_hazard;
wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;
wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;
wire [`MEM_OP_W - 1:0] s_mem_op;
wire [`DEST_SRC_W - 1:0] s_dest_src;
wire s_branch_op;
wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);
wire [`WORD_W - 1:0] s_reg_data_a;
wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);
wire [`WORD_W - 1:0] s_reg_data_b;
reg s_mem_hazard_reg_a;
reg s_mem_hazard_reg_b;
reg [`ADDR_W - 1:0] r_temp_pc;
reg [`INSTR_W - 1:0] r_temp_instr;
reg r_temp_valid;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_temp_valid <= 0;
end else begin
if(r_temp_valid == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
end
if(stall == 1) begin
r_temp_pc <= r_pc;
r_temp_instr <= r_instr;
end
r_temp_valid <= stall;
end
end
assign o_pc = (~stall & r_temp_valid) ? r_temp_pc : r_pc;
assign o_instr = (~stall & r_temp_valid) ? r_temp_instr : r_instr;
assign s_instr = o_instr;
assign o_mem_hazard = s_mem_hazard_reg_a | s_mem_hazard_reg_b;
assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;
assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;
assign o_branch_op = ~stall & s_branch_op;
id_decoder dec(
.instr(s_instr),
.alu_op(o_alu_op),
.imm(o_imm),
.mem_op(s_mem_op),
.alu_a_src(s_alu_src_a),
.alu_b_src(s_alu_src_b),
.dest_src(s_dest_src),
.branch_op(s_branch_op)
);
register_file#(
.DUMP_VARS(DUMP_VARS),
.DUMP_FILE(DUMP_FILE)
) rf(
.clk(clk),
.aresetn(rf_reset),
.rd_reg_a(s_reg_a),
.rd_reg_b(s_reg_b),
.rd_data_a(s_reg_data_a),
.rd_data_b(s_reg_data_b),
.wr_en(i_wb_dest_en),
.wr_reg(i_wb_dest_reg),
.wr_data(i_wb_dest_data)
);
function [`WORD_W - 1:0] fwd_alu_data;
input [`REG_IDX_W - 1:0] reg_num;
input [`WORD_W - 1:0] reg_data;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_ALU) begin
fwd_alu_data = i_ex_alu_eval;
end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
i_me_dest_src != `DEST_SRC_NONE) begin
fwd_alu_data = i_me_dest_data;
end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
i_wb_dest_en == 1) begin
fwd_alu_data = i_wb_dest_data;
end else begin
fwd_alu_data = reg_data;
end
end
endfunction
function mem_hazard_stall;
input [`REG_IDX_W - 1:0] reg_num;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_MEM) begin
mem_hazard_stall = 1;
end else begin
mem_hazard_stall = 0;
end
end
endfunction
always@(s_reg_a, s_reg_data_a, s_reg_b, s_reg_data_b,
i_ex_alu_eval, i_ex_dest_reg, i_ex_dest_src,
i_me_dest_data, i_me_dest_reg, i_me_dest_src,
i_wb_dest_data, i_wb_dest_reg, i_wb_dest_en,
r_pc, o_imm) begin
s_mem_hazard_reg_a = 0;
case(s_alu_src_a)
`ALU_SRC_A_XPR: begin
o_alu_data_a = fwd_alu_data(s_reg_a, s_reg_data_a);
s_mem_hazard_reg_a = mem_hazard_stall(s_reg_a);
end
`ALU_SRC_A_PC: o_alu_data_a = r_pc;
`ALU_SRC_A_NONE: o_alu_data_a = 0;
default: o_alu_data_a = 0;
endcase
s_mem_hazard_reg_b = 0;
case(s_alu_src_b)
`ALU_SRC_B_XPR: begin
o_alu_data_b = fwd_alu_data(s_reg_b, s_reg_data_b);
s_mem_hazard_reg_b = mem_hazard_stall(s_reg_b);
end
`ALU_SRC_B_IMM: o_alu_data_b = o_imm;
`ALU_SRC_B_INSTR_SIZE: o_alu_data_b = `INSTR_W / 8;
`ALU_SRC_B_NONE: o_alu_data_b = 0;
default: o_alu_data_b = 0;
endcase
end
endmodule | module id(
clk,
clr,
stall,
rf_reset,
i_pc,
i_instr,
i_ex_alu_eval,
i_ex_dest_reg,
i_ex_dest_src,
i_me_dest_reg,
i_me_dest_src,
i_me_dest_data,
i_wb_dest_en,
i_wb_dest_reg,
i_wb_dest_data,
o_pc,
o_instr,
o_alu_op,
o_alu_data_a,
o_alu_data_b,
o_imm,
o_mem_op,
o_dest_src,
o_dest_reg,
o_branch_op,
o_mem_hazard
); |
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input clr;
input stall;
input rf_reset;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
wire [`INSTR_W - 1:0] s_instr;
input [`REG_IDX_W - 1:0] i_ex_dest_reg;
input [`DEST_SRC_W - 1:0] i_ex_dest_src;
input [`WORD_W - 1:0] i_ex_alu_eval;
input [`REG_IDX_W - 1:0] i_me_dest_reg;
input [`DEST_SRC_W - 1:0] i_me_dest_src;
input [`WORD_W - 1:0] i_me_dest_data;
input i_wb_dest_en;
input [`REG_IDX_W - 1:0] i_wb_dest_reg;
input [`WORD_W - 1:0] i_wb_dest_data;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
output [`ALU_OP_W - 1:0] o_alu_op;
output reg[`WORD_W - 1:0] o_alu_data_a;
output reg[`WORD_W - 1:0] o_alu_data_b;
output [`WORD_W - 1:0] o_imm;
output [`MEM_OP_W - 1:0] o_mem_op;
output o_branch_op;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
assign o_dest_reg = `INSTR_XPR_DEST(s_instr);
output o_mem_hazard;
wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;
wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;
wire [`MEM_OP_W - 1:0] s_mem_op;
wire [`DEST_SRC_W - 1:0] s_dest_src;
wire s_branch_op;
wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);
wire [`WORD_W - 1:0] s_reg_data_a;
wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);
wire [`WORD_W - 1:0] s_reg_data_b;
reg s_mem_hazard_reg_a;
reg s_mem_hazard_reg_b;
reg [`ADDR_W - 1:0] r_temp_pc;
reg [`INSTR_W - 1:0] r_temp_instr;
reg r_temp_valid;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_temp_valid <= 0;
end else begin
if(r_temp_valid == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
end
if(stall == 1) begin
r_temp_pc <= r_pc;
r_temp_instr <= r_instr;
end
r_temp_valid <= stall;
end
end
assign o_pc = (~stall & r_temp_valid) ? r_temp_pc : r_pc;
assign o_instr = (~stall & r_temp_valid) ? r_temp_instr : r_instr;
assign s_instr = o_instr;
assign o_mem_hazard = s_mem_hazard_reg_a | s_mem_hazard_reg_b;
assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;
assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;
assign o_branch_op = ~stall & s_branch_op;
id_decoder dec(
.instr(s_instr),
.alu_op(o_alu_op),
.imm(o_imm),
.mem_op(s_mem_op),
.alu_a_src(s_alu_src_a),
.alu_b_src(s_alu_src_b),
.dest_src(s_dest_src),
.branch_op(s_branch_op)
);
register_file#(
.DUMP_VARS(DUMP_VARS),
.DUMP_FILE(DUMP_FILE)
) rf(
.clk(clk),
.aresetn(rf_reset),
.rd_reg_a(s_reg_a),
.rd_reg_b(s_reg_b),
.rd_data_a(s_reg_data_a),
.rd_data_b(s_reg_data_b),
.wr_en(i_wb_dest_en),
.wr_reg(i_wb_dest_reg),
.wr_data(i_wb_dest_data)
);
function [`WORD_W - 1:0] fwd_alu_data;
input [`REG_IDX_W - 1:0] reg_num;
input [`WORD_W - 1:0] reg_data;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_ALU) begin
fwd_alu_data = i_ex_alu_eval;
end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
i_me_dest_src != `DEST_SRC_NONE) begin
fwd_alu_data = i_me_dest_data;
end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
i_wb_dest_en == 1) begin
fwd_alu_data = i_wb_dest_data;
end else begin
fwd_alu_data = reg_data;
end
end
endfunction
function mem_hazard_stall;
input [`REG_IDX_W - 1:0] reg_num;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_MEM) begin
mem_hazard_stall = 1;
end else begin
mem_hazard_stall = 0;
end
end
endfunction
always@(s_reg_a, s_reg_data_a, s_reg_b, s_reg_data_b,
i_ex_alu_eval, i_ex_dest_reg, i_ex_dest_src,
i_me_dest_data, i_me_dest_reg, i_me_dest_src,
i_wb_dest_data, i_wb_dest_reg, i_wb_dest_en,
r_pc, o_imm) begin
s_mem_hazard_reg_a = 0;
case(s_alu_src_a)
`ALU_SRC_A_XPR: begin
o_alu_data_a = fwd_alu_data(s_reg_a, s_reg_data_a);
s_mem_hazard_reg_a = mem_hazard_stall(s_reg_a);
end
`ALU_SRC_A_PC: o_alu_data_a = r_pc;
`ALU_SRC_A_NONE: o_alu_data_a = 0;
default: o_alu_data_a = 0;
endcase
s_mem_hazard_reg_b = 0;
case(s_alu_src_b)
`ALU_SRC_B_XPR: begin
o_alu_data_b = fwd_alu_data(s_reg_b, s_reg_data_b);
s_mem_hazard_reg_b = mem_hazard_stall(s_reg_b);
end
`ALU_SRC_B_IMM: o_alu_data_b = o_imm;
`ALU_SRC_B_INSTR_SIZE: o_alu_data_b = `INSTR_W / 8;
`ALU_SRC_B_NONE: o_alu_data_b = 0;
default: o_alu_data_b = 0;
endcase
end
endmodule | 0 |
4,438 | data/full_repos/permissive/109936328/pipeline/id.v | 109,936,328 | id.v | v | 279 | 70 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:70: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:71: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:73: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] s_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:75: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_ex_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:76: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_ex_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:77: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_ex_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:79: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_me_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:81: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:85: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:86: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:89: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:90: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:93: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:94: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:97: Define or directive not defined: \'`ALU_OP_W\'\n output [`ALU_OP_W - 1:0] o_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:100: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:101: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:103: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:105: Define or directive not defined: \'`MEM_OP_W\'\n output [`MEM_OP_W - 1:0] o_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:110: Define or directive not defined: \'`DEST_SRC_W\'\n output [`DEST_SRC_W - 1:0] o_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:111: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:112: Define or directive not defined: \'`INSTR_XPR_DEST\'\n assign o_dest_reg = `INSTR_XPR_DEST(s_instr);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:117: Define or directive not defined: \'`ALU_SRC_A_W\'\n wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:118: Define or directive not defined: \'`ALU_SRC_B_W\'\n wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:120: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] s_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:121: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] s_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`INSTR_XPR_A\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:126: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`INSTR_XPR_B\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:128: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:133: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_temp_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:134: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_temp_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: Define or directive not defined: \'`MEM_OP_NOP\'\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: Define or directive not defined: \'`DEST_SRC_NONE\'\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:212: Define or directive not defined: \'`WORD_W\'\n function [`WORD_W - 1:0] fwd_alu_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:213: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:214: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] reg_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: Define or directive not defined: \'`DEST_SRC_ALU\'\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:221: Define or directive not defined: \'`DEST_SRC_NONE\'\n i_me_dest_src != `DEST_SRC_NONE) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:236: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:239: Define or directive not defined: \'`DEST_SRC_MEM\'\n i_ex_dest_src == `DEST_SRC_MEM) begin\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,692 | function | function [`WORD_W - 1:0] fwd_alu_data;
input [`REG_IDX_W - 1:0] reg_num;
input [`WORD_W - 1:0] reg_data;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_ALU) begin
fwd_alu_data = i_ex_alu_eval;
end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
i_me_dest_src != `DEST_SRC_NONE) begin
fwd_alu_data = i_me_dest_data;
end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
i_wb_dest_en == 1) begin
fwd_alu_data = i_wb_dest_data;
end else begin
fwd_alu_data = reg_data;
end
end
endfunction | function [`WORD_W - 1:0] fwd_alu_data; |
input [`REG_IDX_W - 1:0] reg_num;
input [`WORD_W - 1:0] reg_data;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_ALU) begin
fwd_alu_data = i_ex_alu_eval;
end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
i_me_dest_src != `DEST_SRC_NONE) begin
fwd_alu_data = i_me_dest_data;
end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
i_wb_dest_en == 1) begin
fwd_alu_data = i_wb_dest_data;
end else begin
fwd_alu_data = reg_data;
end
end
endfunction | 0 |
4,439 | data/full_repos/permissive/109936328/pipeline/id.v | 109,936,328 | id.v | v | 279 | 70 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:70: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:71: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:73: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] s_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:75: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_ex_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:76: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_ex_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:77: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_ex_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:79: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_me_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:81: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:85: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:86: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:89: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:90: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:93: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:94: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:97: Define or directive not defined: \'`ALU_OP_W\'\n output [`ALU_OP_W - 1:0] o_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:100: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:101: Define or directive not defined: \'`WORD_W\'\n output reg[`WORD_W - 1:0] o_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:103: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:105: Define or directive not defined: \'`MEM_OP_W\'\n output [`MEM_OP_W - 1:0] o_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:110: Define or directive not defined: \'`DEST_SRC_W\'\n output [`DEST_SRC_W - 1:0] o_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:111: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:112: Define or directive not defined: \'`INSTR_XPR_DEST\'\n assign o_dest_reg = `INSTR_XPR_DEST(s_instr);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:117: Define or directive not defined: \'`ALU_SRC_A_W\'\n wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:118: Define or directive not defined: \'`ALU_SRC_B_W\'\n wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:120: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] s_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:121: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] s_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`INSTR_XPR_A\'\n wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:126: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`INSTR_XPR_B\'\n wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:128: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] s_reg_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:133: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_temp_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:134: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_temp_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: Define or directive not defined: \'`MEM_OP_NOP\'\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: Define or directive not defined: \'`DEST_SRC_NONE\'\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:212: Define or directive not defined: \'`WORD_W\'\n function [`WORD_W - 1:0] fwd_alu_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:213: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:214: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] reg_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: Define or directive not defined: \'`DEST_SRC_ALU\'\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n i_ex_dest_src == `DEST_SRC_ALU) begin\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:221: Define or directive not defined: \'`DEST_SRC_NONE\'\n i_me_dest_src != `DEST_SRC_NONE) begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:236: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] reg_num;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:239: Define or directive not defined: \'`DEST_SRC_MEM\'\n i_ex_dest_src == `DEST_SRC_MEM) begin\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,692 | function | function mem_hazard_stall;
input [`REG_IDX_W - 1:0] reg_num;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_MEM) begin
mem_hazard_stall = 1;
end else begin
mem_hazard_stall = 0;
end
end
endfunction | function mem_hazard_stall; |
input [`REG_IDX_W - 1:0] reg_num;
begin
if(reg_num != 0 && reg_num == i_ex_dest_reg &&
i_ex_dest_src == `DEST_SRC_MEM) begin
mem_hazard_stall = 1;
end else begin
mem_hazard_stall = 0;
end
end
endfunction | 0 |
4,440 | data/full_repos/permissive/109936328/pipeline/me.v | 109,936,328 | me.v | v | 109 | 75 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/me.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:32: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:33: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:35: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:36: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:38: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:39: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_mem_read;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:41: Define or directive not defined: \'`MEM_OP_W\'\n input [`MEM_OP_W -1:0] i_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:43: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:44: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:46: Define or directive not defined: \'`DEST_SRC_W\'\n reg [`DEST_SRC_W - 1:0] r_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:47: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] r_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:49: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:50: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_mem_read;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:51: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] s_final_mem_read;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:53: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:54: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:56: Define or directive not defined: \'`DEST_SRC_W\'\n output [`DEST_SRC_W - 1:0] o_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:57: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:59: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: Define or directive not defined: \'`MEM_OP_RD_UBYTE\'\n if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n ^~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: Define or directive not defined: \'`MEM_OP_RD_UHALF\'\n if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:100: Define or directive not defined: \'`DEST_SRC_NONE\'\n `DEST_SRC_NONE: o_dest_data = 0;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:101: Define or directive not defined: \'`DEST_SRC_ALU\'\n `DEST_SRC_ALU: o_dest_data = r_alu_eval;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:102: Define or directive not defined: \'`DEST_SRC_MEM\'\n `DEST_SRC_MEM: o_dest_data = s_final_mem_read;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:103: Define or directive not defined: \'`DEST_SRC_PC4\'\n `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:103: Define or directive not defined: \'`INSTR_W\'\n `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;\n ^~~~~~~~\n%Error: Cannot continue\n' | 2,693 | module | module me(
clk,
clr,
stall,
i_pc,
i_instr,
i_dest_src,
i_dest_reg,
i_alu_eval,
i_mem_read,
i_mem_op,
o_pc,
o_instr,
o_dest_src,
o_dest_reg,
o_dest_data
);
input clk;
input clr;
input stall;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input [`WORD_W - 1:0] i_alu_eval;
input [`WORD_W - 1:0] i_mem_read;
input [`MEM_OP_W -1:0] i_mem_op;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg [`WORD_W - 1:0] r_alu_eval;
reg [`WORD_W - 1:0] r_mem_read;
reg [`WORD_W - 1:0] s_final_mem_read;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
output reg [`WORD_W - 1:0] o_dest_data;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_src = r_dest_src;
assign o_dest_reg = r_dest_reg;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_dest_src <= 0;
r_dest_reg <= 0;
r_alu_eval <= 0;
r_mem_read <= 0;
end else if(stall == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_alu_eval <= i_alu_eval;
r_mem_read <= i_mem_read;
end
end
always@(*) begin
if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin
s_final_mem_read = i_mem_read;
end else begin
s_final_mem_read = $signed(i_mem_read);
end
case(r_dest_src)
`DEST_SRC_NONE: o_dest_data = 0;
`DEST_SRC_ALU: o_dest_data = r_alu_eval;
`DEST_SRC_MEM: o_dest_data = s_final_mem_read;
`DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;
default: o_dest_data = 0;
endcase
end
endmodule | module me(
clk,
clr,
stall,
i_pc,
i_instr,
i_dest_src,
i_dest_reg,
i_alu_eval,
i_mem_read,
i_mem_op,
o_pc,
o_instr,
o_dest_src,
o_dest_reg,
o_dest_data
); |
input clk;
input clr;
input stall;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input [`WORD_W - 1:0] i_alu_eval;
input [`WORD_W - 1:0] i_mem_read;
input [`MEM_OP_W -1:0] i_mem_op;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg [`WORD_W - 1:0] r_alu_eval;
reg [`WORD_W - 1:0] r_mem_read;
reg [`WORD_W - 1:0] s_final_mem_read;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output [`DEST_SRC_W - 1:0] o_dest_src;
output [`REG_IDX_W - 1:0] o_dest_reg;
output reg [`WORD_W - 1:0] o_dest_data;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_src = r_dest_src;
assign o_dest_reg = r_dest_reg;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_dest_src <= 0;
r_dest_reg <= 0;
r_alu_eval <= 0;
r_mem_read <= 0;
end else if(stall == 0) begin
r_pc <= i_pc;
r_instr <= i_instr;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_alu_eval <= i_alu_eval;
r_mem_read <= i_mem_read;
end
end
always@(*) begin
if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin
s_final_mem_read = i_mem_read;
end else begin
s_final_mem_read = $signed(i_mem_read);
end
case(r_dest_src)
`DEST_SRC_NONE: o_dest_data = 0;
`DEST_SRC_ALU: o_dest_data = r_alu_eval;
`DEST_SRC_MEM: o_dest_data = s_final_mem_read;
`DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;
default: o_dest_data = 0;
endcase
end
endmodule | 0 |
4,441 | data/full_repos/permissive/109936328/pipeline/pipeline.v | 109,936,328 | pipeline.v | v | 249 | 47 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:4: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:31: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_instr_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:33: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_instr_res_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:35: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:36: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:38: Define or directive not defined: \'`MEM_COUNT_W\'\n output [`MEM_COUNT_W - 1:0] o_mem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:40: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_mem_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:41: Define or directive not defined: \'`MEM_CODE_W\'\n input [`MEM_CODE_W - 1:0] i_mem_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:47: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] fe_branch_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:48: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] fe_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:53: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] id_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:54: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] id_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:55: Define or directive not defined: \'`ALU_OP_W\'\n wire [`ALU_OP_W - 1:0] id_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:56: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:57: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:58: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:59: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] id_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:60: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] id_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:61: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] id_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:68: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] ex_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:69: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] ex_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:70: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] ex_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:71: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] ex_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:72: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] ex_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:73: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] ex_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:78: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] me_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:79: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] me_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] me_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:81: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:82: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:88: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:89: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/pipeline.v:117: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] fe_pc_delay;\n ^~~~~~~\n%Error: Exiting due to 36 error(s)\n' | 2,694 | module | module pipeline(
clk,
resetn,
aresetn,
o_instr_req_addr,
o_instr_req_en,
i_instr_res_data,
o_mem_req_addr,
o_mem_req_wr_data,
o_mem_req_wr_en,
o_mem_req_count,
i_mem_res_rd_data,
i_mem_res_code
);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input resetn;
input aresetn;
output [`ADDR_W - 1:0] o_instr_req_addr;
output o_instr_req_en;
input [`WORD_W - 1:0] i_instr_res_data;
output [`ADDR_W - 1:0] o_mem_req_addr;
output [`WORD_W - 1:0] o_mem_req_wr_data;
output o_mem_req_wr_en;
output [`MEM_COUNT_W - 1:0] o_mem_req_count;
input [`WORD_W - 1:0] i_mem_res_rd_data;
input [`MEM_CODE_W - 1:0] i_mem_res_code;
wire fe_clr;
wire fe_stall;
wire fe_branch;
wire [`ADDR_W - 1:0] fe_branch_addr;
wire [`ADDR_W - 1:0] fe_pc;
wire id_clr;
wire id_stall;
wire [`ADDR_W - 1:0] id_pc;
wire [`INSTR_W - 1:0] id_instr;
wire [`ALU_OP_W - 1:0] id_alu_op;
wire [`WORD_W - 1:0] id_alu_data_a;
wire [`WORD_W - 1:0] id_alu_data_b;
wire [`WORD_W - 1:0] id_imm;
wire [`MEM_OP_W - 1:0] id_mem_op;
wire [`DEST_SRC_W - 1:0] id_dest_src;
wire [`REG_IDX_W - 1:0] id_dest_reg;
wire id_branch_op;
wire id_mem_hazard;
wire ex_clr;
wire ex_stall;
wire [`ADDR_W - 1:0] ex_pc;
wire [`INSTR_W - 1:0] ex_instr;
wire [`WORD_W - 1:0] ex_alu_eval;
wire [`DEST_SRC_W - 1:0] ex_dest_src;
wire [`REG_IDX_W - 1:0] ex_dest_reg;
wire [`MEM_OP_W - 1:0] ex_mem_op;
wire me_clr;
wire me_stall;
wire [`ADDR_W - 1:0] me_pc;
wire [`INSTR_W - 1:0] me_instr;
wire [`DEST_SRC_W - 1:0] me_dest_src;
wire [`REG_IDX_W - 1:0] me_dest_reg;
wire [`WORD_W - 1:0] me_dest_data;
wire wb_clr;
wire wb_stall;
wire wb_dest_en;
wire [`REG_IDX_W - 1:0] wb_dest_reg;
wire [`WORD_W - 1:0] wb_dest_data;
assign fe_clr = ~resetn;
assign id_clr = ~resetn | fe_branch;
assign ex_clr = ~resetn | fe_branch;
assign me_clr = ~resetn;
assign wb_clr = ~resetn;
assign fe_stall = id_mem_hazard;
assign id_stall = id_mem_hazard;
assign ex_stall = 0;
assign me_stall = 0;
assign wb_stall = 0;
assign o_instr_req_addr = fe_pc;
fe p0(
.clk(clk),
.clr(fe_clr),
.stall(fe_stall),
.i_branch(fe_branch),
.i_branch_addr(fe_branch_addr),
.o_pc(fe_pc),
.o_instr_req(o_instr_req_en)
);
reg [`ADDR_W - 1:0] fe_pc_delay;
always@(posedge clk) begin
fe_pc_delay <= fe_pc;
end
id#(
.DUMP_VARS(DUMP_VARS),
.DUMP_FILE(DUMP_FILE)
) p1(
.clk(clk),
.clr(id_clr),
.stall(id_stall),
.rf_reset(aresetn),
.i_pc(fe_pc_delay),
.i_instr(i_instr_res_data),
.i_ex_dest_reg(ex_dest_reg),
.i_ex_dest_src(ex_dest_src),
.i_ex_alu_eval(ex_alu_eval),
.i_me_dest_reg(me_dest_reg),
.i_me_dest_src(me_dest_src),
.i_me_dest_data(me_dest_data),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(id_pc),
.o_instr(id_instr),
.o_alu_op(id_alu_op),
.o_alu_data_a(id_alu_data_a),
.o_alu_data_b(id_alu_data_b),
.o_imm(id_imm),
.o_mem_op(id_mem_op),
.o_dest_src(id_dest_src),
.o_dest_reg(id_dest_reg),
.o_branch_op(id_branch_op),
.o_mem_hazard(id_mem_hazard)
);
ex p2(
.clk(clk),
.clr(ex_clr),
.stall(ex_stall),
.i_pc(id_pc),
.i_instr(id_instr),
.i_alu_op(id_alu_op),
.i_alu_data_a(id_alu_data_a),
.i_alu_data_b(id_alu_data_b),
.i_imm(id_imm),
.i_mem_op(id_mem_op),
.i_dest_src(id_dest_src),
.i_dest_reg(id_dest_reg),
.i_branch_op(id_branch_op),
.o_pc(ex_pc),
.o_instr(ex_instr),
.o_dest_src(ex_dest_src),
.o_dest_reg(ex_dest_reg),
.o_alu_eval(ex_alu_eval),
.o_mem_op(ex_mem_op),
.o_mem_req_addr(o_mem_req_addr),
.o_mem_req_wr_data(o_mem_req_wr_data),
.o_mem_req_wr_en(o_mem_req_wr_en),
.o_mem_req_count(o_mem_req_count),
.o_branch(fe_branch),
.o_branch_addr(fe_branch_addr)
);
me p3(
.clk(clk),
.clr(me_clr),
.stall(me_stall),
.i_pc(ex_pc),
.i_instr(ex_instr),
.i_dest_src(ex_dest_src),
.i_dest_reg(ex_dest_reg),
.i_alu_eval(ex_alu_eval),
.i_mem_read(i_mem_res_rd_data),
.i_mem_op(ex_mem_op),
.o_pc(me_pc),
.o_instr(me_instr),
.o_dest_src(me_dest_src),
.o_dest_reg(me_dest_reg),
.o_dest_data(me_dest_data)
);
wb p4(
.clk(clk),
.clr(wb_clr),
.i_pc(me_pc),
.i_instr(me_instr),
.i_dest_src(me_dest_src),
.i_dest_reg(me_dest_reg),
.i_dest_data(me_dest_data),
.o_dest_en(wb_dest_en),
.o_dest_reg(wb_dest_reg),
.o_dest_data(wb_dest_data)
);
endmodule | module pipeline(
clk,
resetn,
aresetn,
o_instr_req_addr,
o_instr_req_en,
i_instr_res_data,
o_mem_req_addr,
o_mem_req_wr_data,
o_mem_req_wr_en,
o_mem_req_count,
i_mem_res_rd_data,
i_mem_res_code
); |
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input resetn;
input aresetn;
output [`ADDR_W - 1:0] o_instr_req_addr;
output o_instr_req_en;
input [`WORD_W - 1:0] i_instr_res_data;
output [`ADDR_W - 1:0] o_mem_req_addr;
output [`WORD_W - 1:0] o_mem_req_wr_data;
output o_mem_req_wr_en;
output [`MEM_COUNT_W - 1:0] o_mem_req_count;
input [`WORD_W - 1:0] i_mem_res_rd_data;
input [`MEM_CODE_W - 1:0] i_mem_res_code;
wire fe_clr;
wire fe_stall;
wire fe_branch;
wire [`ADDR_W - 1:0] fe_branch_addr;
wire [`ADDR_W - 1:0] fe_pc;
wire id_clr;
wire id_stall;
wire [`ADDR_W - 1:0] id_pc;
wire [`INSTR_W - 1:0] id_instr;
wire [`ALU_OP_W - 1:0] id_alu_op;
wire [`WORD_W - 1:0] id_alu_data_a;
wire [`WORD_W - 1:0] id_alu_data_b;
wire [`WORD_W - 1:0] id_imm;
wire [`MEM_OP_W - 1:0] id_mem_op;
wire [`DEST_SRC_W - 1:0] id_dest_src;
wire [`REG_IDX_W - 1:0] id_dest_reg;
wire id_branch_op;
wire id_mem_hazard;
wire ex_clr;
wire ex_stall;
wire [`ADDR_W - 1:0] ex_pc;
wire [`INSTR_W - 1:0] ex_instr;
wire [`WORD_W - 1:0] ex_alu_eval;
wire [`DEST_SRC_W - 1:0] ex_dest_src;
wire [`REG_IDX_W - 1:0] ex_dest_reg;
wire [`MEM_OP_W - 1:0] ex_mem_op;
wire me_clr;
wire me_stall;
wire [`ADDR_W - 1:0] me_pc;
wire [`INSTR_W - 1:0] me_instr;
wire [`DEST_SRC_W - 1:0] me_dest_src;
wire [`REG_IDX_W - 1:0] me_dest_reg;
wire [`WORD_W - 1:0] me_dest_data;
wire wb_clr;
wire wb_stall;
wire wb_dest_en;
wire [`REG_IDX_W - 1:0] wb_dest_reg;
wire [`WORD_W - 1:0] wb_dest_data;
assign fe_clr = ~resetn;
assign id_clr = ~resetn | fe_branch;
assign ex_clr = ~resetn | fe_branch;
assign me_clr = ~resetn;
assign wb_clr = ~resetn;
assign fe_stall = id_mem_hazard;
assign id_stall = id_mem_hazard;
assign ex_stall = 0;
assign me_stall = 0;
assign wb_stall = 0;
assign o_instr_req_addr = fe_pc;
fe p0(
.clk(clk),
.clr(fe_clr),
.stall(fe_stall),
.i_branch(fe_branch),
.i_branch_addr(fe_branch_addr),
.o_pc(fe_pc),
.o_instr_req(o_instr_req_en)
);
reg [`ADDR_W - 1:0] fe_pc_delay;
always@(posedge clk) begin
fe_pc_delay <= fe_pc;
end
id#(
.DUMP_VARS(DUMP_VARS),
.DUMP_FILE(DUMP_FILE)
) p1(
.clk(clk),
.clr(id_clr),
.stall(id_stall),
.rf_reset(aresetn),
.i_pc(fe_pc_delay),
.i_instr(i_instr_res_data),
.i_ex_dest_reg(ex_dest_reg),
.i_ex_dest_src(ex_dest_src),
.i_ex_alu_eval(ex_alu_eval),
.i_me_dest_reg(me_dest_reg),
.i_me_dest_src(me_dest_src),
.i_me_dest_data(me_dest_data),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(id_pc),
.o_instr(id_instr),
.o_alu_op(id_alu_op),
.o_alu_data_a(id_alu_data_a),
.o_alu_data_b(id_alu_data_b),
.o_imm(id_imm),
.o_mem_op(id_mem_op),
.o_dest_src(id_dest_src),
.o_dest_reg(id_dest_reg),
.o_branch_op(id_branch_op),
.o_mem_hazard(id_mem_hazard)
);
ex p2(
.clk(clk),
.clr(ex_clr),
.stall(ex_stall),
.i_pc(id_pc),
.i_instr(id_instr),
.i_alu_op(id_alu_op),
.i_alu_data_a(id_alu_data_a),
.i_alu_data_b(id_alu_data_b),
.i_imm(id_imm),
.i_mem_op(id_mem_op),
.i_dest_src(id_dest_src),
.i_dest_reg(id_dest_reg),
.i_branch_op(id_branch_op),
.o_pc(ex_pc),
.o_instr(ex_instr),
.o_dest_src(ex_dest_src),
.o_dest_reg(ex_dest_reg),
.o_alu_eval(ex_alu_eval),
.o_mem_op(ex_mem_op),
.o_mem_req_addr(o_mem_req_addr),
.o_mem_req_wr_data(o_mem_req_wr_data),
.o_mem_req_wr_en(o_mem_req_wr_en),
.o_mem_req_count(o_mem_req_count),
.o_branch(fe_branch),
.o_branch_addr(fe_branch_addr)
);
me p3(
.clk(clk),
.clr(me_clr),
.stall(me_stall),
.i_pc(ex_pc),
.i_instr(ex_instr),
.i_dest_src(ex_dest_src),
.i_dest_reg(ex_dest_reg),
.i_alu_eval(ex_alu_eval),
.i_mem_read(i_mem_res_rd_data),
.i_mem_op(ex_mem_op),
.o_pc(me_pc),
.o_instr(me_instr),
.o_dest_src(me_dest_src),
.o_dest_reg(me_dest_reg),
.o_dest_data(me_dest_data)
);
wb p4(
.clk(clk),
.clr(wb_clr),
.i_pc(me_pc),
.i_instr(me_instr),
.i_dest_src(me_dest_src),
.i_dest_reg(me_dest_reg),
.i_dest_data(me_dest_data),
.o_dest_en(wb_dest_en),
.o_dest_reg(wb_dest_reg),
.o_dest_data(wb_dest_data)
);
endmodule | 0 |
4,442 | data/full_repos/permissive/109936328/pipeline/wb.v | 109,936,328 | wb.v | v | 78 | 51 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipeline/wb.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:27: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:28: Define or directive not defined: \'`INSTR_W\'\n input [`INSTR_W - 1:0] i_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:30: Define or directive not defined: \'`DEST_SRC_W\'\n input [`DEST_SRC_W - 1:0] i_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:31: Define or directive not defined: \'`REG_IDX_W\'\n input [`REG_IDX_W - 1:0] i_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:33: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:35: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] r_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:36: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] r_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:38: Define or directive not defined: \'`DEST_SRC_W\'\n reg [`DEST_SRC_W - 1:0] r_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:39: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] r_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:41: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] r_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:43: Define or directive not defined: \'`ADDR_W\'\n output [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:44: Define or directive not defined: \'`INSTR_W\'\n output [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:47: Define or directive not defined: \'`REG_IDX_W\'\n output [`REG_IDX_W - 1:0] o_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:48: Define or directive not defined: \'`WORD_W\'\n output [`WORD_W - 1:0] o_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:53: Define or directive not defined: \'`DEST_SRC_NONE\'\n assign o_dest_en = r_dest_src != `DEST_SRC_NONE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n assign o_dest_en = r_dest_src != `DEST_SRC_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:62: Define or directive not defined: \'`DEST_SRC_NONE\'\n r_dest_src <= `DEST_SRC_NONE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n r_dest_src <= `DEST_SRC_NONE;\n ^\n%Error: Exiting due to 20 error(s)\n' | 2,695 | module | module wb(
clk,
clr,
i_pc,
i_instr,
i_dest_src,
i_dest_reg,
i_dest_data,
o_pc,
o_instr,
o_dest_en,
o_dest_reg,
o_dest_data
);
input clk;
input clr;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input [`WORD_W - 1:0] i_dest_data;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg [`WORD_W - 1:0] r_dest_data;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output o_dest_en;
output [`REG_IDX_W - 1:0] o_dest_reg;
output [`WORD_W - 1:0] o_dest_data;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_en = r_dest_src != `DEST_SRC_NONE;
assign o_dest_reg = r_dest_reg;
assign o_dest_data = r_dest_data;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_dest_src <= `DEST_SRC_NONE;
r_dest_reg <= 0;
r_dest_data <= 0;
end else begin
r_pc <= i_pc;
r_instr <= i_instr;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_dest_data <= i_dest_data;
end
end
endmodule | module wb(
clk,
clr,
i_pc,
i_instr,
i_dest_src,
i_dest_reg,
i_dest_data,
o_pc,
o_instr,
o_dest_en,
o_dest_reg,
o_dest_data
); |
input clk;
input clr;
input [`ADDR_W - 1:0] i_pc;
input [`INSTR_W - 1:0] i_instr;
input [`DEST_SRC_W - 1:0] i_dest_src;
input [`REG_IDX_W - 1:0] i_dest_reg;
input [`WORD_W - 1:0] i_dest_data;
reg [`ADDR_W - 1:0] r_pc;
reg [`INSTR_W - 1:0] r_instr;
reg [`DEST_SRC_W - 1:0] r_dest_src;
reg [`REG_IDX_W - 1:0] r_dest_reg;
reg [`WORD_W - 1:0] r_dest_data;
output [`ADDR_W - 1:0] o_pc;
output [`INSTR_W - 1:0] o_instr;
output o_dest_en;
output [`REG_IDX_W - 1:0] o_dest_reg;
output [`WORD_W - 1:0] o_dest_data;
assign o_pc = r_pc;
assign o_instr = r_instr;
assign o_dest_en = r_dest_src != `DEST_SRC_NONE;
assign o_dest_reg = r_dest_reg;
assign o_dest_data = r_dest_data;
always@(posedge clk) begin
if(clr == 1) begin
r_pc <= 0;
r_instr <= 0;
r_dest_src <= `DEST_SRC_NONE;
r_dest_reg <= 0;
r_dest_data <= 0;
end else begin
r_pc <= i_pc;
r_instr <= i_instr;
r_dest_src <= i_dest_src;
r_dest_reg <= i_dest_reg;
r_dest_data <= i_dest_data;
end
end
endmodule | 0 |
4,443 | data/full_repos/permissive/109936328/pipe_util/alu.v | 109,936,328 | alu.v | v | 42 | 57 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:10: Cannot find include file: alu_op.vh\n `include "alu_op.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh.v\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh.sv\n alu_op.vh\n alu_op.vh.v\n alu_op.vh.sv\n obj_dir/alu_op.vh\n obj_dir/alu_op.vh.v\n obj_dir/alu_op.vh.sv\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:13: Define or directive not defined: \'`ALU_OP_W\'\n localparam ALU_OP_W = `ALU_OP_W;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:13: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam ALU_OP_W = `ALU_OP_W;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:27: Define or directive not defined: \'`ALU_ADD\'\n `ALU_ADD: eval = opp_a + opp_b;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:27: syntax error, unexpected \':\', expecting endcase\n `ALU_ADD: eval = opp_a + opp_b;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:28: Define or directive not defined: \'`ALU_SUB\'\n `ALU_SUB: eval = opp_a - opp_b;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:29: Define or directive not defined: \'`ALU_AND\'\n `ALU_AND: eval = opp_a & opp_b;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:30: Define or directive not defined: \'`ALU_OR\'\n `ALU_OR: eval = opp_a | opp_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:31: Define or directive not defined: \'`ALU_XOR\'\n `ALU_XOR: eval = opp_a ^ opp_b;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:32: Define or directive not defined: \'`ALU_SLT\'\n `ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:33: Define or directive not defined: \'`ALU_SLTU\'\n `ALU_SLTU: eval = opp_a < opp_b;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:34: Define or directive not defined: \'`ALU_SGE\'\n `ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:35: Define or directive not defined: \'`ALU_SGEU\'\n `ALU_SGEU: eval = opp_a >= opp_b;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:36: Define or directive not defined: \'`ALU_SNE\'\n `ALU_SNE: eval = opp_a != opp_b;\n ^~~~~~~~\n%Error: Cannot continue\n' | 2,696 | module | module alu(
opp_a,
opp_b,
op,
eval,
zero
);
`include "alu_op.vh"
parameter DATA_W = 32;
localparam ALU_OP_W = `ALU_OP_W;
input [DATA_W - 1:0] opp_a;
input [DATA_W - 1:0] opp_b;
input [ALU_OP_W - 1:0] op;
output reg [DATA_W - 1:0] eval;
output zero;
assign zero = (eval == 0);
always@(*) begin
case(op)
`ALU_ADD: eval = opp_a + opp_b;
`ALU_SUB: eval = opp_a - opp_b;
`ALU_AND: eval = opp_a & opp_b;
`ALU_OR: eval = opp_a | opp_b;
`ALU_XOR: eval = opp_a ^ opp_b;
`ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);
`ALU_SLTU: eval = opp_a < opp_b;
`ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);
`ALU_SGEU: eval = opp_a >= opp_b;
`ALU_SNE: eval = opp_a != opp_b;
default: eval = 0;
endcase
end
endmodule | module alu(
opp_a,
opp_b,
op,
eval,
zero
); |
`include "alu_op.vh"
parameter DATA_W = 32;
localparam ALU_OP_W = `ALU_OP_W;
input [DATA_W - 1:0] opp_a;
input [DATA_W - 1:0] opp_b;
input [ALU_OP_W - 1:0] op;
output reg [DATA_W - 1:0] eval;
output zero;
assign zero = (eval == 0);
always@(*) begin
case(op)
`ALU_ADD: eval = opp_a + opp_b;
`ALU_SUB: eval = opp_a - opp_b;
`ALU_AND: eval = opp_a & opp_b;
`ALU_OR: eval = opp_a | opp_b;
`ALU_XOR: eval = opp_a ^ opp_b;
`ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);
`ALU_SLTU: eval = opp_a < opp_b;
`ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);
`ALU_SGEU: eval = opp_a >= opp_b;
`ALU_SNE: eval = opp_a != opp_b;
default: eval = 0;
endcase
end
endmodule | 0 |
4,444 | data/full_repos/permissive/109936328/pipe_util/id_decoder.v | 109,936,328 | id_decoder.v | v | 223 | 75 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:3: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:4: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:30: Define or directive not defined: \'`INSTR_W\'\n parameter INSTR_W = `INSTR_W;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter INSTR_W = `INSTR_W;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:31: Define or directive not defined: \'`ALU_OP_W\'\n parameter ALU_OP_W = `ALU_OP_W;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter ALU_OP_W = `ALU_OP_W;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:32: Define or directive not defined: \'`WORD_W\'\n parameter WORD_W = `WORD_W;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter WORD_W = `WORD_W;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:39: Define or directive not defined: \'`ALU_SRC_A_W\'\n output reg [`ALU_SRC_A_W - 1:0] alu_a_src;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:40: Define or directive not defined: \'`ALU_SRC_B_W\'\n output reg [`ALU_SRC_B_W - 1:0] alu_b_src;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:42: Define or directive not defined: \'`MEM_OP_W\'\n output reg [`MEM_OP_W - 1:0] mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:46: Define or directive not defined: \'`DEST_SRC_W\'\n output reg [`DEST_SRC_W - 1:0] dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:48: Define or directive not defined: \'`OPCODE\'\n wire [6:0] opcode = `OPCODE(instr);\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:49: Define or directive not defined: \'`FUNCT3\'\n wire [2:0] funct3 = `FUNCT3(instr);\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:50: Define or directive not defined: \'`FUNCT7\'\n wire [6:0] funct7 = `FUNCT7(instr);\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:52: Define or directive not defined: \'`OPCODE_COMPLETE_RTYPE\'\n wire [16:0] opcode_rtype = `OPCODE_COMPLETE_RTYPE(instr);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:53: Define or directive not defined: \'`OPCODE_COMPLETE_ITYPE\'\n wire [16:0] opcode_itype = `OPCODE_COMPLETE_ITYPE(instr);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:54: Define or directive not defined: \'`OPCODE_COMPLETE_STYPE\'\n wire [16:0] opcode_stype = `OPCODE_COMPLETE_STYPE(instr);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:55: Define or directive not defined: \'`OPCODE_COMPLETE_BTYPE\'\n wire [16:0] opcode_btype = `OPCODE_COMPLETE_BTYPE(instr);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:59: Define or directive not defined: \'`ITYPE_IMM12\'\n wire [11:0] itype_imm12 = `ITYPE_IMM12(instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:60: Define or directive not defined: \'`STYPE_IMM12\'\n wire [11:0] stype_imm12 = `STYPE_IMM12(instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:61: Define or directive not defined: \'`BTYPE_IMM12\'\n wire [11:0] btype_imm12 = `BTYPE_IMM12(instr);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:65: Define or directive not defined: \'`OPCODE_RTYPE\'\n `OPCODE_RTYPE: opcode_complete = opcode_rtype;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:65: syntax error, unexpected \':\', expecting endcase\n `OPCODE_RTYPE: opcode_complete = opcode_rtype;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:66: Define or directive not defined: \'`OPCODE_ITYPE\'\n `OPCODE_ITYPE: opcode_complete = opcode_itype;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:68: Define or directive not defined: \'`OPCODE_STYPE_LOAD\'\n `OPCODE_STYPE_LOAD: opcode_complete = opcode_stype;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:69: Define or directive not defined: \'`OPCODE_STYPE_STORE\'\n `OPCODE_STYPE_STORE: opcode_complete = opcode_stype;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:70: Define or directive not defined: \'`OPCODE_BTYPE\'\n `OPCODE_BTYPE: opcode_complete = opcode_btype;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:71: Define or directive not defined: \'`OPCODE_LUI\'\n `OPCODE_LUI: opcode_complete = `OPC_LUI;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:71: Define or directive not defined: \'`OPC_LUI\'\n `OPCODE_LUI: opcode_complete = `OPC_LUI;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:72: Define or directive not defined: \'`OPCODE_AUIPC\'\n `OPCODE_AUIPC: opcode_complete = `OPC_AUIPC;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:72: Define or directive not defined: \'`OPC_AUIPC\'\n `OPCODE_AUIPC: opcode_complete = `OPC_AUIPC;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:73: Define or directive not defined: \'`OPCODE_JAL\'\n `OPCODE_JAL: opcode_complete = `OPC_JAL;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:73: Define or directive not defined: \'`OPC_JAL\'\n `OPCODE_JAL: opcode_complete = `OPC_JAL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:74: Define or directive not defined: \'`OPCODE_JALR\'\n `OPCODE_JALR: opcode_complete = `OPC_JALR;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:74: Define or directive not defined: \'`OPC_JALR\'\n `OPCODE_JALR: opcode_complete = `OPC_JALR;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:81: Define or directive not defined: \'`MEM_OP_NOP\'\n mem_op = `MEM_OP_NOP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:84: Define or directive not defined: \'`OPCODE_RTYPE\'\n `OPCODE_RTYPE: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:84: syntax error, unexpected \':\', expecting endcase\n `OPCODE_RTYPE: begin\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:85: Define or directive not defined: \'`WORD_W\'\n imm = {`WORD_W{1\'b0}};\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:87: Define or directive not defined: \'`ALU_SRC_A_XPR\'\n alu_a_src = `ALU_SRC_A_XPR;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n alu_a_src = `ALU_SRC_A_XPR;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:88: Define or directive not defined: \'`ALU_SRC_B_XPR\'\n alu_b_src = `ALU_SRC_B_XPR;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n alu_b_src = `ALU_SRC_B_XPR;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:90: Define or directive not defined: \'`DEST_SRC_ALU\'\n dest_src = `DEST_SRC_ALU;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n dest_src = `DEST_SRC_ALU;\n ^\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:93: Define or directive not defined: \'`OPCODE_ITYPE\'\n `OPCODE_ITYPE: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/id_decoder.v:93: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `OPCODE_ITYPE: begin\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,697 | module | module id_decoder(
instr,
alu_op,
imm,
alu_a_src,
alu_b_src,
mem_op,
branch_op,
dest_src
);
parameter INSTR_W = `INSTR_W;
parameter ALU_OP_W = `ALU_OP_W;
parameter WORD_W = `WORD_W;
input [INSTR_W - 1:0] instr;
output reg [ALU_OP_W - 1:0] alu_op;
output reg [WORD_W - 1:0] imm;
output reg [`ALU_SRC_A_W - 1:0] alu_a_src;
output reg [`ALU_SRC_B_W - 1:0] alu_b_src;
output reg [`MEM_OP_W - 1:0] mem_op;
output reg branch_op;
output reg [`DEST_SRC_W - 1:0] dest_src;
wire [6:0] opcode = `OPCODE(instr);
wire [2:0] funct3 = `FUNCT3(instr);
wire [6:0] funct7 = `FUNCT7(instr);
wire [16:0] opcode_rtype = `OPCODE_COMPLETE_RTYPE(instr);
wire [16:0] opcode_itype = `OPCODE_COMPLETE_ITYPE(instr);
wire [16:0] opcode_stype = `OPCODE_COMPLETE_STYPE(instr);
wire [16:0] opcode_btype = `OPCODE_COMPLETE_BTYPE(instr);
reg [16:0] opcode_complete;
wire [11:0] itype_imm12 = `ITYPE_IMM12(instr);
wire [11:0] stype_imm12 = `STYPE_IMM12(instr);
wire [11:0] btype_imm12 = `BTYPE_IMM12(instr);
always@(*) begin
case(opcode)
`OPCODE_RTYPE: opcode_complete = opcode_rtype;
`OPCODE_ITYPE: opcode_complete = opcode_itype;
`OPCODE_STYPE_LOAD: opcode_complete = opcode_stype;
`OPCODE_STYPE_STORE: opcode_complete = opcode_stype;
`OPCODE_BTYPE: opcode_complete = opcode_btype;
`OPCODE_LUI: opcode_complete = `OPC_LUI;
`OPCODE_AUIPC: opcode_complete = `OPC_AUIPC;
`OPCODE_JAL: opcode_complete = `OPC_JAL;
`OPCODE_JALR: opcode_complete = `OPC_JALR;
default: opcode_complete = 0;
endcase
end
always@(*) begin
mem_op = `MEM_OP_NOP;
branch_op = 0;
case(opcode)
`OPCODE_RTYPE: begin
imm = {`WORD_W{1'b0}};
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_ITYPE: begin
imm = $signed(itype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_STYPE_LOAD: begin
imm = $signed(itype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_MEM;
case(funct3)
`FUNCT3_LB: mem_op = `MEM_OP_RD_BYTE;
`FUNCT3_LH: mem_op = `MEM_OP_RD_HALF;
`FUNCT3_LW: mem_op = `MEM_OP_RD_WORD;
`FUNCT3_LBU: mem_op = `MEM_OP_RD_UBYTE;
`FUNCT3_LHU: mem_op = `MEM_OP_RD_UHALF;
default: mem_op = `MEM_OP_NOP;
endcase
end
`OPCODE_STYPE_STORE: begin
imm = $signed(stype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
case(funct3)
`FUNCT3_SB: mem_op = `MEM_OP_WR_BYTE;
`FUNCT3_SH: mem_op = `MEM_OP_WR_HALF;
`FUNCT3_SW: mem_op = `MEM_OP_WR_WORD;
default: mem_op = `MEM_OP_NOP;
endcase
end
`OPCODE_BTYPE: begin
imm = $signed(btype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
branch_op = 1;
end
`OPCODE_LUI: begin
imm = `LUI_IMM20(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_AUIPC: begin
imm = `AUIPC_IMM20(instr);
alu_a_src = `ALU_SRC_A_PC;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_JAL: begin
imm = `JAL_IMM20(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_NONE;
dest_src = `DEST_SRC_NONE;
branch_op = 1;
end
`OPCODE_JALR: begin
imm = `JALR_IMM12(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_NONE;
dest_src = `DEST_SRC_PC4;
branch_op = 1;
end
default: begin
imm = 0;
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
end
endcase
end
always@(*) begin
case(opcode_complete)
`OPC_ADD, `OPC_ADDI: alu_op = `ALU_ADD;
`OPC_SUB: alu_op = `ALU_SUB;
`OPC_SLT, `OPC_SLTI: alu_op = `ALU_SLT;
`OPC_SLTU, `OPC_SLTIU: alu_op = `ALU_SLTU;
`OPC_XOR, `OPC_XORI: alu_op = `ALU_XOR;
`OPC_OR, `OPC_ORI: alu_op = `ALU_OR;
`OPC_AND, `OPC_ANDI: alu_op = `ALU_AND;
`OPC_BEQ: alu_op = `ALU_XOR;
`OPC_BNE: alu_op = `ALU_SNE;
`OPC_BLT: alu_op = `ALU_SGE;
`OPC_BGE: alu_op = `ALU_SLT;
`OPC_BLTU: alu_op = `ALU_SGE;
`OPC_BGEU: alu_op = `ALU_SGEU;
`OPC_LUI: alu_op = `ALU_ADD;
`OPC_AUIPC: alu_op = `ALU_ADD;
`OPC_JAL: alu_op = `ALU_ADD;
`OPC_JALR: alu_op = `ALU_ADD;
default: alu_op = `ALU_ADD;
endcase
end
endmodule | module id_decoder(
instr,
alu_op,
imm,
alu_a_src,
alu_b_src,
mem_op,
branch_op,
dest_src
); |
parameter INSTR_W = `INSTR_W;
parameter ALU_OP_W = `ALU_OP_W;
parameter WORD_W = `WORD_W;
input [INSTR_W - 1:0] instr;
output reg [ALU_OP_W - 1:0] alu_op;
output reg [WORD_W - 1:0] imm;
output reg [`ALU_SRC_A_W - 1:0] alu_a_src;
output reg [`ALU_SRC_B_W - 1:0] alu_b_src;
output reg [`MEM_OP_W - 1:0] mem_op;
output reg branch_op;
output reg [`DEST_SRC_W - 1:0] dest_src;
wire [6:0] opcode = `OPCODE(instr);
wire [2:0] funct3 = `FUNCT3(instr);
wire [6:0] funct7 = `FUNCT7(instr);
wire [16:0] opcode_rtype = `OPCODE_COMPLETE_RTYPE(instr);
wire [16:0] opcode_itype = `OPCODE_COMPLETE_ITYPE(instr);
wire [16:0] opcode_stype = `OPCODE_COMPLETE_STYPE(instr);
wire [16:0] opcode_btype = `OPCODE_COMPLETE_BTYPE(instr);
reg [16:0] opcode_complete;
wire [11:0] itype_imm12 = `ITYPE_IMM12(instr);
wire [11:0] stype_imm12 = `STYPE_IMM12(instr);
wire [11:0] btype_imm12 = `BTYPE_IMM12(instr);
always@(*) begin
case(opcode)
`OPCODE_RTYPE: opcode_complete = opcode_rtype;
`OPCODE_ITYPE: opcode_complete = opcode_itype;
`OPCODE_STYPE_LOAD: opcode_complete = opcode_stype;
`OPCODE_STYPE_STORE: opcode_complete = opcode_stype;
`OPCODE_BTYPE: opcode_complete = opcode_btype;
`OPCODE_LUI: opcode_complete = `OPC_LUI;
`OPCODE_AUIPC: opcode_complete = `OPC_AUIPC;
`OPCODE_JAL: opcode_complete = `OPC_JAL;
`OPCODE_JALR: opcode_complete = `OPC_JALR;
default: opcode_complete = 0;
endcase
end
always@(*) begin
mem_op = `MEM_OP_NOP;
branch_op = 0;
case(opcode)
`OPCODE_RTYPE: begin
imm = {`WORD_W{1'b0}};
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_ITYPE: begin
imm = $signed(itype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_STYPE_LOAD: begin
imm = $signed(itype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_MEM;
case(funct3)
`FUNCT3_LB: mem_op = `MEM_OP_RD_BYTE;
`FUNCT3_LH: mem_op = `MEM_OP_RD_HALF;
`FUNCT3_LW: mem_op = `MEM_OP_RD_WORD;
`FUNCT3_LBU: mem_op = `MEM_OP_RD_UBYTE;
`FUNCT3_LHU: mem_op = `MEM_OP_RD_UHALF;
default: mem_op = `MEM_OP_NOP;
endcase
end
`OPCODE_STYPE_STORE: begin
imm = $signed(stype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
case(funct3)
`FUNCT3_SB: mem_op = `MEM_OP_WR_BYTE;
`FUNCT3_SH: mem_op = `MEM_OP_WR_HALF;
`FUNCT3_SW: mem_op = `MEM_OP_WR_WORD;
default: mem_op = `MEM_OP_NOP;
endcase
end
`OPCODE_BTYPE: begin
imm = $signed(btype_imm12);
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
branch_op = 1;
end
`OPCODE_LUI: begin
imm = `LUI_IMM20(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_AUIPC: begin
imm = `AUIPC_IMM20(instr);
alu_a_src = `ALU_SRC_A_PC;
alu_b_src = `ALU_SRC_B_IMM;
dest_src = `DEST_SRC_ALU;
end
`OPCODE_JAL: begin
imm = `JAL_IMM20(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_NONE;
dest_src = `DEST_SRC_NONE;
branch_op = 1;
end
`OPCODE_JALR: begin
imm = `JALR_IMM12(instr);
alu_a_src = `ALU_SRC_A_NONE;
alu_b_src = `ALU_SRC_B_NONE;
dest_src = `DEST_SRC_PC4;
branch_op = 1;
end
default: begin
imm = 0;
alu_a_src = `ALU_SRC_A_XPR;
alu_b_src = `ALU_SRC_B_XPR;
dest_src = `DEST_SRC_NONE;
end
endcase
end
always@(*) begin
case(opcode_complete)
`OPC_ADD, `OPC_ADDI: alu_op = `ALU_ADD;
`OPC_SUB: alu_op = `ALU_SUB;
`OPC_SLT, `OPC_SLTI: alu_op = `ALU_SLT;
`OPC_SLTU, `OPC_SLTIU: alu_op = `ALU_SLTU;
`OPC_XOR, `OPC_XORI: alu_op = `ALU_XOR;
`OPC_OR, `OPC_ORI: alu_op = `ALU_OR;
`OPC_AND, `OPC_ANDI: alu_op = `ALU_AND;
`OPC_BEQ: alu_op = `ALU_XOR;
`OPC_BNE: alu_op = `ALU_SNE;
`OPC_BLT: alu_op = `ALU_SGE;
`OPC_BGE: alu_op = `ALU_SLT;
`OPC_BLTU: alu_op = `ALU_SGE;
`OPC_BGEU: alu_op = `ALU_SGEU;
`OPC_LUI: alu_op = `ALU_ADD;
`OPC_AUIPC: alu_op = `ALU_ADD;
`OPC_JAL: alu_op = `ALU_ADD;
`OPC_JALR: alu_op = `ALU_ADD;
default: alu_op = `ALU_ADD;
endcase
end
endmodule | 0 |
4,445 | data/full_repos/permissive/109936328/pipe_util/register_file.v | 109,936,328 | register_file.v | v | 80 | 64 | [] | [] | [] | [(1, 79)] | null | null | 1: b'%Error: data/full_repos/permissive/109936328/pipe_util/register_file.v:52: Unsupported or unknown PLI call: $dumpfile\n $dumpfile(DUMP_FILE);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/register_file.v:54: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, registers[i]);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,698 | module | module register_file(
clk,
aresetn,
rd_reg_a,
rd_reg_b,
rd_data_a,
rd_data_b,
wr_en,
wr_reg,
wr_data
);
parameter REG_COUNT = 32;
parameter REG_W = 32;
parameter REG_IDX_W = $clog2(REG_COUNT);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input aresetn;
input [REG_IDX_W - 1:0] rd_reg_a;
input [REG_IDX_W - 1:0] rd_reg_b;
output reg [REG_W - 1:0] rd_data_a;
output reg [REG_W - 1:0] rd_data_b;
input wr_en;
input [REG_IDX_W - 1:0] wr_reg;
input [REG_W - 1:0] wr_data;
reg [REG_W - 1:0] registers [0:REG_COUNT - 1];
integer i;
initial begin
if(DUMP_VARS == 1) begin
$dumpfile(DUMP_FILE);
for(i = 0; i < REG_COUNT; i = i + 1) begin
$dumpvars(0, registers[i]);
end
end
end
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < REG_COUNT; i = i + 1) begin
registers[i] <= 0;
end
end else if(wr_en == 1 && wr_reg != 0) begin
registers[wr_reg] <= wr_data;
end
end
always@(negedge clk) begin
if(aresetn == 1) begin
rd_data_a <= registers[rd_reg_a];
rd_data_b <= registers[rd_reg_b];
end
end
endmodule | module register_file(
clk,
aresetn,
rd_reg_a,
rd_reg_b,
rd_data_a,
rd_data_b,
wr_en,
wr_reg,
wr_data
); |
parameter REG_COUNT = 32;
parameter REG_W = 32;
parameter REG_IDX_W = $clog2(REG_COUNT);
parameter DUMP_VARS = 0;
parameter DUMP_FILE = "a.vcd";
input clk;
input aresetn;
input [REG_IDX_W - 1:0] rd_reg_a;
input [REG_IDX_W - 1:0] rd_reg_b;
output reg [REG_W - 1:0] rd_data_a;
output reg [REG_W - 1:0] rd_data_b;
input wr_en;
input [REG_IDX_W - 1:0] wr_reg;
input [REG_W - 1:0] wr_data;
reg [REG_W - 1:0] registers [0:REG_COUNT - 1];
integer i;
initial begin
if(DUMP_VARS == 1) begin
$dumpfile(DUMP_FILE);
for(i = 0; i < REG_COUNT; i = i + 1) begin
$dumpvars(0, registers[i]);
end
end
end
always@(posedge clk, negedge aresetn) begin
if(aresetn == 0) begin
for(i = 0; i < REG_COUNT; i = i + 1) begin
registers[i] <= 0;
end
end else if(wr_en == 1 && wr_reg != 0) begin
registers[wr_reg] <= wr_data;
end
end
always@(negedge clk) begin
if(aresetn == 1) begin
rd_data_a <= registers[rd_reg_a];
rd_data_b <= registers[rd_reg_b];
end
end
endmodule | 0 |
4,446 | data/full_repos/permissive/109936328/tb/tb_gpio_interface.v | 109,936,328 | tb_gpio_interface.v | v | 100 | 79 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:15: Define or directive not defined: \'`WORD_W\'\n localparam GPIO_W = BANK_COUNT * `WORD_W;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam GPIO_W = BANK_COUNT * `WORD_W;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:20: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] req_addr = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:21: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] req_wr_data = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:23: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:23: Define or directive not defined: \'`MEM_COUNT_NONE\'\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:25: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:26: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] res_code; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:30: Define or directive not defined: \'`MEM_COUNT_WORD\'\n req_count = `MEM_COUNT_WORD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_WORD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:42: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] tw_count,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:43: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] tw_data \n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:50: Define or directive not defined: \'`MEM_CODE_WRITE\'\n if (!(res_code == `MEM_CODE_WRITE)) begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:50: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (!(res_code == `MEM_CODE_WRITE)) begin\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_gpio_interface.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:62: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:68: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD,\n ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:72: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:74: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/109936328/tb/tb_gpio_interface.v:79: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,699 | module | module tb_gpio_interface;
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam ADDR_START = 0;
localparam BANK_COUNT = 1;
localparam GPIO_W = BANK_COUNT * `WORD_W;
reg clk = 0;
reg aresetn = 0;
reg [`ADDR_W - 1:0] req_addr = 0;
reg [`WORD_W - 1:0] req_wr_data = 0;
reg req_wr_en = 0;
reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;
wire [`WORD_W - 1:0] res_rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
wire [GPIO_W - 1:0] gpio_state;
task test_reset_condition; begin
req_count = `MEM_COUNT_WORD;
req_wr_en = 0;
#(CLK_PERIOD);
`ASSERT(res_rd_data == 0) begin
$display("Assertion failed in test_reset_condition! res_rd_data = %8x",
res_rd_data);
end
end
endtask
task test_write(
input [`MEM_COUNT_W - 1:0] tw_count,
input [`WORD_W - 1:0] tw_data
); begin
req_count = tw_count;
req_wr_data = tw_data;
req_wr_en = 1;
#(CLK_PERIOD);
`ASSERT(res_code == `MEM_CODE_WRITE) begin
$display("Assertion failed in test_write! res_code = %8x", res_code);
end
end
endtask
integer i;
initial begin
$dumpfile("tb_gpio_interface.vcd");
$dumpvars();
$display("%d", $ceil(BANK_COUNT / 4));
#(CLK_PERIOD);
aresetn = 1;
test_reset_condition();
test_write(
`MEM_COUNT_WORD,
'hdeadbeef
);
#(CLK_PERIOD);
$finish();
end
always begin
#(CLK_HPERIOD);
clk = ~clk;
end
gpio_interface#(
.ADDR_START(ADDR_START),
.BANK_COUNT(BANK_COUNT)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_wr_en(req_wr_en),
.i_req_count(req_count),
.o_res_rd_data(res_rd_data),
.o_res_code(res_code),
.o_gpio_state(gpio_state)
);
endmodule | module tb_gpio_interface; |
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam ADDR_START = 0;
localparam BANK_COUNT = 1;
localparam GPIO_W = BANK_COUNT * `WORD_W;
reg clk = 0;
reg aresetn = 0;
reg [`ADDR_W - 1:0] req_addr = 0;
reg [`WORD_W - 1:0] req_wr_data = 0;
reg req_wr_en = 0;
reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;
wire [`WORD_W - 1:0] res_rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
wire [GPIO_W - 1:0] gpio_state;
task test_reset_condition; begin
req_count = `MEM_COUNT_WORD;
req_wr_en = 0;
#(CLK_PERIOD);
`ASSERT(res_rd_data == 0) begin
$display("Assertion failed in test_reset_condition! res_rd_data = %8x",
res_rd_data);
end
end
endtask
task test_write(
input [`MEM_COUNT_W - 1:0] tw_count,
input [`WORD_W - 1:0] tw_data
); begin
req_count = tw_count;
req_wr_data = tw_data;
req_wr_en = 1;
#(CLK_PERIOD);
`ASSERT(res_code == `MEM_CODE_WRITE) begin
$display("Assertion failed in test_write! res_code = %8x", res_code);
end
end
endtask
integer i;
initial begin
$dumpfile("tb_gpio_interface.vcd");
$dumpvars();
$display("%d", $ceil(BANK_COUNT / 4));
#(CLK_PERIOD);
aresetn = 1;
test_reset_condition();
test_write(
`MEM_COUNT_WORD,
'hdeadbeef
);
#(CLK_PERIOD);
$finish();
end
always begin
#(CLK_HPERIOD);
clk = ~clk;
end
gpio_interface#(
.ADDR_START(ADDR_START),
.BANK_COUNT(BANK_COUNT)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_wr_en(req_wr_en),
.i_req_count(req_count),
.o_res_rd_data(res_rd_data),
.o_res_code(res_code),
.o_gpio_state(gpio_state)
);
endmodule | 0 |
4,447 | data/full_repos/permissive/109936328/tb/tb_id.v | 109,936,328 | tb_id.v | v | 126 | 65 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:4: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:16: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] i_pc = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:17: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] i_instr = 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:19: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: Define or directive not defined: \'`DEST_SRC_W\'\n reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: Define or directive not defined: \'`DEST_SRC_NONE\'\n reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:21: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] ex_alu_eval = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:23: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: Define or directive not defined: \'`DEST_SRC_W\'\n reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: Define or directive not defined: \'`DEST_SRC_NONE\'\n reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:25: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:28: Define or directive not defined: \'`REG_IDX_W\'\n reg [`REG_IDX_W - 1:0] wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:29: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:31: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] o_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:32: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] o_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:34: Define or directive not defined: \'`ALU_OP_W\'\n wire [`ALU_OP_W - 1:0] alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:36: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:37: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:38: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:40: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:42: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:43: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:49: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_id.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:50: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(RESET_DURATION * CLK_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:71: Unsupported: Ignoring delay on this delayed statement.\n #(5 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:83: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD / 2);\n ^\n%Error: Exiting due to 29 error(s), 3 warning(s)\n' | 2,700 | module | module tb_id;
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 5;
reg clk = 0;
reg clr = 0;
reg stall = 0;
reg rf_aresetn = 0;
reg [`ADDR_W - 1:0] i_pc = 0;
reg [`INSTR_W - 1:0] i_instr = 0;
reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;
reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;
reg [`WORD_W - 1:0] ex_alu_eval = 0;
reg [`REG_IDX_W - 1:0] me_dest_reg;
reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;
reg [`WORD_W - 1:0] me_dest_data;
reg wb_dest_en = 0;
reg [`REG_IDX_W - 1:0] wb_dest_reg;
reg [`WORD_W - 1:0] wb_dest_data;
wire [`ADDR_W - 1:0] o_pc;
wire [`INSTR_W - 1:0] o_instr;
wire [`ALU_OP_W - 1:0] alu_op;
wire [`WORD_W - 1:0] alu_data_a;
wire [`WORD_W - 1:0] alu_data_b;
wire [`WORD_W - 1:0] imm;
wire [`MEM_OP_W - 1:0] mem_op;
wire [`DEST_SRC_W - 1:0] dest_src;
wire [`REG_IDX_W - 1:0] dest_reg;
wire mem_hazard;
initial begin
$dumpfile("tb_id.vcd");
$dumpvars;
clk = 0;
clr = 1;
stall = 0;
rf_aresetn = 0;
i_pc = 0;
i_instr = 0;
wb_dest_en = 0;
wb_dest_reg = 0;
wb_dest_data = 0;
#(RESET_DURATION * CLK_PERIOD);
clr = 0;
rf_aresetn = 1;
i_instr = {12'hfff, 5'b00000, 3'b000, 5'b00001, 7'b0010011};
#(5 * CLK_PERIOD);
$display("%0x", i_instr);
$display("%0x", alu_op);
$display("%0d", $signed(imm));
$display("%0d", $signed(dut.s_reg_data_a));
$display("%0d", $signed(alu_data_b));
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
id dut(
.clk(clk),
.clr(clr),
.stall(stall),
.rf_reset(rf_aresetn),
.i_pc(i_pc),
.i_instr(i_instr),
.i_ex_dest_reg(ex_dest_reg),
.i_ex_dest_src(ex_dest_src),
.i_ex_alu_eval(ex_alu_eval),
.i_me_dest_reg(me_dest_reg),
.i_me_dest_src(me_dest_src),
.i_me_dest_data(me_dest_data),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(o_pc),
.o_instr(o_instr),
.o_alu_op(alu_op),
.o_alu_data_a(alu_data_a),
.o_alu_data_b(alu_data_b),
.o_imm(imm),
.o_mem_op(mem_op),
.o_dest_src(dest_src),
.o_dest_reg(dest_reg),
.o_mem_hazard(mem_hazard)
);
endmodule | module tb_id; |
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 5;
reg clk = 0;
reg clr = 0;
reg stall = 0;
reg rf_aresetn = 0;
reg [`ADDR_W - 1:0] i_pc = 0;
reg [`INSTR_W - 1:0] i_instr = 0;
reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;
reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;
reg [`WORD_W - 1:0] ex_alu_eval = 0;
reg [`REG_IDX_W - 1:0] me_dest_reg;
reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;
reg [`WORD_W - 1:0] me_dest_data;
reg wb_dest_en = 0;
reg [`REG_IDX_W - 1:0] wb_dest_reg;
reg [`WORD_W - 1:0] wb_dest_data;
wire [`ADDR_W - 1:0] o_pc;
wire [`INSTR_W - 1:0] o_instr;
wire [`ALU_OP_W - 1:0] alu_op;
wire [`WORD_W - 1:0] alu_data_a;
wire [`WORD_W - 1:0] alu_data_b;
wire [`WORD_W - 1:0] imm;
wire [`MEM_OP_W - 1:0] mem_op;
wire [`DEST_SRC_W - 1:0] dest_src;
wire [`REG_IDX_W - 1:0] dest_reg;
wire mem_hazard;
initial begin
$dumpfile("tb_id.vcd");
$dumpvars;
clk = 0;
clr = 1;
stall = 0;
rf_aresetn = 0;
i_pc = 0;
i_instr = 0;
wb_dest_en = 0;
wb_dest_reg = 0;
wb_dest_data = 0;
#(RESET_DURATION * CLK_PERIOD);
clr = 0;
rf_aresetn = 1;
i_instr = {12'hfff, 5'b00000, 3'b000, 5'b00001, 7'b0010011};
#(5 * CLK_PERIOD);
$display("%0x", i_instr);
$display("%0x", alu_op);
$display("%0d", $signed(imm));
$display("%0d", $signed(dut.s_reg_data_a));
$display("%0d", $signed(alu_data_b));
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
id dut(
.clk(clk),
.clr(clr),
.stall(stall),
.rf_reset(rf_aresetn),
.i_pc(i_pc),
.i_instr(i_instr),
.i_ex_dest_reg(ex_dest_reg),
.i_ex_dest_src(ex_dest_src),
.i_ex_alu_eval(ex_alu_eval),
.i_me_dest_reg(me_dest_reg),
.i_me_dest_src(me_dest_src),
.i_me_dest_data(me_dest_data),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(o_pc),
.o_instr(o_instr),
.o_alu_op(alu_op),
.o_alu_data_a(alu_data_a),
.o_alu_data_b(alu_data_b),
.o_imm(imm),
.o_mem_op(mem_op),
.o_dest_src(dest_src),
.o_dest_reg(dest_reg),
.o_mem_hazard(mem_hazard)
);
endmodule | 0 |
4,448 | data/full_repos/permissive/109936328/tb/tb_instruction_memory.v | 109,936,328 | tb_instruction_memory.v | v | 54 | 47 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:1: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh.sv\n opcodes.vh\n opcodes.vh.v\n opcodes.vh.sv\n obj_dir/opcodes.vh\n obj_dir/opcodes.vh.v\n obj_dir/opcodes.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:13: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:15: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] res_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_instruction_memory.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:25: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:31: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:38: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_HPERIOD);\n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 2,701 | module | module tb_instruction_memory;
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam INSTR_MAX = 5;
localparam INSTR_FILE = "instr.txt";
reg clk = 0;
reg [`ADDR_W - 1:0] req_addr;
wire [`WORD_W - 1:0] res_data;
integer i;
initial begin
$dumpfile("tb_instruction_memory.vcd");
$dumpvars;
$display("Printing instructions.");
for(i = 0; i < INSTR_MAX; i = i + 1) begin
req_addr = {i, 2'b00};
#(CLK_PERIOD);
$display("%8h", res_data);
end
$display("Out of bounds test.");
req_addr = {INSTR_MAX, 2'b00};
#(CLK_PERIOD);
$display("%8h", res_data);
$finish;
end
always begin
#(CLK_HPERIOD);
clk = ~clk;
end
instruction_memory#(
.INSTR_MAX(INSTR_MAX),
.INSTR_FILE(INSTR_FILE)
) dut(
.clk(clk),
.i_req_addr(req_addr),
.o_res_data(res_data)
);
endmodule | module tb_instruction_memory; |
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam INSTR_MAX = 5;
localparam INSTR_FILE = "instr.txt";
reg clk = 0;
reg [`ADDR_W - 1:0] req_addr;
wire [`WORD_W - 1:0] res_data;
integer i;
initial begin
$dumpfile("tb_instruction_memory.vcd");
$dumpvars;
$display("Printing instructions.");
for(i = 0; i < INSTR_MAX; i = i + 1) begin
req_addr = {i, 2'b00};
#(CLK_PERIOD);
$display("%8h", res_data);
end
$display("Out of bounds test.");
req_addr = {INSTR_MAX, 2'b00};
#(CLK_PERIOD);
$display("%8h", res_data);
$finish;
end
always begin
#(CLK_HPERIOD);
clk = ~clk;
end
instruction_memory#(
.INSTR_MAX(INSTR_MAX),
.INSTR_FILE(INSTR_FILE)
) dut(
.clk(clk),
.i_req_addr(req_addr),
.o_res_data(res_data)
);
endmodule | 0 |
4,449 | data/full_repos/permissive/109936328/tb/tb_memory_interface.v | 109,936,328 | tb_memory_interface.v | v | 210 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Warning-BSSPACE: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:4: Backslash followed by whitespace, perhaps the whitespace is accidental?\n`define ASSERT(cond)\\ \n ^\n ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:5: syntax error, unexpected if\n if(!(cond)) begin \\\n ^~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:24: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:26: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:28: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:33: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:36: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:39: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:41: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:43: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:69: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_memory_interface.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:70: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:78: Define or directive not defined: \'`MEM_COUNT_NONE\'\n req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:84: Unsupported or unknown PLI call: $urandom\n test_count[i] = $urandom % 3 + 1;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:87: Unsupported or unknown PLI call: $urandom\n test_data[i] = $urandom;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:91: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:91: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE: begin\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:93: Unsupported or unknown PLI call: $urandom\n test_addr[i][1:0] = $urandom % 4;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:97: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_COUNT_HALF: begin\n ^~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:100: Unsupported or unknown PLI call: $urandom\n test_addr[i][1] = $urandom % 2;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:103: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:112: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:122: Define or directive not defined: \'`MEM_COUNT_WORD\'\n req_count = `MEM_COUNT_WORD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_WORD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:126: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:143: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:152: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:152: syntax error, unexpected \':\', expecting endcase\n `MEM_COUNT_BYTE: begin\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:163: Define or directive not defined: \'`MEM_COUNT_HALF\'\n `MEM_COUNT_HALF: begin\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:173: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD: \n ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:190: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:203: syntax error, unexpected always\n always begin\n ^~~~~~\n%Error: Exiting due to 31 error(s), 5 warning(s)\n' | 2,702 | module | module tb_memory_interface;
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 5;
localparam WORD_COUNT = 128;
localparam TEST_DATA_SIZE = 64;
reg clk;
reg aresetn;
reg [`ADDR_W - 1:0] req_addr;
reg [`WORD_W - 1:0] req_wr_data;
reg [`MEM_COUNT_W - 1:0] req_count;
reg req_wr_en;
wire [`WORD_W - 1:0] rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];
reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];
reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];
integer test_num;
integer i;
memory_interface#(
.WORD_COUNT(WORD_COUNT)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_count(req_count),
.i_req_wr_en(req_wr_en),
.o_res_rd_data(rd_data),
.o_res_code(res_code)
);
initial begin
$dumpfile("tb_memory_interface.vcd");
$dumpvars;
clk = 0;
aresetn = 0;
req_addr = 0;
req_wr_data = 0;
req_count = `MEM_COUNT_NONE;
req_wr_en = 0;
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
test_count[i] = $urandom % 3 + 1;
test_addr[i] = i << 2;
test_data[i] = $urandom;
case(test_count[i])
`MEM_COUNT_BYTE: begin
test_addr[i][1:0] = $urandom % 4;
test_data[i][31:8] = 0;
end
`MEM_COUNT_HALF: begin
test_addr[i][0] = 0;
test_addr[i][1] = $urandom % 2;
test_data[i][31:16] = 0;
end
endcase
end
#(RESET_DURATION * CLK_PERIOD);
aresetn = 1;
#(CLK_PERIOD);
test_num = 1;
$display("[%0d] Testing misalignment!", test_num);
req_wr_en = 1;
req_wr_data = 32'hdeadbeef;
req_count = `MEM_COUNT_WORD;
req_addr = 32'h1;
#(CLK_PERIOD);
`ASSERT(res_code == `MEM_CODE_MISALIGNED)
test_num = test_num + 1;
$display("[%0d] Testing write!", test_num);
req_wr_en = 1;
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
req_addr = test_addr[i];
req_count = test_count[i];
req_wr_data = test_data[i];
#(CLK_PERIOD);
`ASSERT(rd_data == 0)
`ASSERT(res_code == `MEM_CODE_WRITE)
case(req_count)
`MEM_COUNT_BYTE: begin
case(req_addr[1:0])
0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][7:0] == req_wr_data[7:0])
1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:8] == req_wr_data[7:0])
2: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][23:16] == req_wr_data[7:0])
3: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:24] == req_wr_data[7:0])
endcase
end
`MEM_COUNT_HALF: begin
case(req_addr[1])
0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:0] == req_wr_data[15:0])
1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:16] == req_wr_data[15:0])
endcase
end
`MEM_COUNT_WORD: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]] == req_wr_data)
endcase
end
req_wr_en = 0;
test_num = test_num + 1;
$display("[%0d] Testing read!", test_num);
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
req_addr = test_addr[i];
req_count = test_count[i];
#(CLK_PERIOD);
`ASSERT(rd_data == test_data[i])
`ASSERT(res_code == `MEM_CODE_READ)
end
$display("All assertions passed!");
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
endmodule | module tb_memory_interface; |
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 5;
localparam WORD_COUNT = 128;
localparam TEST_DATA_SIZE = 64;
reg clk;
reg aresetn;
reg [`ADDR_W - 1:0] req_addr;
reg [`WORD_W - 1:0] req_wr_data;
reg [`MEM_COUNT_W - 1:0] req_count;
reg req_wr_en;
wire [`WORD_W - 1:0] rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];
reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];
reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];
integer test_num;
integer i;
memory_interface#(
.WORD_COUNT(WORD_COUNT)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_count(req_count),
.i_req_wr_en(req_wr_en),
.o_res_rd_data(rd_data),
.o_res_code(res_code)
);
initial begin
$dumpfile("tb_memory_interface.vcd");
$dumpvars;
clk = 0;
aresetn = 0;
req_addr = 0;
req_wr_data = 0;
req_count = `MEM_COUNT_NONE;
req_wr_en = 0;
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
test_count[i] = $urandom % 3 + 1;
test_addr[i] = i << 2;
test_data[i] = $urandom;
case(test_count[i])
`MEM_COUNT_BYTE: begin
test_addr[i][1:0] = $urandom % 4;
test_data[i][31:8] = 0;
end
`MEM_COUNT_HALF: begin
test_addr[i][0] = 0;
test_addr[i][1] = $urandom % 2;
test_data[i][31:16] = 0;
end
endcase
end
#(RESET_DURATION * CLK_PERIOD);
aresetn = 1;
#(CLK_PERIOD);
test_num = 1;
$display("[%0d] Testing misalignment!", test_num);
req_wr_en = 1;
req_wr_data = 32'hdeadbeef;
req_count = `MEM_COUNT_WORD;
req_addr = 32'h1;
#(CLK_PERIOD);
`ASSERT(res_code == `MEM_CODE_MISALIGNED)
test_num = test_num + 1;
$display("[%0d] Testing write!", test_num);
req_wr_en = 1;
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
req_addr = test_addr[i];
req_count = test_count[i];
req_wr_data = test_data[i];
#(CLK_PERIOD);
`ASSERT(rd_data == 0)
`ASSERT(res_code == `MEM_CODE_WRITE)
case(req_count)
`MEM_COUNT_BYTE: begin
case(req_addr[1:0])
0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][7:0] == req_wr_data[7:0])
1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:8] == req_wr_data[7:0])
2: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][23:16] == req_wr_data[7:0])
3: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:24] == req_wr_data[7:0])
endcase
end
`MEM_COUNT_HALF: begin
case(req_addr[1])
0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:0] == req_wr_data[15:0])
1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:16] == req_wr_data[15:0])
endcase
end
`MEM_COUNT_WORD: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]] == req_wr_data)
endcase
end
req_wr_en = 0;
test_num = test_num + 1;
$display("[%0d] Testing read!", test_num);
for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin
req_addr = test_addr[i];
req_count = test_count[i];
#(CLK_PERIOD);
`ASSERT(rd_data == test_data[i])
`ASSERT(res_code == `MEM_CODE_READ)
end
$display("All assertions passed!");
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
endmodule | 0 |
4,450 | data/full_repos/permissive/109936328/tb/tb_pipeline.v | 109,936,328 | tb_pipeline.v | v | 97 | 51 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:3: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:4: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:5: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:16: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] instr_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:18: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] instr_res_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:20: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:21: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:23: Define or directive not defined: \'`MEM_COUNT_W\'\n wire [`MEM_COUNT_W - 1:0] mem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:25: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] mem_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:26: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] mem_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:29: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_pipeline.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline.v:32: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:37: Define or directive not defined: \'`ADDR_W\'\n wait (instr_req_addr[`ADDR_W - 1:2] == \'h100);\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:37: Unsupported: wait statements\n wait (instr_req_addr[`ADDR_W - 1:2] == \'h100);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline.v:43: Unsupported: Ignoring delay on this delayed statement.\n #CLK_HPERIOD;\n ^\n%Error: Exiting due to 14 error(s), 2 warning(s)\n' | 2,703 | module | module tb_pipeline;
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam SIM_DURATION = 30;
reg clk = 0;
reg resetn = 0;
reg rf_aresetn = 0;
wire [`ADDR_W - 1:0] instr_req_addr;
wire instr_req_en;
wire [`WORD_W - 1:0] instr_res_data;
wire [`ADDR_W - 1:0] mem_req_addr;
wire [`WORD_W - 1:0] mem_req_wr_data;
wire mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] mem_req_count;
wire [`WORD_W - 1:0] mem_res_rd_data;
wire [`MEM_CODE_W - 1:0] mem_res_code;
initial begin
$dumpfile("tb_pipeline.vcd");
$dumpvars();
#CLK_PERIOD;
resetn = 1;
rf_aresetn = 1;
wait (instr_req_addr[`ADDR_W - 1:2] == 'h100);
$finish();
end
always begin: clk_gen
#CLK_HPERIOD;
clk = ~clk;
end
pipeline#(
.DUMP_VARS(1),
.DUMP_FILE("tb_pipeline.vcd")
) dut(
.clk(clk),
.resetn(resetn),
.aresetn(rf_aresetn),
.o_instr_req_addr(instr_req_addr),
.o_instr_req_en(instr_req_en),
.i_instr_res_data(instr_res_data),
.o_mem_req_addr(mem_req_addr),
.o_mem_req_wr_data(mem_req_wr_data),
.o_mem_req_wr_en(mem_req_wr_en),
.o_mem_req_count(mem_req_count),
.i_mem_res_rd_data(mem_res_rd_data),
.i_mem_res_code(mem_res_code)
);
instruction_memory#(
.INSTR_MAX(256),
.INSTR_FILE("program.dat"),
.DUMP_INSTR(0),
.DUMP_FILE("tb_pipeline.vcd")
) imem(
.clk(clk),
.i_req_addr(instr_req_addr),
.o_res_data(instr_res_data)
);
memory_interface#(
.WORD_COUNT(3),
.DUMP_VARS(1),
.DUMP_FILE("tb_pipeline.vcd")
) dmem(
.clk(clk),
.aresetn(rf_aresetn),
.i_req_addr(mem_req_addr),
.i_req_wr_data(mem_req_wr_data),
.i_req_wr_en(mem_req_wr_en),
.i_req_count(mem_req_count),
.o_res_rd_data(mem_res_rd_data),
.o_res_code(mem_res_code)
);
endmodule | module tb_pipeline; |
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
localparam SIM_DURATION = 30;
reg clk = 0;
reg resetn = 0;
reg rf_aresetn = 0;
wire [`ADDR_W - 1:0] instr_req_addr;
wire instr_req_en;
wire [`WORD_W - 1:0] instr_res_data;
wire [`ADDR_W - 1:0] mem_req_addr;
wire [`WORD_W - 1:0] mem_req_wr_data;
wire mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] mem_req_count;
wire [`WORD_W - 1:0] mem_res_rd_data;
wire [`MEM_CODE_W - 1:0] mem_res_code;
initial begin
$dumpfile("tb_pipeline.vcd");
$dumpvars();
#CLK_PERIOD;
resetn = 1;
rf_aresetn = 1;
wait (instr_req_addr[`ADDR_W - 1:2] == 'h100);
$finish();
end
always begin: clk_gen
#CLK_HPERIOD;
clk = ~clk;
end
pipeline#(
.DUMP_VARS(1),
.DUMP_FILE("tb_pipeline.vcd")
) dut(
.clk(clk),
.resetn(resetn),
.aresetn(rf_aresetn),
.o_instr_req_addr(instr_req_addr),
.o_instr_req_en(instr_req_en),
.i_instr_res_data(instr_res_data),
.o_mem_req_addr(mem_req_addr),
.o_mem_req_wr_data(mem_req_wr_data),
.o_mem_req_wr_en(mem_req_wr_en),
.o_mem_req_count(mem_req_count),
.i_mem_res_rd_data(mem_res_rd_data),
.i_mem_res_code(mem_res_code)
);
instruction_memory#(
.INSTR_MAX(256),
.INSTR_FILE("program.dat"),
.DUMP_INSTR(0),
.DUMP_FILE("tb_pipeline.vcd")
) imem(
.clk(clk),
.i_req_addr(instr_req_addr),
.o_res_data(instr_res_data)
);
memory_interface#(
.WORD_COUNT(3),
.DUMP_VARS(1),
.DUMP_FILE("tb_pipeline.vcd")
) dmem(
.clk(clk),
.aresetn(rf_aresetn),
.i_req_addr(mem_req_addr),
.i_req_wr_data(mem_req_wr_data),
.i_req_wr_en(mem_req_wr_en),
.i_req_count(mem_req_count),
.o_res_rd_data(mem_res_rd_data),
.o_res_code(mem_res_code)
);
endmodule | 0 |
4,451 | data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v | 109,936,328 | tb_pipeline_id_ex.v | v | 227 | 74 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:4: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:30: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] wb_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:31: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] wb_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:33: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] fe_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:34: Define or directive not defined: \'`INSTR_W\'\n reg [`INSTR_W - 1:0] fe_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:36: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] id_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:37: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] id_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:38: Define or directive not defined: \'`ALU_OP_W\'\n wire [`ALU_OP_W - 1:0] id_alu_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:39: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_alu_data_a;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:40: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_alu_data_b;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:41: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] id_imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:42: Define or directive not defined: \'`MEM_OP_W\'\n wire [`MEM_OP_W - 1:0] id_mem_op;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:43: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] id_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:44: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] id_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:73: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] ex_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:74: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] ex_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:75: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] ex_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:76: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] ex_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:77: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] ex_alu_eval;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:78: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] ex_mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:79: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] ex_mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:81: Define or directive not defined: \'`MEM_COUNT_W\'\n wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:113: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] m1_mem_read;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:114: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] m1_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:128: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] me_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:129: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] me_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:130: Define or directive not defined: \'`DEST_SRC_W\'\n wire [`DEST_SRC_W - 1:0] me_dest_src;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:131: Define or directive not defined: \'`REG_IDX_W\'\n wire [`REG_IDX_W - 1:0] me_dest_reg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:132: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] me_dest_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:156: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] wb_pc;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:157: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] wb_instr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:180: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_pipeline_id_ex.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:181: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:196: Unsupported: Ignoring delay on this delayed statement.\n #(RESET_DURATION * CLK_PERIOD);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: Define or directive not defined: \'`FUNCT3_ADD\'\n fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: Define or directive not defined: \'`OPCODE_ITYPE\'\n fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:207: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: Define or directive not defined: \'`FUNCT3_ADD\'\n fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: Define or directive not defined: \'`OPCODE_ITYPE\'\n fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:212: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: Define or directive not defined: \'`FUNCT3_ADD\'\n fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: Define or directive not defined: \'`OPCODE_ITYPE\'\n fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:216: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD * 5);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:222: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD / 2);\n ^\n%Error: Exiting due to 45 error(s), 5 warning(s)\n' | 2,704 | module | module tb_pipeline_id_ex;
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 4;
reg clk;
reg rf_aresetn;
reg fe_clr;
reg fe_stall;
reg id_clr;
reg id_stall;
reg ex_clr;
reg ex_stall;
reg me_clr;
reg me_stall;
reg wb_clr;
reg wb_stall;
wire wb_dest_en;
wire [`REG_IDX_W - 1:0] wb_dest_reg;
wire [`WORD_W - 1:0] wb_dest_data;
reg [`ADDR_W - 1:0] fe_pc;
reg [`INSTR_W - 1:0] fe_instr;
wire [`ADDR_W - 1:0] id_pc;
wire [`INSTR_W - 1:0] id_instr;
wire [`ALU_OP_W - 1:0] id_alu_op;
wire [`WORD_W - 1:0] id_alu_data_a;
wire [`WORD_W - 1:0] id_alu_data_b;
wire [`WORD_W - 1:0] id_imm;
wire [`MEM_OP_W - 1:0] id_mem_op;
wire [`DEST_SRC_W - 1:0] id_dest_src;
wire [`REG_IDX_W - 1:0] id_dest_reg;
id p1(
.clk(clk),
.clr(id_clr),
.stall(id_stall),
.rf_reset(rf_aresetn),
.i_pc(fe_pc),
.i_instr(fe_instr),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(id_pc),
.o_instr(id_instr),
.o_alu_op(id_alu_op),
.o_alu_data_a(id_alu_data_a),
.o_alu_data_b(id_alu_data_b),
.o_imm(id_imm),
.o_mem_op(id_mem_op),
.o_dest_src(id_dest_src),
.o_dest_reg(id_dest_reg)
);
wire [`ADDR_W - 1:0] ex_pc;
wire [`INSTR_W - 1:0] ex_instr;
wire [`DEST_SRC_W - 1:0] ex_dest_src;
wire [`REG_IDX_W - 1:0] ex_dest_reg;
wire [`WORD_W - 1:0] ex_alu_eval;
wire [`ADDR_W - 1:0] ex_mem_req_addr;
wire [`WORD_W - 1:0] ex_mem_req_wr_data;
wire ex_mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;
ex p2(
.clk(clk),
.clr(ex_clr),
.stall(ex_stall),
.i_pc(id_pc),
.i_instr(id_instr),
.i_alu_op(id_alu_op),
.i_alu_data_a(id_alu_data_a),
.i_alu_data_b(id_alu_data_b),
.i_imm(id_imm),
.i_dest_src(id_dest_src),
.i_dest_reg(id_dest_reg),
.o_pc(ex_pc),
.o_instr(ex_instr),
.o_dest_src(ex_dest_src),
.o_dest_reg(ex_dest_reg),
.o_alu_eval(ex_alu_eval),
.o_mem_req_addr(ex_mem_req_addr),
.o_mem_req_wr_data(ex_mem_req_wr_data),
.o_mem_req_wr_en(ex_mem_req_wr_en),
.o_mem_req_count(ex_mem_req_count)
);
wire [`WORD_W - 1:0] m1_mem_read;
wire [`MEM_CODE_W - 1:0] m1_res_code;
memory_interface m1(
.clk(clk),
.aresetn(rf_aresetn),
.i_req_addr(ex_mem_req_addr),
.i_req_wr_data(ex_mem_req_wr_data),
.i_req_wr_en(ex_mem_req_wr_en),
.i_req_count(ex_mem_req_count),
.o_res_rd_data(m1_mem_read),
.o_res_code(m1_res_code)
);
wire [`ADDR_W - 1:0] me_pc;
wire [`INSTR_W - 1:0] me_instr;
wire [`DEST_SRC_W - 1:0] me_dest_src;
wire [`REG_IDX_W - 1:0] me_dest_reg;
wire [`WORD_W - 1:0] me_dest_data;
me p3(
.clk(clk),
.clr(me_clr),
.stall(me_stall),
.i_pc(ex_pc),
.i_instr(ex_instr),
.i_dest_src(ex_dest_src),
.i_dest_reg(ex_dest_reg),
.i_alu_eval(ex_alu_eval),
.i_mem_read(m1_mem_read),
.o_pc(me_pc),
.o_instr(me_instr),
.o_dest_src(me_dest_src),
.o_dest_reg(me_dest_reg),
.o_dest_data(me_dest_data)
);
wire [`ADDR_W - 1:0] wb_pc;
wire [`INSTR_W - 1:0] wb_instr;
wb p4(
.clk(clk),
.clr(wb_clr),
.i_pc(me_pc),
.i_instr(me_instr),
.i_dest_src(me_dest_src),
.i_dest_reg(me_dest_reg),
.i_dest_data(me_dest_data),
.o_pc(wb_pc),
.o_instr(wb_instr),
.o_dest_en(wb_dest_en),
.o_dest_reg(wb_dest_reg),
.o_dest_data(wb_dest_data)
);
initial begin
$dumpfile("tb_pipeline_id_ex.vcd");
$dumpvars;
clk = 0;
rf_aresetn = 0;
fe_clr = 1;
fe_stall = 0;
id_clr = 1;
id_stall = 0;
ex_clr = 1;
ex_stall = 0;
me_clr = 1;
me_stall = 0;
wb_clr = 1;
wb_stall = 0;
#(RESET_DURATION * CLK_PERIOD);
rf_aresetn = 1;
fe_clr = 0;
id_clr = 0;
ex_clr = 0;
me_clr = 0;
wb_clr = 0;
fe_instr = {12'hfff, 5'b00000, `FUNCT3_ADD, 5'b00001, `OPCODE_ITYPE};
#(CLK_PERIOD);
fe_instr = {12'h000, 5'b00000, `FUNCT3_ADD, 5'b00000, `OPCODE_ITYPE};
#(CLK_PERIOD);
fe_instr = {12'h002, 5'b00001, `FUNCT3_ADD, 5'b00010, `OPCODE_ITYPE};
#(CLK_PERIOD * 5);
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
endmodule | module tb_pipeline_id_ex; |
localparam CLK_PERIOD = 2;
localparam RESET_DURATION = 4;
reg clk;
reg rf_aresetn;
reg fe_clr;
reg fe_stall;
reg id_clr;
reg id_stall;
reg ex_clr;
reg ex_stall;
reg me_clr;
reg me_stall;
reg wb_clr;
reg wb_stall;
wire wb_dest_en;
wire [`REG_IDX_W - 1:0] wb_dest_reg;
wire [`WORD_W - 1:0] wb_dest_data;
reg [`ADDR_W - 1:0] fe_pc;
reg [`INSTR_W - 1:0] fe_instr;
wire [`ADDR_W - 1:0] id_pc;
wire [`INSTR_W - 1:0] id_instr;
wire [`ALU_OP_W - 1:0] id_alu_op;
wire [`WORD_W - 1:0] id_alu_data_a;
wire [`WORD_W - 1:0] id_alu_data_b;
wire [`WORD_W - 1:0] id_imm;
wire [`MEM_OP_W - 1:0] id_mem_op;
wire [`DEST_SRC_W - 1:0] id_dest_src;
wire [`REG_IDX_W - 1:0] id_dest_reg;
id p1(
.clk(clk),
.clr(id_clr),
.stall(id_stall),
.rf_reset(rf_aresetn),
.i_pc(fe_pc),
.i_instr(fe_instr),
.i_wb_dest_en(wb_dest_en),
.i_wb_dest_reg(wb_dest_reg),
.i_wb_dest_data(wb_dest_data),
.o_pc(id_pc),
.o_instr(id_instr),
.o_alu_op(id_alu_op),
.o_alu_data_a(id_alu_data_a),
.o_alu_data_b(id_alu_data_b),
.o_imm(id_imm),
.o_mem_op(id_mem_op),
.o_dest_src(id_dest_src),
.o_dest_reg(id_dest_reg)
);
wire [`ADDR_W - 1:0] ex_pc;
wire [`INSTR_W - 1:0] ex_instr;
wire [`DEST_SRC_W - 1:0] ex_dest_src;
wire [`REG_IDX_W - 1:0] ex_dest_reg;
wire [`WORD_W - 1:0] ex_alu_eval;
wire [`ADDR_W - 1:0] ex_mem_req_addr;
wire [`WORD_W - 1:0] ex_mem_req_wr_data;
wire ex_mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;
ex p2(
.clk(clk),
.clr(ex_clr),
.stall(ex_stall),
.i_pc(id_pc),
.i_instr(id_instr),
.i_alu_op(id_alu_op),
.i_alu_data_a(id_alu_data_a),
.i_alu_data_b(id_alu_data_b),
.i_imm(id_imm),
.i_dest_src(id_dest_src),
.i_dest_reg(id_dest_reg),
.o_pc(ex_pc),
.o_instr(ex_instr),
.o_dest_src(ex_dest_src),
.o_dest_reg(ex_dest_reg),
.o_alu_eval(ex_alu_eval),
.o_mem_req_addr(ex_mem_req_addr),
.o_mem_req_wr_data(ex_mem_req_wr_data),
.o_mem_req_wr_en(ex_mem_req_wr_en),
.o_mem_req_count(ex_mem_req_count)
);
wire [`WORD_W - 1:0] m1_mem_read;
wire [`MEM_CODE_W - 1:0] m1_res_code;
memory_interface m1(
.clk(clk),
.aresetn(rf_aresetn),
.i_req_addr(ex_mem_req_addr),
.i_req_wr_data(ex_mem_req_wr_data),
.i_req_wr_en(ex_mem_req_wr_en),
.i_req_count(ex_mem_req_count),
.o_res_rd_data(m1_mem_read),
.o_res_code(m1_res_code)
);
wire [`ADDR_W - 1:0] me_pc;
wire [`INSTR_W - 1:0] me_instr;
wire [`DEST_SRC_W - 1:0] me_dest_src;
wire [`REG_IDX_W - 1:0] me_dest_reg;
wire [`WORD_W - 1:0] me_dest_data;
me p3(
.clk(clk),
.clr(me_clr),
.stall(me_stall),
.i_pc(ex_pc),
.i_instr(ex_instr),
.i_dest_src(ex_dest_src),
.i_dest_reg(ex_dest_reg),
.i_alu_eval(ex_alu_eval),
.i_mem_read(m1_mem_read),
.o_pc(me_pc),
.o_instr(me_instr),
.o_dest_src(me_dest_src),
.o_dest_reg(me_dest_reg),
.o_dest_data(me_dest_data)
);
wire [`ADDR_W - 1:0] wb_pc;
wire [`INSTR_W - 1:0] wb_instr;
wb p4(
.clk(clk),
.clr(wb_clr),
.i_pc(me_pc),
.i_instr(me_instr),
.i_dest_src(me_dest_src),
.i_dest_reg(me_dest_reg),
.i_dest_data(me_dest_data),
.o_pc(wb_pc),
.o_instr(wb_instr),
.o_dest_en(wb_dest_en),
.o_dest_reg(wb_dest_reg),
.o_dest_data(wb_dest_data)
);
initial begin
$dumpfile("tb_pipeline_id_ex.vcd");
$dumpvars;
clk = 0;
rf_aresetn = 0;
fe_clr = 1;
fe_stall = 0;
id_clr = 1;
id_stall = 0;
ex_clr = 1;
ex_stall = 0;
me_clr = 1;
me_stall = 0;
wb_clr = 1;
wb_stall = 0;
#(RESET_DURATION * CLK_PERIOD);
rf_aresetn = 1;
fe_clr = 0;
id_clr = 0;
ex_clr = 0;
me_clr = 0;
wb_clr = 0;
fe_instr = {12'hfff, 5'b00000, `FUNCT3_ADD, 5'b00001, `OPCODE_ITYPE};
#(CLK_PERIOD);
fe_instr = {12'h000, 5'b00000, `FUNCT3_ADD, 5'b00000, `OPCODE_ITYPE};
#(CLK_PERIOD);
fe_instr = {12'h002, 5'b00001, `FUNCT3_ADD, 5'b00010, `OPCODE_ITYPE};
#(CLK_PERIOD * 5);
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
endmodule | 0 |
4,452 | data/full_repos/permissive/109936328/tb/tb_register_file.v | 109,936,328 | tb_register_file.v | v | 105 | 68 | [] | [] | [] | [(3, 104)] | null | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_register_file.v:29: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_register_file.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_register_file.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_register_file.v:42: Unsupported: Ignoring delay on this delayed statement.\n #RESET_DURATION;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_register_file.v:50: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_register_file.v:57: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_register_file.v:66: Unsupported or unknown PLI call: $urandom\n wr_data = $urandom;\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_register_file.v:69: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_register_file.v:83: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD / 2);\n ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,705 | module | module tb_register_file;
localparam REG_COUNT = 32;
localparam REG_W = 32;
localparam REG_IDX_W = $clog2(REG_COUNT);
localparam CLK_PERIOD = 4;
localparam RESET_DURATION = 5;
reg clk;
reg aresetn;
reg [REG_IDX_W - 1:0] rd_reg_a;
reg [REG_IDX_W - 1:0] rd_reg_b;
wire [REG_W - 1:0] rd_data_a;
wire [REG_W - 1:0] rd_data_b;
reg wr_en;
reg [REG_IDX_W - 1:0] wr_reg;
reg [REG_W - 1:0] wr_data;
reg [REG_W - 1:0] wr_data_check;
reg [REG_W - 1:0] rd_data_tmp;
integer i;
initial begin
$dumpfile("tb_register_file.vcd");
$dumpvars;
clk = 0;
aresetn = 0;
rd_reg_a = 0;
rd_reg_b = 0;
wr_en = 0;
wr_reg = 0;
wr_data = 0;
#RESET_DURATION;
aresetn = 1;
wr_en = 1;
wr_reg = 0;
wr_data = 1;
rd_reg_a = 0;
#CLK_PERIOD;
if(rd_data_a != 0) begin
$display("Assertion failed! Wrote something to register 0!");
$finish;
end
#CLK_PERIOD;
wr_en = 1;
for(i = 1; i < REG_COUNT; i = i + 1) begin
wr_reg = i;
rd_reg_a = i;
wr_data = $urandom;
wr_data_check = wr_data;
#CLK_PERIOD;
if(rd_data_tmp != wr_data_check) begin
$display("Error! Read/write mismatch!");
$finish;
end
end
$display("All assertions passed!");
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
register_file#(
.REG_W(REG_W),
.REG_COUNT(REG_COUNT)
) u0(
.clk(clk),
.aresetn(aresetn),
.rd_reg_a(rd_reg_a),
.rd_reg_b(rd_reg_b),
.rd_data_a(rd_data_a),
.rd_data_b(rd_data_b),
.wr_en(wr_en),
.wr_reg(wr_reg),
.wr_data(wr_data)
);
endmodule | module tb_register_file; |
localparam REG_COUNT = 32;
localparam REG_W = 32;
localparam REG_IDX_W = $clog2(REG_COUNT);
localparam CLK_PERIOD = 4;
localparam RESET_DURATION = 5;
reg clk;
reg aresetn;
reg [REG_IDX_W - 1:0] rd_reg_a;
reg [REG_IDX_W - 1:0] rd_reg_b;
wire [REG_W - 1:0] rd_data_a;
wire [REG_W - 1:0] rd_data_b;
reg wr_en;
reg [REG_IDX_W - 1:0] wr_reg;
reg [REG_W - 1:0] wr_data;
reg [REG_W - 1:0] wr_data_check;
reg [REG_W - 1:0] rd_data_tmp;
integer i;
initial begin
$dumpfile("tb_register_file.vcd");
$dumpvars;
clk = 0;
aresetn = 0;
rd_reg_a = 0;
rd_reg_b = 0;
wr_en = 0;
wr_reg = 0;
wr_data = 0;
#RESET_DURATION;
aresetn = 1;
wr_en = 1;
wr_reg = 0;
wr_data = 1;
rd_reg_a = 0;
#CLK_PERIOD;
if(rd_data_a != 0) begin
$display("Assertion failed! Wrote something to register 0!");
$finish;
end
#CLK_PERIOD;
wr_en = 1;
for(i = 1; i < REG_COUNT; i = i + 1) begin
wr_reg = i;
rd_reg_a = i;
wr_data = $urandom;
wr_data_check = wr_data;
#CLK_PERIOD;
if(rd_data_tmp != wr_data_check) begin
$display("Error! Read/write mismatch!");
$finish;
end
end
$display("All assertions passed!");
$finish;
end
always begin
#(CLK_PERIOD / 2);
clk = ~clk;
end
register_file#(
.REG_W(REG_W),
.REG_COUNT(REG_COUNT)
) u0(
.clk(clk),
.aresetn(aresetn),
.rd_reg_a(rd_reg_a),
.rd_reg_b(rd_reg_b),
.rd_data_a(rd_data_a),
.rd_data_b(rd_data_b),
.wr_en(wr_en),
.wr_reg(wr_reg),
.wr_data(wr_data)
);
endmodule | 0 |
4,453 | data/full_repos/permissive/109936328/tb/tb_timer.v | 109,936,328 | tb_timer.v | v | 252 | 67 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:14: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:15: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: Define or directive not defined: \'`MEM_COUNT_NONE\'\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:19: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:20: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:26: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:27: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:28: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] wr_mask;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:29: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:31: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] temp;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:34: Define or directive not defined: \'`WORD_W\'\n if(wr_mask == {`WORD_W{1\'b1}}) begin\n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:44: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:54: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:57: Define or directive not defined: \'`MEM_COUNT_NONE\'\n req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:63: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:64: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] wr_mask;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:65: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:67: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] temp;\n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:73: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:81: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:87: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:90: Define or directive not defined: \'`MEM_COUNT_NONE\'\n req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:97: Define or directive not defined: \'`ADDR_W\'\n ((0) + (`ADDR_W\'h0)),\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:98: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h8,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:99: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h8,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:100: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:108: Define or directive not defined: \'`ADDR_W\'\n ((0) + (`ADDR_W\'h0)),\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:109: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h0,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:110: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h8,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:111: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:117: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] count;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:119: Define or directive not defined: \'`ADDR_W\'\n req_addr = ((0) + (`ADDR_W\'h16));\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:120: Define or directive not defined: \'`MEM_COUNT_WORD\'\n req_count = `MEM_COUNT_WORD;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:120: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_WORD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:123: Unsupported: Ignoring delay on this delayed statement.\n #CLK_PERIOD;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:126: Define or directive not defined: \'`MEM_COUNT_NONE\'\n req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:135: Define or directive not defined: \'`ADDR_W\'\n ((0) + (`ADDR_W\'h0)),\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:137: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h4,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:138: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:144: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] load_val;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:145: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] temp;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:148: Define or directive not defined: \'`ADDR_W\'\n `ADDR_W\'h8,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:150: Define or directive not defined: \'`WORD_W\'\n {`WORD_W{1\'b1}},\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:151: Define or directive not defined: \'`MEM_COUNT_WORD\'\n `MEM_COUNT_WORD\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:155: Define or directive not defined: \'`ADDR_W\'\n `ADDR_W\'h0,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:156: Define or directive not defined: \'`WORD_W\'\n `WORD_W\'h2,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:157: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n `MEM_COUNT_BYTE\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:163: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] threshold;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:166: Define or directive not defined: \'`ADDR_W\'\n ((0) + (`ADDR_W\'h4)),\n ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 2,706 | module | module tb_timer;
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
reg clk = 0;
reg aresetn = 0;
reg [`ADDR_W - 1:0] req_addr;
reg [`WORD_W - 1:0] req_wr_data;
reg req_wr_en = 0;
reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;
wire [`WORD_W - 1:0] res_rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
wire threshold_trigger;
assign threshold_trigger = dut.timer.threshold_trigger;
task write_register;
input [`ADDR_W - 1:0] addr;
input [`WORD_W - 1:0] data;
input [`WORD_W - 1:0] wr_mask;
input [`MEM_COUNT_W - 1:0] count;
reg [`WORD_W - 1:0] temp;
begin
if(wr_mask == {`WORD_W{1'b1}}) begin
req_addr = addr;
req_wr_data = data;
req_wr_en = 1;
req_count = count;
end else begin
req_addr = addr;
req_wr_en = 0;
req_count = count;
#CLK_PERIOD;
temp = res_rd_data;
temp = temp | (data & wr_mask);
temp = temp & ~(~data & wr_mask);
req_wr_en = 1;
req_wr_data = temp;
end
#CLK_PERIOD;
req_wr_en = 0;
req_count = `MEM_COUNT_NONE;
end
endtask
task toggle_bits;
input [`ADDR_W - 1:0] addr;
input [`WORD_W - 1:0] wr_mask;
input [`MEM_COUNT_W - 1:0] count;
reg [`WORD_W - 1:0] temp;
begin
req_addr = addr;
req_wr_en = 0;
req_count = count;
#CLK_PERIOD;
temp = res_rd_data;
temp = temp ^ wr_mask;
req_wr_en = 1;
req_wr_data = temp;
#CLK_PERIOD;
temp = temp ^ wr_mask;
req_wr_data = temp;
#CLK_PERIOD;
req_wr_en = 0;
req_count = `MEM_COUNT_NONE;
end
endtask
task start_timer;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
`WORD_W'h8,
`WORD_W'h8,
`MEM_COUNT_BYTE
);
end
endtask
task stop_timer;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
`WORD_W'h0,
`WORD_W'h8,
`MEM_COUNT_BYTE
);
end
endtask
task read_timer_count;
output reg [`WORD_W - 1:0] count;
begin
req_addr = `TMR_ADDR(`ADDR_W'h16);
req_count = `MEM_COUNT_WORD;
req_wr_en = 0;
#CLK_PERIOD;
count = res_rd_data;
req_count = `MEM_COUNT_NONE;
req_wr_en = 0;
end
endtask
task set_dir;
input backwards;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
backwards << 2,
`WORD_W'h4,
`MEM_COUNT_BYTE
);
end
endtask
task load_value;
input [`WORD_W - 1:0] load_val;
reg [`WORD_W - 1:0] temp;
begin
write_register(
`ADDR_W'h8,
load_val,
{`WORD_W{1'b1}},
`MEM_COUNT_WORD
);
toggle_bits(
`ADDR_W'h0,
`WORD_W'h2,
`MEM_COUNT_BYTE
);
end
endtask
task set_threshold;
input [`WORD_W - 1:0] threshold;
begin
write_register(
`TMR_ADDR(`ADDR_W'h4),
threshold,
`WORD_W'hffffffff,
`MEM_COUNT_WORD
);
end
endtask
task set_trigger_en;
input en;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
en,
`WORD_W'h1,
`MEM_COUNT_BYTE
);
end
endtask
reg [`WORD_W - 1:0] timer_count;
integer i;
initial begin
$dumpfile("tb_timer.vcd");
$dumpvars();
for(i = 0; i < 1; i = i + 1) begin
$dumpvars(0, dut.timer.rw_reg.readwrite_registers.r_mem[i]);
end
#CLK_PERIOD;
aresetn = 1;
load_value(
`WORD_W'h10000000
);
start_timer();
repeat(10) begin
#CLK_PERIOD;
end
stop_timer();
repeat(3) begin
#CLK_PERIOD;
end
set_dir(1);
set_threshold(`WORD_W'h10000000);
set_trigger_en(1'b1);
start_timer();
wait(threshold_trigger == 1);
#CLK_PERIOD;
set_dir(0);
repeat(5) begin
#CLK_PERIOD;
end
$finish();
end
always begin: clk_gen
#CLK_HPERIOD;
clk = ~clk;
end
timer#(
.ADDR_START(`ADDR_START)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_wr_en(req_wr_en),
.i_req_count(req_count),
.o_res_rd_data(res_rd_data),
.o_res_code(res_code)
);
endmodule | module tb_timer; |
localparam CLK_HPERIOD = 5;
localparam CLK_PERIOD = 2 * CLK_HPERIOD;
reg clk = 0;
reg aresetn = 0;
reg [`ADDR_W - 1:0] req_addr;
reg [`WORD_W - 1:0] req_wr_data;
reg req_wr_en = 0;
reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;
wire [`WORD_W - 1:0] res_rd_data;
wire [`MEM_CODE_W - 1:0] res_code;
wire threshold_trigger;
assign threshold_trigger = dut.timer.threshold_trigger;
task write_register;
input [`ADDR_W - 1:0] addr;
input [`WORD_W - 1:0] data;
input [`WORD_W - 1:0] wr_mask;
input [`MEM_COUNT_W - 1:0] count;
reg [`WORD_W - 1:0] temp;
begin
if(wr_mask == {`WORD_W{1'b1}}) begin
req_addr = addr;
req_wr_data = data;
req_wr_en = 1;
req_count = count;
end else begin
req_addr = addr;
req_wr_en = 0;
req_count = count;
#CLK_PERIOD;
temp = res_rd_data;
temp = temp | (data & wr_mask);
temp = temp & ~(~data & wr_mask);
req_wr_en = 1;
req_wr_data = temp;
end
#CLK_PERIOD;
req_wr_en = 0;
req_count = `MEM_COUNT_NONE;
end
endtask
task toggle_bits;
input [`ADDR_W - 1:0] addr;
input [`WORD_W - 1:0] wr_mask;
input [`MEM_COUNT_W - 1:0] count;
reg [`WORD_W - 1:0] temp;
begin
req_addr = addr;
req_wr_en = 0;
req_count = count;
#CLK_PERIOD;
temp = res_rd_data;
temp = temp ^ wr_mask;
req_wr_en = 1;
req_wr_data = temp;
#CLK_PERIOD;
temp = temp ^ wr_mask;
req_wr_data = temp;
#CLK_PERIOD;
req_wr_en = 0;
req_count = `MEM_COUNT_NONE;
end
endtask
task start_timer;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
`WORD_W'h8,
`WORD_W'h8,
`MEM_COUNT_BYTE
);
end
endtask
task stop_timer;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
`WORD_W'h0,
`WORD_W'h8,
`MEM_COUNT_BYTE
);
end
endtask
task read_timer_count;
output reg [`WORD_W - 1:0] count;
begin
req_addr = `TMR_ADDR(`ADDR_W'h16);
req_count = `MEM_COUNT_WORD;
req_wr_en = 0;
#CLK_PERIOD;
count = res_rd_data;
req_count = `MEM_COUNT_NONE;
req_wr_en = 0;
end
endtask
task set_dir;
input backwards;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
backwards << 2,
`WORD_W'h4,
`MEM_COUNT_BYTE
);
end
endtask
task load_value;
input [`WORD_W - 1:0] load_val;
reg [`WORD_W - 1:0] temp;
begin
write_register(
`ADDR_W'h8,
load_val,
{`WORD_W{1'b1}},
`MEM_COUNT_WORD
);
toggle_bits(
`ADDR_W'h0,
`WORD_W'h2,
`MEM_COUNT_BYTE
);
end
endtask
task set_threshold;
input [`WORD_W - 1:0] threshold;
begin
write_register(
`TMR_ADDR(`ADDR_W'h4),
threshold,
`WORD_W'hffffffff,
`MEM_COUNT_WORD
);
end
endtask
task set_trigger_en;
input en;
begin
write_register(
`TMR_ADDR(`ADDR_W'h0),
en,
`WORD_W'h1,
`MEM_COUNT_BYTE
);
end
endtask
reg [`WORD_W - 1:0] timer_count;
integer i;
initial begin
$dumpfile("tb_timer.vcd");
$dumpvars();
for(i = 0; i < 1; i = i + 1) begin
$dumpvars(0, dut.timer.rw_reg.readwrite_registers.r_mem[i]);
end
#CLK_PERIOD;
aresetn = 1;
load_value(
`WORD_W'h10000000
);
start_timer();
repeat(10) begin
#CLK_PERIOD;
end
stop_timer();
repeat(3) begin
#CLK_PERIOD;
end
set_dir(1);
set_threshold(`WORD_W'h10000000);
set_trigger_en(1'b1);
start_timer();
wait(threshold_trigger == 1);
#CLK_PERIOD;
set_dir(0);
repeat(5) begin
#CLK_PERIOD;
end
$finish();
end
always begin: clk_gen
#CLK_HPERIOD;
clk = ~clk;
end
timer#(
.ADDR_START(`ADDR_START)
) dut(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(req_addr),
.i_req_wr_data(req_wr_data),
.i_req_wr_en(req_wr_en),
.i_req_count(req_count),
.o_res_rd_data(res_rd_data),
.o_res_code(res_code)
);
endmodule | 0 |
4,454 | data/full_repos/permissive/109936328/top/dmem_bus.v | 109,936,328 | dmem_bus.v | v | 62 | 75 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:11: Define or directive not defined: \'`ADDR_W\'\n input [`ADDR_W - 1:0] i_mem_req_addr,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:12: Define or directive not defined: \'`WORD_W\'\n input [`WORD_W - 1:0] i_mem_req_wr_addr,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:14: Define or directive not defined: \'`MEM_COUNT_W\'\n input [`MEM_COUNT_W - 1:0] i_mem_req_count,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:16: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] o_mem_res_data,\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:17: Define or directive not defined: \'`MEM_COUNT_W\'\n output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:19: Define or directive not defined: \'`WORD_W\'\n output reg [`WORD_W - 1:0] peripheral\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:21: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:22: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:24: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] dmem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:25: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] dmem_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:26: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] dmem_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: Define or directive not defined: \'`MEM_CODE_WRITE\'\n o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n ^\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: Define or directive not defined: \'`MEM_CODE_READ\'\n o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:40: Define or directive not defined: \'`MEM_COUNT_NONE\'\n dmem_req_count = `MEM_COUNT_NONE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n dmem_req_count = `MEM_COUNT_NONE;\n ^\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:43: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;\n ^\n%Error: Exiting due to 20 error(s)\n' | 2,707 | module | module dmem_bus#(
parameter WORD_COUNT,
parameter PERIPH_ADDR
)(
input clk,
input aresetn,
input [`ADDR_W - 1:0] i_mem_req_addr,
input [`WORD_W - 1:0] i_mem_req_wr_addr,
input i_mem_req_wr_en,
input [`MEM_COUNT_W - 1:0] i_mem_req_count,
output reg [`WORD_W - 1:0] o_mem_res_data,
output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,
output reg [`WORD_W - 1:0] peripheral
);
reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;
wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;
wire dmem_req_wr_en = i_mem_req_wr_en;
reg [`MEM_COUNT_W - 1:0] dmem_req_count;
wire [`WORD_W - 1:0] dmem_res_rd_data;
wire [`MEM_CODE_W - 1:0] dmem_res_code;
always @(*) begin
if(i_mem_req_addr < {WORD_COUNT, 2'b00}) begin
dmem_req_count = i_mem_req_count;
o_mem_res_rd_data = dmem_res_rd_data;
o_mem_res_code = dmem_res_code;
end else if(i_mem_req_addr == PERIPH_ADDR) begin
dmem_req_count = i_mem_req_count;
o_mem_res_rd_data = peripheral;
o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;
end else begin
dmem_req_count = `MEM_COUNT_NONE;
o_mem_res_rd_data = 0;
o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;
end
end
memory_interface#(
.WORD_COUNT(WORD_COUNT)
) dmem(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(dmem_req_addr),
.i_req_wr_data(dmem_req_wr_data),
.i_req_wr_en(dmem_req_wr_en),
.i_req_count(dmem_req_count),
.o_res_rd_data(dmem_res_rd_data),
.o_res_code(dmem_res_code)
);
endmodule | module dmem_bus#(
parameter WORD_COUNT,
parameter PERIPH_ADDR
)(
input clk,
input aresetn,
input [`ADDR_W - 1:0] i_mem_req_addr,
input [`WORD_W - 1:0] i_mem_req_wr_addr,
input i_mem_req_wr_en,
input [`MEM_COUNT_W - 1:0] i_mem_req_count,
output reg [`WORD_W - 1:0] o_mem_res_data,
output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,
output reg [`WORD_W - 1:0] peripheral
); |
reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;
wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;
wire dmem_req_wr_en = i_mem_req_wr_en;
reg [`MEM_COUNT_W - 1:0] dmem_req_count;
wire [`WORD_W - 1:0] dmem_res_rd_data;
wire [`MEM_CODE_W - 1:0] dmem_res_code;
always @(*) begin
if(i_mem_req_addr < {WORD_COUNT, 2'b00}) begin
dmem_req_count = i_mem_req_count;
o_mem_res_rd_data = dmem_res_rd_data;
o_mem_res_code = dmem_res_code;
end else if(i_mem_req_addr == PERIPH_ADDR) begin
dmem_req_count = i_mem_req_count;
o_mem_res_rd_data = peripheral;
o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;
end else begin
dmem_req_count = `MEM_COUNT_NONE;
o_mem_res_rd_data = 0;
o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;
end
end
memory_interface#(
.WORD_COUNT(WORD_COUNT)
) dmem(
.clk(clk),
.aresetn(aresetn),
.i_req_addr(dmem_req_addr),
.i_req_wr_data(dmem_req_wr_data),
.i_req_wr_en(dmem_req_wr_en),
.i_req_count(dmem_req_count),
.o_res_rd_data(dmem_res_rd_data),
.o_res_code(dmem_res_code)
);
endmodule | 0 |
4,455 | data/full_repos/permissive/109936328/top/top.v | 109,936,328 | top.v | v | 78 | 45 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/109936328/top/top.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.v\n data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/top/top.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:3: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:14: Define or directive not defined: \'`WORD_W\'\n output logic [`WORD_W - 1:0] peripheral\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:16: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] instr_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:17: Define or directive not defined: \'`INSTR_W\'\n wire [`INSTR_W - 1:0] instr_res_data;\n ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:19: Define or directive not defined: \'`ADDR_W\'\n wire [`ADDR_W - 1:0] mem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:20: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] mem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:22: Define or directive not defined: \'`MEM_COUNT_W\'\n wire [`MEM_COUNT_W - 1:0] mem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:24: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] mem_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:25: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] mem_res_code;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:60: Define or directive not defined: \'`ADDR_W\'\n reg [`ADDR_W - 1:0] dmem_req_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:61: Define or directive not defined: \'`WORD_W\'\n reg [`WORD_W - 1:0] dmem_req_wr_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:63: Define or directive not defined: \'`MEM_COUNT_W\'\n reg [`MEM_COUNT_W - 1:0] dmem_req_count;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:64: Define or directive not defined: \'`WORD_W\'\n wire [`WORD_W - 1:0] dmem_res_rd_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:65: Define or directive not defined: \'`MEM_CODE_W\'\n wire [`MEM_CODE_W - 1:0] dmem_res_code;\n ^~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n' | 2,708 | module | module top#(
parameter INSTR_MAX = 100,
parameter INSTR_FILE = "program.instr",
parameter MEMORY_WORD_COUNT = 100
)(
input clk,
input reset,
input aresetn,
output logic [`WORD_W - 1:0] peripheral
);
wire [`ADDR_W - 1:0] instr_req_addr;
wire [`INSTR_W - 1:0] instr_res_data;
wire [`ADDR_W - 1:0] mem_req_addr;
wire [`WORD_W - 1:0] mem_req_wr_data;
wire mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] mem_req_count;
wire [`WORD_W - 1:0] mem_res_rd_data;
wire [`MEM_CODE_W - 1:0] mem_res_code;
pipeline processor(
.clk(clk),
.reset(reset),
.aresetn(aresetn),
.o_instr_req_addr(instr_req_addr),
.i_instr_res_data(instr_res_data),
.o_mem_req_addr(mem_req_addr),
.o_mem_req_wr_data(mem_req_wr_data),
.o_mem_req_wr_en(mem_req_wr_en),
.o_mem_req_count(mem_req_count),
.i_mem_res_rd_data(mem_res_rd_data),
.i_mem_res_code(mem_res_code)
);
dmem_bus#(
.WORD_COUNT(MEMORY_WORD_COUNT),
.PERIPH_ADDR({MEMORY_WORD_COUNT, 2'b00})
) dmem(
.clk(clk),
.aresetn(aresetn),
.i_mem_req_addr(mem_req_addr),
.i_mem_req_wr_data(mem_req_wr_data),
.i_mem_req_wr_en(mem_req_wr_en),
.i_mem_req_count(mem_req_count),
.o_mem_res_rd_data(mem_res_rd_data),
.o_mem_res_code(mem_res_code)
);
reg [`ADDR_W - 1:0] dmem_req_addr;
reg [`WORD_W - 1:0] dmem_req_wr_data;
reg dmem_req_wr_en;
reg [`MEM_COUNT_W - 1:0] dmem_req_count;
wire [`WORD_W - 1:0] dmem_res_rd_data;
wire [`MEM_CODE_W - 1:0] dmem_res_code;
instruction_memory#(
.INSTR_MAX(INSTR_MAX),
.INSTR_FILE(INSTR_FILE)
) imem(
.clk(clk),
.i_req_addr(instr_req_addr),
.o_res_data(instr_res_data)
);
endmodule | module top#(
parameter INSTR_MAX = 100,
parameter INSTR_FILE = "program.instr",
parameter MEMORY_WORD_COUNT = 100
)(
input clk,
input reset,
input aresetn,
output logic [`WORD_W - 1:0] peripheral
); |
wire [`ADDR_W - 1:0] instr_req_addr;
wire [`INSTR_W - 1:0] instr_res_data;
wire [`ADDR_W - 1:0] mem_req_addr;
wire [`WORD_W - 1:0] mem_req_wr_data;
wire mem_req_wr_en;
wire [`MEM_COUNT_W - 1:0] mem_req_count;
wire [`WORD_W - 1:0] mem_res_rd_data;
wire [`MEM_CODE_W - 1:0] mem_res_code;
pipeline processor(
.clk(clk),
.reset(reset),
.aresetn(aresetn),
.o_instr_req_addr(instr_req_addr),
.i_instr_res_data(instr_res_data),
.o_mem_req_addr(mem_req_addr),
.o_mem_req_wr_data(mem_req_wr_data),
.o_mem_req_wr_en(mem_req_wr_en),
.o_mem_req_count(mem_req_count),
.i_mem_res_rd_data(mem_res_rd_data),
.i_mem_res_code(mem_res_code)
);
dmem_bus#(
.WORD_COUNT(MEMORY_WORD_COUNT),
.PERIPH_ADDR({MEMORY_WORD_COUNT, 2'b00})
) dmem(
.clk(clk),
.aresetn(aresetn),
.i_mem_req_addr(mem_req_addr),
.i_mem_req_wr_data(mem_req_wr_data),
.i_mem_req_wr_en(mem_req_wr_en),
.i_mem_req_count(mem_req_count),
.o_mem_res_rd_data(mem_res_rd_data),
.o_mem_res_code(mem_res_code)
);
reg [`ADDR_W - 1:0] dmem_req_addr;
reg [`WORD_W - 1:0] dmem_req_wr_data;
reg dmem_req_wr_en;
reg [`MEM_COUNT_W - 1:0] dmem_req_count;
wire [`WORD_W - 1:0] dmem_res_rd_data;
wire [`MEM_CODE_W - 1:0] dmem_res_code;
instruction_memory#(
.INSTR_MAX(INSTR_MAX),
.INSTR_FILE(INSTR_FILE)
) imem(
.clk(clk),
.i_req_addr(instr_req_addr),
.o_res_data(instr_res_data)
);
endmodule | 0 |
4,456 | data/full_repos/permissive/110056451/plotfour_hex.v | 110,056,451 | plotfour_hex.v | v | 44 | 58 | [] | [] | [] | [(5, 42)] | null | null | 1: b'%Error: data/full_repos/permissive/110056451/plotfour_hex.v:5: Input/output/inout declaration not found for port: \'HEX\'\nmodule plotfour_hex(HEX, SW);\n ^~~\n%Error: data/full_repos/permissive/110056451/plotfour_hex.v:7: Input/output/inout does not appear in port list: \'HEX0\'\n output [6:0] HEX0;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_hex.v:9: Signal definition not found, creating implicitly: \'HEX\'\n : ... Suggested alternative: \'HEX0\'\n assign HEX[0] = ~SW[3] & ~SW[2] & ~SW[1] & SW[0] |\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 2,710 | module | module plotfour_hex(HEX, SW);
input [9:0] SW;
output [6:0] HEX0;
assign HEX[0] = ~SW[3] & ~SW[2] & ~SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[3] & ~SW[2] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & SW[0] ;
assign HEX[1] = ~SW[3] & ~SW[2] & SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & SW[0] |
SW[3] & SW[1] & SW[0] |
SW[2] & SW[1] & ~SW[0] ;
assign HEX[2] = SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[3] & SW[2] & SW[1] |
~SW[3] & ~SW[2] & SW[1] & ~SW[0];
assign HEX[3] = ~SW[3] & ~SW[2] & ~SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[2] & SW[1] & SW[0] |
SW[3] & ~SW[2] & ~SW[1] & SW[0] |
SW[3] & ~SW[2] & SW[1] & ~SW[0];
assign HEX[4] = ~SW[3] & SW[0] |
~SW[3] & SW[2] & ~SW[1] |
SW[3] & ~SW[2] & ~SW[1] & SW[0] ;
assign HEX[5] = ~SW[3] & ~SW[2] & SW[0] |
~SW[3] & ~SW[2] & SW[1] |
~SW[3] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & SW[0] ;
assign HEX[6] = ~SW[3] & ~SW[2] & ~SW[1] |
~SW[3] & SW[2] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & ~SW[0] ;
endmodule | module plotfour_hex(HEX, SW); |
input [9:0] SW;
output [6:0] HEX0;
assign HEX[0] = ~SW[3] & ~SW[2] & ~SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[3] & ~SW[2] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & SW[0] ;
assign HEX[1] = ~SW[3] & ~SW[2] & SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & SW[0] |
SW[3] & SW[1] & SW[0] |
SW[2] & SW[1] & ~SW[0] ;
assign HEX[2] = SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[3] & SW[2] & SW[1] |
~SW[3] & ~SW[2] & SW[1] & ~SW[0];
assign HEX[3] = ~SW[3] & ~SW[2] & ~SW[1] & SW[0] |
~SW[3] & SW[2] & ~SW[1] & ~SW[0] |
SW[2] & SW[1] & SW[0] |
SW[3] & ~SW[2] & ~SW[1] & SW[0] |
SW[3] & ~SW[2] & SW[1] & ~SW[0];
assign HEX[4] = ~SW[3] & SW[0] |
~SW[3] & SW[2] & ~SW[1] |
SW[3] & ~SW[2] & ~SW[1] & SW[0] ;
assign HEX[5] = ~SW[3] & ~SW[2] & SW[0] |
~SW[3] & ~SW[2] & SW[1] |
~SW[3] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & SW[0] ;
assign HEX[6] = ~SW[3] & ~SW[2] & ~SW[1] |
~SW[3] & SW[2] & SW[1] & SW[0] |
SW[3] & SW[2] & ~SW[1] & ~SW[0] ;
endmodule | 0 |
4,457 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module plotfour_top (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
LEDR,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_B
);
input CLOCK_50;
input [5:0] SW;
input [0:3] KEY;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [0:4] LEDR;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_B;
wire resetn, start, p_one, p_two, p_one_win, p_two_win;
assign resetn = ~KEY[0];
assign start = KEY[3];
assign p_one = ~KEY[1];
assign p_two = ~KEY[2];
assign p_one_win = LEDR[3];
assign p_two_win = LEDR[4];
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn, enable;
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "grid.mif";
datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);
control c0(~KEY[1], ~KEY[2], ~KEY[0], CLOCK_50, enable, writeEn);
reg p_one_status, p_two_status;
always @(*)
begin
if(start==1'b1 && p_one==1'b1)
begin
p_one_status <= 1'b1;
end
else
begin
p_one_status <= 1'b0;
end
end
always @(*)
begin
if(start==1'b1 && p_two==1'b1)
begin
p_two_status <= 1'b1;
end
else
begin
p_two_status <= 1'b0;
end
end
assign LEDR[1] = p_one_status;
assign LEDR[2] = p_two_status;
wire [7:0] hex_digit_wire;
assign hex_digit_wire[7:5] = {2'b0, SW[5]};
assign hex_digit_wire[4:0] = SW[4:0];
hex_decoder h0(
.hex_digit(hex_digit_wire[3:0]),
.segments(HEX0)
);
hex_decoder h1(
.hex_digit(hex_digit_wire[7:4]),
.segments(HEX1)
);
wire [41:0] blue_square;
wire [41:0] red_square;
wire turn;
wire p_one_score, p_two_score;
fsm_controller fsm(
.resetn(resetn),
.p_one(p_one),
.p_two(KEY[2]),
.start(start),
.square(SW[5:0]),
.p_one_win(LEDR[3]),
.p_two_win(LEDR[4]),
.blue(blue_square),
.red(red_square),
.turn(turn),
.p_one_score(p_one_score),
.p_two_score(p_two_score)
);
hex_decoder h2(
.hex_digit(p_one_score),
.segments(HEX2)
);
endmodule | module plotfour_top (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
LEDR,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_B
); |
input CLOCK_50;
input [5:0] SW;
input [0:3] KEY;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [0:4] LEDR;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_B;
wire resetn, start, p_one, p_two, p_one_win, p_two_win;
assign resetn = ~KEY[0];
assign start = KEY[3];
assign p_one = ~KEY[1];
assign p_two = ~KEY[2];
assign p_one_win = LEDR[3];
assign p_two_win = LEDR[4];
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn, enable;
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "grid.mif";
datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);
control c0(~KEY[1], ~KEY[2], ~KEY[0], CLOCK_50, enable, writeEn);
reg p_one_status, p_two_status;
always @(*)
begin
if(start==1'b1 && p_one==1'b1)
begin
p_one_status <= 1'b1;
end
else
begin
p_one_status <= 1'b0;
end
end
always @(*)
begin
if(start==1'b1 && p_two==1'b1)
begin
p_two_status <= 1'b1;
end
else
begin
p_two_status <= 1'b0;
end
end
assign LEDR[1] = p_one_status;
assign LEDR[2] = p_two_status;
wire [7:0] hex_digit_wire;
assign hex_digit_wire[7:5] = {2'b0, SW[5]};
assign hex_digit_wire[4:0] = SW[4:0];
hex_decoder h0(
.hex_digit(hex_digit_wire[3:0]),
.segments(HEX0)
);
hex_decoder h1(
.hex_digit(hex_digit_wire[7:4]),
.segments(HEX1)
);
wire [41:0] blue_square;
wire [41:0] red_square;
wire turn;
wire p_one_score, p_two_score;
fsm_controller fsm(
.resetn(resetn),
.p_one(p_one),
.p_two(KEY[2]),
.start(start),
.square(SW[5:0]),
.p_one_win(LEDR[3]),
.p_two_win(LEDR[4]),
.blue(blue_square),
.red(red_square),
.turn(turn),
.p_one_score(p_one_score),
.p_two_score(p_two_score)
);
hex_decoder h2(
.hex_digit(p_one_score),
.segments(HEX2)
);
endmodule | 0 |
4,458 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module fsm_controller (resetn, p_one, p_two, start, square, p_one_win, p_two_win, blue, red, turn, p_one_score, p_two_score);
input [5:0] square;
input resetn, p_one, p_two, start;
output reg [3:0] p_one_score, p_two_score;
output reg p_one_win, p_two_win;
output reg turn;
output reg [41:0] blue, red;
always @(*)
begin
if(resetn==1'b1)
begin
blue <= 1'b0;
red <= 1'b0;
turn <= 1'b0;
end
else if (start==1'b0)
begin
turn <= 1'b1;
end
else if (start==1'b1 && p_one_win==1'b0 && p_two_win==1'b0)
begin
if (p_one==1'b1)
begin
case(square)
6'b000000: if(turn == 1 && blue[0]==0 && red[0]==0) begin blue[0]<=1; turn<=0; end
6'b000001: if(turn == 1 && blue[1]==0 && red[1]==0) begin blue[1]<=1; turn<=0; end
6'b000010: if(turn == 1 && blue[2]==0 && red[2]==0) begin blue[2]<=1; turn<=0; end
6'b000011: if(turn == 1 && blue[3]==0 && red[3]==0) begin blue[3]<=1; turn<=0; end
6'b000100: if(turn == 1 && blue[4]==0 && red[4]==0) begin blue[4]<=1; turn<=0; end
6'b000101: if(turn == 1 && blue[5]==0 && red[5]==0) begin blue[5]<=1; turn<=0; end
6'b000110: if(turn == 1 && blue[6]==0 && red[6]==0) begin blue[6]<=1; turn<=0; end
6'b000111: if(turn == 1 && blue[7]==0 && red[7]==0) begin blue[7]<=1; turn<=0; end
6'b001000: if(turn == 1 && blue[8]==0 && red[8]==0) begin blue[8]<=1; turn<=0; end
6'b001001: if(turn == 1 && blue[9]==0 && red[9]==0) begin blue[9]<=1; turn<=0; end
6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) begin blue[10]<=1; turn<=0; end
6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) begin blue[11]<=1; turn<=0; end
6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) begin blue[12]<=1; turn<=0; end
6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) begin blue[13]<=1; turn<=0; end
6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) begin blue[14]<=1; turn<=0; end
6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) begin blue[15]<=1; turn<=0; end
6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) begin blue[16]<=1; turn<=0; end
6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) begin blue[17]<=1; turn<=0; end
6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) begin blue[18]<=1; turn<=0; end
6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) begin blue[19]<=1; turn<=0; end
6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) begin blue[20]<=1; turn<=0; end
6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) begin blue[21]<=1; turn<=0; end
6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) begin blue[22]<=1; turn<=0; end
6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) begin blue[23]<=1; turn<=0; end
6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) begin blue[24]<=1; turn<=0; end
6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) begin blue[25]<=1; turn<=0; end
6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) begin blue[26]<=1; turn<=0; end
6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) begin blue[27]<=1; turn<=0; end
6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) begin blue[28]<=1; turn<=0; end
6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) begin blue[29]<=1; turn<=0; end
6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) begin blue[30]<=1; turn<=0; end
6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) begin blue[31]<=1; turn<=0; end
6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) begin blue[32]<=1; turn<=0; end
6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) begin blue[33]<=1; turn<=0; end
6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) begin blue[34]<=1; turn<=0; end
6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) begin blue[35]<=1; turn<=0; end
6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) begin blue[36]<=1; turn<=0; end
6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) begin blue[37]<=1; turn<=0; end
6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) begin blue[38]<=1; turn<=0; end
6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) begin blue[39]<=1; turn<=0; end
6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) begin blue[40]<=1; turn<=0; end
6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) begin blue[41]<=1; turn<=0; end
endcase
end
else
begin
case(square)
6'b000000: if(turn == 1 && blue[0]==0 && red[0]==0) begin red[0]<=1; turn<=0; end
6'b000001: if(turn == 1 && blue[1]==0 && red[1]==0) begin red[1]<=1; turn<=0; end
6'b000010: if(turn == 1 && blue[2]==0 && red[2]==0) begin red[2]<=1; turn<=0; end
6'b000011: if(turn == 1 && blue[3]==0 && red[3]==0) begin red[3]<=1; turn<=0; end
6'b000100: if(turn == 1 && blue[4]==0 && red[4]==0) begin red[4]<=1; turn<=0; end
6'b000101: if(turn == 1 && blue[5]==0 && red[5]==0) begin red[5]<=1; turn<=0; end
6'b000110: if(turn == 1 && blue[6]==0 && red[6]==0) begin red[6]<=1; turn<=0; end
6'b000111: if(turn == 1 && blue[7]==0 && red[7]==0) begin red[7]<=1; turn<=0; end
6'b001000: if(turn == 1 && blue[8]==0 && red[8]==0) begin red[8]<=1; turn<=0; end
6'b001001: if(turn == 1 && blue[9]==0 && red[9]==0) begin red[9]<=1; turn<=0; end
6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) begin red[10]<=1; turn<=0; end
6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) begin red[11]<=1; turn<=0; end
6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) begin red[12]<=1; turn<=0; end
6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) begin red[13]<=1; turn<=0; end
6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) begin red[14]<=1; turn<=0; end
6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) begin red[15]<=1; turn<=0; end
6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) begin red[16]<=1; turn<=0; end
6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) begin red[17]<=1; turn<=0; end
6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) begin red[18]<=1; turn<=0; end
6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) begin red[19]<=1; turn<=0; end
6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) begin red[20]<=1; turn<=0; end
6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) begin red[21]<=1; turn<=0; end
6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) begin red[22]<=1; turn<=0; end
6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) begin red[23]<=1; turn<=0; end
6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) begin red[24]<=1; turn<=0; end
6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) begin red[25]<=1; turn<=0; end
6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) begin red[26]<=1; turn<=0; end
6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) begin red[27]<=1; turn<=0; end
6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) begin red[28]<=1; turn<=0; end
6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) begin red[29]<=1; turn<=0; end
6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) begin red[30]<=1; turn<=0; end
6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) begin red[31]<=1; turn<=0; end
6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) begin red[32]<=1; turn<=0; end
6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) begin red[33]<=1; turn<=0; end
6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) begin red[34]<=1; turn<=0; end
6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) begin red[35]<=1; turn<=0; end
6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) begin red[36]<=1; turn<=0; end
6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) begin red[37]<=1; turn<=0; end
6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) begin red[38]<=1; turn<=0; end
6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) begin red[39]<=1; turn<=0; end
6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) begin red[40]<=1; turn<=0; end
6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) begin red[41]<=1; turn<=0; end
endcase
end
end
end
always @(*)
begin
if(blue[0] == 1 && blue[7] == 1 && blue[14] == 1 && blue[21] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[7] == 1 && blue[14] == 1 && blue[21] == 1 && blue[28] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[14] == 1 && blue[21] == 1 && blue[28] == 1 && blue[35] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[0] == 1 && blue[1] == 1 && blue[2] == 1 && blue[3] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[0] == 1 && blue[8] == 1 && blue[16] == 1 && blue[24] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else
begin p_one_win <= 1'b0; p_one_score <= 1'b0; end
end
always @(*)
begin
if(red[0] == 1 && red[7] == 1 && red[14] == 1 && red[21] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[7] == 1 && red[14] == 1 && red[21] == 1 && red[28] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[14] == 1 && red[21] == 1 && red[28] == 1 && red[35] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[0] == 1 && red[1] == 1 && red[2] == 1 && red[3] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[0] == 1 && red[8] == 1 && red[16] == 1 && red[24] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else
begin p_two_win <= 1'b0; p_two_score <= 1'b1; end
end
endmodule | module fsm_controller (resetn, p_one, p_two, start, square, p_one_win, p_two_win, blue, red, turn, p_one_score, p_two_score); |
input [5:0] square;
input resetn, p_one, p_two, start;
output reg [3:0] p_one_score, p_two_score;
output reg p_one_win, p_two_win;
output reg turn;
output reg [41:0] blue, red;
always @(*)
begin
if(resetn==1'b1)
begin
blue <= 1'b0;
red <= 1'b0;
turn <= 1'b0;
end
else if (start==1'b0)
begin
turn <= 1'b1;
end
else if (start==1'b1 && p_one_win==1'b0 && p_two_win==1'b0)
begin
if (p_one==1'b1)
begin
case(square)
6'b000000: if(turn == 1 && blue[0]==0 && red[0]==0) begin blue[0]<=1; turn<=0; end
6'b000001: if(turn == 1 && blue[1]==0 && red[1]==0) begin blue[1]<=1; turn<=0; end
6'b000010: if(turn == 1 && blue[2]==0 && red[2]==0) begin blue[2]<=1; turn<=0; end
6'b000011: if(turn == 1 && blue[3]==0 && red[3]==0) begin blue[3]<=1; turn<=0; end
6'b000100: if(turn == 1 && blue[4]==0 && red[4]==0) begin blue[4]<=1; turn<=0; end
6'b000101: if(turn == 1 && blue[5]==0 && red[5]==0) begin blue[5]<=1; turn<=0; end
6'b000110: if(turn == 1 && blue[6]==0 && red[6]==0) begin blue[6]<=1; turn<=0; end
6'b000111: if(turn == 1 && blue[7]==0 && red[7]==0) begin blue[7]<=1; turn<=0; end
6'b001000: if(turn == 1 && blue[8]==0 && red[8]==0) begin blue[8]<=1; turn<=0; end
6'b001001: if(turn == 1 && blue[9]==0 && red[9]==0) begin blue[9]<=1; turn<=0; end
6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) begin blue[10]<=1; turn<=0; end
6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) begin blue[11]<=1; turn<=0; end
6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) begin blue[12]<=1; turn<=0; end
6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) begin blue[13]<=1; turn<=0; end
6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) begin blue[14]<=1; turn<=0; end
6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) begin blue[15]<=1; turn<=0; end
6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) begin blue[16]<=1; turn<=0; end
6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) begin blue[17]<=1; turn<=0; end
6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) begin blue[18]<=1; turn<=0; end
6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) begin blue[19]<=1; turn<=0; end
6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) begin blue[20]<=1; turn<=0; end
6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) begin blue[21]<=1; turn<=0; end
6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) begin blue[22]<=1; turn<=0; end
6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) begin blue[23]<=1; turn<=0; end
6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) begin blue[24]<=1; turn<=0; end
6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) begin blue[25]<=1; turn<=0; end
6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) begin blue[26]<=1; turn<=0; end
6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) begin blue[27]<=1; turn<=0; end
6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) begin blue[28]<=1; turn<=0; end
6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) begin blue[29]<=1; turn<=0; end
6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) begin blue[30]<=1; turn<=0; end
6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) begin blue[31]<=1; turn<=0; end
6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) begin blue[32]<=1; turn<=0; end
6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) begin blue[33]<=1; turn<=0; end
6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) begin blue[34]<=1; turn<=0; end
6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) begin blue[35]<=1; turn<=0; end
6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) begin blue[36]<=1; turn<=0; end
6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) begin blue[37]<=1; turn<=0; end
6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) begin blue[38]<=1; turn<=0; end
6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) begin blue[39]<=1; turn<=0; end
6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) begin blue[40]<=1; turn<=0; end
6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) begin blue[41]<=1; turn<=0; end
endcase
end
else
begin
case(square)
6'b000000: if(turn == 1 && blue[0]==0 && red[0]==0) begin red[0]<=1; turn<=0; end
6'b000001: if(turn == 1 && blue[1]==0 && red[1]==0) begin red[1]<=1; turn<=0; end
6'b000010: if(turn == 1 && blue[2]==0 && red[2]==0) begin red[2]<=1; turn<=0; end
6'b000011: if(turn == 1 && blue[3]==0 && red[3]==0) begin red[3]<=1; turn<=0; end
6'b000100: if(turn == 1 && blue[4]==0 && red[4]==0) begin red[4]<=1; turn<=0; end
6'b000101: if(turn == 1 && blue[5]==0 && red[5]==0) begin red[5]<=1; turn<=0; end
6'b000110: if(turn == 1 && blue[6]==0 && red[6]==0) begin red[6]<=1; turn<=0; end
6'b000111: if(turn == 1 && blue[7]==0 && red[7]==0) begin red[7]<=1; turn<=0; end
6'b001000: if(turn == 1 && blue[8]==0 && red[8]==0) begin red[8]<=1; turn<=0; end
6'b001001: if(turn == 1 && blue[9]==0 && red[9]==0) begin red[9]<=1; turn<=0; end
6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) begin red[10]<=1; turn<=0; end
6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) begin red[11]<=1; turn<=0; end
6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) begin red[12]<=1; turn<=0; end
6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) begin red[13]<=1; turn<=0; end
6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) begin red[14]<=1; turn<=0; end
6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) begin red[15]<=1; turn<=0; end
6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) begin red[16]<=1; turn<=0; end
6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) begin red[17]<=1; turn<=0; end
6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) begin red[18]<=1; turn<=0; end
6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) begin red[19]<=1; turn<=0; end
6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) begin red[20]<=1; turn<=0; end
6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) begin red[21]<=1; turn<=0; end
6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) begin red[22]<=1; turn<=0; end
6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) begin red[23]<=1; turn<=0; end
6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) begin red[24]<=1; turn<=0; end
6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) begin red[25]<=1; turn<=0; end
6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) begin red[26]<=1; turn<=0; end
6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) begin red[27]<=1; turn<=0; end
6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) begin red[28]<=1; turn<=0; end
6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) begin red[29]<=1; turn<=0; end
6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) begin red[30]<=1; turn<=0; end
6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) begin red[31]<=1; turn<=0; end
6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) begin red[32]<=1; turn<=0; end
6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) begin red[33]<=1; turn<=0; end
6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) begin red[34]<=1; turn<=0; end
6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) begin red[35]<=1; turn<=0; end
6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) begin red[36]<=1; turn<=0; end
6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) begin red[37]<=1; turn<=0; end
6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) begin red[38]<=1; turn<=0; end
6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) begin red[39]<=1; turn<=0; end
6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) begin red[40]<=1; turn<=0; end
6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) begin red[41]<=1; turn<=0; end
endcase
end
end
end
always @(*)
begin
if(blue[0] == 1 && blue[7] == 1 && blue[14] == 1 && blue[21] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[7] == 1 && blue[14] == 1 && blue[21] == 1 && blue[28] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[14] == 1 && blue[21] == 1 && blue[28] == 1 && blue[35] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[0] == 1 && blue[1] == 1 && blue[2] == 1 && blue[3] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else if (blue[0] == 1 && blue[8] == 1 && blue[16] == 1 && blue[24] == 1)
begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
else
begin p_one_win <= 1'b0; p_one_score <= 1'b0; end
end
always @(*)
begin
if(red[0] == 1 && red[7] == 1 && red[14] == 1 && red[21] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[7] == 1 && red[14] == 1 && red[21] == 1 && red[28] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[14] == 1 && red[21] == 1 && red[28] == 1 && red[35] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[0] == 1 && red[1] == 1 && red[2] == 1 && red[3] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else if (red[0] == 1 && red[8] == 1 && red[16] == 1 && red[24] == 1)
begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
else
begin p_two_win <= 1'b0; p_two_score <= 1'b1; end
end
endmodule | 0 |
4,459 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module datapath(data_in, clock, reset_n, p_1, p_2, enable, X, Y, Colour);
input reset_n, enable, clock, p_1, p_2;
input [5:0] data_in;
output [8:0] X;
output [7:0] Y;
output [2:0] Colour;
reg [8:0] x1;
reg [7:0] y1;
reg [2:0] c1;
wire [3:0] controlA, controlB, controlC;
always @ (posedge clock) begin
if (!reset_n) begin
x1 <= 8'b0;
y1 <= 7'b0;
c1 <= 3'b0;
end
else begin
if (p_1) begin
c1 <= 100;
end
if (p_2) begin
c1 <= 001;
end
if (data_in == 6'b000000) begin
x1 <= 8'b00000010;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000001) begin
x1 <= 8'b00011000;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000010) begin
x1 <= 8'b00101110;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000011) begin
x1 <= 8'b01000100;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000100) begin
x1 <= 8'b01011010;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000101) begin
x1 <= 8'b01110000;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000110) begin
x1 <= 8'b10000110;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000111) begin
x1 <= 8'b00000010;
y1 <= 7'b0010110;
end
else if (data_in == 6'b001000) begin
x1 <= 8'b00011000;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001001) begin
x1 <= 8'b00101110;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001010) begin
x1 <= 8'b01000100;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001011) begin
x1 <= 8'b01011010;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001100) begin
x1 <= 8'b01110000;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001101) begin
x1 <= 8'b10000110;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001110) begin
x1 <= 8'b00000010;
y1 <= 7'b0101010;
end
else if (data_in == 6'b001111) begin
x1 <= 8'b00011000;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010000) begin
x1 <= 8'b00101110;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010001) begin
x1 <= 8'b01000100;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010010) begin
x1 <= 8'b01011010;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010011) begin
x1 <= 8'b01110000;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010100) begin
x1 <= 8'b10000110;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010101) begin
x1 <= 8'b00000010;
y1 <= 7'b0111110;
end
else if (data_in == 6'b010110) begin
x1 <= 8'b00011000;
y1 <= 7'b0111011;
end
else if (data_in == 6'b010111) begin
x1 <= 8'b00101110;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011000) begin
x1 <= 8'b01000100;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011001) begin
x1 <= 8'b01011010;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011010) begin
x1 <= 8'b01110000;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011011) begin
x1 <= 8'b10000110;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011100) begin
x1 <= 8'b00000010;
y1 <= 7'b1010001;
end
else if (data_in == 6'b011101) begin
x1 <= 8'b00011000;
y1 <= 7'b1001110;
end
else if (data_in == 6'b011110) begin
x1 <= 8'b00101110;
y1 <= 7'b1001110;
end
else if (data_in == 6'b011111) begin
x1 <= 8'b01000100;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100000) begin
x1 <= 8'b01011010;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100001) begin
x1 <= 8'b01110000;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100010) begin
x1 <= 8'b10000110;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100011) begin
x1 <= 8'b00000010;
y1 <= 7'b1100101;
end
else if (data_in == 6'b100100) begin
x1 <= 8'b00011000;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100101) begin
x1 <= 8'b00101110;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100110) begin
x1 <= 8'b01000100;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100111) begin
x1 <= 8'b01011010;
y1 <= 7'b1100001;
end
else if (data_in == 6'b101000) begin
x1 <= 8'b01110000;
y1 <= 7'b1100001;
end
else if (data_in == 6'b101001) begin
x1 <= 8'b10000110;
y1 <= 7'b1100001;
end
end
end
counter m0 (clock, reset_n, enable, controlA);
rate_counter m1 (clock, reset_n, enable, controlB);
assign enable_1 = (controlB == 2'b00) ? 1 : 0;
counter m2 (clock, reset_n, enable_1, controlC);
assign X = x1 + controlA;
assign Y = y1 + controlC;
assign Colour = c1;
endmodule | module datapath(data_in, clock, reset_n, p_1, p_2, enable, X, Y, Colour); |
input reset_n, enable, clock, p_1, p_2;
input [5:0] data_in;
output [8:0] X;
output [7:0] Y;
output [2:0] Colour;
reg [8:0] x1;
reg [7:0] y1;
reg [2:0] c1;
wire [3:0] controlA, controlB, controlC;
always @ (posedge clock) begin
if (!reset_n) begin
x1 <= 8'b0;
y1 <= 7'b0;
c1 <= 3'b0;
end
else begin
if (p_1) begin
c1 <= 100;
end
if (p_2) begin
c1 <= 001;
end
if (data_in == 6'b000000) begin
x1 <= 8'b00000010;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000001) begin
x1 <= 8'b00011000;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000010) begin
x1 <= 8'b00101110;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000011) begin
x1 <= 8'b01000100;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000100) begin
x1 <= 8'b01011010;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000101) begin
x1 <= 8'b01110000;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000110) begin
x1 <= 8'b10000110;
y1 <= 7'b0000010;
end
else if (data_in == 6'b000111) begin
x1 <= 8'b00000010;
y1 <= 7'b0010110;
end
else if (data_in == 6'b001000) begin
x1 <= 8'b00011000;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001001) begin
x1 <= 8'b00101110;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001010) begin
x1 <= 8'b01000100;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001011) begin
x1 <= 8'b01011010;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001100) begin
x1 <= 8'b01110000;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001101) begin
x1 <= 8'b10000110;
y1 <= 7'b0010101;
end
else if (data_in == 6'b001110) begin
x1 <= 8'b00000010;
y1 <= 7'b0101010;
end
else if (data_in == 6'b001111) begin
x1 <= 8'b00011000;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010000) begin
x1 <= 8'b00101110;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010001) begin
x1 <= 8'b01000100;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010010) begin
x1 <= 8'b01011010;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010011) begin
x1 <= 8'b01110000;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010100) begin
x1 <= 8'b10000110;
y1 <= 7'b0101000;
end
else if (data_in == 6'b010101) begin
x1 <= 8'b00000010;
y1 <= 7'b0111110;
end
else if (data_in == 6'b010110) begin
x1 <= 8'b00011000;
y1 <= 7'b0111011;
end
else if (data_in == 6'b010111) begin
x1 <= 8'b00101110;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011000) begin
x1 <= 8'b01000100;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011001) begin
x1 <= 8'b01011010;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011010) begin
x1 <= 8'b01110000;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011011) begin
x1 <= 8'b10000110;
y1 <= 7'b0111011;
end
else if (data_in == 6'b011100) begin
x1 <= 8'b00000010;
y1 <= 7'b1010001;
end
else if (data_in == 6'b011101) begin
x1 <= 8'b00011000;
y1 <= 7'b1001110;
end
else if (data_in == 6'b011110) begin
x1 <= 8'b00101110;
y1 <= 7'b1001110;
end
else if (data_in == 6'b011111) begin
x1 <= 8'b01000100;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100000) begin
x1 <= 8'b01011010;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100001) begin
x1 <= 8'b01110000;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100010) begin
x1 <= 8'b10000110;
y1 <= 7'b1001110;
end
else if (data_in == 6'b100011) begin
x1 <= 8'b00000010;
y1 <= 7'b1100101;
end
else if (data_in == 6'b100100) begin
x1 <= 8'b00011000;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100101) begin
x1 <= 8'b00101110;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100110) begin
x1 <= 8'b01000100;
y1 <= 7'b1100001;
end
else if (data_in == 6'b100111) begin
x1 <= 8'b01011010;
y1 <= 7'b1100001;
end
else if (data_in == 6'b101000) begin
x1 <= 8'b01110000;
y1 <= 7'b1100001;
end
else if (data_in == 6'b101001) begin
x1 <= 8'b10000110;
y1 <= 7'b1100001;
end
end
end
counter m0 (clock, reset_n, enable, controlA);
rate_counter m1 (clock, reset_n, enable, controlB);
assign enable_1 = (controlB == 2'b00) ? 1 : 0;
counter m2 (clock, reset_n, enable_1, controlC);
assign X = x1 + controlA;
assign Y = y1 + controlC;
assign Colour = c1;
endmodule | 0 |
4,460 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module counter(clock, reset_n, enable, q);
input clock, reset_n, enable;
output reg [3:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) begin
q <= 4'b0000;
end
else if (enable == 1'b1) begin
if (q == 4'b1111) begin
q <= 4'b0000;
end
else begin
q <= q + 3'b111;
end
end
end
endmodule | module counter(clock, reset_n, enable, q); |
input clock, reset_n, enable;
output reg [3:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) begin
q <= 4'b0000;
end
else if (enable == 1'b1) begin
if (q == 4'b1111) begin
q <= 4'b0000;
end
else begin
q <= q + 3'b111;
end
end
end
endmodule | 0 |
4,461 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module rate_counter(clock, reset_n, enable, q);
input clock, reset_n, enable;
output reg [3:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) begin
q <= 4'b1111;
end
else if (enable == 1'b1) begin
if (q == 4'b0000) begin
q <= 4'b1111;
end
else begin
q <= q - 3'b111;
end
end
end
endmodule | module rate_counter(clock, reset_n, enable, q); |
input clock, reset_n, enable;
output reg [3:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) begin
q <= 4'b1111;
end
else if (enable == 1'b1) begin
if (q == 4'b0000) begin
q <= 4'b1111;
end
else begin
q <= q - 3'b111;
end
end
end
endmodule | 0 |
4,462 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module control (go_p1, go_p2, reset_n, clock, enable, plot);
input go_p1, go_p2, reset_n, clock;
output reg enable, plot;
always@(*) begin
enable = 1'b0;
plot = 1'b0;
if (go_p1 || go_p2) begin
plot = 1'b1;
enable = 1'b1;
end
end
endmodule | module control (go_p1, go_p2, reset_n, clock, enable, plot); |
input go_p1, go_p2, reset_n, clock;
output reg enable, plot;
always@(*) begin
enable = 1'b0;
plot = 1'b0;
if (go_p1 || go_p2) begin
plot = 1'b1;
enable = 1'b1;
end
end
endmodule | 0 |
4,463 | data/full_repos/permissive/110056451/plotfour_top.v | 110,056,451 | plotfour_top.v | v | 622 | 126 | [] | [] | [] | null | line:74: before: "." | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n : ... In instance plotfour_top.d0\n c1 <= 100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0010101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0101000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b0111011;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1010001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1001110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00000010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100101;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00011000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b00101110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01000100;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01011010;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b01110000;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n : ... In instance plotfour_top.d0\n x1 <= 8\'b10000110;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n : ... In instance plotfour_top.d0\n y1 <= 7\'b1100001;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n blue <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n red <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance plotfour_top.fsm\n begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] KEY; \n ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output [0:4] LEDR; \n ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n : ... In instance plotfour_top\n datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_one_score(p_one_score),\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n : ... In instance plotfour_top\n .p_two_score(p_two_score)\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n : ... In instance plotfour_top\n .hex_digit(p_one_score),\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n' | 2,711 | module | module hex_decoder(hex_digit, segments);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
begin
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
end
endmodule | module hex_decoder(hex_digit, segments); |
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
begin
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
end
endmodule | 0 |
4,464 | data/full_repos/permissive/110056451/KeyboardFiles/keyboard_press_driver.v | 110,056,451 | keyboard_press_driver.v | v | 95 | 64 | [] | [] | [] | [(1, 94)] | null | null | 1: b"%Error: data/full_repos/permissive/110056451/KeyboardFiles/keyboard_press_driver.v:30: Cannot find file containing module: 'keyboard_inner_driver'\nkeyboard_inner_driver kbd(\n^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/keyboard_inner_driver\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/keyboard_inner_driver.v\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/keyboard_inner_driver.sv\n keyboard_inner_driver\n keyboard_inner_driver.v\n keyboard_inner_driver.sv\n obj_dir/keyboard_inner_driver\n obj_dir/keyboard_inner_driver.v\n obj_dir/keyboard_inner_driver.sv\n%Error: Exiting due to 1 error(s)\n" | 2,717 | module | module keyboard_press_driver(
input CLOCK_50,
output reg valid, makeBreak,
output reg [7:0] outCode,
input PS2_DAT,
input PS2_CLK,
input reset
);
parameter FIRST = 1'b0, SEENF0 = 1'b1;
reg state;
reg [1:0] count;
wire [7:0] scan_code;
reg [7:0] filter_scan;
wire scan_ready;
reg read;
parameter NULL = 8'h00;
initial
begin
state = FIRST;
filter_scan = NULL;
read = 1'b0;
count = 2'b00;
end
keyboard_inner_driver kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
always @(posedge CLOCK_50)
case(count)
2'b00:
if(scan_ready)
count <= 2'b01;
2'b01:
if(scan_ready)
count <= 2'b10;
2'b10:
begin
read <= 1'b1;
count <= 2'b11;
valid <= 0;
outCode <= scan_code;
case(state)
FIRST:
case(scan_code)
8'hF0:
begin
state <= SEENF0;
end
8'hE0:
begin
state <= FIRST;
end
default:
begin
filter_scan <= scan_code;
if(filter_scan != scan_code)
begin
valid <= 1'b1;
makeBreak <= 1'b1;
end
end
endcase
SEENF0:
begin
state <= FIRST;
if(filter_scan == scan_code)
begin
filter_scan <= NULL;
end
valid <= 1'b1;
makeBreak <= 1'b0;
end
endcase
end
2'b11:
begin
read <= 1'b0;
count <= 2'b00;
valid <= 0;
end
endcase
endmodule | module keyboard_press_driver(
input CLOCK_50,
output reg valid, makeBreak,
output reg [7:0] outCode,
input PS2_DAT,
input PS2_CLK,
input reset
); |
parameter FIRST = 1'b0, SEENF0 = 1'b1;
reg state;
reg [1:0] count;
wire [7:0] scan_code;
reg [7:0] filter_scan;
wire scan_ready;
reg read;
parameter NULL = 8'h00;
initial
begin
state = FIRST;
filter_scan = NULL;
read = 1'b0;
count = 2'b00;
end
keyboard_inner_driver kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
always @(posedge CLOCK_50)
case(count)
2'b00:
if(scan_ready)
count <= 2'b01;
2'b01:
if(scan_ready)
count <= 2'b10;
2'b10:
begin
read <= 1'b1;
count <= 2'b11;
valid <= 0;
outCode <= scan_code;
case(state)
FIRST:
case(scan_code)
8'hF0:
begin
state <= SEENF0;
end
8'hE0:
begin
state <= FIRST;
end
default:
begin
filter_scan <= scan_code;
if(filter_scan != scan_code)
begin
valid <= 1'b1;
makeBreak <= 1'b1;
end
end
endcase
SEENF0:
begin
state <= FIRST;
if(filter_scan == scan_code)
begin
filter_scan <= NULL;
end
valid <= 1'b1;
makeBreak <= 1'b0;
end
endcase
end
2'b11:
begin
read <= 1'b0;
count <= 2'b00;
valid <= 0;
end
endcase
endmodule | 0 |
4,465 | data/full_repos/permissive/110056451/KeyboardFiles/keyboard_scancoderaw_driver.v | 110,056,451 | keyboard_scancoderaw_driver.v | v | 31 | 73 | [] | [] | [] | [(1, 31)] | null | null | 1: b"%Error: data/full_repos/permissive/110056451/KeyboardFiles/keyboard_scancoderaw_driver.v:13: Cannot find file containing module: 'oneshot'\noneshot pulser(\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/oneshot\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/oneshot.v\n data/full_repos/permissive/110056451/KeyboardFiles,data/full_repos/permissive/110056451/oneshot.sv\n oneshot\n oneshot.v\n oneshot.sv\n obj_dir/oneshot\n obj_dir/oneshot.v\n obj_dir/oneshot.sv\n%Error: data/full_repos/permissive/110056451/KeyboardFiles/keyboard_scancoderaw_driver.v:21: Cannot find file containing module: 'keyboard_inner_driver'\nkeyboard_inner_driver kbd(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,718 | module | module keyboard_scancoderaw_driver(
input CLOCK_50,
output scan_ready,
output [7:0] scan_code,
input PS2_DAT,
input PS2_CLK,
input reset
);
wire read;
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
keyboard_inner_driver kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
endmodule | module keyboard_scancoderaw_driver(
input CLOCK_50,
output scan_ready,
output [7:0] scan_code,
input PS2_DAT,
input PS2_CLK,
input reset
); |
wire read;
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
keyboard_inner_driver kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
endmodule | 0 |
4,466 | data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v | 110,143,902 | counter.v | v | 92 | 78 | [] | ['apache license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v:42: Cannot find file containing module: 'd_trig'\n d_trig #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig.v\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig.sv\n d_trig\n d_trig.v\n d_trig.sv\n obj_dir/d_trig\n obj_dir/d_trig.v\n obj_dir/d_trig.sv\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v:54: Cannot find file containing module: 'd_trig'\n d_trig #(\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,723 | module | module counter (
DCLR, C, CLR,
Q, notQ,
overflow
);
parameter DATA_WIDTH = 4;
parameter CLEAR_VAL = 1;
input wire [DATA_WIDTH - 1 : 0] DCLR;
input wire C, CLR;
output wire [DATA_WIDTH - 1 : 0] Q, notQ;
output reg overflow;
wire [DATA_WIDTH - 1 : 0] d_trig_Q, d_trig_notQ;
reg [DATA_WIDTH - 1 : 0] d_trig_Q_neg;
genvar i;
integer j;
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
if(i == 0) begin
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
) d_trig_0 (
.D(d_trig_Q[0]),
.DCLR(DCLR[0]),
.C(C),
.CLR(CLR),
.Q(d_trig_notQ[0]),
.notQ(d_trig_Q[0])
);
end
else begin
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
) d_trig_i (
.D(d_trig_Q[i]),
.DCLR(DCLR[i]),
.C(d_trig_Q[i - 1]),
.CLR(CLR),
.Q(d_trig_notQ[i]),
.notQ(d_trig_Q[i])
);
end
end
endgenerate
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
assign Q[i] = d_trig_notQ[i];
assign notQ[i] = d_trig_Q[i];
end
endgenerate
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
always @(d_trig_Q[i]) begin
if(d_trig_Q[i])
d_trig_Q_neg[i] <= 1;
else
d_trig_Q_neg[i] <= 0;
end
end
endgenerate
always @* begin
overflow = 1'b1;
for(j = 0; j < DATA_WIDTH; j = j + 1)
overflow = overflow & d_trig_Q_neg[j];
end
endmodule | module counter (
DCLR, C, CLR,
Q, notQ,
overflow
); |
parameter DATA_WIDTH = 4;
parameter CLEAR_VAL = 1;
input wire [DATA_WIDTH - 1 : 0] DCLR;
input wire C, CLR;
output wire [DATA_WIDTH - 1 : 0] Q, notQ;
output reg overflow;
wire [DATA_WIDTH - 1 : 0] d_trig_Q, d_trig_notQ;
reg [DATA_WIDTH - 1 : 0] d_trig_Q_neg;
genvar i;
integer j;
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
if(i == 0) begin
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
) d_trig_0 (
.D(d_trig_Q[0]),
.DCLR(DCLR[0]),
.C(C),
.CLR(CLR),
.Q(d_trig_notQ[0]),
.notQ(d_trig_Q[0])
);
end
else begin
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
) d_trig_i (
.D(d_trig_Q[i]),
.DCLR(DCLR[i]),
.C(d_trig_Q[i - 1]),
.CLR(CLR),
.Q(d_trig_notQ[i]),
.notQ(d_trig_Q[i])
);
end
end
endgenerate
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
assign Q[i] = d_trig_notQ[i];
assign notQ[i] = d_trig_Q[i];
end
endgenerate
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
always @(d_trig_Q[i]) begin
if(d_trig_Q[i])
d_trig_Q_neg[i] <= 1;
else
d_trig_Q_neg[i] <= 0;
end
end
endgenerate
always @* begin
overflow = 1'b1;
for(j = 0; j < DATA_WIDTH; j = j + 1)
overflow = overflow & d_trig_Q_neg[j];
end
endmodule | 0 |
4,467 | data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/d_trig.v | 110,143,902 | d_trig.v | v | 42 | 78 | [] | ['apache license'] | [] | [(15, 42)] | null | data/verilator_xmls/0a5bd9a5-192c-4d55-8f5f-9211055466f6.xml | null | 2,724 | module | module d_trig(
D, DCLR, C, CLR,
Q, notQ
);
parameter CLEAR_VAL = 1;
input wire D, DCLR, C, CLR;
output wire Q, notQ;
reg Q_reg = 0;
always @(posedge C or posedge CLR) begin
if(CLR == CLEAR_VAL)
Q_reg <= DCLR;
else
Q_reg <= D;
end
assign Q = Q_reg;
assign notQ = !Q_reg;
endmodule | module d_trig(
D, DCLR, C, CLR,
Q, notQ
); |
parameter CLEAR_VAL = 1;
input wire D, DCLR, C, CLR;
output wire Q, notQ;
reg Q_reg = 0;
always @(posedge C or posedge CLR) begin
if(CLR == CLEAR_VAL)
Q_reg <= DCLR;
else
Q_reg <= D;
end
assign Q = Q_reg;
assign notQ = !Q_reg;
endmodule | 0 |
4,468 | data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v | 110,143,902 | counter_testbench.v | v | 53 | 78 | [] | ['apache license'] | [] | null | line:18: before: "reg" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 C = !C;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #4 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n #4 CLR = ~CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #36 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #4 CLR = ~CLEAR_VAL;\n ^\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:25: Cannot find file containing module: \'counter\'\n counter #(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter.v\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter.sv\n counter\n counter.v\n counter.sv\n obj_dir/counter\n obj_dir/counter.v\n obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,725 | module | module counter_testbench ( );
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] CLEAR_DATA = 0;
parameter CLEAR_VAL = 1;
reg C, CLR;
wire [DATA_WIDTH - 1 : 0] Q, notQ;
wire overflow;
counter #(
.DATA_WIDTH(DATA_WIDTH),
.CLEAR_VAL(CLEAR_VAL)
) counter_i (
.DCLR(CLEAR_DATA),
.C(C),
.CLR(CLR),
.Q(Q),
.notQ(notQ),
.overflow(overflow)
);
always
#5 C = !C;
initial begin
C = 0;
CLR = ~CLEAR_VAL;
#4 CLR = CLEAR_VAL;
#4 CLR = ~CLEAR_VAL;
#36 CLR = CLEAR_VAL;
#4 CLR = ~CLEAR_VAL;
end
endmodule | module counter_testbench ( ); |
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] CLEAR_DATA = 0;
parameter CLEAR_VAL = 1;
reg C, CLR;
wire [DATA_WIDTH - 1 : 0] Q, notQ;
wire overflow;
counter #(
.DATA_WIDTH(DATA_WIDTH),
.CLEAR_VAL(CLEAR_VAL)
) counter_i (
.DCLR(CLEAR_DATA),
.C(C),
.CLR(CLR),
.Q(Q),
.notQ(notQ),
.overflow(overflow)
);
always
#5 C = !C;
initial begin
C = 0;
CLR = ~CLEAR_VAL;
#4 CLR = CLEAR_VAL;
#4 CLR = ~CLEAR_VAL;
#36 CLR = CLEAR_VAL;
#4 CLR = ~CLEAR_VAL;
end
endmodule | 0 |
4,469 | data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v | 110,143,902 | d_trig_testbench.v | v | 57 | 78 | [] | ['apache license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 C = !C;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #30 D = !D;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = ~CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #40 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = ~CLEAR_VAL;\n ^\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:23: Cannot find file containing module: \'d_trig\'\n d_trig #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig.v\n data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig.sv\n d_trig\n d_trig.v\n d_trig.sv\n obj_dir/d_trig\n obj_dir/d_trig.v\n obj_dir/d_trig.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,726 | module | module d_trig_testbench ( );
parameter reg CLEAR_DATA = 0;
parameter CLEAR_VAL = 1;
reg D, DCLR, C, CLR;
wire Q, notQ;
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
)
d_trig_i (
.D(D),
.DCLR(CLEAR_DATA),
.C(C),
.CLR(CLR),
.Q(Q),
.notQ(notQ)
);
always
#5 C = !C;
always
#30 D = !D;
initial begin
D = 0;
C = 0;
CLR = ~CLEAR_VAL;
#2 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#40 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
end
endmodule | module d_trig_testbench ( ); |
parameter reg CLEAR_DATA = 0;
parameter CLEAR_VAL = 1;
reg D, DCLR, C, CLR;
wire Q, notQ;
d_trig #(
.CLEAR_VAL(CLEAR_VAL)
)
d_trig_i (
.D(D),
.DCLR(CLEAR_DATA),
.C(C),
.CLR(CLR),
.Q(Q),
.notQ(notQ)
);
always
#5 C = !C;
always
#30 D = !D;
initial begin
D = 0;
C = 0;
CLR = ~CLEAR_VAL;
#2 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#40 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
end
endmodule | 0 |
4,470 | data/full_repos/permissive/110143902/projects/reg_async_reset/src/design/reg.v | 110,143,902 | reg.v | v | 49 | 78 | [] | ['apache license'] | [] | null | line:22: before: "reg" | null | 1: b"%Error: data/full_repos/permissive/110143902/projects/reg_async_reset/src/design/reg.v:36: Cannot find file containing module: 'd_trig'\n d_trig #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig.v\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig.sv\n d_trig\n d_trig.v\n d_trig.sv\n obj_dir/d_trig\n obj_dir/d_trig.v\n obj_dir/d_trig.sv\n%Error: Exiting due to 1 error(s)\n" | 2,734 | module | module register (
D, C, CLR,
Q
);
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter CLEAR_VAL = 1;
input wire [DATA_WIDTH - 1 : 0] D;
input wire C, CLR;
output wire [DATA_WIDTH - 1 : 0] Q;
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
d_trig #(
.INIT_VAL(INIT_VAL[i]),
.CLEAR_VAL(CLEAR_VAL)
) d_trig_i (
.D(D[i]),
.C(C),
.CLR(CLR),
.Q(Q[i]),
.notQ()
);
end
endgenerate
endmodule | module register (
D, C, CLR,
Q
); |
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter CLEAR_VAL = 1;
input wire [DATA_WIDTH - 1 : 0] D;
input wire C, CLR;
output wire [DATA_WIDTH - 1 : 0] Q;
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i + 1) begin
d_trig #(
.INIT_VAL(INIT_VAL[i]),
.CLEAR_VAL(CLEAR_VAL)
) d_trig_i (
.D(D[i]),
.C(C),
.CLR(CLR),
.Q(Q[i]),
.notQ()
);
end
endgenerate
endmodule | 0 |
4,471 | data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v | 110,143,902 | reg_testbench.v | v | 60 | 78 | [] | ['apache license'] | [] | null | line:18: before: "reg" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 C = !C;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = ~CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #57 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = ~CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n #42 CLR = CLEAR_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n #2 CLR = ~CLEAR_VAL;\n ^\n%Error: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:25: Cannot find file containing module: \'register\'\n register #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register.v\n data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,736 | module | module register_testbench ( );
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter CLEAR_VAL = 1;
reg [DATA_WIDTH - 1 : 0] D;
reg C, CLR;
wire [DATA_WIDTH - 1 : 0] Q;
register #(
.DATA_WIDTH(DATA_WIDTH),
.INIT_VAL(INIT_VAL),
.CLEAR_VAL(CLEAR_VAL)
) register_i (
.D(D),
.C(C),
.CLR(CLR),
.Q(Q)
);
always
#5 C = !C;
always @(posedge C)
D <= D + 1;
initial begin
D = INIT_VAL;
C = 0;
CLR = ~CLEAR_VAL;
#2 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#57 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#42 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
end
endmodule | module register_testbench ( ); |
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter CLEAR_VAL = 1;
reg [DATA_WIDTH - 1 : 0] D;
reg C, CLR;
wire [DATA_WIDTH - 1 : 0] Q;
register #(
.DATA_WIDTH(DATA_WIDTH),
.INIT_VAL(INIT_VAL),
.CLEAR_VAL(CLEAR_VAL)
) register_i (
.D(D),
.C(C),
.CLR(CLR),
.Q(Q)
);
always
#5 C = !C;
always @(posedge C)
D <= D + 1;
initial begin
D = INIT_VAL;
C = 0;
CLR = ~CLEAR_VAL;
#2 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#57 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
#42 CLR = CLEAR_VAL;
#2 CLR = ~CLEAR_VAL;
end
endmodule | 0 |
4,472 | data/full_repos/permissive/110143902/projects/reg_sync_reset/src/design/d_trig.v | 110,143,902 | d_trig.v | v | 44 | 78 | [] | ['apache license'] | [] | [(15, 43)] | null | data/verilator_xmls/e5c3669f-1894-497f-9292-c0585881c870.xml | null | 2,737 | module | module d_trig(
D, C, R,
Q, notQ
);
parameter INIT_VAL = 0;
parameter RESET_VAL = 1;
input wire D, C, R;
output wire Q, notQ;
reg Q_reg = INIT_VAL;
always @(posedge C) begin
if(R == RESET_VAL)
Q_reg <= INIT_VAL;
else
Q_reg <= D;
end
assign Q = Q_reg;
assign notQ = !Q_reg;
endmodule | module d_trig(
D, C, R,
Q, notQ
); |
parameter INIT_VAL = 0;
parameter RESET_VAL = 1;
input wire D, C, R;
output wire Q, notQ;
reg Q_reg = INIT_VAL;
always @(posedge C) begin
if(R == RESET_VAL)
Q_reg <= INIT_VAL;
else
Q_reg <= D;
end
assign Q = Q_reg;
assign notQ = !Q_reg;
endmodule | 0 |
4,473 | data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v | 110,143,902 | d_trig_testbench.v | v | 57 | 78 | [] | ['apache license'] | [] | [(15, 57)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 C = !C;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #30 D = !D;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 R = RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2 R = ~RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #40 R = RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 R = ~RESET_VAL;\n ^\n%Error: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/d_trig_testbench.v:23: Cannot find file containing module: \'d_trig\'\n d_trig #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/d_trig\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/d_trig.v\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/d_trig.sv\n d_trig\n d_trig.v\n d_trig.sv\n obj_dir/d_trig\n obj_dir/d_trig.v\n obj_dir/d_trig.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,739 | module | module d_trig_testbench ( );
parameter INIT_VAL = 0;
parameter RESET_VAL = 1;
reg D, C, R;
wire Q, notQ;
d_trig #(
.INIT_VAL(INIT_VAL),
.RESET_VAL(RESET_VAL)
)
d_trig_i (
.D(D),
.C(C),
.R(R),
.Q(Q),
.notQ(notQ)
);
always
#5 C = !C;
always
#30 D = !D;
initial begin
D = INIT_VAL;
C = 0;
R = ~RESET_VAL;
#2 R = RESET_VAL;
#2 R = ~RESET_VAL;
#40 R = RESET_VAL;
#2 R = ~RESET_VAL;
end
endmodule | module d_trig_testbench ( ); |
parameter INIT_VAL = 0;
parameter RESET_VAL = 1;
reg D, C, R;
wire Q, notQ;
d_trig #(
.INIT_VAL(INIT_VAL),
.RESET_VAL(RESET_VAL)
)
d_trig_i (
.D(D),
.C(C),
.R(R),
.Q(Q),
.notQ(notQ)
);
always
#5 C = !C;
always
#30 D = !D;
initial begin
D = INIT_VAL;
C = 0;
R = ~RESET_VAL;
#2 R = RESET_VAL;
#2 R = ~RESET_VAL;
#40 R = RESET_VAL;
#2 R = ~RESET_VAL;
end
endmodule | 0 |
4,474 | data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v | 110,143,902 | reg_testbench.v | v | 57 | 78 | [] | ['apache license'] | [] | null | line:18: before: "reg" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 C = !C;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 R = RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #2 R = ~RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n #40 R = RESET_VAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 R = ~RESET_VAL;\n ^\n%Error: data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation/reg_testbench.v:25: Cannot find file containing module: \'register\'\n register #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/register\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/register.v\n data/full_repos/permissive/110143902/projects/reg_sync_reset/src/simulation,data/full_repos/permissive/110143902/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,740 | module | module register_testbench ( );
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter RESET_VAL = 1;
reg [DATA_WIDTH - 1 : 0] D;
reg C, R;
wire [DATA_WIDTH - 1 : 0] Q;
register #(
.DATA_WIDTH(DATA_WIDTH),
.INIT_VAL(INIT_VAL),
.RESET_VAL(RESET_VAL)
) register_i (
.D(D),
.C(C),
.R(R),
.Q(Q)
);
always
#5 C = !C;
always @(posedge C)
D <= D + 1;
initial begin
D = INIT_VAL;
C = 0;
R = ~RESET_VAL;
#2 R = RESET_VAL;
#2 R = ~RESET_VAL;
#40 R = RESET_VAL;
#2 R = ~RESET_VAL;
end
endmodule | module register_testbench ( ); |
parameter DATA_WIDTH = 4;
parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL = 0;
parameter RESET_VAL = 1;
reg [DATA_WIDTH - 1 : 0] D;
reg C, R;
wire [DATA_WIDTH - 1 : 0] Q;
register #(
.DATA_WIDTH(DATA_WIDTH),
.INIT_VAL(INIT_VAL),
.RESET_VAL(RESET_VAL)
) register_i (
.D(D),
.C(C),
.R(R),
.Q(Q)
);
always
#5 C = !C;
always @(posedge C)
D <= D + 1;
initial begin
D = INIT_VAL;
C = 0;
R = ~RESET_VAL;
#2 R = RESET_VAL;
#2 R = ~RESET_VAL;
#40 R = RESET_VAL;
#2 R = ~RESET_VAL;
end
endmodule | 0 |
4,482 | data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v | 110,151,336 | testbench.v | v | 65 | 36 | [] | [] | [] | null | line:42: before: "(" | null | 1: b'%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:1: Cannot find include file: config.vh\n`include "config.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh\n data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh.v\n data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh.sv\n config.vh\n config.vh.v\n config.vh.sv\n obj_dir/config.vh\n obj_dir/config.vh.v\n obj_dir/config.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n # 10 clk = ! clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:40: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:42: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:49: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n #0\n ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:51: syntax error, unexpected \'@\'\n @ (posedge rst_n);\n ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:55: syntax error, unexpected \'@\'\n @ (posedge clk);\n ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n' | 2,752 | module | module testbench;
reg clk;
reg [ 3:0] key;
reg [ 7:0] sw;
wire [11:0] led;
wire [ 7:0] abcdefgh;
wire [ 7:0] digit;
wire buzzer;
top i_top
(
.clk ( clk ),
.key ( key ),
.sw ( sw ),
.led ( led ),
.abcdefgh ( abcdefgh ),
.digit ( digit ),
.buzzer ( buzzer )
);
initial
begin
clk = 0;
forever
# 10 clk = ! clk;
end
reg rst_n;
always @*
key [3] = rst_n;
initial
begin
repeat (2) @ (posedge clk);
rst_n <= 0;
repeat (2) @ (posedge clk);
rst_n <= 1;
end
initial
begin
#0
$dumpvars;
@ (posedge rst_n);
repeat (10000)
begin
@ (posedge clk);
key <= $random;
sw <= $random;
end
$stop;
end
endmodule | module testbench; |
reg clk;
reg [ 3:0] key;
reg [ 7:0] sw;
wire [11:0] led;
wire [ 7:0] abcdefgh;
wire [ 7:0] digit;
wire buzzer;
top i_top
(
.clk ( clk ),
.key ( key ),
.sw ( sw ),
.led ( led ),
.abcdefgh ( abcdefgh ),
.digit ( digit ),
.buzzer ( buzzer )
);
initial
begin
clk = 0;
forever
# 10 clk = ! clk;
end
reg rst_n;
always @*
key [3] = rst_n;
initial
begin
repeat (2) @ (posedge clk);
rst_n <= 0;
repeat (2) @ (posedge clk);
rst_n <= 1;
end
initial
begin
#0
$dumpvars;
@ (posedge rst_n);
repeat (10000)
begin
@ (posedge clk);
key <= $random;
sw <= $random;
end
$stop;
end
endmodule | 16 |
4,485 | data/full_repos/permissive/110151336/lab_02/src/00_sr_latch_theory/sr_latch.v | 110,151,336 | sr_latch.v | v | 12 | 32 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/2f21a069-d277-4886-9894-85b854751c76.xml | null | 2,758 | module | module sr_latch
(
input s,
input r,
output q,
output q_n
);
assign q = ~ ( r | q_n );
assign q_n = ~ ( s | q );
endmodule | module sr_latch
(
input s,
input r,
output q,
output q_n
); |
assign q = ~ ( r | q_n );
assign q_n = ~ ( s | q );
endmodule | 16 |
4,488 | data/full_repos/permissive/110151336/lab_02/src/01_d_latch_theory/d_latch.v | 110,151,336 | d_latch.v | v | 15 | 38 | [] | [] | [] | [(2, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_02/src/01_d_latch_theory/d_latch.v:12: Cannot find file containing module: 'sr_latch'\n sr_latch sr_latch (s, r, q, q_n);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_02/src/01_d_latch_theory,data/full_repos/permissive/110151336/sr_latch\n data/full_repos/permissive/110151336/lab_02/src/01_d_latch_theory,data/full_repos/permissive/110151336/sr_latch.v\n data/full_repos/permissive/110151336/lab_02/src/01_d_latch_theory,data/full_repos/permissive/110151336/sr_latch.sv\n sr_latch\n sr_latch.v\n sr_latch.sv\n obj_dir/sr_latch\n obj_dir/sr_latch.v\n obj_dir/sr_latch.sv\n%Error: Exiting due to 1 error(s)\n" | 2,761 | module | module d_latch
(
input clk,
input d,
output q,
output q_n
);
wire r = ~d & clk;
wire s = d & clk;
sr_latch sr_latch (s, r, q, q_n);
endmodule | module d_latch
(
input clk,
input d,
output q,
output q_n
); |
wire r = ~d & clk;
wire s = d & clk;
sr_latch sr_latch (s, r, q, q_n);
endmodule | 16 |
4,489 | data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory/d_flip_flop.v | 110,151,336 | d_flip_flop.v | v | 27 | 23 | [] | [] | [] | [(2, 26)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory/d_flip_flop.v:11: Cannot find file containing module: 'd_latch'\n d_latch master\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory,data/full_repos/permissive/110151336/d_latch\n data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory,data/full_repos/permissive/110151336/d_latch.v\n data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory,data/full_repos/permissive/110151336/d_latch.sv\n d_latch\n d_latch.v\n d_latch.sv\n obj_dir/d_latch\n obj_dir/d_latch.v\n obj_dir/d_latch.sv\n%Error: data/full_repos/permissive/110151336/lab_02/src/02_d_flip_flop_theory/d_flip_flop.v:18: Cannot find file containing module: 'd_latch'\n d_latch slave\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,765 | module | module d_flip_flop
(
input clk,
input d,
output q,
output q_n
);
wire n1;
d_latch master
(
.clk ( ~clk ),
.d ( d ),
.q ( n1 )
);
d_latch slave
(
.clk ( clk ),
.d ( n1 ),
.q ( q ),
.q_n ( q_n )
);
endmodule | module d_flip_flop
(
input clk,
input d,
output q,
output q_n
); |
wire n1;
d_latch master
(
.clk ( ~clk ),
.d ( d ),
.q ( n1 )
);
d_latch slave
(
.clk ( clk ),
.d ( n1 ),
.q ( q ),
.q_n ( q_n )
);
endmodule | 16 |
4,490 | data/full_repos/permissive/110151336/lab_02/src/03_d_latch/d_latch.v | 110,151,336 | d_latch.v | v | 13 | 24 | [] | [] | [] | [(1, 12)] | null | data/verilator_xmls/f155006d-12ca-43ff-af31-5a95192f3c89.xml | null | 2,770 | module | module d_latch
(
input clk,
input d,
output reg q
);
always @ (clk or d)
if(clk)
q <= d;
endmodule | module d_latch
(
input clk,
input d,
output reg q
); |
always @ (clk or d)
if(clk)
q <= d;
endmodule | 16 |
4,492 | data/full_repos/permissive/110151336/lab_02/src/04_d_flip_flop/d_flip_flop.v | 110,151,336 | d_flip_flop.v | v | 12 | 27 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/d4daeb67-097c-4ad0-b56a-1ef403c24212.xml | null | 2,773 | module | module d_flip_flop
(
input clk,
input d,
output reg q
);
always @ (posedge clk)
q <= d;
endmodule | module d_flip_flop
(
input clk,
input d,
output reg q
); |
always @ (posedge clk)
q <= d;
endmodule | 16 |
4,493 | data/full_repos/permissive/110151336/lab_02/src/05_dff_with_sync_rst_n/dff_sync_rst_n.v | 110,151,336 | dff_sync_rst_n.v | v | 16 | 27 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/ce3c23f9-109a-47cc-8487-6b7a546b8f08.xml | null | 2,776 | module | module dff_sync_rst_n
(
input clk,
input rst_n,
input d,
output reg q
);
always @ (posedge clk)
if (!rst_n)
q <= 0;
else
q <= d;
endmodule | module dff_sync_rst_n
(
input clk,
input rst_n,
input d,
output reg q
); |
always @ (posedge clk)
if (!rst_n)
q <= 0;
else
q <= d;
endmodule | 16 |
4,494 | data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v | 110,151,336 | testbench.v | v | 42 | 61 | [] | [] | [] | [(3, 41)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:10: Unsupported or unknown PLI call: $dumpvars\n initial $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:17: Unsupported or unknown PLI call: $monitor\n $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 0; rst_n = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 1; rst_n = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 1; rst_n = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/06_dff_with_async_rst_n/simulation/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n # 20;\n ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,780 | module | module testbench;
reg clk, rst_n, d;
wire q;
dff_async_rst_n dff_async_rst_n (clk, rst_n, d, q);
initial $dumpvars;
initial
begin
rst_n = 1;
clk = 1;
$monitor ("%0d clk %b d %b q %b", $time, clk, d, q);
# 20; clk = 0; d = 0; rst_n = 0;
# 20; clk = 1; d = 0;
# 20; clk = 0; d = 1;
# 20; clk = 1; d = 1;
# 20; clk = 0; d = 1; rst_n = 1;
# 20; clk = 1; d = 1;
# 20; clk = 0; d = 0;
# 20; clk = 1; d = 0;
# 10; clk = 1; d = 0;
# 10; clk = 0; d = 0;
# 10; clk = 0; d = 1;
# 10; clk = 1; d = 1;
# 10; clk = 1; d = 1; rst_n = 0;
# 10; clk = 0; d = 1;
# 10; clk = 0; d = 1;
# 10; clk = 1; d = 1;
# 10; clk = 1; d = 0;
# 20;
$finish;
end
endmodule | module testbench; |
reg clk, rst_n, d;
wire q;
dff_async_rst_n dff_async_rst_n (clk, rst_n, d, q);
initial $dumpvars;
initial
begin
rst_n = 1;
clk = 1;
$monitor ("%0d clk %b d %b q %b", $time, clk, d, q);
# 20; clk = 0; d = 0; rst_n = 0;
# 20; clk = 1; d = 0;
# 20; clk = 0; d = 1;
# 20; clk = 1; d = 1;
# 20; clk = 0; d = 1; rst_n = 1;
# 20; clk = 1; d = 1;
# 20; clk = 0; d = 0;
# 20; clk = 1; d = 0;
# 10; clk = 1; d = 0;
# 10; clk = 0; d = 0;
# 10; clk = 0; d = 1;
# 10; clk = 1; d = 1;
# 10; clk = 1; d = 1; rst_n = 0;
# 10; clk = 0; d = 1;
# 10; clk = 0; d = 1;
# 10; clk = 1; d = 1;
# 10; clk = 1; d = 0;
# 20;
$finish;
end
endmodule | 16 |
4,497 | data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/dff_async_rst_n_param.v | 110,151,336 | dff_async_rst_n_param.v | v | 19 | 44 | [] | [] | [] | [(1, 19)] | null | data/verilator_xmls/f9c32ef3-fdb3-487e-a5e0-354a4c2b83b7.xml | null | 2,785 | module | module dff_async_rst_n_param
#(
parameter WIDTH = 8,
RESET = 8'b0
)
(
input clk,
input rst_n,
input [WIDTH - 1 : 0] d,
output reg [WIDTH - 1 : 0] q
);
always @ (posedge clk or negedge rst_n)
if (!rst_n)
q <= RESET;
else
q <= d;
endmodule | module dff_async_rst_n_param
#(
parameter WIDTH = 8,
RESET = 8'b0
)
(
input clk,
input rst_n,
input [WIDTH - 1 : 0] d,
output reg [WIDTH - 1 : 0] q
); |
always @ (posedge clk or negedge rst_n)
if (!rst_n)
q <= RESET;
else
q <= d;
endmodule | 16 |
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