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4,064 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module IFStage(PCAddFour, Instruction, PCWrite, Jump, JumpAddress, Branch, BranchAddress, clock, reset);
input PCWrite, Jump, Branch, clock, reset;
input [31:0] JumpAddress, BranchAddress;
output [31:0] PCAddFour, Instruction;
wire [31:0] PCAddFour, Instruction, PCIn, BranchOut;
reg [31:0] PCOut=0;
always @(posedge clock, posedge reset) begin
if(reset==1) PCOut<=0;
else if(PCWrite==0) PCOut<=PCOut;
else PCOut<=PCIn;
end
InstructionMemory M_Imemory(Instruction, PCOut);
AddFour M_AddFour(PCAddFour, PCOut);
Mux_32bit_2to1 M_Mux_Branch(BranchOut, PCAddFour, BranchAddress, Branch);
Mux_32bit_2to1 M_Mux_Jump(PCIn, BranchOut, JumpAddress, Jump);
endmodule | module IFStage(PCAddFour, Instruction, PCWrite, Jump, JumpAddress, Branch, BranchAddress, clock, reset); |
input PCWrite, Jump, Branch, clock, reset;
input [31:0] JumpAddress, BranchAddress;
output [31:0] PCAddFour, Instruction;
wire [31:0] PCAddFour, Instruction, PCIn, BranchOut;
reg [31:0] PCOut=0;
always @(posedge clock, posedge reset) begin
if(reset==1) PCOut<=0;
else if(PCWrite==0) PCOut<=PCOut;
else PCOut<=PCIn;
end
InstructionMemory M_Imemory(Instruction, PCOut);
AddFour M_AddFour(PCAddFour, PCOut);
Mux_32bit_2to1 M_Mux_Branch(BranchOut, PCAddFour, BranchAddress, Branch);
Mux_32bit_2to1 M_Mux_Jump(PCIn, BranchOut, JumpAddress, Jump);
endmodule | 0 |
4,065 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module IDStage(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFID_Write, IDEX_Flush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction, WriteReg, WriteData, MEMWB_RegWrite, IDEX_Rt, IDEX_MemRead, clock, reset);
input MEMWB_RegWrite, IDEX_MemRead, clock, reset;
input [31:0] Instruction, WriteData;
input [4:0] IDEX_Rt, WriteReg;
output [27:0] JumpAddr_28;
output RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1;
output [1:0] ALUOp;
output [31:0] ReadData1, ReadData2, Immediate_32,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
wire [27:0] JumpAddr_28;
wire RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1, Andi;
wire [1:0] ALUOp;
wire [31:0] ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Immediate_Zero, Immediate_Sign;
RegisterFile M_RegFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,Instruction[25:21],Instruction[20:16],WriteReg,WriteData,MEMWB_RegWrite,clock, reset);
Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
ZeroExtend M_ZeroExtend(Immediate_Zero, Instruction[15:0]);
SignExtend M_SignExtend(Immediate_Sign, Instruction[15:0]);
Mux_32bit_2to1 M_Mux_Addi(Immediate_32, Immediate_Sign, Immediate_Zero, Andi);
ShiftLeftTwo_26to28 M_Shift_Jump(JumpAddr_28, Instruction[25:0]);
LoadUseHazardDetectionUnit M_LoadUse(PCWrite, IFID_Write, IDEX_Flush1, Instruction[31:26], Instruction[25:21], Instruction[20:16], IDEX_MemRead, IDEX_Rt);
endmodule | module IDStage(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFID_Write, IDEX_Flush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction, WriteReg, WriteData, MEMWB_RegWrite, IDEX_Rt, IDEX_MemRead, clock, reset); |
input MEMWB_RegWrite, IDEX_MemRead, clock, reset;
input [31:0] Instruction, WriteData;
input [4:0] IDEX_Rt, WriteReg;
output [27:0] JumpAddr_28;
output RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1;
output [1:0] ALUOp;
output [31:0] ReadData1, ReadData2, Immediate_32,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
wire [27:0] JumpAddr_28;
wire RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1, Andi;
wire [1:0] ALUOp;
wire [31:0] ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Immediate_Zero, Immediate_Sign;
RegisterFile M_RegFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,Instruction[25:21],Instruction[20:16],WriteReg,WriteData,MEMWB_RegWrite,clock, reset);
Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
ZeroExtend M_ZeroExtend(Immediate_Zero, Instruction[15:0]);
SignExtend M_SignExtend(Immediate_Sign, Instruction[15:0]);
Mux_32bit_2to1 M_Mux_Addi(Immediate_32, Immediate_Sign, Immediate_Zero, Andi);
ShiftLeftTwo_26to28 M_Shift_Jump(JumpAddr_28, Instruction[25:0]);
LoadUseHazardDetectionUnit M_LoadUse(PCWrite, IFID_Write, IDEX_Flush1, Instruction[31:26], Instruction[25:21], Instruction[20:16], IDEX_MemRead, IDEX_Rt);
endmodule | 0 |
4,066 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module EXStage(BranchAddr, Zero, ALUResult, ReadData2, RegDst, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite, IDEX_EX);
input [31:0] IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, WriteData, EXMEM_ALUResult;
input [4:0] IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_RegDst, MEMWB_RegDst;
input [3:0] IDEX_EX;
input EXMEM_RegWrite, MEMWB_RegWrite;
output [31:0] BranchAddr, ALUResult, ReadData2;
output Zero;
output [4:0] RegDst;
wire [31:0] BranchAddr, ALUResult, ReadData2, BranchOffset, ALUInput1, ALUInput2;
wire Zero;
wire [4:0] RegDst;
wire [1:0] ForwardA, ForwardB;
wire [3:0] ALUControlSignal;
Mux_5bit_2to1 M_Mux_RegDst(RegDst, IDEX_Rt, IDEX_Rd, IDEX_EX[3]);
ForwardingUnit M_Forward(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite);
Alucontrol M_Alucontrol(ALUControlSignal,IDEX_EX[1:0],IDEX_Immediate_32[5:0]);
ShiftLeftTwo_32to32 M_Shift_Immediate(BranchOffset, IDEX_Immediate_32);
Adder_32bit M_Adder(BranchAddr, IDEX_PC, BranchOffset);
Mux_32bit_3to1 M_Mux_ForwardA(ALUInput1, IDEX_ReadData1, WriteData, EXMEM_ALUResult, ForwardA);
Mux_32bit_3to1 M_Mux_ForwardB(ReadData2, IDEX_ReadData2, WriteData, EXMEM_ALUResult, ForwardB);
Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, IDEX_Immediate_32, ReadData2, IDEX_EX[2]);
ALU M_ALU(ALUResult,Zero,ALUControlSignal,ALUInput1,ALUInput2);
endmodule | module EXStage(BranchAddr, Zero, ALUResult, ReadData2, RegDst, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite, IDEX_EX); |
input [31:0] IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, WriteData, EXMEM_ALUResult;
input [4:0] IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_RegDst, MEMWB_RegDst;
input [3:0] IDEX_EX;
input EXMEM_RegWrite, MEMWB_RegWrite;
output [31:0] BranchAddr, ALUResult, ReadData2;
output Zero;
output [4:0] RegDst;
wire [31:0] BranchAddr, ALUResult, ReadData2, BranchOffset, ALUInput1, ALUInput2;
wire Zero;
wire [4:0] RegDst;
wire [1:0] ForwardA, ForwardB;
wire [3:0] ALUControlSignal;
Mux_5bit_2to1 M_Mux_RegDst(RegDst, IDEX_Rt, IDEX_Rd, IDEX_EX[3]);
ForwardingUnit M_Forward(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite);
Alucontrol M_Alucontrol(ALUControlSignal,IDEX_EX[1:0],IDEX_Immediate_32[5:0]);
ShiftLeftTwo_32to32 M_Shift_Immediate(BranchOffset, IDEX_Immediate_32);
Adder_32bit M_Adder(BranchAddr, IDEX_PC, BranchOffset);
Mux_32bit_3to1 M_Mux_ForwardA(ALUInput1, IDEX_ReadData1, WriteData, EXMEM_ALUResult, ForwardA);
Mux_32bit_3to1 M_Mux_ForwardB(ReadData2, IDEX_ReadData2, WriteData, EXMEM_ALUResult, ForwardB);
Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, IDEX_Immediate_32, ReadData2, IDEX_EX[2]);
ALU M_ALU(ALUResult,Zero,ALUControlSignal,ALUInput1,ALUInput2);
endmodule | 0 |
4,067 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module MEMStage(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst, clock, reset);
input [4:0] EXMEM_MEM;
input EXMEM_Zero, MEMWB_MemtoReg, clock, reset;
input [31:0] EXMEM_ALUResult, EXMEM_ReadData2, WriteData;
input [4:0] EXMEM_RegDst, MEMWB_RegDst;
output IFIDFlush, IDEXFlush2, EXMEMFlush, BranchMuxSignal;
output [31:0] MemData;
wire IFIDFlush, IDEXFlush2, EXMEMFlush, ForwardC;
wire [31:0] MemData, MemWriteData;
BrenchDetection M_BranchDetection(BranchMuxSignal, EXMEM_MEM[4], EXMEM_MEM[3], EXMEM_Zero);
ControlHazardDetectionUnit M_ControlHazard(IFIDFlush, IDEXFlush2, EXMEMFlush, BranchMuxSignal, EXMEM_MEM[0]);
LoadStoreHazardDetectionUnit M_LoadStore(ForwardC, EXMEM_MEM[2], EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst);
Mux_32bit_2to1 M_Mux_WriteData(MemWriteData, EXMEM_ReadData2, WriteData, ForwardC);
DataMemory M_Dmemory(MemData, EXMEM_ALUResult, MemWriteData, EXMEM_MEM[2], EXMEM_MEM[1], clock, reset);
endmodule | module MEMStage(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst, clock, reset); |
input [4:0] EXMEM_MEM;
input EXMEM_Zero, MEMWB_MemtoReg, clock, reset;
input [31:0] EXMEM_ALUResult, EXMEM_ReadData2, WriteData;
input [4:0] EXMEM_RegDst, MEMWB_RegDst;
output IFIDFlush, IDEXFlush2, EXMEMFlush, BranchMuxSignal;
output [31:0] MemData;
wire IFIDFlush, IDEXFlush2, EXMEMFlush, ForwardC;
wire [31:0] MemData, MemWriteData;
BrenchDetection M_BranchDetection(BranchMuxSignal, EXMEM_MEM[4], EXMEM_MEM[3], EXMEM_Zero);
ControlHazardDetectionUnit M_ControlHazard(IFIDFlush, IDEXFlush2, EXMEMFlush, BranchMuxSignal, EXMEM_MEM[0]);
LoadStoreHazardDetectionUnit M_LoadStore(ForwardC, EXMEM_MEM[2], EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst);
Mux_32bit_2to1 M_Mux_WriteData(MemWriteData, EXMEM_ReadData2, WriteData, ForwardC);
DataMemory M_Dmemory(MemData, EXMEM_ALUResult, MemWriteData, EXMEM_MEM[2], EXMEM_MEM[1], clock, reset);
endmodule | 0 |
4,068 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module WBStage(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_MemtoReg);
input [31:0] MEMWB_MemData, MEMWB_ALUData;
input MEMWB_MemtoReg;
output [31:0] WriteData;
wire [31:0] WriteData;
Mux_32bit_2to1 M_Mux_WriteData(WriteData, MEMWB_ALUData, MEMWB_MemData, MEMWB_MemtoReg);
endmodule | module WBStage(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_MemtoReg); |
input [31:0] MEMWB_MemData, MEMWB_ALUData;
input MEMWB_MemtoReg;
output [31:0] WriteData;
wire [31:0] WriteData;
Mux_32bit_2to1 M_Mux_WriteData(WriteData, MEMWB_ALUData, MEMWB_MemData, MEMWB_MemtoReg);
endmodule | 0 |
4,069 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset);
input [4:0] rdreg1,rdreg2,wrtreg;
input [31:0] wrtdata;
input RegWrite, clock, reset;
output [31:0] rddata1,rddata2;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
reg [31:0] rddata1,rddata2;
reg [31:0] RegFile [31:0];
reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
integer i;
always @(negedge clock, posedge reset) begin
if (reset==1) begin
for(i=0; i<32; i=i+1)
RegFile[i]=0;
end
else if (RegWrite) RegFile[wrtreg] = wrtdata;
end
always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin
rddata1 = RegFile[rdreg1];
rddata2 = RegFile[rdreg2];
end
always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
s0=RegFile[16];
s1=RegFile[17];
s2=RegFile[18];
s3=RegFile[19];
s4=RegFile[20];
s5=RegFile[21];
s6=RegFile[22];
s7=RegFile[23];
t0=RegFile[8];
t1=RegFile[9];
t2=RegFile[10];
t3=RegFile[11];
t4=RegFile[12];
t5=RegFile[13];
t6=RegFile[14];
t7=RegFile[15];
t8=RegFile[24];
t9=RegFile[25];
end
endmodule | module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset); |
input [4:0] rdreg1,rdreg2,wrtreg;
input [31:0] wrtdata;
input RegWrite, clock, reset;
output [31:0] rddata1,rddata2;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
reg [31:0] rddata1,rddata2;
reg [31:0] RegFile [31:0];
reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
integer i;
always @(negedge clock, posedge reset) begin
if (reset==1) begin
for(i=0; i<32; i=i+1)
RegFile[i]=0;
end
else if (RegWrite) RegFile[wrtreg] = wrtdata;
end
always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin
rddata1 = RegFile[rdreg1];
rddata2 = RegFile[rdreg2];
end
always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
s0=RegFile[16];
s1=RegFile[17];
s2=RegFile[18];
s3=RegFile[19];
s4=RegFile[20];
s5=RegFile[21];
s6=RegFile[22];
s7=RegFile[23];
t0=RegFile[8];
t1=RegFile[9];
t2=RegFile[10];
t3=RegFile[11];
t4=RegFile[12];
t5=RegFile[13];
t6=RegFile[14];
t7=RegFile[15];
t8=RegFile[24];
t9=RegFile[25];
end
endmodule | 0 |
4,070 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ShiftLeftTwo_26to28(Q, I);
input [25:0] I;
output [27:0] Q;
reg [27:0] Q;
always @ (I)
begin
Q[27:2] = I[25:0];
Q[1:0] = 2'b00;
end
endmodule | module ShiftLeftTwo_26to28(Q, I); |
input [25:0] I;
output [27:0] Q;
reg [27:0] Q;
always @ (I)
begin
Q[27:2] = I[25:0];
Q[1:0] = 2'b00;
end
endmodule | 0 |
4,071 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ShiftLeftTwo_32to32(Q, I);
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[31:2] = I[29:0];
Q[1:0] = 'b0;
end
endmodule | module ShiftLeftTwo_32to32(Q, I); |
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[31:2] = I[29:0];
Q[1:0] = 'b0;
end
endmodule | 0 |
4,072 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ALU(Alurlt,zero,Aluctrl,I1,I2);
input [31:0] I1,I2;
input [3:0] Aluctrl;
output [31:0] Alurlt;
output zero;
reg [31:0] Alurlt;
reg zero;
always @ (I1 or I2 or Aluctrl)
begin
if(Aluctrl==4'b0010) Alurlt = I1 + I2;
else if(Aluctrl==4'b0110) Alurlt=I1-I2;
else if(Aluctrl==4'b0000) Alurlt = I1 & I2;
else if(Aluctrl==4'b0001) Alurlt = I1 | I2;
else begin
if(I1<I2) Alurlt=1;
else Alurlt=0;
end
if (I1==I2) zero=1;
else zero=0;
end
endmodule | module ALU(Alurlt,zero,Aluctrl,I1,I2); |
input [31:0] I1,I2;
input [3:0] Aluctrl;
output [31:0] Alurlt;
output zero;
reg [31:0] Alurlt;
reg zero;
always @ (I1 or I2 or Aluctrl)
begin
if(Aluctrl==4'b0010) Alurlt = I1 + I2;
else if(Aluctrl==4'b0110) Alurlt=I1-I2;
else if(Aluctrl==4'b0000) Alurlt = I1 & I2;
else if(Aluctrl==4'b0001) Alurlt = I1 | I2;
else begin
if(I1<I2) Alurlt=1;
else Alurlt=0;
end
if (I1==I2) zero=1;
else zero=0;
end
endmodule | 0 |
4,073 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Alucontrol(Aluctrl,Aluop,funct);
input [5:0] funct;
input [1:0] Aluop;
output [3:0] Aluctrl;
reg [3:0] Aluctrl;
always @ (Aluop or funct)
begin
if(Aluop==2'b00) Aluctrl=4'b0010;
else if(Aluop==2'b01) Aluctrl=4'b0110;
else if(Aluop==2'b11) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
end
endmodule | module Alucontrol(Aluctrl,Aluop,funct); |
input [5:0] funct;
input [1:0] Aluop;
output [3:0] Aluctrl;
reg [3:0] Aluctrl;
always @ (Aluop or funct)
begin
if(Aluop==2'b00) Aluctrl=4'b0010;
else if(Aluop==2'b01) Aluctrl=4'b0110;
else if(Aluop==2'b11) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
end
endmodule | 0 |
4,074 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ZeroExtend(Q, I);
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = 16'b0;
end
endmodule | module ZeroExtend(Q, I); |
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = 16'b0;
end
endmodule | 0 |
4,075 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module SignExtend(Q, I);
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = {16{I[15]}};
end
endmodule | module SignExtend(Q, I); |
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = {16{I[15]}};
end
endmodule | 0 |
4,076 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module AddFour(Q, I);
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I) begin
Q=I+4;
end
endmodule | module AddFour(Q, I); |
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I) begin
Q=I+4;
end
endmodule | 0 |
4,077 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Adder_32bit(Q, I1, I2);
input [31:0] I1;
input [31:0] I2;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2) begin
Q=I1+I2;
end
endmodule | module Adder_32bit(Q, I1, I2); |
input [31:0] I1;
input [31:0] I2;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2) begin
Q=I1+I2;
end
endmodule | 0 |
4,078 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Mux_32bit_2to1(Q, I1, I2, s);
input [31:0] I1;
input [31:0] I2;
input s;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | module Mux_32bit_2to1(Q, I1, I2, s); |
input [31:0] I1;
input [31:0] I2;
input s;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | 0 |
4,079 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Mux_32bit_3to1(Q, I0, I1, I2, s);
input [31:0] I0, I1, I2;
input [1:0] s;
output [31:0] Q;
reg [31:0] Q;
always @(I0, I1, I2, s) begin
if (s==0) Q=I0;
else if (s==1) Q=I1;
else Q=I2;
end
endmodule | module Mux_32bit_3to1(Q, I0, I1, I2, s); |
input [31:0] I0, I1, I2;
input [1:0] s;
output [31:0] Q;
reg [31:0] Q;
always @(I0, I1, I2, s) begin
if (s==0) Q=I0;
else if (s==1) Q=I1;
else Q=I2;
end
endmodule | 0 |
4,080 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Mux_5bit_2to1(Q, I1, I2, s);
input [4:0] I1;
input [4:0] I2;
input s;
output [4:0] Q;
reg [4:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | module Mux_5bit_2to1(Q, I1, I2, s); |
input [4:0] I1;
input [4:0] I2;
input s;
output [4:0] Q;
reg [4:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | 0 |
4,081 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, I);
input [5:0] I;
output RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
output [1:0] ALUOp;
reg RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
reg [1:0] ALUOp;
always @(I) begin
if (I==0) RegDst=1;
else RegDst=0;
if (I==2) Jump=1;
else Jump=0;
if (I==4) Branch=1;
else Branch=0;
if (I==5) BranchN=1;
else BranchN=0;
if (I==6'h23) MemRead=1;
else MemRead=0;
if (I==6'h23) MemtoReg=1;
else MemtoReg=0;
if (I==6'h23 || I==6'h2b || I==8) ALUOp=0;
else if (I==4 || I==5) ALUOp=1;
else if (I==6'h0c) ALUOp=3;
else ALUOp=2;
if (I==6'h2b) MemWrite=1;
else MemWrite=0;
if (I==0 || I==4 || I==5) ALUSrc=1;
else ALUSrc=0;
if (I==4 || I==5 || I==2 || I==6'h2b) RegWrite=0;
else RegWrite=1;
if (I==6'h0c) Andi=1;
else Andi=0;
end
endmodule | module Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, I); |
input [5:0] I;
output RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
output [1:0] ALUOp;
reg RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
reg [1:0] ALUOp;
always @(I) begin
if (I==0) RegDst=1;
else RegDst=0;
if (I==2) Jump=1;
else Jump=0;
if (I==4) Branch=1;
else Branch=0;
if (I==5) BranchN=1;
else BranchN=0;
if (I==6'h23) MemRead=1;
else MemRead=0;
if (I==6'h23) MemtoReg=1;
else MemtoReg=0;
if (I==6'h23 || I==6'h2b || I==8) ALUOp=0;
else if (I==4 || I==5) ALUOp=1;
else if (I==6'h0c) ALUOp=3;
else ALUOp=2;
if (I==6'h2b) MemWrite=1;
else MemWrite=0;
if (I==0 || I==4 || I==5) ALUSrc=1;
else ALUSrc=0;
if (I==4 || I==5 || I==2 || I==6'h2b) RegWrite=0;
else RegWrite=1;
if (I==6'h0c) Andi=1;
else Andi=0;
end
endmodule | 0 |
4,082 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module InstructionMemory(Instruction, ReadAddress);
input [31:0] ReadAddress;
output [31:0] Instruction;
reg [31:0] Instruction;
reg [31:0] Imemory [31:0];
initial begin
Imemory[0] = 32'b00100000000010000000000000100000;
Imemory[1] = 32'b00100000000010010000000000110111;
Imemory[2] = 32'b00000001000010011000000000100100;
Imemory[3] = 32'b00000001000010011000000000100101;
Imemory[4] = 32'b10101100000100000000000000000100;
Imemory[5] = 32'b10101100000010000000000000001000;
Imemory[6] = 32'b00000001000010011000100000100000;
Imemory[7] = 32'b00000001000010011001000000100010;
Imemory[8] = 32'b00010010001100100000000000001001;
Imemory[9] = 32'b10001100000100010000000000000100;
Imemory[10]= 32'b00110010001100100000000001001000;
Imemory[11] =32'b00010010001100100000000000001001;
Imemory[12] =32'b10001100000100110000000000001000;
Imemory[13] =32'b00010010000100110000000000001010;
Imemory[14] =32'b00000010010100011010000000101010;
Imemory[15] =32'b00010010100000000000000000001111;
Imemory[16] =32'b00000010001000001001000000100000;
Imemory[17] =32'b00001000000000000000000000001110;
Imemory[18] =32'b00100000000010000000000000000000;
Imemory[19] =32'b00100000000010010000000000000000;
Imemory[20] =32'b00001000000000000000000000011111;
Imemory[21] =32'b00100000000010000000000000000001;
Imemory[22] =32'b00100000000010010000000000000001;
Imemory[23] =32'b00001000000000000000000000011111;
Imemory[24] =32'b00100000000010000000000000000010;
Imemory[25] =32'b00100000000010010000000000000010;
Imemory[26] =32'b00001000000000000000000000011111;
Imemory[27] =32'b00100000000010000000000000000011;
Imemory[28] =32'b00100000000010010000000000000011;
Imemory[29] =32'b00001000000000000000000000011111;
Imemory[30] =32'b00000000000000000000000000000000;
Imemory[31] =32'b00000000000000000000000000000000;
end
always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];
endmodule | module InstructionMemory(Instruction, ReadAddress); |
input [31:0] ReadAddress;
output [31:0] Instruction;
reg [31:0] Instruction;
reg [31:0] Imemory [31:0];
initial begin
Imemory[0] = 32'b00100000000010000000000000100000;
Imemory[1] = 32'b00100000000010010000000000110111;
Imemory[2] = 32'b00000001000010011000000000100100;
Imemory[3] = 32'b00000001000010011000000000100101;
Imemory[4] = 32'b10101100000100000000000000000100;
Imemory[5] = 32'b10101100000010000000000000001000;
Imemory[6] = 32'b00000001000010011000100000100000;
Imemory[7] = 32'b00000001000010011001000000100010;
Imemory[8] = 32'b00010010001100100000000000001001;
Imemory[9] = 32'b10001100000100010000000000000100;
Imemory[10]= 32'b00110010001100100000000001001000;
Imemory[11] =32'b00010010001100100000000000001001;
Imemory[12] =32'b10001100000100110000000000001000;
Imemory[13] =32'b00010010000100110000000000001010;
Imemory[14] =32'b00000010010100011010000000101010;
Imemory[15] =32'b00010010100000000000000000001111;
Imemory[16] =32'b00000010001000001001000000100000;
Imemory[17] =32'b00001000000000000000000000001110;
Imemory[18] =32'b00100000000010000000000000000000;
Imemory[19] =32'b00100000000010010000000000000000;
Imemory[20] =32'b00001000000000000000000000011111;
Imemory[21] =32'b00100000000010000000000000000001;
Imemory[22] =32'b00100000000010010000000000000001;
Imemory[23] =32'b00001000000000000000000000011111;
Imemory[24] =32'b00100000000010000000000000000010;
Imemory[25] =32'b00100000000010010000000000000010;
Imemory[26] =32'b00001000000000000000000000011111;
Imemory[27] =32'b00100000000010000000000000000011;
Imemory[28] =32'b00100000000010010000000000000011;
Imemory[29] =32'b00001000000000000000000000011111;
Imemory[30] =32'b00000000000000000000000000000000;
Imemory[31] =32'b00000000000000000000000000000000;
end
always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];
endmodule | 0 |
4,083 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module DataMemory(ReadData, Address, WriteData, MemWrite, MemRead, clock, reset);
input [31:0] Address, WriteData;
input MemWrite, MemRead, clock, reset;
output [31:0] ReadData;
reg [31:0] ReadData;
reg [31:0] Dmemory [31:0];
integer i;
always @(Address[31:2], MemRead, Dmemory[Address[31:2]]) begin
if (MemRead) ReadData=Dmemory[Address[31:2]];
end
always @(negedge clock, posedge reset) begin
if (reset) begin
for(i=0; i<32; i=i+1)
Dmemory[i]=0;
end
else if (MemWrite) Dmemory[Address[31:2]]=WriteData;
end
endmodule | module DataMemory(ReadData, Address, WriteData, MemWrite, MemRead, clock, reset); |
input [31:0] Address, WriteData;
input MemWrite, MemRead, clock, reset;
output [31:0] ReadData;
reg [31:0] ReadData;
reg [31:0] Dmemory [31:0];
integer i;
always @(Address[31:2], MemRead, Dmemory[Address[31:2]]) begin
if (MemRead) ReadData=Dmemory[Address[31:2]];
end
always @(negedge clock, posedge reset) begin
if (reset) begin
for(i=0; i<32; i=i+1)
Dmemory[i]=0;
end
else if (MemWrite) Dmemory[Address[31:2]]=WriteData;
end
endmodule | 0 |
4,084 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module BrenchDetection(BranchMuxSignal, Branch, BranchN, Zero);
input Branch, BranchN, Zero;
output BranchMuxSignal;
reg BranchMuxSignal;
always @(Branch, BranchN, Zero) begin
if (Branch && Zero || BranchN && ~Zero) BranchMuxSignal=1;
else BranchMuxSignal=0;
end
endmodule | module BrenchDetection(BranchMuxSignal, Branch, BranchN, Zero); |
input Branch, BranchN, Zero;
output BranchMuxSignal;
reg BranchMuxSignal;
always @(Branch, BranchN, Zero) begin
if (Branch && Zero || BranchN && ~Zero) BranchMuxSignal=1;
else BranchMuxSignal=0;
end
endmodule | 0 |
4,085 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ForwardingUnit(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite);
input [4:0] IDEX_Rs, IDEX_Rt, EXMEM_RegDst, MEMWB_RegDst;
input EXMEM_RegWrite, MEMWB_RegWrite;
output [1:0] ForwardA, ForwardB;
reg [1:0] ForwardA, ForwardB;
always @(IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite) begin
if (EXMEM_RegWrite==1 && EXMEM_RegDst!=0 && (EXMEM_RegDst==IDEX_Rs)) ForwardA=2'b10;
else if (MEMWB_RegWrite==1 && MEMWB_RegDst!=0 && (MEMWB_RegDst==IDEX_Rs)) ForwardA=2'b01;
else ForwardA=2'b00;
if (EXMEM_RegWrite==1 && EXMEM_RegDst!=0 && (EXMEM_RegDst==IDEX_Rt)) ForwardB=2'b10;
else if (MEMWB_RegWrite==1 && MEMWB_RegDst!=0 && (MEMWB_RegDst==IDEX_Rt)) ForwardB=2'b01;
else ForwardB=2'b00;
end
endmodule | module ForwardingUnit(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite); |
input [4:0] IDEX_Rs, IDEX_Rt, EXMEM_RegDst, MEMWB_RegDst;
input EXMEM_RegWrite, MEMWB_RegWrite;
output [1:0] ForwardA, ForwardB;
reg [1:0] ForwardA, ForwardB;
always @(IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite) begin
if (EXMEM_RegWrite==1 && EXMEM_RegDst!=0 && (EXMEM_RegDst==IDEX_Rs)) ForwardA=2'b10;
else if (MEMWB_RegWrite==1 && MEMWB_RegDst!=0 && (MEMWB_RegDst==IDEX_Rs)) ForwardA=2'b01;
else ForwardA=2'b00;
if (EXMEM_RegWrite==1 && EXMEM_RegDst!=0 && (EXMEM_RegDst==IDEX_Rt)) ForwardB=2'b10;
else if (MEMWB_RegWrite==1 && MEMWB_RegDst!=0 && (MEMWB_RegDst==IDEX_Rt)) ForwardB=2'b01;
else ForwardB=2'b00;
end
endmodule | 0 |
4,086 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);
input [31:0] PCOut, ShowRegOut;
input ShowPC;
output [31:0] ShowNum;
reg [31:0] ShowNum;
always @(PCOut, ShowRegOut, ShowPC) begin
if (ShowPC) ShowNum=PCOut;
else ShowNum=ShowRegOut;
end
endmodule | module ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC); |
input [31:0] PCOut, ShowRegOut;
input ShowPC;
output [31:0] ShowNum;
reg [31:0] ShowNum;
always @(PCOut, ShowRegOut, ShowPC) begin
if (ShowPC) ShowNum=PCOut;
else ShowNum=ShowRegOut;
end
endmodule | 0 |
4,087 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module LoadUseHazardDetectionUnit(PCWrite, IFID_Write, IDEX_Flush1, IFID_Opcode, IFID_Rs, IFID_Rt, IDEX_MemRead, IDEX_Rt);
input [5:0] IFID_Opcode;
input [4:0] IFID_Rs, IFID_Rt, IDEX_Rt;
input IDEX_MemRead;
output PCWrite, IFID_Write, IDEX_Flush1;
reg PCWrite, IFID_Write, IDEX_Flush1;
always @(IFID_Opcode, IFID_Rs, IFID_Rt, IDEX_MemRead, IDEX_Rt) begin
if ((IFID_Opcode!=2 && IDEX_MemRead==1 && IFID_Rs==IDEX_Rt) || ((IFID_Opcode==0 || IFID_Opcode==4 || IFID_Opcode==5) && IDEX_MemRead==1 && IFID_Rt==IDEX_Rt)) begin
PCWrite=0; IFID_Write=0; IDEX_Flush1=1;
end
else begin
PCWrite=1; IFID_Write=1; IDEX_Flush1=0;
end
end
endmodule | module LoadUseHazardDetectionUnit(PCWrite, IFID_Write, IDEX_Flush1, IFID_Opcode, IFID_Rs, IFID_Rt, IDEX_MemRead, IDEX_Rt); |
input [5:0] IFID_Opcode;
input [4:0] IFID_Rs, IFID_Rt, IDEX_Rt;
input IDEX_MemRead;
output PCWrite, IFID_Write, IDEX_Flush1;
reg PCWrite, IFID_Write, IDEX_Flush1;
always @(IFID_Opcode, IFID_Rs, IFID_Rt, IDEX_MemRead, IDEX_Rt) begin
if ((IFID_Opcode!=2 && IDEX_MemRead==1 && IFID_Rs==IDEX_Rt) || ((IFID_Opcode==0 || IFID_Opcode==4 || IFID_Opcode==5) && IDEX_MemRead==1 && IFID_Rt==IDEX_Rt)) begin
PCWrite=0; IFID_Write=0; IDEX_Flush1=1;
end
else begin
PCWrite=1; IFID_Write=1; IDEX_Flush1=0;
end
end
endmodule | 0 |
4,088 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module ControlHazardDetectionUnit(IFIDFlush, IDEXFlush2, EXMEMFlush, Branch, Jump);
input Branch, Jump;
output IFIDFlush, IDEXFlush2, EXMEMFlush;
reg IFIDFlush, IDEXFlush2, EXMEMFlush;
always @(Branch, Jump) begin
if (Branch==1 || Jump==1) begin
IFIDFlush=1;
IDEXFlush2=1;
EXMEMFlush=1;
end
else begin
IFIDFlush=0;
IDEXFlush2=0;
EXMEMFlush=0;
end
end
endmodule | module ControlHazardDetectionUnit(IFIDFlush, IDEXFlush2, EXMEMFlush, Branch, Jump); |
input Branch, Jump;
output IFIDFlush, IDEXFlush2, EXMEMFlush;
reg IFIDFlush, IDEXFlush2, EXMEMFlush;
always @(Branch, Jump) begin
if (Branch==1 || Jump==1) begin
IFIDFlush=1;
IDEXFlush2=1;
EXMEMFlush=1;
end
else begin
IFIDFlush=0;
IDEXFlush2=0;
EXMEMFlush=0;
end
end
endmodule | 0 |
4,089 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module LoadStoreHazardDetectionUnit(ForwardC, EXMEM_MemWrite, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst);
input EXMEM_MemWrite, MEMWB_MemtoReg;
input [4:0] EXMEM_RegDst, MEMWB_RegDst;
output ForwardC;
reg ForwardC;
always @(EXMEM_MemWrite, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst) begin
if(EXMEM_MemWrite==1 && MEMWB_MemtoReg==1 && EXMEM_RegDst==MEMWB_RegDst) ForwardC=1;
else ForwardC=0;
end
endmodule | module LoadStoreHazardDetectionUnit(ForwardC, EXMEM_MemWrite, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst); |
input EXMEM_MemWrite, MEMWB_MemtoReg;
input [4:0] EXMEM_RegDst, MEMWB_RegDst;
output ForwardC;
reg ForwardC;
always @(EXMEM_MemWrite, EXMEM_RegDst, MEMWB_MemtoReg, MEMWB_RegDst) begin
if(EXMEM_MemWrite==1 && MEMWB_MemtoReg==1 && EXMEM_RegDst==MEMWB_RegDst) ForwardC=1;
else ForwardC=0;
end
endmodule | 0 |
4,090 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);
input [3:0] Num_0, Num_1, Num_2, Num_3;
input clk_500;
output [6:0] Cathod;
output [3:0] Anode;
reg [6:0] Cathod;
reg [3:0] Anode;
reg [1:0] digit=0;
always @ (posedge clk_500)
begin
case(digit)
2'b00: digit<=2'b01;
2'b01: digit<=2'b10;
2'b10: digit<=2'b11;
2'b11: digit<=2'b00;
endcase
end
always @(digit, Num_0, Num_1, Num_2, Num_3)
begin
case (digit)
2'b00: begin
Anode <= 4'b1110;
case (Num_0)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b01: begin
Anode <= 4'b1101;
case (Num_1)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b10: begin
Anode <= 4'b1011;
case (Num_2)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b11: begin
Anode <= 4'b0111;
case (Num_3)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
endcase
end
endmodule | module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500); |
input [3:0] Num_0, Num_1, Num_2, Num_3;
input clk_500;
output [6:0] Cathod;
output [3:0] Anode;
reg [6:0] Cathod;
reg [3:0] Anode;
reg [1:0] digit=0;
always @ (posedge clk_500)
begin
case(digit)
2'b00: digit<=2'b01;
2'b01: digit<=2'b10;
2'b10: digit<=2'b11;
2'b11: digit<=2'b00;
endcase
end
always @(digit, Num_0, Num_1, Num_2, Num_3)
begin
case (digit)
2'b00: begin
Anode <= 4'b1110;
case (Num_0)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b01: begin
Anode <= 4'b1101;
case (Num_1)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b10: begin
Anode <= 4'b1011;
case (Num_2)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b11: begin
Anode <= 4'b0111;
case (Num_3)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
endcase
end
endmodule | 0 |
4,091 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module clk_500_Hz(clk_50M, clk_500);
input clk_50M;
output clk_500;
reg clk_500;
reg[16:0] counter=0;
always @ (posedge clk_50M)
begin
if (counter < 100000-1) begin
counter<=counter+1;
clk_500<=0;
end else
begin
counter<=0;
clk_500<=1;
end
end
endmodule | module clk_500_Hz(clk_50M, clk_500); |
input clk_50M;
output clk_500;
reg clk_500;
reg[16:0] counter=0;
always @ (posedge clk_50M)
begin
if (counter < 100000-1) begin
counter<=counter+1;
clk_500<=0;
end else
begin
counter<=0;
clk_500<=1;
end
end
endmodule | 0 |
4,092 | data/full_repos/permissive/108382235/Pipelined.v | 108,382,235 | Pipelined.v | v | 912 | 351 | [] | [] | [] | [(21, 174), (180, 198), (202, 223), (227, 251), (255, 271), (275, 283), (289, 338), (342, 353), (357, 368), (373, 395), (399, 417), (421, 432), (436, 447), (451, 460), (464, 474), (478, 491), (495, 507), (511, 524), (528, 562), (566, 627), (631, 651), (655, 665), (669, 684), (688, 699), (703, 719), (723, 741), (745, 756), (760, 867), (871, 887), (891, 911)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC, SwitchClk_10, reset);\n ^~~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_MEM.M_Dmemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n : ... In instance Pipelined\n IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n ^~\n%Error: Exiting due to 5 warning(s)\n' | 2,317 | module | module clk_10_Hz(clk_50M, clk_10, reset);
input clk_50M, reset;
output clk_10;
reg clk_10;
reg[22:0] counter=0;
always @ (posedge clk_50M)
begin
if (reset==1) begin
counter<=0;
clk_10<=0;
end else
if (counter < 5000000-1) begin
counter<=counter+1;
clk_10<=0;
end else
begin
counter<=0;
clk_10<=1;
end
end
endmodule | module clk_10_Hz(clk_50M, clk_10, reset); |
input clk_50M, reset;
output clk_10;
reg clk_10;
reg[22:0] counter=0;
always @ (posedge clk_50M)
begin
if (reset==1) begin
counter<=0;
clk_10<=0;
end else
if (counter < 5000000-1) begin
counter<=counter+1;
clk_10<=0;
end else
begin
counter<=0;
clk_10<=1;
end
end
endmodule | 0 |
4,093 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);
input SwitchClk_10, reset;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
output [31:0] PCOut;
reg [31:0] PCOut=0;
wire [31:0] PCIn, Instruction, ReadData1, ReadData2, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData_RegFile, Immediate_Sign_32, Immediate_Zero_32, Immediate_32;
wire [31:0] ALUInput2, ALUResult, ReadData, PCAddFour, BranchOffset, BranchAddress, PCNoJump, ShowNum;
wire RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi, Zero, BranchMuxSignal;
wire [1:0] ALUOp;
wire [4:0] WriteRegister;
wire [3:0] ALUControlSignal;
wire [27:0] JumpImmediate;
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) PCOut=0;
else PCOut=PCIn;
end
InstructionMemory M_InstructionMemory(Instruction, PCOut);
Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
Mux_5bit_2to1 M_Mux_WriteReg(WriteRegister, Instruction[20:16], Instruction[15:11], RegDst);
RegisterFile M_RegisterFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction[25:21], Instruction[20:16],WriteRegister,WriteData_RegFile,RegWrite,SwitchClk_10, reset);
SignExtend M_SignExtend(Immediate_Sign_32, Instruction[15:0]);
ZeroExtend M_ZeroExtend(Immediate_Zero_32, Instruction[15:0]);
Mux_32bit_2to1 M_Mux_Immediate(Immediate_32, Immediate_Sign_32, Immediate_Zero_32, Andi);
Alucontrol M_Alucontrol(ALUControlSignal,ALUOp,Instruction[5:0]);
Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, Immediate_32, ReadData2, ALUSrc);
ALU M_ALU(ALUResult,Zero,ALUControlSignal,ReadData1,ALUInput2);
DataMemory M_DataMemory(ReadData, ALUResult, ReadData2, MemWrite, MemRead, SwitchClk_10, reset);
Mux_32bit_2to1 M_Mux_MemtoReg(WriteData_RegFile, ALUResult, ReadData, MemtoReg);
AddFour M_AddFour(PCAddFour, PCOut);
ShiftLeftTwo_26to28 M_Shifter_Jump(JumpImmediate, Instruction[25:0]);
ShiftLeftTwo_32to32 M_Shifter_Branch(BranchOffset, Immediate_32);
Adder_32bit M_AdderBranch(BranchAddress, PCAddFour, BranchOffset);
BrenchDetection M_BranchDetection(BranchMuxSignal, Branch, BranchN, Zero);
Mux_32bit_2to1 M_Mux_Branch(PCNoJump, PCAddFour, BranchAddress, BranchMuxSignal);
Mux_32bit_2to1 M_Mux_Jump(PCIn, PCNoJump, {PCAddFour[31:28],JumpImmediate}, Jump);
endmodule | module SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset); |
input SwitchClk_10, reset;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
output [31:0] PCOut;
reg [31:0] PCOut=0;
wire [31:0] PCIn, Instruction, ReadData1, ReadData2, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData_RegFile, Immediate_Sign_32, Immediate_Zero_32, Immediate_32;
wire [31:0] ALUInput2, ALUResult, ReadData, PCAddFour, BranchOffset, BranchAddress, PCNoJump, ShowNum;
wire RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi, Zero, BranchMuxSignal;
wire [1:0] ALUOp;
wire [4:0] WriteRegister;
wire [3:0] ALUControlSignal;
wire [27:0] JumpImmediate;
always @(posedge SwitchClk_10, posedge reset) begin
if (reset==1) PCOut=0;
else PCOut=PCIn;
end
InstructionMemory M_InstructionMemory(Instruction, PCOut);
Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
Mux_5bit_2to1 M_Mux_WriteReg(WriteRegister, Instruction[20:16], Instruction[15:11], RegDst);
RegisterFile M_RegisterFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction[25:21], Instruction[20:16],WriteRegister,WriteData_RegFile,RegWrite,SwitchClk_10, reset);
SignExtend M_SignExtend(Immediate_Sign_32, Instruction[15:0]);
ZeroExtend M_ZeroExtend(Immediate_Zero_32, Instruction[15:0]);
Mux_32bit_2to1 M_Mux_Immediate(Immediate_32, Immediate_Sign_32, Immediate_Zero_32, Andi);
Alucontrol M_Alucontrol(ALUControlSignal,ALUOp,Instruction[5:0]);
Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, Immediate_32, ReadData2, ALUSrc);
ALU M_ALU(ALUResult,Zero,ALUControlSignal,ReadData1,ALUInput2);
DataMemory M_DataMemory(ReadData, ALUResult, ReadData2, MemWrite, MemRead, SwitchClk_10, reset);
Mux_32bit_2to1 M_Mux_MemtoReg(WriteData_RegFile, ALUResult, ReadData, MemtoReg);
AddFour M_AddFour(PCAddFour, PCOut);
ShiftLeftTwo_26to28 M_Shifter_Jump(JumpImmediate, Instruction[25:0]);
ShiftLeftTwo_32to32 M_Shifter_Branch(BranchOffset, Immediate_32);
Adder_32bit M_AdderBranch(BranchAddress, PCAddFour, BranchOffset);
BrenchDetection M_BranchDetection(BranchMuxSignal, Branch, BranchN, Zero);
Mux_32bit_2to1 M_Mux_Branch(PCNoJump, PCAddFour, BranchAddress, BranchMuxSignal);
Mux_32bit_2to1 M_Mux_Jump(PCIn, PCNoJump, {PCAddFour[31:28],JumpImmediate}, Jump);
endmodule | 0 |
4,094 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset);
input [4:0] rdreg1,rdreg2,wrtreg;
input [31:0] wrtdata;
input RegWrite, clock, reset;
output [31:0] rddata1,rddata2;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
reg [31:0] rddata1,rddata2;
reg [31:0] RegFile [31:0];
reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
integer i;
always @(negedge clock, posedge reset) begin
if (reset==1) begin
for(i=0; i<32; i=i+1)
RegFile[i]=0;
end
else if (RegWrite) RegFile[wrtreg] = wrtdata;
end
always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin
rddata1 = RegFile[rdreg1];
rddata2 = RegFile[rdreg2];
end
always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
s0=RegFile[16];
s1=RegFile[17];
s2=RegFile[18];
s3=RegFile[19];
s4=RegFile[20];
s5=RegFile[21];
s6=RegFile[22];
s7=RegFile[23];
t0=RegFile[8];
t1=RegFile[9];
t2=RegFile[10];
t3=RegFile[11];
t4=RegFile[12];
t5=RegFile[13];
t6=RegFile[14];
t7=RegFile[15];
t8=RegFile[24];
t9=RegFile[25];
end
endmodule | module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset); |
input [4:0] rdreg1,rdreg2,wrtreg;
input [31:0] wrtdata;
input RegWrite, clock, reset;
output [31:0] rddata1,rddata2;
output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
reg [31:0] rddata1,rddata2;
reg [31:0] RegFile [31:0];
reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
integer i;
always @(negedge clock, posedge reset) begin
if (reset==1) begin
for(i=0; i<32; i=i+1)
RegFile[i]=0;
end
else if (RegWrite) RegFile[wrtreg] = wrtdata;
end
always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin
rddata1 = RegFile[rdreg1];
rddata2 = RegFile[rdreg2];
end
always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
s0=RegFile[16];
s1=RegFile[17];
s2=RegFile[18];
s3=RegFile[19];
s4=RegFile[20];
s5=RegFile[21];
s6=RegFile[22];
s7=RegFile[23];
t0=RegFile[8];
t1=RegFile[9];
t2=RegFile[10];
t3=RegFile[11];
t4=RegFile[12];
t5=RegFile[13];
t6=RegFile[14];
t7=RegFile[15];
t8=RegFile[24];
t9=RegFile[25];
end
endmodule | 0 |
4,095 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module ShiftLeftTwo_26to28(Q, I);
input [25:0] I;
output [27:0] Q;
reg [27:0] Q;
always @ (I)
begin
Q[27:2] = I[25:0];
Q[1:0] = 2'b00;
end
endmodule | module ShiftLeftTwo_26to28(Q, I); |
input [25:0] I;
output [27:0] Q;
reg [27:0] Q;
always @ (I)
begin
Q[27:2] = I[25:0];
Q[1:0] = 2'b00;
end
endmodule | 0 |
4,096 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module ShiftLeftTwo_32to32(Q, I);
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[31:2] = I[29:0];
Q[1:0] = 'b0;
end
endmodule | module ShiftLeftTwo_32to32(Q, I); |
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[31:2] = I[29:0];
Q[1:0] = 'b0;
end
endmodule | 0 |
4,097 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module ALU(Alurlt,zero,Aluctrl,I1,I2);
input [31:0] I1,I2;
input [3:0] Aluctrl;
output [31:0] Alurlt;
output zero;
reg [31:0] Alurlt;
reg zero;
always @ (I1 or I2 or Aluctrl)
begin
if(Aluctrl==4'b0010) Alurlt = I1 + I2;
else if(Aluctrl==4'b0110) Alurlt=I1-I2;
else if(Aluctrl==4'b0000) Alurlt = I1 & I2;
else if(Aluctrl==4'b0001) Alurlt = I1 | I2;
else begin
if(I1<I2) Alurlt=1;
else Alurlt=0;
end
if (I1==I2) zero=1;
else zero=0;
end
endmodule | module ALU(Alurlt,zero,Aluctrl,I1,I2); |
input [31:0] I1,I2;
input [3:0] Aluctrl;
output [31:0] Alurlt;
output zero;
reg [31:0] Alurlt;
reg zero;
always @ (I1 or I2 or Aluctrl)
begin
if(Aluctrl==4'b0010) Alurlt = I1 + I2;
else if(Aluctrl==4'b0110) Alurlt=I1-I2;
else if(Aluctrl==4'b0000) Alurlt = I1 & I2;
else if(Aluctrl==4'b0001) Alurlt = I1 | I2;
else begin
if(I1<I2) Alurlt=1;
else Alurlt=0;
end
if (I1==I2) zero=1;
else zero=0;
end
endmodule | 0 |
4,098 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module Alucontrol(Aluctrl,Aluop,funct);
input [5:0] funct;
input [1:0] Aluop;
output [3:0] Aluctrl;
reg [3:0] Aluctrl;
always @ (Aluop or funct)
begin
if(Aluop==2'b00) Aluctrl=4'b0010;
else if(Aluop==2'b01) Aluctrl=4'b0110;
else if(Aluop==2'b11) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
end
endmodule | module Alucontrol(Aluctrl,Aluop,funct); |
input [5:0] funct;
input [1:0] Aluop;
output [3:0] Aluctrl;
reg [3:0] Aluctrl;
always @ (Aluop or funct)
begin
if(Aluop==2'b00) Aluctrl=4'b0010;
else if(Aluop==2'b01) Aluctrl=4'b0110;
else if(Aluop==2'b11) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
end
endmodule | 0 |
4,099 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module ZeroExtend(Q, I);
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = 16'b0;
end
endmodule | module ZeroExtend(Q, I); |
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = 16'b0;
end
endmodule | 0 |
4,100 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module SignExtend(Q, I);
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = {16{I[15]}};
end
endmodule | module SignExtend(Q, I); |
input [15:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I)
begin
Q[15:0] = I[15:0];
Q[31:16] = {16{I[15]}};
end
endmodule | 0 |
4,101 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module AddFour(Q, I);
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I) begin
Q=I+4;
end
endmodule | module AddFour(Q, I); |
input [31:0] I;
output [31:0] Q;
reg [31:0] Q;
always @ (I) begin
Q=I+4;
end
endmodule | 0 |
4,102 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module Adder_32bit(Q, I1, I2);
input [31:0] I1;
input [31:0] I2;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2) begin
Q=I1+I2;
end
endmodule | module Adder_32bit(Q, I1, I2); |
input [31:0] I1;
input [31:0] I2;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2) begin
Q=I1+I2;
end
endmodule | 0 |
4,103 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module Mux_32bit_2to1(Q, I1, I2, s);
input [31:0] I1;
input [31:0] I2;
input s;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | module Mux_32bit_2to1(Q, I1, I2, s); |
input [31:0] I1;
input [31:0] I2;
input s;
output [31:0] Q;
reg [31:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | 0 |
4,104 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module Mux_5bit_2to1(Q, I1, I2, s);
input [4:0] I1;
input [4:0] I2;
input s;
output [4:0] Q;
reg [4:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | module Mux_5bit_2to1(Q, I1, I2, s); |
input [4:0] I1;
input [4:0] I2;
input s;
output [4:0] Q;
reg [4:0] Q;
always @(I1, I2, s) begin
if (s==0) Q=I1;
else Q=I2;
end
endmodule | 0 |
4,105 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module And_1bit(Q, I1, I2);
input I1, I2;
output Q;
reg Q;
always @(I1, I2) Q=I1&I2;
endmodule | module And_1bit(Q, I1, I2); |
input I1, I2;
output Q;
reg Q;
always @(I1, I2) Q=I1&I2;
endmodule | 0 |
4,106 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, I);
input [5:0] I;
output RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
output [1:0] ALUOp;
reg RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
reg [1:0] ALUOp;
always @(I) begin
if (I==0) RegDst=1;
else RegDst=0;
if (I==2) Jump=1;
else Jump=0;
if (I==4) Branch=1;
else Branch=0;
if (I==5) BranchN=1;
else BranchN=0;
if (I==6'h23) MemRead=1;
else MemRead=0;
if (I==6'h23) MemtoReg=1;
else MemtoReg=0;
if (I==6'h23 || I==6'h2b || I==8) ALUOp=0;
else if (I==4 || I==5) ALUOp=1;
else if (I==6'h0c) ALUOp=3;
else ALUOp=2;
if (I==6'h2b) MemWrite=1;
else MemWrite=0;
if (I==0 || I==4 || I==5) ALUSrc=1;
else ALUSrc=0;
if (I==4 || I==5 || I==2 || I==6'h2b) RegWrite=0;
else RegWrite=1;
if (I==6'h0c) Andi=1;
else Andi=0;
end
endmodule | module Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, I); |
input [5:0] I;
output RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
output [1:0] ALUOp;
reg RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi;
reg [1:0] ALUOp;
always @(I) begin
if (I==0) RegDst=1;
else RegDst=0;
if (I==2) Jump=1;
else Jump=0;
if (I==4) Branch=1;
else Branch=0;
if (I==5) BranchN=1;
else BranchN=0;
if (I==6'h23) MemRead=1;
else MemRead=0;
if (I==6'h23) MemtoReg=1;
else MemtoReg=0;
if (I==6'h23 || I==6'h2b || I==8) ALUOp=0;
else if (I==4 || I==5) ALUOp=1;
else if (I==6'h0c) ALUOp=3;
else ALUOp=2;
if (I==6'h2b) MemWrite=1;
else MemWrite=0;
if (I==0 || I==4 || I==5) ALUSrc=1;
else ALUSrc=0;
if (I==4 || I==5 || I==2 || I==6'h2b) RegWrite=0;
else RegWrite=1;
if (I==6'h0c) Andi=1;
else Andi=0;
end
endmodule | 0 |
4,107 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module InstructionMemory(Instruction, ReadAddress);
input [31:0] ReadAddress;
output [31:0] Instruction;
reg [31:0] Instruction;
reg [31:0] Imemory [31:0];
initial begin
Imemory[0] = 32'b00100000000010000000000000100000;
Imemory[1] = 32'b00100000000010010000000000110111;
Imemory[2] = 32'b00000001000010011000000000100100;
Imemory[3] = 32'b00000001000010011000000000100101;
Imemory[4] = 32'b10101100000100000000000000000100;
Imemory[5] = 32'b10101100000010000000000000001000;
Imemory[6] = 32'b00000001000010011000100000100000;
Imemory[7] = 32'b00000001000010011001000000100010;
Imemory[8] = 32'b00010010001100100000000000001001;
Imemory[9] = 32'b10001100000100010000000000000100;
Imemory[10]= 32'b00110010001100100000000001001000;
Imemory[11] =32'b00010010001100100000000000001001;
Imemory[12] =32'b10001100000100110000000000001000;
Imemory[13] =32'b00010010000100110000000000001010;
Imemory[14] =32'b00000010010100011010000000101010;
Imemory[15] =32'b00010010100000000000000000001111;
Imemory[16] =32'b00000010001000001001000000100000;
Imemory[17] =32'b00001000000000000000000000001110;
Imemory[18] =32'b00100000000010000000000000000000;
Imemory[19] =32'b00100000000010010000000000000000;
Imemory[20] =32'b00001000000000000000000000011111;
Imemory[21] =32'b00100000000010000000000000000001;
Imemory[22] =32'b00100000000010010000000000000001;
Imemory[23] =32'b00001000000000000000000000011111;
Imemory[24] =32'b00100000000010000000000000000010;
Imemory[25] =32'b00100000000010010000000000000010;
Imemory[26] =32'b00001000000000000000000000011111;
Imemory[27] =32'b00100000000010000000000000000011;
Imemory[28] =32'b00100000000010010000000000000011;
Imemory[29] =32'b00001000000000000000000000011111;
Imemory[30] =32'b00000000000000000000000000000000;
Imemory[31] =32'b00000000000000000000000000000000;
end
always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];
endmodule | module InstructionMemory(Instruction, ReadAddress); |
input [31:0] ReadAddress;
output [31:0] Instruction;
reg [31:0] Instruction;
reg [31:0] Imemory [31:0];
initial begin
Imemory[0] = 32'b00100000000010000000000000100000;
Imemory[1] = 32'b00100000000010010000000000110111;
Imemory[2] = 32'b00000001000010011000000000100100;
Imemory[3] = 32'b00000001000010011000000000100101;
Imemory[4] = 32'b10101100000100000000000000000100;
Imemory[5] = 32'b10101100000010000000000000001000;
Imemory[6] = 32'b00000001000010011000100000100000;
Imemory[7] = 32'b00000001000010011001000000100010;
Imemory[8] = 32'b00010010001100100000000000001001;
Imemory[9] = 32'b10001100000100010000000000000100;
Imemory[10]= 32'b00110010001100100000000001001000;
Imemory[11] =32'b00010010001100100000000000001001;
Imemory[12] =32'b10001100000100110000000000001000;
Imemory[13] =32'b00010010000100110000000000001010;
Imemory[14] =32'b00000010010100011010000000101010;
Imemory[15] =32'b00010010100000000000000000001111;
Imemory[16] =32'b00000010001000001001000000100000;
Imemory[17] =32'b00001000000000000000000000001110;
Imemory[18] =32'b00100000000010000000000000000000;
Imemory[19] =32'b00100000000010010000000000000000;
Imemory[20] =32'b00001000000000000000000000011111;
Imemory[21] =32'b00100000000010000000000000000001;
Imemory[22] =32'b00100000000010010000000000000001;
Imemory[23] =32'b00001000000000000000000000011111;
Imemory[24] =32'b00100000000010000000000000000010;
Imemory[25] =32'b00100000000010010000000000000010;
Imemory[26] =32'b00001000000000000000000000011111;
Imemory[27] =32'b00100000000010000000000000000011;
Imemory[28] =32'b00100000000010010000000000000011;
Imemory[29] =32'b00001000000000000000000000011111;
Imemory[30] =32'b00000000000000000000000000000000;
Imemory[31] =32'b00000000000000000000000000000000;
end
always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];
endmodule | 0 |
4,108 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module DataMemory(ReadData, Address, WriteData, MemWrite, MemRead, clock, reset);
input [31:0] Address, WriteData;
input MemWrite, MemRead, clock, reset;
output [31:0] ReadData;
reg [31:0] ReadData;
reg [31:0] Dmemory [31:0];
integer i;
always @(Address[31:2], MemRead, Dmemory[Address[31:2]]) begin
if (MemRead) ReadData=Dmemory[Address[31:2]];
end
always @(negedge clock, posedge reset) begin
if (reset) begin
for(i=0; i<32; i=i+1)
Dmemory[i]=0;
end
else if (MemWrite) Dmemory[Address[31:2]]=WriteData;
end
endmodule | module DataMemory(ReadData, Address, WriteData, MemWrite, MemRead, clock, reset); |
input [31:0] Address, WriteData;
input MemWrite, MemRead, clock, reset;
output [31:0] ReadData;
reg [31:0] ReadData;
reg [31:0] Dmemory [31:0];
integer i;
always @(Address[31:2], MemRead, Dmemory[Address[31:2]]) begin
if (MemRead) ReadData=Dmemory[Address[31:2]];
end
always @(negedge clock, posedge reset) begin
if (reset) begin
for(i=0; i<32; i=i+1)
Dmemory[i]=0;
end
else if (MemWrite) Dmemory[Address[31:2]]=WriteData;
end
endmodule | 0 |
4,109 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module BrenchDetection(BranchMuxSignal, Branch, BranchN, Zero);
input Branch, BranchN, Zero;
output BranchMuxSignal;
reg BranchMuxSignal;
always @(Branch, BranchN, Zero) begin
if (Branch && Zero || BranchN && ~Zero) BranchMuxSignal=1;
else BranchMuxSignal=0;
end
endmodule | module BrenchDetection(BranchMuxSignal, Branch, BranchN, Zero); |
input Branch, BranchN, Zero;
output BranchMuxSignal;
reg BranchMuxSignal;
always @(Branch, BranchN, Zero) begin
if (Branch && Zero || BranchN && ~Zero) BranchMuxSignal=1;
else BranchMuxSignal=0;
end
endmodule | 0 |
4,110 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);
input [31:0] PCOut, ShowRegOut;
input ShowPC;
output [31:0] ShowNum;
reg [31:0] ShowNum;
always @(PCOut, ShowRegOut, ShowPC) begin
if (ShowPC) ShowNum=PCOut;
else ShowNum=ShowRegOut;
end
endmodule | module ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC); |
input [31:0] PCOut, ShowRegOut;
input ShowPC;
output [31:0] ShowNum;
reg [31:0] ShowNum;
always @(PCOut, ShowRegOut, ShowPC) begin
if (ShowPC) ShowNum=PCOut;
else ShowNum=ShowRegOut;
end
endmodule | 0 |
4,111 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);
input [3:0] Num_0, Num_1, Num_2, Num_3;
input clk_500;
output [6:0] Cathod;
output [3:0] Anode;
reg [6:0] Cathod;
reg [3:0] Anode;
reg [1:0] digit=0;
always @ (posedge clk_500)
begin
case(digit)
2'b00: digit<=2'b01;
2'b01: digit<=2'b10;
2'b10: digit<=2'b11;
2'b11: digit<=2'b00;
endcase
end
always @(digit, Num_0, Num_1, Num_2, Num_3)
begin
case (digit)
2'b00: begin
Anode <= 4'b1110;
case (Num_0)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b01: begin
Anode <= 4'b1101;
case (Num_1)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b10: begin
Anode <= 4'b1011;
case (Num_2)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b11: begin
Anode <= 4'b0111;
case (Num_3)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
endcase
end
endmodule | module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500); |
input [3:0] Num_0, Num_1, Num_2, Num_3;
input clk_500;
output [6:0] Cathod;
output [3:0] Anode;
reg [6:0] Cathod;
reg [3:0] Anode;
reg [1:0] digit=0;
always @ (posedge clk_500)
begin
case(digit)
2'b00: digit<=2'b01;
2'b01: digit<=2'b10;
2'b10: digit<=2'b11;
2'b11: digit<=2'b00;
endcase
end
always @(digit, Num_0, Num_1, Num_2, Num_3)
begin
case (digit)
2'b00: begin
Anode <= 4'b1110;
case (Num_0)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b01: begin
Anode <= 4'b1101;
case (Num_1)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b10: begin
Anode <= 4'b1011;
case (Num_2)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
2'b11: begin
Anode <= 4'b0111;
case (Num_3)
4'b0000: Cathod <= 7'b0000001;
4'b0001: Cathod <= 7'b1001111;
4'b0010: Cathod <= 7'b0010010;
4'b0011: Cathod <= 7'b0000110;
4'b0100: Cathod <= 7'b1001100;
4'b0101: Cathod <= 7'b0100100;
4'b0110: Cathod <= 7'b0100000;
4'b0111: Cathod <= 7'b0001111;
4'b1000: Cathod <= 7'b0000000;
4'b1001: Cathod <= 7'b0000100;
4'b1010: Cathod <= 7'b0001000;
4'b1011: Cathod <= 7'b1100000;
4'b1100: Cathod <= 7'b0110001;
4'b1101: Cathod <= 7'b1000010;
4'b1110: Cathod <= 7'b0110000;
default: Cathod <= 7'b0111000;
endcase end
endcase
end
endmodule | 0 |
4,112 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module clk_500_Hz(clk_50M, clk_500);
input clk_50M;
output clk_500;
reg clk_500;
reg[16:0] counter=0;
always @ (posedge clk_50M)
begin
if (counter < 100000-1) begin
counter<=counter+1;
clk_500<=0;
end else
begin
counter<=0;
clk_500<=1;
end
end
endmodule | module clk_500_Hz(clk_50M, clk_500); |
input clk_50M;
output clk_500;
reg clk_500;
reg[16:0] counter=0;
always @ (posedge clk_50M)
begin
if (counter < 100000-1) begin
counter<=counter+1;
clk_500<=0;
end else
begin
counter<=0;
clk_500<=1;
end
end
endmodule | 0 |
4,113 | data/full_repos/permissive/108382235/SingleCycle.v | 108,382,235 | SingleCycle.v | v | 626 | 247 | [] | [] | [] | [(21, 62), (67, 116), (120, 131), (135, 146), (151, 173), (177, 195), (199, 210), (214, 225), (229, 238), (242, 252), (256, 269), (273, 286), (290, 298), (302, 336), (340, 415), (419, 439), (443, 453), (457, 468), (472, 579), (583, 599), (603, 623)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n ^~~~~~~~~~~\n : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n ^~~~~~~~\n : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n ^~~~~~~~~~~~\n : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n ^~~~~~~~~~\n : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n if (MemRead) ReadData=Dmemory[Address[31:2]];\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_DataMemory\n else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 2,319 | module | module clk_10_Hz(clk_50M, clk_10, reset);
input clk_50M, reset;
output clk_10;
reg clk_10;
reg[22:0] counter=0;
always @ (posedge clk_50M)
begin
if (reset==1) begin
counter<=0;
clk_10<=0;
end else
if (counter < 5000000-1) begin
counter<=counter+1;
clk_10<=0;
end else
begin
counter<=0;
clk_10<=1;
end
end
endmodule | module clk_10_Hz(clk_50M, clk_10, reset); |
input clk_50M, reset;
output clk_10;
reg clk_10;
reg[22:0] counter=0;
always @ (posedge clk_50M)
begin
if (reset==1) begin
counter<=0;
clk_10<=0;
end else
if (counter < 5000000-1) begin
counter<=counter+1;
clk_10<=0;
end else
begin
counter<=0;
clk_10<=1;
end
end
endmodule | 0 |
4,114 | data/full_repos/permissive/108382235/SingleCycleTest.v | 108,382,235 | SingleCycleTest.v | v | 50 | 379 | [] | [] | [] | null | line:48: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0 SwitchClk_10=1; reset=1;Time=-1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 reset=0;\n ^\n%Error: data/full_repos/permissive/108382235/SingleCycleTest.v:43: Unsupported or unknown PLI call: $monitor\n $monitor(" Time: %d, CLK = %d, PC = %h \\n [$s0] = %h, [$s1] = %h, [$s2] = %h \\n [$s3] = %h, [$s4] = %h, [$s5] = %h \\n [$s6] = %h, [$s7] = %h, [$t0] = %h \\n [$t1] = %h, [$t2] = %h, [$t3] = %h \\n [$t4] = %h, [$t5] = %h, [$t6] = %h \\n [$t7] = %h, [$t8] = %h, [$t9] = %h \\n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n always #50 SwitchClk_10=~SwitchClk_10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $stop;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,320 | module | module SingleCycleTest;
wire [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC;
reg SwitchClk_10, reset;
reg [9:0] Time;
SingleCycle UUT(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,CurrentPC, SwitchClk_10, reset);
always @(posedge SwitchClk_10) begin
Time=Time+1;
end
initial begin
#0 SwitchClk_10=1; reset=1;Time=-1;
#10 reset=0;
end
initial begin
$display("**********************************************");
$display("The textual simulation results:");
$display("**********************************************");
$monitor(" Time: %d, CLK = %d, PC = %h \n [$s0] = %h, [$s1] = %h, [$s2] = %h \n [$s3] = %h, [$s4] = %h, [$s5] = %h \n [$s6] = %h, [$s7] = %h, [$t0] = %h \n [$t1] = %h, [$t2] = %h, [$t3] = %h \n [$t4] = %h, [$t5] = %h, [$t6] = %h \n [$t7] = %h, [$t8] = %h, [$t9] = %h \n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);
end
always #50 SwitchClk_10=~SwitchClk_10;
initial #3000 $stop;
endmodule | module SingleCycleTest; |
wire [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC;
reg SwitchClk_10, reset;
reg [9:0] Time;
SingleCycle UUT(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,CurrentPC, SwitchClk_10, reset);
always @(posedge SwitchClk_10) begin
Time=Time+1;
end
initial begin
#0 SwitchClk_10=1; reset=1;Time=-1;
#10 reset=0;
end
initial begin
$display("**********************************************");
$display("The textual simulation results:");
$display("**********************************************");
$monitor(" Time: %d, CLK = %d, PC = %h \n [$s0] = %h, [$s1] = %h, [$s2] = %h \n [$s3] = %h, [$s4] = %h, [$s5] = %h \n [$s6] = %h, [$s7] = %h, [$t0] = %h \n [$t1] = %h, [$t2] = %h, [$t3] = %h \n [$t4] = %h, [$t5] = %h, [$t6] = %h \n [$t7] = %h, [$t8] = %h, [$t9] = %h \n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);
end
always #50 SwitchClk_10=~SwitchClk_10;
initial #3000 $stop;
endmodule | 0 |
4,124 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module dff (output reg q, output qn,
input d, input clk);
always @(posedge clk) begin
q <= d;
end
assign qn = ~q;
endmodule | module dff (output reg q, output qn,
input d, input clk); |
always @(posedge clk) begin
q <= d;
end
assign qn = ~q;
endmodule | 1 |
4,125 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module dff_ne (output reg q, output qn,
input d, input clk);
always @(negedge clk) q <= d;
assign qn = ~q;
endmodule | module dff_ne (output reg q, output qn,
input d, input clk); |
always @(negedge clk) q <= d;
assign qn = ~q;
endmodule | 1 |
4,126 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module dff_en (output reg q, output qn,
input d, en, clk);
always @(posedge clk) begin
if (en)
q <= d;
end
assign qn = ~q;
endmodule | module dff_en (output reg q, output qn,
input d, en, clk); |
always @(posedge clk) begin
if (en)
q <= d;
end
assign qn = ~q;
endmodule | 1 |
4,127 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module JKFF (output reg q, qn,
input clk, j, k);
always @(posedge clk) begin
case ({j, k})
2'b10: {q, qn} <= 2'b10;
2'b01: {q, qn} <= 2'b01;
2'b11: {q, qn} <= {qn, q};
default ;
endcase
end
endmodule | module JKFF (output reg q, qn,
input clk, j, k); |
always @(posedge clk) begin
case ({j, k})
2'b10: {q, qn} <= 2'b10;
2'b01: {q, qn} <= 2'b01;
2'b11: {q, qn} <= {qn, q};
default ;
endcase
end
endmodule | 1 |
4,128 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module JKFF2 (output reg q, output qn,
input clk, j, k);
always @(posedge clk) begin
case ({j, k})
2'b10: q <= 1;
2'b01: q <= 0;
2'b11: q <= ~q;
default ;
endcase
end
assign qn = ~q;
endmodule | module JKFF2 (output reg q, output qn,
input clk, j, k); |
always @(posedge clk) begin
case ({j, k})
2'b10: q <= 1;
2'b01: q <= 0;
2'b11: q <= ~q;
default ;
endcase
end
assign qn = ~q;
endmodule | 1 |
4,129 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module TFF (output reg q, qn,
input clk, rst_n, t);
always @(posedge clk) begin
if (~rst_n) {q, qn} <= 2'b01;
else begin
if (t)
{q, qn} <= {qn, q};
end
end
endmodule | module TFF (output reg q, qn,
input clk, rst_n, t); |
always @(posedge clk) begin
if (~rst_n) {q, qn} <= 2'b01;
else begin
if (t)
{q, qn} <= {qn, q};
end
end
endmodule | 1 |
4,130 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module DFF_asr (output reg q, qn,
input d, clk, reset, set);
always @(posedge clk, posedge reset, posedge set) begin
if (reset)
{q, qn} <= 2'b01;
else begin
if (set)
{q, qn} <= 2'b10;
else
{q, qn} <= {d, ~d};
end
end
endmodule | module DFF_asr (output reg q, qn,
input d, clk, reset, set); |
always @(posedge clk, posedge reset, posedge set) begin
if (reset)
{q, qn} <= 2'b01;
else begin
if (set)
{q, qn} <= 2'b10;
else
{q, qn} <= {d, ~d};
end
end
endmodule | 1 |
4,131 | data/full_repos/permissive/108410192/src/FlipFlop.v | 108,410,192 | FlipFlop.v | v | 100 | 63 | [] | [] | [] | null | line:38: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/FlipFlop.v:97: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 2,325 | module | module DFFn #(parameter N=8) (output reg [N-1:0] q,
input [N-1:0] d,
input clk, rst_n);
always @(posedge clk, negedge rst_n) begin
if (~rst_n) q <= 0;
else q <= d
end
endmodule | module DFFn #(parameter N=8) (output reg [N-1:0] q,
input [N-1:0] d,
input clk, rst_n); |
always @(posedge clk, negedge rst_n) begin
if (~rst_n) q <= 0;
else q <= d
end
endmodule | 1 |
4,132 | data/full_repos/permissive/108410192/src/Latch.v | 108,410,192 | Latch.v | v | 20 | 41 | [] | [] | [] | null | line:8: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/Latch.v:9: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 2,326 | module | module SRLatch(output reg q, qbar,
input s, r);
always @(*) begin
case ({s, r})
2'b01: {q, qbar} <= 2'b01;
2'b10: {q, qbar} <= 2'b10;
2'b11: {q, qbar} <= 2'bx;
default ;
end
endmodule | module SRLatch(output reg q, qbar,
input s, r); |
always @(*) begin
case ({s, r})
2'b01: {q, qbar} <= 2'b01;
2'b10: {q, qbar} <= 2'b10;
2'b11: {q, qbar} <= 2'bx;
default ;
end
endmodule | 1 |
4,133 | data/full_repos/permissive/108410192/src/Latch.v | 108,410,192 | Latch.v | v | 20 | 41 | [] | [] | [] | null | line:8: before: ";" | null | 1: b'%Error: data/full_repos/permissive/108410192/src/Latch.v:9: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 2,326 | module | module DLatch(output reg q, output qbar,
input d, input ctl);
always @(*) begin
if (ctl)
q <= d;
end
assign qbar = ~q;
endmodule | module DLatch(output reg q, output qbar,
input d, input ctl); |
always @(*) begin
if (ctl)
q <= d;
end
assign qbar = ~q;
endmodule | 1 |
4,135 | data/full_repos/permissive/108410192/src/LSFR.v | 108,410,192 | LSFR.v | v | 54 | 62 | [] | [] | [] | [(3, 27), (29, 53)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108410192/src/LSFR.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'LFSR\'\nmodule LFSR (output reg [0:7] q,\n ^~~~\n : ... Top module \'LFSR2\'\nmodule LFSR2 (output reg [1:8] q,\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:29: Little bit endian vector: MSB < LSB of bit range: 1:8\nmodule LFSR2 (output reg [1:8] q,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:31: Little bit endian vector: MSB < LSB of bit range: 1:8\n input [1:8] din);\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:3: Little bit endian vector: MSB < LSB of bit range: 0:7\nmodule LFSR (output reg [0:7] q,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] din);\n ^\n%Error: Exiting due to 5 warning(s)\n' | 2,328 | module | module LFSR (output reg [0:7] q,
input clk, rst_n, load,
input [0:7] din);
always @(posedge clk) begin
if (~rst_n)
q <= 8'b0;
else begin
if (load)
q <= (|din) ? din : 8'b0000_0001;
else begin
if (q == 8'b0) q <= 8'b0000_0001;
else begin
q[7] <= q[6];
q[6] <= q[5] ^ q[7];
q[5] <= q[4] ^ q[7];
{q[4], q[3], q[2]} <= {q[3], q[2], q[1]};
q[1] <= q[0] ^ q[7];
q[0] <= q[7];
end
end
end
end
endmodule | module LFSR (output reg [0:7] q,
input clk, rst_n, load,
input [0:7] din); |
always @(posedge clk) begin
if (~rst_n)
q <= 8'b0;
else begin
if (load)
q <= (|din) ? din : 8'b0000_0001;
else begin
if (q == 8'b0) q <= 8'b0000_0001;
else begin
q[7] <= q[6];
q[6] <= q[5] ^ q[7];
q[5] <= q[4] ^ q[7];
{q[4], q[3], q[2]} <= {q[3], q[2], q[1]};
q[1] <= q[0] ^ q[7];
q[0] <= q[7];
end
end
end
end
endmodule | 1 |
4,136 | data/full_repos/permissive/108410192/src/LSFR.v | 108,410,192 | LSFR.v | v | 54 | 62 | [] | [] | [] | [(3, 27), (29, 53)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/108410192/src/LSFR.v:29: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'LFSR\'\nmodule LFSR (output reg [0:7] q,\n ^~~~\n : ... Top module \'LFSR2\'\nmodule LFSR2 (output reg [1:8] q,\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:29: Little bit endian vector: MSB < LSB of bit range: 1:8\nmodule LFSR2 (output reg [1:8] q,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:31: Little bit endian vector: MSB < LSB of bit range: 1:8\n input [1:8] din);\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:3: Little bit endian vector: MSB < LSB of bit range: 0:7\nmodule LFSR (output reg [0:7] q,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] din);\n ^\n%Error: Exiting due to 5 warning(s)\n' | 2,328 | module | module LFSR2 (output reg [1:8] q,
input clk, rst_n, load,
input [1:8] din);
always @(posedge clk) begin
if (~rst_n)
q <= 8'b0;
else begin
if (load)
q <= (|din) ? din : 8'b0000_0001;
else begin
if (q == 8'b0) q <= 8'b0000_0001;
else begin
q[8] <= q[7];
q[7] <= q[6] ^ q[8];
q[6] <= q[5] ^ q[8];
{q[5], q[4], q[3]} <= {q[4], q[3], q[2]};
q[2] <= q[1] ^ q[8];
q[1] <= q[8];
end
end
end
end
endmodule | module LFSR2 (output reg [1:8] q,
input clk, rst_n, load,
input [1:8] din); |
always @(posedge clk) begin
if (~rst_n)
q <= 8'b0;
else begin
if (load)
q <= (|din) ? din : 8'b0000_0001;
else begin
if (q == 8'b0) q <= 8'b0000_0001;
else begin
q[8] <= q[7];
q[7] <= q[6] ^ q[8];
q[6] <= q[5] ^ q[8];
{q[5], q[4], q[3]} <= {q[4], q[3], q[2]};
q[2] <= q[1] ^ q[8];
q[1] <= q[8];
end
end
end
end
endmodule | 1 |
4,137 | data/full_repos/permissive/108410192/src/RAM.v | 108,410,192 | RAM.v | v | 111 | 63 | [] | [] | [] | null | line:17: before: ":" | null | 1: b"%Error: data/full_repos/permissive/108410192/src/RAM.v:18: syntax error, unexpected if\n if (cs && we)\n ^~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:69: syntax error, unexpected ';', expecting ')' or ','\n input clk;\n ^\n%Error: data/full_repos/permissive/108410192/src/RAM.v:79: syntax error, unexpected always\n always @(posedge clk) begin : MEM_WRITE\n ^~~~~~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:89: syntax error, unexpected assign\n assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 2,329 | module | module RAM_sync #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] data_out,
input [ADDR_WIDTH-1:0] address,
input [DATA_WIDTH-1:0] data_in,
input clk, cs, we, oe);
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data;
assign data_out = (cs && ~we && oe) ? data : 8'bz;
always @(posedge clk) bgein : MEM_WRITE
if (cs && we)
mem[address] <= data_in;
end
always @(posedge clk) bgein : MEM_READ
if (cs && ~we && oe)
data <= mem[address];
end
endmodule | module RAM_sync #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] data_out,
input [ADDR_WIDTH-1:0] address,
input [DATA_WIDTH-1:0] data_in,
input clk, cs, we, oe); |
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data;
assign data_out = (cs && ~we && oe) ? data : 8'bz;
always @(posedge clk) bgein : MEM_WRITE
if (cs && we)
mem[address] <= data_in;
end
always @(posedge clk) bgein : MEM_READ
if (cs && ~we && oe)
data <= mem[address];
end
endmodule | 1 |
4,138 | data/full_repos/permissive/108410192/src/RAM.v | 108,410,192 | RAM.v | v | 111 | 63 | [] | [] | [] | null | line:17: before: ":" | null | 1: b"%Error: data/full_repos/permissive/108410192/src/RAM.v:18: syntax error, unexpected if\n if (cs && we)\n ^~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:69: syntax error, unexpected ';', expecting ')' or ','\n input clk;\n ^\n%Error: data/full_repos/permissive/108410192/src/RAM.v:79: syntax error, unexpected always\n always @(posedge clk) begin : MEM_WRITE\n ^~~~~~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:89: syntax error, unexpected assign\n assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 2,329 | module | module RAM_sync2 #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] data_out,
input [ADDR_WIDTH-1:0] address,
input [DATA_WIDTH-1:0] data_in,
input clk, cs, we, oe);
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data;
assign data_out = (cs && ~we && oe) ? data : 8'bz;
always @(posedge clk) begin
if (cs)
case ({we, oe})
2'b01: data <= mem[address];
2'b10: mem[address] <= data_in;
default: ;
endcase
end
endmodule | module RAM_sync2 #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] data_out,
input [ADDR_WIDTH-1:0] address,
input [DATA_WIDTH-1:0] data_in,
input clk, cs, we, oe); |
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data;
assign data_out = (cs && ~we && oe) ? data : 8'bz;
always @(posedge clk) begin
if (cs)
case ({we, oe})
2'b01: data <= mem[address];
2'b10: mem[address] <= data_in;
default: ;
endcase
end
endmodule | 1 |
4,139 | data/full_repos/permissive/108410192/src/RAM.v | 108,410,192 | RAM.v | v | 111 | 63 | [] | [] | [] | null | line:17: before: ":" | null | 1: b"%Error: data/full_repos/permissive/108410192/src/RAM.v:18: syntax error, unexpected if\n if (cs && we)\n ^~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:69: syntax error, unexpected ';', expecting ')' or ','\n input clk;\n ^\n%Error: data/full_repos/permissive/108410192/src/RAM.v:79: syntax error, unexpected always\n always @(posedge clk) begin : MEM_WRITE\n ^~~~~~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:89: syntax error, unexpected assign\n assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 2,329 | module | module DualPortRAM #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] dout0,
input [ADDR_WIDTH-1:0] address0,
input [DATA_WIDTH-1:0] din0,
input cs0, we0, oe0,
output [DATA_WIDTH-1:0] dout1,
input [ADDR_WIDTH-1:0] address1,
input [DATA_WIDTH-1:0] din1,
input cs1, we1, oe1,
input clk;
);
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
always @(posedge clk) begin : MEM_WRITE
if (cs0 && we0) begin
mem[address0] <= din0;
end
else if (cs1 && we1) begin
mem[address1] <= din1;
end
end
wire we = we0 | we1;
assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;
always @(posedge clk) begin : MEM_READ_0
if (cs0 && oe0 && ~we) begin
data0 <= mem[address0];
end
else begin
data0 <= 8'b0;
end
end
assign dout1 = (cs1 && oe1 && ~we) ? data1 : 8'bz;
always @(posedge clk) begin : MEM_READ_1
if (cs1 && oe1 && ~we) begin
data1 <= mem[address1];
end
else begin
data1 <= 8'b0;
end
end
endmodule | module DualPortRAM #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
(output [DATA_WIDTH-1:0] dout0,
input [ADDR_WIDTH-1:0] address0,
input [DATA_WIDTH-1:0] din0,
input cs0, we0, oe0,
output [DATA_WIDTH-1:0] dout1,
input [ADDR_WIDTH-1:0] address1,
input [DATA_WIDTH-1:0] din1,
input cs1, we1, oe1,
input clk; |
);
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
always @(posedge clk) begin : MEM_WRITE
if (cs0 && we0) begin
mem[address0] <= din0;
end
else if (cs1 && we1) begin
mem[address1] <= din1;
end
end
wire we = we0 | we1;
assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;
always @(posedge clk) begin : MEM_READ_0
if (cs0 && oe0 && ~we) begin
data0 <= mem[address0];
end
else begin
data0 <= 8'b0;
end
end
assign dout1 = (cs1 && oe1 && ~we) ? data1 : 8'bz;
always @(posedge clk) begin : MEM_READ_1
if (cs1 && oe1 && ~we) begin
data1 <= mem[address1];
end
else begin
data1 <= 8'b0;
end
end
endmodule | 1 |
4,145 | data/full_repos/permissive/108500919/proc.v | 108,500,919 | proc.v | v | 74 | 83 | [] | [] | [] | null | line:74: before: "version" | data/verilator_xmls/4b00334f-c464-4a91-8a9c-a50bec7f2c42.xml | null | 2,332 | module | module proc(
input [15:0] x,
input [15:0] x_init,
input [15:0] a,
input reset,
input clk,
output[15:0] y
);
reg [15:0] cuenta;
reg [15:0] suma;
reg [15:0]ym;
assign y = ym;
always @ (posedge clk )
begin
if (reset == 1'b1)
cuenta <= 16'h0000;
else
begin
if (cuenta < 16'h0003)
cuenta <= cuenta + 16'h0001;
else
cuenta <= 16'h0000;
end
end
always @(posedge clk )
begin
if (reset == 1'b1)
begin
ym <= x_init;
suma <= 16'h0000;
end
else
begin
if (cuenta < 16'h0003)
begin
ym <= x;
suma <= suma + x * a;
end
else
begin
ym <= suma + x * a;
suma <= 16'h0000;
end
end
end
endmodule | module proc(
input [15:0] x,
input [15:0] x_init,
input [15:0] a,
input reset,
input clk,
output[15:0] y
); |
reg [15:0] cuenta;
reg [15:0] suma;
reg [15:0]ym;
assign y = ym;
always @ (posedge clk )
begin
if (reset == 1'b1)
cuenta <= 16'h0000;
else
begin
if (cuenta < 16'h0003)
cuenta <= cuenta + 16'h0001;
else
cuenta <= 16'h0000;
end
end
always @(posedge clk )
begin
if (reset == 1'b1)
begin
ym <= x_init;
suma <= 16'h0000;
end
else
begin
if (cuenta < 16'h0003)
begin
ym <= x;
suma <= suma + x * a;
end
else
begin
ym <= suma + x * a;
suma <= 16'h0000;
end
end
end
endmodule | 0 |
4,146 | data/full_repos/permissive/108500919/proc_tb.v | 108,500,919 | proc_tb.v | v | 63 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Error: data/full_repos/permissive/108500919/proc_tb.v:32: Cannot find file containing module: \'proc\'\n proc uut(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.v\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.sv\n proc\n proc.v\n proc.sv\n obj_dir/proc\n obj_dir/proc.v\n obj_dir/proc.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,333 | module | module proc_tb( );
reg [15:0] x;
reg [15:0] x_init;
reg [15:0] a;
reg reset;
reg clk;
wire [15:0] y;
proc uut(
.x(x),
.x_init(x_init),
.a(a),
.reset(reset),
.clk(clk),
.y(y)
);
always begin
clk =1'b1;
#50;
clk =1'b0;
#50;
end
initial begin
reset = 1'b1;
#50;
reset = 1'b0;
#50;
a = 16'h0003;
x_init = 16'h0002;
x = 16'h0001;
#100;
#100;
end
endmodule | module proc_tb( ); |
reg [15:0] x;
reg [15:0] x_init;
reg [15:0] a;
reg reset;
reg clk;
wire [15:0] y;
proc uut(
.x(x),
.x_init(x_init),
.a(a),
.reset(reset),
.clk(clk),
.y(y)
);
always begin
clk =1'b1;
#50;
clk =1'b0;
#50;
end
initial begin
reset = 1'b1;
#50;
reset = 1'b0;
#50;
a = 16'h0003;
x_init = 16'h0002;
x = 16'h0001;
#100;
#100;
end
endmodule | 0 |
4,147 | data/full_repos/permissive/108500919/unidad.v | 108,500,919 | unidad.v | v | 74 | 83 | [] | [] | [] | [(23, 73)] | null | null | 1: b"%Error: data/full_repos/permissive/108500919/unidad.v:36: Cannot find file containing module: 'proc'\n proc modulo1(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.v\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.sv\n proc\n proc.v\n proc.sv\n obj_dir/proc\n obj_dir/proc.v\n obj_dir/proc.sv\n%Error: data/full_repos/permissive/108500919/unidad.v:46: Cannot find file containing module: 'proc'\n proc modulo2(\n ^~~~\n%Error: data/full_repos/permissive/108500919/unidad.v:55: Cannot find file containing module: 'proc'\n proc modulo3(\n ^~~~\n%Error: data/full_repos/permissive/108500919/unidad.v:64: Cannot find file containing module: 'proc'\n proc modulo4(\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 2,334 | module | module unidad(
input [15:0] x1,x2,x3,x4,
input [15:0] a1,a2,a3,a4,
input reset,
input clk,
output wire [15:0] y1,y2,y3,y4
);
proc modulo1(
.x(y4),
.x_init(x1),
.a(a1),
.reset(reset),
.clk(clk),
.y(y1)
);
proc modulo2(
.x(y1),
.x_init(x2),
.a(a2),
.reset(reset),
.clk(clk),
.y(y2)
);
proc modulo3(
.x(y2),
.x_init(x3),
.a(a3),
.reset(reset),
.clk(clk),
.y(y3)
);
proc modulo4(
.x(y3),
.x_init(x4),
.a(a4),
.reset(reset),
.clk(clk),
.y(y4)
);
endmodule | module unidad(
input [15:0] x1,x2,x3,x4,
input [15:0] a1,a2,a3,a4,
input reset,
input clk,
output wire [15:0] y1,y2,y3,y4
); |
proc modulo1(
.x(y4),
.x_init(x1),
.a(a1),
.reset(reset),
.clk(clk),
.y(y1)
);
proc modulo2(
.x(y1),
.x_init(x2),
.a(a2),
.reset(reset),
.clk(clk),
.y(y2)
);
proc modulo3(
.x(y2),
.x_init(x3),
.a(a3),
.reset(reset),
.clk(clk),
.y(y3)
);
proc modulo4(
.x(y3),
.x_init(x4),
.a(a4),
.reset(reset),
.clk(clk),
.y(y4)
);
endmodule | 0 |
4,148 | data/full_repos/permissive/108500919/unidad_tb.v | 108,500,919 | unidad_tb.v | v | 90 | 83 | [] | [] | [] | [(23, 89)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #75;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/108500919/unidad_tb.v:35: Cannot find file containing module: \'unidad\'\n unidad uut(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad.v\n data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad.sv\n unidad\n unidad.v\n unidad.sv\n obj_dir/unidad\n obj_dir/unidad.v\n obj_dir/unidad.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,335 | module | module unidad_tb();
reg [15:0] a1,a2,a3,a4;
wire [15:0] y1,y2,y3,y4;
reg reset;
reg clk;
parameter x1 = 16'h0004;
parameter x2 = 16'h0003;
parameter x3 = 16'h0002;
parameter x4 = 16'h0001;
unidad uut(
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.a1(a1),
.a2(a2),
.a3(a3),
.a4(a4),
.reset(reset),
.clk(clk),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4)
);
always begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#75;
reset = 1'b0;
#25;
a1 = 16'h0001;
a2 = 16'h0008;
a3 = 16'h000a;
a4 = 16'h000f;
#100;
a1 = 16'h0002;
a2 = 16'h0005;
a3 = 16'h0009;
a4 = 16'h000e;
#100;
a1 = 16'h0003;
a2 = 16'h0006;
a3 = 16'h000c;
a4 = 16'h000d;
#100;
a1 = 16'h0004;
a2 = 16'h0007;
a3 = 16'h000b;
a4 = 16'h0010;
#100;
end
endmodule | module unidad_tb(); |
reg [15:0] a1,a2,a3,a4;
wire [15:0] y1,y2,y3,y4;
reg reset;
reg clk;
parameter x1 = 16'h0004;
parameter x2 = 16'h0003;
parameter x3 = 16'h0002;
parameter x4 = 16'h0001;
unidad uut(
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.a1(a1),
.a2(a2),
.a3(a3),
.a4(a4),
.reset(reset),
.clk(clk),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4)
);
always begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#75;
reset = 1'b0;
#25;
a1 = 16'h0001;
a2 = 16'h0008;
a3 = 16'h000a;
a4 = 16'h000f;
#100;
a1 = 16'h0002;
a2 = 16'h0005;
a3 = 16'h0009;
a4 = 16'h000e;
#100;
a1 = 16'h0003;
a2 = 16'h0006;
a3 = 16'h000c;
a4 = 16'h000d;
#100;
a1 = 16'h0004;
a2 = 16'h0007;
a3 = 16'h000b;
a4 = 16'h0010;
#100;
end
endmodule | 0 |
4,149 | data/full_repos/permissive/108561032/alu32.v | 108,561,032 | alu32.v | v | 42 | 86 | [] | [] | [] | [(1, 41)] | null | data/verilator_xmls/37a5340c-1671-4cdb-9e01-a66ac94747d5.xml | null | 2,336 | module | module alu32(reset,data1, data2 ,clk, ctrl, oCarry,oZero, out);
input [31:0] data1;
input [31:0] data2;
input reset;
input [2:0] ctrl;
input clk;
output reg oCarry;
output reg oZero;
output reg [31:0] out;
always@ (*)
begin
if (reset == 1)
oZero = 1'b0;
else
oZero=oZero;
case(ctrl)
3'b010: {oCarry ,out} = data1+data2;
3'b110: begin {oCarry, out} = data1-data2;
if (out == 32'b0000_0000_0000_0000_0000_0000_0000_0000)
oZero = 1;
else
oZero = 0;
end
3'b000: out = data1&data2;
3'b001: out = data1|data2;
3'b111: out = data1^data2;
default:
begin
out = data1;
oZero = 0;
oCarry = 0;
end
endcase
end
endmodule | module alu32(reset,data1, data2 ,clk, ctrl, oCarry,oZero, out); |
input [31:0] data1;
input [31:0] data2;
input reset;
input [2:0] ctrl;
input clk;
output reg oCarry;
output reg oZero;
output reg [31:0] out;
always@ (*)
begin
if (reset == 1)
oZero = 1'b0;
else
oZero=oZero;
case(ctrl)
3'b010: {oCarry ,out} = data1+data2;
3'b110: begin {oCarry, out} = data1-data2;
if (out == 32'b0000_0000_0000_0000_0000_0000_0000_0000)
oZero = 1;
else
oZero = 0;
end
3'b000: out = data1&data2;
3'b001: out = data1|data2;
3'b111: out = data1^data2;
default:
begin
out = data1;
oZero = 0;
oCarry = 0;
end
endcase
end
endmodule | 0 |
4,150 | data/full_repos/permissive/108561032/control.v | 108,561,032 | control.v | v | 92 | 149 | [] | [] | [] | [(23, 91)] | null | data/verilator_xmls/a5d2738b-868a-46b2-a43c-555adc061f75.xml | null | 2,340 | module | module control(instru,clk,Control,FFetch,FDecode,FExecute,FMemory);
input [5:0]instru;
input clk;
input FFetch;
input FDecode;
input FExecute;
input FMemory;
output reg [9:0] Control;
reg [9:0] aux;
wire [3:0] auxControl;
always @ (*)
begin
case(instru)
6'b000_000: aux=10'b0100_100_010;
6'b100_011: aux=10'b00_1111_0000;
6'b101_011: aux=10'b0x1x001000;
6'b000_100: aux=10'b0x0x000101;
6'b111_111: aux=10'b00_1010_0000;
6'b111_110: aux=10'b00_0000_0101;
default: aux=10'b00_1010_0000;
endcase
end
assign auxControl = {FFetch,FDecode,FExecute,FMemory};
always @(*)
begin
if(auxControl == 4'b1111)
Control = aux;
else
Control = aux;
end
endmodule | module control(instru,clk,Control,FFetch,FDecode,FExecute,FMemory); |
input [5:0]instru;
input clk;
input FFetch;
input FDecode;
input FExecute;
input FMemory;
output reg [9:0] Control;
reg [9:0] aux;
wire [3:0] auxControl;
always @ (*)
begin
case(instru)
6'b000_000: aux=10'b0100_100_010;
6'b100_011: aux=10'b00_1111_0000;
6'b101_011: aux=10'b0x1x001000;
6'b000_100: aux=10'b0x0x000101;
6'b111_111: aux=10'b00_1010_0000;
6'b111_110: aux=10'b00_0000_0101;
default: aux=10'b00_1010_0000;
endcase
end
assign auxControl = {FFetch,FDecode,FExecute,FMemory};
always @(*)
begin
if(auxControl == 4'b1111)
Control = aux;
else
Control = aux;
end
endmodule | 0 |
4,151 | data/full_repos/permissive/108561032/control1.v | 108,561,032 | control1.v | v | 62 | 94 | [] | [] | [] | null | line:36: before: "parameter" | data/verilator_xmls/eb05ab33-faf4-4bd6-8aea-2a9ac98c085f.xml | null | 2,341 | module | module control1(reset,clk,Control,RegDest,ALUOp,FuenteALU,Controls1,Saltoincond);
input [9:0] Control;
input clk;
input reset;
output reg [9:0] Controls1;
output reg RegDest;
output reg Saltoincond;
output reg [1:0]ALUOp;
output reg FuenteALU;
always @(posedge clk)
begin
Controls1 = Control;
Saltoincond = Control[9];
RegDest = Control[8];
FuenteALU = Control[7];
ALUOp = Control[1:0];
end
endmodule | module control1(reset,clk,Control,RegDest,ALUOp,FuenteALU,Controls1,Saltoincond); |
input [9:0] Control;
input clk;
input reset;
output reg [9:0] Controls1;
output reg RegDest;
output reg Saltoincond;
output reg [1:0]ALUOp;
output reg FuenteALU;
always @(posedge clk)
begin
Controls1 = Control;
Saltoincond = Control[9];
RegDest = Control[8];
FuenteALU = Control[7];
ALUOp = Control[1:0];
end
endmodule | 0 |
4,152 | data/full_repos/permissive/108561032/control2.v | 108,561,032 | control2.v | v | 73 | 83 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/9e4e4389-12dd-489a-9dc8-dc42b43729ce.xml | null | 2,342 | module | module control2(reset,Control,clk,SaltoCond,EscrMem,Controls2,LeerMem);
input wire [9:0] Control;
input clk;
output reg [9:0] Controls2;
input reset;
output reg SaltoCond;
output reg LeerMem;
output reg EscrMem;
wire SaltoConda;
assign SaltoConda = 1'b0;
always @(posedge clk)
begin
if (Control[2] == 1'b1)
begin
SaltoCond = 1'b1;
end
else
SaltoCond=SaltoConda;
end
always @(posedge clk)
begin
Controls2 = Control;
EscrMem = Control[3];
LeerMem = Control[4];
end
endmodule | module control2(reset,Control,clk,SaltoCond,EscrMem,Controls2,LeerMem); |
input wire [9:0] Control;
input clk;
output reg [9:0] Controls2;
input reset;
output reg SaltoCond;
output reg LeerMem;
output reg EscrMem;
wire SaltoConda;
assign SaltoConda = 1'b0;
always @(posedge clk)
begin
if (Control[2] == 1'b1)
begin
SaltoCond = 1'b1;
end
else
SaltoCond=SaltoConda;
end
always @(posedge clk)
begin
Controls2 = Control;
EscrMem = Control[3];
LeerMem = Control[4];
end
endmodule | 0 |
4,153 | data/full_repos/permissive/108561032/control3.v | 108,561,032 | control3.v | v | 66 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/dc7e414c-0691-4170-9f4b-cb8771ec7e24.xml | null | 2,343 | module | module control3(reset,Control,clk,MemaReg,EscrReg);
input wire [9:0] Control;
input clk;
input reset;
output reg MemaReg;
output reg EscrReg;
always @(posedge clk)
begin
if (reset == 1)
begin
end
else
begin
end
MemaReg = Control[6];
EscrReg = Control[5];
end
endmodule | module control3(reset,Control,clk,MemaReg,EscrReg); |
input wire [9:0] Control;
input clk;
input reset;
output reg MemaReg;
output reg EscrReg;
always @(posedge clk)
begin
if (reset == 1)
begin
end
else
begin
end
MemaReg = Control[6];
EscrReg = Control[5];
end
endmodule | 0 |
4,154 | data/full_repos/permissive/108561032/Decode.v | 108,561,032 | Decode.v | v | 56 | 141 | [] | [] | [] | [(23, 55)] | null | data/verilator_xmls/2176e788-67e8-4dc2-ab98-579b545f14f2.xml | null | 2,347 | module | module Decode(clk,data1R,data2R,data1D,data2D,instru2016,instru2016D,instru1511,instru1511D,oinstru,oinstruD,sum2sumOF,sum2sumOF_D,FDecode);
input clk;
input [31:0] data1R;
input [31:0] data2R;
input [4:0] instru2016;
input [4:0] instru1511;
input [31:0] oinstru;
input [31:0] sum2sumOF;
output reg [31:0] data1D;
output reg [31:0] data2D;
output reg [4:0] instru2016D;
output reg [4:0] instru1511D;
output reg [31:0] oinstruD;
output reg [31:0] sum2sumOF_D;
output wire FDecode;
assign FDecode = clk ? 1'b1 : 1'b0;
always @(posedge clk)
begin
data1D = data1R;
data2D = data2R;
instru2016D = instru2016;
instru1511D = instru1511;
oinstruD = oinstru;
sum2sumOF_D = sum2sumOF;
end
endmodule | module Decode(clk,data1R,data2R,data1D,data2D,instru2016,instru2016D,instru1511,instru1511D,oinstru,oinstruD,sum2sumOF,sum2sumOF_D,FDecode); |
input clk;
input [31:0] data1R;
input [31:0] data2R;
input [4:0] instru2016;
input [4:0] instru1511;
input [31:0] oinstru;
input [31:0] sum2sumOF;
output reg [31:0] data1D;
output reg [31:0] data2D;
output reg [4:0] instru2016D;
output reg [4:0] instru1511D;
output reg [31:0] oinstruD;
output reg [31:0] sum2sumOF_D;
output wire FDecode;
assign FDecode = clk ? 1'b1 : 1'b0;
always @(posedge clk)
begin
data1D = data1R;
data2D = data2R;
instru2016D = instru2016;
instru1511D = instru1511;
oinstruD = oinstru;
sum2sumOF_D = sum2sumOF;
end
endmodule | 0 |
4,155 | data/full_repos/permissive/108561032/Execute.v | 108,561,032 | Execute.v | v | 56 | 113 | [] | [] | [] | [(23, 55)] | null | data/verilator_xmls/5d9872b2-ba8e-4dbf-bd63-981912ab1660.xml | null | 2,348 | module | module Execute(reset,clk,out,outE,oZero,oZeroD,data2D,data2D_E,RegEscr1,RegEscr1E,salSum2out,salSum2E,FExecute);
input clk;
input [31:0] out;
input oZero;
input [31:0] data2D;
input [31:0] RegEscr1;
input [31:0] salSum2out;
input reset;
output reg [31:0] outE;
output reg oZeroD;
output reg [31:0] data2D_E;
output reg [31:0] RegEscr1E;
output reg [31:0] salSum2E;
output wire FExecute;
assign FExecute = clk ? 1'b1:1'b0;
always @(posedge clk)
begin
if (reset==1)
oZeroD = 1'b0;
outE = out;
oZeroD = oZero;
data2D_E = data2D;
RegEscr1E = RegEscr1;
salSum2E = salSum2out;
end
endmodule | module Execute(reset,clk,out,outE,oZero,oZeroD,data2D,data2D_E,RegEscr1,RegEscr1E,salSum2out,salSum2E,FExecute); |
input clk;
input [31:0] out;
input oZero;
input [31:0] data2D;
input [31:0] RegEscr1;
input [31:0] salSum2out;
input reset;
output reg [31:0] outE;
output reg oZeroD;
output reg [31:0] data2D_E;
output reg [31:0] RegEscr1E;
output reg [31:0] salSum2E;
output wire FExecute;
assign FExecute = clk ? 1'b1:1'b0;
always @(posedge clk)
begin
if (reset==1)
oZeroD = 1'b0;
outE = out;
oZeroD = oZero;
data2D_E = data2D;
RegEscr1E = RegEscr1;
salSum2E = salSum2out;
end
endmodule | 0 |
4,156 | data/full_repos/permissive/108561032/Fetch.v | 108,561,032 | Fetch.v | v | 45 | 83 | [] | [] | [] | [(23, 44)] | null | data/verilator_xmls/78f86279-ff70-4b88-bc70-3a911971df47.xml | null | 2,351 | module | module Fetch(clk,instru,instruD,sum2sumIF,sum2sumOF,FFetch);
input clk;
input [31:0] instru;
input [31:0] sum2sumIF;
output reg [31:0] instruD;
output reg [31:0] sum2sumOF;
output wire FFetch;
assign FFetch = clk? 1'b1:1'b0;
always @(posedge clk)
begin
instruD = instru;
sum2sumOF = sum2sumIF;
end
endmodule | module Fetch(clk,instru,instruD,sum2sumIF,sum2sumOF,FFetch); |
input clk;
input [31:0] instru;
input [31:0] sum2sumIF;
output reg [31:0] instruD;
output reg [31:0] sum2sumOF;
output wire FFetch;
assign FFetch = clk? 1'b1:1'b0;
always @(posedge clk)
begin
instruD = instru;
sum2sumOF = sum2sumIF;
end
endmodule | 0 |
4,157 | data/full_repos/permissive/108561032/memoriaintrucciones.v | 108,561,032 | memoriaintrucciones.v | v | 123 | 118 | [] | [] | [] | [(23, 122)] | null | data/verilator_xmls/2b76c1ce-e075-47f3-b952-661027d1f7da.xml | null | 2,352 | module | module memoriaintrucciones(direinstru,instru,clk,reset);
input [31:0] direinstru;
input clk;
input reset;
output wire [31:0] instru;
reg [31:0] registro_rom [31:0];
assign instru = registro_rom[direinstru];
always @ (*)
begin
if (reset == 1)
begin
registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[2] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
registro_rom[3] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[4] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[5] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[6] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[7] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[8] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[9] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
end
else
begin
end
end
endmodule | module memoriaintrucciones(direinstru,instru,clk,reset); |
input [31:0] direinstru;
input clk;
input reset;
output wire [31:0] instru;
reg [31:0] registro_rom [31:0];
assign instru = registro_rom[direinstru];
always @ (*)
begin
if (reset == 1)
begin
registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[2] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
registro_rom[3] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[4] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[5] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[6] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[7] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[8] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[9] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
end
else
begin
end
end
endmodule | 0 |
4,158 | data/full_repos/permissive/108561032/Memory.v | 108,561,032 | Memory.v | v | 47 | 83 | [] | [] | [] | [(23, 46)] | null | data/verilator_xmls/73011a10-05a3-4537-bcc3-fae2d667fad9.xml | null | 2,356 | module | module Memory(clk,outE,outE_M,Dataout,DataoutM,RegEscr1E,RegEscr1E_M,FMemory);
input clk;
input [31:0] outE;
input [31:0] Dataout;
input [4:0] RegEscr1E;
output reg [31:0] outE_M;
output reg [31:0] DataoutM;
output reg [4:0] RegEscr1E_M;
output wire FMemory;
assign FMemory = clk ? 1'b1:1'b0;
always @ (posedge clk)
begin
outE_M = outE;
DataoutM = Dataout;
RegEscr1E_M = RegEscr1E;
end
endmodule | module Memory(clk,outE,outE_M,Dataout,DataoutM,RegEscr1E,RegEscr1E_M,FMemory); |
input clk;
input [31:0] outE;
input [31:0] Dataout;
input [4:0] RegEscr1E;
output reg [31:0] outE_M;
output reg [31:0] DataoutM;
output reg [4:0] RegEscr1E_M;
output wire FMemory;
assign FMemory = clk ? 1'b1:1'b0;
always @ (posedge clk)
begin
outE_M = outE;
DataoutM = Dataout;
RegEscr1E_M = RegEscr1E;
end
endmodule | 0 |
4,159 | data/full_repos/permissive/108561032/pc.v | 108,561,032 | pc.v | v | 126 | 91 | [] | [] | [] | [(23, 125)] | null | data/verilator_xmls/d5e4cbe2-7199-4b84-b0c5-cc25c707994e.xml | null | 2,357 | module | module pc(
input SaltoCond,
input Saltoincond,
input [31:0] extSigno,
input oZero,
input clk,
input reset,
input [31:0]instru,
input [31:0] sum2sumin,
output [31:0] sum2sumout,
output reg [31:0] direinstru,
output [31:0] salSum2out,
input [31:0] salSum2in
);
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] sal2PC;
wire [31:0] mux2mux;
wire oZeroD;
assign salSum2out = extSigno + sum2sumin;
assign sum2sumout = direinstru +1;
assign sal2PC = mux2mux;
assign FuentePC = SaltoCond & oZeroD;
assign mux2mux = FuentePC ? salSum2in : sum2sumout;
/
always @(negedge reset )
begin
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
end
assign oZeroD = oZero ? 1'b1 : 1'b0;
always @(posedge clk)
begin
if (reset==1)
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
else
direinstru = sal2PC;
end
endmodule | module pc(
input SaltoCond,
input Saltoincond,
input [31:0] extSigno,
input oZero,
input clk,
input reset,
input [31:0]instru,
input [31:0] sum2sumin,
output [31:0] sum2sumout,
output reg [31:0] direinstru,
output [31:0] salSum2out,
input [31:0] salSum2in
); |
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] sal2PC;
wire [31:0] mux2mux;
wire oZeroD;
assign salSum2out = extSigno + sum2sumin;
assign sum2sumout = direinstru +1;
assign sal2PC = mux2mux;
assign FuentePC = SaltoCond & oZeroD;
assign mux2mux = FuentePC ? salSum2in : sum2sumout;
/
always @(negedge reset )
begin
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
end
assign oZeroD = oZero ? 1'b1 : 1'b0;
always @(posedge clk)
begin
if (reset==1)
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
else
direinstru = sal2PC;
end
endmodule | 0 |
4,160 | data/full_repos/permissive/108561032/procesador_segmentado.v | 108,561,032 | procesador_segmentado.v | v | 260 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:107: Cannot find file containing module: 'memoriaintrucciones'\n memoriaintrucciones memoriainstru(.direinstru(direinstrux),\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones.v\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones.sv\n memoriaintrucciones\n memoriaintrucciones.v\n memoriaintrucciones.sv\n obj_dir/memoriaintrucciones\n obj_dir/memoriaintrucciones.v\n obj_dir/memoriaintrucciones.sv\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:113: Cannot find file containing module: 'control'\n control control(.instru(instruD[31:26]),\n ^~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:122: Cannot find file containing module: 'bankregister'\n bankregister registros(.RegLe1(instruD[25:21]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:133: Cannot find file containing module: 'extension_signo'\n extension_signo extension(.instr(instru[15:0]),\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:138: Cannot find file containing module: 'alu32'\n alu32 alu(.data1(data1D),\n ^~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:147: Cannot find file containing module: 'memoria_datos'\n memoria_datos datos(.clk(clk),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:154: Cannot find file containing module: 'pc'\n pc pro_counter(\n ^~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:169: Cannot find file containing module: 'controlALU'\n controlALU contrALU(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:180: Cannot find file containing module: 'control1'\ncontrol1 control1(.Control(Control),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:189: Cannot find file containing module: 'control2'\ncontrol2 control2(.Control(Controls1),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:197: Cannot find file containing module: 'control3'\ncontrol3 control3(.Control(Controls2),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:206: Cannot find file containing module: 'Fetch'\nFetch Fetch(.clk(clk),\n^~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:214: Cannot find file containing module: 'Decode'\nDecode Decode(.clk(clk),\n^~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:230: Cannot find file containing module: 'Execute'\n Execute Execute(.clk(clk),\n ^~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:244: Cannot find file containing module: 'Memory'\nMemory Memory(.clk(clk),\n^~~~~~\n%Error: Exiting due to 15 error(s)\n" | 2,359 | module | module procesador_segmentado(
clk,reset
);
input wire clk;
reg [31:0] direinstru;
wire [31:0] instru;
wire RegDest;
wire SaltoCond;
wire Saltoincond;
wire LeerMem;
wire MemaReg;
wire [1:0]ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
wire [31:0] data1;
wire [31:0] data2;
wire [31:0] datain;
wire [31:0] oinstru;
wire [2:0] ctrl;
wire oCarry;
wire oZero;
wire [31:0] out;
wire [31:0] Dataout;
wire [4:0] RegEscr1;
wire [31:0] data21;
wire [31:0] dataEscr;
wire [31:0] ext2;
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] toPC;
wire [31:0]direinstrux;
input wire reset;
parameter varCuatro=3'b100;
wire [9:0] Control;
wire [9:0] Controls1;
wire [9:0] Controls2;
wire FFetch;
wire FDecode;
wire FExecute;
wire FMemory;
wire [31:0] instruD;
wire [31:0] sum2sumOF;
wire [31:0] sum2sumIF;
wire [31:0] data1D;
wire [31:0] data2D;
wire [4:0] instru2016D;
wire [4:0] instru1511D;
wire [31:0] oinstruD;
wire [31:0] sum2sumOF_D;
wire [31:0] outE;
wire oZeroD;
wire [31:0] data2D_E;
wire [31:0] RegEscr1E;
wire [31:0] salSum2out;
wire [31:0] salSum2E;
wire [31:0] outE_M;
wire [31:0] DataoutM;
wire [4:0] RegEscr1E_M;
memoriaintrucciones memoriainstru(.direinstru(direinstrux),
.instru(instru),
.clk(clk),
.reset(reset)
);
control control(.instru(instruD[31:26]),
.clk(clk),
.Control(Control),
.FFetch(FFetch),
.FDecode(FDecode),
.FExecute(FExecute),
.FMemory(FMemory)
);
bankregister registros(.RegLe1(instruD[25:21]),
.RegLe2(instruD[20:16]),
.RegEscr(RegEscr1),
.EscrReg(EscrReg),
.clk(clk),
.datain(dataEscr),
.data1(data1),
.data2(data2),
.reset(reset)
);
extension_signo extension(.instr(instru[15:0]),
.oinstr(oinstru),
.clk(clk)
);
alu32 alu(.data1(data1D),
.data2(data21),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
memoria_datos datos(.clk(clk),
.EscrMem(EscrMem),
.Direc(outE),
.Datain(data2D_E),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
pc pro_counter(
.SaltoCond(SaltoCond),
.Saltoincond(Saltoincond),
.extSigno(oinstruD),
.oZero(oZeroD),
.direinstru(direinstrux),
.clk(clk),
.reset(reset),
.instru(instru),
.sum2sumin(sum2sumOF_D),
.sum2sumout(sum2sumIF),
.salSum2out(salSum2out),
.salSum2in(salSum2E)
);
controlALU contrALU(
.ALUop(ALUOp),
.instru(instruD[5:0]),
.clk(clk),
.contALU(ctrl)
);
control1 control1(.Control(Control),
.clk(clk),
.RegDest(RegDest),
.ALUOp(ALUOp),
.FuenteALU(FuenteALU),
.Controls1(Controls1),
.Saltoincond(Saltoincond)
);
control2 control2(.Control(Controls1),
.clk(clk),
.SaltoCond(SaltoCond),
.EscrMem(EscrMem),
.Controls2(Controls2),
.LeerMem(LeerMem),
.reset(reset)
);
control3 control3(.Control(Controls2),
.clk(clk),
.MemaReg(MemaReg),
.EscrReg(EscrReg),
.reset(reset)
);
Fetch Fetch(.clk(clk),
.instru(instru),
.instruD(instruD),
.sum2sumIF(sum2sumIF),
.sum2sumOF(sum2sumOF),
.FFetch(FFetch)
);
Decode Decode(.clk(clk),
.data1R(data1),
.data2R(data2),
.data1D(data1D),
.data2D(data2D),
.instru2016(instru[20:16]),
.instru1511(instru[15:11]),
.instru2016D(instru2016D),
.instru1511D(instru1511D),
.oinstru(oinstru),
.oinstruD(oinstruD),
.sum2sumOF(sum2sumOF),
.sum2sumOF_D(sum2sumOF_D),
.FDecode(FDecode)
);
Execute Execute(.clk(clk),
.out(out),
.outE(outE),
.oZero(oZero),
.oZeroD(oZeroD),
.data2D(data2D),
.data2D_E(data2D_E),
.RegEscr1(RegEscr1),
.RegEscr1E(RegEscr1E),
.salSum2out(salSum2out),
.salSum2E(salSum2E),
.FExecute(FExecute),
.reset(reset)
);
Memory Memory(.clk(clk),
.outE(outE),
.outE_M(outE_M),
.Dataout(Dataout),
.DataoutM(DataoutM),
.RegEscr1E(RegEscr1E),
.RegEscr1E_M(RegEscr1E_M),
.FMemory(FMemory)
);
assign RegEscr1 = RegDest ? instru1511D: instru2016D;
assign data21 = FuenteALU ? oinstruD : data2D;
assign dataEscr = MemaReg ? DataoutM : outE_M;
endmodule | module procesador_segmentado(
clk,reset
); |
input wire clk;
reg [31:0] direinstru;
wire [31:0] instru;
wire RegDest;
wire SaltoCond;
wire Saltoincond;
wire LeerMem;
wire MemaReg;
wire [1:0]ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
wire [31:0] data1;
wire [31:0] data2;
wire [31:0] datain;
wire [31:0] oinstru;
wire [2:0] ctrl;
wire oCarry;
wire oZero;
wire [31:0] out;
wire [31:0] Dataout;
wire [4:0] RegEscr1;
wire [31:0] data21;
wire [31:0] dataEscr;
wire [31:0] ext2;
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] toPC;
wire [31:0]direinstrux;
input wire reset;
parameter varCuatro=3'b100;
wire [9:0] Control;
wire [9:0] Controls1;
wire [9:0] Controls2;
wire FFetch;
wire FDecode;
wire FExecute;
wire FMemory;
wire [31:0] instruD;
wire [31:0] sum2sumOF;
wire [31:0] sum2sumIF;
wire [31:0] data1D;
wire [31:0] data2D;
wire [4:0] instru2016D;
wire [4:0] instru1511D;
wire [31:0] oinstruD;
wire [31:0] sum2sumOF_D;
wire [31:0] outE;
wire oZeroD;
wire [31:0] data2D_E;
wire [31:0] RegEscr1E;
wire [31:0] salSum2out;
wire [31:0] salSum2E;
wire [31:0] outE_M;
wire [31:0] DataoutM;
wire [4:0] RegEscr1E_M;
memoriaintrucciones memoriainstru(.direinstru(direinstrux),
.instru(instru),
.clk(clk),
.reset(reset)
);
control control(.instru(instruD[31:26]),
.clk(clk),
.Control(Control),
.FFetch(FFetch),
.FDecode(FDecode),
.FExecute(FExecute),
.FMemory(FMemory)
);
bankregister registros(.RegLe1(instruD[25:21]),
.RegLe2(instruD[20:16]),
.RegEscr(RegEscr1),
.EscrReg(EscrReg),
.clk(clk),
.datain(dataEscr),
.data1(data1),
.data2(data2),
.reset(reset)
);
extension_signo extension(.instr(instru[15:0]),
.oinstr(oinstru),
.clk(clk)
);
alu32 alu(.data1(data1D),
.data2(data21),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
memoria_datos datos(.clk(clk),
.EscrMem(EscrMem),
.Direc(outE),
.Datain(data2D_E),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
pc pro_counter(
.SaltoCond(SaltoCond),
.Saltoincond(Saltoincond),
.extSigno(oinstruD),
.oZero(oZeroD),
.direinstru(direinstrux),
.clk(clk),
.reset(reset),
.instru(instru),
.sum2sumin(sum2sumOF_D),
.sum2sumout(sum2sumIF),
.salSum2out(salSum2out),
.salSum2in(salSum2E)
);
controlALU contrALU(
.ALUop(ALUOp),
.instru(instruD[5:0]),
.clk(clk),
.contALU(ctrl)
);
control1 control1(.Control(Control),
.clk(clk),
.RegDest(RegDest),
.ALUOp(ALUOp),
.FuenteALU(FuenteALU),
.Controls1(Controls1),
.Saltoincond(Saltoincond)
);
control2 control2(.Control(Controls1),
.clk(clk),
.SaltoCond(SaltoCond),
.EscrMem(EscrMem),
.Controls2(Controls2),
.LeerMem(LeerMem),
.reset(reset)
);
control3 control3(.Control(Controls2),
.clk(clk),
.MemaReg(MemaReg),
.EscrReg(EscrReg),
.reset(reset)
);
Fetch Fetch(.clk(clk),
.instru(instru),
.instruD(instruD),
.sum2sumIF(sum2sumIF),
.sum2sumOF(sum2sumOF),
.FFetch(FFetch)
);
Decode Decode(.clk(clk),
.data1R(data1),
.data2R(data2),
.data1D(data1D),
.data2D(data2D),
.instru2016(instru[20:16]),
.instru1511(instru[15:11]),
.instru2016D(instru2016D),
.instru1511D(instru1511D),
.oinstru(oinstru),
.oinstruD(oinstruD),
.sum2sumOF(sum2sumOF),
.sum2sumOF_D(sum2sumOF_D),
.FDecode(FDecode)
);
Execute Execute(.clk(clk),
.out(out),
.outE(outE),
.oZero(oZero),
.oZeroD(oZeroD),
.data2D(data2D),
.data2D_E(data2D_E),
.RegEscr1(RegEscr1),
.RegEscr1E(RegEscr1E),
.salSum2out(salSum2out),
.salSum2E(salSum2E),
.FExecute(FExecute),
.reset(reset)
);
Memory Memory(.clk(clk),
.outE(outE),
.outE_M(outE_M),
.Dataout(Dataout),
.DataoutM(DataoutM),
.RegEscr1E(RegEscr1E),
.RegEscr1E_M(RegEscr1E_M),
.FMemory(FMemory)
);
assign RegEscr1 = RegDest ? instru1511D: instru2016D;
assign data21 = FuenteALU ? oinstruD : data2D;
assign dataEscr = MemaReg ? DataoutM : outE_M;
endmodule | 0 |
4,161 | data/full_repos/permissive/108561032/procesador_segmentado_tb.v | 108,561,032 | procesador_segmentado_tb.v | v | 49 | 83 | [] | [] | [] | [(23, 48)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:27: Cannot find file containing module: \'procesador_segmentado\'\n procesador_segmentado uut(\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado.v\n data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado.sv\n procesador_segmentado\n procesador_segmentado.v\n procesador_segmentado.sv\n obj_dir/procesador_segmentado\n obj_dir/procesador_segmentado.v\n obj_dir/procesador_segmentado.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,360 | module | module procesador_segmentado_tb();
reg clk;
reg reset;
procesador_segmentado uut(
.clk(clk),
.reset(reset)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
reset=1'b1;
#50;
reset=1'b0;
#50;
end
endmodule | module procesador_segmentado_tb(); |
reg clk;
reg reset;
procesador_segmentado uut(
.clk(clk),
.reset(reset)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
reset=1'b1;
#50;
reset=1'b0;
#50;
end
endmodule | 0 |
4,162 | data/full_repos/permissive/108698528/clock_divider.v | 108,698,528 | clock_divider.v | v | 32 | 60 | [] | [] | [] | [(3, 31)] | null | data/verilator_xmls/454edddd-b4e6-4385-90bb-8ab9f2df1e57.xml | null | 2,363 | module | module clock_divider(clk, out);
parameter BITS = 8;
parameter DIV = 16;
input clk;
output reg out;
reg [BITS-1:0] count;
reg clr;
initial begin
out = 0;
count = 0;
end
always @(posedge clk) begin
if(count == (DIV - 1)) begin
count <= 0;
out <= ~out;
end else begin
count <= count + 1;
end
end
endmodule | module clock_divider(clk, out); |
parameter BITS = 8;
parameter DIV = 16;
input clk;
output reg out;
reg [BITS-1:0] count;
reg clr;
initial begin
out = 0;
count = 0;
end
always @(posedge clk) begin
if(count == (DIV - 1)) begin
count <= 0;
out <= ~out;
end else begin
count <= count + 1;
end
end
endmodule | 20 |
4,167 | data/full_repos/permissive/108698528/mux2x.v | 108,698,528 | mux2x.v | v | 17 | 57 | [] | [] | [] | [(5, 17)] | null | data/verilator_xmls/c7ac31cc-b238-405e-b63a-404f7d5f8c54.xml | null | 2,368 | module | module mux2x(in_a, in_b, select, out);
parameter WIDTH = 8;
input [WIDTH - 1:0] in_a, in_b;
output reg [WIDTH - 1:0] out;
input select;
always @* begin
if(select == 1) out = in_b;
else out = in_a;
end
endmodule | module mux2x(in_a, in_b, select, out); |
parameter WIDTH = 8;
input [WIDTH - 1:0] in_a, in_b;
output reg [WIDTH - 1:0] out;
input select;
always @* begin
if(select == 1) out = in_b;
else out = in_a;
end
endmodule | 20 |
4,168 | data/full_repos/permissive/108698528/ram.v | 108,698,528 | ram.v | v | 47 | 68 | [] | [] | [] | null | line:47: before: "/" | data/verilator_xmls/1bc899f4-8fd1-4c1a-8d09-2f8b7b6fa9c7.xml | null | 2,369 | module | module simple_ram(mem_bus_in, mem_bus_out, address, r_e, w_e, clk);
parameter BYTE_W = 8;
parameter ADDR_W = 8;
parameter NUM_ADDR = 1 << ADDR_W;
input [BYTE_W - 1:0] mem_bus_in;
output reg [BYTE_W - 1:0] mem_bus_out;
input [ADDR_W - 1:0] address;
input r_e, w_e;
input clk;
tri [BYTE_W - 1: 0] mem_bus;
reg [BYTE_W - 1:0] mem_storage [0:NUM_ADDR - 1];
always @(posedge clk) begin
if(w_e) mem_storage[address] <= mem_bus_in;
else if(r_e) mem_bus_out <= mem_storage[address];
else mem_bus_out <= 0;
end
endmodule | module simple_ram(mem_bus_in, mem_bus_out, address, r_e, w_e, clk); |
parameter BYTE_W = 8;
parameter ADDR_W = 8;
parameter NUM_ADDR = 1 << ADDR_W;
input [BYTE_W - 1:0] mem_bus_in;
output reg [BYTE_W - 1:0] mem_bus_out;
input [ADDR_W - 1:0] address;
input r_e, w_e;
input clk;
tri [BYTE_W - 1: 0] mem_bus;
reg [BYTE_W - 1:0] mem_storage [0:NUM_ADDR - 1];
always @(posedge clk) begin
if(w_e) mem_storage[address] <= mem_bus_in;
else if(r_e) mem_bus_out <= mem_storage[address];
else mem_bus_out <= 0;
end
endmodule | 20 |
4,171 | data/full_repos/permissive/108698528/ts_buf.v | 108,698,528 | ts_buf.v | v | 12 | 47 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/2392aa75-3c15-460f-b9d0-0b549f89e11b.xml | null | 2,373 | module | module ts_buf(in, out, en);
parameter WIDTH = 1;
input [WIDTH-1:0] in;
input en;
output [WIDTH-1:0] out;
tri [WIDTH-1:0] out;
assign out = (en) ? in:{(WIDTH){1'bz}};
endmodule | module ts_buf(in, out, en); |
parameter WIDTH = 1;
input [WIDTH-1:0] in;
input en;
output [WIDTH-1:0] out;
tri [WIDTH-1:0] out;
assign out = (en) ? in:{(WIDTH){1'bz}};
endmodule | 20 |
4,173 | data/full_repos/permissive/108698528/uart_out.v | 108,698,528 | uart_out.v | v | 134 | 91 | [] | [] | [] | [(7, 106)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/108698528/uart_out.v:21: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n : ... In instance uart_out\n assign final_packet = {1\'b1, packet_l, 1\'b0};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108698528/uart_out.v:23: Cannot find file containing module: \'sr_latch\'\n sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch\n data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch.v\n data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch.sv\n sr_latch\n sr_latch.v\n sr_latch.sv\n obj_dir/sr_latch\n obj_dir/sr_latch.v\n obj_dir/sr_latch.sv\n%Error: data/full_repos/permissive/108698528/uart_out.v:31: Cannot find file containing module: \'up_counter\'\n up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108698528/uart_out.v:32: Cannot find file containing module: \'up_counter\'\n up_counter #(4, ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 2,375 | module | module uart_out(data_in, ready, rst, tx, tx_done, clk);
parameter BIT_SIZE = 10415;
parameter WORDSIZE = 8;
input ready, clk, rst;
input [WORDSIZE - 1:0] data_in;
output reg tx, tx_done;
wire [7:0] packet, packet_l;
wire [10:0] final_packet;
assign packet = data_in;
assign final_packet = {1'b1, packet_l, 1'b0};
reg latch_set, latch_reset;
sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);
wire [31:0] cycles;
wire [3:0] packet_pos;
reg baud_ctl_en, baud_ctl_clr, packet_cnt_en, packet_cnt_clr;
up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);
up_counter #(4, ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);
reg [2:0] state;
parameter init = 0, wait_for_ready = 1, translate_input = 2, push = 3,
clock_wait = 4, done = 5;
initial begin
state = init;
end
reg byte_done, bit_done;
always @* begin
if(packet_pos >= 10) byte_done = 1;
else byte_done = 0;
if(cycles >= BIT_SIZE) bit_done = 1;
else bit_done = 0;
end
always @(posedge clk) begin
if(rst) state <= init;
else begin
case(state)
init: state <= wait_for_ready;
wait_for_ready: begin
if(ready) state <= translate_input;
else state <= wait_for_ready;
end
translate_input: state <= clock_wait;
push: state <= clock_wait;
clock_wait: begin
if(bit_done) begin
if(byte_done) state <= done;
else state <= push;
end
else state <= clock_wait;
end
done: state <= wait_for_ready;
endcase
end
end
always @* begin
if(state == init) latch_reset = 1;
else latch_reset = 0;
if(state == translate_input) latch_set = 1;
else latch_set = 0;
if(state == push) packet_cnt_en = 1;
else packet_cnt_en = 0;
if((state == done) || (state == init)) packet_cnt_clr = 1;
else packet_cnt_clr = 0;
if(state == clock_wait) baud_ctl_en = 1;
else baud_ctl_en = 0;
if(state == clock_wait) baud_ctl_clr = 0;
else baud_ctl_clr = 1;
if(state == done) tx_done = 1;
else tx_done = 0;
if(packet_pos >= 10) tx = 1;
else if((state == push) || (state == clock_wait))
tx = final_packet[packet_pos];
else tx = 1;
end
endmodule | module uart_out(data_in, ready, rst, tx, tx_done, clk); |
parameter BIT_SIZE = 10415;
parameter WORDSIZE = 8;
input ready, clk, rst;
input [WORDSIZE - 1:0] data_in;
output reg tx, tx_done;
wire [7:0] packet, packet_l;
wire [10:0] final_packet;
assign packet = data_in;
assign final_packet = {1'b1, packet_l, 1'b0};
reg latch_set, latch_reset;
sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);
wire [31:0] cycles;
wire [3:0] packet_pos;
reg baud_ctl_en, baud_ctl_clr, packet_cnt_en, packet_cnt_clr;
up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);
up_counter #(4, ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);
reg [2:0] state;
parameter init = 0, wait_for_ready = 1, translate_input = 2, push = 3,
clock_wait = 4, done = 5;
initial begin
state = init;
end
reg byte_done, bit_done;
always @* begin
if(packet_pos >= 10) byte_done = 1;
else byte_done = 0;
if(cycles >= BIT_SIZE) bit_done = 1;
else bit_done = 0;
end
always @(posedge clk) begin
if(rst) state <= init;
else begin
case(state)
init: state <= wait_for_ready;
wait_for_ready: begin
if(ready) state <= translate_input;
else state <= wait_for_ready;
end
translate_input: state <= clock_wait;
push: state <= clock_wait;
clock_wait: begin
if(bit_done) begin
if(byte_done) state <= done;
else state <= push;
end
else state <= clock_wait;
end
done: state <= wait_for_ready;
endcase
end
end
always @* begin
if(state == init) latch_reset = 1;
else latch_reset = 0;
if(state == translate_input) latch_set = 1;
else latch_set = 0;
if(state == push) packet_cnt_en = 1;
else packet_cnt_en = 0;
if((state == done) || (state == init)) packet_cnt_clr = 1;
else packet_cnt_clr = 0;
if(state == clock_wait) baud_ctl_en = 1;
else baud_ctl_en = 0;
if(state == clock_wait) baud_ctl_clr = 0;
else baud_ctl_clr = 1;
if(state == done) tx_done = 1;
else tx_done = 0;
if(packet_pos >= 10) tx = 1;
else if((state == push) || (state == clock_wait))
tx = final_packet[packet_pos];
else tx = 1;
end
endmodule | 20 |
4,175 | data/full_repos/permissive/108698528/up_counter.v | 108,698,528 | up_counter.v | v | 24 | 56 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 672: invalid start byte | data/verilator_xmls/83bf140a-5169-4ea4-bf15-d4999650445a.xml | null | 2,377 | module | module up_counter(en, clr, count, clk);
parameter WIDTH = 8;
parameter MAX = (1 << WIDTH) - 1;
input en, clr, clk;
(* KEEP = "TRUE"*)
output reg [WIDTH-1:0] count;
initial begin
count = 0;
end
always @(posedge clk) begin
if(clr) begin
count <= 0;
end
else if(en && (count < MAX)) begin
count <= count + 1;
end
end
endmodule | module up_counter(en, clr, count, clk); |
parameter WIDTH = 8;
parameter MAX = (1 << WIDTH) - 1;
input en, clr, clk;
(* KEEP = "TRUE"*)
output reg [WIDTH-1:0] count;
initial begin
count = 0;
end
always @(posedge clk) begin
if(clr) begin
count <= 0;
end
else if(en && (count < MAX)) begin
count <= count + 1;
end
end
endmodule | 20 |
4,180 | data/full_repos/permissive/108891607/src/design/rd_valid_gen.v | 108,891,607 | rd_valid_gen.v | v | 46 | 73 | [] | [] | [] | [(1, 45)] | null | data/verilator_xmls/6ffff1ac-2460-42f5-b2e7-ac40da1b5a63.xml | null | 2,381 | module | module rd_valid_gen( full, rd_clk, reset, rd_valid );
parameter FIFO_DEPTH = 8;
parameter COUNTER_WIDTH = 3;
input wire full;
input wire rd_clk;
input wire reset;
output wire rd_valid;
reg [COUNTER_WIDTH : 0] counter = 0;
reg full_counter = 0;
assign rd_valid = (counter < FIFO_DEPTH + 1) & full_counter & !full;
always @(posedge full or posedge reset) begin
if(reset)
full_counter <= 0;
else
if(!full_counter)
full_counter <= 1;
end
always @(posedge full or posedge rd_clk or posedge reset) begin
if(reset)
counter <= 0;
else begin
if(full)
counter <= 0;
else
if(rd_valid)
counter <= counter + 1;
end
end
endmodule | module rd_valid_gen( full, rd_clk, reset, rd_valid ); |
parameter FIFO_DEPTH = 8;
parameter COUNTER_WIDTH = 3;
input wire full;
input wire rd_clk;
input wire reset;
output wire rd_valid;
reg [COUNTER_WIDTH : 0] counter = 0;
reg full_counter = 0;
assign rd_valid = (counter < FIFO_DEPTH + 1) & full_counter & !full;
always @(posedge full or posedge reset) begin
if(reset)
full_counter <= 0;
else
if(!full_counter)
full_counter <= 1;
end
always @(posedge full or posedge rd_clk or posedge reset) begin
if(reset)
counter <= 0;
else begin
if(full)
counter <= 0;
else
if(rd_valid)
counter <= counter + 1;
end
end
endmodule | 5 |
4,182 | data/full_repos/permissive/108891607/src/design/wr_memory.v | 108,891,607 | wr_memory.v | v | 50 | 60 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/ec4abe20-8f7b-41a1-b3ec-82bfef60400d.xml | null | 2,383 | module | module wr_memory ( wr_data, wr_clk, wr_en, wr_addr,
remapping_memory,
full,
reset );
parameter WR_DATA_WIDTH = 1;
parameter WR_ADDR_WIDTH = 3;
parameter MEM_DEPTH = 8;
input wire [WR_DATA_WIDTH - 1 : 0] wr_data;
input wire [WR_ADDR_WIDTH - 1 : 0] wr_addr;
input wire wr_clk, wr_en;
input wire full;
output reg [MEM_DEPTH - 1 : 0] remapping_memory;
input wire reset;
reg [WR_DATA_WIDTH - 1 : 0] memory [MEM_DEPTH - 1 : 0];
integer i;
always @(posedge wr_clk or posedge reset) begin
if(reset)
for(i = 0; i < MEM_DEPTH; i = i + 1)
memory[i] <= 0;
else
if(wr_en)
memory[wr_addr] <= wr_data;
end
always @(posedge full or posedge reset) begin
if(reset)
remapping_memory <= 0;
else
for(i = 0; i < MEM_DEPTH; i = i + 1)
remapping_memory[i] <= memory[i];
end
endmodule | module wr_memory ( wr_data, wr_clk, wr_en, wr_addr,
remapping_memory,
full,
reset ); |
parameter WR_DATA_WIDTH = 1;
parameter WR_ADDR_WIDTH = 3;
parameter MEM_DEPTH = 8;
input wire [WR_DATA_WIDTH - 1 : 0] wr_data;
input wire [WR_ADDR_WIDTH - 1 : 0] wr_addr;
input wire wr_clk, wr_en;
input wire full;
output reg [MEM_DEPTH - 1 : 0] remapping_memory;
input wire reset;
reg [WR_DATA_WIDTH - 1 : 0] memory [MEM_DEPTH - 1 : 0];
integer i;
always @(posedge wr_clk or posedge reset) begin
if(reset)
for(i = 0; i < MEM_DEPTH; i = i + 1)
memory[i] <= 0;
else
if(wr_en)
memory[wr_addr] <= wr_data;
end
always @(posedge full or posedge reset) begin
if(reset)
remapping_memory <= 0;
else
for(i = 0; i < MEM_DEPTH; i = i + 1)
remapping_memory[i] <= memory[i];
end
endmodule | 5 |
4,185 | data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v | 108,891,607 | rd_valid_gen_testbench.v | v | 45 | 38 | [] | [] | [] | [(1, 45)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 rd_clk = !rd_clk & !full;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #30 full = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 full = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #110 full = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 full = 0;\n ^\n%Error: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:19: Cannot find file containing module: \'rd_valid_gen\'\n rd_valid_gen #(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen\n data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen.v\n data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen.sv\n rd_valid_gen\n rd_valid_gen.v\n rd_valid_gen.sv\n obj_dir/rd_valid_gen\n obj_dir/rd_valid_gen.v\n obj_dir/rd_valid_gen.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,386 | module | module rd_valid_gen_testbench ( );
parameter FIFO_DEPTH = 8;
parameter COUNTER_WIDTH = 3;
reg full = 0;
reg rd_clk = 0;
reg reset = 0;
wire rd_valid;
rd_valid_gen #(
.FIFO_DEPTH(FIFO_DEPTH),
.COUNTER_WIDTH(COUNTER_WIDTH)
) rd_valid_gen_inst (
.full(full),
.rd_clk(rd_clk),
.reset(reset),
.rd_valid(rd_valid)
);
always
#5 rd_clk = !rd_clk & !full;
initial begin
#2 reset = 1;
#2 reset = 0;
#30 full = 1;
#10 full = 0;
#110 full = 1;
#10 full = 0;
end
endmodule | module rd_valid_gen_testbench ( ); |
parameter FIFO_DEPTH = 8;
parameter COUNTER_WIDTH = 3;
reg full = 0;
reg rd_clk = 0;
reg reset = 0;
wire rd_valid;
rd_valid_gen #(
.FIFO_DEPTH(FIFO_DEPTH),
.COUNTER_WIDTH(COUNTER_WIDTH)
) rd_valid_gen_inst (
.full(full),
.rd_clk(rd_clk),
.reset(reset),
.rd_valid(rd_valid)
);
always
#5 rd_clk = !rd_clk & !full;
initial begin
#2 reset = 1;
#2 reset = 0;
#30 full = 1;
#10 full = 0;
#110 full = 1;
#10 full = 0;
end
endmodule | 5 |
4,188 | data/full_repos/permissive/108908995/fcell.v | 108,908,995 | fcell.v | v | 21 | 31 | [] | [] | [] | [(1, 20)] | null | null | 1: b"%Error: data/full_repos/permissive/108908995/fcell.v:12: Cannot find file containing module: 'f'\nf f (\n^\n ... Looked in:\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/f\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/f.v\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/f.sv\n f\n f.v\n f.sv\n obj_dir/f\n obj_dir/f.v\n obj_dir/f.sv\n%Error: Exiting due to 1 error(s)\n" | 2,390 | module | module fcell (
input [63:0]IN,
input [31:0]KEY,
output [63:0]OUT
);
wire [31:0]a = IN[63:32];
wire [31:0]b = IN[31:0];
wire [31:0]f_out;
f f (
.X(a),
.K(KEY),
.Y(f_out)
);
assign OUT = { b ^ f_out, a };
endmodule | module fcell (
input [63:0]IN,
input [31:0]KEY,
output [63:0]OUT
); |
wire [31:0]a = IN[63:32];
wire [31:0]b = IN[31:0];
wire [31:0]f_out;
f f (
.X(a),
.K(KEY),
.Y(f_out)
);
assign OUT = { b ^ f_out, a };
endmodule | 4 |
4,191 | data/full_repos/permissive/108908995/sbox.v | 108,908,995 | sbox.v | v | 13 | 42 | [] | [] | [] | [(1, 12)] | null | data/verilator_xmls/f1e4c318-d979-4ba0-8a5f-baf834aa4c5d.xml | null | 2,394 | module | module sbox #(parameter init_file = "") (
input [3:0]IN,
output [3:0]OUT
);
reg [3:0]box[15:0];
initial $readmemh(init_file, box);
assign OUT = box[IN];
endmodule | module sbox #(parameter init_file = "") (
input [3:0]IN,
output [3:0]OUT
); |
reg [3:0]box[15:0];
initial $readmemh(init_file, box);
assign OUT = box[IN];
endmodule | 4 |
4,192 | data/full_repos/permissive/108908995/sbox_array.v | 108,908,995 | sbox_array.v | v | 17 | 74 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Error: data/full_repos/permissive/108908995/sbox_array.v:7: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox7.txt")) sbox7 (.IN(IN[3:0] ), .OUT(OUT[3:0] ));\n^~~~\n ... Looked in:\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/sbox\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/sbox.v\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/sbox.sv\n sbox\n sbox.v\n sbox.sv\n obj_dir/sbox\n obj_dir/sbox.v\n obj_dir/sbox.sv\n%Error: data/full_repos/permissive/108908995/sbox_array.v:8: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox6.txt")) sbox6 (.IN(IN[7:4] ), .OUT(OUT[7:4] ));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:9: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox5.txt")) sbox5 (.IN(IN[11:8] ), .OUT(OUT[11:8] ));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:10: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox4.txt")) sbox4 (.IN(IN[15:12]), .OUT(OUT[15:12]));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:11: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox3.txt")) sbox3 (.IN(IN[19:16]), .OUT(OUT[19:16]));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:12: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox2.txt")) sbox2 (.IN(IN[23:20]), .OUT(OUT[23:20]));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:13: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox1.txt")) sbox1 (.IN(IN[27:24]), .OUT(OUT[27:24]));\n^~~~\n%Error: data/full_repos/permissive/108908995/sbox_array.v:14: Cannot find file containing module: \'sbox\'\nsbox #(.init_file("sbox0.txt")) sbox0 (.IN(IN[31:28]), .OUT(OUT[31:28]));\n^~~~\n%Error: Exiting due to 8 error(s)\n' | 2,395 | module | module sbox_array(
input [31:0]IN,
output [31:0]OUT
);
sbox #(.init_file("sbox7.txt")) sbox7 (.IN(IN[3:0] ), .OUT(OUT[3:0] ));
sbox #(.init_file("sbox6.txt")) sbox6 (.IN(IN[7:4] ), .OUT(OUT[7:4] ));
sbox #(.init_file("sbox5.txt")) sbox5 (.IN(IN[11:8] ), .OUT(OUT[11:8] ));
sbox #(.init_file("sbox4.txt")) sbox4 (.IN(IN[15:12]), .OUT(OUT[15:12]));
sbox #(.init_file("sbox3.txt")) sbox3 (.IN(IN[19:16]), .OUT(OUT[19:16]));
sbox #(.init_file("sbox2.txt")) sbox2 (.IN(IN[23:20]), .OUT(OUT[23:20]));
sbox #(.init_file("sbox1.txt")) sbox1 (.IN(IN[27:24]), .OUT(OUT[27:24]));
sbox #(.init_file("sbox0.txt")) sbox0 (.IN(IN[31:28]), .OUT(OUT[31:28]));
endmodule | module sbox_array(
input [31:0]IN,
output [31:0]OUT
); |
sbox #(.init_file("sbox7.txt")) sbox7 (.IN(IN[3:0] ), .OUT(OUT[3:0] ));
sbox #(.init_file("sbox6.txt")) sbox6 (.IN(IN[7:4] ), .OUT(OUT[7:4] ));
sbox #(.init_file("sbox5.txt")) sbox5 (.IN(IN[11:8] ), .OUT(OUT[11:8] ));
sbox #(.init_file("sbox4.txt")) sbox4 (.IN(IN[15:12]), .OUT(OUT[15:12]));
sbox #(.init_file("sbox3.txt")) sbox3 (.IN(IN[19:16]), .OUT(OUT[19:16]));
sbox #(.init_file("sbox2.txt")) sbox2 (.IN(IN[23:20]), .OUT(OUT[23:20]));
sbox #(.init_file("sbox1.txt")) sbox1 (.IN(IN[27:24]), .OUT(OUT[27:24]));
sbox #(.init_file("sbox0.txt")) sbox0 (.IN(IN[31:28]), .OUT(OUT[31:28]));
endmodule | 4 |
4,193 | data/full_repos/permissive/108908995/ssd.sv | 108,908,995 | ssd.sv | sv | 64 | 54 | [] | [] | [] | [(1, 63)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n : ... In instance ssd\n sen = 4'b1110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n : ... In instance ssd\n hb = WORD[3:0];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n : ... In instance ssd\n sen = 4'b1101;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n : ... In instance ssd\n hb = WORD[7:4];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n : ... In instance ssd\n sen = 4'b1011;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n : ... In instance ssd\n hb = WORD[11:8];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n : ... In instance ssd\n sen = 4'b0111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n : ... In instance ssd\n hb = WORD[15:12];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h0: ssc = 7'b1111110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h1: ssc = 7'b0110000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h2: ssc = 7'b1101101;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h3: ssc = 7'b1111001;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:48: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h4: ssc = 7'b0110011;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h5: ssc = 7'b1011011;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:50: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h6: ssc = 7'b1011111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h7: ssc = 7'b1110000;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h8: ssc = 7'b1111111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'h9: ssc = 7'b1111011;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'ha: ssc = 7'b1110111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:55: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'hb: ssc = 7'b0011111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'hc: ssc = 7'b1001110;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'hd: ssc = 7'b0111101;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:58: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'he: ssc = 7'b1101111;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:59: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n : ... In instance ssd\n 4'hf: ssc = 7'b1000111;\n ^~~\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 2,396 | module | module ssd
(
input CLK,
input [15:0]WORD,
input EN,
output SEN1, SEN2, SEN3, SEN4,
output SSA, SSB, SSC, SSD, SSE, SSF, SSG
);
reg [15:0]cnt = 16'b0;
always @(posedge CLK) begin
cnt <= cnt + 16'b1;
end
wire [3:0]sen;
assign {SEN1, SEN2, SEN3, SEN4} = EN ? sen : 4'b1111;
wire [3:0]hb;
always_comb begin
case (cnt[15:14])
2'b00: begin
sen = 4'b1110;
hb = WORD[3:0];
end
2'b01: begin
sen = 4'b1101;
hb = WORD[7:4];
end
2'b10: begin
sen = 4'b1011;
hb = WORD[11:8];
end
2'b11: begin
sen = 4'b0111;
hb = WORD[15:12];
end
endcase
end
wire [6:0]ssc;
assign {SSA, SSB, SSC, SSD, SSE, SSF, SSG} = ssc;
always_comb begin
case (hb)
4'h0: ssc = 7'b1111110;
4'h1: ssc = 7'b0110000;
4'h2: ssc = 7'b1101101;
4'h3: ssc = 7'b1111001;
4'h4: ssc = 7'b0110011;
4'h5: ssc = 7'b1011011;
4'h6: ssc = 7'b1011111;
4'h7: ssc = 7'b1110000;
4'h8: ssc = 7'b1111111;
4'h9: ssc = 7'b1111011;
4'ha: ssc = 7'b1110111;
4'hb: ssc = 7'b0011111;
4'hc: ssc = 7'b1001110;
4'hd: ssc = 7'b0111101;
4'he: ssc = 7'b1101111;
4'hf: ssc = 7'b1000111;
endcase
end
endmodule | module ssd
(
input CLK,
input [15:0]WORD,
input EN,
output SEN1, SEN2, SEN3, SEN4,
output SSA, SSB, SSC, SSD, SSE, SSF, SSG
); |
reg [15:0]cnt = 16'b0;
always @(posedge CLK) begin
cnt <= cnt + 16'b1;
end
wire [3:0]sen;
assign {SEN1, SEN2, SEN3, SEN4} = EN ? sen : 4'b1111;
wire [3:0]hb;
always_comb begin
case (cnt[15:14])
2'b00: begin
sen = 4'b1110;
hb = WORD[3:0];
end
2'b01: begin
sen = 4'b1101;
hb = WORD[7:4];
end
2'b10: begin
sen = 4'b1011;
hb = WORD[11:8];
end
2'b11: begin
sen = 4'b0111;
hb = WORD[15:12];
end
endcase
end
wire [6:0]ssc;
assign {SSA, SSB, SSC, SSD, SSE, SSF, SSG} = ssc;
always_comb begin
case (hb)
4'h0: ssc = 7'b1111110;
4'h1: ssc = 7'b0110000;
4'h2: ssc = 7'b1101101;
4'h3: ssc = 7'b1111001;
4'h4: ssc = 7'b0110011;
4'h5: ssc = 7'b1011011;
4'h6: ssc = 7'b1011111;
4'h7: ssc = 7'b1110000;
4'h8: ssc = 7'b1111111;
4'h9: ssc = 7'b1111011;
4'ha: ssc = 7'b1110111;
4'hb: ssc = 7'b0011111;
4'hc: ssc = 7'b1001110;
4'hd: ssc = 7'b0111101;
4'he: ssc = 7'b1101111;
4'hf: ssc = 7'b1000111;
endcase
end
endmodule | 4 |
4,194 | data/full_repos/permissive/108908995/test_cells.v | 108,908,995 | test_cells.v | v | 39 | 37 | [] | [] | [] | null | line:27: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108908995/test_cells.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("y = %h", y);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/108908995/test_cells.v:4: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1234567\' generates 64 bits.\n : ... In instance top\nwire [31:0]k = 64\'h01234567;\n ^\n%Error: data/full_repos/permissive/108908995/test_cells.v:7: Cannot find file containing module: \'fcell\'\nfcell fc (\n^~~~~\n ... Looked in:\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell.v\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell.sv\n fcell\n fcell.v\n fcell.sv\n obj_dir/fcell\n obj_dir/fcell.v\n obj_dir/fcell.sv\n%Error: data/full_repos/permissive/108908995/test_cells.v:20: Cannot find file containing module: \'ifcell\'\nifcell ifc (\n^~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,397 | module | module top;
wire [63:0]x = 64'hDEADBEEFBAADF00D;
wire [31:0]k = 64'h01234567;
wire [63:0]y;
fcell fc (
.IN(x),
.KEY(k),
.OUT(y)
);
initial begin
$display("x = %h", x);
$display("k = %h", k);
end
wire [63:0]x_dec;
ifcell ifc (
.IN(y),
.KEY(k),
.OUT(x_dec)
);
initial begin
#1 $display("y = %h", y);
$display("x' = %h", x_dec);
if (x == x_dec)
$display("[PASSED]");
else
$display("[FAILED]");
$finish;
end
endmodule | module top; |
wire [63:0]x = 64'hDEADBEEFBAADF00D;
wire [31:0]k = 64'h01234567;
wire [63:0]y;
fcell fc (
.IN(x),
.KEY(k),
.OUT(y)
);
initial begin
$display("x = %h", x);
$display("k = %h", k);
end
wire [63:0]x_dec;
ifcell ifc (
.IN(y),
.KEY(k),
.OUT(x_dec)
);
initial begin
#1 $display("y = %h", y);
$display("x' = %h", x_dec);
if (x == x_dec)
$display("[PASSED]");
else
$display("[FAILED]");
$finish;
end
endmodule | 4 |
4,195 | data/full_repos/permissive/108908995/test_fnet.v | 108,908,995 | test_fnet.v | v | 41 | 89 | [] | [] | [] | null | line:29: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/108908995/test_fnet.v:9: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108908995/test_fnet.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("%h", out);\n ^\n%Error: data/full_repos/permissive/108908995/test_fnet.v:16: Cannot find file containing module: \'fnet\'\nfnet fnet (\n^~~~\n ... Looked in:\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.v\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.sv\n fnet\n fnet.v\n fnet.sv\n obj_dir/fnet\n obj_dir/fnet.v\n obj_dir/fnet.sv\n%Error: data/full_repos/permissive/108908995/test_fnet.v:22: Cannot find file containing module: \'ifnet\'\nifnet ifnet (\n^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,398 | module | module top;
reg clk;
initial
clk = 1'b0;
always
#1 clk = ~clk;
wire [63:0]in = 64'hDEADBEEFBAADF00D;
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
wire [63:0]out;
wire [63:0]i_out;
fnet fnet (
.IN(in),
.KEY(key),
.OUT(out)
);
ifnet ifnet (
.IN(out),
.KEY(key),
.OUT(i_out)
);
initial begin
#1 $display("%h", out);
$display("%h", i_out);
if (in == i_out)
$display("[PASSED]");
else
$display("[FAILED]");
$finish;
end
endmodule | module top; |
reg clk;
initial
clk = 1'b0;
always
#1 clk = ~clk;
wire [63:0]in = 64'hDEADBEEFBAADF00D;
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
wire [63:0]out;
wire [63:0]i_out;
fnet fnet (
.IN(in),
.KEY(key),
.OUT(out)
);
ifnet ifnet (
.IN(out),
.KEY(key),
.OUT(i_out)
);
initial begin
#1 $display("%h", out);
$display("%h", i_out);
if (in == i_out)
$display("[PASSED]");
else
$display("[FAILED]");
$finish;
end
endmodule | 4 |
4,197 | data/full_repos/permissive/108908995/top.v | 108,908,995 | top.v | v | 203 | 141 | [] | [] | [] | [(1, 202)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/108908995/top.v:14: Operator XOR expects 512 bits on the LHS, but LHS\'s CONST \'256\'h1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100\' generates 256 bits.\n : ... In instance top\nwire [255:0]key = 256\'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 ^ {{8{pin}}, {16{{pin[7:0], pin[15:8]}}}, {8{pin}}};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/108908995/top.v:14: Operator ASSIGNW expects 256 bits on the Assign RHS, but Assign RHS\'s XOR generates 512 bits.\n : ... In instance top\nwire [255:0]key = 256\'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 ^ {{8{pin}}, {16{{pin[7:0], pin[15:8]}}}, {8{pin}}};\n ^\n%Error: data/full_repos/permissive/108908995/top.v:18: Cannot find file containing module: \'fnet\'\nfnet fnet (\n^~~~\n ... Looked in:\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.v\n data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.sv\n fnet\n fnet.v\n fnet.sv\n obj_dir/fnet\n obj_dir/fnet.v\n obj_dir/fnet.sv\n%Error: data/full_repos/permissive/108908995/top.v:26: Cannot find file containing module: \'ifnet\'\nifnet ifnet (\n^~~~~\n%Error: data/full_repos/permissive/108908995/top.v:55: Cannot find file containing module: \'async_receiver\'\nasync_receiver ar(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/108908995/top.v:125: Cannot find file containing module: \'uart_tx\'\nuart_tx ut(\n^~~~~~~\n%Error: data/full_repos/permissive/108908995/top.v:194: Cannot find file containing module: \'ssd\'\nssd ssd_inst(\n^~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 2,400 | module | module top
(
input CLK,
output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G,
input TXD,
output RXD,
input KEY1, KEY2, KEY3
);
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 ^ {{8{pin}}, {16{{pin[7:0], pin[15:8]}}}, {8{pin}}};
wire [63:0]enc_in = enc_buffer;
wire [63:0]enc_out;
fnet fnet (
.IN(enc_in),
.KEY(key),
.OUT(enc_out)
);
wire [63:0]dec_in = dec_buffer;
wire [63:0]dec_out;
ifnet ifnet (
.IN(dec_in),
.KEY(key),
.OUT(dec_out)
);
reg mode = 1'b1;
reg mode_set = 1'b0;
reg [15:0]pin = 16'b0;
reg [23:0]cnt = 0;
always @(posedge CLK) begin
cnt <= cnt + 1;
if (~|cnt[22:0] & ~KEY3)
pin[7:0] <= pin[7:0] + 1;
if (~|cnt[22:0] & ~KEY2)
pin[15:8] <= pin[15:8] + 1;
if (~|cnt & ~KEY1)
mode <= ~mode;
end
wire [63:0]out = mode ? enc_out : dec_out;
wire [15:0]word = pin;
wire [7:0]uart_rx_data1;
wire [7:0]uart_rx_data = uart_rx_data1;
wire uart_ready;
async_receiver ar(
.clk(CLK),
.RxD(TXD),
.RxD_data_ready(uart_ready),
.RxD_data(uart_rx_data1)
);
wire [63:0]in_data = { in_buffer[63:8], uart_rx_data };
reg [63:0]in_buffer = 64'h0;
reg [2:0]uart_read_state = 3'b000;
always @(posedge CLK) begin
if (uart_ready) begin
case (uart_read_state)
3'b000: begin
in_buffer[63:56] <= uart_rx_data;
uart_read_state <= 3'b001;
end
3'b001: begin
in_buffer[55:48] <= uart_rx_data;
uart_read_state <= 3'b010;
end
3'b010: begin
in_buffer[47:40] <= uart_rx_data;
uart_read_state <= 3'b011;
end
3'b011: begin
in_buffer[39:32] <= uart_rx_data;
uart_read_state <= 3'b100;
end
3'b100: begin
in_buffer[31:24] <= uart_rx_data;
uart_read_state <= 3'b101;
end
3'b101: begin
in_buffer[23:16] <= uart_rx_data;
uart_read_state <= 3'b110;
end
3'b110: begin
in_buffer[15:8] <= uart_rx_data;
uart_read_state <= 3'b111;
end
3'b111: begin
if (&in_data & ~mode_set) begin
mode_set <= 1'b1;
end
if (mode)
enc_buffer <= in_data;
else
dec_buffer <= in_data;
in_buffer[7:0] <= uart_rx_data;
uart_read_state <= 3'b000;
buffer_ready <= 1'b1;
end
endcase
end
else begin
buffer_ready <= 1'b0;
end
end
reg [63:0]enc_buffer = 64'h0;
reg [63:0]dec_buffer = 64'h0;
reg buffer_ready = 1'b0;
reg [7:0]uart_tx_data;
reg uart_tx_start = 0;
wire uart_tx_busy;
uart_tx ut(
.CLK(CLK),
.TXD(RXD),
.BUSY(uart_tx_busy),
.START(uart_tx_start),
.DATA(uart_tx_data)
);
reg [2:0]delay_cnt = 3'b000;
wire delay_start = buffer_ready;
wire delay_sig = (delay_cnt == 3'b111);
always @(posedge CLK) begin
if (delay_start)
delay_cnt <= 3'b001;
else if (|delay_cnt)
delay_cnt <= delay_cnt + 3'b001;
end
reg [63:0]out_buffer = 64'h3031323334353637;
reg [3:0]uart_write_state = 4'b1000;
always @(posedge CLK) begin
if (delay_sig & (uart_write_state == 4'b1000)) begin
out_buffer <= out;
uart_write_state <= 4'b0;
end
if (!uart_tx_busy) begin
case (uart_write_state)
4'b0000: begin
uart_tx_data <= out_buffer[63:56];
uart_write_state <= 4'b0001;
end
4'b0001: begin
uart_tx_data <= out_buffer[55:48];
uart_write_state <= 4'b0010;
end
4'b0010: begin
uart_tx_data <= out_buffer[47:40];
uart_write_state <= 4'b0011;
end
4'b0011: begin
uart_tx_data <= out_buffer[39:32];
uart_write_state <= 4'b0100;
end
4'b0100: begin
uart_tx_data <= out_buffer[31:24];
uart_write_state <= 4'b0101;
end
4'b0101: begin
uart_tx_data <= out_buffer[23:16];
uart_write_state <= 4'b0110;
end
4'b0110: begin
uart_tx_data <= out_buffer[15:8];
uart_write_state <= 4'b0111;
end
4'b0111: begin
uart_tx_data <= out_buffer[7:0];
uart_write_state <= 4'b1000;
end
endcase
if (uart_write_state != 4'b1000)
uart_tx_start <= 1'b1;
end
else
uart_tx_start <= 1'b0;
end
ssd ssd_inst(
.CLK(CLK),
.EN(mode),
.SEN1(DS_EN1), .SEN2(DS_EN2), .SEN3(DS_EN3), .SEN4(DS_EN4),
.SSA(DS_A), .SSB(DS_B), .SSC(DS_C), .SSD(DS_D), .SSE(DS_E), .SSF(DS_F), .SSG(DS_G),
.WORD(word)
);
endmodule | module top
(
input CLK,
output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G,
input TXD,
output RXD,
input KEY1, KEY2, KEY3
); |
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 ^ {{8{pin}}, {16{{pin[7:0], pin[15:8]}}}, {8{pin}}};
wire [63:0]enc_in = enc_buffer;
wire [63:0]enc_out;
fnet fnet (
.IN(enc_in),
.KEY(key),
.OUT(enc_out)
);
wire [63:0]dec_in = dec_buffer;
wire [63:0]dec_out;
ifnet ifnet (
.IN(dec_in),
.KEY(key),
.OUT(dec_out)
);
reg mode = 1'b1;
reg mode_set = 1'b0;
reg [15:0]pin = 16'b0;
reg [23:0]cnt = 0;
always @(posedge CLK) begin
cnt <= cnt + 1;
if (~|cnt[22:0] & ~KEY3)
pin[7:0] <= pin[7:0] + 1;
if (~|cnt[22:0] & ~KEY2)
pin[15:8] <= pin[15:8] + 1;
if (~|cnt & ~KEY1)
mode <= ~mode;
end
wire [63:0]out = mode ? enc_out : dec_out;
wire [15:0]word = pin;
wire [7:0]uart_rx_data1;
wire [7:0]uart_rx_data = uart_rx_data1;
wire uart_ready;
async_receiver ar(
.clk(CLK),
.RxD(TXD),
.RxD_data_ready(uart_ready),
.RxD_data(uart_rx_data1)
);
wire [63:0]in_data = { in_buffer[63:8], uart_rx_data };
reg [63:0]in_buffer = 64'h0;
reg [2:0]uart_read_state = 3'b000;
always @(posedge CLK) begin
if (uart_ready) begin
case (uart_read_state)
3'b000: begin
in_buffer[63:56] <= uart_rx_data;
uart_read_state <= 3'b001;
end
3'b001: begin
in_buffer[55:48] <= uart_rx_data;
uart_read_state <= 3'b010;
end
3'b010: begin
in_buffer[47:40] <= uart_rx_data;
uart_read_state <= 3'b011;
end
3'b011: begin
in_buffer[39:32] <= uart_rx_data;
uart_read_state <= 3'b100;
end
3'b100: begin
in_buffer[31:24] <= uart_rx_data;
uart_read_state <= 3'b101;
end
3'b101: begin
in_buffer[23:16] <= uart_rx_data;
uart_read_state <= 3'b110;
end
3'b110: begin
in_buffer[15:8] <= uart_rx_data;
uart_read_state <= 3'b111;
end
3'b111: begin
if (&in_data & ~mode_set) begin
mode_set <= 1'b1;
end
if (mode)
enc_buffer <= in_data;
else
dec_buffer <= in_data;
in_buffer[7:0] <= uart_rx_data;
uart_read_state <= 3'b000;
buffer_ready <= 1'b1;
end
endcase
end
else begin
buffer_ready <= 1'b0;
end
end
reg [63:0]enc_buffer = 64'h0;
reg [63:0]dec_buffer = 64'h0;
reg buffer_ready = 1'b0;
reg [7:0]uart_tx_data;
reg uart_tx_start = 0;
wire uart_tx_busy;
uart_tx ut(
.CLK(CLK),
.TXD(RXD),
.BUSY(uart_tx_busy),
.START(uart_tx_start),
.DATA(uart_tx_data)
);
reg [2:0]delay_cnt = 3'b000;
wire delay_start = buffer_ready;
wire delay_sig = (delay_cnt == 3'b111);
always @(posedge CLK) begin
if (delay_start)
delay_cnt <= 3'b001;
else if (|delay_cnt)
delay_cnt <= delay_cnt + 3'b001;
end
reg [63:0]out_buffer = 64'h3031323334353637;
reg [3:0]uart_write_state = 4'b1000;
always @(posedge CLK) begin
if (delay_sig & (uart_write_state == 4'b1000)) begin
out_buffer <= out;
uart_write_state <= 4'b0;
end
if (!uart_tx_busy) begin
case (uart_write_state)
4'b0000: begin
uart_tx_data <= out_buffer[63:56];
uart_write_state <= 4'b0001;
end
4'b0001: begin
uart_tx_data <= out_buffer[55:48];
uart_write_state <= 4'b0010;
end
4'b0010: begin
uart_tx_data <= out_buffer[47:40];
uart_write_state <= 4'b0011;
end
4'b0011: begin
uart_tx_data <= out_buffer[39:32];
uart_write_state <= 4'b0100;
end
4'b0100: begin
uart_tx_data <= out_buffer[31:24];
uart_write_state <= 4'b0101;
end
4'b0101: begin
uart_tx_data <= out_buffer[23:16];
uart_write_state <= 4'b0110;
end
4'b0110: begin
uart_tx_data <= out_buffer[15:8];
uart_write_state <= 4'b0111;
end
4'b0111: begin
uart_tx_data <= out_buffer[7:0];
uart_write_state <= 4'b1000;
end
endcase
if (uart_write_state != 4'b1000)
uart_tx_start <= 1'b1;
end
else
uart_tx_start <= 1'b0;
end
ssd ssd_inst(
.CLK(CLK),
.EN(mode),
.SEN1(DS_EN1), .SEN2(DS_EN2), .SEN3(DS_EN3), .SEN4(DS_EN4),
.SSA(DS_A), .SSB(DS_B), .SSC(DS_C), .SSD(DS_D), .SSE(DS_E), .SSF(DS_F), .SSG(DS_G),
.WORD(word)
);
endmodule | 4 |
4,204 | data/full_repos/permissive/109209652/verilog/fifo_deserial.v | 109,209,652 | fifo_deserial.v | v | 95 | 64 | [] | [] | [] | null | line:22: before: "<=" | data/verilator_xmls/22c7a12f-95aa-4636-b173-3fd7a381fe37.xml | null | 2,403 | module | module fifo_deserial(
input clk,
input reset,
input [31:0] data_in,
input fifo_empty,
input outfifo_full,
output fifo_rdreq,
output reg [9:0] img_in_x,
output reg [9:0] img_in_y,
output reg [7:0] img_in_left,
output reg [7:0] img_in_right,
output img_is_val,
input [9:0] debug_in,
output [5:0] debug_out
);
assign fifo_rdreq = ~fifo_empty & ~outfifo_full;
reg in_is_val;
always @(posedge clk) begin
if (fifo_rdreq) begin
in_is_val <= 1;
end
else begin
in_is_val <= 0;
end
end
reg coord_is_val;
reg pix_is_val;
reg read_next_packet;
always @(posedge clk) begin
if (reset) begin
coord_is_val <= 0;
pix_is_val <= 0;
read_next_packet <= 1;
end
else begin
if (read_next_packet) begin
pix_is_val <= 0;
if (!data_in[31] && in_is_val) begin
img_in_x <= data_in[9:0];
img_in_y <= data_in[25:16];
coord_is_val <= 1;
read_next_packet <= 0;
end
else begin
coord_is_val <= 0;
read_next_packet <= 1;
end
end
else begin
if (data_in[31] && in_is_val) begin
img_in_left <= data_in[15:8];
img_in_right <= data_in[7:0];
pix_is_val <= 1;
read_next_packet <= 1;
end
else begin
pix_is_val <= 0;
read_next_packet <= 0;
end
end
end
end
assign img_is_val = coord_is_val & pix_is_val;
assign debug_out[0] = pix_is_val;
assign debug_out[1] = coord_is_val;
assign debug_out[2] = fifo_rdreq;
assign debug_out[3] = in_is_val;
assign debug_out[4] = read_next_packet;
assign debug_out[5] = data_in[31];
endmodule | module fifo_deserial(
input clk,
input reset,
input [31:0] data_in,
input fifo_empty,
input outfifo_full,
output fifo_rdreq,
output reg [9:0] img_in_x,
output reg [9:0] img_in_y,
output reg [7:0] img_in_left,
output reg [7:0] img_in_right,
output img_is_val,
input [9:0] debug_in,
output [5:0] debug_out
); |
assign fifo_rdreq = ~fifo_empty & ~outfifo_full;
reg in_is_val;
always @(posedge clk) begin
if (fifo_rdreq) begin
in_is_val <= 1;
end
else begin
in_is_val <= 0;
end
end
reg coord_is_val;
reg pix_is_val;
reg read_next_packet;
always @(posedge clk) begin
if (reset) begin
coord_is_val <= 0;
pix_is_val <= 0;
read_next_packet <= 1;
end
else begin
if (read_next_packet) begin
pix_is_val <= 0;
if (!data_in[31] && in_is_val) begin
img_in_x <= data_in[9:0];
img_in_y <= data_in[25:16];
coord_is_val <= 1;
read_next_packet <= 0;
end
else begin
coord_is_val <= 0;
read_next_packet <= 1;
end
end
else begin
if (data_in[31] && in_is_val) begin
img_in_left <= data_in[15:8];
img_in_right <= data_in[7:0];
pix_is_val <= 1;
read_next_packet <= 1;
end
else begin
pix_is_val <= 0;
read_next_packet <= 0;
end
end
end
end
assign img_is_val = coord_is_val & pix_is_val;
assign debug_out[0] = pix_is_val;
assign debug_out[1] = coord_is_val;
assign debug_out[2] = fifo_rdreq;
assign debug_out[3] = in_is_val;
assign debug_out[4] = read_next_packet;
assign debug_out[5] = data_in[31];
endmodule | 1 |
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