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3,807 | data/full_repos/permissive/106966316/extencion_signo.v | 106,966,316 | extencion_signo.v | v | 34 | 102 | [] | [] | [] | [(23, 33)] | null | data/verilator_xmls/a7db788c-ebba-4a3e-be9c-63eba5ecc15a.xml | null | 1,591 | module | module extencion_signo(clk,instr,oinstr);
input [15:0] instr;
input clk;
output reg [31:0] oinstr;
always @(*)
begin
oinstr = instr[15] ? ({16'b1111111111111111,instr[15:0]}) : ({16'b0000000000000000,instr[15:0]});
end
endmodule | module extencion_signo(clk,instr,oinstr); |
input [15:0] instr;
input clk;
output reg [31:0] oinstr;
always @(*)
begin
oinstr = instr[15] ? ({16'b1111111111111111,instr[15:0]}) : ({16'b0000000000000000,instr[15:0]});
end
endmodule | 0 |
3,808 | data/full_repos/permissive/106966316/extencion_signo_tb.v | 106,966,316 | extencion_signo_tb.v | v | 50 | 83 | [] | [] | [] | null | line:31: before: "reg" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/extencion_signo_tb.v:28: Cannot find file containing module: \'extencion_signo\'\n extencion_signo uut (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo.sv\n extencion_signo\n extencion_signo.v\n extencion_signo.sv\n obj_dir/extencion_signo\n obj_dir/extencion_signo.v\n obj_dir/extencion_signo.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,592 | module | module extencion_signo_tb;
reg [15:0] instr;
wire [31:0] oinstr;
extencion_signo uut (
.instr(instr),
.oinstr(oinstr)
);
initial begin
instr = 16'b1111111111111111;
#100;
instr = 16'b0111111111111111;
#100;
instr = 16'b1111111111111111;
#100;
instr = 16'b0111111111111111;
#100;
end
endmodule | module extencion_signo_tb; |
reg [15:0] instr;
wire [31:0] oinstr;
extencion_signo uut (
.instr(instr),
.oinstr(oinstr)
);
initial begin
instr = 16'b1111111111111111;
#100;
instr = 16'b0111111111111111;
#100;
instr = 16'b1111111111111111;
#100;
instr = 16'b0111111111111111;
#100;
end
endmodule | 0 |
3,809 | data/full_repos/permissive/106966316/memoriaintrucciones.v | 106,966,316 | memoriaintrucciones.v | v | 116 | 118 | [] | [] | [] | [(23, 115)] | null | data/verilator_xmls/71ab8c3b-ecea-42f3-bd62-f9f60feeb641.xml | null | 1,593 | module | module memoriaintrucciones(direinstru,instru,clk,reset);
input [4:0] direinstru;
input clk;
input reset;
output wire [31:0] instru;
reg [31:0] registro_rom [31:0];
assign instru = registro_rom[direinstru];
always @ (*)
begin
if (reset == 1)
begin
registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[2] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[3] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
registro_rom[4] = 32'b1000_1100_0000_0001__0001_1000_0110_0000;
registro_rom[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[6] = 32'b1010_1111_1111_1111__0000_0000_0000_0000;
registro_rom[7] = 32'b1000_1111_1111_1110__0000_0000_0000_0000;
registro_rom[8] = 32'b1000_1100_0000_0001__0001_1000_0110_0000;
registro_rom[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[20] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
else
begin
end
end
endmodule | module memoriaintrucciones(direinstru,instru,clk,reset); |
input [4:0] direinstru;
input clk;
input reset;
output wire [31:0] instru;
reg [31:0] registro_rom [31:0];
assign instru = registro_rom[direinstru];
always @ (*)
begin
if (reset == 1)
begin
registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
registro_rom[2] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
registro_rom[3] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
registro_rom[4] = 32'b1000_1100_0000_0001__0001_1000_0110_0000;
registro_rom[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[6] = 32'b1010_1111_1111_1111__0000_0000_0000_0000;
registro_rom[7] = 32'b1000_1111_1111_1110__0000_0000_0000_0000;
registro_rom[8] = 32'b1000_1100_0000_0001__0001_1000_0110_0000;
registro_rom[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[20] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
registro_rom[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
registro_rom[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
end
else
begin
end
end
endmodule | 0 |
3,810 | data/full_repos/permissive/106966316/memoriaintrucciones_tb.v | 106,966,316 | memoriaintrucciones_tb.v | v | 62 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:30: Cannot find file containing module: \'memoriaintrucciones\'\nmemoriaintrucciones uut(\n^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.sv\n memoriaintrucciones\n memoriaintrucciones.v\n memoriaintrucciones.sv\n obj_dir/memoriaintrucciones\n obj_dir/memoriaintrucciones.v\n obj_dir/memoriaintrucciones.sv\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:50: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:52: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:54: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:56: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h3\' generates 5 bits.\n : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00011;\n ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,594 | module | module memoriaintrucciones_tb;
reg [5:0] direinstru;
wire [31:0] instru;
reg clk;
reg reset;
memoriaintrucciones uut(
.direinstru(direinstru),
.instru(instru),
.clk(clk)
);
always begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100
reset = 1'b0;
#100
direinstru = 5'b00000;
#100;
direinstru = 5'b00001;
#100;
direinstru = 5'b00010;
#100;
direinstru = 5'b00011;
end
endmodule | module memoriaintrucciones_tb; |
reg [5:0] direinstru;
wire [31:0] instru;
reg clk;
reg reset;
memoriaintrucciones uut(
.direinstru(direinstru),
.instru(instru),
.clk(clk)
);
always begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100
reset = 1'b0;
#100
direinstru = 5'b00000;
#100;
direinstru = 5'b00001;
#100;
direinstru = 5'b00010;
#100;
direinstru = 5'b00011;
end
endmodule | 0 |
3,811 | data/full_repos/permissive/106966316/memoria_datos.v | 106,966,316 | memoria_datos.v | v | 94 | 126 | [] | [] | [] | [(23, 92)] | null | null | 1: b"%Error: data/full_repos/permissive/106966316/memoria_datos.v:43: Cannot find file containing module: 'sram'\nsram sram1(.clk(clk),\n^~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.sv\n sram\n sram.v\n sram.sv\n obj_dir/sram\n obj_dir/sram.v\n obj_dir/sram.sv\n%Error: data/full_repos/permissive/106966316/memoria_datos.v:51: Cannot find file containing module: 'sram'\nsram sram2(.clk(clk),\n^~~~\n%Error: data/full_repos/permissive/106966316/memoria_datos.v:60: Cannot find file containing module: 'sram'\nsram ROM(\n^~~~\n%Error: Exiting due to 3 error(s)\n" | 1,595 | module | module memoria_datos(clk,EscrMem,Direc,Datain,LeerMem,Dataout);
input clk;
input EscrMem;
input [31:0] Direc;
input [31:0] Datain;
input LeerMem;
output reg [31:0] Dataout;
wire CSram1;
wire CSram2;
wire [2:0] CS;
wire [31:0] Dataout1;
wire [31:0] Dataout2;
wire [31:0] Dataout3;
wire CSrom;
sram sram1(.clk(clk),
.CSram(CSram1),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout1),
.EscrMem(EscrMem)
);
sram sram2(.clk(clk),
.CSram(CSram2),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout2),
.EscrMem(EscrMem)
);
sram ROM(
.clk(clk),
.CSram(CSrom),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout3),
.EscrMem(EscrMem)
);
assign CSrom = (Direc[31:8]==24'b0000_0000_0000_0000_0000_0100) ? 1 : 0 ;
assign CSram1 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0000)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0001)) ? 1 : 0 ;
assign CSram2 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0010)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0011)) ? 1 : 0 ;
assign CS = {CSrom,CSram1,CSram2};
always @ (*)
begin
case(CS)
3'b100:Dataout = Dataout3;
3'b010:Dataout = Dataout1;
3'b001:Dataout = Dataout2;
endcase
end
endmodule | module memoria_datos(clk,EscrMem,Direc,Datain,LeerMem,Dataout); |
input clk;
input EscrMem;
input [31:0] Direc;
input [31:0] Datain;
input LeerMem;
output reg [31:0] Dataout;
wire CSram1;
wire CSram2;
wire [2:0] CS;
wire [31:0] Dataout1;
wire [31:0] Dataout2;
wire [31:0] Dataout3;
wire CSrom;
sram sram1(.clk(clk),
.CSram(CSram1),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout1),
.EscrMem(EscrMem)
);
sram sram2(.clk(clk),
.CSram(CSram2),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout2),
.EscrMem(EscrMem)
);
sram ROM(
.clk(clk),
.CSram(CSrom),
.Direc(Direc[7:0]),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout3),
.EscrMem(EscrMem)
);
assign CSrom = (Direc[31:8]==24'b0000_0000_0000_0000_0000_0100) ? 1 : 0 ;
assign CSram1 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0000)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0001)) ? 1 : 0 ;
assign CSram2 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0010)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0011)) ? 1 : 0 ;
assign CS = {CSrom,CSram1,CSram2};
always @ (*)
begin
case(CS)
3'b100:Dataout = Dataout3;
3'b010:Dataout = Dataout1;
3'b001:Dataout = Dataout2;
endcase
end
endmodule | 0 |
3,812 | data/full_repos/permissive/106966316/memoria_datos_tb.v | 106,966,316 | memoria_datos_tb.v | v | 101 | 83 | [] | [] | [] | [(23, 100)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/memoria_datos_tb.v:31: Cannot find file containing module: \'memoria_datos\'\n memoria_datos uut(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos.sv\n memoria_datos\n memoria_datos.v\n memoria_datos.sv\n obj_dir/memoria_datos\n obj_dir/memoria_datos.v\n obj_dir/memoria_datos.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,596 | module | module memoria_datos_tb();
reg clk;
reg EscrMem;
reg [31:0] Direc;
reg [31:0] Datain;
reg LeerMem;
wire [31:0] Dataout;
memoria_datos uut(
.clk(clk),
.EscrMem(EscrMem),
.Direc(Direc),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0100_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0000_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
#100;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0010_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0011;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0100_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0000_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0010_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
end
endmodule | module memoria_datos_tb(); |
reg clk;
reg EscrMem;
reg [31:0] Direc;
reg [31:0] Datain;
reg LeerMem;
wire [31:0] Dataout;
memoria_datos uut(
.clk(clk),
.EscrMem(EscrMem),
.Direc(Direc),
.Datain(Datain),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0100_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0000_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
#100;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 32'b0000_0000_0000_0000__0000_0010_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0011;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0100_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0000_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
#100;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 32'b0000_0000_0000_0000__0000_0010_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0010;
end
endmodule | 0 |
3,813 | data/full_repos/permissive/106966316/pc.v | 106,966,316 | pc.v | v | 102 | 91 | [] | [] | [] | [(23, 101)] | null | data/verilator_xmls/ac4b341d-d02c-472c-b8d0-8b8077e98995.xml | null | 1,597 | module | module pc(
input SaltoCond,
input Saltoincond,
input [31:0] extSigno,
input oZero,
input clk,
input reset,
input [31:0]instru,
output reg [31:0] direinstru
);
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] sal2PC;
wire [31:0] mux2mux;
parameter init = 0;
assign salSum2 = extSigno + sum2sum;
assign sum2sum = direinstru +1;
assign sal2PC = (Saltoincond)? {sum2sum[31:28],instru[27:0]} : mux2mux;
assign FuentePC = SaltoCond & oZero;
assign mux2mux = FuentePC ? salSum2 : sum2sum;
/
always @(posedge clk)
begin
if (reset==1)
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
else
direinstru = sal2PC;
end
endmodule | module pc(
input SaltoCond,
input Saltoincond,
input [31:0] extSigno,
input oZero,
input clk,
input reset,
input [31:0]instru,
output reg [31:0] direinstru
); |
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] sal2PC;
wire [31:0] mux2mux;
parameter init = 0;
assign salSum2 = extSigno + sum2sum;
assign sum2sum = direinstru +1;
assign sal2PC = (Saltoincond)? {sum2sum[31:28],instru[27:0]} : mux2mux;
assign FuentePC = SaltoCond & oZero;
assign mux2mux = FuentePC ? salSum2 : sum2sum;
/
always @(posedge clk)
begin
if (reset==1)
direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
else
direinstru = sal2PC;
end
endmodule | 0 |
3,814 | data/full_repos/permissive/106966316/pc_tb.v | 106,966,316 | pc_tb.v | v | 90 | 83 | [] | [] | [] | [(23, 89)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/pc_tb.v:33: Cannot find file containing module: \'pc\'\n pc uut(\n ^~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc.sv\n pc\n pc.v\n pc.sv\n obj_dir/pc\n obj_dir/pc.v\n obj_dir/pc.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,598 | module | module pc_tb();
reg clk;
reg SaltoCond;
reg [31:0] extSigno;
reg oZero;
reg reset;
wire [31:0] direinstru;
pc uut(
.clk(clk),
.SaltoCond(SaltoCond),
.extSigno(extSigno),
.oZero(oZero),
.direinstru(direinstru),
.reset(reset)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
reset = 1'b1;
extSigno = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
oZero=1'b0;
SaltoCond = 1'b0;
#100
reset = 1'b0;
#100
oZero=1'b0;
SaltoCond = 1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero = 1'b1;
SaltoCond=1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b0;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100;
end
endmodule | module pc_tb(); |
reg clk;
reg SaltoCond;
reg [31:0] extSigno;
reg oZero;
reg reset;
wire [31:0] direinstru;
pc uut(
.clk(clk),
.SaltoCond(SaltoCond),
.extSigno(extSigno),
.oZero(oZero),
.direinstru(direinstru),
.reset(reset)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
reset = 1'b1;
extSigno = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
oZero=1'b0;
SaltoCond = 1'b0;
#100
reset = 1'b0;
#100
oZero=1'b0;
SaltoCond = 1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero = 1'b1;
SaltoCond=1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b0;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100;
end
endmodule | 0 |
3,815 | data/full_repos/permissive/106966316/procesador_monociclo.v | 106,966,316 | procesador_monociclo.v | v | 144 | 83 | [] | [] | [] | [(23, 143)] | null | null | 1: b"%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:67: Cannot find file containing module: 'memoriaintrucciones'\n memoriaintrucciones memoriainstru(\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.sv\n memoriaintrucciones\n memoriaintrucciones.v\n memoriaintrucciones.sv\n obj_dir/memoriaintrucciones\n obj_dir/memoriaintrucciones.v\n obj_dir/memoriaintrucciones.sv\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:74: Cannot find file containing module: 'control'\n control control(.instru(instru[31:26]),\n ^~~~~~~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:87: Cannot find file containing module: 'bankregister'\n bankregister registros(.RegLe1(instru[25:21]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:98: Cannot find file containing module: 'extencion_signo'\n extencion_signo extencion(.instr(instru[15:0]),\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:103: Cannot find file containing module: 'alu32'\n alu32 alu(.data1(data1),\n ^~~~~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:112: Cannot find file containing module: 'memoria_datos'\n memoria_datos datos(.clk(clk),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:119: Cannot find file containing module: 'pc'\n pc pro_counter(\n ^~\n%Error: data/full_repos/permissive/106966316/procesador_monociclo.v:130: Cannot find file containing module: 'controlALU'\n controlALU contrALU(\n ^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 1,599 | module | module procesador_monociclo(
clk,reset
);
input wire clk;
reg [5:0] direinstru;
wire [31:0] instru;
wire RegDest;
wire SaltoCond;
wire Saltoincond;
wire LeerMem;
wire MemaReg;
wire [1:0]ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
wire [31:0] data1;
wire [31:0] data2;
wire [31:0] datain;
wire [31:0] oinstru;
wire [2:0] ctrl;
wire oCarry;
wire oZero;
wire [31:0] out;
wire [31:0] Dataout;
wire [4:0] RegEscr1;
wire [31:0] data21;
wire [31:0] dataEscr;
wire [31:0] ext2;
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] toPC;
wire [31:0]direinstrux;
input wire reset;
parameter varCuatro=3'b100;
memoriaintrucciones memoriainstru(
.direinstru(direinstrux),
.instru(instru),
.clk(clk),
.reset(reset)
);
control control(.instru(instru[31:26]),
.clk(clk),
.RegDest(RegDest),
.Saltoincond(Saltoincond),
.SaltoCond(SaltoCond),
.LeerMem(LeerMem),
.MemaReg(MemaReg),
.ALUOp(ALUOp),
.EscrMem(EscrMem),
.FuenteALU(FuenteALU),
.EscrReg(EscrReg)
);
bankregister registros(.RegLe1(instru[25:21]),
.RegLe2(instru[20:16]),
.RegEscr(RegEscr1),
.EscrReg(EscrReg),
.clk(clk),
.datain(dataEscr),
.data1(data1),
.data2(data2),
.reset(reset)
);
extencion_signo extencion(.instr(instru[15:0]),
.oinstr(oinstru),
.clk(clk)
);
alu32 alu(.data1(data1),
.data2(data21),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
memoria_datos datos(.clk(clk),
.EscrMem(EscrMem),
.Direc(out),
.Datain(data2),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
pc pro_counter(
.SaltoCond(SaltoCond),
.Saltoincond(Saltoincond),
.extSigno(oinstru),
.oZero(oZero),
.direinstru(direinstrux),
.clk(clk),
.reset(reset),
.instru(instru)
);
controlALU contrALU(
.ALUop(ALUOp),
.instru(instru[5:0]),
.clk(clk),
.contALU(ctrl)
);
assign RegEscr1 = RegDest ? instru[15:11]: instru[20:16];
assign data21 = FuenteALU ? oinstru : data2;
assign dataEscr = MemaReg ? Dataout : out;
endmodule | module procesador_monociclo(
clk,reset
); |
input wire clk;
reg [5:0] direinstru;
wire [31:0] instru;
wire RegDest;
wire SaltoCond;
wire Saltoincond;
wire LeerMem;
wire MemaReg;
wire [1:0]ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
wire [31:0] data1;
wire [31:0] data2;
wire [31:0] datain;
wire [31:0] oinstru;
wire [2:0] ctrl;
wire oCarry;
wire oZero;
wire [31:0] out;
wire [31:0] Dataout;
wire [4:0] RegEscr1;
wire [31:0] data21;
wire [31:0] dataEscr;
wire [31:0] ext2;
wire [31:0] sum2sum;
wire [31:0] salSum2;
wire FuentePC;
wire [31:0] toPC;
wire [31:0]direinstrux;
input wire reset;
parameter varCuatro=3'b100;
memoriaintrucciones memoriainstru(
.direinstru(direinstrux),
.instru(instru),
.clk(clk),
.reset(reset)
);
control control(.instru(instru[31:26]),
.clk(clk),
.RegDest(RegDest),
.Saltoincond(Saltoincond),
.SaltoCond(SaltoCond),
.LeerMem(LeerMem),
.MemaReg(MemaReg),
.ALUOp(ALUOp),
.EscrMem(EscrMem),
.FuenteALU(FuenteALU),
.EscrReg(EscrReg)
);
bankregister registros(.RegLe1(instru[25:21]),
.RegLe2(instru[20:16]),
.RegEscr(RegEscr1),
.EscrReg(EscrReg),
.clk(clk),
.datain(dataEscr),
.data1(data1),
.data2(data2),
.reset(reset)
);
extencion_signo extencion(.instr(instru[15:0]),
.oinstr(oinstru),
.clk(clk)
);
alu32 alu(.data1(data1),
.data2(data21),
.ctrl(ctrl),
.clk(clk),
.oCarry(oCarry),
.oZero(oZero),
.out(out)
);
memoria_datos datos(.clk(clk),
.EscrMem(EscrMem),
.Direc(out),
.Datain(data2),
.LeerMem(LeerMem),
.Dataout(Dataout)
);
pc pro_counter(
.SaltoCond(SaltoCond),
.Saltoincond(Saltoincond),
.extSigno(oinstru),
.oZero(oZero),
.direinstru(direinstrux),
.clk(clk),
.reset(reset),
.instru(instru)
);
controlALU contrALU(
.ALUop(ALUOp),
.instru(instru[5:0]),
.clk(clk),
.contALU(ctrl)
);
assign RegEscr1 = RegDest ? instru[15:11]: instru[20:16];
assign data21 = FuenteALU ? oinstru : data2;
assign dataEscr = MemaReg ? Dataout : out;
endmodule | 0 |
3,816 | data/full_repos/permissive/106966316/procesador_monociclo_tb.v | 106,966,316 | procesador_monociclo_tb.v | v | 49 | 83 | [] | [] | [] | [(23, 48)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/procesador_monociclo_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/procesador_monociclo_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/procesador_monociclo_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/procesador_monociclo_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #101;\n ^\n%Error: data/full_repos/permissive/106966316/procesador_monociclo_tb.v:27: Cannot find file containing module: \'procesador_monociclo\'\n procesador_monociclo uut(\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/procesador_monociclo\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/procesador_monociclo.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/procesador_monociclo.sv\n procesador_monociclo\n procesador_monociclo.v\n procesador_monociclo.sv\n obj_dir/procesador_monociclo\n obj_dir/procesador_monociclo.v\n obj_dir/procesador_monociclo.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,600 | module | module procesador_monociclo_tb();
reg clk;
reg reset;
procesador_monociclo uut(
.clk(clk),
.reset(reset)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
reset=1'b1;
#101;
reset=1'b0;
#101;
end
endmodule | module procesador_monociclo_tb(); |
reg clk;
reg reset;
procesador_monociclo uut(
.clk(clk),
.reset(reset)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
reset=1'b1;
#101;
reset=1'b0;
#101;
end
endmodule | 0 |
3,817 | data/full_repos/permissive/106966316/sram.v | 106,966,316 | sram.v | v | 49 | 83 | [] | [] | [] | [(23, 48)] | null | data/verilator_xmls/27e4b1b1-9159-4dfd-8f55-4110b3e95358.xml | null | 1,601 | module | module sram(clk,CSram,Direc,Datain,LeerMem,Dataout,EscrMem);
input clk;
input CSram;
input [7:0] Direc;
input [31:0] Datain;
input LeerMem;
output wire [31:0] Dataout;
input EscrMem;
reg [31:0] RAM [0:255];
assign Dataout = LeerMem ? RAM[Direc]:32'b0;
always @ (posedge clk)
begin
if(CSram==1'b1)
begin
if (EscrMem==1'b1)
begin
RAM[Direc] = Datain;
end
end
end
endmodule | module sram(clk,CSram,Direc,Datain,LeerMem,Dataout,EscrMem); |
input clk;
input CSram;
input [7:0] Direc;
input [31:0] Datain;
input LeerMem;
output wire [31:0] Dataout;
input EscrMem;
reg [31:0] RAM [0:255];
assign Dataout = LeerMem ? RAM[Direc]:32'b0;
always @ (posedge clk)
begin
if(CSram==1'b1)
begin
if (EscrMem==1'b1)
begin
RAM[Direc] = Datain;
end
end
end
endmodule | 0 |
3,818 | data/full_repos/permissive/106966316/sram_tb.v | 106,966,316 | sram_tb.v | v | 92 | 83 | [] | [] | [] | null | line:56 column:13: Illegal character "'" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/sram_tb.v:34: Cannot find file containing module: \'sram\'\nsram uut(\n^~~~\n ... Looked in:\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.v\n data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.sv\n sram\n sram.v\n sram.sv\n obj_dir/sram\n obj_dir/sram.v\n obj_dir/sram.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,602 | module | module sram_tb();
reg clk;
reg CSram;
reg [7:0] Direc;
reg [31:0] Datain;
reg LeerMem;
reg EscrMem;
wire [31:0] Dataout;
sram uut(
.clk(clk),
.CSram(CSram),
.Direc(Direc),
.Datain(Datain),
.LeerMem(LeerMem),
.EscrMem(EscrMem),
.Dataout(Dataout)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0011;
#100;
CSram=1'b1;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
end
endmodule | module sram_tb(); |
reg clk;
reg CSram;
reg [7:0] Direc;
reg [31:0] Datain;
reg LeerMem;
reg EscrMem;
wire [31:0] Dataout;
sram uut(
.clk(clk),
.CSram(CSram),
.Direc(Direc),
.Datain(Datain),
.LeerMem(LeerMem),
.EscrMem(EscrMem),
.Dataout(Dataout)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0011;
#100;
CSram=1'b1;
EscrMem = 1'b0;
LeerMem = 1'b1;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
CSram=1'b1;
EscrMem = 1'b1;
LeerMem = 1'b0;
Direc = 8'b_0110_0000;
Datain = 32'b0000_0000_0000_0000__0000_0000_0000_0001;
#100;
end
endmodule | 0 |
3,819 | data/full_repos/permissive/107007139/Lab 1/add_overall_switch.v | 107,007,139 | add_overall_switch.v | v | 36 | 83 | [] | [] | [] | [(23, 35)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/add_overall_switch.v\n%Error: Exiting due to 3 error(s)\n' | 1,603 | module | module add_overall_switch(
input A,
input B,
input C,
output LED1,
output LED2,
output LED3
);
assign LED1 = C & ((A & ~B) | (A & B));
assign LED2 = C & ((~A & B) | (A & B));
assign LED3 = C & (A & B);
endmodule | module add_overall_switch(
input A,
input B,
input C,
output LED1,
output LED2,
output LED3
); |
assign LED1 = C & ((A & ~B) | (A & B));
assign LED2 = C & ((~A & B) | (A & B));
assign LED3 = C & (A & B);
endmodule | 0 |
3,820 | data/full_repos/permissive/107007139/Lab 1/add_overall_switch_simulation.v | 107,007,139 | add_overall_switch_simulation.v | v | 52 | 83 | [] | [] | [] | [(23, 51)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/add_overall_switch_simulation.v\n%Error: Exiting due to 3 error(s)\n' | 1,604 | module | module add_overall_switch_simulation(
);
reg A;
reg B;
reg C;
wire LED1;
wire LED2;
wire LED3;
add_overall_switch dut(A, B, C, LED1, LED2, LED3);
initial begin
A = 0; B = 0; C = 0; #10;
A = 0; B = 1; C = 0; #10;
A = 0; B = 0; C = 1; #10;
A = 0; B = 1; C = 1; #10;
A = 1; B = 0; C = 0; #10;
A = 1; B = 1; C = 0; #10;
A = 1; B = 0; C = 1; #10;
A = 1; B = 1; C = 1; #10;
end
endmodule | module add_overall_switch_simulation(
); |
reg A;
reg B;
reg C;
wire LED1;
wire LED2;
wire LED3;
add_overall_switch dut(A, B, C, LED1, LED2, LED3);
initial begin
A = 0; B = 0; C = 0; #10;
A = 0; B = 1; C = 0; #10;
A = 0; B = 0; C = 1; #10;
A = 0; B = 1; C = 1; #10;
A = 1; B = 0; C = 0; #10;
A = 1; B = 1; C = 0; #10;
A = 1; B = 0; C = 1; #10;
A = 1; B = 1; C = 1; #10;
end
endmodule | 0 |
3,821 | data/full_repos/permissive/107007139/Lab 1/Lab 1 Codes [AY1718S1].v | 107,007,139 | Lab 1 Codes [AY1718S1].v | v | 80 | 63 | [] | [] | [] | null | line:1: before: "**" | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/Lab\n%Error: Cannot find file containing module: 1\n%Error: Cannot find file containing module: Codes\n%Error: Cannot find file containing module: [AY1718S1].v\n%Error: Exiting due to 6 error(s)\n' | 1,605 | module | module my_control_module(
input A,
input B,
output LED1,
output LED2,
output LED3
);
assign LED1 = (A & ~B) | (A & B);
endmodule | module my_control_module(
input A,
input B,
output LED1,
output LED2,
output LED3
); |
assign LED1 = (A & ~B) | (A & B);
endmodule | 0 |
3,822 | data/full_repos/permissive/107007139/Lab 1/Lab 1 Codes [AY1718S1].v | 107,007,139 | Lab 1 Codes [AY1718S1].v | v | 80 | 63 | [] | [] | [] | null | line:1: before: "**" | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/Lab\n%Error: Cannot find file containing module: 1\n%Error: Cannot find file containing module: Codes\n%Error: Cannot find file containing module: [AY1718S1].v\n%Error: Exiting due to 6 error(s)\n' | 1,605 | module | module my_control_module_simulation(
);
reg A;
reg B;
wire LED1;
wire LED2;
wire LED3;
my_control_module dut(A, B, LED1, LED2, LED3);
initial begin
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
end
endmodule | module my_control_module_simulation(
); |
reg A;
reg B;
wire LED1;
wire LED2;
wire LED3;
my_control_module dut(A, B, LED1, LED2, LED3);
initial begin
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
end
endmodule | 0 |
3,823 | data/full_repos/permissive/107007139/Lab 1/Lab 1 Codes [AY1718S1].v | 107,007,139 | Lab 1 Codes [AY1718S1].v | v | 80 | 63 | [] | [] | [] | null | line:1: before: "**" | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/Lab\n%Error: Cannot find file containing module: 1\n%Error: Cannot find file containing module: Codes\n%Error: Cannot find file containing module: [AY1718S1].v\n%Error: Exiting due to 6 error(s)\n' | 1,605 | module | module my_2_to_1_mux (input A, B, S, output Z);
assign Z = S ? B : A;
endmodule | module my_2_to_1_mux (input A, B, S, output Z); |
assign Z = S ? B : A;
endmodule | 0 |
3,824 | data/full_repos/permissive/107007139/Lab 1/multiplexer.v | 107,007,139 | multiplexer.v | v | 34 | 83 | [] | [] | [] | [(23, 33)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/multiplexer.v\n%Error: Exiting due to 3 error(s)\n' | 1,606 | module | module multiplexer(
input A,
input B,
input S,
output Z
);
assign Z = S ? B : A;
endmodule | module multiplexer(
input A,
input B,
input S,
output Z
); |
assign Z = S ? B : A;
endmodule | 0 |
3,825 | data/full_repos/permissive/107007139/Lab 1/multiplexer_simulation.v | 107,007,139 | multiplexer_simulation.v | v | 45 | 83 | [] | [] | [] | [(23, 44)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/multiplexer_simulation.v\n%Error: Exiting due to 3 error(s)\n' | 1,607 | module | module multiplexer_simulation(
);
reg A;
reg B;
reg S;
wire Z;
multiplexer dut(A, B, S, Z);
initial begin
S = 0; A = 0; B = 0; #10;
S = 0; A = 1; B = 0; #10;
S = 1; A = 0; B = 0; #10;
S = 1; A = 0; B = 1; #10;
end
endmodule | module multiplexer_simulation(
); |
reg A;
reg B;
reg S;
wire Z;
multiplexer dut(A, B, S, Z);
initial begin
S = 0; A = 0; B = 0; #10;
S = 0; A = 1; B = 0; #10;
S = 1; A = 0; B = 0; #10;
S = 1; A = 0; B = 1; #10;
end
endmodule | 0 |
3,826 | data/full_repos/permissive/107007139/Lab 1/test_simple_boolean.v | 107,007,139 | test_simple_boolean.v | v | 48 | 83 | [] | [] | [] | [(23, 47)] | null | null | 1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/1,data/full_repos/permissive/107007139.sv\n 1,data/full_repos/permissive/107007139\n 1,data/full_repos/permissive/107007139.v\n 1,data/full_repos/permissive/107007139.sv\n obj_dir/1,data/full_repos/permissive/107007139\n obj_dir/1,data/full_repos/permissive/107007139.v\n obj_dir/1,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 1/test_simple_boolean.v\n%Error: Exiting due to 3 error(s)\n' | 1,609 | module | module my_control_module_simulation(
);
reg A;
reg B;
wire LED1;
wire LED2;
wire LED3;
my_control_module dut(A, B, LED1, LED2, LED3);
initial begin
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
end
endmodule | module my_control_module_simulation(
); |
reg A;
reg B;
wire LED1;
wire LED2;
wire LED3;
my_control_module dut(A, B, LED1, LED2, LED3);
initial begin
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
end
endmodule | 0 |
3,827 | data/full_repos/permissive/107007139/Lab 2/my_2_bit_full_adder.v | 107,007,139 | my_2_bit_full_adder.v | v | 37 | 83 | [] | [] | [] | [(23, 36)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_2_bit_full_adder.v\n%Error: Exiting due to 3 error(s)\n' | 1,610 | module | module my_2_bit_full_adder(
input [1:0] A,
input [1:0] B,
input C0,
output [1:0] S,
output C2
);
wire C1;
my_full_adder fa0(A[0], B[0], C0, S[0], C1);
my_full_adder fa1(A[1], B[1], C1, S[1], C2);
endmodule | module my_2_bit_full_adder(
input [1:0] A,
input [1:0] B,
input C0,
output [1:0] S,
output C2
); |
wire C1;
my_full_adder fa0(A[0], B[0], C0, S[0], C1);
my_full_adder fa1(A[1], B[1], C1, S[1], C2);
endmodule | 0 |
3,828 | data/full_repos/permissive/107007139/Lab 2/my_2_bit_full_adder_simulation.v | 107,007,139 | my_2_bit_full_adder_simulation.v | v | 46 | 83 | [] | [] | [] | [(23, 45)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_2_bit_full_adder_simulation.v\n%Error: Exiting due to 3 error(s)\n' | 1,611 | module | module my_2_bit_full_adder_simulation(
);
reg [1:0] A;
reg [1:0] B;
reg CIN;
wire COUT;
wire [1:0] S;
my_2_bit_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 2'b00; B = 2'b00; CIN = 1'b0; #10;
A = 2'b00; B = 2'b01; CIN = 1'b0; #10;
A = 2'b01; B = 2'b01; CIN = 1'b0; #10;
A = 2'b01; B = 2'b01; CIN = 1'b1; #10;
end
endmodule | module my_2_bit_full_adder_simulation(
); |
reg [1:0] A;
reg [1:0] B;
reg CIN;
wire COUT;
wire [1:0] S;
my_2_bit_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 2'b00; B = 2'b00; CIN = 1'b0; #10;
A = 2'b00; B = 2'b01; CIN = 1'b0; #10;
A = 2'b01; B = 2'b01; CIN = 1'b0; #10;
A = 2'b01; B = 2'b01; CIN = 1'b1; #10;
end
endmodule | 0 |
3,829 | data/full_repos/permissive/107007139/Lab 2/my_4_bit_full_adder.v | 107,007,139 | my_4_bit_full_adder.v | v | 41 | 83 | [] | [] | [] | [(23, 40)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_4_bit_full_adder.v\n%Error: Exiting due to 3 error(s)\n' | 1,612 | module | module my_4_bit_full_adder(
input [3:0] A,
input [3:0] B,
input C0,
output [3:0] S,
output C4
);
wire C1;
wire C2;
wire C3;
my_full_adder fa0(A[0], B[0], C0, S[0], C1);
my_full_adder fa1(A[1], B[1], C1, S[1], C2);
my_full_adder fa2(A[2], B[2], C2, S[2], C3);
my_full_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule | module my_4_bit_full_adder(
input [3:0] A,
input [3:0] B,
input C0,
output [3:0] S,
output C4
); |
wire C1;
wire C2;
wire C3;
my_full_adder fa0(A[0], B[0], C0, S[0], C1);
my_full_adder fa1(A[1], B[1], C1, S[1], C2);
my_full_adder fa2(A[2], B[2], C2, S[2], C3);
my_full_adder fa3(A[3], B[3], C3, S[3], C4);
endmodule | 0 |
3,830 | data/full_repos/permissive/107007139/Lab 2/my_4_bit_full_adder_simulation.v | 107,007,139 | my_4_bit_full_adder_simulation.v | v | 45 | 83 | [] | [] | [] | [(23, 44)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_4_bit_full_adder_simulation.v\n%Error: Exiting due to 3 error(s)\n' | 1,613 | module | module my_4_bit_full_adder_simulation(
);
reg [3:0] A;
reg [3:0] B;
reg CIN;
wire [3:0] S;
wire COUT;
my_4_bit_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 4'b0011; B = 4'b0011; CIN = 1'b0; #10;
A = 4'b1011; B = 4'b0111; CIN = 1'b0; #10;
A = 4'b1111; B = 4'b1111; CIN = 1'b0; #10;
end
endmodule | module my_4_bit_full_adder_simulation(
); |
reg [3:0] A;
reg [3:0] B;
reg CIN;
wire [3:0] S;
wire COUT;
my_4_bit_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 4'b0011; B = 4'b0011; CIN = 1'b0; #10;
A = 4'b1011; B = 4'b0111; CIN = 1'b0; #10;
A = 4'b1111; B = 4'b1111; CIN = 1'b0; #10;
end
endmodule | 0 |
3,831 | data/full_repos/permissive/107007139/Lab 2/my_full_adder.v | 107,007,139 | my_full_adder.v | v | 35 | 83 | [] | [] | [] | [(23, 34)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_full_adder.v\n%Error: Exiting due to 3 error(s)\n' | 1,614 | module | module my_full_adder(
input A,
input B,
input CIN,
output S,
output COUT
);
assign S = A ^ B ^ CIN;
assign COUT = A & B | CIN & (A ^ B);
endmodule | module my_full_adder(
input A,
input B,
input CIN,
output S,
output COUT
); |
assign S = A ^ B ^ CIN;
assign COUT = A & B | CIN & (A ^ B);
endmodule | 0 |
3,832 | data/full_repos/permissive/107007139/Lab 2/my_full_adder_simulation.v | 107,007,139 | my_full_adder_simulation.v | v | 51 | 83 | [] | [] | [] | [(23, 50)] | null | null | 1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n 2,data/full_repos/permissive/107007139\n 2,data/full_repos/permissive/107007139.v\n 2,data/full_repos/permissive/107007139.sv\n obj_dir/2,data/full_repos/permissive/107007139\n obj_dir/2,data/full_repos/permissive/107007139.v\n obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_full_adder_simulation.v\n%Error: Exiting due to 3 error(s)\n' | 1,615 | module | module my_full_adder_simulation(
);
reg A;
reg B;
reg CIN;
wire S;
wire COUT;
my_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 0; B = 0; CIN = 0; #10;
A = 0; B = 0; CIN = 1; #10;
A = 0; B = 1; CIN = 0; #10;
A = 0; B = 1; CIN = 1; #10;
A = 1; B = 0; CIN = 0; #10;
A = 1; B = 0; CIN = 1; #10;
A = 1; B = 1; CIN = 0; #10;
A = 1; B = 1; CIN = 1; #10;
end
endmodule | module my_full_adder_simulation(
); |
reg A;
reg B;
reg CIN;
wire S;
wire COUT;
my_full_adder dut(A, B, CIN, S, COUT);
initial begin
A = 0; B = 0; CIN = 0; #10;
A = 0; B = 0; CIN = 1; #10;
A = 0; B = 1; CIN = 0; #10;
A = 0; B = 1; CIN = 1; #10;
A = 1; B = 0; CIN = 0; #10;
A = 1; B = 0; CIN = 1; #10;
A = 1; B = 1; CIN = 0; #10;
A = 1; B = 1; CIN = 1; #10;
end
endmodule | 0 |
3,833 | data/full_repos/permissive/107007139/Lab 3/blinky.v | 107,007,139 | blinky.v | v | 30 | 83 | [] | [] | [] | [(23, 29)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/blinky.v\n%Error: Exiting due to 3 error(s)\n' | 1,616 | module | module blinky(
input CLOCK,
output LED
);
assign LED = CLOCK;
endmodule | module blinky(
input CLOCK,
output LED
); |
assign LED = CLOCK;
endmodule | 0 |
3,834 | data/full_repos/permissive/107007139/Lab 3/my_dff.v | 107,007,139 | my_dff.v | v | 8 | 55 | [] | [] | [] | [(3, 7)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/my_dff.v\n%Error: Exiting due to 3 error(s)\n' | 1,617 | module | module my_dff(input DFF_CLOCK, input D, output reg Q);
always @ (posedge DFF_CLOCK) begin
Q <= D;
end
endmodule | module my_dff(input DFF_CLOCK, input D, output reg Q); |
always @ (posedge DFF_CLOCK) begin
Q <= D;
end
endmodule | 0 |
3,835 | data/full_repos/permissive/107007139/Lab 3/single_pulse.v | 107,007,139 | single_pulse.v | v | 19 | 60 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/single_pulse.v\n%Error: Exiting due to 3 error(s)\n' | 1,618 | module | module single_pulse(input CLOCK, input BUTTON, output OUT);
wire SLOW_CLOCK;
wire Q1;
wire Q2;
slow_clock my_clock(CLOCK, SLOW_CLOCK);
my_dff dff1(SLOW_CLOCK, BUTTON, Q1);
my_dff dff2(SLOW_CLOCK, Q1, Q2);
assign OUT = Q1 & ~Q2;
endmodule | module single_pulse(input CLOCK, input BUTTON, output OUT); |
wire SLOW_CLOCK;
wire Q1;
wire Q2;
slow_clock my_clock(CLOCK, SLOW_CLOCK);
my_dff dff1(SLOW_CLOCK, BUTTON, Q1);
my_dff dff2(SLOW_CLOCK, Q1, Q2);
assign OUT = Q1 & ~Q2;
endmodule | 0 |
3,836 | data/full_repos/permissive/107007139/Lab 3/single_pulse_counter.v | 107,007,139 | single_pulse_counter.v | v | 19 | 78 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/single_pulse_counter.v\n%Error: Exiting due to 3 error(s)\n' | 1,619 | module | module single_pulse_counter(input CLOCK, input BUTTON, output reg [7:0] OUT);
wire PULSE;
initial begin
OUT = 8'b0000_0000;
end
single_pulse my_pulse(CLOCK, BUTTON, PULSE);
always @ (posedge PULSE) begin
OUT <= OUT + 1;
end
endmodule | module single_pulse_counter(input CLOCK, input BUTTON, output reg [7:0] OUT); |
wire PULSE;
initial begin
OUT = 8'b0000_0000;
end
single_pulse my_pulse(CLOCK, BUTTON, PULSE);
always @ (posedge PULSE) begin
OUT <= OUT + 1;
end
endmodule | 0 |
3,837 | data/full_repos/permissive/107007139/Lab 3/slow_blinky_module.v | 107,007,139 | slow_blinky_module.v | v | 36 | 83 | [] | [] | [] | [(23, 35)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/slow_blinky_module.v\n%Error: Exiting due to 3 error(s)\n' | 1,620 | module | module slow_blinky_module(input CLOCK, output reg LED);
reg [3:0] COUNT = 4'b0000;
initial begin
LED = 0;
end
always @ (posedge CLOCK) begin
COUNT <= COUNT + 1;
LED <= (COUNT == 4'b0000) ? ~LED : LED;
end
endmodule | module slow_blinky_module(input CLOCK, output reg LED); |
reg [3:0] COUNT = 4'b0000;
initial begin
LED = 0;
end
always @ (posedge CLOCK) begin
COUNT <= COUNT + 1;
LED <= (COUNT == 4'b0000) ? ~LED : LED;
end
endmodule | 0 |
3,838 | data/full_repos/permissive/107007139/Lab 3/slow_clock.v | 107,007,139 | slow_clock.v | v | 19 | 79 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/slow_clock.v\n%Error: Exiting due to 3 error(s)\n' | 1,621 | module | module slow_clock(input CLOCK, output reg LED);
parameter N = 24;
reg [N - 1:0] COUNT = 1'b0;
initial begin
LED = 0;
end
always @ (posedge CLOCK) begin
COUNT <= COUNT + 1;
LED <= (COUNT == {N{1'b0}}) ? ~LED : LED;
end
endmodule | module slow_clock(input CLOCK, output reg LED); |
parameter N = 24;
reg [N - 1:0] COUNT = 1'b0;
initial begin
LED = 0;
end
always @ (posedge CLOCK) begin
COUNT <= COUNT + 1;
LED <= (COUNT == {N{1'b0}}) ? ~LED : LED;
end
endmodule | 0 |
3,839 | data/full_repos/permissive/107007139/Lab 3/test_single_pulse.v | 107,007,139 | test_single_pulse.v | v | 21 | 42 | [] | [] | [] | [(3, 20)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/test_single_pulse.v\n%Error: Exiting due to 3 error(s)\n' | 1,623 | module | module test_single_pulse();
reg CLOCK;
reg BUTTON;
wire OUT;
single_pulse dut(CLOCK, BUTTON, OUT);
initial begin
CLOCK = 0;
BUTTON = 0;
#22 BUTTON = ~BUTTON;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | module test_single_pulse(); |
reg CLOCK;
reg BUTTON;
wire OUT;
single_pulse dut(CLOCK, BUTTON, OUT);
initial begin
CLOCK = 0;
BUTTON = 0;
#22 BUTTON = ~BUTTON;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | 0 |
3,840 | data/full_repos/permissive/107007139/Lab 3/test_slow_blinky.v | 107,007,139 | test_slow_blinky.v | v | 17 | 40 | [] | [] | [] | [(3, 16)] | null | null | 1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/3,data/full_repos/permissive/107007139.sv\n 3,data/full_repos/permissive/107007139\n 3,data/full_repos/permissive/107007139.v\n 3,data/full_repos/permissive/107007139.sv\n obj_dir/3,data/full_repos/permissive/107007139\n obj_dir/3,data/full_repos/permissive/107007139.v\n obj_dir/3,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 3/test_slow_blinky.v\n%Error: Exiting due to 3 error(s)\n' | 1,624 | module | module test_slow_blinky();
reg CLOCK;
wire LED;
slow_blinky_module dut(CLOCK, LED);
initial begin
CLOCK = 0;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | module test_slow_blinky(); |
reg CLOCK;
wire LED;
slow_blinky_module dut(CLOCK, LED);
initial begin
CLOCK = 0;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | 0 |
3,841 | data/full_repos/permissive/107007139/Lab 4/black_box_file.v | 107,007,139 | black_box_file.v | v | 71 | 223 | [] | [] | [] | null | line:26: before: "," | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/black_box_file.v\n%Error: Exiting due to 3 error(s)\n' | 1,625 | module | module session_black_box (input box_input_1, input box_input_2, input [13:0] box_input_3, output reg [3:0] box_output_1, output reg [7:0] box_output_2, input box_input_4, box_input_5, box_input_6, input [2:0] box_input_7);
reg lock_display = 0;
reg [3:0] display_decimal = 0;
reg [13:0] internal_display_value = 0, locked_display_value = 0;
reg [31:0] edge_count = 0, edge_one_1 = 0, edge_two_1 = 0, edge_one_2 = 0, edge_two_2 = 0, edge_one_3 = 0, edge_two_3 = 0;
always @ (posedge box_input_1) begin edge_count <= edge_count + 1; end
always @ (posedge box_input_4) begin edge_one_1 <= edge_two_1; edge_two_1 <= edge_count; end
always @ (posedge box_input_5) begin edge_one_2 <= edge_two_2; edge_two_2 <= edge_count; end
always @ (posedge box_input_6) begin edge_one_3 <= edge_two_3; edge_two_3 <= edge_count; end
always @ (posedge box_input_2)
begin
case (box_input_7)
3'b001: internal_display_value <= ( 100000000 / (edge_two_1 - edge_one_1));
3'b010: internal_display_value <= ( 100000000 / (edge_two_2 - edge_one_2));
3'b011: internal_display_value <= ( 100000000 / (edge_two_3 - edge_one_3));
3'b111: begin lock_display <= 1; locked_display_value <= (locked_display_value == 0) ? box_input_3 : locked_display_value ; end
default: begin internal_display_value <= (lock_display == 1) ? locked_display_value : box_input_3; end
endcase
case (box_output_1)
4'b0111: begin box_output_1 <= 4'b1110; display_decimal <= (internal_display_value/1)%10; end
4'b1110: begin box_output_1 <= 4'b1101; display_decimal <= (internal_display_value/10)%10; end
4'b1101: begin box_output_1 <= 4'b1011; display_decimal <= (internal_display_value/100)%10; end
4'b1011: begin box_output_1 <= 4'b0111; display_decimal <= (internal_display_value/1000)%10; end
default: begin box_output_1 <= 4'b1110; display_decimal <= 4'hF; end
endcase
end
always @ (*)
begin
case (display_decimal)
4'd0 : box_output_2 <= 8'b11000000;
4'd1 : box_output_2 <= 8'b11111001;
4'd2 : box_output_2 <= 8'b10100100;
4'd3 : box_output_2 <= 8'b10110000;
4'd4 : box_output_2 <= 8'b10011001;
4'd5 : box_output_2 <= 8'b10010010;
4'd6 : box_output_2 <= 8'b10000010;
4'd7 : box_output_2 <= 8'b11111000;
4'd8 : box_output_2 <= 8'b10000000;
4'd9 : box_output_2 <= 8'b10010000;
default: box_output_2 <= 8'b01111111;
endcase
end
endmodule | module session_black_box (input box_input_1, input box_input_2, input [13:0] box_input_3, output reg [3:0] box_output_1, output reg [7:0] box_output_2, input box_input_4, box_input_5, box_input_6, input [2:0] box_input_7); |
reg lock_display = 0;
reg [3:0] display_decimal = 0;
reg [13:0] internal_display_value = 0, locked_display_value = 0;
reg [31:0] edge_count = 0, edge_one_1 = 0, edge_two_1 = 0, edge_one_2 = 0, edge_two_2 = 0, edge_one_3 = 0, edge_two_3 = 0;
always @ (posedge box_input_1) begin edge_count <= edge_count + 1; end
always @ (posedge box_input_4) begin edge_one_1 <= edge_two_1; edge_two_1 <= edge_count; end
always @ (posedge box_input_5) begin edge_one_2 <= edge_two_2; edge_two_2 <= edge_count; end
always @ (posedge box_input_6) begin edge_one_3 <= edge_two_3; edge_two_3 <= edge_count; end
always @ (posedge box_input_2)
begin
case (box_input_7)
3'b001: internal_display_value <= ( 100000000 / (edge_two_1 - edge_one_1));
3'b010: internal_display_value <= ( 100000000 / (edge_two_2 - edge_one_2));
3'b011: internal_display_value <= ( 100000000 / (edge_two_3 - edge_one_3));
3'b111: begin lock_display <= 1; locked_display_value <= (locked_display_value == 0) ? box_input_3 : locked_display_value ; end
default: begin internal_display_value <= (lock_display == 1) ? locked_display_value : box_input_3; end
endcase
case (box_output_1)
4'b0111: begin box_output_1 <= 4'b1110; display_decimal <= (internal_display_value/1)%10; end
4'b1110: begin box_output_1 <= 4'b1101; display_decimal <= (internal_display_value/10)%10; end
4'b1101: begin box_output_1 <= 4'b1011; display_decimal <= (internal_display_value/100)%10; end
4'b1011: begin box_output_1 <= 4'b0111; display_decimal <= (internal_display_value/1000)%10; end
default: begin box_output_1 <= 4'b1110; display_decimal <= 4'hF; end
endcase
end
always @ (*)
begin
case (display_decimal)
4'd0 : box_output_2 <= 8'b11000000;
4'd1 : box_output_2 <= 8'b11111001;
4'd2 : box_output_2 <= 8'b10100100;
4'd3 : box_output_2 <= 8'b10110000;
4'd4 : box_output_2 <= 8'b10011001;
4'd5 : box_output_2 <= 8'b10010010;
4'd6 : box_output_2 <= 8'b10000010;
4'd7 : box_output_2 <= 8'b11111000;
4'd8 : box_output_2 <= 8'b10000000;
4'd9 : box_output_2 <= 8'b10010000;
default: box_output_2 <= 8'b01111111;
endcase
end
endmodule | 0 |
3,842 | data/full_repos/permissive/107007139/Lab 4/lab_test_full_file.v | 107,007,139 | lab_test_full_file.v | v | 81 | 167 | [] | [] | [] | [(30, 80)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/lab_test_full_file.v\n%Error: Exiting due to 3 error(s)\n' | 1,626 | module | module lab_test_module(input clk, input [2:0] examiner_value, input session_pb,
output [3:0] link_with_box_output_1, output [7:0] link_with_box_output_2,
output reg [5:0] my_register_one);
wire [2:0] link_to_box_input_7;
assign link_to_box_input_7 = (session_pb == 1) ? 7 : examiner_value;
reg [13:0] my_register_two;
wire out1;
wire out2;
wire out3;
my_clock1 clock1(clk, out1);
my_clock2 clock2(clk, out2);
my_clock3 clock3(clk, out3);
wire pulse;
my_single_pulse single_pulse(out2, session_pb, pulse);
initial begin
my_register_one = 6'b100111;
my_register_two = 400;
end
always @(posedge pulse) begin
my_register_one <= my_register_one + 1;
end
always @(posedge out1) begin
my_register_two <= my_register_two + 1;
end
session_black_box black_box(clk, out3, my_register_two, link_with_box_output_1, link_with_box_output_2, out1, out2, out3, link_to_box_input_7);
endmodule | module lab_test_module(input clk, input [2:0] examiner_value, input session_pb,
output [3:0] link_with_box_output_1, output [7:0] link_with_box_output_2,
output reg [5:0] my_register_one); |
wire [2:0] link_to_box_input_7;
assign link_to_box_input_7 = (session_pb == 1) ? 7 : examiner_value;
reg [13:0] my_register_two;
wire out1;
wire out2;
wire out3;
my_clock1 clock1(clk, out1);
my_clock2 clock2(clk, out2);
my_clock3 clock3(clk, out3);
wire pulse;
my_single_pulse single_pulse(out2, session_pb, pulse);
initial begin
my_register_one = 6'b100111;
my_register_two = 400;
end
always @(posedge pulse) begin
my_register_one <= my_register_one + 1;
end
always @(posedge out1) begin
my_register_two <= my_register_two + 1;
end
session_black_box black_box(clk, out3, my_register_two, link_with_box_output_1, link_with_box_output_2, out1, out2, out3, link_to_box_input_7);
endmodule | 0 |
3,843 | data/full_repos/permissive/107007139/Lab 4/my_clock2.v | 107,007,139 | my_clock2.v | v | 19 | 83 | [] | [] | [] | [(7, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/my_clock2.v\n%Error: Exiting due to 3 error(s)\n' | 1,628 | module | module my_clock2(input CLOCK, output reg OUT);
reg [21:0] COUNT = 0;
initial begin
OUT = 0;
end
always @(posedge CLOCK) begin
COUNT <= COUNT + 1;
OUT <= (COUNT == 0) ? ~OUT : OUT;
end
endmodule | module my_clock2(input CLOCK, output reg OUT); |
reg [21:0] COUNT = 0;
initial begin
OUT = 0;
end
always @(posedge CLOCK) begin
COUNT <= COUNT + 1;
OUT <= (COUNT == 0) ? ~OUT : OUT;
end
endmodule | 0 |
3,844 | data/full_repos/permissive/107007139/Lab 4/my_dff.v | 107,007,139 | my_dff.v | v | 11 | 83 | [] | [] | [] | [(6, 10)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/my_dff.v\n%Error: Exiting due to 3 error(s)\n' | 1,630 | module | module my_dff(input CLOCK, input D, output reg OUT);
always @(posedge CLOCK) begin
OUT <= D;
end
endmodule | module my_dff(input CLOCK, input D, output reg OUT); |
always @(posedge CLOCK) begin
OUT <= D;
end
endmodule | 0 |
3,845 | data/full_repos/permissive/107007139/Lab 4/my_single_pulse.v | 107,007,139 | my_single_pulse.v | v | 16 | 83 | [] | [] | [] | [(6, 15)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/my_single_pulse.v\n%Error: Exiting due to 3 error(s)\n' | 1,631 | module | module my_single_pulse(input CLOCK, input BUTTON, output OUT);
wire Q1;
wire Q2;
my_dff dff1(CLOCK, BUTTON, Q1);
my_dff dff2(CLOCK, Q1, Q2);
assign OUT = Q1 & ~Q2;
endmodule | module my_single_pulse(input CLOCK, input BUTTON, output OUT); |
wire Q1;
wire Q2;
my_dff dff1(CLOCK, BUTTON, Q1);
my_dff dff2(CLOCK, Q1, Q2);
assign OUT = Q1 & ~Q2;
endmodule | 0 |
3,846 | data/full_repos/permissive/107007139/Lab 4/test_clock1.v | 107,007,139 | test_clock1.v | v | 18 | 34 | [] | [] | [] | [(3, 17)] | null | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n ... Looked in:\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n 4,data/full_repos/permissive/107007139\n 4,data/full_repos/permissive/107007139.v\n 4,data/full_repos/permissive/107007139.sv\n obj_dir/4,data/full_repos/permissive/107007139\n obj_dir/4,data/full_repos/permissive/107007139.v\n obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/test_clock1.v\n%Error: Exiting due to 3 error(s)\n' | 1,632 | module | module test_clock1();
reg CLOCK;
wire OUT;
my_clock1 clock1(CLOCK, OUT);
initial begin
CLOCK = 0;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | module test_clock1(); |
reg CLOCK;
wire OUT;
my_clock1 clock1(CLOCK, OUT);
initial begin
CLOCK = 0;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule | 0 |
3,847 | data/full_repos/permissive/107007139/Project/binary_to_bcd_converter.v | 107,007,139 | binary_to_bcd_converter.v | v | 45 | 93 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa3 in position 60: invalid start byte | data/verilator_xmls/c558ddb4-5d7d-41da-bf1a-acf220cf409d.xml | null | 1,634 | module | module binary_to_bcd_converter(
input [12:0] binary,
output reg [3:0] thousands,
output reg [3:0] hundreds,
output reg [3:0] tens,
output reg [3:0] ones);
integer i;
always @(binary) begin
thousands = 4'd0;
hundreds = 4'd0;
tens = 4'd0;
ones = 4'd0;
for (i = 12; i >= 0; i = i - 1) begin
if (thousands >= 5)
thousands = thousands + 3;
if (hundreds >= 5)
hundreds = hundreds + 3;
if (tens >= 5)
tens = tens + 3;
if (ones >= 5)
ones = ones + 3;
thousands = thousands << 1;
thousands[0] = hundreds[3];
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = binary[i];
end
end
endmodule | module binary_to_bcd_converter(
input [12:0] binary,
output reg [3:0] thousands,
output reg [3:0] hundreds,
output reg [3:0] tens,
output reg [3:0] ones); |
integer i;
always @(binary) begin
thousands = 4'd0;
hundreds = 4'd0;
tens = 4'd0;
ones = 4'd0;
for (i = 12; i >= 0; i = i - 1) begin
if (thousands >= 5)
thousands = thousands + 3;
if (hundreds >= 5)
hundreds = hundreds + 3;
if (tens >= 5)
tens = tens + 3;
if (ones >= 5)
ones = ones + 3;
thousands = thousands << 1;
thousands[0] = hundreds[3];
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = binary[i];
end
end
endmodule | 0 |
3,848 | data/full_repos/permissive/107007139/Project/clock_generator.v | 107,007,139 | clock_generator.v | v | 54 | 83 | [] | [] | [] | [(23, 53)] | null | data/verilator_xmls/9885533b-aa39-419a-9ef1-d8ac65a0e917.xml | null | 1,635 | module | module clock_generator(
input CLK,
output reg clk_20k,
output reg clk_50M,
output reg clk_4
);
reg [11:0] count = 12'd0;
reg [19:0] count_4 = 20'b0;
initial begin
clk_20k <= 1'b0;
clk_50M <= 1'b0;
clk_4 <= 1'b0;
end
always @(posedge CLK) begin
clk_50M <= ~clk_50M;
end
always @(posedge CLK) begin
count <= (count == 2499) ? 0 : count + 1;
clk_20k <= (count == 0) ? ~ clk_20k : clk_20k;
end
always @(posedge CLK) begin
count_4 <= count_4 + 1;
clk_4 <= (count_4 == 0) ? ~ clk_4 : clk_4;
end
endmodule | module clock_generator(
input CLK,
output reg clk_20k,
output reg clk_50M,
output reg clk_4
); |
reg [11:0] count = 12'd0;
reg [19:0] count_4 = 20'b0;
initial begin
clk_20k <= 1'b0;
clk_50M <= 1'b0;
clk_4 <= 1'b0;
end
always @(posedge CLK) begin
clk_50M <= ~clk_50M;
end
always @(posedge CLK) begin
count <= (count == 2499) ? 0 : count + 1;
clk_20k <= (count == 0) ? ~ clk_20k : clk_20k;
end
always @(posedge CLK) begin
count_4 <= count_4 + 1;
clk_4 <= (count_4 == 0) ? ~ clk_4 : clk_4;
end
endmodule | 0 |
3,849 | data/full_repos/permissive/107007139/Project/delay_voice.v | 107,007,139 | delay_voice.v | v | 49 | 83 | [] | [] | [] | [(23, 48)] | null | data/verilator_xmls/f6f25526-58c4-4e8c-a511-59872c89e7e6.xml | null | 1,636 | module | module delay_voice(
input wire clk_20k,
input wire [11:0] in_voice,
output wire [11:0] out_voice
);
parameter MEM_SIZE = 5000;
reg [11:0] memory [0:MEM_SIZE-1];
reg [12:0] i;
initial begin
for (i = 0 ; i < MEM_SIZE ; i = i + 1) begin
memory[i] <= 12'b0111_1111_1111;
end
end
always @(posedge clk_20k) begin
memory[0] <= in_voice;
for (i = 0 ; i < MEM_SIZE - 1 ; i = i + 1) begin
memory[i+1] <= memory[i];
end
end
assign out_voice = memory[MEM_SIZE-1];
endmodule | module delay_voice(
input wire clk_20k,
input wire [11:0] in_voice,
output wire [11:0] out_voice
); |
parameter MEM_SIZE = 5000;
reg [11:0] memory [0:MEM_SIZE-1];
reg [12:0] i;
initial begin
for (i = 0 ; i < MEM_SIZE ; i = i + 1) begin
memory[i] <= 12'b0111_1111_1111;
end
end
always @(posedge clk_20k) begin
memory[0] <= in_voice;
for (i = 0 ; i < MEM_SIZE - 1 ; i = i + 1) begin
memory[i+1] <= memory[i];
end
end
assign out_voice = memory[MEM_SIZE-1];
endmodule | 0 |
3,850 | data/full_repos/permissive/107007139/Project/display_controller.v | 107,007,139 | display_controller.v | v | 72 | 80 | [] | [] | [] | [(3, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/107007139/Project/display_controller.v:15: Cannot find file containing module: 'binary_to_bcd_converter'\n binary_to_bcd_converter converter(number, thousands, hundreds, tens, ones);\n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/binary_to_bcd_converter\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/binary_to_bcd_converter.v\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/binary_to_bcd_converter.sv\n binary_to_bcd_converter\n binary_to_bcd_converter.v\n binary_to_bcd_converter.sv\n obj_dir/binary_to_bcd_converter\n obj_dir/binary_to_bcd_converter.v\n obj_dir/binary_to_bcd_converter.sv\n%Error: Exiting due to 1 error(s)\n" | 1,637 | module | module display_controller(
input [12:0] number,
input clk_20k,
output reg [7:0] seg,
output reg [3:0] digit
);
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
binary_to_bcd_converter converter(number, thousands, hundreds, tens, ones);
reg [3:0] current_display;
initial begin
digit <= 4'b1110;
current_display <= ones;
end
always @(posedge clk_20k) begin
case (digit)
4'b1110: begin
digit <= 4'b1101;
current_display <= tens;
end
4'b1101: begin
digit <= 4'b1011;
current_display <= hundreds;
end
4'b1011: begin
digit <= 4'b0111;
current_display <= thousands;
end
4'b0111: begin
digit <= 4'b1110;
current_display <= ones;
end
default: begin
digit <= 4'b1110;
current_display <= 4'hF;
end
endcase
end
always @(*) begin
case (current_display)
4'd0: seg <= 8'b11000000;
4'd1: seg <= 8'b11111001;
4'd2: seg <= 8'b10100100;
4'd3: seg <= 8'b10110000;
4'd4: seg <= 8'b10011001;
4'd5: seg <= 8'b10010010;
4'd6: seg <= 8'b10000010;
4'd7: seg <= 8'b11111000;
4'd8: seg <= 8'b10000000;
4'd9: seg <= 8'b10010000;
default: seg <= 8'b01111111;
endcase
end
endmodule | module display_controller(
input [12:0] number,
input clk_20k,
output reg [7:0] seg,
output reg [3:0] digit
); |
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
binary_to_bcd_converter converter(number, thousands, hundreds, tens, ones);
reg [3:0] current_display;
initial begin
digit <= 4'b1110;
current_display <= ones;
end
always @(posedge clk_20k) begin
case (digit)
4'b1110: begin
digit <= 4'b1101;
current_display <= tens;
end
4'b1101: begin
digit <= 4'b1011;
current_display <= hundreds;
end
4'b1011: begin
digit <= 4'b0111;
current_display <= thousands;
end
4'b0111: begin
digit <= 4'b1110;
current_display <= ones;
end
default: begin
digit <= 4'b1110;
current_display <= 4'hF;
end
endcase
end
always @(*) begin
case (current_display)
4'd0: seg <= 8'b11000000;
4'd1: seg <= 8'b11111001;
4'd2: seg <= 8'b10100100;
4'd3: seg <= 8'b10110000;
4'd4: seg <= 8'b10011001;
4'd5: seg <= 8'b10010010;
4'd6: seg <= 8'b10000010;
4'd7: seg <= 8'b11111000;
4'd8: seg <= 8'b10000000;
4'd9: seg <= 8'b10010000;
default: seg <= 8'b01111111;
endcase
end
endmodule | 0 |
3,851 | data/full_repos/permissive/107007139/Project/display_demo_top.v | 107,007,139 | display_demo_top.v | v | 16 | 74 | [] | [] | [] | [(3, 15)] | null | null | 1: b"%Error: data/full_repos/permissive/107007139/Project/display_demo_top.v:14: Cannot find file containing module: 'display_controller'\n display_controller display(number, clk_20k, seg, digit);\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/display_controller\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/display_controller.v\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/display_controller.sv\n display_controller\n display_controller.v\n display_controller.sv\n obj_dir/display_controller\n obj_dir/display_controller.v\n obj_dir/display_controller.sv\n%Error: Exiting due to 1 error(s)\n" | 1,638 | module | module display_demo_top(input CLK, output [7:0] seg, output [3:0] digit);
reg [12:0] number = 4085;
reg [11:0] count = 12'd0;
reg clk_20k;
always @(posedge CLK) begin
count <= (count == 2499) ? 0 : count + 1;
clk_20k <= (count == 0) ? ~ clk_20k : clk_20k;
end
display_controller display(number, clk_20k, seg, digit);
endmodule | module display_demo_top(input CLK, output [7:0] seg, output [3:0] digit); |
reg [12:0] number = 4085;
reg [11:0] count = 12'd0;
reg clk_20k;
always @(posedge CLK) begin
count <= (count == 2499) ? 0 : count + 1;
clk_20k <= (count == 0) ? ~ clk_20k : clk_20k;
end
display_controller display(number, clk_20k, seg, digit);
endmodule | 0 |
3,852 | data/full_repos/permissive/107007139/Project/hello_playback.v | 107,007,139 | hello_playback.v | v | 48 | 83 | [] | [] | [] | [(23, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/107007139/Project/hello_playback.v:32: Cannot find file containing module: 'hello_data'\n hello_data memory(index_pointer, value);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/hello_data\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/hello_data.v\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/hello_data.sv\n hello_data\n hello_data.v\n hello_data.sv\n obj_dir/hello_data\n obj_dir/hello_data.v\n obj_dir/hello_data.sv\n%Error: data/full_repos/permissive/107007139/Project/hello_playback.v:37: Cannot find file containing module: 'pulse_detector'\n pulse_detector my_pulse(clk_4, pause_button, pulse_result);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,639 | module | module hello_playback(
input clk_20k,
input clk_4,
input pause_button,
output reg [11:0] out
);
reg [12:0] index_pointer = 0;
wire [11:0] value;
hello_data memory(index_pointer, value);
wire pulse_result;
reg continue_or_not = 1;
pulse_detector my_pulse(clk_4, pause_button, pulse_result);
always @(posedge pulse_result) begin
continue_or_not <= ~continue_or_not;
end
always @(posedge clk_20k) begin
index_pointer <= continue_or_not ? index_pointer + 1 : index_pointer;
out <= continue_or_not ? value : {12{1'b0}};
end
endmodule | module hello_playback(
input clk_20k,
input clk_4,
input pause_button,
output reg [11:0] out
); |
reg [12:0] index_pointer = 0;
wire [11:0] value;
hello_data memory(index_pointer, value);
wire pulse_result;
reg continue_or_not = 1;
pulse_detector my_pulse(clk_4, pause_button, pulse_result);
always @(posedge pulse_result) begin
continue_or_not <= ~continue_or_not;
end
always @(posedge clk_20k) begin
index_pointer <= continue_or_not ? index_pointer + 1 : index_pointer;
out <= continue_or_not ? value : {12{1'b0}};
end
endmodule | 0 |
3,853 | data/full_repos/permissive/107007139/Project/mic_in_latch.v | 107,007,139 | mic_in_latch.v | v | 15 | 36 | [] | [] | [] | [(3, 14)] | null | data/verilator_xmls/92e0ca50-06da-46b3-9c72-0c5488d9f222.xml | null | 1,640 | module | module mic_in_latch(
input wire clk_20k,
input wire [11:0] mic_in,
output reg [11:0] led_out,
output reg [11:0] speaker_out
);
always @(posedge clk_20k) begin
led_out <= mic_in;
speaker_out <= mic_in;
end
endmodule | module mic_in_latch(
input wire clk_20k,
input wire [11:0] mic_in,
output reg [11:0] led_out,
output reg [11:0] speaker_out
); |
always @(posedge clk_20k) begin
led_out <= mic_in;
speaker_out <= mic_in;
end
endmodule | 0 |
3,854 | data/full_repos/permissive/107007139/Project/music_node_selector.v | 107,007,139 | music_node_selector.v | v | 40 | 84 | [] | [] | [] | [(23, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/107007139/Project/music_node_selector.v:35: Cannot find file containing module: 'square_node_generator'\n square_node_generator square_node(clk, node_select, square_out);\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/square_node_generator\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/square_node_generator.v\n data/full_repos/permissive/107007139/Project,data/full_repos/permissive/107007139/square_node_generator.sv\n square_node_generator\n square_node_generator.v\n square_node_generator.sv\n obj_dir/square_node_generator\n obj_dir/square_node_generator.v\n obj_dir/square_node_generator.sv\n%Error: data/full_repos/permissive/107007139/Project/music_node_selector.v:36: Cannot find file containing module: 'triangle_node_generator'\n triangle_node_generator triangle_node(clk, node_select, triangle_out);\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,641 | module | module music_node_selector(
input clk,
input [5:0] select,
output [11:0] out
);
wire [4:0] node_select;
wire [11:0] square_out;
wire [11:0] triangle_out;
assign node_select = { select[4], select[3], select[2], select[1], select[0] };
square_node_generator square_node(clk, node_select, square_out);
triangle_node_generator triangle_node(clk, node_select, triangle_out);
assign out = select[5] ? triangle_out : square_out;
endmodule | module music_node_selector(
input clk,
input [5:0] select,
output [11:0] out
); |
wire [4:0] node_select;
wire [11:0] square_out;
wire [11:0] triangle_out;
assign node_select = { select[4], select[3], select[2], select[1], select[0] };
square_node_generator square_node(clk, node_select, square_out);
triangle_node_generator triangle_node(clk, node_select, triangle_out);
assign out = select[5] ? triangle_out : square_out;
endmodule | 0 |
3,855 | data/full_repos/permissive/107007139/Project/pulse_detector.v | 107,007,139 | pulse_detector.v | v | 43 | 83 | [] | [] | [] | [(23, 42)] | null | data/verilator_xmls/94c249d4-3c7e-4fcc-8901-784daab4a32a.xml | null | 1,642 | module | module pulse_detector(
input wire clk_4,
input wire btn_signal,
output wire out
);
reg Q1, Q2;
initial begin
Q1 = 1'b0;
Q2 = 1'b0;
end
always @(posedge clk_4) begin
Q1 <= btn_signal;
Q2 <= Q1;
end
assign out = Q1 & ~Q2;
endmodule | module pulse_detector(
input wire clk_4,
input wire btn_signal,
output wire out
); |
reg Q1, Q2;
initial begin
Q1 = 1'b0;
Q2 = 1'b0;
end
always @(posedge clk_4) begin
Q1 <= btn_signal;
Q2 <= Q1;
end
assign out = Q1 & ~Q2;
endmodule | 0 |
3,856 | data/full_repos/permissive/107007139/Project/SPI.v | 107,007,139 | SPI.v | v | 52 | 589 | [] | [] | [] | [(20, 52)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107007139/Project/SPI.v:45: Operator OR expects 16 bits on the RHS, but RHS\'s VARREF \'MISO\' generates 1 bits.\n : ... In instance SPI\n temp <= temp<<1 | MISO;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,643 | module | module SPI(
input CLK,
input cs,
input MISO,
output clk_samp,
output reg sclk,
output reg [11:0]sample
);
reg [11:0]count2 = 0;
reg [15:0]temp = 0;
initial begin
sclk = 0;
end
assign clk_samp = cs;
always @ (posedge CLK) begin
count2 <= (cs == 0) ? count2 + 1 : 0;
sclk <= (count2 == 50 || count2 == 100 || count2 == 150 || count2 == 200 || count2 == 250 || count2 == 300 || count2 == 350 || count2 == 400 || count2 == 450 || count2 == 500 || count2 == 550 || count2 == 600 || count2 == 650 || count2 == 700 || count2 == 750 || count2 == 800 || count2 == 850 || count2 == 900 || count2 == 950 || count2 == 1000 ||count2 == 1050 || count2 == 1100 || count2 == 1150 || count2 == 1200 || count2 == 1250 || count2 == 1300 || count2 == 1350 || count2 == 1400 || count2 == 1450 || count2 == 1500 || count2 == 1550 || count2 == 1600) ? ~sclk : sclk ;
end
always @ (negedge sclk) begin
temp <= temp<<1 | MISO;
end
always @ (posedge cs) begin
sample <= temp[11:0];
end
endmodule | module SPI(
input CLK,
input cs,
input MISO,
output clk_samp,
output reg sclk,
output reg [11:0]sample
); |
reg [11:0]count2 = 0;
reg [15:0]temp = 0;
initial begin
sclk = 0;
end
assign clk_samp = cs;
always @ (posedge CLK) begin
count2 <= (cs == 0) ? count2 + 1 : 0;
sclk <= (count2 == 50 || count2 == 100 || count2 == 150 || count2 == 200 || count2 == 250 || count2 == 300 || count2 == 350 || count2 == 400 || count2 == 450 || count2 == 500 || count2 == 550 || count2 == 600 || count2 == 650 || count2 == 700 || count2 == 750 || count2 == 800 || count2 == 850 || count2 == 900 || count2 == 950 || count2 == 1000 ||count2 == 1050 || count2 == 1100 || count2 == 1150 || count2 == 1200 || count2 == 1250 || count2 == 1300 || count2 == 1350 || count2 == 1400 || count2 == 1450 || count2 == 1500 || count2 == 1550 || count2 == 1600) ? ~sclk : sclk ;
end
always @ (negedge sclk) begin
temp <= temp<<1 | MISO;
end
always @ (posedge cs) begin
sample <= temp[11:0];
end
endmodule | 0 |
3,857 | data/full_repos/permissive/107007139/Project/square_node_generator.v | 107,007,139 | square_node_generator.v | v | 60 | 104 | [] | [] | [] | [(24, 59)] | null | data/verilator_xmls/ae5648e6-6916-4ab4-ba11-ee2b2b305d34.xml | null | 1,644 | module | module square_node_generator(
input clk,
input [4:0] select,
output reg [11:0] out
);
reg [17:0] doi = 190839;
reg [17:0] re = 170067;
reg [17:0] mi = 151514;
reg [17:0] fa = 143265;
reg [17:0] so = 127550;
wire [17:0] count_until;
assign count_until = select[0] ? doi
: (select[1] ? re
: (select[2] ? mi
: (select[3] ? fa
: so)));
reg [17:0] count = 0;
reg slow_clock = 0;
always @(posedge clk) begin
count <= (count == count_until) ? 0 : count + 1;
slow_clock <= (select == 0) ? 1'bz
: ((count == 0) ? ~slow_clock
: slow_clock);
out = {12{slow_clock}};
end
endmodule | module square_node_generator(
input clk,
input [4:0] select,
output reg [11:0] out
); |
reg [17:0] doi = 190839;
reg [17:0] re = 170067;
reg [17:0] mi = 151514;
reg [17:0] fa = 143265;
reg [17:0] so = 127550;
wire [17:0] count_until;
assign count_until = select[0] ? doi
: (select[1] ? re
: (select[2] ? mi
: (select[3] ? fa
: so)));
reg [17:0] count = 0;
reg slow_clock = 0;
always @(posedge clk) begin
count <= (count == count_until) ? 0 : count + 1;
slow_clock <= (select == 0) ? 1'bz
: ((count == 0) ? ~slow_clock
: slow_clock);
out = {12{slow_clock}};
end
endmodule | 0 |
3,858 | data/full_repos/permissive/107007139/Project/triangle_node_generator.v | 107,007,139 | triangle_node_generator.v | v | 75 | 103 | [] | [] | [] | [(24, 74)] | null | data/verilator_xmls/f41087f9-0659-4fc6-b225-5df25a87bdcd.xml | null | 1,645 | module | module triangle_node_generator(
input clk,
input [4:0] select,
output reg [11:0] out
);
parameter doi_inc = 23;
parameter re_inc = 21;
parameter mi_inc = 18;
parameter fa_inc = 17;
parameter so_inc = 16;
parameter max_out = 4095;
wire [7:0] increment_until;
assign increment_until = select[0] ? doi_inc
: (select[1] ? re_inc
: (select[2] ? mi_inc
: (select[3] ? fa_inc : so_inc)));
reg [7:0] increment_count = 0;
reg increase_or_decrease = 1;
initial begin
out = 1;
end
always @(posedge clk) begin
increment_count = (increment_count == increment_until) ? 0 : increment_count + 1;
increase_or_decrease = (out == 0) ? 1
: ((out == max_out) ? 0 : increase_or_decrease);
if (select == 0) begin
out = {12{1'b0}};
end else begin
out = (increment_count == 0) ? (increase_or_decrease ? out + 1 : out - 1)
: out;
end
end
endmodule | module triangle_node_generator(
input clk,
input [4:0] select,
output reg [11:0] out
); |
parameter doi_inc = 23;
parameter re_inc = 21;
parameter mi_inc = 18;
parameter fa_inc = 17;
parameter so_inc = 16;
parameter max_out = 4095;
wire [7:0] increment_until;
assign increment_until = select[0] ? doi_inc
: (select[1] ? re_inc
: (select[2] ? mi_inc
: (select[3] ? fa_inc : so_inc)));
reg [7:0] increment_count = 0;
reg increase_or_decrease = 1;
initial begin
out = 1;
end
always @(posedge clk) begin
increment_count = (increment_count == increment_until) ? 0 : increment_count + 1;
increase_or_decrease = (out == 0) ? 1
: ((out == max_out) ? 0 : increase_or_decrease);
if (select == 0) begin
out = {12{1'b0}};
end else begin
out = (increment_count == 0) ? (increase_or_decrease ? out + 1 : out - 1)
: out;
end
end
endmodule | 0 |
3,859 | data/full_repos/permissive/107007139/Project/volume_indicator.v | 107,007,139 | volume_indicator.v | v | 33 | 58 | [] | [] | [] | [(4, 32)] | null | data/verilator_xmls/af0a49c1-59e6-4f94-9b4f-ca765522ac2e.xml | null | 1,646 | module | module volume_indicator(
input wire clk_20k,
input wire [11:0] MIC_IN,
output reg [11:0] led
);
parameter SAMPLE = 1000;
reg [11:0] peak_value = 12'b0;
reg [4:0] temp_value;
reg [3:0] after_divide;
reg [11:0] counter = 12'b0;
always @(posedge clk_20k) begin
if (MIC_IN > peak_value) begin
peak_value = MIC_IN;
end
counter <= (counter == SAMPLE) ? 0 : counter + 1;
if (counter == SAMPLE) begin
led <= peak_value;
peak_value <= 0;
end
end
endmodule | module volume_indicator(
input wire clk_20k,
input wire [11:0] MIC_IN,
output reg [11:0] led
); |
parameter SAMPLE = 1000;
reg [11:0] peak_value = 12'b0;
reg [4:0] temp_value;
reg [3:0] after_divide;
reg [11:0] counter = 12'b0;
always @(posedge clk_20k) begin
if (MIC_IN > peak_value) begin
peak_value = MIC_IN;
end
counter <= (counter == SAMPLE) ? 0 : counter + 1;
if (counter == SAMPLE) begin
led <= peak_value;
peak_value <= 0;
end
end
endmodule | 0 |
3,861 | data/full_repos/permissive/107057345/7 Seg Display/Basys3_Abacus_Top.v | 107,057,345 | Basys3_Abacus_Top.v | v | 357 | 230 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: Display/Basys3_Abacus_Top.v\n%Error: Exiting due to 4 error(s)\n' | 1,648 | module | module Basys3_Abacus_Top(
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp
);
reg [15:0] x;
wire [7:0] sum;
wire [7:0] diff;
wire cout;
reg [15:0] B;
wire[19:0] bcdout;
reg [15:0] B1;
wire[19:0] bcdout1;
reg [15:0] B2;
wire[19:0] bcdout2;
wire [19:0] scroll_datain;
wire [15:0] scroll_dataout;
wire [19:0] scroll_datain_QU;
wire [15:0] scroll_dataout_QU;
wire [19:0] scroll_datain_REM;
wire [15:0] scroll_dataout_REM;
wire [7:0] QU;
wire [7:0] REM;
wire [15:0] Product;
wire [7:0] PP0;
wire [7:0] PP1;
wire [7:0] PP2;
wire [7:0] PP3;
wire [21:0] p_temp;
wire [7:0] zero_diff;
wire [7:0] twoC_diff;
wire clr_seg;
assign clr_seg = btnU | btnD | btnC;
wire clr_seg_DIV;
assign clr_seg_DIV = btnR | btnL;
assign zero_diff[7:0] = diff[7:0];
assign twoC_diff[7:0] = ((~(zero_diff[7:0])) +8'b00000001);
assign p_temp[3:0] = PP0[3:0];
assign Product[3:0] = p_temp[3:0];
assign p_temp[9:4] = PP0[7:4]+PP1[3:0]+PP2[3:0];
assign Product[7:4] = p_temp[7:4];
assign p_temp[15:10] = PP1[7:4] + PP2[7:4] + PP3[3:0]+ {2'b00, p_temp[9:8]} ;
assign Product[11:8] = p_temp[13:10];
assign p_temp[21:16] = PP3[7:4] + {2'b00,p_temp[15:14]};
assign Product[15:12] = p_temp[19:16];
assign led[15:0] = sw[15:0];
always @(*) begin
if ( (btnU == 1) && (sw[15:8] <= sw[7:0]))
begin
B = twoC_diff[7:0];
x[15:12] = 'hA;
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if ( (btnU == 1) && (sw[15:8] >= sw[7:0] ))
begin
B = diff[7:0];
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if (btnD == 1) begin
B = Product[15:0];
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if (btnR == 1) begin
B1 = QU[7:0];
x[15:12] = scroll_dataout_QU[15:12];
x[11:8] = scroll_dataout_QU[11:8];
x[7:4] = scroll_dataout_QU[7:4];
x[3:0] = scroll_dataout_QU[3:0];
end
else if (btnL == 1) begin
B2 = REM[7:0];
x[15:12] = scroll_dataout_REM[15:12];
x[11:8] = scroll_dataout_REM[11:8];
x[7:4] = scroll_dataout_REM[7:4];
x[3:0] = scroll_dataout_REM[3:0];
end
else
begin
B = {cout, sum[7:0]};
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
end
bin_to_decimal u1 (
.B(B),
.bcdout(bcdout)
);
BIN_DEC1 u2 (
.B1(B1),
.bcdout1(bcdout1)
);
BIN_DEC2 u3 (
.B2(B2),
.bcdout2(bcdout2)
);
seg_scroll u4(
.clk(clk),
.clr(clr_seg),
.scroll_datain(bcdout),
.scroll_dataout(scroll_dataout)
);
Seg_Scroll_QU u5(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_QU(bcdout1),
.scroll_dataout_QU(scroll_dataout_QU)
);
Seg_Scroll_REM u6(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_REM(bcdout2),
.scroll_dataout_REM(scroll_dataout_REM)
);
seg7decimal u7 (
.x(x),
.clk(clk),
.clr(btnC),
.a_to_g(seg),
.an(an),
.dp(dp)
);
adder u8 (
.clk(clk),
.a(sw[15:8]),
.b(sw[7:0]),
.sum(sum),
.diff(diff),
.cout(cout),
.cin(btnU)
);
multi_4_4_pp0 u9 (
.clk(clk),
.A0_3(sw[11:8]),
.B0_3(sw[3:0]),
.pp0(PP0)
);
multi_4_4_pp1 u10 (
.clk(clk),
.A4_7(sw[15:12]),
.B0_3(sw[3:0]),
.pp1(PP1)
);
multi_4_4_pp2 u11 (
.clk(clk),
.A0_3(sw[11:8]),
.B4_7(sw[7:4]),
.pp2(PP2)
);
multi_4_4_pp3 u12 (
.clk(clk),
.A4_7(sw[15:12]),
.B4_7(sw[7:4]),
.pp3(PP3)
);
divider u13(
.clk(clk),
.div(sw[15:8]),
.dvr(sw[7:0]),
.quotient(QU),
.remainder(REM)
);
endmodule | module Basys3_Abacus_Top(
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp
); |
reg [15:0] x;
wire [7:0] sum;
wire [7:0] diff;
wire cout;
reg [15:0] B;
wire[19:0] bcdout;
reg [15:0] B1;
wire[19:0] bcdout1;
reg [15:0] B2;
wire[19:0] bcdout2;
wire [19:0] scroll_datain;
wire [15:0] scroll_dataout;
wire [19:0] scroll_datain_QU;
wire [15:0] scroll_dataout_QU;
wire [19:0] scroll_datain_REM;
wire [15:0] scroll_dataout_REM;
wire [7:0] QU;
wire [7:0] REM;
wire [15:0] Product;
wire [7:0] PP0;
wire [7:0] PP1;
wire [7:0] PP2;
wire [7:0] PP3;
wire [21:0] p_temp;
wire [7:0] zero_diff;
wire [7:0] twoC_diff;
wire clr_seg;
assign clr_seg = btnU | btnD | btnC;
wire clr_seg_DIV;
assign clr_seg_DIV = btnR | btnL;
assign zero_diff[7:0] = diff[7:0];
assign twoC_diff[7:0] = ((~(zero_diff[7:0])) +8'b00000001);
assign p_temp[3:0] = PP0[3:0];
assign Product[3:0] = p_temp[3:0];
assign p_temp[9:4] = PP0[7:4]+PP1[3:0]+PP2[3:0];
assign Product[7:4] = p_temp[7:4];
assign p_temp[15:10] = PP1[7:4] + PP2[7:4] + PP3[3:0]+ {2'b00, p_temp[9:8]} ;
assign Product[11:8] = p_temp[13:10];
assign p_temp[21:16] = PP3[7:4] + {2'b00,p_temp[15:14]};
assign Product[15:12] = p_temp[19:16];
assign led[15:0] = sw[15:0];
always @(*) begin
if ( (btnU == 1) && (sw[15:8] <= sw[7:0]))
begin
B = twoC_diff[7:0];
x[15:12] = 'hA;
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if ( (btnU == 1) && (sw[15:8] >= sw[7:0] ))
begin
B = diff[7:0];
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if (btnD == 1) begin
B = Product[15:0];
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
else if (btnR == 1) begin
B1 = QU[7:0];
x[15:12] = scroll_dataout_QU[15:12];
x[11:8] = scroll_dataout_QU[11:8];
x[7:4] = scroll_dataout_QU[7:4];
x[3:0] = scroll_dataout_QU[3:0];
end
else if (btnL == 1) begin
B2 = REM[7:0];
x[15:12] = scroll_dataout_REM[15:12];
x[11:8] = scroll_dataout_REM[11:8];
x[7:4] = scroll_dataout_REM[7:4];
x[3:0] = scroll_dataout_REM[3:0];
end
else
begin
B = {cout, sum[7:0]};
x[15:12] = scroll_dataout[15:12];
x[11:8] = scroll_dataout[11:8];
x[7:4] = scroll_dataout[7:4];
x[3:0] = scroll_dataout[3:0];
end
end
bin_to_decimal u1 (
.B(B),
.bcdout(bcdout)
);
BIN_DEC1 u2 (
.B1(B1),
.bcdout1(bcdout1)
);
BIN_DEC2 u3 (
.B2(B2),
.bcdout2(bcdout2)
);
seg_scroll u4(
.clk(clk),
.clr(clr_seg),
.scroll_datain(bcdout),
.scroll_dataout(scroll_dataout)
);
Seg_Scroll_QU u5(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_QU(bcdout1),
.scroll_dataout_QU(scroll_dataout_QU)
);
Seg_Scroll_REM u6(
.clk(clk),
.clr(clr_seg_DIV),
.scroll_datain_REM(bcdout2),
.scroll_dataout_REM(scroll_dataout_REM)
);
seg7decimal u7 (
.x(x),
.clk(clk),
.clr(btnC),
.a_to_g(seg),
.an(an),
.dp(dp)
);
adder u8 (
.clk(clk),
.a(sw[15:8]),
.b(sw[7:0]),
.sum(sum),
.diff(diff),
.cout(cout),
.cin(btnU)
);
multi_4_4_pp0 u9 (
.clk(clk),
.A0_3(sw[11:8]),
.B0_3(sw[3:0]),
.pp0(PP0)
);
multi_4_4_pp1 u10 (
.clk(clk),
.A4_7(sw[15:12]),
.B0_3(sw[3:0]),
.pp1(PP1)
);
multi_4_4_pp2 u11 (
.clk(clk),
.A0_3(sw[11:8]),
.B4_7(sw[7:4]),
.pp2(PP2)
);
multi_4_4_pp3 u12 (
.clk(clk),
.A4_7(sw[15:12]),
.B4_7(sw[7:4]),
.pp3(PP3)
);
divider u13(
.clk(clk),
.div(sw[15:8]),
.dvr(sw[7:0]),
.quotient(QU),
.remainder(REM)
);
endmodule | 0 |
3,862 | data/full_repos/permissive/107057345/7 Seg Display/Seg_7_Display.v | 107,057,345 | Seg_7_Display.v | v | 102 | 93 | [] | [] | [] | [(21, 101)] | null | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: Display/Seg_7_Display.v\n%Error: Exiting due to 4 error(s)\n' | 1,649 | module | module seg7decimal(
input [15:0] x,
input clk,
input clr,
output reg [6:0] a_to_g,
output reg [3:0] an,
output wire dp
);
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:18];
assign aen = 4'b1111;
always @(posedge clk)
case(s)
0:digit = x[3:0];
1:digit = x[7:4];
2:digit = x[11:8];
3:digit = x[15:12];
default:digit = x[3:0];
endcase
always @(*)
case(digit)
0:a_to_g = 7'b1000000;
1:a_to_g = 7'b1111001;
2:a_to_g = 7'b0100100;
3:a_to_g = 7'b0110000;
4:a_to_g = 7'b0011001;
5:a_to_g = 7'b0010010;
6:a_to_g = 7'b0000010;
7:a_to_g = 7'b1111000;
8:a_to_g = 7'b0000000;
9:a_to_g = 7'b0010000;
'hA:a_to_g = 7'b0111111;
'hB:a_to_g = 7'b1111111;
'hC:a_to_g = 7'b1110111;
default: a_to_g = 7'b0000000;
endcase
always @(*)begin
an=4'b1111;
if(aen[s] == 1)
an[s] = 0;
end
always @(posedge clk or posedge clr) begin
if ( clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv+1;
end
endmodule | module seg7decimal(
input [15:0] x,
input clk,
input clr,
output reg [6:0] a_to_g,
output reg [3:0] an,
output wire dp
); |
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:18];
assign aen = 4'b1111;
always @(posedge clk)
case(s)
0:digit = x[3:0];
1:digit = x[7:4];
2:digit = x[11:8];
3:digit = x[15:12];
default:digit = x[3:0];
endcase
always @(*)
case(digit)
0:a_to_g = 7'b1000000;
1:a_to_g = 7'b1111001;
2:a_to_g = 7'b0100100;
3:a_to_g = 7'b0110000;
4:a_to_g = 7'b0011001;
5:a_to_g = 7'b0010010;
6:a_to_g = 7'b0000010;
7:a_to_g = 7'b1111000;
8:a_to_g = 7'b0000000;
9:a_to_g = 7'b0010000;
'hA:a_to_g = 7'b0111111;
'hB:a_to_g = 7'b1111111;
'hC:a_to_g = 7'b1110111;
default: a_to_g = 7'b0000000;
endcase
always @(*)begin
an=4'b1111;
if(aen[s] == 1)
an[s] = 0;
end
always @(posedge clk or posedge clr) begin
if ( clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv+1;
end
endmodule | 0 |
3,863 | data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v | 107,057,345 | dassign2.v | v | 244 | 74 | [] | [] | [] | [(7, 44), (46, 139), (141, 192), (194, 242)] | null | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n' | 1,650 | module | module deciadd (digInA, digInB, sub, cin, digOut, cout);
parameter dlen=3;
input [dlen:0] digInA, digInB;
input sub, cin;
output [dlen:0] digOut;
output cout;
reg [dlen:0] digOut;
reg cout;
reg[dlen + 1:0] S;
reg[dlen:0] A, B;
always @(sub or cin or digInA or digInB)
begin
A = digInA;
if(sub)
B = 4'b1001 - digInB;
else
B = digInB;
S = A + B + cin;
digOut = (S < 5'b01010) ? S : S - 4'b1010;
cout = (S < 5'b01010) ? 1'b0 : 1'b1;
end
endmodule | module deciadd (digInA, digInB, sub, cin, digOut, cout); |
parameter dlen=3;
input [dlen:0] digInA, digInB;
input sub, cin;
output [dlen:0] digOut;
output cout;
reg [dlen:0] digOut;
reg cout;
reg[dlen + 1:0] S;
reg[dlen:0] A, B;
always @(sub or cin or digInA or digInB)
begin
A = digInA;
if(sub)
B = 4'b1001 - digInB;
else
B = digInB;
S = A + B + cin;
digOut = (S < 5'b01010) ? S : S - 4'b1010;
cout = (S < 5'b01010) ? 1'b0 : 1'b1;
end
endmodule | 0 |
3,864 | data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v | 107,057,345 | dassign2.v | v | 244 | 74 | [] | [] | [] | [(7, 44), (46, 139), (141, 192), (194, 242)] | null | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n' | 1,650 | module | module dassign2 (
wdinA, wdinB, sub, wdout, ovunflow);
parameter wlen=15;
parameter dlen=3;
input [wlen:0] wdinA;
input [wlen:0] wdinB;
input sub;
output [wlen:0] wdout;
output ovunflow;
reg [wlen:0] out;
wire [dlen:0] d1inA, d2inA, d3inA, d4inA;
wire [dlen:0] d1inB, d2inB, d3inB, d4inB;
wire [dlen:0] d1out, d2out, d3out, d4out;
reg cin;
wire cout1,cout2,cout3,cout4;
assign {d4inA,d3inA,d2inA,d1inA} = wdinA;
assign {d4inB,d3inB,d2inB,d1inB} = wdinB;
assign wdout = {d4out,d3out,d2out,d1out};
deciadd dig1(d1inA, d1inB, sub, cin, d1out, cout1);
deciadd dig2(d2inA, d2inB, sub, cout1, d2out, cout2);
deciadd dig3(d3inA, d3inB, sub, cout2, d3out, cout3);
deciadd dig4(d4inA, d4inB, sub, cout3, d4out, cout4);
reg ovunflow;
reg firstpos, secpos, respos;
reg[3:0] signs;
always @(sub or cin or cout4 or cout3 or d4inA or d4inB or d4out) begin
begin
if(sub)
cin = 1'b1;
else
cin = 1'b0;
end
if(d4inA < 4'b0101)
firstpos = 1'b1;
else
firstpos = 1'b0;
if(d4inB < 4'b0101)
secpos = 1'b1;
else
secpos = 1'b0;
if(d4out < 4'b0101)
respos = 1'b1;
else
respos = 1'b0;
signs = {sub, firstpos, secpos, respos};
case(signs)
4'b0110:
ovunflow = 1'b1;
4'b0001:
ovunflow = 1'b1;
4'b1100:
ovunflow = 1'b1;
4'b1011:
ovunflow = 1'b1;
default:
ovunflow = 1'b0;
endcase
end
endmodule | module dassign2 (
wdinA, wdinB, sub, wdout, ovunflow); |
parameter wlen=15;
parameter dlen=3;
input [wlen:0] wdinA;
input [wlen:0] wdinB;
input sub;
output [wlen:0] wdout;
output ovunflow;
reg [wlen:0] out;
wire [dlen:0] d1inA, d2inA, d3inA, d4inA;
wire [dlen:0] d1inB, d2inB, d3inB, d4inB;
wire [dlen:0] d1out, d2out, d3out, d4out;
reg cin;
wire cout1,cout2,cout3,cout4;
assign {d4inA,d3inA,d2inA,d1inA} = wdinA;
assign {d4inB,d3inB,d2inB,d1inB} = wdinB;
assign wdout = {d4out,d3out,d2out,d1out};
deciadd dig1(d1inA, d1inB, sub, cin, d1out, cout1);
deciadd dig2(d2inA, d2inB, sub, cout1, d2out, cout2);
deciadd dig3(d3inA, d3inB, sub, cout2, d3out, cout3);
deciadd dig4(d4inA, d4inB, sub, cout3, d4out, cout4);
reg ovunflow;
reg firstpos, secpos, respos;
reg[3:0] signs;
always @(sub or cin or cout4 or cout3 or d4inA or d4inB or d4out) begin
begin
if(sub)
cin = 1'b1;
else
cin = 1'b0;
end
if(d4inA < 4'b0101)
firstpos = 1'b1;
else
firstpos = 1'b0;
if(d4inB < 4'b0101)
secpos = 1'b1;
else
secpos = 1'b0;
if(d4out < 4'b0101)
respos = 1'b1;
else
respos = 1'b0;
signs = {sub, firstpos, secpos, respos};
case(signs)
4'b0110:
ovunflow = 1'b1;
4'b0001:
ovunflow = 1'b1;
4'b1100:
ovunflow = 1'b1;
4'b1011:
ovunflow = 1'b1;
default:
ovunflow = 1'b0;
endcase
end
endmodule | 0 |
3,865 | data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v | 107,057,345 | dassign2.v | v | 244 | 74 | [] | [] | [] | [(7, 44), (46, 139), (141, 192), (194, 242)] | null | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n' | 1,650 | module | module Top(
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output led,
output [6:0] seg,
output [3:0] an,
output dp
);
wire [15:0] x;
Buttons u1(
.sw(sw),
.left(btnL),
.right(btnR),
.up(btnU),
.down(btnD),
.x(x),
.led(led)
);
seg7decimal u3 (
.x(x),
.clk(clk),
.clr(btnC),
.a_to_g(seg),
.an(an),
.dp(dp)
);
endmodule | module Top(
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output led,
output [6:0] seg,
output [3:0] an,
output dp
); |
wire [15:0] x;
Buttons u1(
.sw(sw),
.left(btnL),
.right(btnR),
.up(btnU),
.down(btnD),
.x(x),
.led(led)
);
seg7decimal u3 (
.x(x),
.clk(clk),
.clr(btnC),
.a_to_g(seg),
.an(an),
.dp(dp)
);
endmodule | 0 |
3,866 | data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v | 107,057,345 | dassign2.v | v | 244 | 74 | [] | [] | [] | [(7, 44), (46, 139), (141, 192), (194, 242)] | null | null | 1: b'%Error: Cannot find file containing module: Seg\n ... Looked in:\n data/full_repos/permissive/107057345/7/Seg\n data/full_repos/permissive/107057345/7/Seg.v\n data/full_repos/permissive/107057345/7/Seg.sv\n Seg\n Seg.v\n Seg.sv\n obj_dir/Seg\n obj_dir/Seg.v\n obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n' | 1,650 | module | module Buttons(input [15:0] sw,
input left,
input right,
input up,
input down,
output[15:0] x,
output led
);
reg sub;
reg[15:0] wdinA, wdinB;
wire[15:0] inputA, inputB;
wire subt;
assign inputA = wdinA;
assign inputB = wdinB;
assign subt = sub;
dassign2 u2(
.wdinA(inputA),
.wdinB(inputB),
.sub(subt),
.wdout(x),
.ovunflow(led)
);
always @(left or right or up or down or sw) begin
if(left == 1)
begin
wdinA = sw;
end
else if (right == 1)
begin
wdinB = sw;
end
else if(down == 1)
begin
sub = 1;
end
else if(up == 1)
begin
sub = 0;
end
else
begin
wdinA = wdinA;
wdinB = wdinB;
end
end
endmodule | module Buttons(input [15:0] sw,
input left,
input right,
input up,
input down,
output[15:0] x,
output led
); |
reg sub;
reg[15:0] wdinA, wdinB;
wire[15:0] inputA, inputB;
wire subt;
assign inputA = wdinA;
assign inputB = wdinB;
assign subt = sub;
dassign2 u2(
.wdinA(inputA),
.wdinB(inputB),
.sub(subt),
.wdout(x),
.ovunflow(led)
);
always @(left or right or up or down or sw) begin
if(left == 1)
begin
wdinA = sw;
end
else if (right == 1)
begin
wdinB = sw;
end
else if(down == 1)
begin
sub = 1;
end
else if(up == 1)
begin
sub = 0;
end
else
begin
wdinA = wdinA;
wdinB = wdinB;
end
end
endmodule | 0 |
3,867 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module inverter(y,a);
output y;
input a;
assign y = ~a;
endmodule | module inverter(y,a); |
output y;
input a;
assign y = ~a;
endmodule | 0 |
3,868 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module nand2(y,a,b);
output y;
input a,b;
wire c;
assign c = ~(a & b);
assign y = c;
endmodule | module nand2(y,a,b); |
output y;
input a,b;
wire c;
assign c = ~(a & b);
assign y = c;
endmodule | 0 |
3,869 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module nand3(y,a,b,c);
output y;
input a,b,c;
wire d;
assign d = ~(a & b & c);
assign y = d;
endmodule | module nand3(y,a,b,c); |
output y;
input a,b,c;
wire d;
assign d = ~(a & b & c);
assign y = d;
endmodule | 0 |
3,870 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module nor2(y,a,b);
output y;
input a,b;
wire c;
assign c = ~(a | b);
assign y = c;
endmodule | module nor2(y,a,b); |
output y;
input a,b;
wire c;
assign c = ~(a | b);
assign y = c;
endmodule | 0 |
3,871 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module nor3(y,a,b,c);
output y;
input a,b,c;
wire d;
assign d = ~(a | b | c);
assign y = d;
endmodule | module nor3(y,a,b,c); |
output y;
input a,b,c;
wire d;
assign d = ~(a | b | c);
assign y = d;
endmodule | 0 |
3,872 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module mux2(y,a,b,sel);
input sel;
input a, b;
output y;
reg y;
always @ (sel or a or b)
begin
if(sel) y = a;
else y = b;
end
endmodule | module mux2(y,a,b,sel); |
input sel;
input a, b;
output y;
reg y;
always @ (sel or a or b)
begin
if(sel) y = a;
else y = b;
end
endmodule | 0 |
3,873 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module xor2(y,a,b);
input a, b;
output y;
wire c = a | b;
wire d = ~a | ~b;
assign y = c & d;
endmodule | module xor2(y,a,b); |
input a, b;
output y;
wire c = a | b;
wire d = ~a | ~b;
assign y = c & d;
endmodule | 0 |
3,874 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_1.v | 107,057,345 | dassign1_1.v | v | 73 | 37 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_1.v\n%Error: Exiting due to 5 error(s)\n' | 1,652 | module | module dassign1_1 (y,a,b,c,d,e,f,g);
output y;
input a,b,c,d,e,f,g;
wire y1, y2, y3, y4, y5, y6;
nand3 one(y1, a, b, c);
nand2 two(y2, y1, d);
nand2 three(y3, f, g);
nor2 four(y4, e, y3);
nor2 five(y5, y2, y4);
nor2 six(y6, y5, y5);
assign y = y6;
endmodule | module dassign1_1 (y,a,b,c,d,e,f,g); |
output y;
input a,b,c,d,e,f,g;
wire y1, y2, y3, y4, y5, y6;
nand3 one(y1, a, b, c);
nand2 two(y2, y1, d);
nand2 three(y3, f, g);
nor2 four(y4, e, y3);
nor2 five(y5, y2, y4);
nor2 six(y6, y5, y5);
assign y = y6;
endmodule | 0 |
3,875 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_2.v | 107,057,345 | dassign1_2.v | v | 11 | 74 | [] | [] | [] | [(4, 11)] | null | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_2.v\n%Error: Exiting due to 5 error(s)\n' | 1,653 | module | module dassign1_2 (y,z,a,b,c,d,e);
output y,z;
input a,b,c,d,e;
assign y = (~b | c);
assign z = ((a & b & ~c) | ~(a & ~(~b&c)) | ~(~d|e) & c);
endmodule | module dassign1_2 (y,z,a,b,c,d,e); |
output y,z;
input a,b,c,d,e;
assign y = (~b | c);
assign z = ((a & b & ~c) | ~(a & ~(~b&c)) | ~(~d|e) & c);
endmodule | 0 |
3,876 | data/full_repos/permissive/107057345/LED and Boolean Algebra/dassign1_3.v | 107,057,345 | dassign1_3.v | v | 28 | 37 | [] | [] | [] | null | line:10: before: "assign" | null | 1: b'%Error: Cannot find file containing module: and\n ... Looked in:\n data/full_repos/permissive/107057345/LED/and\n data/full_repos/permissive/107057345/LED/and.v\n data/full_repos/permissive/107057345/LED/and.sv\n and\n and.v\n and.sv\n obj_dir/and\n obj_dir/and.v\n obj_dir/and.sv\n%Error: Cannot find file containing module: Boolean\n%Error: Cannot find file containing module: Algebra,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/LED\n%Error: Cannot find file containing module: Algebra/dassign1_3.v\n%Error: Exiting due to 5 error(s)\n' | 1,654 | module | module dassign1_3(y,x);
output y;
input [3:0] x;
reg y;
always @(x) begin
case(x)
4'b0000: assign y = 0;
4'b0001: assign y = 0;
4'b0010: assign y = 0;
4'b0011: assign y = 1;
4'b0100: assign y = 0;
4'b0101: assign y = 0;
4'b0110: assign y = 1;
4'b0111: assign y = 1;
4'b1000: assign y = 0;
4'b1001: assign y = 1;
4'b1010: assign y = 1;
4'b1011: assign y = 1;
4'b1100: assign y = 0;
4'b1101: assign y = 0;
4'b1110: assign y = 0;
4'b1111: assign y = 0;
endcase
end
endmodule | module dassign1_3(y,x); |
output y;
input [3:0] x;
reg y;
always @(x) begin
case(x)
4'b0000: assign y = 0;
4'b0001: assign y = 0;
4'b0010: assign y = 0;
4'b0011: assign y = 1;
4'b0100: assign y = 0;
4'b0101: assign y = 0;
4'b0110: assign y = 1;
4'b0111: assign y = 1;
4'b1000: assign y = 0;
4'b1001: assign y = 1;
4'b1010: assign y = 1;
4'b1011: assign y = 1;
4'b1100: assign y = 0;
4'b1101: assign y = 0;
4'b1110: assign y = 0;
4'b1111: assign y = 0;
endcase
end
endmodule | 0 |
3,877 | data/full_repos/permissive/107057345/Morse Encoder/led_fsm.v | 107,057,345 | led_fsm.v | v | 89 | 65 | [] | [] | [] | [(4, 87)] | null | null | 1: b'%Error: Cannot find file containing module: Encoder,data/full_repos/permissive/107057345\n ... Looked in:\n data/full_repos/permissive/107057345/Morse/Encoder,data/full_repos/permissive/107057345\n data/full_repos/permissive/107057345/Morse/Encoder,data/full_repos/permissive/107057345.v\n data/full_repos/permissive/107057345/Morse/Encoder,data/full_repos/permissive/107057345.sv\n Encoder,data/full_repos/permissive/107057345\n Encoder,data/full_repos/permissive/107057345.v\n Encoder,data/full_repos/permissive/107057345.sv\n obj_dir/Encoder,data/full_repos/permissive/107057345\n obj_dir/Encoder,data/full_repos/permissive/107057345.v\n obj_dir/Encoder,data/full_repos/permissive/107057345.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/Morse\n%Error: Cannot find file containing module: Encoder/led_fsm.v\n%Error: Exiting due to 3 error(s)\n' | 1,657 | module | module led_fsm(
input sym_strt, symbol,
output led_drv, sym_done,
input reset, clock
);
parameter START=3'b000;
parameter DASH0 = 3'b001;
parameter DASH1 = 3'b010;
parameter DASH2 = 3'b011;
parameter DOT = 3'b100;
reg [2:0] led_st;
always @(posedge clock) begin
led_st <= led_nx_st;
end
reg [2:0] led_nx_st;
reg led_drv, sym_done;
always @(*) begin
if (reset) begin
led_nx_st = START;
end
else begin
case (led_st)
START: begin
if(~sym_strt) begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b0;
end
else begin
if(symbol) begin
led_nx_st = DASH0;
led_drv = 1'b1;
sym_done = 1'b0;
end
else begin
led_nx_st = DOT;
led_drv = 1'b1;
sym_done = 1'b0;
end
end
end
DASH0: begin
led_nx_st = DASH1;
led_drv = 1'b1;
sym_done = 1'b0;
end
DASH1: begin
led_nx_st = DASH2;
led_drv = 1'b1;
sym_done = 1'b0;
end
DASH2: begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b1;
end
DOT: begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b1;
end
default: begin
end
endcase
end
end
endmodule | module led_fsm(
input sym_strt, symbol,
output led_drv, sym_done,
input reset, clock
); |
parameter START=3'b000;
parameter DASH0 = 3'b001;
parameter DASH1 = 3'b010;
parameter DASH2 = 3'b011;
parameter DOT = 3'b100;
reg [2:0] led_st;
always @(posedge clock) begin
led_st <= led_nx_st;
end
reg [2:0] led_nx_st;
reg led_drv, sym_done;
always @(*) begin
if (reset) begin
led_nx_st = START;
end
else begin
case (led_st)
START: begin
if(~sym_strt) begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b0;
end
else begin
if(symbol) begin
led_nx_st = DASH0;
led_drv = 1'b1;
sym_done = 1'b0;
end
else begin
led_nx_st = DOT;
led_drv = 1'b1;
sym_done = 1'b0;
end
end
end
DASH0: begin
led_nx_st = DASH1;
led_drv = 1'b1;
sym_done = 1'b0;
end
DASH1: begin
led_nx_st = DASH2;
led_drv = 1'b1;
sym_done = 1'b0;
end
DASH2: begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b1;
end
DOT: begin
led_nx_st = START;
led_drv = 1'b0;
sym_done = 1'b1;
end
default: begin
end
endcase
end
end
endmodule | 0 |
3,878 | data/full_repos/permissive/107057345/Morse Encoder Synthesized/Design Project 3 synthesis.srcs/sources_1/imports/Design 3/code_reg.v | 107,057,345 | code_reg.v | v | 67 | 68 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: Cannot find file containing module: Encoder\n ... Looked in:\n data/full_repos/permissive/107057345/Morse/Encoder\n data/full_repos/permissive/107057345/Morse/Encoder.v\n data/full_repos/permissive/107057345/Morse/Encoder.sv\n Encoder\n Encoder.v\n Encoder.sv\n obj_dir/Encoder\n obj_dir/Encoder.v\n obj_dir/Encoder.sv\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Project\n%Error: Cannot find file containing module: 3\n%Error: Cannot find file containing module: synthesis.srcs/sources_1/imports/Design\n%Error: Cannot find file containing module: 3,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/Morse\n%Error: Cannot find file containing module: 3/code_reg.v\n%Error: Exiting due to 8 error(s)\n' | 1,658 | module | module code_reg(
input [7:0] charcode_data,
input [3:0] charlen_data,
input char_load, shft_cnt,
output [3:0] cntr_data,
output shft_data,
input reset, clock
);
reg [7:0] shftr_o, shftr_i;
reg [3:0] cntr_o, cntr_i;
always @(posedge clock) begin
shftr_o <= shftr_i;
cntr_o <= cntr_i;
end
wire shft_data;
wire [3:0] cntr_data;
always @(*) begin
if (reset) begin
shftr_i = 8'b00000000;
cntr_i = 4'b0000;
end
else begin
if (char_load) begin
if(charlen_data == 4'b0000) begin
cntr_i = 4'b0111;
shftr_i = charcode_data;
end
else begin
shftr_i = charcode_data;
cntr_i = charlen_data;
end
end
else begin
if (shft_cnt) begin
if(cntr_o == 4'b0000) begin
cntr_i = cntr_o;
shftr_i = shftr_o;
end
else begin
shftr_i = shftr_o << 1;
cntr_i = cntr_o - 4'b0001;
end
end
else begin
if(charlen_data == 4'b0000) begin
cntr_i = cntr_o - 4'b0001;
end
else begin
shftr_i = shftr_o;
cntr_i = cntr_o;
end
end
end
end
end
assign cntr_data = cntr_o;
assign shft_data = shftr_o[7];
endmodule | module code_reg(
input [7:0] charcode_data,
input [3:0] charlen_data,
input char_load, shft_cnt,
output [3:0] cntr_data,
output shft_data,
input reset, clock
); |
reg [7:0] shftr_o, shftr_i;
reg [3:0] cntr_o, cntr_i;
always @(posedge clock) begin
shftr_o <= shftr_i;
cntr_o <= cntr_i;
end
wire shft_data;
wire [3:0] cntr_data;
always @(*) begin
if (reset) begin
shftr_i = 8'b00000000;
cntr_i = 4'b0000;
end
else begin
if (char_load) begin
if(charlen_data == 4'b0000) begin
cntr_i = 4'b0111;
shftr_i = charcode_data;
end
else begin
shftr_i = charcode_data;
cntr_i = charlen_data;
end
end
else begin
if (shft_cnt) begin
if(cntr_o == 4'b0000) begin
cntr_i = cntr_o;
shftr_i = shftr_o;
end
else begin
shftr_i = shftr_o << 1;
cntr_i = cntr_o - 4'b0001;
end
end
else begin
if(charlen_data == 4'b0000) begin
cntr_i = cntr_o - 4'b0001;
end
else begin
shftr_i = shftr_o;
cntr_i = cntr_o;
end
end
end
end
end
assign cntr_data = cntr_o;
assign shft_data = shftr_o[7];
endmodule | 0 |
3,879 | data/full_repos/permissive/107434030/src/freq_est.v | 107,434,030 | freq_est.v | v | 46 | 71 | [] | [] | [] | null | line:46: before: "/" | data/verilator_xmls/3bd53e1c-d726-4dd3-b52c-c6f91c31fb6c.xml | null | 1,661 | module | module freq_est(
input clk, RESETn,
input stop,
input signed [3:0] signal,
output reg valid,
output reg [9:0] counter_result
);
reg last_sign;
reg [9:0] counter;
reg [10:0] time_counter;
wire counter_rst;
wire counter_rst_posedge;
wire stop_negedge;
reg last_counter_rst;
reg last_stop;
assign counter_rst = time_counter == 11'd1599;
assign counter_rst_posedge = counter_rst && !last_counter_rst;
assign stop_negedge = !stop && last_stop;
always @(posedge clk) begin
if(~RESETn) begin
last_sign <= 0;
time_counter <= 11'b0;
counter <= 10'b0;
counter_result <= 10'b0;
valid <= 0;
last_stop <= 0;
end else begin
last_sign <= signal[3] & !stop;
time_counter <= (counter_rst | stop) ? 11'b0 : time_counter + 1;
counter <= (counter_rst | stop) ? 10'b0 :
last_sign ^ signal[3] ? counter + 1 :
counter;
counter_result <= (counter_rst & !stop) ? counter : counter_result;
last_counter_rst <= counter_rst;
last_stop <= stop;
valid <= stop_negedge ? 0 : (valid || counter_rst_posedge);
end
end
endmodule | module freq_est(
input clk, RESETn,
input stop,
input signed [3:0] signal,
output reg valid,
output reg [9:0] counter_result
); |
reg last_sign;
reg [9:0] counter;
reg [10:0] time_counter;
wire counter_rst;
wire counter_rst_posedge;
wire stop_negedge;
reg last_counter_rst;
reg last_stop;
assign counter_rst = time_counter == 11'd1599;
assign counter_rst_posedge = counter_rst && !last_counter_rst;
assign stop_negedge = !stop && last_stop;
always @(posedge clk) begin
if(~RESETn) begin
last_sign <= 0;
time_counter <= 11'b0;
counter <= 10'b0;
counter_result <= 10'b0;
valid <= 0;
last_stop <= 0;
end else begin
last_sign <= signal[3] & !stop;
time_counter <= (counter_rst | stop) ? 11'b0 : time_counter + 1;
counter <= (counter_rst | stop) ? 10'b0 :
last_sign ^ signal[3] ? counter + 1 :
counter;
counter_result <= (counter_rst & !stop) ? counter : counter_result;
last_counter_rst <= counter_rst;
last_stop <= stop;
valid <= stop_negedge ? 0 : (valid || counter_rst_posedge);
end
end
endmodule | 0 |
3,880 | data/full_repos/permissive/107434030/src/freq_est_testbench.v | 107,434,030 | freq_est_testbench.v | v | 61 | 48 | [] | [] | [] | null | line:61: before: "/" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #(clk_period_half);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #(clk_period);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #(clk_period*7);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n #(clk_period);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #(clk_period);\n ^\n%Error: data/full_repos/permissive/107434030/src/freq_est_testbench.v:23: Cannot find file containing module: \'freq_est\'\n freq_est DUT(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est\n data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est.v\n data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est.sv\n freq_est\n freq_est.v\n freq_est.sv\n obj_dir/freq_est\n obj_dir/freq_est.v\n obj_dir/freq_est.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,662 | module | module freq_est_testbench();
localparam clk_period = 0.0625;
localparam clk_period_half = 0.03125;
integer sample_count;
reg clk_16MHz, RESETn;
reg stop;
reg signed [3:0] signal;
wire valid;
wire [9:0] counter_result;
reg [3:0] signal_thread [0:9999];
always begin : clock_toggle_16MHz
#(clk_period_half);
clk_16MHz = ~clk_16MHz;
end
freq_est DUT(
.clk (clk_16MHz),
.RESETn (RESETn),
.stop (stop),
.signal (signal),
.valid (valid),
.counter_result(counter_result)
);
initial begin : run_sim
$readmemh("signal.dat", signal_thread);
signal = signal_thread[0] - 4'd8;
sample_count = 0;
clk_16MHz = 1;
RESETn = 0;
stop = 0;
#(clk_period);
#(clk_period*7);
RESETn = 1;
#(clk_period);
while (sample_count < 10000) begin
signal = signal_thread[sample_count] - 4'd8;
sample_count = sample_count + 1;
#(clk_period);
if(sample_count == 5000)
stop = 1;
if(sample_count == 5100)
stop = 0;
end
stop = 1;
end
endmodule | module freq_est_testbench(); |
localparam clk_period = 0.0625;
localparam clk_period_half = 0.03125;
integer sample_count;
reg clk_16MHz, RESETn;
reg stop;
reg signed [3:0] signal;
wire valid;
wire [9:0] counter_result;
reg [3:0] signal_thread [0:9999];
always begin : clock_toggle_16MHz
#(clk_period_half);
clk_16MHz = ~clk_16MHz;
end
freq_est DUT(
.clk (clk_16MHz),
.RESETn (RESETn),
.stop (stop),
.signal (signal),
.valid (valid),
.counter_result(counter_result)
);
initial begin : run_sim
$readmemh("signal.dat", signal_thread);
signal = signal_thread[0] - 4'd8;
sample_count = 0;
clk_16MHz = 1;
RESETn = 0;
stop = 0;
#(clk_period);
#(clk_period*7);
RESETn = 1;
#(clk_period);
while (sample_count < 10000) begin
signal = signal_thread[sample_count] - 4'd8;
sample_count = sample_count + 1;
#(clk_period);
if(sample_count == 5000)
stop = 1;
if(sample_count == 5100)
stop = 0;
end
stop = 1;
end
endmodule | 0 |
3,881 | data/full_repos/permissive/107499099/ex1/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 56 | 93 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex1/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,663 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000000c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408050;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfff8;
10'h009: data = 32'hafbe0000;
10'h00a: data = 32'h03a0f021;
10'h00b: data = 32'h24020300;
10'h00c: data = 32'hac400000;
10'h00d: data = 32'h24030304;
10'h00e: data = 32'h24020002;
10'h00f: data = 32'hac620000;
10'h010: data = 32'h24030300;
10'h011: data = 32'h24020001;
10'h012: data = 32'hac620000;
10'h013: data = 32'h03c0e821;
10'h014: data = 32'h8fbe0000;
10'h015: data = 32'h27bd0008;
10'h016: data = 32'h03e00008;
10'h017: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000000c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408050;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfff8;
10'h009: data = 32'hafbe0000;
10'h00a: data = 32'h03a0f021;
10'h00b: data = 32'h24020300;
10'h00c: data = 32'hac400000;
10'h00d: data = 32'h24030304;
10'h00e: data = 32'h24020002;
10'h00f: data = 32'hac620000;
10'h010: data = 32'h24030300;
10'h011: data = 32'h24020001;
10'h012: data = 32'hac620000;
10'h013: data = 32'h03c0e821;
10'h014: data = 32'h8fbe0000;
10'h015: data = 32'h27bd0008;
10'h016: data = 32'h03e00008;
10'h017: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,882 | data/full_repos/permissive/107499099/ex2/sltiu_lw_bne/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 72 | 96 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex2/sltiu_lw_bne/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,664 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000000c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408090;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfff0;
10'h009: data = 32'hafbe0008;
10'h00a: data = 32'h03a0f021;
10'h00b: data = 32'hafc00000;
10'h00c: data = 32'h0810001b;
10'h00d: data = 32'h00000000;
10'h00e: data = 32'h24020300;
10'h00f: data = 32'hac400000;
10'h010: data = 32'h24030304;
10'h011: data = 32'h8fc20000;
10'h012: data = 32'h00000000;
10'h013: data = 32'hac620000;
10'h014: data = 32'h24030300;
10'h015: data = 32'h24020001;
10'h016: data = 32'hac620000;
10'h017: data = 32'h8fc20000;
10'h018: data = 32'h00000000;
10'h019: data = 32'h24420001;
10'h01a: data = 32'hafc20000;
10'h01b: data = 32'h8fc20000;
10'h01c: data = 32'h00000000;
10'h01d: data = 32'h2c42003d;
10'h01e: data = 32'h1440ffef;
10'h01f: data = 32'h00000000;
10'h020: data = 32'h03c0e821;
10'h021: data = 32'h8fbe0008;
10'h022: data = 32'h27bd0010;
10'h023: data = 32'h03e00008;
10'h024: data = 32'h00000000;
10'h025: data = 32'h00000000;
10'h026: data = 32'h00000000;
10'h027: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000000c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408090;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfff0;
10'h009: data = 32'hafbe0008;
10'h00a: data = 32'h03a0f021;
10'h00b: data = 32'hafc00000;
10'h00c: data = 32'h0810001b;
10'h00d: data = 32'h00000000;
10'h00e: data = 32'h24020300;
10'h00f: data = 32'hac400000;
10'h010: data = 32'h24030304;
10'h011: data = 32'h8fc20000;
10'h012: data = 32'h00000000;
10'h013: data = 32'hac620000;
10'h014: data = 32'h24030300;
10'h015: data = 32'h24020001;
10'h016: data = 32'hac620000;
10'h017: data = 32'h8fc20000;
10'h018: data = 32'h00000000;
10'h019: data = 32'h24420001;
10'h01a: data = 32'hafc20000;
10'h01b: data = 32'h8fc20000;
10'h01c: data = 32'h00000000;
10'h01d: data = 32'h2c42003d;
10'h01e: data = 32'h1440ffef;
10'h01f: data = 32'h00000000;
10'h020: data = 32'h03c0e821;
10'h021: data = 32'h8fbe0008;
10'h022: data = 32'h27bd0010;
10'h023: data = 32'h03e00008;
10'h024: data = 32'h00000000;
10'h025: data = 32'h00000000;
10'h026: data = 32'h00000000;
10'h027: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,883 | data/full_repos/permissive/107499099/ex3/my_print/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 280 | 99 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex3/my_print/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,665 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h004083d0;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfee8;
10'h009: data = 32'hafbf0114;
10'h00a: data = 32'hafbe0110;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20010;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc20014;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20018;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc2001c;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20020;
10'h016: data = 32'h24020021;
10'h017: data = 32'hafc20024;
10'h018: data = 32'h24020021;
10'h019: data = 32'hafc20028;
10'h01a: data = 32'hafc0002c;
10'h01b: data = 32'h27c20010;
10'h01c: data = 32'h00402021;
10'h01d: data = 32'h0c100028;
10'h01e: data = 32'h00000000;
10'h01f: data = 32'h24020042;
10'h020: data = 32'hafc20010;
10'h021: data = 32'hafc00014;
10'h022: data = 32'h03c0e821;
10'h023: data = 32'h8fbf0114;
10'h024: data = 32'h8fbe0110;
10'h025: data = 32'h27bd0118;
10'h026: data = 32'h03e00008;
10'h027: data = 32'h00000000;
10'h028: data = 32'h27bdfff8;
10'h029: data = 32'hafbe0000;
10'h02a: data = 32'h03a0f021;
10'h02b: data = 32'hafc40008;
10'h02c: data = 32'h081000ea;
10'h02d: data = 32'h00000000;
10'h02e: data = 32'h24020300;
10'h02f: data = 32'hac400000;
10'h030: data = 32'h8fc20008;
10'h031: data = 32'h00000000;
10'h032: data = 32'h8c420000;
10'h033: data = 32'h00000000;
10'h034: data = 32'h2c420041;
10'h035: data = 32'h14400011;
10'h036: data = 32'h00000000;
10'h037: data = 32'h8fc20008;
10'h038: data = 32'h00000000;
10'h039: data = 32'h8c420000;
10'h03a: data = 32'h00000000;
10'h03b: data = 32'h2c42005b;
10'h03c: data = 32'h1040000a;
10'h03d: data = 32'h00000000;
10'h03e: data = 32'h24030304;
10'h03f: data = 32'h8fc20008;
10'h040: data = 32'h00000000;
10'h041: data = 32'h8c420000;
10'h042: data = 32'h00000000;
10'h043: data = 32'h2442ffc0;
10'h044: data = 32'hac620000;
10'h045: data = 32'h081000e3;
10'h046: data = 32'h00000000;
10'h047: data = 32'h8fc20008;
10'h048: data = 32'h00000000;
10'h049: data = 32'h8c420000;
10'h04a: data = 32'h00000000;
10'h04b: data = 32'h2c420061;
10'h04c: data = 32'h14400011;
10'h04d: data = 32'h00000000;
10'h04e: data = 32'h8fc20008;
10'h04f: data = 32'h00000000;
10'h050: data = 32'h8c420000;
10'h051: data = 32'h00000000;
10'h052: data = 32'h2c42007b;
10'h053: data = 32'h1040000a;
10'h054: data = 32'h00000000;
10'h055: data = 32'h24030304;
10'h056: data = 32'h8fc20008;
10'h057: data = 32'h00000000;
10'h058: data = 32'h8c420000;
10'h059: data = 32'h00000000;
10'h05a: data = 32'h2442ffa0;
10'h05b: data = 32'hac620000;
10'h05c: data = 32'h081000e3;
10'h05d: data = 32'h00000000;
10'h05e: data = 32'h8fc20008;
10'h05f: data = 32'h00000000;
10'h060: data = 32'h8c420000;
10'h061: data = 32'h00000000;
10'h062: data = 32'h2c420030;
10'h063: data = 32'h14400010;
10'h064: data = 32'h00000000;
10'h065: data = 32'h8fc20008;
10'h066: data = 32'h00000000;
10'h067: data = 32'h8c420000;
10'h068: data = 32'h00000000;
10'h069: data = 32'h2c42003a;
10'h06a: data = 32'h10400009;
10'h06b: data = 32'h00000000;
10'h06c: data = 32'h24020304;
10'h06d: data = 32'h8fc30008;
10'h06e: data = 32'h00000000;
10'h06f: data = 32'h8c630000;
10'h070: data = 32'h00000000;
10'h071: data = 32'hac430000;
10'h072: data = 32'h081000e3;
10'h073: data = 32'h00000000;
10'h074: data = 32'h8fc20008;
10'h075: data = 32'h00000000;
10'h076: data = 32'h8c430000;
10'h077: data = 32'h24020040;
10'h078: data = 32'h14620005;
10'h079: data = 32'h00000000;
10'h07a: data = 32'h24020304;
10'h07b: data = 32'hac400000;
10'h07c: data = 32'h081000e3;
10'h07d: data = 32'h00000000;
10'h07e: data = 32'h8fc20008;
10'h07f: data = 32'h00000000;
10'h080: data = 32'h8c430000;
10'h081: data = 32'h2402005b;
10'h082: data = 32'h14620006;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24030304;
10'h085: data = 32'h2402001b;
10'h086: data = 32'hac620000;
10'h087: data = 32'h081000e3;
10'h088: data = 32'h00000000;
10'h089: data = 32'h8fc20008;
10'h08a: data = 32'h00000000;
10'h08b: data = 32'h8c430000;
10'h08c: data = 32'h2402005d;
10'h08d: data = 32'h14620006;
10'h08e: data = 32'h00000000;
10'h08f: data = 32'h24030304;
10'h090: data = 32'h2402001d;
10'h091: data = 32'hac620000;
10'h092: data = 32'h081000e3;
10'h093: data = 32'h00000000;
10'h094: data = 32'h8fc20008;
10'h095: data = 32'h00000000;
10'h096: data = 32'h8c420000;
10'h097: data = 32'h00000000;
10'h098: data = 32'h2c420020;
10'h099: data = 32'h14400010;
10'h09a: data = 32'h00000000;
10'h09b: data = 32'h8fc20008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h8c420000;
10'h09e: data = 32'h00000000;
10'h09f: data = 32'h2c420030;
10'h0a0: data = 32'h10400009;
10'h0a1: data = 32'h00000000;
10'h0a2: data = 32'h24020304;
10'h0a3: data = 32'h8fc30008;
10'h0a4: data = 32'h00000000;
10'h0a5: data = 32'h8c630000;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'hac430000;
10'h0a8: data = 32'h081000e3;
10'h0a9: data = 32'h00000000;
10'h0aa: data = 32'h8fc20008;
10'h0ab: data = 32'h00000000;
10'h0ac: data = 32'h8c430000;
10'h0ad: data = 32'h2402003f;
10'h0ae: data = 32'h14620006;
10'h0af: data = 32'h00000000;
10'h0b0: data = 32'h24030304;
10'h0b1: data = 32'h2402003a;
10'h0b2: data = 32'hac620000;
10'h0b3: data = 32'h081000e3;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'h8fc20008;
10'h0b6: data = 32'h00000000;
10'h0b7: data = 32'h8c430000;
10'h0b8: data = 32'h2402003d;
10'h0b9: data = 32'h14620006;
10'h0ba: data = 32'h00000000;
10'h0bb: data = 32'h24030304;
10'h0bc: data = 32'h2402003b;
10'h0bd: data = 32'hac620000;
10'h0be: data = 32'h081000e3;
10'h0bf: data = 32'h00000000;
10'h0c0: data = 32'h8fc20008;
10'h0c1: data = 32'h00000000;
10'h0c2: data = 32'h8c430000;
10'h0c3: data = 32'h2402003b;
10'h0c4: data = 32'h14620006;
10'h0c5: data = 32'h00000000;
10'h0c6: data = 32'h24030304;
10'h0c7: data = 32'h2402003c;
10'h0c8: data = 32'hac620000;
10'h0c9: data = 32'h081000e3;
10'h0ca: data = 32'h00000000;
10'h0cb: data = 32'h8fc20008;
10'h0cc: data = 32'h00000000;
10'h0cd: data = 32'h8c430000;
10'h0ce: data = 32'h2402003a;
10'h0cf: data = 32'h14620006;
10'h0d0: data = 32'h00000000;
10'h0d1: data = 32'h24030304;
10'h0d2: data = 32'h2402003d;
10'h0d3: data = 32'hac620000;
10'h0d4: data = 32'h081000e3;
10'h0d5: data = 32'h00000000;
10'h0d6: data = 32'h8fc20008;
10'h0d7: data = 32'h00000000;
10'h0d8: data = 32'h8c430000;
10'h0d9: data = 32'h2402000a;
10'h0da: data = 32'h14620006;
10'h0db: data = 32'h00000000;
10'h0dc: data = 32'h24030304;
10'h0dd: data = 32'h2402003e;
10'h0de: data = 32'hac620000;
10'h0df: data = 32'h081000e3;
10'h0e0: data = 32'h00000000;
10'h0e1: data = 32'h24020304;
10'h0e2: data = 32'hac400000;
10'h0e3: data = 32'h24030300;
10'h0e4: data = 32'h24020001;
10'h0e5: data = 32'hac620000;
10'h0e6: data = 32'h8fc20008;
10'h0e7: data = 32'h00000000;
10'h0e8: data = 32'h24420004;
10'h0e9: data = 32'hafc20008;
10'h0ea: data = 32'h8fc20008;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8c420000;
10'h0ed: data = 32'h00000000;
10'h0ee: data = 32'h1440ff3f;
10'h0ef: data = 32'h00000000;
10'h0f0: data = 32'h03c0e821;
10'h0f1: data = 32'h8fbe0000;
10'h0f2: data = 32'h27bd0008;
10'h0f3: data = 32'h03e00008;
10'h0f4: data = 32'h00000000;
10'h0f5: data = 32'h00000000;
10'h0f6: data = 32'h00000000;
10'h0f7: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h004083d0;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfee8;
10'h009: data = 32'hafbf0114;
10'h00a: data = 32'hafbe0110;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20010;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc20014;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20018;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc2001c;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20020;
10'h016: data = 32'h24020021;
10'h017: data = 32'hafc20024;
10'h018: data = 32'h24020021;
10'h019: data = 32'hafc20028;
10'h01a: data = 32'hafc0002c;
10'h01b: data = 32'h27c20010;
10'h01c: data = 32'h00402021;
10'h01d: data = 32'h0c100028;
10'h01e: data = 32'h00000000;
10'h01f: data = 32'h24020042;
10'h020: data = 32'hafc20010;
10'h021: data = 32'hafc00014;
10'h022: data = 32'h03c0e821;
10'h023: data = 32'h8fbf0114;
10'h024: data = 32'h8fbe0110;
10'h025: data = 32'h27bd0118;
10'h026: data = 32'h03e00008;
10'h027: data = 32'h00000000;
10'h028: data = 32'h27bdfff8;
10'h029: data = 32'hafbe0000;
10'h02a: data = 32'h03a0f021;
10'h02b: data = 32'hafc40008;
10'h02c: data = 32'h081000ea;
10'h02d: data = 32'h00000000;
10'h02e: data = 32'h24020300;
10'h02f: data = 32'hac400000;
10'h030: data = 32'h8fc20008;
10'h031: data = 32'h00000000;
10'h032: data = 32'h8c420000;
10'h033: data = 32'h00000000;
10'h034: data = 32'h2c420041;
10'h035: data = 32'h14400011;
10'h036: data = 32'h00000000;
10'h037: data = 32'h8fc20008;
10'h038: data = 32'h00000000;
10'h039: data = 32'h8c420000;
10'h03a: data = 32'h00000000;
10'h03b: data = 32'h2c42005b;
10'h03c: data = 32'h1040000a;
10'h03d: data = 32'h00000000;
10'h03e: data = 32'h24030304;
10'h03f: data = 32'h8fc20008;
10'h040: data = 32'h00000000;
10'h041: data = 32'h8c420000;
10'h042: data = 32'h00000000;
10'h043: data = 32'h2442ffc0;
10'h044: data = 32'hac620000;
10'h045: data = 32'h081000e3;
10'h046: data = 32'h00000000;
10'h047: data = 32'h8fc20008;
10'h048: data = 32'h00000000;
10'h049: data = 32'h8c420000;
10'h04a: data = 32'h00000000;
10'h04b: data = 32'h2c420061;
10'h04c: data = 32'h14400011;
10'h04d: data = 32'h00000000;
10'h04e: data = 32'h8fc20008;
10'h04f: data = 32'h00000000;
10'h050: data = 32'h8c420000;
10'h051: data = 32'h00000000;
10'h052: data = 32'h2c42007b;
10'h053: data = 32'h1040000a;
10'h054: data = 32'h00000000;
10'h055: data = 32'h24030304;
10'h056: data = 32'h8fc20008;
10'h057: data = 32'h00000000;
10'h058: data = 32'h8c420000;
10'h059: data = 32'h00000000;
10'h05a: data = 32'h2442ffa0;
10'h05b: data = 32'hac620000;
10'h05c: data = 32'h081000e3;
10'h05d: data = 32'h00000000;
10'h05e: data = 32'h8fc20008;
10'h05f: data = 32'h00000000;
10'h060: data = 32'h8c420000;
10'h061: data = 32'h00000000;
10'h062: data = 32'h2c420030;
10'h063: data = 32'h14400010;
10'h064: data = 32'h00000000;
10'h065: data = 32'h8fc20008;
10'h066: data = 32'h00000000;
10'h067: data = 32'h8c420000;
10'h068: data = 32'h00000000;
10'h069: data = 32'h2c42003a;
10'h06a: data = 32'h10400009;
10'h06b: data = 32'h00000000;
10'h06c: data = 32'h24020304;
10'h06d: data = 32'h8fc30008;
10'h06e: data = 32'h00000000;
10'h06f: data = 32'h8c630000;
10'h070: data = 32'h00000000;
10'h071: data = 32'hac430000;
10'h072: data = 32'h081000e3;
10'h073: data = 32'h00000000;
10'h074: data = 32'h8fc20008;
10'h075: data = 32'h00000000;
10'h076: data = 32'h8c430000;
10'h077: data = 32'h24020040;
10'h078: data = 32'h14620005;
10'h079: data = 32'h00000000;
10'h07a: data = 32'h24020304;
10'h07b: data = 32'hac400000;
10'h07c: data = 32'h081000e3;
10'h07d: data = 32'h00000000;
10'h07e: data = 32'h8fc20008;
10'h07f: data = 32'h00000000;
10'h080: data = 32'h8c430000;
10'h081: data = 32'h2402005b;
10'h082: data = 32'h14620006;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24030304;
10'h085: data = 32'h2402001b;
10'h086: data = 32'hac620000;
10'h087: data = 32'h081000e3;
10'h088: data = 32'h00000000;
10'h089: data = 32'h8fc20008;
10'h08a: data = 32'h00000000;
10'h08b: data = 32'h8c430000;
10'h08c: data = 32'h2402005d;
10'h08d: data = 32'h14620006;
10'h08e: data = 32'h00000000;
10'h08f: data = 32'h24030304;
10'h090: data = 32'h2402001d;
10'h091: data = 32'hac620000;
10'h092: data = 32'h081000e3;
10'h093: data = 32'h00000000;
10'h094: data = 32'h8fc20008;
10'h095: data = 32'h00000000;
10'h096: data = 32'h8c420000;
10'h097: data = 32'h00000000;
10'h098: data = 32'h2c420020;
10'h099: data = 32'h14400010;
10'h09a: data = 32'h00000000;
10'h09b: data = 32'h8fc20008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h8c420000;
10'h09e: data = 32'h00000000;
10'h09f: data = 32'h2c420030;
10'h0a0: data = 32'h10400009;
10'h0a1: data = 32'h00000000;
10'h0a2: data = 32'h24020304;
10'h0a3: data = 32'h8fc30008;
10'h0a4: data = 32'h00000000;
10'h0a5: data = 32'h8c630000;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'hac430000;
10'h0a8: data = 32'h081000e3;
10'h0a9: data = 32'h00000000;
10'h0aa: data = 32'h8fc20008;
10'h0ab: data = 32'h00000000;
10'h0ac: data = 32'h8c430000;
10'h0ad: data = 32'h2402003f;
10'h0ae: data = 32'h14620006;
10'h0af: data = 32'h00000000;
10'h0b0: data = 32'h24030304;
10'h0b1: data = 32'h2402003a;
10'h0b2: data = 32'hac620000;
10'h0b3: data = 32'h081000e3;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'h8fc20008;
10'h0b6: data = 32'h00000000;
10'h0b7: data = 32'h8c430000;
10'h0b8: data = 32'h2402003d;
10'h0b9: data = 32'h14620006;
10'h0ba: data = 32'h00000000;
10'h0bb: data = 32'h24030304;
10'h0bc: data = 32'h2402003b;
10'h0bd: data = 32'hac620000;
10'h0be: data = 32'h081000e3;
10'h0bf: data = 32'h00000000;
10'h0c0: data = 32'h8fc20008;
10'h0c1: data = 32'h00000000;
10'h0c2: data = 32'h8c430000;
10'h0c3: data = 32'h2402003b;
10'h0c4: data = 32'h14620006;
10'h0c5: data = 32'h00000000;
10'h0c6: data = 32'h24030304;
10'h0c7: data = 32'h2402003c;
10'h0c8: data = 32'hac620000;
10'h0c9: data = 32'h081000e3;
10'h0ca: data = 32'h00000000;
10'h0cb: data = 32'h8fc20008;
10'h0cc: data = 32'h00000000;
10'h0cd: data = 32'h8c430000;
10'h0ce: data = 32'h2402003a;
10'h0cf: data = 32'h14620006;
10'h0d0: data = 32'h00000000;
10'h0d1: data = 32'h24030304;
10'h0d2: data = 32'h2402003d;
10'h0d3: data = 32'hac620000;
10'h0d4: data = 32'h081000e3;
10'h0d5: data = 32'h00000000;
10'h0d6: data = 32'h8fc20008;
10'h0d7: data = 32'h00000000;
10'h0d8: data = 32'h8c430000;
10'h0d9: data = 32'h2402000a;
10'h0da: data = 32'h14620006;
10'h0db: data = 32'h00000000;
10'h0dc: data = 32'h24030304;
10'h0dd: data = 32'h2402003e;
10'h0de: data = 32'hac620000;
10'h0df: data = 32'h081000e3;
10'h0e0: data = 32'h00000000;
10'h0e1: data = 32'h24020304;
10'h0e2: data = 32'hac400000;
10'h0e3: data = 32'h24030300;
10'h0e4: data = 32'h24020001;
10'h0e5: data = 32'hac620000;
10'h0e6: data = 32'h8fc20008;
10'h0e7: data = 32'h00000000;
10'h0e8: data = 32'h24420004;
10'h0e9: data = 32'hafc20008;
10'h0ea: data = 32'h8fc20008;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8c420000;
10'h0ed: data = 32'h00000000;
10'h0ee: data = 32'h1440ff3f;
10'h0ef: data = 32'h00000000;
10'h0f0: data = 32'h03c0e821;
10'h0f1: data = 32'h8fbe0000;
10'h0f2: data = 32'h27bd0008;
10'h0f3: data = 32'h03e00008;
10'h0f4: data = 32'h00000000;
10'h0f5: data = 32'h00000000;
10'h0f6: data = 32'h00000000;
10'h0f7: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,884 | data/full_repos/permissive/107499099/ex3/my_scan/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 548 | 99 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex3/my_scan/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,666 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408800;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfee8;
10'h009: data = 32'hafbf0114;
10'h00a: data = 32'hafbe0110;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20010;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc20014;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20018;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc2001c;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20020;
10'h016: data = 32'h24020021;
10'h017: data = 32'hafc20024;
10'h018: data = 32'h24020021;
10'h019: data = 32'hafc20028;
10'h01a: data = 32'h2402000a;
10'h01b: data = 32'hafc2002c;
10'h01c: data = 32'hafc00030;
10'h01d: data = 32'h27c20010;
10'h01e: data = 32'h00402021;
10'h01f: data = 32'h0c100136;
10'h020: data = 32'h00000000;
10'h021: data = 32'h24020053;
10'h022: data = 32'hafc20010;
10'h023: data = 32'h24020054;
10'h024: data = 32'hafc20014;
10'h025: data = 32'h24020052;
10'h026: data = 32'hafc20018;
10'h027: data = 32'h24020049;
10'h028: data = 32'hafc2001c;
10'h029: data = 32'h2402004e;
10'h02a: data = 32'hafc20020;
10'h02b: data = 32'h24020047;
10'h02c: data = 32'hafc20024;
10'h02d: data = 32'h2402003d;
10'h02e: data = 32'hafc20028;
10'h02f: data = 32'hafc0002c;
10'h030: data = 32'h27c20010;
10'h031: data = 32'h00402021;
10'h032: data = 32'h0c100136;
10'h033: data = 32'h00000000;
10'h034: data = 32'h27c20090;
10'h035: data = 32'h00402021;
10'h036: data = 32'h0c100054;
10'h037: data = 32'h00000000;
10'h038: data = 32'h24020045;
10'h039: data = 32'hafc20010;
10'h03a: data = 32'h24020043;
10'h03b: data = 32'hafc20014;
10'h03c: data = 32'h24020048;
10'h03d: data = 32'hafc20018;
10'h03e: data = 32'h2402004f;
10'h03f: data = 32'hafc2001c;
10'h040: data = 32'h24020020;
10'h041: data = 32'hafc20020;
10'h042: data = 32'hafc00024;
10'h043: data = 32'h27c20010;
10'h044: data = 32'h00402021;
10'h045: data = 32'h0c100136;
10'h046: data = 32'h00000000;
10'h047: data = 32'h27c20090;
10'h048: data = 32'h00402021;
10'h049: data = 32'h0c100136;
10'h04a: data = 32'h00000000;
10'h04b: data = 32'h2402000a;
10'h04c: data = 32'hafc20010;
10'h04d: data = 32'hafc00014;
10'h04e: data = 32'h27c20010;
10'h04f: data = 32'h00402021;
10'h050: data = 32'h0c100136;
10'h051: data = 32'h00000000;
10'h052: data = 32'h08100021;
10'h053: data = 32'h00000000;
10'h054: data = 32'h27bdfff8;
10'h055: data = 32'hafbe0000;
10'h056: data = 32'h03a0f021;
10'h057: data = 32'hafc40008;
10'h058: data = 32'h24020308;
10'h059: data = 32'hac400000;
10'h05a: data = 32'h2403030c;
10'h05b: data = 32'h24020001;
10'h05c: data = 32'hac620000;
10'h05d: data = 32'h24030308;
10'h05e: data = 32'h24020001;
10'h05f: data = 32'hac620000;
10'h060: data = 32'h24020308;
10'h061: data = 32'hac400000;
10'h062: data = 32'h24030308;
10'h063: data = 32'h24020001;
10'h064: data = 32'hac620000;
10'h065: data = 32'h0810006c;
10'h066: data = 32'h00000000;
10'h067: data = 32'h24020308;
10'h068: data = 32'hac400000;
10'h069: data = 32'h24030308;
10'h06a: data = 32'h24020001;
10'h06b: data = 32'hac620000;
10'h06c: data = 32'h24020310;
10'h06d: data = 32'h8c430000;
10'h06e: data = 32'h2402ffff;
10'h06f: data = 32'h1062fff7;
10'h070: data = 32'h00000000;
10'h071: data = 32'h0810011a;
10'h072: data = 32'h00000000;
10'h073: data = 32'h8fc20008;
10'h074: data = 32'h00000000;
10'h075: data = 32'h8c420000;
10'h076: data = 32'h00000000;
10'h077: data = 32'h10400012;
10'h078: data = 32'h00000000;
10'h079: data = 32'h8fc20008;
10'h07a: data = 32'h00000000;
10'h07b: data = 32'h8c420000;
10'h07c: data = 32'h00000000;
10'h07d: data = 32'h2c42001b;
10'h07e: data = 32'h1040000b;
10'h07f: data = 32'h00000000;
10'h080: data = 32'h8fc20008;
10'h081: data = 32'h00000000;
10'h082: data = 32'h8c420000;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24430040;
10'h085: data = 32'h8fc20008;
10'h086: data = 32'h00000000;
10'h087: data = 32'hac430000;
10'h088: data = 32'h08100111;
10'h089: data = 32'h00000000;
10'h08a: data = 32'h8fc20008;
10'h08b: data = 32'h00000000;
10'h08c: data = 32'h8c420000;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h2c420030;
10'h08f: data = 32'h14400010;
10'h090: data = 32'h00000000;
10'h091: data = 32'h8fc20008;
10'h092: data = 32'h00000000;
10'h093: data = 32'h8c420000;
10'h094: data = 32'h00000000;
10'h095: data = 32'h2c42003a;
10'h096: data = 32'h10400009;
10'h097: data = 32'h00000000;
10'h098: data = 32'h8fc20008;
10'h099: data = 32'h00000000;
10'h09a: data = 32'h8c430000;
10'h09b: data = 32'h8fc20008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'hac430000;
10'h09e: data = 32'h08100111;
10'h09f: data = 32'h00000000;
10'h0a0: data = 32'h8fc20008;
10'h0a1: data = 32'h00000000;
10'h0a2: data = 32'h8c420000;
10'h0a3: data = 32'h00000000;
10'h0a4: data = 32'h14400006;
10'h0a5: data = 32'h00000000;
10'h0a6: data = 32'h8fc30008;
10'h0a7: data = 32'h24020040;
10'h0a8: data = 32'hac620000;
10'h0a9: data = 32'h08100111;
10'h0aa: data = 32'h00000000;
10'h0ab: data = 32'h8fc20008;
10'h0ac: data = 32'h00000000;
10'h0ad: data = 32'h8c430000;
10'h0ae: data = 32'h2402001b;
10'h0af: data = 32'h14620006;
10'h0b0: data = 32'h00000000;
10'h0b1: data = 32'h8fc30008;
10'h0b2: data = 32'h2402005b;
10'h0b3: data = 32'hac620000;
10'h0b4: data = 32'h08100111;
10'h0b5: data = 32'h00000000;
10'h0b6: data = 32'h8fc20008;
10'h0b7: data = 32'h00000000;
10'h0b8: data = 32'h8c430000;
10'h0b9: data = 32'h2402001d;
10'h0ba: data = 32'h14620006;
10'h0bb: data = 32'h00000000;
10'h0bc: data = 32'h8fc30008;
10'h0bd: data = 32'h2402005d;
10'h0be: data = 32'hac620000;
10'h0bf: data = 32'h08100111;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h8fc20008;
10'h0c2: data = 32'h00000000;
10'h0c3: data = 32'h8c420000;
10'h0c4: data = 32'h00000000;
10'h0c5: data = 32'h2c420020;
10'h0c6: data = 32'h14400010;
10'h0c7: data = 32'h00000000;
10'h0c8: data = 32'h8fc20008;
10'h0c9: data = 32'h00000000;
10'h0ca: data = 32'h8c420000;
10'h0cb: data = 32'h00000000;
10'h0cc: data = 32'h2c420030;
10'h0cd: data = 32'h10400009;
10'h0ce: data = 32'h00000000;
10'h0cf: data = 32'h8fc20008;
10'h0d0: data = 32'h00000000;
10'h0d1: data = 32'h8c430000;
10'h0d2: data = 32'h8fc20008;
10'h0d3: data = 32'h00000000;
10'h0d4: data = 32'hac430000;
10'h0d5: data = 32'h08100111;
10'h0d6: data = 32'h00000000;
10'h0d7: data = 32'h8fc20008;
10'h0d8: data = 32'h00000000;
10'h0d9: data = 32'h8c430000;
10'h0da: data = 32'h2402003a;
10'h0db: data = 32'h14620006;
10'h0dc: data = 32'h00000000;
10'h0dd: data = 32'h8fc30008;
10'h0de: data = 32'h2402003f;
10'h0df: data = 32'hac620000;
10'h0e0: data = 32'h08100111;
10'h0e1: data = 32'h00000000;
10'h0e2: data = 32'h8fc20008;
10'h0e3: data = 32'h00000000;
10'h0e4: data = 32'h8c430000;
10'h0e5: data = 32'h2402003b;
10'h0e6: data = 32'h14620006;
10'h0e7: data = 32'h00000000;
10'h0e8: data = 32'h8fc30008;
10'h0e9: data = 32'h2402003d;
10'h0ea: data = 32'hac620000;
10'h0eb: data = 32'h08100111;
10'h0ec: data = 32'h00000000;
10'h0ed: data = 32'h8fc20008;
10'h0ee: data = 32'h00000000;
10'h0ef: data = 32'h8c430000;
10'h0f0: data = 32'h2402003c;
10'h0f1: data = 32'h14620006;
10'h0f2: data = 32'h00000000;
10'h0f3: data = 32'h8fc30008;
10'h0f4: data = 32'h2402003b;
10'h0f5: data = 32'hac620000;
10'h0f6: data = 32'h08100111;
10'h0f7: data = 32'h00000000;
10'h0f8: data = 32'h8fc20008;
10'h0f9: data = 32'h00000000;
10'h0fa: data = 32'h8c430000;
10'h0fb: data = 32'h2402003d;
10'h0fc: data = 32'h14620006;
10'h0fd: data = 32'h00000000;
10'h0fe: data = 32'h8fc30008;
10'h0ff: data = 32'h2402003a;
10'h100: data = 32'hac620000;
10'h101: data = 32'h08100111;
10'h102: data = 32'h00000000;
10'h103: data = 32'h8fc20008;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8c430000;
10'h106: data = 32'h2402003e;
10'h107: data = 32'h14620006;
10'h108: data = 32'h00000000;
10'h109: data = 32'h8fc30008;
10'h10a: data = 32'h2402000a;
10'h10b: data = 32'hac620000;
10'h10c: data = 32'h08100111;
10'h10d: data = 32'h00000000;
10'h10e: data = 32'h8fc30008;
10'h10f: data = 32'h24020040;
10'h110: data = 32'hac620000;
10'h111: data = 32'h24020308;
10'h112: data = 32'hac400000;
10'h113: data = 32'h24030308;
10'h114: data = 32'h24020001;
10'h115: data = 32'hac620000;
10'h116: data = 32'h8fc20008;
10'h117: data = 32'h00000000;
10'h118: data = 32'h24420004;
10'h119: data = 32'hafc20008;
10'h11a: data = 32'h24020310;
10'h11b: data = 32'h8c430000;
10'h11c: data = 32'h8fc20008;
10'h11d: data = 32'h00000000;
10'h11e: data = 32'hac430000;
10'h11f: data = 32'h8fc20008;
10'h120: data = 32'h00000000;
10'h121: data = 32'h8c430000;
10'h122: data = 32'h2402003e;
10'h123: data = 32'h1462ff4f;
10'h124: data = 32'h00000000;
10'h125: data = 32'h8fc20008;
10'h126: data = 32'h00000000;
10'h127: data = 32'hac400000;
10'h128: data = 32'h24020308;
10'h129: data = 32'hac400000;
10'h12a: data = 32'h2402030c;
10'h12b: data = 32'hac400000;
10'h12c: data = 32'h24030308;
10'h12d: data = 32'h24020001;
10'h12e: data = 32'hac620000;
10'h12f: data = 32'h24020308;
10'h130: data = 32'hac400000;
10'h131: data = 32'h03c0e821;
10'h132: data = 32'h8fbe0000;
10'h133: data = 32'h27bd0008;
10'h134: data = 32'h03e00008;
10'h135: data = 32'h00000000;
10'h136: data = 32'h27bdfff8;
10'h137: data = 32'hafbe0000;
10'h138: data = 32'h03a0f021;
10'h139: data = 32'hafc40008;
10'h13a: data = 32'h081001f8;
10'h13b: data = 32'h00000000;
10'h13c: data = 32'h24020300;
10'h13d: data = 32'hac400000;
10'h13e: data = 32'h8fc20008;
10'h13f: data = 32'h00000000;
10'h140: data = 32'h8c420000;
10'h141: data = 32'h00000000;
10'h142: data = 32'h2c420041;
10'h143: data = 32'h14400011;
10'h144: data = 32'h00000000;
10'h145: data = 32'h8fc20008;
10'h146: data = 32'h00000000;
10'h147: data = 32'h8c420000;
10'h148: data = 32'h00000000;
10'h149: data = 32'h2c42005b;
10'h14a: data = 32'h1040000a;
10'h14b: data = 32'h00000000;
10'h14c: data = 32'h24030304;
10'h14d: data = 32'h8fc20008;
10'h14e: data = 32'h00000000;
10'h14f: data = 32'h8c420000;
10'h150: data = 32'h00000000;
10'h151: data = 32'h2442ffc0;
10'h152: data = 32'hac620000;
10'h153: data = 32'h081001f1;
10'h154: data = 32'h00000000;
10'h155: data = 32'h8fc20008;
10'h156: data = 32'h00000000;
10'h157: data = 32'h8c420000;
10'h158: data = 32'h00000000;
10'h159: data = 32'h2c420061;
10'h15a: data = 32'h14400011;
10'h15b: data = 32'h00000000;
10'h15c: data = 32'h8fc20008;
10'h15d: data = 32'h00000000;
10'h15e: data = 32'h8c420000;
10'h15f: data = 32'h00000000;
10'h160: data = 32'h2c42007b;
10'h161: data = 32'h1040000a;
10'h162: data = 32'h00000000;
10'h163: data = 32'h24030304;
10'h164: data = 32'h8fc20008;
10'h165: data = 32'h00000000;
10'h166: data = 32'h8c420000;
10'h167: data = 32'h00000000;
10'h168: data = 32'h2442ffa0;
10'h169: data = 32'hac620000;
10'h16a: data = 32'h081001f1;
10'h16b: data = 32'h00000000;
10'h16c: data = 32'h8fc20008;
10'h16d: data = 32'h00000000;
10'h16e: data = 32'h8c420000;
10'h16f: data = 32'h00000000;
10'h170: data = 32'h2c420030;
10'h171: data = 32'h14400010;
10'h172: data = 32'h00000000;
10'h173: data = 32'h8fc20008;
10'h174: data = 32'h00000000;
10'h175: data = 32'h8c420000;
10'h176: data = 32'h00000000;
10'h177: data = 32'h2c42003a;
10'h178: data = 32'h10400009;
10'h179: data = 32'h00000000;
10'h17a: data = 32'h24020304;
10'h17b: data = 32'h8fc30008;
10'h17c: data = 32'h00000000;
10'h17d: data = 32'h8c630000;
10'h17e: data = 32'h00000000;
10'h17f: data = 32'hac430000;
10'h180: data = 32'h081001f1;
10'h181: data = 32'h00000000;
10'h182: data = 32'h8fc20008;
10'h183: data = 32'h00000000;
10'h184: data = 32'h8c430000;
10'h185: data = 32'h24020040;
10'h186: data = 32'h14620005;
10'h187: data = 32'h00000000;
10'h188: data = 32'h24020304;
10'h189: data = 32'hac400000;
10'h18a: data = 32'h081001f1;
10'h18b: data = 32'h00000000;
10'h18c: data = 32'h8fc20008;
10'h18d: data = 32'h00000000;
10'h18e: data = 32'h8c430000;
10'h18f: data = 32'h2402005b;
10'h190: data = 32'h14620006;
10'h191: data = 32'h00000000;
10'h192: data = 32'h24030304;
10'h193: data = 32'h2402001b;
10'h194: data = 32'hac620000;
10'h195: data = 32'h081001f1;
10'h196: data = 32'h00000000;
10'h197: data = 32'h8fc20008;
10'h198: data = 32'h00000000;
10'h199: data = 32'h8c430000;
10'h19a: data = 32'h2402005d;
10'h19b: data = 32'h14620006;
10'h19c: data = 32'h00000000;
10'h19d: data = 32'h24030304;
10'h19e: data = 32'h2402001d;
10'h19f: data = 32'hac620000;
10'h1a0: data = 32'h081001f1;
10'h1a1: data = 32'h00000000;
10'h1a2: data = 32'h8fc20008;
10'h1a3: data = 32'h00000000;
10'h1a4: data = 32'h8c420000;
10'h1a5: data = 32'h00000000;
10'h1a6: data = 32'h2c420020;
10'h1a7: data = 32'h14400010;
10'h1a8: data = 32'h00000000;
10'h1a9: data = 32'h8fc20008;
10'h1aa: data = 32'h00000000;
10'h1ab: data = 32'h8c420000;
10'h1ac: data = 32'h00000000;
10'h1ad: data = 32'h2c420030;
10'h1ae: data = 32'h10400009;
10'h1af: data = 32'h00000000;
10'h1b0: data = 32'h24020304;
10'h1b1: data = 32'h8fc30008;
10'h1b2: data = 32'h00000000;
10'h1b3: data = 32'h8c630000;
10'h1b4: data = 32'h00000000;
10'h1b5: data = 32'hac430000;
10'h1b6: data = 32'h081001f1;
10'h1b7: data = 32'h00000000;
10'h1b8: data = 32'h8fc20008;
10'h1b9: data = 32'h00000000;
10'h1ba: data = 32'h8c430000;
10'h1bb: data = 32'h2402003f;
10'h1bc: data = 32'h14620006;
10'h1bd: data = 32'h00000000;
10'h1be: data = 32'h24030304;
10'h1bf: data = 32'h2402003a;
10'h1c0: data = 32'hac620000;
10'h1c1: data = 32'h081001f1;
10'h1c2: data = 32'h00000000;
10'h1c3: data = 32'h8fc20008;
10'h1c4: data = 32'h00000000;
10'h1c5: data = 32'h8c430000;
10'h1c6: data = 32'h2402003d;
10'h1c7: data = 32'h14620006;
10'h1c8: data = 32'h00000000;
10'h1c9: data = 32'h24030304;
10'h1ca: data = 32'h2402003b;
10'h1cb: data = 32'hac620000;
10'h1cc: data = 32'h081001f1;
10'h1cd: data = 32'h00000000;
10'h1ce: data = 32'h8fc20008;
10'h1cf: data = 32'h00000000;
10'h1d0: data = 32'h8c430000;
10'h1d1: data = 32'h2402003b;
10'h1d2: data = 32'h14620006;
10'h1d3: data = 32'h00000000;
10'h1d4: data = 32'h24030304;
10'h1d5: data = 32'h2402003c;
10'h1d6: data = 32'hac620000;
10'h1d7: data = 32'h081001f1;
10'h1d8: data = 32'h00000000;
10'h1d9: data = 32'h8fc20008;
10'h1da: data = 32'h00000000;
10'h1db: data = 32'h8c430000;
10'h1dc: data = 32'h2402003a;
10'h1dd: data = 32'h14620006;
10'h1de: data = 32'h00000000;
10'h1df: data = 32'h24030304;
10'h1e0: data = 32'h2402003d;
10'h1e1: data = 32'hac620000;
10'h1e2: data = 32'h081001f1;
10'h1e3: data = 32'h00000000;
10'h1e4: data = 32'h8fc20008;
10'h1e5: data = 32'h00000000;
10'h1e6: data = 32'h8c430000;
10'h1e7: data = 32'h2402000a;
10'h1e8: data = 32'h14620006;
10'h1e9: data = 32'h00000000;
10'h1ea: data = 32'h24030304;
10'h1eb: data = 32'h2402003e;
10'h1ec: data = 32'hac620000;
10'h1ed: data = 32'h081001f1;
10'h1ee: data = 32'h00000000;
10'h1ef: data = 32'h24020304;
10'h1f0: data = 32'hac400000;
10'h1f1: data = 32'h24030300;
10'h1f2: data = 32'h24020001;
10'h1f3: data = 32'hac620000;
10'h1f4: data = 32'h8fc20008;
10'h1f5: data = 32'h00000000;
10'h1f6: data = 32'h24420004;
10'h1f7: data = 32'hafc20008;
10'h1f8: data = 32'h8fc20008;
10'h1f9: data = 32'h00000000;
10'h1fa: data = 32'h8c420000;
10'h1fb: data = 32'h00000000;
10'h1fc: data = 32'h1440ff3f;
10'h1fd: data = 32'h00000000;
10'h1fe: data = 32'h03c0e821;
10'h1ff: data = 32'h8fbe0000;
10'h200: data = 32'h27bd0008;
10'h201: data = 32'h03e00008;
10'h202: data = 32'h00000000;
10'h203: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408800;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdfee8;
10'h009: data = 32'hafbf0114;
10'h00a: data = 32'hafbe0110;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20010;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc20014;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20018;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc2001c;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20020;
10'h016: data = 32'h24020021;
10'h017: data = 32'hafc20024;
10'h018: data = 32'h24020021;
10'h019: data = 32'hafc20028;
10'h01a: data = 32'h2402000a;
10'h01b: data = 32'hafc2002c;
10'h01c: data = 32'hafc00030;
10'h01d: data = 32'h27c20010;
10'h01e: data = 32'h00402021;
10'h01f: data = 32'h0c100136;
10'h020: data = 32'h00000000;
10'h021: data = 32'h24020053;
10'h022: data = 32'hafc20010;
10'h023: data = 32'h24020054;
10'h024: data = 32'hafc20014;
10'h025: data = 32'h24020052;
10'h026: data = 32'hafc20018;
10'h027: data = 32'h24020049;
10'h028: data = 32'hafc2001c;
10'h029: data = 32'h2402004e;
10'h02a: data = 32'hafc20020;
10'h02b: data = 32'h24020047;
10'h02c: data = 32'hafc20024;
10'h02d: data = 32'h2402003d;
10'h02e: data = 32'hafc20028;
10'h02f: data = 32'hafc0002c;
10'h030: data = 32'h27c20010;
10'h031: data = 32'h00402021;
10'h032: data = 32'h0c100136;
10'h033: data = 32'h00000000;
10'h034: data = 32'h27c20090;
10'h035: data = 32'h00402021;
10'h036: data = 32'h0c100054;
10'h037: data = 32'h00000000;
10'h038: data = 32'h24020045;
10'h039: data = 32'hafc20010;
10'h03a: data = 32'h24020043;
10'h03b: data = 32'hafc20014;
10'h03c: data = 32'h24020048;
10'h03d: data = 32'hafc20018;
10'h03e: data = 32'h2402004f;
10'h03f: data = 32'hafc2001c;
10'h040: data = 32'h24020020;
10'h041: data = 32'hafc20020;
10'h042: data = 32'hafc00024;
10'h043: data = 32'h27c20010;
10'h044: data = 32'h00402021;
10'h045: data = 32'h0c100136;
10'h046: data = 32'h00000000;
10'h047: data = 32'h27c20090;
10'h048: data = 32'h00402021;
10'h049: data = 32'h0c100136;
10'h04a: data = 32'h00000000;
10'h04b: data = 32'h2402000a;
10'h04c: data = 32'hafc20010;
10'h04d: data = 32'hafc00014;
10'h04e: data = 32'h27c20010;
10'h04f: data = 32'h00402021;
10'h050: data = 32'h0c100136;
10'h051: data = 32'h00000000;
10'h052: data = 32'h08100021;
10'h053: data = 32'h00000000;
10'h054: data = 32'h27bdfff8;
10'h055: data = 32'hafbe0000;
10'h056: data = 32'h03a0f021;
10'h057: data = 32'hafc40008;
10'h058: data = 32'h24020308;
10'h059: data = 32'hac400000;
10'h05a: data = 32'h2403030c;
10'h05b: data = 32'h24020001;
10'h05c: data = 32'hac620000;
10'h05d: data = 32'h24030308;
10'h05e: data = 32'h24020001;
10'h05f: data = 32'hac620000;
10'h060: data = 32'h24020308;
10'h061: data = 32'hac400000;
10'h062: data = 32'h24030308;
10'h063: data = 32'h24020001;
10'h064: data = 32'hac620000;
10'h065: data = 32'h0810006c;
10'h066: data = 32'h00000000;
10'h067: data = 32'h24020308;
10'h068: data = 32'hac400000;
10'h069: data = 32'h24030308;
10'h06a: data = 32'h24020001;
10'h06b: data = 32'hac620000;
10'h06c: data = 32'h24020310;
10'h06d: data = 32'h8c430000;
10'h06e: data = 32'h2402ffff;
10'h06f: data = 32'h1062fff7;
10'h070: data = 32'h00000000;
10'h071: data = 32'h0810011a;
10'h072: data = 32'h00000000;
10'h073: data = 32'h8fc20008;
10'h074: data = 32'h00000000;
10'h075: data = 32'h8c420000;
10'h076: data = 32'h00000000;
10'h077: data = 32'h10400012;
10'h078: data = 32'h00000000;
10'h079: data = 32'h8fc20008;
10'h07a: data = 32'h00000000;
10'h07b: data = 32'h8c420000;
10'h07c: data = 32'h00000000;
10'h07d: data = 32'h2c42001b;
10'h07e: data = 32'h1040000b;
10'h07f: data = 32'h00000000;
10'h080: data = 32'h8fc20008;
10'h081: data = 32'h00000000;
10'h082: data = 32'h8c420000;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24430040;
10'h085: data = 32'h8fc20008;
10'h086: data = 32'h00000000;
10'h087: data = 32'hac430000;
10'h088: data = 32'h08100111;
10'h089: data = 32'h00000000;
10'h08a: data = 32'h8fc20008;
10'h08b: data = 32'h00000000;
10'h08c: data = 32'h8c420000;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h2c420030;
10'h08f: data = 32'h14400010;
10'h090: data = 32'h00000000;
10'h091: data = 32'h8fc20008;
10'h092: data = 32'h00000000;
10'h093: data = 32'h8c420000;
10'h094: data = 32'h00000000;
10'h095: data = 32'h2c42003a;
10'h096: data = 32'h10400009;
10'h097: data = 32'h00000000;
10'h098: data = 32'h8fc20008;
10'h099: data = 32'h00000000;
10'h09a: data = 32'h8c430000;
10'h09b: data = 32'h8fc20008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'hac430000;
10'h09e: data = 32'h08100111;
10'h09f: data = 32'h00000000;
10'h0a0: data = 32'h8fc20008;
10'h0a1: data = 32'h00000000;
10'h0a2: data = 32'h8c420000;
10'h0a3: data = 32'h00000000;
10'h0a4: data = 32'h14400006;
10'h0a5: data = 32'h00000000;
10'h0a6: data = 32'h8fc30008;
10'h0a7: data = 32'h24020040;
10'h0a8: data = 32'hac620000;
10'h0a9: data = 32'h08100111;
10'h0aa: data = 32'h00000000;
10'h0ab: data = 32'h8fc20008;
10'h0ac: data = 32'h00000000;
10'h0ad: data = 32'h8c430000;
10'h0ae: data = 32'h2402001b;
10'h0af: data = 32'h14620006;
10'h0b0: data = 32'h00000000;
10'h0b1: data = 32'h8fc30008;
10'h0b2: data = 32'h2402005b;
10'h0b3: data = 32'hac620000;
10'h0b4: data = 32'h08100111;
10'h0b5: data = 32'h00000000;
10'h0b6: data = 32'h8fc20008;
10'h0b7: data = 32'h00000000;
10'h0b8: data = 32'h8c430000;
10'h0b9: data = 32'h2402001d;
10'h0ba: data = 32'h14620006;
10'h0bb: data = 32'h00000000;
10'h0bc: data = 32'h8fc30008;
10'h0bd: data = 32'h2402005d;
10'h0be: data = 32'hac620000;
10'h0bf: data = 32'h08100111;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h8fc20008;
10'h0c2: data = 32'h00000000;
10'h0c3: data = 32'h8c420000;
10'h0c4: data = 32'h00000000;
10'h0c5: data = 32'h2c420020;
10'h0c6: data = 32'h14400010;
10'h0c7: data = 32'h00000000;
10'h0c8: data = 32'h8fc20008;
10'h0c9: data = 32'h00000000;
10'h0ca: data = 32'h8c420000;
10'h0cb: data = 32'h00000000;
10'h0cc: data = 32'h2c420030;
10'h0cd: data = 32'h10400009;
10'h0ce: data = 32'h00000000;
10'h0cf: data = 32'h8fc20008;
10'h0d0: data = 32'h00000000;
10'h0d1: data = 32'h8c430000;
10'h0d2: data = 32'h8fc20008;
10'h0d3: data = 32'h00000000;
10'h0d4: data = 32'hac430000;
10'h0d5: data = 32'h08100111;
10'h0d6: data = 32'h00000000;
10'h0d7: data = 32'h8fc20008;
10'h0d8: data = 32'h00000000;
10'h0d9: data = 32'h8c430000;
10'h0da: data = 32'h2402003a;
10'h0db: data = 32'h14620006;
10'h0dc: data = 32'h00000000;
10'h0dd: data = 32'h8fc30008;
10'h0de: data = 32'h2402003f;
10'h0df: data = 32'hac620000;
10'h0e0: data = 32'h08100111;
10'h0e1: data = 32'h00000000;
10'h0e2: data = 32'h8fc20008;
10'h0e3: data = 32'h00000000;
10'h0e4: data = 32'h8c430000;
10'h0e5: data = 32'h2402003b;
10'h0e6: data = 32'h14620006;
10'h0e7: data = 32'h00000000;
10'h0e8: data = 32'h8fc30008;
10'h0e9: data = 32'h2402003d;
10'h0ea: data = 32'hac620000;
10'h0eb: data = 32'h08100111;
10'h0ec: data = 32'h00000000;
10'h0ed: data = 32'h8fc20008;
10'h0ee: data = 32'h00000000;
10'h0ef: data = 32'h8c430000;
10'h0f0: data = 32'h2402003c;
10'h0f1: data = 32'h14620006;
10'h0f2: data = 32'h00000000;
10'h0f3: data = 32'h8fc30008;
10'h0f4: data = 32'h2402003b;
10'h0f5: data = 32'hac620000;
10'h0f6: data = 32'h08100111;
10'h0f7: data = 32'h00000000;
10'h0f8: data = 32'h8fc20008;
10'h0f9: data = 32'h00000000;
10'h0fa: data = 32'h8c430000;
10'h0fb: data = 32'h2402003d;
10'h0fc: data = 32'h14620006;
10'h0fd: data = 32'h00000000;
10'h0fe: data = 32'h8fc30008;
10'h0ff: data = 32'h2402003a;
10'h100: data = 32'hac620000;
10'h101: data = 32'h08100111;
10'h102: data = 32'h00000000;
10'h103: data = 32'h8fc20008;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8c430000;
10'h106: data = 32'h2402003e;
10'h107: data = 32'h14620006;
10'h108: data = 32'h00000000;
10'h109: data = 32'h8fc30008;
10'h10a: data = 32'h2402000a;
10'h10b: data = 32'hac620000;
10'h10c: data = 32'h08100111;
10'h10d: data = 32'h00000000;
10'h10e: data = 32'h8fc30008;
10'h10f: data = 32'h24020040;
10'h110: data = 32'hac620000;
10'h111: data = 32'h24020308;
10'h112: data = 32'hac400000;
10'h113: data = 32'h24030308;
10'h114: data = 32'h24020001;
10'h115: data = 32'hac620000;
10'h116: data = 32'h8fc20008;
10'h117: data = 32'h00000000;
10'h118: data = 32'h24420004;
10'h119: data = 32'hafc20008;
10'h11a: data = 32'h24020310;
10'h11b: data = 32'h8c430000;
10'h11c: data = 32'h8fc20008;
10'h11d: data = 32'h00000000;
10'h11e: data = 32'hac430000;
10'h11f: data = 32'h8fc20008;
10'h120: data = 32'h00000000;
10'h121: data = 32'h8c430000;
10'h122: data = 32'h2402003e;
10'h123: data = 32'h1462ff4f;
10'h124: data = 32'h00000000;
10'h125: data = 32'h8fc20008;
10'h126: data = 32'h00000000;
10'h127: data = 32'hac400000;
10'h128: data = 32'h24020308;
10'h129: data = 32'hac400000;
10'h12a: data = 32'h2402030c;
10'h12b: data = 32'hac400000;
10'h12c: data = 32'h24030308;
10'h12d: data = 32'h24020001;
10'h12e: data = 32'hac620000;
10'h12f: data = 32'h24020308;
10'h130: data = 32'hac400000;
10'h131: data = 32'h03c0e821;
10'h132: data = 32'h8fbe0000;
10'h133: data = 32'h27bd0008;
10'h134: data = 32'h03e00008;
10'h135: data = 32'h00000000;
10'h136: data = 32'h27bdfff8;
10'h137: data = 32'hafbe0000;
10'h138: data = 32'h03a0f021;
10'h139: data = 32'hafc40008;
10'h13a: data = 32'h081001f8;
10'h13b: data = 32'h00000000;
10'h13c: data = 32'h24020300;
10'h13d: data = 32'hac400000;
10'h13e: data = 32'h8fc20008;
10'h13f: data = 32'h00000000;
10'h140: data = 32'h8c420000;
10'h141: data = 32'h00000000;
10'h142: data = 32'h2c420041;
10'h143: data = 32'h14400011;
10'h144: data = 32'h00000000;
10'h145: data = 32'h8fc20008;
10'h146: data = 32'h00000000;
10'h147: data = 32'h8c420000;
10'h148: data = 32'h00000000;
10'h149: data = 32'h2c42005b;
10'h14a: data = 32'h1040000a;
10'h14b: data = 32'h00000000;
10'h14c: data = 32'h24030304;
10'h14d: data = 32'h8fc20008;
10'h14e: data = 32'h00000000;
10'h14f: data = 32'h8c420000;
10'h150: data = 32'h00000000;
10'h151: data = 32'h2442ffc0;
10'h152: data = 32'hac620000;
10'h153: data = 32'h081001f1;
10'h154: data = 32'h00000000;
10'h155: data = 32'h8fc20008;
10'h156: data = 32'h00000000;
10'h157: data = 32'h8c420000;
10'h158: data = 32'h00000000;
10'h159: data = 32'h2c420061;
10'h15a: data = 32'h14400011;
10'h15b: data = 32'h00000000;
10'h15c: data = 32'h8fc20008;
10'h15d: data = 32'h00000000;
10'h15e: data = 32'h8c420000;
10'h15f: data = 32'h00000000;
10'h160: data = 32'h2c42007b;
10'h161: data = 32'h1040000a;
10'h162: data = 32'h00000000;
10'h163: data = 32'h24030304;
10'h164: data = 32'h8fc20008;
10'h165: data = 32'h00000000;
10'h166: data = 32'h8c420000;
10'h167: data = 32'h00000000;
10'h168: data = 32'h2442ffa0;
10'h169: data = 32'hac620000;
10'h16a: data = 32'h081001f1;
10'h16b: data = 32'h00000000;
10'h16c: data = 32'h8fc20008;
10'h16d: data = 32'h00000000;
10'h16e: data = 32'h8c420000;
10'h16f: data = 32'h00000000;
10'h170: data = 32'h2c420030;
10'h171: data = 32'h14400010;
10'h172: data = 32'h00000000;
10'h173: data = 32'h8fc20008;
10'h174: data = 32'h00000000;
10'h175: data = 32'h8c420000;
10'h176: data = 32'h00000000;
10'h177: data = 32'h2c42003a;
10'h178: data = 32'h10400009;
10'h179: data = 32'h00000000;
10'h17a: data = 32'h24020304;
10'h17b: data = 32'h8fc30008;
10'h17c: data = 32'h00000000;
10'h17d: data = 32'h8c630000;
10'h17e: data = 32'h00000000;
10'h17f: data = 32'hac430000;
10'h180: data = 32'h081001f1;
10'h181: data = 32'h00000000;
10'h182: data = 32'h8fc20008;
10'h183: data = 32'h00000000;
10'h184: data = 32'h8c430000;
10'h185: data = 32'h24020040;
10'h186: data = 32'h14620005;
10'h187: data = 32'h00000000;
10'h188: data = 32'h24020304;
10'h189: data = 32'hac400000;
10'h18a: data = 32'h081001f1;
10'h18b: data = 32'h00000000;
10'h18c: data = 32'h8fc20008;
10'h18d: data = 32'h00000000;
10'h18e: data = 32'h8c430000;
10'h18f: data = 32'h2402005b;
10'h190: data = 32'h14620006;
10'h191: data = 32'h00000000;
10'h192: data = 32'h24030304;
10'h193: data = 32'h2402001b;
10'h194: data = 32'hac620000;
10'h195: data = 32'h081001f1;
10'h196: data = 32'h00000000;
10'h197: data = 32'h8fc20008;
10'h198: data = 32'h00000000;
10'h199: data = 32'h8c430000;
10'h19a: data = 32'h2402005d;
10'h19b: data = 32'h14620006;
10'h19c: data = 32'h00000000;
10'h19d: data = 32'h24030304;
10'h19e: data = 32'h2402001d;
10'h19f: data = 32'hac620000;
10'h1a0: data = 32'h081001f1;
10'h1a1: data = 32'h00000000;
10'h1a2: data = 32'h8fc20008;
10'h1a3: data = 32'h00000000;
10'h1a4: data = 32'h8c420000;
10'h1a5: data = 32'h00000000;
10'h1a6: data = 32'h2c420020;
10'h1a7: data = 32'h14400010;
10'h1a8: data = 32'h00000000;
10'h1a9: data = 32'h8fc20008;
10'h1aa: data = 32'h00000000;
10'h1ab: data = 32'h8c420000;
10'h1ac: data = 32'h00000000;
10'h1ad: data = 32'h2c420030;
10'h1ae: data = 32'h10400009;
10'h1af: data = 32'h00000000;
10'h1b0: data = 32'h24020304;
10'h1b1: data = 32'h8fc30008;
10'h1b2: data = 32'h00000000;
10'h1b3: data = 32'h8c630000;
10'h1b4: data = 32'h00000000;
10'h1b5: data = 32'hac430000;
10'h1b6: data = 32'h081001f1;
10'h1b7: data = 32'h00000000;
10'h1b8: data = 32'h8fc20008;
10'h1b9: data = 32'h00000000;
10'h1ba: data = 32'h8c430000;
10'h1bb: data = 32'h2402003f;
10'h1bc: data = 32'h14620006;
10'h1bd: data = 32'h00000000;
10'h1be: data = 32'h24030304;
10'h1bf: data = 32'h2402003a;
10'h1c0: data = 32'hac620000;
10'h1c1: data = 32'h081001f1;
10'h1c2: data = 32'h00000000;
10'h1c3: data = 32'h8fc20008;
10'h1c4: data = 32'h00000000;
10'h1c5: data = 32'h8c430000;
10'h1c6: data = 32'h2402003d;
10'h1c7: data = 32'h14620006;
10'h1c8: data = 32'h00000000;
10'h1c9: data = 32'h24030304;
10'h1ca: data = 32'h2402003b;
10'h1cb: data = 32'hac620000;
10'h1cc: data = 32'h081001f1;
10'h1cd: data = 32'h00000000;
10'h1ce: data = 32'h8fc20008;
10'h1cf: data = 32'h00000000;
10'h1d0: data = 32'h8c430000;
10'h1d1: data = 32'h2402003b;
10'h1d2: data = 32'h14620006;
10'h1d3: data = 32'h00000000;
10'h1d4: data = 32'h24030304;
10'h1d5: data = 32'h2402003c;
10'h1d6: data = 32'hac620000;
10'h1d7: data = 32'h081001f1;
10'h1d8: data = 32'h00000000;
10'h1d9: data = 32'h8fc20008;
10'h1da: data = 32'h00000000;
10'h1db: data = 32'h8c430000;
10'h1dc: data = 32'h2402003a;
10'h1dd: data = 32'h14620006;
10'h1de: data = 32'h00000000;
10'h1df: data = 32'h24030304;
10'h1e0: data = 32'h2402003d;
10'h1e1: data = 32'hac620000;
10'h1e2: data = 32'h081001f1;
10'h1e3: data = 32'h00000000;
10'h1e4: data = 32'h8fc20008;
10'h1e5: data = 32'h00000000;
10'h1e6: data = 32'h8c430000;
10'h1e7: data = 32'h2402000a;
10'h1e8: data = 32'h14620006;
10'h1e9: data = 32'h00000000;
10'h1ea: data = 32'h24030304;
10'h1eb: data = 32'h2402003e;
10'h1ec: data = 32'hac620000;
10'h1ed: data = 32'h081001f1;
10'h1ee: data = 32'h00000000;
10'h1ef: data = 32'h24020304;
10'h1f0: data = 32'hac400000;
10'h1f1: data = 32'h24030300;
10'h1f2: data = 32'h24020001;
10'h1f3: data = 32'hac620000;
10'h1f4: data = 32'h8fc20008;
10'h1f5: data = 32'h00000000;
10'h1f6: data = 32'h24420004;
10'h1f7: data = 32'hafc20008;
10'h1f8: data = 32'h8fc20008;
10'h1f9: data = 32'h00000000;
10'h1fa: data = 32'h8c420000;
10'h1fb: data = 32'h00000000;
10'h1fc: data = 32'h1440ff3f;
10'h1fd: data = 32'h00000000;
10'h1fe: data = 32'h03c0e821;
10'h1ff: data = 32'h8fbe0000;
10'h200: data = 32'h27bd0008;
10'h201: data = 32'h03e00008;
10'h202: data = 32'h00000000;
10'h203: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,885 | data/full_repos/permissive/107499099/ex4/sosuu/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 812 | 99 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex4/sosuu/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,667 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408c20;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdff60;
10'h009: data = 32'hafbf009c;
10'h00a: data = 32'hafbe0098;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20018;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc2001c;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20020;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc20024;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20028;
10'h016: data = 32'h2402000a;
10'h017: data = 32'hafc2002c;
10'h018: data = 32'hafc00030;
10'h019: data = 32'h27c20018;
10'h01a: data = 32'h00402021;
10'h01b: data = 32'h0c10023c;
10'h01c: data = 32'h00000000;
10'h01d: data = 32'h2402004e;
10'h01e: data = 32'hafc20018;
10'h01f: data = 32'h24020055;
10'h020: data = 32'hafc2001c;
10'h021: data = 32'h2402004d;
10'h022: data = 32'hafc20020;
10'h023: data = 32'h2402003d;
10'h024: data = 32'hafc20024;
10'h025: data = 32'hafc00028;
10'h026: data = 32'h27c20018;
10'h027: data = 32'h00402021;
10'h028: data = 32'h0c10023c;
10'h029: data = 32'h00000000;
10'h02a: data = 32'h27c20058;
10'h02b: data = 32'h00402021;
10'h02c: data = 32'h0c10015a;
10'h02d: data = 32'h00000000;
10'h02e: data = 32'h24020045;
10'h02f: data = 32'hafc20018;
10'h030: data = 32'h24020043;
10'h031: data = 32'hafc2001c;
10'h032: data = 32'h24020048;
10'h033: data = 32'hafc20020;
10'h034: data = 32'h2402004f;
10'h035: data = 32'hafc20024;
10'h036: data = 32'h24020020;
10'h037: data = 32'hafc20028;
10'h038: data = 32'hafc0002c;
10'h039: data = 32'h27c20018;
10'h03a: data = 32'h00402021;
10'h03b: data = 32'h0c10023c;
10'h03c: data = 32'h00000000;
10'h03d: data = 32'h27c20058;
10'h03e: data = 32'h00402021;
10'h03f: data = 32'h0c10023c;
10'h040: data = 32'h00000000;
10'h041: data = 32'h2402000a;
10'h042: data = 32'hafc20018;
10'h043: data = 32'hafc0001c;
10'h044: data = 32'h27c20018;
10'h045: data = 32'h00402021;
10'h046: data = 32'h0c10023c;
10'h047: data = 32'h00000000;
10'h048: data = 32'h27c20058;
10'h049: data = 32'h00402021;
10'h04a: data = 32'h0c10009d;
10'h04b: data = 32'h00000000;
10'h04c: data = 32'hafc20010;
10'h04d: data = 32'h24020003;
10'h04e: data = 32'hafc20014;
10'h04f: data = 32'h0810005d;
10'h050: data = 32'h00000000;
10'h051: data = 32'h8fc40014;
10'h052: data = 32'h0c10006c;
10'h053: data = 32'h00000000;
10'h054: data = 32'h10400004;
10'h055: data = 32'h00000000;
10'h056: data = 32'h8fc40014;
10'h057: data = 32'h0c100130;
10'h058: data = 32'h00000000;
10'h059: data = 32'h8fc20014;
10'h05a: data = 32'h00000000;
10'h05b: data = 32'h24420001;
10'h05c: data = 32'hafc20014;
10'h05d: data = 32'h8fc20014;
10'h05e: data = 32'h8fc30010;
10'h05f: data = 32'h00000000;
10'h060: data = 32'h0062102b;
10'h061: data = 32'h1040ffef;
10'h062: data = 32'h00000000;
10'h063: data = 32'h2402000a;
10'h064: data = 32'hafc20018;
10'h065: data = 32'hafc0001c;
10'h066: data = 32'h27c20018;
10'h067: data = 32'h00402021;
10'h068: data = 32'h0c10023c;
10'h069: data = 32'h00000000;
10'h06a: data = 32'h0810001d;
10'h06b: data = 32'h00000000;
10'h06c: data = 32'h27bdffe0;
10'h06d: data = 32'hafbe0018;
10'h06e: data = 32'h03a0f021;
10'h06f: data = 32'hafc40020;
10'h070: data = 32'h8fc20020;
10'h071: data = 32'h00000000;
10'h072: data = 32'h30420001;
10'h073: data = 32'h14400004;
10'h074: data = 32'h00000000;
10'h075: data = 32'hafc00010;
10'h076: data = 32'h08100097;
10'h077: data = 32'h00000000;
10'h078: data = 32'h24020001;
10'h079: data = 32'hafc20000;
10'h07a: data = 32'h24020003;
10'h07b: data = 32'hafc20004;
10'h07c: data = 32'h0810008c;
10'h07d: data = 32'h00000000;
10'h07e: data = 32'h8fc30020;
10'h07f: data = 32'h8fc20004;
10'h080: data = 32'h00000000;
10'h081: data = 32'h14400002;
10'h082: data = 32'h0062001b;
10'h083: data = 32'h0007000d;
10'h084: data = 32'h00001010;
10'h085: data = 32'h14400002;
10'h086: data = 32'h00000000;
10'h087: data = 32'hafc00000;
10'h088: data = 32'h8fc20004;
10'h089: data = 32'h00000000;
10'h08a: data = 32'h24420002;
10'h08b: data = 32'hafc20004;
10'h08c: data = 32'h8fc20020;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h00021842;
10'h08f: data = 32'h8fc20004;
10'h090: data = 32'h00000000;
10'h091: data = 32'h0043102b;
10'h092: data = 32'h1440ffeb;
10'h093: data = 32'h00000000;
10'h094: data = 32'h8fc20000;
10'h095: data = 32'h00000000;
10'h096: data = 32'hafc20010;
10'h097: data = 32'h8fc20010;
10'h098: data = 32'h03c0e821;
10'h099: data = 32'h8fbe0018;
10'h09a: data = 32'h27bd0020;
10'h09b: data = 32'h03e00008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h27bdffe8;
10'h09e: data = 32'hafbe0010;
10'h09f: data = 32'h03a0f021;
10'h0a0: data = 32'hafc40018;
10'h0a1: data = 32'h8fc20018;
10'h0a2: data = 32'h00000000;
10'h0a3: data = 32'hafc20008;
10'h0a4: data = 32'hafc00004;
10'h0a5: data = 32'h081000af;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'h8fc20008;
10'h0a8: data = 32'h00000000;
10'h0a9: data = 32'h24420004;
10'h0aa: data = 32'hafc20008;
10'h0ab: data = 32'h8fc20004;
10'h0ac: data = 32'h00000000;
10'h0ad: data = 32'h24420001;
10'h0ae: data = 32'hafc20004;
10'h0af: data = 32'h8fc20008;
10'h0b0: data = 32'h00000000;
10'h0b1: data = 32'h8c420000;
10'h0b2: data = 32'h00000000;
10'h0b3: data = 32'h1440fff3;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'hafc00000;
10'h0b6: data = 32'h8fc20018;
10'h0b7: data = 32'h00000000;
10'h0b8: data = 32'hafc20008;
10'h0b9: data = 32'h8fc30004;
10'h0ba: data = 32'h24020001;
10'h0bb: data = 32'h14620009;
10'h0bc: data = 32'h00000000;
10'h0bd: data = 32'h8fc20008;
10'h0be: data = 32'h00000000;
10'h0bf: data = 32'h8c420000;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h2442ffd0;
10'h0c2: data = 32'hafc20000;
10'h0c3: data = 32'h0810012a;
10'h0c4: data = 32'h00000000;
10'h0c5: data = 32'h8fc30004;
10'h0c6: data = 32'h24020002;
10'h0c7: data = 32'h14620024;
10'h0c8: data = 32'h00000000;
10'h0c9: data = 32'hafc00004;
10'h0ca: data = 32'h081000d4;
10'h0cb: data = 32'h00000000;
10'h0cc: data = 32'h8fc20000;
10'h0cd: data = 32'h00000000;
10'h0ce: data = 32'h2442000a;
10'h0cf: data = 32'hafc20000;
10'h0d0: data = 32'h8fc20004;
10'h0d1: data = 32'h00000000;
10'h0d2: data = 32'h24420001;
10'h0d3: data = 32'hafc20004;
10'h0d4: data = 32'h8fc20008;
10'h0d5: data = 32'h00000000;
10'h0d6: data = 32'h8c420000;
10'h0d7: data = 32'h00000000;
10'h0d8: data = 32'h2443ffd0;
10'h0d9: data = 32'h8fc20004;
10'h0da: data = 32'h00000000;
10'h0db: data = 32'h0043102b;
10'h0dc: data = 32'h1440ffef;
10'h0dd: data = 32'h00000000;
10'h0de: data = 32'h8fc20008;
10'h0df: data = 32'h00000000;
10'h0e0: data = 32'h24420004;
10'h0e1: data = 32'hafc20008;
10'h0e2: data = 32'h8fc20008;
10'h0e3: data = 32'h00000000;
10'h0e4: data = 32'h8c430000;
10'h0e5: data = 32'h8fc20000;
10'h0e6: data = 32'h00000000;
10'h0e7: data = 32'h00621021;
10'h0e8: data = 32'h2442ffd0;
10'h0e9: data = 32'hafc20000;
10'h0ea: data = 32'h0810012a;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8fc30004;
10'h0ed: data = 32'h24020003;
10'h0ee: data = 32'h1462003b;
10'h0ef: data = 32'h00000000;
10'h0f0: data = 32'hafc00004;
10'h0f1: data = 32'h081000fb;
10'h0f2: data = 32'h00000000;
10'h0f3: data = 32'h8fc20000;
10'h0f4: data = 32'h00000000;
10'h0f5: data = 32'h24420064;
10'h0f6: data = 32'hafc20000;
10'h0f7: data = 32'h8fc20004;
10'h0f8: data = 32'h00000000;
10'h0f9: data = 32'h24420001;
10'h0fa: data = 32'hafc20004;
10'h0fb: data = 32'h8fc20008;
10'h0fc: data = 32'h00000000;
10'h0fd: data = 32'h8c420000;
10'h0fe: data = 32'h00000000;
10'h0ff: data = 32'h2443ffd0;
10'h100: data = 32'h8fc20004;
10'h101: data = 32'h00000000;
10'h102: data = 32'h0043102b;
10'h103: data = 32'h1440ffef;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8fc20008;
10'h106: data = 32'h00000000;
10'h107: data = 32'h24420004;
10'h108: data = 32'hafc20008;
10'h109: data = 32'hafc00004;
10'h10a: data = 32'h08100114;
10'h10b: data = 32'h00000000;
10'h10c: data = 32'h8fc20000;
10'h10d: data = 32'h00000000;
10'h10e: data = 32'h2442000a;
10'h10f: data = 32'hafc20000;
10'h110: data = 32'h8fc20004;
10'h111: data = 32'h00000000;
10'h112: data = 32'h24420001;
10'h113: data = 32'hafc20004;
10'h114: data = 32'h8fc20008;
10'h115: data = 32'h00000000;
10'h116: data = 32'h8c420000;
10'h117: data = 32'h00000000;
10'h118: data = 32'h2443ffd0;
10'h119: data = 32'h8fc20004;
10'h11a: data = 32'h00000000;
10'h11b: data = 32'h0043102b;
10'h11c: data = 32'h1440ffef;
10'h11d: data = 32'h00000000;
10'h11e: data = 32'h8fc20008;
10'h11f: data = 32'h00000000;
10'h120: data = 32'h24420004;
10'h121: data = 32'hafc20008;
10'h122: data = 32'h8fc20008;
10'h123: data = 32'h00000000;
10'h124: data = 32'h8c430000;
10'h125: data = 32'h8fc20000;
10'h126: data = 32'h00000000;
10'h127: data = 32'h00621021;
10'h128: data = 32'h2442ffd0;
10'h129: data = 32'hafc20000;
10'h12a: data = 32'h8fc20000;
10'h12b: data = 32'h03c0e821;
10'h12c: data = 32'h8fbe0010;
10'h12d: data = 32'h27bd0018;
10'h12e: data = 32'h03e00008;
10'h12f: data = 32'h00000000;
10'h130: data = 32'h27bdffd0;
10'h131: data = 32'hafbf002c;
10'h132: data = 32'hafbe0028;
10'h133: data = 32'h03a0f021;
10'h134: data = 32'hafc40030;
10'h135: data = 32'hafc00010;
10'h136: data = 32'h08100140;
10'h137: data = 32'h00000000;
10'h138: data = 32'h8fc20030;
10'h139: data = 32'h00000000;
10'h13a: data = 32'h2442fff6;
10'h13b: data = 32'hafc20030;
10'h13c: data = 32'h8fc20010;
10'h13d: data = 32'h00000000;
10'h13e: data = 32'h24420001;
10'h13f: data = 32'hafc20010;
10'h140: data = 32'h8fc20030;
10'h141: data = 32'h00000000;
10'h142: data = 32'h2c42000a;
10'h143: data = 32'h1040fff4;
10'h144: data = 32'h00000000;
10'h145: data = 32'h8fc20010;
10'h146: data = 32'h00000000;
10'h147: data = 32'h24420030;
10'h148: data = 32'hafc20014;
10'h149: data = 32'h8fc20030;
10'h14a: data = 32'h00000000;
10'h14b: data = 32'h24420030;
10'h14c: data = 32'hafc20018;
10'h14d: data = 32'h24020020;
10'h14e: data = 32'hafc2001c;
10'h14f: data = 32'hafc00020;
10'h150: data = 32'h27c20014;
10'h151: data = 32'h00402021;
10'h152: data = 32'h0c10023c;
10'h153: data = 32'h00000000;
10'h154: data = 32'h03c0e821;
10'h155: data = 32'h8fbf002c;
10'h156: data = 32'h8fbe0028;
10'h157: data = 32'h27bd0030;
10'h158: data = 32'h03e00008;
10'h159: data = 32'h00000000;
10'h15a: data = 32'h27bdfff8;
10'h15b: data = 32'hafbe0000;
10'h15c: data = 32'h03a0f021;
10'h15d: data = 32'hafc40008;
10'h15e: data = 32'h24020308;
10'h15f: data = 32'hac400000;
10'h160: data = 32'h2403030c;
10'h161: data = 32'h24020001;
10'h162: data = 32'hac620000;
10'h163: data = 32'h24030308;
10'h164: data = 32'h24020001;
10'h165: data = 32'hac620000;
10'h166: data = 32'h24020308;
10'h167: data = 32'hac400000;
10'h168: data = 32'h24030308;
10'h169: data = 32'h24020001;
10'h16a: data = 32'hac620000;
10'h16b: data = 32'h08100172;
10'h16c: data = 32'h00000000;
10'h16d: data = 32'h24020308;
10'h16e: data = 32'hac400000;
10'h16f: data = 32'h24030308;
10'h170: data = 32'h24020001;
10'h171: data = 32'hac620000;
10'h172: data = 32'h24020310;
10'h173: data = 32'h8c430000;
10'h174: data = 32'h2402ffff;
10'h175: data = 32'h1062fff7;
10'h176: data = 32'h00000000;
10'h177: data = 32'h08100220;
10'h178: data = 32'h00000000;
10'h179: data = 32'h8fc20008;
10'h17a: data = 32'h00000000;
10'h17b: data = 32'h8c420000;
10'h17c: data = 32'h00000000;
10'h17d: data = 32'h10400012;
10'h17e: data = 32'h00000000;
10'h17f: data = 32'h8fc20008;
10'h180: data = 32'h00000000;
10'h181: data = 32'h8c420000;
10'h182: data = 32'h00000000;
10'h183: data = 32'h2c42001b;
10'h184: data = 32'h1040000b;
10'h185: data = 32'h00000000;
10'h186: data = 32'h8fc20008;
10'h187: data = 32'h00000000;
10'h188: data = 32'h8c420000;
10'h189: data = 32'h00000000;
10'h18a: data = 32'h24430040;
10'h18b: data = 32'h8fc20008;
10'h18c: data = 32'h00000000;
10'h18d: data = 32'hac430000;
10'h18e: data = 32'h08100217;
10'h18f: data = 32'h00000000;
10'h190: data = 32'h8fc20008;
10'h191: data = 32'h00000000;
10'h192: data = 32'h8c420000;
10'h193: data = 32'h00000000;
10'h194: data = 32'h2c420030;
10'h195: data = 32'h14400010;
10'h196: data = 32'h00000000;
10'h197: data = 32'h8fc20008;
10'h198: data = 32'h00000000;
10'h199: data = 32'h8c420000;
10'h19a: data = 32'h00000000;
10'h19b: data = 32'h2c42003a;
10'h19c: data = 32'h10400009;
10'h19d: data = 32'h00000000;
10'h19e: data = 32'h8fc20008;
10'h19f: data = 32'h00000000;
10'h1a0: data = 32'h8c430000;
10'h1a1: data = 32'h8fc20008;
10'h1a2: data = 32'h00000000;
10'h1a3: data = 32'hac430000;
10'h1a4: data = 32'h08100217;
10'h1a5: data = 32'h00000000;
10'h1a6: data = 32'h8fc20008;
10'h1a7: data = 32'h00000000;
10'h1a8: data = 32'h8c420000;
10'h1a9: data = 32'h00000000;
10'h1aa: data = 32'h14400006;
10'h1ab: data = 32'h00000000;
10'h1ac: data = 32'h8fc30008;
10'h1ad: data = 32'h24020040;
10'h1ae: data = 32'hac620000;
10'h1af: data = 32'h08100217;
10'h1b0: data = 32'h00000000;
10'h1b1: data = 32'h8fc20008;
10'h1b2: data = 32'h00000000;
10'h1b3: data = 32'h8c430000;
10'h1b4: data = 32'h2402001b;
10'h1b5: data = 32'h14620006;
10'h1b6: data = 32'h00000000;
10'h1b7: data = 32'h8fc30008;
10'h1b8: data = 32'h2402005b;
10'h1b9: data = 32'hac620000;
10'h1ba: data = 32'h08100217;
10'h1bb: data = 32'h00000000;
10'h1bc: data = 32'h8fc20008;
10'h1bd: data = 32'h00000000;
10'h1be: data = 32'h8c430000;
10'h1bf: data = 32'h2402001d;
10'h1c0: data = 32'h14620006;
10'h1c1: data = 32'h00000000;
10'h1c2: data = 32'h8fc30008;
10'h1c3: data = 32'h2402005d;
10'h1c4: data = 32'hac620000;
10'h1c5: data = 32'h08100217;
10'h1c6: data = 32'h00000000;
10'h1c7: data = 32'h8fc20008;
10'h1c8: data = 32'h00000000;
10'h1c9: data = 32'h8c420000;
10'h1ca: data = 32'h00000000;
10'h1cb: data = 32'h2c420020;
10'h1cc: data = 32'h14400010;
10'h1cd: data = 32'h00000000;
10'h1ce: data = 32'h8fc20008;
10'h1cf: data = 32'h00000000;
10'h1d0: data = 32'h8c420000;
10'h1d1: data = 32'h00000000;
10'h1d2: data = 32'h2c420030;
10'h1d3: data = 32'h10400009;
10'h1d4: data = 32'h00000000;
10'h1d5: data = 32'h8fc20008;
10'h1d6: data = 32'h00000000;
10'h1d7: data = 32'h8c430000;
10'h1d8: data = 32'h8fc20008;
10'h1d9: data = 32'h00000000;
10'h1da: data = 32'hac430000;
10'h1db: data = 32'h08100217;
10'h1dc: data = 32'h00000000;
10'h1dd: data = 32'h8fc20008;
10'h1de: data = 32'h00000000;
10'h1df: data = 32'h8c430000;
10'h1e0: data = 32'h2402003a;
10'h1e1: data = 32'h14620006;
10'h1e2: data = 32'h00000000;
10'h1e3: data = 32'h8fc30008;
10'h1e4: data = 32'h2402003f;
10'h1e5: data = 32'hac620000;
10'h1e6: data = 32'h08100217;
10'h1e7: data = 32'h00000000;
10'h1e8: data = 32'h8fc20008;
10'h1e9: data = 32'h00000000;
10'h1ea: data = 32'h8c430000;
10'h1eb: data = 32'h2402003b;
10'h1ec: data = 32'h14620006;
10'h1ed: data = 32'h00000000;
10'h1ee: data = 32'h8fc30008;
10'h1ef: data = 32'h2402003d;
10'h1f0: data = 32'hac620000;
10'h1f1: data = 32'h08100217;
10'h1f2: data = 32'h00000000;
10'h1f3: data = 32'h8fc20008;
10'h1f4: data = 32'h00000000;
10'h1f5: data = 32'h8c430000;
10'h1f6: data = 32'h2402003c;
10'h1f7: data = 32'h14620006;
10'h1f8: data = 32'h00000000;
10'h1f9: data = 32'h8fc30008;
10'h1fa: data = 32'h2402003b;
10'h1fb: data = 32'hac620000;
10'h1fc: data = 32'h08100217;
10'h1fd: data = 32'h00000000;
10'h1fe: data = 32'h8fc20008;
10'h1ff: data = 32'h00000000;
10'h200: data = 32'h8c430000;
10'h201: data = 32'h2402003d;
10'h202: data = 32'h14620006;
10'h203: data = 32'h00000000;
10'h204: data = 32'h8fc30008;
10'h205: data = 32'h2402003a;
10'h206: data = 32'hac620000;
10'h207: data = 32'h08100217;
10'h208: data = 32'h00000000;
10'h209: data = 32'h8fc20008;
10'h20a: data = 32'h00000000;
10'h20b: data = 32'h8c430000;
10'h20c: data = 32'h2402003e;
10'h20d: data = 32'h14620006;
10'h20e: data = 32'h00000000;
10'h20f: data = 32'h8fc30008;
10'h210: data = 32'h2402000a;
10'h211: data = 32'hac620000;
10'h212: data = 32'h08100217;
10'h213: data = 32'h00000000;
10'h214: data = 32'h8fc30008;
10'h215: data = 32'h24020040;
10'h216: data = 32'hac620000;
10'h217: data = 32'h24020308;
10'h218: data = 32'hac400000;
10'h219: data = 32'h24030308;
10'h21a: data = 32'h24020001;
10'h21b: data = 32'hac620000;
10'h21c: data = 32'h8fc20008;
10'h21d: data = 32'h00000000;
10'h21e: data = 32'h24420004;
10'h21f: data = 32'hafc20008;
10'h220: data = 32'h24020310;
10'h221: data = 32'h8c430000;
10'h222: data = 32'h8fc20008;
10'h223: data = 32'h00000000;
10'h224: data = 32'hac430000;
10'h225: data = 32'h8fc20008;
10'h226: data = 32'h00000000;
10'h227: data = 32'h8c430000;
10'h228: data = 32'h2402003e;
10'h229: data = 32'h1462ff4f;
10'h22a: data = 32'h00000000;
10'h22b: data = 32'h8fc20008;
10'h22c: data = 32'h00000000;
10'h22d: data = 32'hac400000;
10'h22e: data = 32'h24020308;
10'h22f: data = 32'hac400000;
10'h230: data = 32'h2402030c;
10'h231: data = 32'hac400000;
10'h232: data = 32'h24030308;
10'h233: data = 32'h24020001;
10'h234: data = 32'hac620000;
10'h235: data = 32'h24020308;
10'h236: data = 32'hac400000;
10'h237: data = 32'h03c0e821;
10'h238: data = 32'h8fbe0000;
10'h239: data = 32'h27bd0008;
10'h23a: data = 32'h03e00008;
10'h23b: data = 32'h00000000;
10'h23c: data = 32'h27bdfff8;
10'h23d: data = 32'hafbe0000;
10'h23e: data = 32'h03a0f021;
10'h23f: data = 32'hafc40008;
10'h240: data = 32'h081002fe;
10'h241: data = 32'h00000000;
10'h242: data = 32'h24020300;
10'h243: data = 32'hac400000;
10'h244: data = 32'h8fc20008;
10'h245: data = 32'h00000000;
10'h246: data = 32'h8c420000;
10'h247: data = 32'h00000000;
10'h248: data = 32'h2c420041;
10'h249: data = 32'h14400011;
10'h24a: data = 32'h00000000;
10'h24b: data = 32'h8fc20008;
10'h24c: data = 32'h00000000;
10'h24d: data = 32'h8c420000;
10'h24e: data = 32'h00000000;
10'h24f: data = 32'h2c42005b;
10'h250: data = 32'h1040000a;
10'h251: data = 32'h00000000;
10'h252: data = 32'h24030304;
10'h253: data = 32'h8fc20008;
10'h254: data = 32'h00000000;
10'h255: data = 32'h8c420000;
10'h256: data = 32'h00000000;
10'h257: data = 32'h2442ffc0;
10'h258: data = 32'hac620000;
10'h259: data = 32'h081002f7;
10'h25a: data = 32'h00000000;
10'h25b: data = 32'h8fc20008;
10'h25c: data = 32'h00000000;
10'h25d: data = 32'h8c420000;
10'h25e: data = 32'h00000000;
10'h25f: data = 32'h2c420061;
10'h260: data = 32'h14400011;
10'h261: data = 32'h00000000;
10'h262: data = 32'h8fc20008;
10'h263: data = 32'h00000000;
10'h264: data = 32'h8c420000;
10'h265: data = 32'h00000000;
10'h266: data = 32'h2c42007b;
10'h267: data = 32'h1040000a;
10'h268: data = 32'h00000000;
10'h269: data = 32'h24030304;
10'h26a: data = 32'h8fc20008;
10'h26b: data = 32'h00000000;
10'h26c: data = 32'h8c420000;
10'h26d: data = 32'h00000000;
10'h26e: data = 32'h2442ffa0;
10'h26f: data = 32'hac620000;
10'h270: data = 32'h081002f7;
10'h271: data = 32'h00000000;
10'h272: data = 32'h8fc20008;
10'h273: data = 32'h00000000;
10'h274: data = 32'h8c420000;
10'h275: data = 32'h00000000;
10'h276: data = 32'h2c420030;
10'h277: data = 32'h14400010;
10'h278: data = 32'h00000000;
10'h279: data = 32'h8fc20008;
10'h27a: data = 32'h00000000;
10'h27b: data = 32'h8c420000;
10'h27c: data = 32'h00000000;
10'h27d: data = 32'h2c42003a;
10'h27e: data = 32'h10400009;
10'h27f: data = 32'h00000000;
10'h280: data = 32'h24020304;
10'h281: data = 32'h8fc30008;
10'h282: data = 32'h00000000;
10'h283: data = 32'h8c630000;
10'h284: data = 32'h00000000;
10'h285: data = 32'hac430000;
10'h286: data = 32'h081002f7;
10'h287: data = 32'h00000000;
10'h288: data = 32'h8fc20008;
10'h289: data = 32'h00000000;
10'h28a: data = 32'h8c430000;
10'h28b: data = 32'h24020040;
10'h28c: data = 32'h14620005;
10'h28d: data = 32'h00000000;
10'h28e: data = 32'h24020304;
10'h28f: data = 32'hac400000;
10'h290: data = 32'h081002f7;
10'h291: data = 32'h00000000;
10'h292: data = 32'h8fc20008;
10'h293: data = 32'h00000000;
10'h294: data = 32'h8c430000;
10'h295: data = 32'h2402005b;
10'h296: data = 32'h14620006;
10'h297: data = 32'h00000000;
10'h298: data = 32'h24030304;
10'h299: data = 32'h2402001b;
10'h29a: data = 32'hac620000;
10'h29b: data = 32'h081002f7;
10'h29c: data = 32'h00000000;
10'h29d: data = 32'h8fc20008;
10'h29e: data = 32'h00000000;
10'h29f: data = 32'h8c430000;
10'h2a0: data = 32'h2402005d;
10'h2a1: data = 32'h14620006;
10'h2a2: data = 32'h00000000;
10'h2a3: data = 32'h24030304;
10'h2a4: data = 32'h2402001d;
10'h2a5: data = 32'hac620000;
10'h2a6: data = 32'h081002f7;
10'h2a7: data = 32'h00000000;
10'h2a8: data = 32'h8fc20008;
10'h2a9: data = 32'h00000000;
10'h2aa: data = 32'h8c420000;
10'h2ab: data = 32'h00000000;
10'h2ac: data = 32'h2c420020;
10'h2ad: data = 32'h14400010;
10'h2ae: data = 32'h00000000;
10'h2af: data = 32'h8fc20008;
10'h2b0: data = 32'h00000000;
10'h2b1: data = 32'h8c420000;
10'h2b2: data = 32'h00000000;
10'h2b3: data = 32'h2c420030;
10'h2b4: data = 32'h10400009;
10'h2b5: data = 32'h00000000;
10'h2b6: data = 32'h24020304;
10'h2b7: data = 32'h8fc30008;
10'h2b8: data = 32'h00000000;
10'h2b9: data = 32'h8c630000;
10'h2ba: data = 32'h00000000;
10'h2bb: data = 32'hac430000;
10'h2bc: data = 32'h081002f7;
10'h2bd: data = 32'h00000000;
10'h2be: data = 32'h8fc20008;
10'h2bf: data = 32'h00000000;
10'h2c0: data = 32'h8c430000;
10'h2c1: data = 32'h2402003f;
10'h2c2: data = 32'h14620006;
10'h2c3: data = 32'h00000000;
10'h2c4: data = 32'h24030304;
10'h2c5: data = 32'h2402003a;
10'h2c6: data = 32'hac620000;
10'h2c7: data = 32'h081002f7;
10'h2c8: data = 32'h00000000;
10'h2c9: data = 32'h8fc20008;
10'h2ca: data = 32'h00000000;
10'h2cb: data = 32'h8c430000;
10'h2cc: data = 32'h2402003d;
10'h2cd: data = 32'h14620006;
10'h2ce: data = 32'h00000000;
10'h2cf: data = 32'h24030304;
10'h2d0: data = 32'h2402003b;
10'h2d1: data = 32'hac620000;
10'h2d2: data = 32'h081002f7;
10'h2d3: data = 32'h00000000;
10'h2d4: data = 32'h8fc20008;
10'h2d5: data = 32'h00000000;
10'h2d6: data = 32'h8c430000;
10'h2d7: data = 32'h2402003b;
10'h2d8: data = 32'h14620006;
10'h2d9: data = 32'h00000000;
10'h2da: data = 32'h24030304;
10'h2db: data = 32'h2402003c;
10'h2dc: data = 32'hac620000;
10'h2dd: data = 32'h081002f7;
10'h2de: data = 32'h00000000;
10'h2df: data = 32'h8fc20008;
10'h2e0: data = 32'h00000000;
10'h2e1: data = 32'h8c430000;
10'h2e2: data = 32'h2402003a;
10'h2e3: data = 32'h14620006;
10'h2e4: data = 32'h00000000;
10'h2e5: data = 32'h24030304;
10'h2e6: data = 32'h2402003d;
10'h2e7: data = 32'hac620000;
10'h2e8: data = 32'h081002f7;
10'h2e9: data = 32'h00000000;
10'h2ea: data = 32'h8fc20008;
10'h2eb: data = 32'h00000000;
10'h2ec: data = 32'h8c430000;
10'h2ed: data = 32'h2402000a;
10'h2ee: data = 32'h14620006;
10'h2ef: data = 32'h00000000;
10'h2f0: data = 32'h24030304;
10'h2f1: data = 32'h2402003e;
10'h2f2: data = 32'hac620000;
10'h2f3: data = 32'h081002f7;
10'h2f4: data = 32'h00000000;
10'h2f5: data = 32'h24020304;
10'h2f6: data = 32'hac400000;
10'h2f7: data = 32'h24030300;
10'h2f8: data = 32'h24020001;
10'h2f9: data = 32'hac620000;
10'h2fa: data = 32'h8fc20008;
10'h2fb: data = 32'h00000000;
10'h2fc: data = 32'h24420004;
10'h2fd: data = 32'hafc20008;
10'h2fe: data = 32'h8fc20008;
10'h2ff: data = 32'h00000000;
10'h300: data = 32'h8c420000;
10'h301: data = 32'h00000000;
10'h302: data = 32'h1440ff3f;
10'h303: data = 32'h00000000;
10'h304: data = 32'h03c0e821;
10'h305: data = 32'h8fbe0000;
10'h306: data = 32'h27bd0008;
10'h307: data = 32'h03e00008;
10'h308: data = 32'h00000000;
10'h309: data = 32'h00000000;
10'h30a: data = 32'h00000000;
10'h30b: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408c20;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdff60;
10'h009: data = 32'hafbf009c;
10'h00a: data = 32'hafbe0098;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h24020048;
10'h00d: data = 32'hafc20018;
10'h00e: data = 32'h24020045;
10'h00f: data = 32'hafc2001c;
10'h010: data = 32'h2402004c;
10'h011: data = 32'hafc20020;
10'h012: data = 32'h2402004c;
10'h013: data = 32'hafc20024;
10'h014: data = 32'h2402004f;
10'h015: data = 32'hafc20028;
10'h016: data = 32'h2402000a;
10'h017: data = 32'hafc2002c;
10'h018: data = 32'hafc00030;
10'h019: data = 32'h27c20018;
10'h01a: data = 32'h00402021;
10'h01b: data = 32'h0c10023c;
10'h01c: data = 32'h00000000;
10'h01d: data = 32'h2402004e;
10'h01e: data = 32'hafc20018;
10'h01f: data = 32'h24020055;
10'h020: data = 32'hafc2001c;
10'h021: data = 32'h2402004d;
10'h022: data = 32'hafc20020;
10'h023: data = 32'h2402003d;
10'h024: data = 32'hafc20024;
10'h025: data = 32'hafc00028;
10'h026: data = 32'h27c20018;
10'h027: data = 32'h00402021;
10'h028: data = 32'h0c10023c;
10'h029: data = 32'h00000000;
10'h02a: data = 32'h27c20058;
10'h02b: data = 32'h00402021;
10'h02c: data = 32'h0c10015a;
10'h02d: data = 32'h00000000;
10'h02e: data = 32'h24020045;
10'h02f: data = 32'hafc20018;
10'h030: data = 32'h24020043;
10'h031: data = 32'hafc2001c;
10'h032: data = 32'h24020048;
10'h033: data = 32'hafc20020;
10'h034: data = 32'h2402004f;
10'h035: data = 32'hafc20024;
10'h036: data = 32'h24020020;
10'h037: data = 32'hafc20028;
10'h038: data = 32'hafc0002c;
10'h039: data = 32'h27c20018;
10'h03a: data = 32'h00402021;
10'h03b: data = 32'h0c10023c;
10'h03c: data = 32'h00000000;
10'h03d: data = 32'h27c20058;
10'h03e: data = 32'h00402021;
10'h03f: data = 32'h0c10023c;
10'h040: data = 32'h00000000;
10'h041: data = 32'h2402000a;
10'h042: data = 32'hafc20018;
10'h043: data = 32'hafc0001c;
10'h044: data = 32'h27c20018;
10'h045: data = 32'h00402021;
10'h046: data = 32'h0c10023c;
10'h047: data = 32'h00000000;
10'h048: data = 32'h27c20058;
10'h049: data = 32'h00402021;
10'h04a: data = 32'h0c10009d;
10'h04b: data = 32'h00000000;
10'h04c: data = 32'hafc20010;
10'h04d: data = 32'h24020003;
10'h04e: data = 32'hafc20014;
10'h04f: data = 32'h0810005d;
10'h050: data = 32'h00000000;
10'h051: data = 32'h8fc40014;
10'h052: data = 32'h0c10006c;
10'h053: data = 32'h00000000;
10'h054: data = 32'h10400004;
10'h055: data = 32'h00000000;
10'h056: data = 32'h8fc40014;
10'h057: data = 32'h0c100130;
10'h058: data = 32'h00000000;
10'h059: data = 32'h8fc20014;
10'h05a: data = 32'h00000000;
10'h05b: data = 32'h24420001;
10'h05c: data = 32'hafc20014;
10'h05d: data = 32'h8fc20014;
10'h05e: data = 32'h8fc30010;
10'h05f: data = 32'h00000000;
10'h060: data = 32'h0062102b;
10'h061: data = 32'h1040ffef;
10'h062: data = 32'h00000000;
10'h063: data = 32'h2402000a;
10'h064: data = 32'hafc20018;
10'h065: data = 32'hafc0001c;
10'h066: data = 32'h27c20018;
10'h067: data = 32'h00402021;
10'h068: data = 32'h0c10023c;
10'h069: data = 32'h00000000;
10'h06a: data = 32'h0810001d;
10'h06b: data = 32'h00000000;
10'h06c: data = 32'h27bdffe0;
10'h06d: data = 32'hafbe0018;
10'h06e: data = 32'h03a0f021;
10'h06f: data = 32'hafc40020;
10'h070: data = 32'h8fc20020;
10'h071: data = 32'h00000000;
10'h072: data = 32'h30420001;
10'h073: data = 32'h14400004;
10'h074: data = 32'h00000000;
10'h075: data = 32'hafc00010;
10'h076: data = 32'h08100097;
10'h077: data = 32'h00000000;
10'h078: data = 32'h24020001;
10'h079: data = 32'hafc20000;
10'h07a: data = 32'h24020003;
10'h07b: data = 32'hafc20004;
10'h07c: data = 32'h0810008c;
10'h07d: data = 32'h00000000;
10'h07e: data = 32'h8fc30020;
10'h07f: data = 32'h8fc20004;
10'h080: data = 32'h00000000;
10'h081: data = 32'h14400002;
10'h082: data = 32'h0062001b;
10'h083: data = 32'h0007000d;
10'h084: data = 32'h00001010;
10'h085: data = 32'h14400002;
10'h086: data = 32'h00000000;
10'h087: data = 32'hafc00000;
10'h088: data = 32'h8fc20004;
10'h089: data = 32'h00000000;
10'h08a: data = 32'h24420002;
10'h08b: data = 32'hafc20004;
10'h08c: data = 32'h8fc20020;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h00021842;
10'h08f: data = 32'h8fc20004;
10'h090: data = 32'h00000000;
10'h091: data = 32'h0043102b;
10'h092: data = 32'h1440ffeb;
10'h093: data = 32'h00000000;
10'h094: data = 32'h8fc20000;
10'h095: data = 32'h00000000;
10'h096: data = 32'hafc20010;
10'h097: data = 32'h8fc20010;
10'h098: data = 32'h03c0e821;
10'h099: data = 32'h8fbe0018;
10'h09a: data = 32'h27bd0020;
10'h09b: data = 32'h03e00008;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h27bdffe8;
10'h09e: data = 32'hafbe0010;
10'h09f: data = 32'h03a0f021;
10'h0a0: data = 32'hafc40018;
10'h0a1: data = 32'h8fc20018;
10'h0a2: data = 32'h00000000;
10'h0a3: data = 32'hafc20008;
10'h0a4: data = 32'hafc00004;
10'h0a5: data = 32'h081000af;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'h8fc20008;
10'h0a8: data = 32'h00000000;
10'h0a9: data = 32'h24420004;
10'h0aa: data = 32'hafc20008;
10'h0ab: data = 32'h8fc20004;
10'h0ac: data = 32'h00000000;
10'h0ad: data = 32'h24420001;
10'h0ae: data = 32'hafc20004;
10'h0af: data = 32'h8fc20008;
10'h0b0: data = 32'h00000000;
10'h0b1: data = 32'h8c420000;
10'h0b2: data = 32'h00000000;
10'h0b3: data = 32'h1440fff3;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'hafc00000;
10'h0b6: data = 32'h8fc20018;
10'h0b7: data = 32'h00000000;
10'h0b8: data = 32'hafc20008;
10'h0b9: data = 32'h8fc30004;
10'h0ba: data = 32'h24020001;
10'h0bb: data = 32'h14620009;
10'h0bc: data = 32'h00000000;
10'h0bd: data = 32'h8fc20008;
10'h0be: data = 32'h00000000;
10'h0bf: data = 32'h8c420000;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h2442ffd0;
10'h0c2: data = 32'hafc20000;
10'h0c3: data = 32'h0810012a;
10'h0c4: data = 32'h00000000;
10'h0c5: data = 32'h8fc30004;
10'h0c6: data = 32'h24020002;
10'h0c7: data = 32'h14620024;
10'h0c8: data = 32'h00000000;
10'h0c9: data = 32'hafc00004;
10'h0ca: data = 32'h081000d4;
10'h0cb: data = 32'h00000000;
10'h0cc: data = 32'h8fc20000;
10'h0cd: data = 32'h00000000;
10'h0ce: data = 32'h2442000a;
10'h0cf: data = 32'hafc20000;
10'h0d0: data = 32'h8fc20004;
10'h0d1: data = 32'h00000000;
10'h0d2: data = 32'h24420001;
10'h0d3: data = 32'hafc20004;
10'h0d4: data = 32'h8fc20008;
10'h0d5: data = 32'h00000000;
10'h0d6: data = 32'h8c420000;
10'h0d7: data = 32'h00000000;
10'h0d8: data = 32'h2443ffd0;
10'h0d9: data = 32'h8fc20004;
10'h0da: data = 32'h00000000;
10'h0db: data = 32'h0043102b;
10'h0dc: data = 32'h1440ffef;
10'h0dd: data = 32'h00000000;
10'h0de: data = 32'h8fc20008;
10'h0df: data = 32'h00000000;
10'h0e0: data = 32'h24420004;
10'h0e1: data = 32'hafc20008;
10'h0e2: data = 32'h8fc20008;
10'h0e3: data = 32'h00000000;
10'h0e4: data = 32'h8c430000;
10'h0e5: data = 32'h8fc20000;
10'h0e6: data = 32'h00000000;
10'h0e7: data = 32'h00621021;
10'h0e8: data = 32'h2442ffd0;
10'h0e9: data = 32'hafc20000;
10'h0ea: data = 32'h0810012a;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8fc30004;
10'h0ed: data = 32'h24020003;
10'h0ee: data = 32'h1462003b;
10'h0ef: data = 32'h00000000;
10'h0f0: data = 32'hafc00004;
10'h0f1: data = 32'h081000fb;
10'h0f2: data = 32'h00000000;
10'h0f3: data = 32'h8fc20000;
10'h0f4: data = 32'h00000000;
10'h0f5: data = 32'h24420064;
10'h0f6: data = 32'hafc20000;
10'h0f7: data = 32'h8fc20004;
10'h0f8: data = 32'h00000000;
10'h0f9: data = 32'h24420001;
10'h0fa: data = 32'hafc20004;
10'h0fb: data = 32'h8fc20008;
10'h0fc: data = 32'h00000000;
10'h0fd: data = 32'h8c420000;
10'h0fe: data = 32'h00000000;
10'h0ff: data = 32'h2443ffd0;
10'h100: data = 32'h8fc20004;
10'h101: data = 32'h00000000;
10'h102: data = 32'h0043102b;
10'h103: data = 32'h1440ffef;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8fc20008;
10'h106: data = 32'h00000000;
10'h107: data = 32'h24420004;
10'h108: data = 32'hafc20008;
10'h109: data = 32'hafc00004;
10'h10a: data = 32'h08100114;
10'h10b: data = 32'h00000000;
10'h10c: data = 32'h8fc20000;
10'h10d: data = 32'h00000000;
10'h10e: data = 32'h2442000a;
10'h10f: data = 32'hafc20000;
10'h110: data = 32'h8fc20004;
10'h111: data = 32'h00000000;
10'h112: data = 32'h24420001;
10'h113: data = 32'hafc20004;
10'h114: data = 32'h8fc20008;
10'h115: data = 32'h00000000;
10'h116: data = 32'h8c420000;
10'h117: data = 32'h00000000;
10'h118: data = 32'h2443ffd0;
10'h119: data = 32'h8fc20004;
10'h11a: data = 32'h00000000;
10'h11b: data = 32'h0043102b;
10'h11c: data = 32'h1440ffef;
10'h11d: data = 32'h00000000;
10'h11e: data = 32'h8fc20008;
10'h11f: data = 32'h00000000;
10'h120: data = 32'h24420004;
10'h121: data = 32'hafc20008;
10'h122: data = 32'h8fc20008;
10'h123: data = 32'h00000000;
10'h124: data = 32'h8c430000;
10'h125: data = 32'h8fc20000;
10'h126: data = 32'h00000000;
10'h127: data = 32'h00621021;
10'h128: data = 32'h2442ffd0;
10'h129: data = 32'hafc20000;
10'h12a: data = 32'h8fc20000;
10'h12b: data = 32'h03c0e821;
10'h12c: data = 32'h8fbe0010;
10'h12d: data = 32'h27bd0018;
10'h12e: data = 32'h03e00008;
10'h12f: data = 32'h00000000;
10'h130: data = 32'h27bdffd0;
10'h131: data = 32'hafbf002c;
10'h132: data = 32'hafbe0028;
10'h133: data = 32'h03a0f021;
10'h134: data = 32'hafc40030;
10'h135: data = 32'hafc00010;
10'h136: data = 32'h08100140;
10'h137: data = 32'h00000000;
10'h138: data = 32'h8fc20030;
10'h139: data = 32'h00000000;
10'h13a: data = 32'h2442fff6;
10'h13b: data = 32'hafc20030;
10'h13c: data = 32'h8fc20010;
10'h13d: data = 32'h00000000;
10'h13e: data = 32'h24420001;
10'h13f: data = 32'hafc20010;
10'h140: data = 32'h8fc20030;
10'h141: data = 32'h00000000;
10'h142: data = 32'h2c42000a;
10'h143: data = 32'h1040fff4;
10'h144: data = 32'h00000000;
10'h145: data = 32'h8fc20010;
10'h146: data = 32'h00000000;
10'h147: data = 32'h24420030;
10'h148: data = 32'hafc20014;
10'h149: data = 32'h8fc20030;
10'h14a: data = 32'h00000000;
10'h14b: data = 32'h24420030;
10'h14c: data = 32'hafc20018;
10'h14d: data = 32'h24020020;
10'h14e: data = 32'hafc2001c;
10'h14f: data = 32'hafc00020;
10'h150: data = 32'h27c20014;
10'h151: data = 32'h00402021;
10'h152: data = 32'h0c10023c;
10'h153: data = 32'h00000000;
10'h154: data = 32'h03c0e821;
10'h155: data = 32'h8fbf002c;
10'h156: data = 32'h8fbe0028;
10'h157: data = 32'h27bd0030;
10'h158: data = 32'h03e00008;
10'h159: data = 32'h00000000;
10'h15a: data = 32'h27bdfff8;
10'h15b: data = 32'hafbe0000;
10'h15c: data = 32'h03a0f021;
10'h15d: data = 32'hafc40008;
10'h15e: data = 32'h24020308;
10'h15f: data = 32'hac400000;
10'h160: data = 32'h2403030c;
10'h161: data = 32'h24020001;
10'h162: data = 32'hac620000;
10'h163: data = 32'h24030308;
10'h164: data = 32'h24020001;
10'h165: data = 32'hac620000;
10'h166: data = 32'h24020308;
10'h167: data = 32'hac400000;
10'h168: data = 32'h24030308;
10'h169: data = 32'h24020001;
10'h16a: data = 32'hac620000;
10'h16b: data = 32'h08100172;
10'h16c: data = 32'h00000000;
10'h16d: data = 32'h24020308;
10'h16e: data = 32'hac400000;
10'h16f: data = 32'h24030308;
10'h170: data = 32'h24020001;
10'h171: data = 32'hac620000;
10'h172: data = 32'h24020310;
10'h173: data = 32'h8c430000;
10'h174: data = 32'h2402ffff;
10'h175: data = 32'h1062fff7;
10'h176: data = 32'h00000000;
10'h177: data = 32'h08100220;
10'h178: data = 32'h00000000;
10'h179: data = 32'h8fc20008;
10'h17a: data = 32'h00000000;
10'h17b: data = 32'h8c420000;
10'h17c: data = 32'h00000000;
10'h17d: data = 32'h10400012;
10'h17e: data = 32'h00000000;
10'h17f: data = 32'h8fc20008;
10'h180: data = 32'h00000000;
10'h181: data = 32'h8c420000;
10'h182: data = 32'h00000000;
10'h183: data = 32'h2c42001b;
10'h184: data = 32'h1040000b;
10'h185: data = 32'h00000000;
10'h186: data = 32'h8fc20008;
10'h187: data = 32'h00000000;
10'h188: data = 32'h8c420000;
10'h189: data = 32'h00000000;
10'h18a: data = 32'h24430040;
10'h18b: data = 32'h8fc20008;
10'h18c: data = 32'h00000000;
10'h18d: data = 32'hac430000;
10'h18e: data = 32'h08100217;
10'h18f: data = 32'h00000000;
10'h190: data = 32'h8fc20008;
10'h191: data = 32'h00000000;
10'h192: data = 32'h8c420000;
10'h193: data = 32'h00000000;
10'h194: data = 32'h2c420030;
10'h195: data = 32'h14400010;
10'h196: data = 32'h00000000;
10'h197: data = 32'h8fc20008;
10'h198: data = 32'h00000000;
10'h199: data = 32'h8c420000;
10'h19a: data = 32'h00000000;
10'h19b: data = 32'h2c42003a;
10'h19c: data = 32'h10400009;
10'h19d: data = 32'h00000000;
10'h19e: data = 32'h8fc20008;
10'h19f: data = 32'h00000000;
10'h1a0: data = 32'h8c430000;
10'h1a1: data = 32'h8fc20008;
10'h1a2: data = 32'h00000000;
10'h1a3: data = 32'hac430000;
10'h1a4: data = 32'h08100217;
10'h1a5: data = 32'h00000000;
10'h1a6: data = 32'h8fc20008;
10'h1a7: data = 32'h00000000;
10'h1a8: data = 32'h8c420000;
10'h1a9: data = 32'h00000000;
10'h1aa: data = 32'h14400006;
10'h1ab: data = 32'h00000000;
10'h1ac: data = 32'h8fc30008;
10'h1ad: data = 32'h24020040;
10'h1ae: data = 32'hac620000;
10'h1af: data = 32'h08100217;
10'h1b0: data = 32'h00000000;
10'h1b1: data = 32'h8fc20008;
10'h1b2: data = 32'h00000000;
10'h1b3: data = 32'h8c430000;
10'h1b4: data = 32'h2402001b;
10'h1b5: data = 32'h14620006;
10'h1b6: data = 32'h00000000;
10'h1b7: data = 32'h8fc30008;
10'h1b8: data = 32'h2402005b;
10'h1b9: data = 32'hac620000;
10'h1ba: data = 32'h08100217;
10'h1bb: data = 32'h00000000;
10'h1bc: data = 32'h8fc20008;
10'h1bd: data = 32'h00000000;
10'h1be: data = 32'h8c430000;
10'h1bf: data = 32'h2402001d;
10'h1c0: data = 32'h14620006;
10'h1c1: data = 32'h00000000;
10'h1c2: data = 32'h8fc30008;
10'h1c3: data = 32'h2402005d;
10'h1c4: data = 32'hac620000;
10'h1c5: data = 32'h08100217;
10'h1c6: data = 32'h00000000;
10'h1c7: data = 32'h8fc20008;
10'h1c8: data = 32'h00000000;
10'h1c9: data = 32'h8c420000;
10'h1ca: data = 32'h00000000;
10'h1cb: data = 32'h2c420020;
10'h1cc: data = 32'h14400010;
10'h1cd: data = 32'h00000000;
10'h1ce: data = 32'h8fc20008;
10'h1cf: data = 32'h00000000;
10'h1d0: data = 32'h8c420000;
10'h1d1: data = 32'h00000000;
10'h1d2: data = 32'h2c420030;
10'h1d3: data = 32'h10400009;
10'h1d4: data = 32'h00000000;
10'h1d5: data = 32'h8fc20008;
10'h1d6: data = 32'h00000000;
10'h1d7: data = 32'h8c430000;
10'h1d8: data = 32'h8fc20008;
10'h1d9: data = 32'h00000000;
10'h1da: data = 32'hac430000;
10'h1db: data = 32'h08100217;
10'h1dc: data = 32'h00000000;
10'h1dd: data = 32'h8fc20008;
10'h1de: data = 32'h00000000;
10'h1df: data = 32'h8c430000;
10'h1e0: data = 32'h2402003a;
10'h1e1: data = 32'h14620006;
10'h1e2: data = 32'h00000000;
10'h1e3: data = 32'h8fc30008;
10'h1e4: data = 32'h2402003f;
10'h1e5: data = 32'hac620000;
10'h1e6: data = 32'h08100217;
10'h1e7: data = 32'h00000000;
10'h1e8: data = 32'h8fc20008;
10'h1e9: data = 32'h00000000;
10'h1ea: data = 32'h8c430000;
10'h1eb: data = 32'h2402003b;
10'h1ec: data = 32'h14620006;
10'h1ed: data = 32'h00000000;
10'h1ee: data = 32'h8fc30008;
10'h1ef: data = 32'h2402003d;
10'h1f0: data = 32'hac620000;
10'h1f1: data = 32'h08100217;
10'h1f2: data = 32'h00000000;
10'h1f3: data = 32'h8fc20008;
10'h1f4: data = 32'h00000000;
10'h1f5: data = 32'h8c430000;
10'h1f6: data = 32'h2402003c;
10'h1f7: data = 32'h14620006;
10'h1f8: data = 32'h00000000;
10'h1f9: data = 32'h8fc30008;
10'h1fa: data = 32'h2402003b;
10'h1fb: data = 32'hac620000;
10'h1fc: data = 32'h08100217;
10'h1fd: data = 32'h00000000;
10'h1fe: data = 32'h8fc20008;
10'h1ff: data = 32'h00000000;
10'h200: data = 32'h8c430000;
10'h201: data = 32'h2402003d;
10'h202: data = 32'h14620006;
10'h203: data = 32'h00000000;
10'h204: data = 32'h8fc30008;
10'h205: data = 32'h2402003a;
10'h206: data = 32'hac620000;
10'h207: data = 32'h08100217;
10'h208: data = 32'h00000000;
10'h209: data = 32'h8fc20008;
10'h20a: data = 32'h00000000;
10'h20b: data = 32'h8c430000;
10'h20c: data = 32'h2402003e;
10'h20d: data = 32'h14620006;
10'h20e: data = 32'h00000000;
10'h20f: data = 32'h8fc30008;
10'h210: data = 32'h2402000a;
10'h211: data = 32'hac620000;
10'h212: data = 32'h08100217;
10'h213: data = 32'h00000000;
10'h214: data = 32'h8fc30008;
10'h215: data = 32'h24020040;
10'h216: data = 32'hac620000;
10'h217: data = 32'h24020308;
10'h218: data = 32'hac400000;
10'h219: data = 32'h24030308;
10'h21a: data = 32'h24020001;
10'h21b: data = 32'hac620000;
10'h21c: data = 32'h8fc20008;
10'h21d: data = 32'h00000000;
10'h21e: data = 32'h24420004;
10'h21f: data = 32'hafc20008;
10'h220: data = 32'h24020310;
10'h221: data = 32'h8c430000;
10'h222: data = 32'h8fc20008;
10'h223: data = 32'h00000000;
10'h224: data = 32'hac430000;
10'h225: data = 32'h8fc20008;
10'h226: data = 32'h00000000;
10'h227: data = 32'h8c430000;
10'h228: data = 32'h2402003e;
10'h229: data = 32'h1462ff4f;
10'h22a: data = 32'h00000000;
10'h22b: data = 32'h8fc20008;
10'h22c: data = 32'h00000000;
10'h22d: data = 32'hac400000;
10'h22e: data = 32'h24020308;
10'h22f: data = 32'hac400000;
10'h230: data = 32'h2402030c;
10'h231: data = 32'hac400000;
10'h232: data = 32'h24030308;
10'h233: data = 32'h24020001;
10'h234: data = 32'hac620000;
10'h235: data = 32'h24020308;
10'h236: data = 32'hac400000;
10'h237: data = 32'h03c0e821;
10'h238: data = 32'h8fbe0000;
10'h239: data = 32'h27bd0008;
10'h23a: data = 32'h03e00008;
10'h23b: data = 32'h00000000;
10'h23c: data = 32'h27bdfff8;
10'h23d: data = 32'hafbe0000;
10'h23e: data = 32'h03a0f021;
10'h23f: data = 32'hafc40008;
10'h240: data = 32'h081002fe;
10'h241: data = 32'h00000000;
10'h242: data = 32'h24020300;
10'h243: data = 32'hac400000;
10'h244: data = 32'h8fc20008;
10'h245: data = 32'h00000000;
10'h246: data = 32'h8c420000;
10'h247: data = 32'h00000000;
10'h248: data = 32'h2c420041;
10'h249: data = 32'h14400011;
10'h24a: data = 32'h00000000;
10'h24b: data = 32'h8fc20008;
10'h24c: data = 32'h00000000;
10'h24d: data = 32'h8c420000;
10'h24e: data = 32'h00000000;
10'h24f: data = 32'h2c42005b;
10'h250: data = 32'h1040000a;
10'h251: data = 32'h00000000;
10'h252: data = 32'h24030304;
10'h253: data = 32'h8fc20008;
10'h254: data = 32'h00000000;
10'h255: data = 32'h8c420000;
10'h256: data = 32'h00000000;
10'h257: data = 32'h2442ffc0;
10'h258: data = 32'hac620000;
10'h259: data = 32'h081002f7;
10'h25a: data = 32'h00000000;
10'h25b: data = 32'h8fc20008;
10'h25c: data = 32'h00000000;
10'h25d: data = 32'h8c420000;
10'h25e: data = 32'h00000000;
10'h25f: data = 32'h2c420061;
10'h260: data = 32'h14400011;
10'h261: data = 32'h00000000;
10'h262: data = 32'h8fc20008;
10'h263: data = 32'h00000000;
10'h264: data = 32'h8c420000;
10'h265: data = 32'h00000000;
10'h266: data = 32'h2c42007b;
10'h267: data = 32'h1040000a;
10'h268: data = 32'h00000000;
10'h269: data = 32'h24030304;
10'h26a: data = 32'h8fc20008;
10'h26b: data = 32'h00000000;
10'h26c: data = 32'h8c420000;
10'h26d: data = 32'h00000000;
10'h26e: data = 32'h2442ffa0;
10'h26f: data = 32'hac620000;
10'h270: data = 32'h081002f7;
10'h271: data = 32'h00000000;
10'h272: data = 32'h8fc20008;
10'h273: data = 32'h00000000;
10'h274: data = 32'h8c420000;
10'h275: data = 32'h00000000;
10'h276: data = 32'h2c420030;
10'h277: data = 32'h14400010;
10'h278: data = 32'h00000000;
10'h279: data = 32'h8fc20008;
10'h27a: data = 32'h00000000;
10'h27b: data = 32'h8c420000;
10'h27c: data = 32'h00000000;
10'h27d: data = 32'h2c42003a;
10'h27e: data = 32'h10400009;
10'h27f: data = 32'h00000000;
10'h280: data = 32'h24020304;
10'h281: data = 32'h8fc30008;
10'h282: data = 32'h00000000;
10'h283: data = 32'h8c630000;
10'h284: data = 32'h00000000;
10'h285: data = 32'hac430000;
10'h286: data = 32'h081002f7;
10'h287: data = 32'h00000000;
10'h288: data = 32'h8fc20008;
10'h289: data = 32'h00000000;
10'h28a: data = 32'h8c430000;
10'h28b: data = 32'h24020040;
10'h28c: data = 32'h14620005;
10'h28d: data = 32'h00000000;
10'h28e: data = 32'h24020304;
10'h28f: data = 32'hac400000;
10'h290: data = 32'h081002f7;
10'h291: data = 32'h00000000;
10'h292: data = 32'h8fc20008;
10'h293: data = 32'h00000000;
10'h294: data = 32'h8c430000;
10'h295: data = 32'h2402005b;
10'h296: data = 32'h14620006;
10'h297: data = 32'h00000000;
10'h298: data = 32'h24030304;
10'h299: data = 32'h2402001b;
10'h29a: data = 32'hac620000;
10'h29b: data = 32'h081002f7;
10'h29c: data = 32'h00000000;
10'h29d: data = 32'h8fc20008;
10'h29e: data = 32'h00000000;
10'h29f: data = 32'h8c430000;
10'h2a0: data = 32'h2402005d;
10'h2a1: data = 32'h14620006;
10'h2a2: data = 32'h00000000;
10'h2a3: data = 32'h24030304;
10'h2a4: data = 32'h2402001d;
10'h2a5: data = 32'hac620000;
10'h2a6: data = 32'h081002f7;
10'h2a7: data = 32'h00000000;
10'h2a8: data = 32'h8fc20008;
10'h2a9: data = 32'h00000000;
10'h2aa: data = 32'h8c420000;
10'h2ab: data = 32'h00000000;
10'h2ac: data = 32'h2c420020;
10'h2ad: data = 32'h14400010;
10'h2ae: data = 32'h00000000;
10'h2af: data = 32'h8fc20008;
10'h2b0: data = 32'h00000000;
10'h2b1: data = 32'h8c420000;
10'h2b2: data = 32'h00000000;
10'h2b3: data = 32'h2c420030;
10'h2b4: data = 32'h10400009;
10'h2b5: data = 32'h00000000;
10'h2b6: data = 32'h24020304;
10'h2b7: data = 32'h8fc30008;
10'h2b8: data = 32'h00000000;
10'h2b9: data = 32'h8c630000;
10'h2ba: data = 32'h00000000;
10'h2bb: data = 32'hac430000;
10'h2bc: data = 32'h081002f7;
10'h2bd: data = 32'h00000000;
10'h2be: data = 32'h8fc20008;
10'h2bf: data = 32'h00000000;
10'h2c0: data = 32'h8c430000;
10'h2c1: data = 32'h2402003f;
10'h2c2: data = 32'h14620006;
10'h2c3: data = 32'h00000000;
10'h2c4: data = 32'h24030304;
10'h2c5: data = 32'h2402003a;
10'h2c6: data = 32'hac620000;
10'h2c7: data = 32'h081002f7;
10'h2c8: data = 32'h00000000;
10'h2c9: data = 32'h8fc20008;
10'h2ca: data = 32'h00000000;
10'h2cb: data = 32'h8c430000;
10'h2cc: data = 32'h2402003d;
10'h2cd: data = 32'h14620006;
10'h2ce: data = 32'h00000000;
10'h2cf: data = 32'h24030304;
10'h2d0: data = 32'h2402003b;
10'h2d1: data = 32'hac620000;
10'h2d2: data = 32'h081002f7;
10'h2d3: data = 32'h00000000;
10'h2d4: data = 32'h8fc20008;
10'h2d5: data = 32'h00000000;
10'h2d6: data = 32'h8c430000;
10'h2d7: data = 32'h2402003b;
10'h2d8: data = 32'h14620006;
10'h2d9: data = 32'h00000000;
10'h2da: data = 32'h24030304;
10'h2db: data = 32'h2402003c;
10'h2dc: data = 32'hac620000;
10'h2dd: data = 32'h081002f7;
10'h2de: data = 32'h00000000;
10'h2df: data = 32'h8fc20008;
10'h2e0: data = 32'h00000000;
10'h2e1: data = 32'h8c430000;
10'h2e2: data = 32'h2402003a;
10'h2e3: data = 32'h14620006;
10'h2e4: data = 32'h00000000;
10'h2e5: data = 32'h24030304;
10'h2e6: data = 32'h2402003d;
10'h2e7: data = 32'hac620000;
10'h2e8: data = 32'h081002f7;
10'h2e9: data = 32'h00000000;
10'h2ea: data = 32'h8fc20008;
10'h2eb: data = 32'h00000000;
10'h2ec: data = 32'h8c430000;
10'h2ed: data = 32'h2402000a;
10'h2ee: data = 32'h14620006;
10'h2ef: data = 32'h00000000;
10'h2f0: data = 32'h24030304;
10'h2f1: data = 32'h2402003e;
10'h2f2: data = 32'hac620000;
10'h2f3: data = 32'h081002f7;
10'h2f4: data = 32'h00000000;
10'h2f5: data = 32'h24020304;
10'h2f6: data = 32'hac400000;
10'h2f7: data = 32'h24030300;
10'h2f8: data = 32'h24020001;
10'h2f9: data = 32'hac620000;
10'h2fa: data = 32'h8fc20008;
10'h2fb: data = 32'h00000000;
10'h2fc: data = 32'h24420004;
10'h2fd: data = 32'hafc20008;
10'h2fe: data = 32'h8fc20008;
10'h2ff: data = 32'h00000000;
10'h300: data = 32'h8c420000;
10'h301: data = 32'h00000000;
10'h302: data = 32'h1440ff3f;
10'h303: data = 32'h00000000;
10'h304: data = 32'h03c0e821;
10'h305: data = 32'h8fbe0000;
10'h306: data = 32'h27bd0008;
10'h307: data = 32'h03e00008;
10'h308: data = 32'h00000000;
10'h309: data = 32'h00000000;
10'h30a: data = 32'h00000000;
10'h30b: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,886 | data/full_repos/permissive/107499099/ex4/stepping/rom8x1024_sim.v | 107,499,099 | rom8x1024_sim.v | v | 372 | 99 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex4/stepping/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance rom8x1024_sim\n assign word_addr = rom_addr[9:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,669 | module | module rom8x1024_sim (rom_addr, rom_data);
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408540;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdffb8;
10'h009: data = 32'hafbf0044;
10'h00a: data = 32'hafbe0040;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h27c20014;
10'h00d: data = 32'h00402021;
10'h00e: data = 32'h0c100071;
10'h00f: data = 32'h00000000;
10'h010: data = 32'h8fc30014;
10'h011: data = 32'h24020052;
10'h012: data = 32'h14620011;
10'h013: data = 32'h00000000;
10'h014: data = 32'hafc00010;
10'h015: data = 32'h0810001d;
10'h016: data = 32'h00000000;
10'h017: data = 32'h0c10004e;
10'h018: data = 32'h00000000;
10'h019: data = 32'h8fc20010;
10'h01a: data = 32'h00000000;
10'h01b: data = 32'h24420001;
10'h01c: data = 32'hafc20010;
10'h01d: data = 32'h8fc20010;
10'h01e: data = 32'h00000000;
10'h01f: data = 32'h2c42000a;
10'h020: data = 32'h1440fff6;
10'h021: data = 32'h00000000;
10'h022: data = 32'h0810000c;
10'h023: data = 32'h00000000;
10'h024: data = 32'h8fc30014;
10'h025: data = 32'h2402004c;
10'h026: data = 32'h1462ffe5;
10'h027: data = 32'h00000000;
10'h028: data = 32'hafc00010;
10'h029: data = 32'h08100031;
10'h02a: data = 32'h00000000;
10'h02b: data = 32'h0c100038;
10'h02c: data = 32'h00000000;
10'h02d: data = 32'h8fc20010;
10'h02e: data = 32'h00000000;
10'h02f: data = 32'h24420001;
10'h030: data = 32'hafc20010;
10'h031: data = 32'h8fc20010;
10'h032: data = 32'h00000000;
10'h033: data = 32'h2c42000a;
10'h034: data = 32'h1440fff6;
10'h035: data = 32'h00000000;
10'h036: data = 32'h0810000c;
10'h037: data = 32'h00000000;
10'h038: data = 32'h27bdffe8;
10'h039: data = 32'hafbf0014;
10'h03a: data = 32'hafbe0010;
10'h03b: data = 32'h03a0f021;
10'h03c: data = 32'h24040001;
10'h03d: data = 32'h0c100064;
10'h03e: data = 32'h00000000;
10'h03f: data = 32'h24040002;
10'h040: data = 32'h0c100064;
10'h041: data = 32'h00000000;
10'h042: data = 32'h24040004;
10'h043: data = 32'h0c100064;
10'h044: data = 32'h00000000;
10'h045: data = 32'h24040008;
10'h046: data = 32'h0c100064;
10'h047: data = 32'h00000000;
10'h048: data = 32'h03c0e821;
10'h049: data = 32'h8fbf0014;
10'h04a: data = 32'h8fbe0010;
10'h04b: data = 32'h27bd0018;
10'h04c: data = 32'h03e00008;
10'h04d: data = 32'h00000000;
10'h04e: data = 32'h27bdffe8;
10'h04f: data = 32'hafbf0014;
10'h050: data = 32'hafbe0010;
10'h051: data = 32'h03a0f021;
10'h052: data = 32'h24040008;
10'h053: data = 32'h0c100064;
10'h054: data = 32'h00000000;
10'h055: data = 32'h24040004;
10'h056: data = 32'h0c100064;
10'h057: data = 32'h00000000;
10'h058: data = 32'h24040002;
10'h059: data = 32'h0c100064;
10'h05a: data = 32'h00000000;
10'h05b: data = 32'h24040001;
10'h05c: data = 32'h0c100064;
10'h05d: data = 32'h00000000;
10'h05e: data = 32'h03c0e821;
10'h05f: data = 32'h8fbf0014;
10'h060: data = 32'h8fbe0010;
10'h061: data = 32'h27bd0018;
10'h062: data = 32'h03e00008;
10'h063: data = 32'h00000000;
10'h064: data = 32'h27bdfff0;
10'h065: data = 32'hafbe0008;
10'h066: data = 32'h03a0f021;
10'h067: data = 32'hafc40010;
10'h068: data = 32'h24030320;
10'h069: data = 32'h8fc20010;
10'h06a: data = 32'h00000000;
10'h06b: data = 32'hac620000;
10'h06c: data = 32'h03c0e821;
10'h06d: data = 32'h8fbe0008;
10'h06e: data = 32'h27bd0010;
10'h06f: data = 32'h03e00008;
10'h070: data = 32'h00000000;
10'h071: data = 32'h27bdfff8;
10'h072: data = 32'hafbe0000;
10'h073: data = 32'h03a0f021;
10'h074: data = 32'hafc40008;
10'h075: data = 32'h24020308;
10'h076: data = 32'hac400000;
10'h077: data = 32'h2403030c;
10'h078: data = 32'h24020001;
10'h079: data = 32'hac620000;
10'h07a: data = 32'h24030308;
10'h07b: data = 32'h24020001;
10'h07c: data = 32'hac620000;
10'h07d: data = 32'h24020308;
10'h07e: data = 32'hac400000;
10'h07f: data = 32'h24030308;
10'h080: data = 32'h24020001;
10'h081: data = 32'hac620000;
10'h082: data = 32'h08100089;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24020308;
10'h085: data = 32'hac400000;
10'h086: data = 32'h24030308;
10'h087: data = 32'h24020001;
10'h088: data = 32'hac620000;
10'h089: data = 32'h24020310;
10'h08a: data = 32'h8c430000;
10'h08b: data = 32'h2402ffff;
10'h08c: data = 32'h1062fff7;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h08100137;
10'h08f: data = 32'h00000000;
10'h090: data = 32'h8fc20008;
10'h091: data = 32'h00000000;
10'h092: data = 32'h8c420000;
10'h093: data = 32'h00000000;
10'h094: data = 32'h10400012;
10'h095: data = 32'h00000000;
10'h096: data = 32'h8fc20008;
10'h097: data = 32'h00000000;
10'h098: data = 32'h8c420000;
10'h099: data = 32'h00000000;
10'h09a: data = 32'h2c42001b;
10'h09b: data = 32'h1040000b;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h8fc20008;
10'h09e: data = 32'h00000000;
10'h09f: data = 32'h8c420000;
10'h0a0: data = 32'h00000000;
10'h0a1: data = 32'h24430040;
10'h0a2: data = 32'h8fc20008;
10'h0a3: data = 32'h00000000;
10'h0a4: data = 32'hac430000;
10'h0a5: data = 32'h0810012e;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'h8fc20008;
10'h0a8: data = 32'h00000000;
10'h0a9: data = 32'h8c420000;
10'h0aa: data = 32'h00000000;
10'h0ab: data = 32'h2c420030;
10'h0ac: data = 32'h14400010;
10'h0ad: data = 32'h00000000;
10'h0ae: data = 32'h8fc20008;
10'h0af: data = 32'h00000000;
10'h0b0: data = 32'h8c420000;
10'h0b1: data = 32'h00000000;
10'h0b2: data = 32'h2c42003a;
10'h0b3: data = 32'h10400009;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'h8fc20008;
10'h0b6: data = 32'h00000000;
10'h0b7: data = 32'h8c430000;
10'h0b8: data = 32'h8fc20008;
10'h0b9: data = 32'h00000000;
10'h0ba: data = 32'hac430000;
10'h0bb: data = 32'h0810012e;
10'h0bc: data = 32'h00000000;
10'h0bd: data = 32'h8fc20008;
10'h0be: data = 32'h00000000;
10'h0bf: data = 32'h8c420000;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h14400006;
10'h0c2: data = 32'h00000000;
10'h0c3: data = 32'h8fc30008;
10'h0c4: data = 32'h24020040;
10'h0c5: data = 32'hac620000;
10'h0c6: data = 32'h0810012e;
10'h0c7: data = 32'h00000000;
10'h0c8: data = 32'h8fc20008;
10'h0c9: data = 32'h00000000;
10'h0ca: data = 32'h8c430000;
10'h0cb: data = 32'h2402001b;
10'h0cc: data = 32'h14620006;
10'h0cd: data = 32'h00000000;
10'h0ce: data = 32'h8fc30008;
10'h0cf: data = 32'h2402005b;
10'h0d0: data = 32'hac620000;
10'h0d1: data = 32'h0810012e;
10'h0d2: data = 32'h00000000;
10'h0d3: data = 32'h8fc20008;
10'h0d4: data = 32'h00000000;
10'h0d5: data = 32'h8c430000;
10'h0d6: data = 32'h2402001d;
10'h0d7: data = 32'h14620006;
10'h0d8: data = 32'h00000000;
10'h0d9: data = 32'h8fc30008;
10'h0da: data = 32'h2402005d;
10'h0db: data = 32'hac620000;
10'h0dc: data = 32'h0810012e;
10'h0dd: data = 32'h00000000;
10'h0de: data = 32'h8fc20008;
10'h0df: data = 32'h00000000;
10'h0e0: data = 32'h8c420000;
10'h0e1: data = 32'h00000000;
10'h0e2: data = 32'h2c420020;
10'h0e3: data = 32'h14400010;
10'h0e4: data = 32'h00000000;
10'h0e5: data = 32'h8fc20008;
10'h0e6: data = 32'h00000000;
10'h0e7: data = 32'h8c420000;
10'h0e8: data = 32'h00000000;
10'h0e9: data = 32'h2c420030;
10'h0ea: data = 32'h10400009;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8fc20008;
10'h0ed: data = 32'h00000000;
10'h0ee: data = 32'h8c430000;
10'h0ef: data = 32'h8fc20008;
10'h0f0: data = 32'h00000000;
10'h0f1: data = 32'hac430000;
10'h0f2: data = 32'h0810012e;
10'h0f3: data = 32'h00000000;
10'h0f4: data = 32'h8fc20008;
10'h0f5: data = 32'h00000000;
10'h0f6: data = 32'h8c430000;
10'h0f7: data = 32'h2402003a;
10'h0f8: data = 32'h14620006;
10'h0f9: data = 32'h00000000;
10'h0fa: data = 32'h8fc30008;
10'h0fb: data = 32'h2402003f;
10'h0fc: data = 32'hac620000;
10'h0fd: data = 32'h0810012e;
10'h0fe: data = 32'h00000000;
10'h0ff: data = 32'h8fc20008;
10'h100: data = 32'h00000000;
10'h101: data = 32'h8c430000;
10'h102: data = 32'h2402003b;
10'h103: data = 32'h14620006;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8fc30008;
10'h106: data = 32'h2402003d;
10'h107: data = 32'hac620000;
10'h108: data = 32'h0810012e;
10'h109: data = 32'h00000000;
10'h10a: data = 32'h8fc20008;
10'h10b: data = 32'h00000000;
10'h10c: data = 32'h8c430000;
10'h10d: data = 32'h2402003c;
10'h10e: data = 32'h14620006;
10'h10f: data = 32'h00000000;
10'h110: data = 32'h8fc30008;
10'h111: data = 32'h2402003b;
10'h112: data = 32'hac620000;
10'h113: data = 32'h0810012e;
10'h114: data = 32'h00000000;
10'h115: data = 32'h8fc20008;
10'h116: data = 32'h00000000;
10'h117: data = 32'h8c430000;
10'h118: data = 32'h2402003d;
10'h119: data = 32'h14620006;
10'h11a: data = 32'h00000000;
10'h11b: data = 32'h8fc30008;
10'h11c: data = 32'h2402003a;
10'h11d: data = 32'hac620000;
10'h11e: data = 32'h0810012e;
10'h11f: data = 32'h00000000;
10'h120: data = 32'h8fc20008;
10'h121: data = 32'h00000000;
10'h122: data = 32'h8c430000;
10'h123: data = 32'h2402003e;
10'h124: data = 32'h14620006;
10'h125: data = 32'h00000000;
10'h126: data = 32'h8fc30008;
10'h127: data = 32'h2402000a;
10'h128: data = 32'hac620000;
10'h129: data = 32'h0810012e;
10'h12a: data = 32'h00000000;
10'h12b: data = 32'h8fc30008;
10'h12c: data = 32'h24020040;
10'h12d: data = 32'hac620000;
10'h12e: data = 32'h24020308;
10'h12f: data = 32'hac400000;
10'h130: data = 32'h24030308;
10'h131: data = 32'h24020001;
10'h132: data = 32'hac620000;
10'h133: data = 32'h8fc20008;
10'h134: data = 32'h00000000;
10'h135: data = 32'h24420004;
10'h136: data = 32'hafc20008;
10'h137: data = 32'h24020310;
10'h138: data = 32'h8c430000;
10'h139: data = 32'h8fc20008;
10'h13a: data = 32'h00000000;
10'h13b: data = 32'hac430000;
10'h13c: data = 32'h8fc20008;
10'h13d: data = 32'h00000000;
10'h13e: data = 32'h8c430000;
10'h13f: data = 32'h2402003e;
10'h140: data = 32'h1462ff4f;
10'h141: data = 32'h00000000;
10'h142: data = 32'h8fc20008;
10'h143: data = 32'h00000000;
10'h144: data = 32'hac400000;
10'h145: data = 32'h24020308;
10'h146: data = 32'hac400000;
10'h147: data = 32'h2402030c;
10'h148: data = 32'hac400000;
10'h149: data = 32'h24030308;
10'h14a: data = 32'h24020001;
10'h14b: data = 32'hac620000;
10'h14c: data = 32'h24020308;
10'h14d: data = 32'hac400000;
10'h14e: data = 32'h03c0e821;
10'h14f: data = 32'h8fbe0000;
10'h150: data = 32'h27bd0008;
10'h151: data = 32'h03e00008;
10'h152: data = 32'h00000000;
10'h153: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | module rom8x1024_sim (rom_addr, rom_data); |
input [11:0] rom_addr;
output [31:0] rom_data;
reg [31:0] data;
wire [9:0] word_addr;
assign word_addr = rom_addr[9:2];
always @(word_addr) begin
case (word_addr)
10'h000: data = 32'he000001c;
10'h001: data = 32'h00000000;
10'h002: data = 32'h00000000;
10'h003: data = 32'h00000000;
10'h004: data = 32'h00000000;
10'h005: data = 32'h00408540;
10'h006: data = 32'h00000000;
10'h007: data = 32'h00000000;
10'h008: data = 32'h27bdffb8;
10'h009: data = 32'hafbf0044;
10'h00a: data = 32'hafbe0040;
10'h00b: data = 32'h03a0f021;
10'h00c: data = 32'h27c20014;
10'h00d: data = 32'h00402021;
10'h00e: data = 32'h0c100071;
10'h00f: data = 32'h00000000;
10'h010: data = 32'h8fc30014;
10'h011: data = 32'h24020052;
10'h012: data = 32'h14620011;
10'h013: data = 32'h00000000;
10'h014: data = 32'hafc00010;
10'h015: data = 32'h0810001d;
10'h016: data = 32'h00000000;
10'h017: data = 32'h0c10004e;
10'h018: data = 32'h00000000;
10'h019: data = 32'h8fc20010;
10'h01a: data = 32'h00000000;
10'h01b: data = 32'h24420001;
10'h01c: data = 32'hafc20010;
10'h01d: data = 32'h8fc20010;
10'h01e: data = 32'h00000000;
10'h01f: data = 32'h2c42000a;
10'h020: data = 32'h1440fff6;
10'h021: data = 32'h00000000;
10'h022: data = 32'h0810000c;
10'h023: data = 32'h00000000;
10'h024: data = 32'h8fc30014;
10'h025: data = 32'h2402004c;
10'h026: data = 32'h1462ffe5;
10'h027: data = 32'h00000000;
10'h028: data = 32'hafc00010;
10'h029: data = 32'h08100031;
10'h02a: data = 32'h00000000;
10'h02b: data = 32'h0c100038;
10'h02c: data = 32'h00000000;
10'h02d: data = 32'h8fc20010;
10'h02e: data = 32'h00000000;
10'h02f: data = 32'h24420001;
10'h030: data = 32'hafc20010;
10'h031: data = 32'h8fc20010;
10'h032: data = 32'h00000000;
10'h033: data = 32'h2c42000a;
10'h034: data = 32'h1440fff6;
10'h035: data = 32'h00000000;
10'h036: data = 32'h0810000c;
10'h037: data = 32'h00000000;
10'h038: data = 32'h27bdffe8;
10'h039: data = 32'hafbf0014;
10'h03a: data = 32'hafbe0010;
10'h03b: data = 32'h03a0f021;
10'h03c: data = 32'h24040001;
10'h03d: data = 32'h0c100064;
10'h03e: data = 32'h00000000;
10'h03f: data = 32'h24040002;
10'h040: data = 32'h0c100064;
10'h041: data = 32'h00000000;
10'h042: data = 32'h24040004;
10'h043: data = 32'h0c100064;
10'h044: data = 32'h00000000;
10'h045: data = 32'h24040008;
10'h046: data = 32'h0c100064;
10'h047: data = 32'h00000000;
10'h048: data = 32'h03c0e821;
10'h049: data = 32'h8fbf0014;
10'h04a: data = 32'h8fbe0010;
10'h04b: data = 32'h27bd0018;
10'h04c: data = 32'h03e00008;
10'h04d: data = 32'h00000000;
10'h04e: data = 32'h27bdffe8;
10'h04f: data = 32'hafbf0014;
10'h050: data = 32'hafbe0010;
10'h051: data = 32'h03a0f021;
10'h052: data = 32'h24040008;
10'h053: data = 32'h0c100064;
10'h054: data = 32'h00000000;
10'h055: data = 32'h24040004;
10'h056: data = 32'h0c100064;
10'h057: data = 32'h00000000;
10'h058: data = 32'h24040002;
10'h059: data = 32'h0c100064;
10'h05a: data = 32'h00000000;
10'h05b: data = 32'h24040001;
10'h05c: data = 32'h0c100064;
10'h05d: data = 32'h00000000;
10'h05e: data = 32'h03c0e821;
10'h05f: data = 32'h8fbf0014;
10'h060: data = 32'h8fbe0010;
10'h061: data = 32'h27bd0018;
10'h062: data = 32'h03e00008;
10'h063: data = 32'h00000000;
10'h064: data = 32'h27bdfff0;
10'h065: data = 32'hafbe0008;
10'h066: data = 32'h03a0f021;
10'h067: data = 32'hafc40010;
10'h068: data = 32'h24030320;
10'h069: data = 32'h8fc20010;
10'h06a: data = 32'h00000000;
10'h06b: data = 32'hac620000;
10'h06c: data = 32'h03c0e821;
10'h06d: data = 32'h8fbe0008;
10'h06e: data = 32'h27bd0010;
10'h06f: data = 32'h03e00008;
10'h070: data = 32'h00000000;
10'h071: data = 32'h27bdfff8;
10'h072: data = 32'hafbe0000;
10'h073: data = 32'h03a0f021;
10'h074: data = 32'hafc40008;
10'h075: data = 32'h24020308;
10'h076: data = 32'hac400000;
10'h077: data = 32'h2403030c;
10'h078: data = 32'h24020001;
10'h079: data = 32'hac620000;
10'h07a: data = 32'h24030308;
10'h07b: data = 32'h24020001;
10'h07c: data = 32'hac620000;
10'h07d: data = 32'h24020308;
10'h07e: data = 32'hac400000;
10'h07f: data = 32'h24030308;
10'h080: data = 32'h24020001;
10'h081: data = 32'hac620000;
10'h082: data = 32'h08100089;
10'h083: data = 32'h00000000;
10'h084: data = 32'h24020308;
10'h085: data = 32'hac400000;
10'h086: data = 32'h24030308;
10'h087: data = 32'h24020001;
10'h088: data = 32'hac620000;
10'h089: data = 32'h24020310;
10'h08a: data = 32'h8c430000;
10'h08b: data = 32'h2402ffff;
10'h08c: data = 32'h1062fff7;
10'h08d: data = 32'h00000000;
10'h08e: data = 32'h08100137;
10'h08f: data = 32'h00000000;
10'h090: data = 32'h8fc20008;
10'h091: data = 32'h00000000;
10'h092: data = 32'h8c420000;
10'h093: data = 32'h00000000;
10'h094: data = 32'h10400012;
10'h095: data = 32'h00000000;
10'h096: data = 32'h8fc20008;
10'h097: data = 32'h00000000;
10'h098: data = 32'h8c420000;
10'h099: data = 32'h00000000;
10'h09a: data = 32'h2c42001b;
10'h09b: data = 32'h1040000b;
10'h09c: data = 32'h00000000;
10'h09d: data = 32'h8fc20008;
10'h09e: data = 32'h00000000;
10'h09f: data = 32'h8c420000;
10'h0a0: data = 32'h00000000;
10'h0a1: data = 32'h24430040;
10'h0a2: data = 32'h8fc20008;
10'h0a3: data = 32'h00000000;
10'h0a4: data = 32'hac430000;
10'h0a5: data = 32'h0810012e;
10'h0a6: data = 32'h00000000;
10'h0a7: data = 32'h8fc20008;
10'h0a8: data = 32'h00000000;
10'h0a9: data = 32'h8c420000;
10'h0aa: data = 32'h00000000;
10'h0ab: data = 32'h2c420030;
10'h0ac: data = 32'h14400010;
10'h0ad: data = 32'h00000000;
10'h0ae: data = 32'h8fc20008;
10'h0af: data = 32'h00000000;
10'h0b0: data = 32'h8c420000;
10'h0b1: data = 32'h00000000;
10'h0b2: data = 32'h2c42003a;
10'h0b3: data = 32'h10400009;
10'h0b4: data = 32'h00000000;
10'h0b5: data = 32'h8fc20008;
10'h0b6: data = 32'h00000000;
10'h0b7: data = 32'h8c430000;
10'h0b8: data = 32'h8fc20008;
10'h0b9: data = 32'h00000000;
10'h0ba: data = 32'hac430000;
10'h0bb: data = 32'h0810012e;
10'h0bc: data = 32'h00000000;
10'h0bd: data = 32'h8fc20008;
10'h0be: data = 32'h00000000;
10'h0bf: data = 32'h8c420000;
10'h0c0: data = 32'h00000000;
10'h0c1: data = 32'h14400006;
10'h0c2: data = 32'h00000000;
10'h0c3: data = 32'h8fc30008;
10'h0c4: data = 32'h24020040;
10'h0c5: data = 32'hac620000;
10'h0c6: data = 32'h0810012e;
10'h0c7: data = 32'h00000000;
10'h0c8: data = 32'h8fc20008;
10'h0c9: data = 32'h00000000;
10'h0ca: data = 32'h8c430000;
10'h0cb: data = 32'h2402001b;
10'h0cc: data = 32'h14620006;
10'h0cd: data = 32'h00000000;
10'h0ce: data = 32'h8fc30008;
10'h0cf: data = 32'h2402005b;
10'h0d0: data = 32'hac620000;
10'h0d1: data = 32'h0810012e;
10'h0d2: data = 32'h00000000;
10'h0d3: data = 32'h8fc20008;
10'h0d4: data = 32'h00000000;
10'h0d5: data = 32'h8c430000;
10'h0d6: data = 32'h2402001d;
10'h0d7: data = 32'h14620006;
10'h0d8: data = 32'h00000000;
10'h0d9: data = 32'h8fc30008;
10'h0da: data = 32'h2402005d;
10'h0db: data = 32'hac620000;
10'h0dc: data = 32'h0810012e;
10'h0dd: data = 32'h00000000;
10'h0de: data = 32'h8fc20008;
10'h0df: data = 32'h00000000;
10'h0e0: data = 32'h8c420000;
10'h0e1: data = 32'h00000000;
10'h0e2: data = 32'h2c420020;
10'h0e3: data = 32'h14400010;
10'h0e4: data = 32'h00000000;
10'h0e5: data = 32'h8fc20008;
10'h0e6: data = 32'h00000000;
10'h0e7: data = 32'h8c420000;
10'h0e8: data = 32'h00000000;
10'h0e9: data = 32'h2c420030;
10'h0ea: data = 32'h10400009;
10'h0eb: data = 32'h00000000;
10'h0ec: data = 32'h8fc20008;
10'h0ed: data = 32'h00000000;
10'h0ee: data = 32'h8c430000;
10'h0ef: data = 32'h8fc20008;
10'h0f0: data = 32'h00000000;
10'h0f1: data = 32'hac430000;
10'h0f2: data = 32'h0810012e;
10'h0f3: data = 32'h00000000;
10'h0f4: data = 32'h8fc20008;
10'h0f5: data = 32'h00000000;
10'h0f6: data = 32'h8c430000;
10'h0f7: data = 32'h2402003a;
10'h0f8: data = 32'h14620006;
10'h0f9: data = 32'h00000000;
10'h0fa: data = 32'h8fc30008;
10'h0fb: data = 32'h2402003f;
10'h0fc: data = 32'hac620000;
10'h0fd: data = 32'h0810012e;
10'h0fe: data = 32'h00000000;
10'h0ff: data = 32'h8fc20008;
10'h100: data = 32'h00000000;
10'h101: data = 32'h8c430000;
10'h102: data = 32'h2402003b;
10'h103: data = 32'h14620006;
10'h104: data = 32'h00000000;
10'h105: data = 32'h8fc30008;
10'h106: data = 32'h2402003d;
10'h107: data = 32'hac620000;
10'h108: data = 32'h0810012e;
10'h109: data = 32'h00000000;
10'h10a: data = 32'h8fc20008;
10'h10b: data = 32'h00000000;
10'h10c: data = 32'h8c430000;
10'h10d: data = 32'h2402003c;
10'h10e: data = 32'h14620006;
10'h10f: data = 32'h00000000;
10'h110: data = 32'h8fc30008;
10'h111: data = 32'h2402003b;
10'h112: data = 32'hac620000;
10'h113: data = 32'h0810012e;
10'h114: data = 32'h00000000;
10'h115: data = 32'h8fc20008;
10'h116: data = 32'h00000000;
10'h117: data = 32'h8c430000;
10'h118: data = 32'h2402003d;
10'h119: data = 32'h14620006;
10'h11a: data = 32'h00000000;
10'h11b: data = 32'h8fc30008;
10'h11c: data = 32'h2402003a;
10'h11d: data = 32'hac620000;
10'h11e: data = 32'h0810012e;
10'h11f: data = 32'h00000000;
10'h120: data = 32'h8fc20008;
10'h121: data = 32'h00000000;
10'h122: data = 32'h8c430000;
10'h123: data = 32'h2402003e;
10'h124: data = 32'h14620006;
10'h125: data = 32'h00000000;
10'h126: data = 32'h8fc30008;
10'h127: data = 32'h2402000a;
10'h128: data = 32'hac620000;
10'h129: data = 32'h0810012e;
10'h12a: data = 32'h00000000;
10'h12b: data = 32'h8fc30008;
10'h12c: data = 32'h24020040;
10'h12d: data = 32'hac620000;
10'h12e: data = 32'h24020308;
10'h12f: data = 32'hac400000;
10'h130: data = 32'h24030308;
10'h131: data = 32'h24020001;
10'h132: data = 32'hac620000;
10'h133: data = 32'h8fc20008;
10'h134: data = 32'h00000000;
10'h135: data = 32'h24420004;
10'h136: data = 32'hafc20008;
10'h137: data = 32'h24020310;
10'h138: data = 32'h8c430000;
10'h139: data = 32'h8fc20008;
10'h13a: data = 32'h00000000;
10'h13b: data = 32'hac430000;
10'h13c: data = 32'h8fc20008;
10'h13d: data = 32'h00000000;
10'h13e: data = 32'h8c430000;
10'h13f: data = 32'h2402003e;
10'h140: data = 32'h1462ff4f;
10'h141: data = 32'h00000000;
10'h142: data = 32'h8fc20008;
10'h143: data = 32'h00000000;
10'h144: data = 32'hac400000;
10'h145: data = 32'h24020308;
10'h146: data = 32'hac400000;
10'h147: data = 32'h2402030c;
10'h148: data = 32'hac400000;
10'h149: data = 32'h24030308;
10'h14a: data = 32'h24020001;
10'h14b: data = 32'hac620000;
10'h14c: data = 32'h24020308;
10'h14d: data = 32'hac400000;
10'h14e: data = 32'h03c0e821;
10'h14f: data = 32'h8fbe0000;
10'h150: data = 32'h27bd0008;
10'h151: data = 32'h03e00008;
10'h152: data = 32'h00000000;
10'h153: data = 32'h00000000;
endcase
end
assign rom_data = data;
endmodule | 0 |
3,887 | data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v | 107,499,099 | DE2_115_Default.v | v | 849 | 111 | [] | [] | [] | null | line:846: before: ")" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:581: Signal definition not found, creating implicitly: \'OTG_FSPEED\'\nassign OTG_FSPEED = 1\'bz;\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:582: Signal definition not found, creating implicitly: \'OTG_LSPEED\'\n : ... Suggested alternative: \'OTG_FSPEED\'\nassign OTG_LSPEED = 1\'bz;\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:601: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 bits.\n : ... In instance DE2_115_Default\nassign mSEG7_DIG = { key_ascii_D[7:4], key_ascii_D[3:0],\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:607: Operator ADD expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'PUT_ROW\' generates 5 bits.\n : ... In instance DE2_115_Default\nassign ROW_Cursor = (PUT_ROW+1)*16+1;\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:611: Cannot find file containing module: \'Reset_Delay\'\nReset_Delay r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay\n data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay.v\n data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay.sv\n Reset_Delay\n Reset_Delay.v\n Reset_Delay.sv\n obj_dir/Reset_Delay\n obj_dir/Reset_Delay.v\n obj_dir/Reset_Delay.sv\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:613: Cannot find file containing module: \'VGA_Audio_PLL\'\nVGA_Audio_PLL p1 ( .areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK) );\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:616: Cannot find file containing module: \'SEG7_LUT_8\'\nSEG7_LUT_8 u0 ( .oSEG0(HEX0),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:631: Cannot find file containing module: \'VGA_Controller\'\nVGA_Controller u1 ( \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:658: Cannot find file containing module: \'VGA_OSD_RAM\'\nVGA_OSD_RAM u2 ( \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:680: Cannot find file containing module: \'I2C_AV_Config\'\nI2C_AV_Config u3 ( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:687: Cannot find file containing module: \'AUDIO_DAC\'\nAUDIO_DAC u4 ( \n^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:697: Cannot find file containing module: \'LCD_TEST\'\nLCD_TEST u5 ( \n^~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:711: Cannot find file containing module: \'KEYBOARD_DEC\'\nKEYBOARD_DEC u6 ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:725: Cannot find file containing module: \'VGA_CHAR_RAM\'\nVGA_CHAR_RAM u7 ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:745: Cannot find file containing module: \'update_monitor_rom\'\nupdate_monitor_rom update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:747: Cannot find file containing module: \'VGA_CHAR_Ctrl\'\nVGA_CHAR_Ctrl u8 ( \n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:789: Operator ASSIGNDLY expects 36 bits on the Assign RHS, but Assign RHS\'s VARREF \'RAM_WDATA\' generates 32 bits.\n : ... In instance DE2_115_Default\n gpio_reg <= RAM_WDATA;\n ^~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:819: Cannot find file containing module: \'cpu\'\ncpu u9( \n^~~\n%Error: Exiting due to 13 error(s), 5 warning(s)\n' | 1,671 | module | module DE2_115_Default(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
SMA_CLKIN,
SMA_CLKOUT,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
EEP_I2C_SCLK,
EEP_I2C_SDAT,
I2C_SCLK,
I2C_SDAT,
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
IRDA_RXD,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
GPIO,
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
HSMC_RX_D_P,
HSMC_TX_D_P,
EX_IO
);
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input ENETCLK_25;
input SMA_CLKIN;
output SMA_CLKOUT;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output LCD_BLON;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
output UART_CTS;
input UART_RTS;
input UART_RXD;
output UART_TXD;
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_N;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output EEP_I2C_SCLK;
inout EEP_I2C_SDAT;
output I2C_SCLK;
inout I2C_SDAT;
output ENET0_GTX_CLK;
input ENET0_INT_N;
output ENET0_MDC;
input ENET0_MDIO;
output ENET0_RST_N;
input ENET0_RX_CLK;
input ENET0_RX_COL;
input ENET0_RX_CRS;
input [3:0] ENET0_RX_DATA;
input ENET0_RX_DV;
input ENET0_RX_ER;
input ENET0_TX_CLK;
output [3:0] ENET0_TX_DATA;
output ENET0_TX_EN;
output ENET0_TX_ER;
input ENET0_LINK100;
output ENET1_GTX_CLK;
input ENET1_INT_N;
output ENET1_MDC;
input ENET1_MDIO;
output ENET1_RST_N;
input ENET1_RX_CLK;
input ENET1_RX_COL;
input ENET1_RX_CRS;
input [3:0] ENET1_RX_DATA;
input ENET1_RX_DV;
input ENET1_RX_ER;
input ENET1_TX_CLK;
output [3:0] ENET1_TX_DATA;
output ENET1_TX_EN;
output ENET1_TX_ER;
input ENET1_LINK100;
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
inout [15:0] OTG_DATA;
output [1:0] OTG_ADDR;
output OTG_CS_N;
output OTG_WR_N;
output OTG_RD_N;
input OTG_INT;
output OTG_RST_N;
input IRDA_RXD;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [31:0] DRAM_DQ;
output [3:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
output [22:0] FL_ADDR;
output FL_CE_N;
inout [7:0] FL_DQ;
output FL_OE_N;
output FL_RST_N;
input FL_RY;
output FL_WE_N;
output FL_WP_N;
inout [35:0] GPIO;
input HSMC_CLKIN_P1;
input HSMC_CLKIN_P2;
input HSMC_CLKIN0;
output HSMC_CLKOUT_P1;
output HSMC_CLKOUT_P2;
output HSMC_CLKOUT0;
inout [3:0] HSMC_D;
input [16:0] HSMC_RX_D_P;
output [16:0] HSMC_TX_D_P;
inout [6:0] EX_IO;
wire AUD_CTRL_CLK;
wire [31:0] mSEG7_DIG;
wire VGA_CTRL_CLK;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
wire [19:0] mVGA_ADDR;
wire mVGA_WEN;
wire [9:0] mVGA_CoordX;
wire [9:0] mVGA_CoordY;
wire DLY_RST;
wire mVGA_CLK;
wire [9:0] mRed;
wire [9:0] mGreen;
wire [9:0] mBlue;
wire VGA_Read;
wire [9:0] recon_VGA_R;
wire [9:0] recon_VGA_G;
wire [9:0] recon_VGA_B;
wire [3:0] Remain;
wire [9:0] Quotient;
wire mDVAL;
wire [7:0] LCD_D_1;
wire LCD_RW_1;
wire LCD_EN_1;
wire LCD_RS_1;
wire [7:0] key_data_D;
wire key_parity_D;
wire key_stopbit_D;
wire [7:0] key_ascii_D;
wire key_stroke;
wire pixel_val;
wire [4:0] PUT_ROW;
wire [5:0] PUT_COL;
wire PUT_EN;
wire [7:0] PUT_DATA;
wire [8:0] ROW_Cursor;
wire [9:0] COL_Cursor;
wire CLOCK_CPU;
wire [11:0] PC;
wire [31:0] ALU_Y;
wire [31:0] ALU_A;
wire [31:0] ALU_B;
wire [3:0] ALU_CTRL;
wire [1:0] ALU_COMP;
wire [31:0] REG_DATA1;
wire [4:0] REG_IDX1;
wire [31:0] REG_DATA2;
wire [4:0] REG_IDX2;
wire [31:0] REG_WDATA;
wire [4:0] REG_WIDX;
wire REG_WEN;
wire [12:0] RAM_ADDR;
wire [31:0] RAM_RDATA;
wire [31:0] RAM_WDATA;
wire RAM_WEN;
wire [12:0] toRAM_ADDR;
wire [31:0] toRAM_WDATA;
wire toRAM_WEN;
wire cpu_clk;
reg cpu_clk_reg;
reg key1_reg;
reg sw0_reg;
reg sw1_reg;
reg [31:0] Cont;
reg [35:0] gpio_reg;
assign LCD_DATA = LCD_D_1;
assign LCD_RW = LCD_RW_1;
assign LCD_EN = LCD_EN_1;
assign LCD_RS = LCD_RS_1;
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b0;
assign DRAM_DQ = 32'hzzzzzzzz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_DACDAT = 1'bz;
assign AUD_BCLK = 1'bz;
assign AUD_XCK = 1'bz;
assign I2C_SDAT = 1'bz;
assign I2C_SCLK = 1'bz;
assign EEP_I2C_SDAT = 1'bz;
assign EEP_I2C_SCLK = 1'bz;
assign SD_DAT = 4'bz;
assign SD_CMD = 1'bz;
assign SD_CLK = 1'bz;
assign OTG_DATA = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SD_DAT = 4'bz;
assign GPIO = 36'hzzzzzzzz;
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
assign DRAM_DQ = 32'hzzzzzzzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 4'bz;
always@(posedge CLOCK_50 or negedge KEY[2])
begin
if(!KEY[2])
Cont <= 0;
else
Cont <= Cont+1;
end
assign TD_RESET_N = 1'b1;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
assign mSEG7_DIG = { key_ascii_D[7:4], key_ascii_D[3:0],
key_data_D[7:4], key_data_D[3:0], 8'b0000, PC};
assign LEDR = { Cont[26:24],Cont[26:24],Cont[26:24],
Cont[26:24],Cont[26:24],Cont[26:24] };
assign LEDG = { Cont[26:24],Cont[26:24],Cont[26:24] };
assign ROW_Cursor = (PUT_ROW+1)*16+1;
assign COL_Cursor = PUT_COL*16;
Reset_Delay r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );
VGA_Audio_PLL p1 ( .areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK) );
SEG7_LUT_8 u0 ( .oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.oSEG6(HEX6),
.oSEG7(HEX7),
.iDIG(mSEG7_DIG) );
assign VGA_CLK = VGA_CTRL_CLK;
VGA_Controller u1 (
.iCursor_RGB_EN(4'hf),
.iCursor_X(COL_Cursor),
.iCursor_Y(ROW_Cursor),
.iCursor_R(512),
.iCursor_G(0),
.iCursor_B(0),
.oAddress(mVGA_ADDR),
.oCoord_X(mVGA_CoordX),
.oCoord_Y(mVGA_CoordY),
.oWen(mVGA_WEN),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC_N),
.oVGA_BLANK(VGA_BLANK_N),
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST) );
VGA_OSD_RAM u2 (
.oRed(mVGA_R),
.oGreen(mVGA_G),
.oBlue(mVGA_B),
.iVGA_ADDR(mVGA_ADDR),
.iVGA_CLK(VGA_CLK),
.iWR_DATA(pixel_val),
.iWR_ADDR(mVGA_ADDR),
.iWR_EN(mVGA_WEN),
.iWR_CLK(VGA_CLK),
.iON_R(1023),
.iON_G(1023),
.iON_B(1023),
.iOFF_R(0),
.iOFF_G(0),
.iOFF_B(512),
.iRST_N(DLY_RST) );
I2C_AV_Config u3 (
.iCLK(CLOCK_50),
.iRST_N(KEY[2]),
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
AUDIO_DAC u4 (
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
.iSrc_Select(SW[17]),
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY_RST) );
LCD_TEST u5 (
.iCLK(CLOCK_50),
.iRST_N(DLY_RST),
.LCD_DATA(LCD_D_1),
.LCD_RW(LCD_RW_1),
.LCD_EN(LCD_EN_1),
.LCD_RS(LCD_RS_1) );
KEYBOARD_DEC u6 (
.iClock (CLOCK_50),
.iReset_N (KEY[2]),
.iKeyboard_DATA (PS2_DAT),
.iKeyboard_CLOCK (PS2_CLK),
.oKey_data_D (key_data_D),
.oKey_parity_D (key_parity_D),
.oKey_stopbit_D (key_stopbit_D),
.oKey_ascii_D (key_ascii_D),
.oKey_stroke (key_stroke)
);
VGA_CHAR_RAM u7 (
.oPIXEL_VAL (pixel_val),
.iVGA_ADDR (mVGA_ADDR),
.iVGA_CoordX (mVGA_CoordX),
.iVGA_CoordY (mVGA_CoordY),
.iVGA_CLK (VGA_CLK),
.iWR_DATA(PUT_DATA),
.iWR_PUT_ROW (PUT_ROW),
.iWR_PUT_COL (PUT_COL),
.iWR_EN (PUT_EN),
.iWR_CLK (VGA_CTRL_CLK),
.iRST_N (DLY_RST)
);
wire[9:0] romMonitorAddr;
wire[31:0] romMonitorRdat;
update_monitor_rom update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));
VGA_CHAR_Ctrl u8 (
.ikey_ascii_D (key_ascii_D),
.ikey_stroke (key_stroke),
.imVGA_WEN (mVGA_WEN),
.iVGA_CLK (VGA_CLK),
.iCLOCK (CLOCK_50),
.iPC (PC),
.iALU_Y (ALU_Y),
.iALU_A (ALU_A),
.iALU_B (ALU_B),
.iALU_CTRL (ALU_CTRL),
.iALU_COMP (ALU_COMP),
.iREG_DATA1 (REG_DATA1),
.iREG_IDX1 (REG_IDX1),
.iREG_DATA2 (REG_DATA2),
.iREG_IDX2 (REG_IDX2),
.iREG_WDATA (REG_WDATA),
.iREG_WIDX (REG_WIDX),
.iREG_WEN (REG_WEN),
.iRAM_ADDR (RAM_ADDR),
.iRAM_RDATA (RAM_RDATA),
.iRAM_WDATA (RAM_WDATA),
.iRAM_WEN (RAM_WEN),
.oCurrentPosRow (PUT_ROW),
.oCurrentPosCol (PUT_COL),
.oPUT_EN (PUT_EN),
.oPUT_DATA (PUT_DATA),
.oRAM_ADDR (toRAM_ADDR),
.oRAM_WDATA (toRAM_WDATA),
.oRAM_WEN (toRAM_WEN),
.oROMmonitorADDR (romMonitorAddr),
.iROMmonitorRDAT (romMonitorRdat),
.iRST_N (KEY[2])
);
always @(posedge CLOCK_50 or negedge KEY[2]) begin
if (KEY[2] == 1'b0) begin
gpio_reg <= 0;
end else begin
if ((RAM_ADDR == `GPIO0_ADDR) && (RAM_WEN == 1'b1)) begin
gpio_reg <= RAM_WDATA;
end
end
end
assign GPIO = gpio_reg;
always @(posedge CLOCK_50 or negedge KEY[2]) begin
if (KEY[2] == 1'b0) begin
cpu_clk_reg <= 1'b0;
key1_reg <= 1'b0;
sw0_reg <= 1'b0;
sw1_reg <= 1'b0;
end else begin
if (key1_reg != KEY[3]) begin
key1_reg <= KEY[3];
end
if (sw0_reg != SW[0]) begin
sw0_reg <= SW[0];
end
if (sw1_reg != SW[1]) begin
sw1_reg <= SW[1];
end
end
end
assign cpu_clk = CLOCK_50;
cpu u9(
.clk (cpu_clk),
.reset (KEY[2]),
.clk_ctrl0 (sw0_reg),
.clk_ctrl1 (sw1_reg),
.clk_ctrl_clk (key1_reg),
.o_clock (CLOCK_CPU),
.o_pc (PC),
.o_alu_y (ALU_Y),
.o_alu_a (ALU_A),
.o_alu_b (ALU_B),
.o_alu_ctrl (ALU_CTRL),
.o_alu_comp (ALU_COMP),
.o_reg_data1 (REG_DATA1),
.o_reg_idx1 (REG_IDX1),
.o_reg_data2 (REG_DATA2),
.o_reg_idx2 (REG_IDX2),
.o_reg_wdata (REG_WDATA),
.o_reg_widx (REG_WIDX),
.o_reg_wen (REG_WEN),
.o_ram_addr (RAM_ADDR),
.o_ram_rdata (RAM_RDATA),
.o_ram_wdata (RAM_WDATA),
.o_ram_wen (RAM_WEN),
.i_ram_addr (toRAM_ADDR),
.i_ram_wdata (toRAM_WDATA),
.i_ram_wen (toRAM_WEN),
);
endmodule | module DE2_115_Default(
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
SMA_CLKIN,
SMA_CLKOUT,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LCD_BLON,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW,
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
EEP_I2C_SCLK,
EEP_I2C_SDAT,
I2C_SCLK,
I2C_SDAT,
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
IRDA_RXD,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
GPIO,
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
HSMC_RX_D_P,
HSMC_TX_D_P,
EX_IO
); |
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input ENETCLK_25;
input SMA_CLKIN;
output SMA_CLKOUT;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output LCD_BLON;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
output UART_CTS;
input UART_RTS;
input UART_RXD;
output UART_TXD;
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_N;
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output EEP_I2C_SCLK;
inout EEP_I2C_SDAT;
output I2C_SCLK;
inout I2C_SDAT;
output ENET0_GTX_CLK;
input ENET0_INT_N;
output ENET0_MDC;
input ENET0_MDIO;
output ENET0_RST_N;
input ENET0_RX_CLK;
input ENET0_RX_COL;
input ENET0_RX_CRS;
input [3:0] ENET0_RX_DATA;
input ENET0_RX_DV;
input ENET0_RX_ER;
input ENET0_TX_CLK;
output [3:0] ENET0_TX_DATA;
output ENET0_TX_EN;
output ENET0_TX_ER;
input ENET0_LINK100;
output ENET1_GTX_CLK;
input ENET1_INT_N;
output ENET1_MDC;
input ENET1_MDIO;
output ENET1_RST_N;
input ENET1_RX_CLK;
input ENET1_RX_COL;
input ENET1_RX_CRS;
input [3:0] ENET1_RX_DATA;
input ENET1_RX_DV;
input ENET1_RX_ER;
input ENET1_TX_CLK;
output [3:0] ENET1_TX_DATA;
output ENET1_TX_EN;
output ENET1_TX_ER;
input ENET1_LINK100;
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
inout [15:0] OTG_DATA;
output [1:0] OTG_ADDR;
output OTG_CS_N;
output OTG_WR_N;
output OTG_RD_N;
input OTG_INT;
output OTG_RST_N;
input IRDA_RXD;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [31:0] DRAM_DQ;
output [3:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
output [22:0] FL_ADDR;
output FL_CE_N;
inout [7:0] FL_DQ;
output FL_OE_N;
output FL_RST_N;
input FL_RY;
output FL_WE_N;
output FL_WP_N;
inout [35:0] GPIO;
input HSMC_CLKIN_P1;
input HSMC_CLKIN_P2;
input HSMC_CLKIN0;
output HSMC_CLKOUT_P1;
output HSMC_CLKOUT_P2;
output HSMC_CLKOUT0;
inout [3:0] HSMC_D;
input [16:0] HSMC_RX_D_P;
output [16:0] HSMC_TX_D_P;
inout [6:0] EX_IO;
wire AUD_CTRL_CLK;
wire [31:0] mSEG7_DIG;
wire VGA_CTRL_CLK;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
wire [19:0] mVGA_ADDR;
wire mVGA_WEN;
wire [9:0] mVGA_CoordX;
wire [9:0] mVGA_CoordY;
wire DLY_RST;
wire mVGA_CLK;
wire [9:0] mRed;
wire [9:0] mGreen;
wire [9:0] mBlue;
wire VGA_Read;
wire [9:0] recon_VGA_R;
wire [9:0] recon_VGA_G;
wire [9:0] recon_VGA_B;
wire [3:0] Remain;
wire [9:0] Quotient;
wire mDVAL;
wire [7:0] LCD_D_1;
wire LCD_RW_1;
wire LCD_EN_1;
wire LCD_RS_1;
wire [7:0] key_data_D;
wire key_parity_D;
wire key_stopbit_D;
wire [7:0] key_ascii_D;
wire key_stroke;
wire pixel_val;
wire [4:0] PUT_ROW;
wire [5:0] PUT_COL;
wire PUT_EN;
wire [7:0] PUT_DATA;
wire [8:0] ROW_Cursor;
wire [9:0] COL_Cursor;
wire CLOCK_CPU;
wire [11:0] PC;
wire [31:0] ALU_Y;
wire [31:0] ALU_A;
wire [31:0] ALU_B;
wire [3:0] ALU_CTRL;
wire [1:0] ALU_COMP;
wire [31:0] REG_DATA1;
wire [4:0] REG_IDX1;
wire [31:0] REG_DATA2;
wire [4:0] REG_IDX2;
wire [31:0] REG_WDATA;
wire [4:0] REG_WIDX;
wire REG_WEN;
wire [12:0] RAM_ADDR;
wire [31:0] RAM_RDATA;
wire [31:0] RAM_WDATA;
wire RAM_WEN;
wire [12:0] toRAM_ADDR;
wire [31:0] toRAM_WDATA;
wire toRAM_WEN;
wire cpu_clk;
reg cpu_clk_reg;
reg key1_reg;
reg sw0_reg;
reg sw1_reg;
reg [31:0] Cont;
reg [35:0] gpio_reg;
assign LCD_DATA = LCD_D_1;
assign LCD_RW = LCD_RW_1;
assign LCD_EN = LCD_EN_1;
assign LCD_RS = LCD_RS_1;
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b0;
assign DRAM_DQ = 32'hzzzzzzzz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_DACDAT = 1'bz;
assign AUD_BCLK = 1'bz;
assign AUD_XCK = 1'bz;
assign I2C_SDAT = 1'bz;
assign I2C_SCLK = 1'bz;
assign EEP_I2C_SDAT = 1'bz;
assign EEP_I2C_SCLK = 1'bz;
assign SD_DAT = 4'bz;
assign SD_CMD = 1'bz;
assign SD_CLK = 1'bz;
assign OTG_DATA = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SD_DAT = 4'bz;
assign GPIO = 36'hzzzzzzzz;
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
assign DRAM_DQ = 32'hzzzzzzzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 4'bz;
always@(posedge CLOCK_50 or negedge KEY[2])
begin
if(!KEY[2])
Cont <= 0;
else
Cont <= Cont+1;
end
assign TD_RESET_N = 1'b1;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
assign mSEG7_DIG = { key_ascii_D[7:4], key_ascii_D[3:0],
key_data_D[7:4], key_data_D[3:0], 8'b0000, PC};
assign LEDR = { Cont[26:24],Cont[26:24],Cont[26:24],
Cont[26:24],Cont[26:24],Cont[26:24] };
assign LEDG = { Cont[26:24],Cont[26:24],Cont[26:24] };
assign ROW_Cursor = (PUT_ROW+1)*16+1;
assign COL_Cursor = PUT_COL*16;
Reset_Delay r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );
VGA_Audio_PLL p1 ( .areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK) );
SEG7_LUT_8 u0 ( .oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.oSEG6(HEX6),
.oSEG7(HEX7),
.iDIG(mSEG7_DIG) );
assign VGA_CLK = VGA_CTRL_CLK;
VGA_Controller u1 (
.iCursor_RGB_EN(4'hf),
.iCursor_X(COL_Cursor),
.iCursor_Y(ROW_Cursor),
.iCursor_R(512),
.iCursor_G(0),
.iCursor_B(0),
.oAddress(mVGA_ADDR),
.oCoord_X(mVGA_CoordX),
.oCoord_Y(mVGA_CoordY),
.oWen(mVGA_WEN),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC_N),
.oVGA_BLANK(VGA_BLANK_N),
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST) );
VGA_OSD_RAM u2 (
.oRed(mVGA_R),
.oGreen(mVGA_G),
.oBlue(mVGA_B),
.iVGA_ADDR(mVGA_ADDR),
.iVGA_CLK(VGA_CLK),
.iWR_DATA(pixel_val),
.iWR_ADDR(mVGA_ADDR),
.iWR_EN(mVGA_WEN),
.iWR_CLK(VGA_CLK),
.iON_R(1023),
.iON_G(1023),
.iON_B(1023),
.iOFF_R(0),
.iOFF_G(0),
.iOFF_B(512),
.iRST_N(DLY_RST) );
I2C_AV_Config u3 (
.iCLK(CLOCK_50),
.iRST_N(KEY[2]),
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
AUDIO_DAC u4 (
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
.iSrc_Select(SW[17]),
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY_RST) );
LCD_TEST u5 (
.iCLK(CLOCK_50),
.iRST_N(DLY_RST),
.LCD_DATA(LCD_D_1),
.LCD_RW(LCD_RW_1),
.LCD_EN(LCD_EN_1),
.LCD_RS(LCD_RS_1) );
KEYBOARD_DEC u6 (
.iClock (CLOCK_50),
.iReset_N (KEY[2]),
.iKeyboard_DATA (PS2_DAT),
.iKeyboard_CLOCK (PS2_CLK),
.oKey_data_D (key_data_D),
.oKey_parity_D (key_parity_D),
.oKey_stopbit_D (key_stopbit_D),
.oKey_ascii_D (key_ascii_D),
.oKey_stroke (key_stroke)
);
VGA_CHAR_RAM u7 (
.oPIXEL_VAL (pixel_val),
.iVGA_ADDR (mVGA_ADDR),
.iVGA_CoordX (mVGA_CoordX),
.iVGA_CoordY (mVGA_CoordY),
.iVGA_CLK (VGA_CLK),
.iWR_DATA(PUT_DATA),
.iWR_PUT_ROW (PUT_ROW),
.iWR_PUT_COL (PUT_COL),
.iWR_EN (PUT_EN),
.iWR_CLK (VGA_CTRL_CLK),
.iRST_N (DLY_RST)
);
wire[9:0] romMonitorAddr;
wire[31:0] romMonitorRdat;
update_monitor_rom update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));
VGA_CHAR_Ctrl u8 (
.ikey_ascii_D (key_ascii_D),
.ikey_stroke (key_stroke),
.imVGA_WEN (mVGA_WEN),
.iVGA_CLK (VGA_CLK),
.iCLOCK (CLOCK_50),
.iPC (PC),
.iALU_Y (ALU_Y),
.iALU_A (ALU_A),
.iALU_B (ALU_B),
.iALU_CTRL (ALU_CTRL),
.iALU_COMP (ALU_COMP),
.iREG_DATA1 (REG_DATA1),
.iREG_IDX1 (REG_IDX1),
.iREG_DATA2 (REG_DATA2),
.iREG_IDX2 (REG_IDX2),
.iREG_WDATA (REG_WDATA),
.iREG_WIDX (REG_WIDX),
.iREG_WEN (REG_WEN),
.iRAM_ADDR (RAM_ADDR),
.iRAM_RDATA (RAM_RDATA),
.iRAM_WDATA (RAM_WDATA),
.iRAM_WEN (RAM_WEN),
.oCurrentPosRow (PUT_ROW),
.oCurrentPosCol (PUT_COL),
.oPUT_EN (PUT_EN),
.oPUT_DATA (PUT_DATA),
.oRAM_ADDR (toRAM_ADDR),
.oRAM_WDATA (toRAM_WDATA),
.oRAM_WEN (toRAM_WEN),
.oROMmonitorADDR (romMonitorAddr),
.iROMmonitorRDAT (romMonitorRdat),
.iRST_N (KEY[2])
);
always @(posedge CLOCK_50 or negedge KEY[2]) begin
if (KEY[2] == 1'b0) begin
gpio_reg <= 0;
end else begin
if ((RAM_ADDR == `GPIO0_ADDR) && (RAM_WEN == 1'b1)) begin
gpio_reg <= RAM_WDATA;
end
end
end
assign GPIO = gpio_reg;
always @(posedge CLOCK_50 or negedge KEY[2]) begin
if (KEY[2] == 1'b0) begin
cpu_clk_reg <= 1'b0;
key1_reg <= 1'b0;
sw0_reg <= 1'b0;
sw1_reg <= 1'b0;
end else begin
if (key1_reg != KEY[3]) begin
key1_reg <= KEY[3];
end
if (sw0_reg != SW[0]) begin
sw0_reg <= SW[0];
end
if (sw1_reg != SW[1]) begin
sw1_reg <= SW[1];
end
end
end
assign cpu_clk = CLOCK_50;
cpu u9(
.clk (cpu_clk),
.reset (KEY[2]),
.clk_ctrl0 (sw0_reg),
.clk_ctrl1 (sw1_reg),
.clk_ctrl_clk (key1_reg),
.o_clock (CLOCK_CPU),
.o_pc (PC),
.o_alu_y (ALU_Y),
.o_alu_a (ALU_A),
.o_alu_b (ALU_B),
.o_alu_ctrl (ALU_CTRL),
.o_alu_comp (ALU_COMP),
.o_reg_data1 (REG_DATA1),
.o_reg_idx1 (REG_IDX1),
.o_reg_data2 (REG_DATA2),
.o_reg_idx2 (REG_IDX2),
.o_reg_wdata (REG_WDATA),
.o_reg_widx (REG_WIDX),
.o_reg_wen (REG_WEN),
.o_ram_addr (RAM_ADDR),
.o_ram_rdata (RAM_RDATA),
.o_ram_wdata (RAM_WDATA),
.o_ram_wen (RAM_WEN),
.i_ram_addr (toRAM_ADDR),
.i_ram_wdata (toRAM_WDATA),
.i_ram_wen (toRAM_WEN),
);
endmodule | 0 |
3,888 | data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v | 107,499,099 | VGA_CHAR_Ctrl_UpdateMONITOR.v | v | 259 | 59 | [] | [] | [] | null | line:10: before: "," | null | 1: b"%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:10: Define or directive not defined: '`PC3col'\n data[17:7] <= {`PC3col,`PC3row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:10: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`PC3col,`PC3row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:10: Define or directive not defined: '`PC3row'\n data[17:7] <= {`PC3col,`PC3row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:13: Define or directive not defined: '`PC2col'\n data[17:7] <= {`PC2col,`PC2row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:13: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`PC2col,`PC2row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:13: Define or directive not defined: '`PC2row'\n data[17:7] <= {`PC2col,`PC2row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:16: Define or directive not defined: '`PC1col'\n data[17:7] <= {`PC1col,`PC1row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:16: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`PC1col,`PC1row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:16: Define or directive not defined: '`PC1row'\n data[17:7] <= {`PC1col,`PC1row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:19: Define or directive not defined: '`PC0col'\n data[17:7] <= {`PC0col,`PC0row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:19: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`PC0col,`PC0row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:19: Define or directive not defined: '`PC0row'\n data[17:7] <= {`PC0col,`PC0row};\n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:22: Define or directive not defined: '`ALUY7col'\n data[17:7] <= {`ALUY7col,`ALUY7row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:22: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY7col,`ALUY7row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:22: Define or directive not defined: '`ALUY7row'\n data[17:7] <= {`ALUY7col,`ALUY7row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:25: Define or directive not defined: '`ALUY6col'\n data[17:7] <= {`ALUY6col,`ALUY6row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:25: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY6col,`ALUY6row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:25: Define or directive not defined: '`ALUY6row'\n data[17:7] <= {`ALUY6col,`ALUY6row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:28: Define or directive not defined: '`ALUY5col'\n data[17:7] <= {`ALUY5col,`ALUY5row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:28: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY5col,`ALUY5row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:28: Define or directive not defined: '`ALUY5row'\n data[17:7] <= {`ALUY5col,`ALUY5row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:31: Define or directive not defined: '`ALUY4col'\n data[17:7] <= {`ALUY4col,`ALUY4row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:31: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY4col,`ALUY4row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:31: Define or directive not defined: '`ALUY4row'\n data[17:7] <= {`ALUY4col,`ALUY4row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:34: Define or directive not defined: '`ALUY3col'\n data[17:7] <= {`ALUY3col,`ALUY3row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:34: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY3col,`ALUY3row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:34: Define or directive not defined: '`ALUY3row'\n data[17:7] <= {`ALUY3col,`ALUY3row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:37: Define or directive not defined: '`ALUY2col'\n data[17:7] <= {`ALUY2col,`ALUY2row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:37: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY2col,`ALUY2row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:37: Define or directive not defined: '`ALUY2row'\n data[17:7] <= {`ALUY2col,`ALUY2row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:40: Define or directive not defined: '`ALUY1col'\n data[17:7] <= {`ALUY1col,`ALUY1row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:40: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY1col,`ALUY1row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:40: Define or directive not defined: '`ALUY1row'\n data[17:7] <= {`ALUY1col,`ALUY1row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:43: Define or directive not defined: '`ALUY0col'\n data[17:7] <= {`ALUY0col,`ALUY0row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:43: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUY0col,`ALUY0row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:43: Define or directive not defined: '`ALUY0row'\n data[17:7] <= {`ALUY0col,`ALUY0row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:46: Define or directive not defined: '`ALUA7col'\n data[17:7] <= {`ALUA7col,`ALUA7row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:46: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUA7col,`ALUA7row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:46: Define or directive not defined: '`ALUA7row'\n data[17:7] <= {`ALUA7col,`ALUA7row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:49: Define or directive not defined: '`ALUA6col'\n data[17:7] <= {`ALUA6col,`ALUA6row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:49: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUA6col,`ALUA6row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:49: Define or directive not defined: '`ALUA6row'\n data[17:7] <= {`ALUA6col,`ALUA6row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:52: Define or directive not defined: '`ALUA5col'\n data[17:7] <= {`ALUA5col,`ALUA5row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:52: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUA5col,`ALUA5row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:52: Define or directive not defined: '`ALUA5row'\n data[17:7] <= {`ALUA5col,`ALUA5row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:55: Define or directive not defined: '`ALUA4col'\n data[17:7] <= {`ALUA4col,`ALUA4row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:55: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUA4col,`ALUA4row};\n ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:55: Define or directive not defined: '`ALUA4row'\n data[17:7] <= {`ALUA4col,`ALUA4row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:58: Define or directive not defined: '`ALUA3col'\n data[17:7] <= {`ALUA3col,`ALUA3row};\n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/VGA_CHAR_Ctrl_UpdateMONITOR.v:58: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n data[17:7] <= {`ALUA3col,`ALUA3row};\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 1,675 | module | module update_monitor_rom(addr, data);
input [9:0] addr;
output [31:0] data;
reg [31:0] data;
always @(addr) begin
if(addr == 0) begin
data[17:7] <= {`PC3col,`PC3row};
end else
if(addr == 1) begin
data[17:7] <= {`PC2col,`PC2row};
end else
if(addr == 2) begin
data[17:7] <= {`PC1col,`PC1row};
end else
if(addr == 3) begin
data[17:7] <= {`PC0col,`PC0row};
end else
if(addr == 4) begin
data[17:7] <= {`ALUY7col,`ALUY7row};
end else
if(addr == 5) begin
data[17:7] <= {`ALUY6col,`ALUY6row};
end else
if(addr == 6) begin
data[17:7] <= {`ALUY5col,`ALUY5row};
end else
if(addr == 7) begin
data[17:7] <= {`ALUY4col,`ALUY4row};
end else
if(addr == 8) begin
data[17:7] <= {`ALUY3col,`ALUY3row};
end else
if(addr == 9) begin
data[17:7] <= {`ALUY2col,`ALUY2row};
end else
if(addr == 10) begin
data[17:7] <= {`ALUY1col,`ALUY1row};
end else
if(addr == 11) begin
data[17:7] <= {`ALUY0col,`ALUY0row};
end else
if(addr == 12) begin
data[17:7] <= {`ALUA7col,`ALUA7row};
end else
if(addr == 13) begin
data[17:7] <= {`ALUA6col,`ALUA6row};
end else
if(addr == 14) begin
data[17:7] <= {`ALUA5col,`ALUA5row};
end else
if(addr == 15) begin
data[17:7] <= {`ALUA4col,`ALUA4row};
end else
if(addr == 16) begin
data[17:7] <= {`ALUA3col,`ALUA3row};
end else
if(addr == 17) begin
data[17:7] <= {`ALUA2col,`ALUA2row};
end else
if(addr == 18) begin
data[17:7] <= {`ALUA1col,`ALUA1row};
end else
if(addr == 19) begin
data[17:7] <= {`ALUA0col,`ALUA0row};
end else
if(addr == 20) begin
data[17:7] <= {`ALUCTRL0col,`ALUCTRL0row};
end else
if(addr == 21) begin
data[17:7] <= {`ALUB7col,`ALUB7row};
end else
if(addr == 22) begin
data[17:7] <= {`ALUB6col,`ALUB6row};
end else
if(addr == 23) begin
data[17:7] <= {`ALUB5col,`ALUB5row};
end else
if(addr == 24) begin
data[17:7] <= {`ALUB4col,`ALUB4row};
end else
if(addr == 25) begin
data[17:7] <= {`ALUB3col,`ALUB3row};
end else
if(addr == 26) begin
data[17:7] <= {`ALUB2col,`ALUB2row};
end else
if(addr == 27) begin
data[17:7] <= {`ALUB1col,`ALUB1row};
end else
if(addr == 28) begin
data[17:7] <= {`ALUB0col,`ALUB0row};
end else
if(addr == 29) begin
data[17:7] <= {`ALUCOMP0col,`ALUCOMP0row};
end else
if(addr == 30) begin
data[17:7] <= {`REGDATA1_7col,`REGDATA1_7row};
end else
if(addr == 31) begin
data[17:7] <= {`REGDATA1_6col,`REGDATA1_6row};
end else
if(addr == 32) begin
data[17:7] <= {`REGDATA1_5col,`REGDATA1_5row};
end else
if(addr == 33) begin
data[17:7] <= {`REGDATA1_4col,`REGDATA1_4row};
end else
if(addr == 34) begin
data[17:7] <= {`REGDATA1_3col,`REGDATA1_3row};
end else
if(addr == 35) begin
data[17:7] <= {`REGDATA1_2col,`REGDATA1_2row};
end else
if(addr == 36) begin
data[17:7] <= {`REGDATA1_1col,`REGDATA1_1row};
end else
if(addr == 37) begin
data[17:7] <= {`REGDATA1_0col,`REGDATA1_0row};
end else
if(addr == 38) begin
data[17:7] <= {`REGIDX1_1col,`REGIDX1_1row};
end else
if(addr == 39) begin
data[17:7] <= {`REGIDX1_0col,`REGIDX1_0row};
end else
if(addr == 40) begin
data[17:7] <= {`REGDATA2_7col,`REGDATA2_7row};
end else
if(addr == 41) begin
data[17:7] <= {`REGDATA2_6col,`REGDATA2_6row};
end else
if(addr == 42) begin
data[17:7] <= {`REGDATA2_5col,`REGDATA2_5row};
end else
if(addr == 43) begin
data[17:7] <= {`REGDATA2_4col,`REGDATA2_4row};
end else
if(addr == 44) begin
data[17:7] <= {`REGDATA2_3col,`REGDATA2_3row};
end else
if(addr == 45) begin
data[17:7] <= {`REGDATA2_2col,`REGDATA2_2row};
end else
if(addr == 46) begin
data[17:7] <= {`REGDATA2_1col,`REGDATA2_1row};
end else
if(addr == 47) begin
data[17:7] <= {`REGDATA2_0col,`REGDATA2_0row};
end else
if(addr == 48) begin
data[17:7] <= {`REGIDX2_1col,`REGIDX2_1row};
end else
if(addr == 49) begin
data[17:7] <= {`REGIDX2_0col,`REGIDX2_0row};
end else
if(addr == 50) begin
data[17:7] <= {`REGWDATA_7col,`REGWDATA_7row};
end else
if(addr == 51) begin
data[17:7] <= {`REGWDATA_6col,`REGWDATA_6row};
end else
if(addr == 52) begin
data[17:7] <= {`REGWDATA_5col,`REGWDATA_5row};
end else
if(addr == 53) begin
data[17:7] <= {`REGWDATA_4col,`REGWDATA_4row};
end else
if(addr == 54) begin
data[17:7] <= {`REGWDATA_3col,`REGWDATA_3row};
end else
if(addr == 55) begin
data[17:7] <= {`REGWDATA_2col,`REGWDATA_2row};
end else
if(addr == 56) begin
data[17:7] <= {`REGWDATA_1col,`REGWDATA_1row};
end else
if(addr == 57) begin
data[17:7] <= {`REGWDATA_0col,`REGWDATA_0row};
end else
if(addr == 58) begin
data[17:7] <= {`REGWIDX_1col,`REGWIDX_1row};
end else
if(addr == 59) begin
data[17:7] <= {`REGWIDX_0col,`REGWIDX_0row};
end else
if(addr == 60) begin
data[17:7] <= {`REGWENcol,`REGWENrow};
end else
if(addr == 61) begin
data[17:7] <= {`RAMRDATA_7col,`RAMRDATA_7row};
end else
if(addr == 62) begin
data[17:7] <= {`RAMRDATA_6col,`RAMRDATA_6row};
end else
if(addr == 63) begin
data[17:7] <= {`RAMRDATA_5col,`RAMRDATA_5row};
end else
if(addr == 64) begin
data[17:7] <= {`RAMRDATA_4col,`RAMRDATA_4row};
end else
if(addr == 65) begin
data[17:7] <= {`RAMRDATA_3col,`RAMRDATA_3row};
end else
if(addr == 66) begin
data[17:7] <= {`RAMRDATA_2col,`RAMRDATA_2row};
end else
if(addr == 67) begin
data[17:7] <= {`RAMRDATA_1col,`RAMRDATA_1row};
end else
if(addr == 68) begin
data[17:7] <= {`RAMRDATA_0col,`RAMRDATA_0row};
end else
if(addr == 69) begin
data[17:7] <= {`RAMADDR_3col,`RAMADDR_3row};
end else
if(addr == 70) begin
data[17:7] <= {`RAMADDR_2col,`RAMADDR_2row};
end else
if(addr == 71) begin
data[17:7] <= {`RAMADDR_1col,`RAMADDR_1row};
end else
if(addr == 72) begin
data[17:7] <= {`RAMADDR_0col,`RAMADDR_0row};
end else
if(addr == 73) begin
data[17:7] <= {`RAMWDATA_7col,`RAMWDATA_7row};
end else
if(addr == 74) begin
data[17:7] <= {`RAMWDATA_6col,`RAMWDATA_6row};
end else
if(addr == 75) begin
data[17:7] <= {`RAMWDATA_5col,`RAMWDATA_5row};
end else
if(addr == 76) begin
data[17:7] <= {`RAMWDATA_4col,`RAMWDATA_4row};
end else
if(addr == 77) begin
data[17:7] <= {`RAMWDATA_3col,`RAMWDATA_3row};
end else
if(addr == 78) begin
data[17:7] <= {`RAMWDATA_2col,`RAMWDATA_2row};
end else
if(addr == 79) begin
data[17:7] <= {`RAMWDATA_1col,`RAMWDATA_1row};
end else
if(addr == 80) begin
data[17:7] <= {`RAMWDATA_0col,`RAMWDATA_0row};
end else
if(addr == 81) begin
data[17:7] <= {`RAMWENcol,`RAMWENrow};
end else begin
data <= 32'b0;
end
end
endmodule | module update_monitor_rom(addr, data); |
input [9:0] addr;
output [31:0] data;
reg [31:0] data;
always @(addr) begin
if(addr == 0) begin
data[17:7] <= {`PC3col,`PC3row};
end else
if(addr == 1) begin
data[17:7] <= {`PC2col,`PC2row};
end else
if(addr == 2) begin
data[17:7] <= {`PC1col,`PC1row};
end else
if(addr == 3) begin
data[17:7] <= {`PC0col,`PC0row};
end else
if(addr == 4) begin
data[17:7] <= {`ALUY7col,`ALUY7row};
end else
if(addr == 5) begin
data[17:7] <= {`ALUY6col,`ALUY6row};
end else
if(addr == 6) begin
data[17:7] <= {`ALUY5col,`ALUY5row};
end else
if(addr == 7) begin
data[17:7] <= {`ALUY4col,`ALUY4row};
end else
if(addr == 8) begin
data[17:7] <= {`ALUY3col,`ALUY3row};
end else
if(addr == 9) begin
data[17:7] <= {`ALUY2col,`ALUY2row};
end else
if(addr == 10) begin
data[17:7] <= {`ALUY1col,`ALUY1row};
end else
if(addr == 11) begin
data[17:7] <= {`ALUY0col,`ALUY0row};
end else
if(addr == 12) begin
data[17:7] <= {`ALUA7col,`ALUA7row};
end else
if(addr == 13) begin
data[17:7] <= {`ALUA6col,`ALUA6row};
end else
if(addr == 14) begin
data[17:7] <= {`ALUA5col,`ALUA5row};
end else
if(addr == 15) begin
data[17:7] <= {`ALUA4col,`ALUA4row};
end else
if(addr == 16) begin
data[17:7] <= {`ALUA3col,`ALUA3row};
end else
if(addr == 17) begin
data[17:7] <= {`ALUA2col,`ALUA2row};
end else
if(addr == 18) begin
data[17:7] <= {`ALUA1col,`ALUA1row};
end else
if(addr == 19) begin
data[17:7] <= {`ALUA0col,`ALUA0row};
end else
if(addr == 20) begin
data[17:7] <= {`ALUCTRL0col,`ALUCTRL0row};
end else
if(addr == 21) begin
data[17:7] <= {`ALUB7col,`ALUB7row};
end else
if(addr == 22) begin
data[17:7] <= {`ALUB6col,`ALUB6row};
end else
if(addr == 23) begin
data[17:7] <= {`ALUB5col,`ALUB5row};
end else
if(addr == 24) begin
data[17:7] <= {`ALUB4col,`ALUB4row};
end else
if(addr == 25) begin
data[17:7] <= {`ALUB3col,`ALUB3row};
end else
if(addr == 26) begin
data[17:7] <= {`ALUB2col,`ALUB2row};
end else
if(addr == 27) begin
data[17:7] <= {`ALUB1col,`ALUB1row};
end else
if(addr == 28) begin
data[17:7] <= {`ALUB0col,`ALUB0row};
end else
if(addr == 29) begin
data[17:7] <= {`ALUCOMP0col,`ALUCOMP0row};
end else
if(addr == 30) begin
data[17:7] <= {`REGDATA1_7col,`REGDATA1_7row};
end else
if(addr == 31) begin
data[17:7] <= {`REGDATA1_6col,`REGDATA1_6row};
end else
if(addr == 32) begin
data[17:7] <= {`REGDATA1_5col,`REGDATA1_5row};
end else
if(addr == 33) begin
data[17:7] <= {`REGDATA1_4col,`REGDATA1_4row};
end else
if(addr == 34) begin
data[17:7] <= {`REGDATA1_3col,`REGDATA1_3row};
end else
if(addr == 35) begin
data[17:7] <= {`REGDATA1_2col,`REGDATA1_2row};
end else
if(addr == 36) begin
data[17:7] <= {`REGDATA1_1col,`REGDATA1_1row};
end else
if(addr == 37) begin
data[17:7] <= {`REGDATA1_0col,`REGDATA1_0row};
end else
if(addr == 38) begin
data[17:7] <= {`REGIDX1_1col,`REGIDX1_1row};
end else
if(addr == 39) begin
data[17:7] <= {`REGIDX1_0col,`REGIDX1_0row};
end else
if(addr == 40) begin
data[17:7] <= {`REGDATA2_7col,`REGDATA2_7row};
end else
if(addr == 41) begin
data[17:7] <= {`REGDATA2_6col,`REGDATA2_6row};
end else
if(addr == 42) begin
data[17:7] <= {`REGDATA2_5col,`REGDATA2_5row};
end else
if(addr == 43) begin
data[17:7] <= {`REGDATA2_4col,`REGDATA2_4row};
end else
if(addr == 44) begin
data[17:7] <= {`REGDATA2_3col,`REGDATA2_3row};
end else
if(addr == 45) begin
data[17:7] <= {`REGDATA2_2col,`REGDATA2_2row};
end else
if(addr == 46) begin
data[17:7] <= {`REGDATA2_1col,`REGDATA2_1row};
end else
if(addr == 47) begin
data[17:7] <= {`REGDATA2_0col,`REGDATA2_0row};
end else
if(addr == 48) begin
data[17:7] <= {`REGIDX2_1col,`REGIDX2_1row};
end else
if(addr == 49) begin
data[17:7] <= {`REGIDX2_0col,`REGIDX2_0row};
end else
if(addr == 50) begin
data[17:7] <= {`REGWDATA_7col,`REGWDATA_7row};
end else
if(addr == 51) begin
data[17:7] <= {`REGWDATA_6col,`REGWDATA_6row};
end else
if(addr == 52) begin
data[17:7] <= {`REGWDATA_5col,`REGWDATA_5row};
end else
if(addr == 53) begin
data[17:7] <= {`REGWDATA_4col,`REGWDATA_4row};
end else
if(addr == 54) begin
data[17:7] <= {`REGWDATA_3col,`REGWDATA_3row};
end else
if(addr == 55) begin
data[17:7] <= {`REGWDATA_2col,`REGWDATA_2row};
end else
if(addr == 56) begin
data[17:7] <= {`REGWDATA_1col,`REGWDATA_1row};
end else
if(addr == 57) begin
data[17:7] <= {`REGWDATA_0col,`REGWDATA_0row};
end else
if(addr == 58) begin
data[17:7] <= {`REGWIDX_1col,`REGWIDX_1row};
end else
if(addr == 59) begin
data[17:7] <= {`REGWIDX_0col,`REGWIDX_0row};
end else
if(addr == 60) begin
data[17:7] <= {`REGWENcol,`REGWENrow};
end else
if(addr == 61) begin
data[17:7] <= {`RAMRDATA_7col,`RAMRDATA_7row};
end else
if(addr == 62) begin
data[17:7] <= {`RAMRDATA_6col,`RAMRDATA_6row};
end else
if(addr == 63) begin
data[17:7] <= {`RAMRDATA_5col,`RAMRDATA_5row};
end else
if(addr == 64) begin
data[17:7] <= {`RAMRDATA_4col,`RAMRDATA_4row};
end else
if(addr == 65) begin
data[17:7] <= {`RAMRDATA_3col,`RAMRDATA_3row};
end else
if(addr == 66) begin
data[17:7] <= {`RAMRDATA_2col,`RAMRDATA_2row};
end else
if(addr == 67) begin
data[17:7] <= {`RAMRDATA_1col,`RAMRDATA_1row};
end else
if(addr == 68) begin
data[17:7] <= {`RAMRDATA_0col,`RAMRDATA_0row};
end else
if(addr == 69) begin
data[17:7] <= {`RAMADDR_3col,`RAMADDR_3row};
end else
if(addr == 70) begin
data[17:7] <= {`RAMADDR_2col,`RAMADDR_2row};
end else
if(addr == 71) begin
data[17:7] <= {`RAMADDR_1col,`RAMADDR_1row};
end else
if(addr == 72) begin
data[17:7] <= {`RAMADDR_0col,`RAMADDR_0row};
end else
if(addr == 73) begin
data[17:7] <= {`RAMWDATA_7col,`RAMWDATA_7row};
end else
if(addr == 74) begin
data[17:7] <= {`RAMWDATA_6col,`RAMWDATA_6row};
end else
if(addr == 75) begin
data[17:7] <= {`RAMWDATA_5col,`RAMWDATA_5row};
end else
if(addr == 76) begin
data[17:7] <= {`RAMWDATA_4col,`RAMWDATA_4row};
end else
if(addr == 77) begin
data[17:7] <= {`RAMWDATA_3col,`RAMWDATA_3row};
end else
if(addr == 78) begin
data[17:7] <= {`RAMWDATA_2col,`RAMWDATA_2row};
end else
if(addr == 79) begin
data[17:7] <= {`RAMWDATA_1col,`RAMWDATA_1row};
end else
if(addr == 80) begin
data[17:7] <= {`RAMWDATA_0col,`RAMWDATA_0row};
end else
if(addr == 81) begin
data[17:7] <= {`RAMWENcol,`RAMWENrow};
end else begin
data <= 32'b0;
end
end
endmodule | 0 |
3,889 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/adder32.v | 107,499,099 | adder32.v | v | 17 | 53 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 195: invalid continuation byte | data/verilator_xmls/4908221c-ef1e-4980-b36a-a2ff86335e81.xml | null | 1,677 | module | module adder32 (add_a, add_b, add_y);
input [31:0] add_a;
input [31:0] add_b;
output [31:0] add_y;
assign add_y = add_a + add_b;
endmodule | module adder32 (add_a, add_b, add_y); |
input [31:0] add_a;
input [31:0] add_b;
output [31:0] add_y;
assign add_y = add_a + add_b;
endmodule | 0 |
3,890 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/alu.v | 107,499,099 | alu.v | v | 419 | 79 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xce in position 206: invalid continuation byte | data/verilator_xmls/ae45fe9f-0ec6-40e4-9a4d-7e06593093cf.xml | null | 1,678 | module | module alu (alu_a, alu_b, alu_ctrl, alu_y, alu_comp);
input [31:0] alu_a;
input [31:0] alu_b;
input [3:0] alu_ctrl;
output [31:0] alu_y;
output [1:0] alu_comp;
reg [31:0] result;
reg [1:0] comp;
always @(alu_a or alu_b or alu_ctrl or comp) begin
case (alu_ctrl)
`ALU_ADD: begin
result <= alu_a + alu_b;
end
`ALU_SUB: begin
result <= alu_a - alu_b;
end
`ALU_AND: begin
result <= alu_a & alu_b;
end
`ALU_OR: begin
result <= alu_a | alu_b;
end
`ALU_SLT: begin
result <= (comp == 2'b10) ? 32'h00000001 : 32'h00000000;
end
`ALU_NOR: begin
result <= ~(alu_a | alu_b);
end
`ALU_XOR: begin
result <= alu_a ^ alu_b;
end
`ALU_SLL: begin
result <= alu_b << alu_a;
end
`ALU_SRL: begin
result <= alu_b >> alu_a;
end
`ALU_SRA: begin
case (alu_a[4:0])
5'b00001: begin
result[31] <= alu_b[31];
result[30:0] <= alu_b[31:1];
end
5'b00010: begin
result[31:30] <= {alu_b[31], alu_b[31]};
result[29:0] <= alu_b[31:2];
end
5'b00011: begin
result[31:29] <= {alu_b[31], alu_b[31], alu_b[31]};
result[28:0] <= alu_b[31:3];
end
5'b00100: begin
result[31:28] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[27:0] <= alu_b[31:4];
end
5'b00101: begin
result[31:27] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[26:0] <= alu_b[31:5];
end
5'b00110: begin
result[31:26] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[25:0] <= alu_b[31:6];
end
5'b00111: begin
result[31:25] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[24:0] <= alu_b[31:7];
end
5'b01000: begin
result[31:24] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[23:0] <= alu_b[31:8];
end
5'b01001: begin
result[31:23] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[22:0] <= alu_b[31:9];
end
5'b01010: begin
result[31:22] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[21:0] <= alu_b[31:10];
end
5'b01011: begin
result[31:21] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[20:0] <= alu_b[31:11];
end
5'b01100: begin
result[31:20] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[19:0] <= alu_b[31:12];
end
5'b01101: begin
result[31:19] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[18:0] <= alu_b[31:13];
end
5'b01110: begin
result[31:18] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[17:0] <= alu_b[31:14];
end
5'b01111: begin
result[31:17] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[16:0] <= alu_b[31:15];
end
5'b10000: begin
result[31:16] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[15:0] <= alu_b[31:16];
end
5'b10001: begin
result[31:15] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[14:0] <= alu_b[31:17];
end
5'b10010: begin
result[31:14] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[13:0] <= alu_b[31:18];
end
5'b10011: begin
result[31:13] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[12:0] <= alu_b[31:19];
end
5'b10100: begin
result[31:12] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[11:0] <= alu_b[31:20];
end
5'b10101: begin
result[31:11] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[10:0] <= alu_b[31:21];
end
5'b10110: begin
result[31:10] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[9:0] <= alu_b[31:22];
end
5'b10111: begin
result[31:9] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[8:0] <= alu_b[31:23];
end
5'b11000: begin
result[31:8] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[7:0] <= alu_b[31:24];
end
5'b11001: begin
result[31:7] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[6:0] <= alu_b[31:25];
end
5'b11010: begin
result[31:6] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[5:0] <= alu_b[31:26];
end
5'b11011: begin
result[31:5] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[4:0] <= alu_b[31:27];
end
5'b11100: begin
result[31:4] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[3:0] <= alu_b[31:28];
end
5'b11101: begin
result[31:3] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[2:0] <= alu_b[31:29];
end
5'b11110: begin
result[31:2] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[1:0] <= alu_b[31:30];
end
5'b11111: begin
result[31:1] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[0] <= alu_b[31];
end
default: begin
result <= alu_b;
end
endcase
end
`ALU_SLTU: begin
result <= (alu_a < alu_b) ? 32'h00000001 : 32'h00000000;
end
`ALU_LUI: begin
result <= alu_b << 16;
end
default: begin
result <= 0;
end
endcase
end
always @(alu_a or alu_b) begin
if (alu_a == alu_b) begin
comp <= 2'b00;
end else begin
if (alu_a[31] == 0) begin
if (alu_b[31] == 0) begin
if (alu_a > alu_b) begin
comp <= 2'b01;
end else begin
comp <= 2'b10;
end
end else begin
comp <= 2'b01;
end
end else begin
if (alu_b[31] == 0) begin
comp <= 2'b10;
end else begin
if (alu_a > alu_b) begin
comp <= 2'b10;
end else begin
comp <= 2'b01;
end
end
end
end
end
assign alu_y = result;
assign alu_comp = comp;
endmodule | module alu (alu_a, alu_b, alu_ctrl, alu_y, alu_comp); |
input [31:0] alu_a;
input [31:0] alu_b;
input [3:0] alu_ctrl;
output [31:0] alu_y;
output [1:0] alu_comp;
reg [31:0] result;
reg [1:0] comp;
always @(alu_a or alu_b or alu_ctrl or comp) begin
case (alu_ctrl)
`ALU_ADD: begin
result <= alu_a + alu_b;
end
`ALU_SUB: begin
result <= alu_a - alu_b;
end
`ALU_AND: begin
result <= alu_a & alu_b;
end
`ALU_OR: begin
result <= alu_a | alu_b;
end
`ALU_SLT: begin
result <= (comp == 2'b10) ? 32'h00000001 : 32'h00000000;
end
`ALU_NOR: begin
result <= ~(alu_a | alu_b);
end
`ALU_XOR: begin
result <= alu_a ^ alu_b;
end
`ALU_SLL: begin
result <= alu_b << alu_a;
end
`ALU_SRL: begin
result <= alu_b >> alu_a;
end
`ALU_SRA: begin
case (alu_a[4:0])
5'b00001: begin
result[31] <= alu_b[31];
result[30:0] <= alu_b[31:1];
end
5'b00010: begin
result[31:30] <= {alu_b[31], alu_b[31]};
result[29:0] <= alu_b[31:2];
end
5'b00011: begin
result[31:29] <= {alu_b[31], alu_b[31], alu_b[31]};
result[28:0] <= alu_b[31:3];
end
5'b00100: begin
result[31:28] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[27:0] <= alu_b[31:4];
end
5'b00101: begin
result[31:27] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[26:0] <= alu_b[31:5];
end
5'b00110: begin
result[31:26] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[25:0] <= alu_b[31:6];
end
5'b00111: begin
result[31:25] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[24:0] <= alu_b[31:7];
end
5'b01000: begin
result[31:24] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[23:0] <= alu_b[31:8];
end
5'b01001: begin
result[31:23] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[22:0] <= alu_b[31:9];
end
5'b01010: begin
result[31:22] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[21:0] <= alu_b[31:10];
end
5'b01011: begin
result[31:21] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[20:0] <= alu_b[31:11];
end
5'b01100: begin
result[31:20] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[19:0] <= alu_b[31:12];
end
5'b01101: begin
result[31:19] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[18:0] <= alu_b[31:13];
end
5'b01110: begin
result[31:18] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[17:0] <= alu_b[31:14];
end
5'b01111: begin
result[31:17] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[16:0] <= alu_b[31:15];
end
5'b10000: begin
result[31:16] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[15:0] <= alu_b[31:16];
end
5'b10001: begin
result[31:15] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[14:0] <= alu_b[31:17];
end
5'b10010: begin
result[31:14] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[13:0] <= alu_b[31:18];
end
5'b10011: begin
result[31:13] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[12:0] <= alu_b[31:19];
end
5'b10100: begin
result[31:12] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[11:0] <= alu_b[31:20];
end
5'b10101: begin
result[31:11] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[10:0] <= alu_b[31:21];
end
5'b10110: begin
result[31:10] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[9:0] <= alu_b[31:22];
end
5'b10111: begin
result[31:9] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[8:0] <= alu_b[31:23];
end
5'b11000: begin
result[31:8] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[7:0] <= alu_b[31:24];
end
5'b11001: begin
result[31:7] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[6:0] <= alu_b[31:25];
end
5'b11010: begin
result[31:6] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[5:0] <= alu_b[31:26];
end
5'b11011: begin
result[31:5] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[4:0] <= alu_b[31:27];
end
5'b11100: begin
result[31:4] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31]};
result[3:0] <= alu_b[31:28];
end
5'b11101: begin
result[31:3] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31]};
result[2:0] <= alu_b[31:29];
end
5'b11110: begin
result[31:2] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31]};
result[1:0] <= alu_b[31:30];
end
5'b11111: begin
result[31:1] <= {alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31], alu_b[31],
alu_b[31], alu_b[31], alu_b[31]};
result[0] <= alu_b[31];
end
default: begin
result <= alu_b;
end
endcase
end
`ALU_SLTU: begin
result <= (alu_a < alu_b) ? 32'h00000001 : 32'h00000000;
end
`ALU_LUI: begin
result <= alu_b << 16;
end
default: begin
result <= 0;
end
endcase
end
always @(alu_a or alu_b) begin
if (alu_a == alu_b) begin
comp <= 2'b00;
end else begin
if (alu_a[31] == 0) begin
if (alu_b[31] == 0) begin
if (alu_a > alu_b) begin
comp <= 2'b01;
end else begin
comp <= 2'b10;
end
end else begin
comp <= 2'b01;
end
end else begin
if (alu_b[31] == 0) begin
comp <= 2'b10;
end else begin
if (alu_a > alu_b) begin
comp <= 2'b10;
end else begin
comp <= 2'b01;
end
end
end
end
end
assign alu_y = result;
assign alu_comp = comp;
endmodule | 0 |
3,891 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/alu_ctrler.v | 107,499,099 | alu_ctrler.v | v | 154 | 98 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc0 in position 173: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/alu_ctrler.v:131: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance alu_ctrler\n y = 3\'b000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,679 | module | module alu_ctrler (alu_op, func, alu_ctrl);
input [2:0] alu_op;
input [5:0] func;
output [3:0] alu_ctrl;
reg [3:0] y;
always @(alu_op or func) begin
case (alu_op)
3'b000: begin
y = `ALU_CTRL_ADD;
end
3'b001: begin
y = `ALU_CTRL_LUI;
end
3'b010: begin
if (func == 6'b100000) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b100001) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b100010) begin
y = `ALU_CTRL_SUB;
end else if (func == 6'b100011) begin
y = `ALU_CTRL_SUB;
end else if (func == 6'b100100) begin
y = `ALU_CTRL_AND;
end else if (func == 6'b100101) begin
y = `ALU_CTRL_OR;
end else if (func == 6'b101010) begin
y = `ALU_CTRL_SLT;
end else if (func == 6'b001001) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_NOR;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_XOR;
end else if (func == 6'b000000) begin
y = `ALU_CTRL_SLL;
end else if (func == 6'b000010) begin
y = `ALU_CTRL_SRL;
end else if (func == 6'b000100) begin
y = `ALU_CTRL_SLL;
end else if (func == 6'b000110) begin
y = `ALU_CTRL_SRL;
end else if (func == 6'b000011) begin
y = `ALU_CTRL_SRA;
end else if (func == 6'b000111) begin
y = `ALU_CTRL_SRA;
end else if (func == 6'b101011) begin
y = `ALU_CTRL_SLTU;
end else begin
y = 3'b000;
end
end
3'b011: begin
y = `ALU_CTRL_AND;
end
3'b100: begin
y = `ALU_CTRL_OR;
end
3'b101: begin
y = `ALU_CTRL_XOR;
end
3'b110: begin
y = `ALU_CTRL_SLT;
end
default: begin
y = `ALU_CTRL_SLTU;
end
endcase
end
assign alu_ctrl = y;
endmodule | module alu_ctrler (alu_op, func, alu_ctrl); |
input [2:0] alu_op;
input [5:0] func;
output [3:0] alu_ctrl;
reg [3:0] y;
always @(alu_op or func) begin
case (alu_op)
3'b000: begin
y = `ALU_CTRL_ADD;
end
3'b001: begin
y = `ALU_CTRL_LUI;
end
3'b010: begin
if (func == 6'b100000) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b100001) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b100010) begin
y = `ALU_CTRL_SUB;
end else if (func == 6'b100011) begin
y = `ALU_CTRL_SUB;
end else if (func == 6'b100100) begin
y = `ALU_CTRL_AND;
end else if (func == 6'b100101) begin
y = `ALU_CTRL_OR;
end else if (func == 6'b101010) begin
y = `ALU_CTRL_SLT;
end else if (func == 6'b001001) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_ADD;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_NOR;
end else if (func == 6'b001000) begin
y = `ALU_CTRL_XOR;
end else if (func == 6'b000000) begin
y = `ALU_CTRL_SLL;
end else if (func == 6'b000010) begin
y = `ALU_CTRL_SRL;
end else if (func == 6'b000100) begin
y = `ALU_CTRL_SLL;
end else if (func == 6'b000110) begin
y = `ALU_CTRL_SRL;
end else if (func == 6'b000011) begin
y = `ALU_CTRL_SRA;
end else if (func == 6'b000111) begin
y = `ALU_CTRL_SRA;
end else if (func == 6'b101011) begin
y = `ALU_CTRL_SLTU;
end else begin
y = 3'b000;
end
end
3'b011: begin
y = `ALU_CTRL_AND;
end
3'b100: begin
y = `ALU_CTRL_OR;
end
3'b101: begin
y = `ALU_CTRL_XOR;
end
3'b110: begin
y = `ALU_CTRL_SLT;
end
default: begin
y = `ALU_CTRL_SLTU;
end
endcase
end
assign alu_ctrl = y;
endmodule | 0 |
3,892 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v | 107,499,099 | cpu.v | v | 573 | 109 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 220: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:72: Cannot find include file: rom8x1024_DE2.v\n `include "rom8x1024_DE2.v" // ROM DE2 , quartus, \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v.sv\n rom8x1024_DE2.v\n rom8x1024_DE2.v.v\n rom8x1024_DE2.v.sv\n obj_dir/rom8x1024_DE2.v\n obj_dir/rom8x1024_DE2.v.v\n obj_dir/rom8x1024_DE2.v.sv\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:73: Cannot find include file: ram8x2048_DE2.v\n `include "ram8x2048_DE2.v" // RAM DE2 , quartus, \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:75: Cannot find include file: alu.v\n`include "alu.v" // ALU \n ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:76: Cannot find include file: pc.v\n`include "pc.v" // PC \n ^~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:77: Cannot find include file: registers.v\n`include "registers.v" // \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:78: Cannot find include file: plus4.v\n`include "plus4.v" // PC \n ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:79: Cannot find include file: adder32.v\n`include "adder32.v" // PC \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:80: Cannot find include file: mux32_32_32.v\n`include "mux32_32_32.v" // 32-bit, 32-bit , \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:82: Cannot find include file: mux5_5_5.v\n`include "mux5_5_5.v" // 5-bit, 5-bit , \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:84: Cannot find include file: main_ctrl.v\n`include "main_ctrl.v" // \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:85: Cannot find include file: alu_ctrler.v\n`include "alu_ctrler.v" // ALU \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:86: Cannot find include file: shifter32_32_l2.v\n`include "shifter32_32_l2.v" // 32-bit , 32-bit 2 \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:87: Cannot find include file: signext16_32.v\n`include "signext16_32.v" // 16-bit , 32-bit \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:88: Cannot find include file: is_branch.v\n`include "is_branch.v" // \n ^~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n' | 1,680 | module | module cpu (clk, reset,
clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata, o_reg_widx, o_reg_wen,
o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
i_ram_addr, i_ram_wdata, i_ram_wen
);
input clk;
input reset;
input clk_ctrl0;
input clk_ctrl1;
input clk_ctrl_clk;
input [12:0] i_ram_addr;
input [31:0] i_ram_wdata;
input i_ram_wen;
output o_clock;
output [11:0] o_pc;
output [31:0] o_alu_y;
output [31:0] o_alu_a;
output [31:0] o_alu_b;
output [3:0] o_alu_ctrl;
output [1:0] o_alu_comp;
output [31:0] o_reg_data1;
output [4:0] o_reg_idx1;
output [31:0] o_reg_data2;
output [4:0] o_reg_idx2;
output [31:0] o_reg_wdata;
output [4:0] o_reg_widx;
output o_reg_wen;
output [12:0] o_ram_addr;
output [31:0] o_ram_rdata;
output [31:0] o_ram_wdata;
output o_ram_wen;
wire [23:0] max_bunsyuu_reg_val;
reg clock_reg;
reg [23:0] bunsyuu_reg;
wire clock;
wire clock_rom;
wire clock_ram;
assign clock = ((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b1)) ? clk_ctrl_clk : clock_reg;
assign clock_rom = bunsyuu_reg[3];
assign clock_ram = bunsyuu_reg[4];
assign max_bunsyuu_reg_val = ((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_2Hz
: (((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b1)) ? `max_bunsyuu_reg_val_200Hz
: (((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_1kHz
: `max_bunsyuu_reg_val_2Hz));
always @(posedge clk or negedge reset) begin
if (reset == 1'b0) begin
bunsyuu_reg <= 24'b000000000000000000000000;
clock_reg <= 1'b0;
end else begin
if (bunsyuu_reg >= max_bunsyuu_reg_val) begin
bunsyuu_reg <= 24'b000000000000000000000000;
clock_reg <= ~clock_reg;
end else begin
bunsyuu_reg <= bunsyuu_reg + 1;
end
end
end
wire [11:0] rom_addr;
wire [31:0] rom_data;
wire [12:0] ram_addr;
wire ram_write_enable;
wire [31:0] ram_write_data;
wire [31:0] ram_read_data;
wire [12:0] key_ram_addr;
wire [31:0] key_ram_wdata;
wire key_ram_wen;
wire [31:0] alu_a, alu_b;
wire [3:0] alu_ctrl;
wire [31:0] alu_y;
wire [1:0] alu_comp;
wire [31:0] pc_next;
wire [31:0] pc;
wire [4:0] reg_read_idx1;
wire [4:0] reg_read_idx2;
wire [4:0] reg_write_idx;
wire [31:0] reg_write_data;
wire [31:0] reg_read_data1;
wire [31:0] reg_read_data2;
wire [31:0] inc_a;
wire [31:0] inc_y;
wire [31:0] add_a;
wire [31:0] add_b;
wire [31:0] add_y;
wire [31:0] alu_b_sel1_d0;
wire [31:0] alu_b_sel1_d1;
wire alu_b_sel1_s;
wire [31:0] alu_b_sel1_y;
wire [31:0] alu_b_sel2_d0;
wire [31:0] alu_b_sel2_d1;
wire alu_b_sel2_s;
wire [31:0] alu_b_sel2_y;
wire [31:0] alu_ram_sel_d0;
wire [31:0] alu_ram_sel_d1;
wire alu_ram_sel_s;
wire [31:0] alu_ram_sel_y;
wire [31:0] link_sel_d0;
wire [31:0] link_sel_d1;
wire link_sel_s;
wire [31:0] link_sel_y;
wire [4:0] reg_widx_sel1_d0;
wire [4:0] reg_widx_sel1_d1;
wire reg_widx_sel1_s;
wire [4:0] reg_widx_sel1_y;
wire [4:0] reg_widx_sel2_d0;
wire [4:0] reg_widx_sel2_d1;
wire reg_widx_sel2_s;
wire [4:0] reg_widx_sel2_y;
wire [31:0] pc_sel_d0;
wire [31:0] pc_sel_d1;
wire pc_sel_s;
wire [31:0] pc_sel_y;
wire [31:0] jp_sel_d0;
wire [31:0] jp_sel_d1;
wire jp_sel_s;
wire [31:0] jp_sel_y;
wire [31:0] jpr_sel_d0;
wire [31:0] jpr_sel_d1;
wire jpr_sel_s;
wire [31:0] jpr_sel_y;
wire [31:0] instruction;
wire alu_b_sel1;
wire alu_b_sel2;
wire [2:0] alu_op;
wire [2:0] is_branch_ctrl;
wire reg_write_enable;
wire jp;
wire link;
wire jpr;
wire shiftv;
wire do_sign_ext;
wire [5:0] func;
wire [31:0] sh_a;
wire [31:0] sh_y;
wire [31:0] sh_j_a;
wire [31:0] sh_j_y;
wire [15:0] a16;
wire [31:0] y32;
wire [2:0] is_branch_d0;
wire [1:0] is_branch_d1;
wire is_branch_y;
wire [31:0] alu_a_sel1_d0;
wire [31:0] alu_a_sel1_d1;
wire alu_a_sel1_s;
wire [31:0] alu_a_sel1_y;
rom8x1024_DE2 rom8x1024a(clock_rom, rom_addr, rom_data);
ram8x2048_DE2 ram8x2048a(clock_ram, ram_addr, ram_write_enable,
ram_write_data, ram_read_data,
key_ram_addr, key_ram_wdata, key_ram_wen);
alu alua(alu_a, alu_b, alu_ctrl, alu_y, alu_comp);
pc pca (clock, reset, pc_next, pc);
registers register_file(clock, reset,
reg_read_idx1, reg_read_idx2,
reg_write_idx, reg_write_enable, reg_write_data,
reg_read_data1, reg_read_data2);
plus4 pc_plus4 (inc_a, inc_y);
adder32 pc_add(add_a, add_b, add_y);
mux32_32_32 alu_b_sel_1(alu_b_sel1_d0, alu_b_sel1_d1, alu_b_sel1_s, alu_b_sel1_y);
mux32_32_32 alu_b_sel_2(alu_b_sel2_d0, alu_b_sel2_d1, alu_b_sel2_s, alu_b_sel2_y);
mux32_32_32 alu_ram_sel(alu_ram_sel_d0, alu_ram_sel_d1, alu_ram_sel_s, alu_ram_sel_y);
mux32_32_32 link_sel(link_sel_d0, link_sel_d1, link_sel_s, link_sel_y);
mux32_32_32 alu_a_sel_1(alu_a_sel1_d0, alu_a_sel1_d1, alu_a_sel1_s, alu_a_sel1_y);
mux32_32_32 jpr_sel(jpr_sel_d0, jpr_sel_d1, jpr_sel_s, jpr_sel_y);
mux32_32_32 jp_sel(jp_sel_d0, jp_sel_d1, jp_sel_s, jp_sel_y);
mux32_32_32 pc_sel(pc_sel_d0, pc_sel_d1, pc_sel_s, pc_sel_y);
mux5_5_5 reg_widx_sel1(reg_widx_sel1_d0, reg_widx_sel1_d1,
reg_widx_sel1_s, reg_widx_sel1_y);
mux5_5_5 reg_widx_sel2(reg_widx_sel2_d0, reg_widx_sel2_d1,
reg_widx_sel2_s, reg_widx_sel2_y);
main_ctrl main_ctrla(instruction, ram_write_enable, alu_b_sel1, alu_b_sel2, alu_op,
is_branch_ctrl, reg_write_enable,
alu_ram_sel_s, reg_widx_sel1_s, jp, link, jpr,
shiftv, do_sign_ext);
alu_ctrler alu_ctrlera(alu_op, func, alu_ctrl);
shifter32_32_l2 shifter32_32_l2a(sh_a, sh_y);
shifter32_32_l2 shifter32_32_l2b(sh_j_a, sh_j_y);
signext16_32 signext16_32a(do_sign_ext, a16, y32);
is_branch is_brancha(is_branch_d0, is_branch_d1, is_branch_y);
assign rom_addr = (pc[31:0] > 32'h00400fff) ? 12'hfff : pc[11:0];
assign ram_addr = alu_y[12:0];
assign ram_write_data = reg_read_data2;
assign key_ram_addr = i_ram_addr;
assign key_ram_wdata = i_ram_wdata;
assign key_ram_wen = i_ram_wen;
assign alu_a = alu_a_sel1_y;
assign alu_b = alu_b_sel2_y;
assign pc_next = jpr_sel_y;
assign reg_read_idx1 = instruction[25:21];
assign reg_read_idx2 = instruction[20:16];
assign reg_write_idx = reg_widx_sel2_y;
assign reg_write_data = link_sel_y;
assign inc_a = pc;
assign add_a = inc_y;
assign add_b = sh_y;
assign alu_b_sel1_d0 = reg_read_data2;
assign alu_b_sel1_d1 = y32;
assign alu_b_sel1_s = alu_b_sel1;
assign alu_b_sel2_d0 = alu_b_sel1_y;
assign alu_b_sel2_d1 = 0;
assign alu_b_sel2_s = alu_b_sel2;
assign alu_ram_sel_d0 = alu_y;
assign alu_ram_sel_d1 = ram_read_data;
assign reg_widx_sel1_d0 = instruction[20:16];
assign reg_widx_sel1_d1 = instruction[15:11];
assign reg_widx_sel2_d0 = reg_widx_sel1_y;
assign reg_widx_sel2_d1 = 5'b11111;
assign reg_widx_sel2_s = link;
assign link_sel_d0 = alu_ram_sel_y;
assign link_sel_d1 = inc_y;
assign link_sel_s = link;
assign pc_sel_d0 = inc_y;
assign pc_sel_d1 = add_y;
assign pc_sel_s = is_branch_y;
assign jp_sel_d0 = pc_sel_y;
assign jp_sel_d1 = sh_j_y;
assign jp_sel_s = jp;
assign jpr_sel_d0 = jp_sel_y;
assign jpr_sel_d1 = alu_ram_sel_y;
assign jpr_sel_s = jpr;
assign instruction = rom_data;
assign func = y32[5:0];
assign sh_a = y32;
assign sh_j_a = {6'b000000, instruction[25:0]};
assign a16 = instruction[15:0];
assign is_branch_d0 = is_branch_ctrl;
assign is_branch_d1 = alu_comp;
assign alu_a_sel1_d0 = reg_read_data1;
assign alu_a_sel1_d1 = {27'b000000000000000000000000000, y32[10:6]};
assign alu_a_sel1_s = shiftv;
assign o_pc = pc[11:0];
assign o_clock = clock;
assign o_alu_y = alu_y;
assign o_alu_a = alu_a;
assign o_alu_b = alu_b;
assign o_alu_ctrl = alu_ctrl;
assign o_alu_comp = alu_comp;
assign o_reg_data1 = reg_read_data1;
assign o_reg_idx1 = reg_read_idx1;
assign o_reg_data2 = reg_read_data2;
assign o_reg_idx2 = reg_read_idx2;
assign o_reg_wdata = reg_write_data;
assign o_reg_widx = reg_write_idx;
assign o_reg_wen = reg_write_enable;
assign o_ram_addr = ram_addr;
assign o_ram_rdata = ram_read_data;
assign o_ram_wdata = ram_write_data;
assign o_ram_wen = ram_write_enable;
endmodule | module cpu (clk, reset,
clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata, o_reg_widx, o_reg_wen,
o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
i_ram_addr, i_ram_wdata, i_ram_wen
); |
input clk;
input reset;
input clk_ctrl0;
input clk_ctrl1;
input clk_ctrl_clk;
input [12:0] i_ram_addr;
input [31:0] i_ram_wdata;
input i_ram_wen;
output o_clock;
output [11:0] o_pc;
output [31:0] o_alu_y;
output [31:0] o_alu_a;
output [31:0] o_alu_b;
output [3:0] o_alu_ctrl;
output [1:0] o_alu_comp;
output [31:0] o_reg_data1;
output [4:0] o_reg_idx1;
output [31:0] o_reg_data2;
output [4:0] o_reg_idx2;
output [31:0] o_reg_wdata;
output [4:0] o_reg_widx;
output o_reg_wen;
output [12:0] o_ram_addr;
output [31:0] o_ram_rdata;
output [31:0] o_ram_wdata;
output o_ram_wen;
wire [23:0] max_bunsyuu_reg_val;
reg clock_reg;
reg [23:0] bunsyuu_reg;
wire clock;
wire clock_rom;
wire clock_ram;
assign clock = ((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b1)) ? clk_ctrl_clk : clock_reg;
assign clock_rom = bunsyuu_reg[3];
assign clock_ram = bunsyuu_reg[4];
assign max_bunsyuu_reg_val = ((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_2Hz
: (((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b1)) ? `max_bunsyuu_reg_val_200Hz
: (((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_1kHz
: `max_bunsyuu_reg_val_2Hz));
always @(posedge clk or negedge reset) begin
if (reset == 1'b0) begin
bunsyuu_reg <= 24'b000000000000000000000000;
clock_reg <= 1'b0;
end else begin
if (bunsyuu_reg >= max_bunsyuu_reg_val) begin
bunsyuu_reg <= 24'b000000000000000000000000;
clock_reg <= ~clock_reg;
end else begin
bunsyuu_reg <= bunsyuu_reg + 1;
end
end
end
wire [11:0] rom_addr;
wire [31:0] rom_data;
wire [12:0] ram_addr;
wire ram_write_enable;
wire [31:0] ram_write_data;
wire [31:0] ram_read_data;
wire [12:0] key_ram_addr;
wire [31:0] key_ram_wdata;
wire key_ram_wen;
wire [31:0] alu_a, alu_b;
wire [3:0] alu_ctrl;
wire [31:0] alu_y;
wire [1:0] alu_comp;
wire [31:0] pc_next;
wire [31:0] pc;
wire [4:0] reg_read_idx1;
wire [4:0] reg_read_idx2;
wire [4:0] reg_write_idx;
wire [31:0] reg_write_data;
wire [31:0] reg_read_data1;
wire [31:0] reg_read_data2;
wire [31:0] inc_a;
wire [31:0] inc_y;
wire [31:0] add_a;
wire [31:0] add_b;
wire [31:0] add_y;
wire [31:0] alu_b_sel1_d0;
wire [31:0] alu_b_sel1_d1;
wire alu_b_sel1_s;
wire [31:0] alu_b_sel1_y;
wire [31:0] alu_b_sel2_d0;
wire [31:0] alu_b_sel2_d1;
wire alu_b_sel2_s;
wire [31:0] alu_b_sel2_y;
wire [31:0] alu_ram_sel_d0;
wire [31:0] alu_ram_sel_d1;
wire alu_ram_sel_s;
wire [31:0] alu_ram_sel_y;
wire [31:0] link_sel_d0;
wire [31:0] link_sel_d1;
wire link_sel_s;
wire [31:0] link_sel_y;
wire [4:0] reg_widx_sel1_d0;
wire [4:0] reg_widx_sel1_d1;
wire reg_widx_sel1_s;
wire [4:0] reg_widx_sel1_y;
wire [4:0] reg_widx_sel2_d0;
wire [4:0] reg_widx_sel2_d1;
wire reg_widx_sel2_s;
wire [4:0] reg_widx_sel2_y;
wire [31:0] pc_sel_d0;
wire [31:0] pc_sel_d1;
wire pc_sel_s;
wire [31:0] pc_sel_y;
wire [31:0] jp_sel_d0;
wire [31:0] jp_sel_d1;
wire jp_sel_s;
wire [31:0] jp_sel_y;
wire [31:0] jpr_sel_d0;
wire [31:0] jpr_sel_d1;
wire jpr_sel_s;
wire [31:0] jpr_sel_y;
wire [31:0] instruction;
wire alu_b_sel1;
wire alu_b_sel2;
wire [2:0] alu_op;
wire [2:0] is_branch_ctrl;
wire reg_write_enable;
wire jp;
wire link;
wire jpr;
wire shiftv;
wire do_sign_ext;
wire [5:0] func;
wire [31:0] sh_a;
wire [31:0] sh_y;
wire [31:0] sh_j_a;
wire [31:0] sh_j_y;
wire [15:0] a16;
wire [31:0] y32;
wire [2:0] is_branch_d0;
wire [1:0] is_branch_d1;
wire is_branch_y;
wire [31:0] alu_a_sel1_d0;
wire [31:0] alu_a_sel1_d1;
wire alu_a_sel1_s;
wire [31:0] alu_a_sel1_y;
rom8x1024_DE2 rom8x1024a(clock_rom, rom_addr, rom_data);
ram8x2048_DE2 ram8x2048a(clock_ram, ram_addr, ram_write_enable,
ram_write_data, ram_read_data,
key_ram_addr, key_ram_wdata, key_ram_wen);
alu alua(alu_a, alu_b, alu_ctrl, alu_y, alu_comp);
pc pca (clock, reset, pc_next, pc);
registers register_file(clock, reset,
reg_read_idx1, reg_read_idx2,
reg_write_idx, reg_write_enable, reg_write_data,
reg_read_data1, reg_read_data2);
plus4 pc_plus4 (inc_a, inc_y);
adder32 pc_add(add_a, add_b, add_y);
mux32_32_32 alu_b_sel_1(alu_b_sel1_d0, alu_b_sel1_d1, alu_b_sel1_s, alu_b_sel1_y);
mux32_32_32 alu_b_sel_2(alu_b_sel2_d0, alu_b_sel2_d1, alu_b_sel2_s, alu_b_sel2_y);
mux32_32_32 alu_ram_sel(alu_ram_sel_d0, alu_ram_sel_d1, alu_ram_sel_s, alu_ram_sel_y);
mux32_32_32 link_sel(link_sel_d0, link_sel_d1, link_sel_s, link_sel_y);
mux32_32_32 alu_a_sel_1(alu_a_sel1_d0, alu_a_sel1_d1, alu_a_sel1_s, alu_a_sel1_y);
mux32_32_32 jpr_sel(jpr_sel_d0, jpr_sel_d1, jpr_sel_s, jpr_sel_y);
mux32_32_32 jp_sel(jp_sel_d0, jp_sel_d1, jp_sel_s, jp_sel_y);
mux32_32_32 pc_sel(pc_sel_d0, pc_sel_d1, pc_sel_s, pc_sel_y);
mux5_5_5 reg_widx_sel1(reg_widx_sel1_d0, reg_widx_sel1_d1,
reg_widx_sel1_s, reg_widx_sel1_y);
mux5_5_5 reg_widx_sel2(reg_widx_sel2_d0, reg_widx_sel2_d1,
reg_widx_sel2_s, reg_widx_sel2_y);
main_ctrl main_ctrla(instruction, ram_write_enable, alu_b_sel1, alu_b_sel2, alu_op,
is_branch_ctrl, reg_write_enable,
alu_ram_sel_s, reg_widx_sel1_s, jp, link, jpr,
shiftv, do_sign_ext);
alu_ctrler alu_ctrlera(alu_op, func, alu_ctrl);
shifter32_32_l2 shifter32_32_l2a(sh_a, sh_y);
shifter32_32_l2 shifter32_32_l2b(sh_j_a, sh_j_y);
signext16_32 signext16_32a(do_sign_ext, a16, y32);
is_branch is_brancha(is_branch_d0, is_branch_d1, is_branch_y);
assign rom_addr = (pc[31:0] > 32'h00400fff) ? 12'hfff : pc[11:0];
assign ram_addr = alu_y[12:0];
assign ram_write_data = reg_read_data2;
assign key_ram_addr = i_ram_addr;
assign key_ram_wdata = i_ram_wdata;
assign key_ram_wen = i_ram_wen;
assign alu_a = alu_a_sel1_y;
assign alu_b = alu_b_sel2_y;
assign pc_next = jpr_sel_y;
assign reg_read_idx1 = instruction[25:21];
assign reg_read_idx2 = instruction[20:16];
assign reg_write_idx = reg_widx_sel2_y;
assign reg_write_data = link_sel_y;
assign inc_a = pc;
assign add_a = inc_y;
assign add_b = sh_y;
assign alu_b_sel1_d0 = reg_read_data2;
assign alu_b_sel1_d1 = y32;
assign alu_b_sel1_s = alu_b_sel1;
assign alu_b_sel2_d0 = alu_b_sel1_y;
assign alu_b_sel2_d1 = 0;
assign alu_b_sel2_s = alu_b_sel2;
assign alu_ram_sel_d0 = alu_y;
assign alu_ram_sel_d1 = ram_read_data;
assign reg_widx_sel1_d0 = instruction[20:16];
assign reg_widx_sel1_d1 = instruction[15:11];
assign reg_widx_sel2_d0 = reg_widx_sel1_y;
assign reg_widx_sel2_d1 = 5'b11111;
assign reg_widx_sel2_s = link;
assign link_sel_d0 = alu_ram_sel_y;
assign link_sel_d1 = inc_y;
assign link_sel_s = link;
assign pc_sel_d0 = inc_y;
assign pc_sel_d1 = add_y;
assign pc_sel_s = is_branch_y;
assign jp_sel_d0 = pc_sel_y;
assign jp_sel_d1 = sh_j_y;
assign jp_sel_s = jp;
assign jpr_sel_d0 = jp_sel_y;
assign jpr_sel_d1 = alu_ram_sel_y;
assign jpr_sel_s = jpr;
assign instruction = rom_data;
assign func = y32[5:0];
assign sh_a = y32;
assign sh_j_a = {6'b000000, instruction[25:0]};
assign a16 = instruction[15:0];
assign is_branch_d0 = is_branch_ctrl;
assign is_branch_d1 = alu_comp;
assign alu_a_sel1_d0 = reg_read_data1;
assign alu_a_sel1_d1 = {27'b000000000000000000000000000, y32[10:6]};
assign alu_a_sel1_s = shiftv;
assign o_pc = pc[11:0];
assign o_clock = clock;
assign o_alu_y = alu_y;
assign o_alu_a = alu_a;
assign o_alu_b = alu_b;
assign o_alu_ctrl = alu_ctrl;
assign o_alu_comp = alu_comp;
assign o_reg_data1 = reg_read_data1;
assign o_reg_idx1 = reg_read_idx1;
assign o_reg_data2 = reg_read_data2;
assign o_reg_idx2 = reg_read_idx2;
assign o_reg_wdata = reg_write_data;
assign o_reg_widx = reg_write_idx;
assign o_reg_wen = reg_write_enable;
assign o_ram_addr = ram_addr;
assign o_ram_rdata = ram_read_data;
assign o_ram_wdata = ram_write_data;
assign o_ram_wen = ram_write_enable;
endmodule | 0 |
3,893 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/is_branch.v | 107,499,099 | is_branch.v | v | 40 | 60 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 181: invalid continuation byte | data/verilator_xmls/438660ba-5d95-4690-8c17-c6046265c987.xml | null | 1,681 | module | module is_branch (d0, d1, y);
input [2:0] d0;
input [1:0] d1;
output y;
reg y_temp;
always @(d0 or d1) begin
case (d0)
`EQ: y_temp = (d1 == 2'b00) ? 1'b1 : 1'b0;
`NEQ: y_temp = (d1 == 2'b00) ? 1'b0 : 1'b1;
`GE: y_temp = (d1[1] == 1'b0) ? 1'b1 : 1'b0;
`LE: y_temp = (d1[0] == 1'b0) ? 1'b1 : 1'b0;
`GT: y_temp = (d1 == 2'b01) ? 1'b1 : 1'b0;
`LT: y_temp = (d1 == 2'b10) ? 1'b1 : 1'b0;
`X: y_temp = 1'b0;
default: y_temp = 1'b0;
endcase
end
assign y = y_temp;
endmodule | module is_branch (d0, d1, y); |
input [2:0] d0;
input [1:0] d1;
output y;
reg y_temp;
always @(d0 or d1) begin
case (d0)
`EQ: y_temp = (d1 == 2'b00) ? 1'b1 : 1'b0;
`NEQ: y_temp = (d1 == 2'b00) ? 1'b0 : 1'b1;
`GE: y_temp = (d1[1] == 1'b0) ? 1'b1 : 1'b0;
`LE: y_temp = (d1[0] == 1'b0) ? 1'b1 : 1'b0;
`GT: y_temp = (d1 == 2'b01) ? 1'b1 : 1'b0;
`LT: y_temp = (d1 == 2'b10) ? 1'b1 : 1'b0;
`X: y_temp = 1'b0;
default: y_temp = 1'b0;
endcase
end
assign y = y_temp;
endmodule | 0 |
3,894 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/main_ctrl.v | 107,499,099 | main_ctrl.v | v | 796 | 104 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc4 in position 679: invalid continuation byte | data/verilator_xmls/6ad8b8b9-65ca-41c0-9bfd-a09cdbbba223.xml | null | 1,682 | module | module main_ctrl (instruction,
ram_write_enable,
alu_b_sel1_s,
alu_b_sel2_s,
alu_op,
is_branch_ctrl,
reg_write_enable,
alu_ram_sel_s,
reg_widx_sel1_s,
jp,
link,
jpr,
shiftv,
do_sign_ext
);
input [31:0] instruction;
output ram_write_enable;
output alu_b_sel1_s;
output alu_b_sel2_s;
output [2:0] alu_op;
output [2:0] is_branch_ctrl;
output reg_write_enable;
output alu_ram_sel_s;
output reg_widx_sel1_s;
output jp;
output link;
output jpr;
output shiftv;
output do_sign_ext;
wire [5:0] op_code;
wire [4:0] Rrs;
wire [4:0] Rrt;
wire [4:0] Rrd;
wire [4:0] Rshamt;
wire [5:0] Rfunc;
assign op_code = instruction[31:26];
assign Rrs = instruction[25:21];
assign Rrt = instruction[20:16];
assign Rrd = instruction[15:11];
assign Rshamt = instruction[10:6];
assign Rfunc = instruction[5:0];
wire [4:0] Irs;
wire [4:0] Irt;
wire [15:0] Iaddr;
assign Irs = instruction[25:21];
assign Irt = instruction[20:16];
assign Iaddr = instruction[15:0];
wire [25:0] Jaddr;
assign Jaddr = instruction[25:0];
reg [2:0] is_branch_ctrl_tmp;
reg alu_b_sel1_s_tmp;
reg [2:0] alu_op_tmp;
reg reg_write_enable_tmp;
reg alu_ram_sel_s_tmp;
reg reg_widx_sel1_s_tmp;
reg link_tmp;
assign ram_write_enable = (op_code == `SW) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: is_branch_ctrl_tmp = 3'b110;
`LW: is_branch_ctrl_tmp = 3'b110;
`SW: is_branch_ctrl_tmp = 3'b110;
`ADDI: is_branch_ctrl_tmp = 3'b110;
`ADDIU: is_branch_ctrl_tmp = 3'b110;
`ANDI: is_branch_ctrl_tmp = 3'b110;
`ORI: is_branch_ctrl_tmp = 3'b110;
`BEQ: is_branch_ctrl_tmp = 3'b000;
`BNE: is_branch_ctrl_tmp = 3'b001;
`BGEZ: is_branch_ctrl_tmp = 3'b010;
`BLEZ: is_branch_ctrl_tmp = 3'b011;
`BGTZ: is_branch_ctrl_tmp = 3'b100;
`BLTZ: is_branch_ctrl_tmp = 3'b101;
`BGEZAL: is_branch_ctrl_tmp = 3'b010;
`BLTZAL: is_branch_ctrl_tmp = 3'b101;
`XORI: is_branch_ctrl_tmp = 3'b110;
`SLTI: is_branch_ctrl_tmp = 3'b110;
`SLTIU: is_branch_ctrl_tmp = 3'b110;
`LUI: is_branch_ctrl_tmp = 3'b110;
default: is_branch_ctrl_tmp = 3'b110;
endcase
end
assign is_branch_ctrl = is_branch_ctrl_tmp;
assign jp = ((op_code == `J) || (op_code == `JAL)) ? 1'b1 : 1'b0;
assign jpr = (op_code == `R &&
(Rfunc == 6'b001001
|| Rfunc == 6'b001000)) ? 1'b1 : 1'b0;
assign shiftv = (op_code == `R &&
(Rfunc == 6'b000000 || Rfunc == 6'b000010
|| Rfunc == 6'b000011)) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: alu_b_sel1_s_tmp = 1'b0;
`LW: alu_b_sel1_s_tmp = 1'b1;
`SW: alu_b_sel1_s_tmp = 1'b1;
`ADDI: alu_b_sel1_s_tmp = 1'b1;
`ADDIU: alu_b_sel1_s_tmp = 1'b1;
`ANDI: alu_b_sel1_s_tmp = 1'b1;
`ORI: alu_b_sel1_s_tmp = 1'b1;
`BEQ: alu_b_sel1_s_tmp = 1'b0;
`BNE: alu_b_sel1_s_tmp = 1'b0;
`XORI: alu_b_sel1_s_tmp = 1'b1;
`SLTI: alu_b_sel1_s_tmp = 1'b1;
`SLTIU: alu_b_sel1_s_tmp = 1'b1;
`LUI: alu_b_sel1_s_tmp = 1'b1;
default: alu_b_sel1_s_tmp = 1'b0;
endcase
end
assign alu_b_sel1_s = alu_b_sel1_s_tmp;
assign alu_b_sel2_s = (op_code == 6'b000001) ? 1'b1 : 1'b0;
assign do_sign_ext = ((op_code == `ADDI)
|| (op_code == `ADDIU)
|| (op_code == `SW)
|| (op_code == `LW)
|| (op_code == `SLTI)
|| (op_code == `BEQ)
|| (op_code == `BNE)
|| (op_code == `BGEZ) || (op_code == `BLEZ)
|| (op_code == `BGTZ) || (op_code == `BLTZ)
|| (op_code == `BGEZAL) || (op_code == `BLTZAL)) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: alu_op_tmp = 3'b010;
`LW: alu_op_tmp = 3'b000;
`SW: alu_op_tmp = 3'b000;
`ADDI: alu_op_tmp = 3'b000;
`ADDIU: alu_op_tmp = 3'b000;
`ANDI: alu_op_tmp = 3'b011;
`ORI: alu_op_tmp = 3'b100;
`XORI: alu_op_tmp = 3'b101;
`SLTI: alu_op_tmp = 3'b110;
`SLTIU: alu_op_tmp = 3'b111;
`LUI: alu_op_tmp = 3'b001;
default: alu_op_tmp = 3'b000;
endcase
end
assign alu_op = alu_op_tmp;
always @(op_code) begin
case (op_code)
`R: begin
if (Rfunc == 6'b001000) begin
reg_write_enable_tmp = 1'b0;
end else begin
reg_write_enable_tmp = 1'b1;
end
end
`LW: reg_write_enable_tmp = 1'b1;
`SW: reg_write_enable_tmp = 1'b0;
`ADDI: reg_write_enable_tmp = 1'b1;
`ADDIU: reg_write_enable_tmp = 1'b1;
`ANDI: reg_write_enable_tmp = 1'b1;
`ORI: reg_write_enable_tmp = 1'b1;
`BEQ: reg_write_enable_tmp = 1'b0;
`BNE: reg_write_enable_tmp = 1'b0;
`J: reg_write_enable_tmp = 1'b0;
`JAL: reg_write_enable_tmp = 1'b1;
`XORI: reg_write_enable_tmp = 1'b1;
`SLTI: reg_write_enable_tmp = 1'b1;
`SLTIU: reg_write_enable_tmp = 1'b1;
`LUI: reg_write_enable_tmp = 1'b1;
default: reg_write_enable_tmp = 1'b0;
endcase
end
assign reg_write_enable = reg_write_enable_tmp;
always @(op_code) begin
case (op_code)
`R: alu_ram_sel_s_tmp = 1'b0;
`LW: alu_ram_sel_s_tmp = 1'b1;
`ADDI: alu_ram_sel_s_tmp = 1'b0;
`ADDIU: alu_ram_sel_s_tmp = 1'b0;
`ANDI: alu_ram_sel_s_tmp = 1'b0;
`ORI: alu_ram_sel_s_tmp = 1'b0;
`BEQ: alu_ram_sel_s_tmp = 1'b0;
`XORI: alu_ram_sel_s_tmp = 1'b0;
`SLTI: alu_ram_sel_s_tmp = 1'b0;
`SLTIU: alu_ram_sel_s_tmp = 1'b0;
`LUI: alu_ram_sel_s_tmp = 1'b0;
default: alu_ram_sel_s_tmp = 1'b0;
endcase
end
assign alu_ram_sel_s = alu_ram_sel_s_tmp;
always @(op_code) begin
case (op_code)
`R: reg_widx_sel1_s_tmp = 1'b1;
`LW: reg_widx_sel1_s_tmp = 1'b0;
`ADDI: reg_widx_sel1_s_tmp = 1'b0;
`ADDIU: reg_widx_sel1_s_tmp = 1'b0;
`ANDI: reg_widx_sel1_s_tmp = 1'b0;
`ORI: reg_widx_sel1_s_tmp = 1'b0;
`BEQ: reg_widx_sel1_s_tmp = 1'b0;
`XORI: reg_widx_sel1_s_tmp = 1'b0;
`SLTI: reg_widx_sel1_s_tmp = 1'b0;
`SLTIU: reg_widx_sel1_s_tmp = 1'b0;
`LUI: reg_widx_sel1_s_tmp = 1'b0;
default: reg_widx_sel1_s_tmp = 1'b0;
endcase
end
assign reg_widx_sel1_s = reg_widx_sel1_s_tmp;
always @(op_code) begin
case (op_code)
`R: begin
if (Rfunc == 6'b001001) begin
link_tmp = 1'b1;
end else begin
link_tmp = 1'b0;
end
end
`LW: link_tmp = 1'b0;
`ADDI: link_tmp = 1'b0;
`ADDIU: link_tmp = 1'b0;
`ANDI: link_tmp = 1'b0;
`ORI: link_tmp = 1'b0;
`BEQ: link_tmp = 1'b0;
`BGEZ: link_tmp = 1'b0;
`BLEZ: link_tmp = 1'b0;
`BGTZ: link_tmp = 1'b0;
`BLTZ: link_tmp = 1'b0;
`BGEZAL: link_tmp = 1'b1;
`BLTZAL: link_tmp = 1'b1;
`JAL: link_tmp = 1'b1;
`XORI: link_tmp = 1'b0;
`SLTI: link_tmp = 1'b0;
`SLTIU: link_tmp = 1'b0;
`LUI: link_tmp = 1'b0;
default: link_tmp = 1'b0;
endcase
end
assign link = link_tmp;
endmodule | module main_ctrl (instruction,
ram_write_enable,
alu_b_sel1_s,
alu_b_sel2_s,
alu_op,
is_branch_ctrl,
reg_write_enable,
alu_ram_sel_s,
reg_widx_sel1_s,
jp,
link,
jpr,
shiftv,
do_sign_ext
); |
input [31:0] instruction;
output ram_write_enable;
output alu_b_sel1_s;
output alu_b_sel2_s;
output [2:0] alu_op;
output [2:0] is_branch_ctrl;
output reg_write_enable;
output alu_ram_sel_s;
output reg_widx_sel1_s;
output jp;
output link;
output jpr;
output shiftv;
output do_sign_ext;
wire [5:0] op_code;
wire [4:0] Rrs;
wire [4:0] Rrt;
wire [4:0] Rrd;
wire [4:0] Rshamt;
wire [5:0] Rfunc;
assign op_code = instruction[31:26];
assign Rrs = instruction[25:21];
assign Rrt = instruction[20:16];
assign Rrd = instruction[15:11];
assign Rshamt = instruction[10:6];
assign Rfunc = instruction[5:0];
wire [4:0] Irs;
wire [4:0] Irt;
wire [15:0] Iaddr;
assign Irs = instruction[25:21];
assign Irt = instruction[20:16];
assign Iaddr = instruction[15:0];
wire [25:0] Jaddr;
assign Jaddr = instruction[25:0];
reg [2:0] is_branch_ctrl_tmp;
reg alu_b_sel1_s_tmp;
reg [2:0] alu_op_tmp;
reg reg_write_enable_tmp;
reg alu_ram_sel_s_tmp;
reg reg_widx_sel1_s_tmp;
reg link_tmp;
assign ram_write_enable = (op_code == `SW) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: is_branch_ctrl_tmp = 3'b110;
`LW: is_branch_ctrl_tmp = 3'b110;
`SW: is_branch_ctrl_tmp = 3'b110;
`ADDI: is_branch_ctrl_tmp = 3'b110;
`ADDIU: is_branch_ctrl_tmp = 3'b110;
`ANDI: is_branch_ctrl_tmp = 3'b110;
`ORI: is_branch_ctrl_tmp = 3'b110;
`BEQ: is_branch_ctrl_tmp = 3'b000;
`BNE: is_branch_ctrl_tmp = 3'b001;
`BGEZ: is_branch_ctrl_tmp = 3'b010;
`BLEZ: is_branch_ctrl_tmp = 3'b011;
`BGTZ: is_branch_ctrl_tmp = 3'b100;
`BLTZ: is_branch_ctrl_tmp = 3'b101;
`BGEZAL: is_branch_ctrl_tmp = 3'b010;
`BLTZAL: is_branch_ctrl_tmp = 3'b101;
`XORI: is_branch_ctrl_tmp = 3'b110;
`SLTI: is_branch_ctrl_tmp = 3'b110;
`SLTIU: is_branch_ctrl_tmp = 3'b110;
`LUI: is_branch_ctrl_tmp = 3'b110;
default: is_branch_ctrl_tmp = 3'b110;
endcase
end
assign is_branch_ctrl = is_branch_ctrl_tmp;
assign jp = ((op_code == `J) || (op_code == `JAL)) ? 1'b1 : 1'b0;
assign jpr = (op_code == `R &&
(Rfunc == 6'b001001
|| Rfunc == 6'b001000)) ? 1'b1 : 1'b0;
assign shiftv = (op_code == `R &&
(Rfunc == 6'b000000 || Rfunc == 6'b000010
|| Rfunc == 6'b000011)) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: alu_b_sel1_s_tmp = 1'b0;
`LW: alu_b_sel1_s_tmp = 1'b1;
`SW: alu_b_sel1_s_tmp = 1'b1;
`ADDI: alu_b_sel1_s_tmp = 1'b1;
`ADDIU: alu_b_sel1_s_tmp = 1'b1;
`ANDI: alu_b_sel1_s_tmp = 1'b1;
`ORI: alu_b_sel1_s_tmp = 1'b1;
`BEQ: alu_b_sel1_s_tmp = 1'b0;
`BNE: alu_b_sel1_s_tmp = 1'b0;
`XORI: alu_b_sel1_s_tmp = 1'b1;
`SLTI: alu_b_sel1_s_tmp = 1'b1;
`SLTIU: alu_b_sel1_s_tmp = 1'b1;
`LUI: alu_b_sel1_s_tmp = 1'b1;
default: alu_b_sel1_s_tmp = 1'b0;
endcase
end
assign alu_b_sel1_s = alu_b_sel1_s_tmp;
assign alu_b_sel2_s = (op_code == 6'b000001) ? 1'b1 : 1'b0;
assign do_sign_ext = ((op_code == `ADDI)
|| (op_code == `ADDIU)
|| (op_code == `SW)
|| (op_code == `LW)
|| (op_code == `SLTI)
|| (op_code == `BEQ)
|| (op_code == `BNE)
|| (op_code == `BGEZ) || (op_code == `BLEZ)
|| (op_code == `BGTZ) || (op_code == `BLTZ)
|| (op_code == `BGEZAL) || (op_code == `BLTZAL)) ? 1'b1 : 1'b0;
always @(op_code) begin
case (op_code)
`R: alu_op_tmp = 3'b010;
`LW: alu_op_tmp = 3'b000;
`SW: alu_op_tmp = 3'b000;
`ADDI: alu_op_tmp = 3'b000;
`ADDIU: alu_op_tmp = 3'b000;
`ANDI: alu_op_tmp = 3'b011;
`ORI: alu_op_tmp = 3'b100;
`XORI: alu_op_tmp = 3'b101;
`SLTI: alu_op_tmp = 3'b110;
`SLTIU: alu_op_tmp = 3'b111;
`LUI: alu_op_tmp = 3'b001;
default: alu_op_tmp = 3'b000;
endcase
end
assign alu_op = alu_op_tmp;
always @(op_code) begin
case (op_code)
`R: begin
if (Rfunc == 6'b001000) begin
reg_write_enable_tmp = 1'b0;
end else begin
reg_write_enable_tmp = 1'b1;
end
end
`LW: reg_write_enable_tmp = 1'b1;
`SW: reg_write_enable_tmp = 1'b0;
`ADDI: reg_write_enable_tmp = 1'b1;
`ADDIU: reg_write_enable_tmp = 1'b1;
`ANDI: reg_write_enable_tmp = 1'b1;
`ORI: reg_write_enable_tmp = 1'b1;
`BEQ: reg_write_enable_tmp = 1'b0;
`BNE: reg_write_enable_tmp = 1'b0;
`J: reg_write_enable_tmp = 1'b0;
`JAL: reg_write_enable_tmp = 1'b1;
`XORI: reg_write_enable_tmp = 1'b1;
`SLTI: reg_write_enable_tmp = 1'b1;
`SLTIU: reg_write_enable_tmp = 1'b1;
`LUI: reg_write_enable_tmp = 1'b1;
default: reg_write_enable_tmp = 1'b0;
endcase
end
assign reg_write_enable = reg_write_enable_tmp;
always @(op_code) begin
case (op_code)
`R: alu_ram_sel_s_tmp = 1'b0;
`LW: alu_ram_sel_s_tmp = 1'b1;
`ADDI: alu_ram_sel_s_tmp = 1'b0;
`ADDIU: alu_ram_sel_s_tmp = 1'b0;
`ANDI: alu_ram_sel_s_tmp = 1'b0;
`ORI: alu_ram_sel_s_tmp = 1'b0;
`BEQ: alu_ram_sel_s_tmp = 1'b0;
`XORI: alu_ram_sel_s_tmp = 1'b0;
`SLTI: alu_ram_sel_s_tmp = 1'b0;
`SLTIU: alu_ram_sel_s_tmp = 1'b0;
`LUI: alu_ram_sel_s_tmp = 1'b0;
default: alu_ram_sel_s_tmp = 1'b0;
endcase
end
assign alu_ram_sel_s = alu_ram_sel_s_tmp;
always @(op_code) begin
case (op_code)
`R: reg_widx_sel1_s_tmp = 1'b1;
`LW: reg_widx_sel1_s_tmp = 1'b0;
`ADDI: reg_widx_sel1_s_tmp = 1'b0;
`ADDIU: reg_widx_sel1_s_tmp = 1'b0;
`ANDI: reg_widx_sel1_s_tmp = 1'b0;
`ORI: reg_widx_sel1_s_tmp = 1'b0;
`BEQ: reg_widx_sel1_s_tmp = 1'b0;
`XORI: reg_widx_sel1_s_tmp = 1'b0;
`SLTI: reg_widx_sel1_s_tmp = 1'b0;
`SLTIU: reg_widx_sel1_s_tmp = 1'b0;
`LUI: reg_widx_sel1_s_tmp = 1'b0;
default: reg_widx_sel1_s_tmp = 1'b0;
endcase
end
assign reg_widx_sel1_s = reg_widx_sel1_s_tmp;
always @(op_code) begin
case (op_code)
`R: begin
if (Rfunc == 6'b001001) begin
link_tmp = 1'b1;
end else begin
link_tmp = 1'b0;
end
end
`LW: link_tmp = 1'b0;
`ADDI: link_tmp = 1'b0;
`ADDIU: link_tmp = 1'b0;
`ANDI: link_tmp = 1'b0;
`ORI: link_tmp = 1'b0;
`BEQ: link_tmp = 1'b0;
`BGEZ: link_tmp = 1'b0;
`BLEZ: link_tmp = 1'b0;
`BGTZ: link_tmp = 1'b0;
`BLTZ: link_tmp = 1'b0;
`BGEZAL: link_tmp = 1'b1;
`BLTZAL: link_tmp = 1'b1;
`JAL: link_tmp = 1'b1;
`XORI: link_tmp = 1'b0;
`SLTI: link_tmp = 1'b0;
`SLTIU: link_tmp = 1'b0;
`LUI: link_tmp = 1'b0;
default: link_tmp = 1'b0;
endcase
end
assign link = link_tmp;
endmodule | 0 |
3,895 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/mux32_32_32.v | 107,499,099 | mux32_32_32.v | v | 21 | 50 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 204: invalid continuation byte | data/verilator_xmls/0988f8e0-052d-46e0-96a1-c0f2e974bfee.xml | null | 1,683 | module | module mux32_32_32 (d0, d1, s, y);
input [31:0] d0;
input [31:0] d1;
input s;
output [31:0] y;
assign y = (s == 1'b0) ? d0 : d1;
endmodule | module mux32_32_32 (d0, d1, s, y); |
input [31:0] d0;
input [31:0] d1;
input s;
output [31:0] y;
assign y = (s == 1'b0) ? d0 : d1;
endmodule | 0 |
3,896 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/mux5_5_5.v | 107,499,099 | mux5_5_5.v | v | 21 | 47 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 197: invalid continuation byte | data/verilator_xmls/d915148c-722c-44f3-986e-4a67a4483bf4.xml | null | 1,684 | module | module mux5_5_5 (d0, d1, s, y);
input [4:0] d0;
input [4:0] d1;
input s;
output [4:0] y;
assign y = (s == 1'b0) ? d0 : d1;
endmodule | module mux5_5_5 (d0, d1, s, y); |
input [4:0] d0;
input [4:0] d1;
input s;
output [4:0] y;
assign y = (s == 1'b0) ? d0 : d1;
endmodule | 0 |
3,897 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/pc.v | 107,499,099 | pc.v | v | 37 | 63 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 40: invalid start byte | data/verilator_xmls/1ba59cc4-a3cd-4156-b12a-8388ae61090d.xml | null | 1,685 | module | module pc (clock, reset, pc_next, pc);
input clock, reset;
input [31:0] pc_next;
output [31:0] pc;
reg [31:0] pc_reg;
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
pc_reg <= 32'h00400000;
end else begin
pc_reg <= pc_next;
end
end
assign pc = pc_reg;
endmodule | module pc (clock, reset, pc_next, pc); |
input clock, reset;
input [31:0] pc_next;
output [31:0] pc;
reg [31:0] pc_reg;
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
pc_reg <= 32'h00400000;
end else begin
pc_reg <= pc_next;
end
end
assign pc = pc_reg;
endmodule | 0 |
3,898 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/plus4.v | 107,499,099 | plus4.v | v | 15 | 48 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 159: invalid continuation byte | data/verilator_xmls/58b101cc-da4f-44c2-8411-d8697f49e328.xml | null | 1,686 | module | module plus4 (inc_a, inc_y);
input [31:0] inc_a;
output [31:0] inc_y;
assign inc_y = inc_a + 4;
endmodule | module plus4 (inc_a, inc_y); |
input [31:0] inc_a;
output [31:0] inc_y;
assign inc_y = inc_a + 4;
endmodule | 0 |
3,899 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_DE2.v | 107,499,099 | ram8x2048_DE2.v | v | 87 | 96 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa4 in position 398: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_DE2.v:51: Cannot find file containing module: 'altsyncram'\n altsyncram altsyncram_component (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/altsyncram\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/altsyncram.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/altsyncram.sv\n altsyncram\n altsyncram.v\n altsyncram.sv\n obj_dir/altsyncram\n obj_dir/altsyncram.v\n obj_dir/altsyncram.sv\n%Error: Exiting due to 1 error(s)\n" | 1,687 | module | module ram8x2048_DE2 (clock, ram_addr, ram_write_enable,
ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata, key_ram_wen);
input clock;
input [12:0] ram_addr;
input ram_write_enable;
input [31:0] ram_write_data;
input [12:0] key_ram_addr;
input [31:0] key_ram_wdata;
input key_ram_wen;
output [31:0] ram_read_data;
wire inclock;
wire outclock;
wire [10:0] word_addr;
wire [31:0] ram_read_data_tmp;
assign inclock = clock;
assign outclock = ~clock;
assign word_addr = ram_addr[12:2];
assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
&& (key_ram_wen == `SCAN_ASCII_WEN)
&& (ram_addr == `SCAN_ASCII_ADDR)
&& (ram_write_enable == 1'b0)) ? key_ram_wdata : ram_read_data_tmp;
altsyncram altsyncram_component (
.wren_a (ram_write_enable),
.clock0 (inclock),
.clock1 (outclock),
.address_a (word_addr),
.data_a (ram_write_data),
.q_a (ram_read_data_tmp),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b (1'b1),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.init_file = "ram8x2048_DE2.mif";
endmodule | module ram8x2048_DE2 (clock, ram_addr, ram_write_enable,
ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata, key_ram_wen); |
input clock;
input [12:0] ram_addr;
input ram_write_enable;
input [31:0] ram_write_data;
input [12:0] key_ram_addr;
input [31:0] key_ram_wdata;
input key_ram_wen;
output [31:0] ram_read_data;
wire inclock;
wire outclock;
wire [10:0] word_addr;
wire [31:0] ram_read_data_tmp;
assign inclock = clock;
assign outclock = ~clock;
assign word_addr = ram_addr[12:2];
assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
&& (key_ram_wen == `SCAN_ASCII_WEN)
&& (ram_addr == `SCAN_ASCII_ADDR)
&& (ram_write_enable == 1'b0)) ? key_ram_wdata : ram_read_data_tmp;
altsyncram altsyncram_component (
.wren_a (ram_write_enable),
.clock0 (inclock),
.clock1 (outclock),
.address_a (word_addr),
.data_a (ram_write_data),
.q_a (ram_read_data_tmp),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b (1'b1),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.init_file = "ram8x2048_DE2.mif";
endmodule | 0 |
3,900 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v | 107,499,099 | ram8x2048_sim.v | v | 67 | 88 | [] | [] | [] | null | line:68: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:43: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n : ... In instance ram8x2048_sim\n assign word_addr = ram_addr[12:2];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:48: Bit extraction of array[2048:0] requires 12 bit index, not 6 bits.\n : ... In instance ram8x2048_sim\n mem[word_addr] <= ram_write_data;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:55: Bit extraction of array[2048:0] requires 12 bit index, not 6 bits.\n : ... In instance ram8x2048_sim\n read_data = mem[word_addr];\n ^\n%Error: Exiting due to 3 warning(s)\n' | 1,688 | module | module ram8x2048_sim (clk, ram_addr, ram_write_enable,
ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata , key_ram_wen);
input clk;
input [12:0] ram_addr;
input ram_write_enable;
input [31:0] ram_write_data;
input [12:0] key_ram_addr;
input [31:0] key_ram_wdata;
input key_ram_wen;
output [31:0] ram_read_data;
reg [31:0] mem[0:2048];
reg [31:0] read_data;
wire [5:0] word_addr;
assign word_addr = ram_addr[12:2];
always @(posedge clk) begin
if (ram_write_enable == 1'b1) begin
mem[word_addr] <= ram_write_data;
end
end
always @(word_addr or ram_write_enable or ram_write_data) begin
if (ram_write_enable == 1'b0) begin
read_data = mem[word_addr];
end else begin
read_data = ram_write_data;
end
end
assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
&& (key_ram_wen == `SCAN_ASCII_WEN)
&& (ram_addr == `SCAN_ASCII_ADDR)
&& (ram_write_enable == 1'b0)) ? key_ram_wdata : read_data;
endmodule | module ram8x2048_sim (clk, ram_addr, ram_write_enable,
ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata , key_ram_wen); |
input clk;
input [12:0] ram_addr;
input ram_write_enable;
input [31:0] ram_write_data;
input [12:0] key_ram_addr;
input [31:0] key_ram_wdata;
input key_ram_wen;
output [31:0] ram_read_data;
reg [31:0] mem[0:2048];
reg [31:0] read_data;
wire [5:0] word_addr;
assign word_addr = ram_addr[12:2];
always @(posedge clk) begin
if (ram_write_enable == 1'b1) begin
mem[word_addr] <= ram_write_data;
end
end
always @(word_addr or ram_write_enable or ram_write_data) begin
if (ram_write_enable == 1'b0) begin
read_data = mem[word_addr];
end else begin
read_data = ram_write_data;
end
end
assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
&& (key_ram_wen == `SCAN_ASCII_WEN)
&& (ram_addr == `SCAN_ASCII_ADDR)
&& (ram_write_enable == 1'b0)) ? key_ram_wdata : read_data;
endmodule | 0 |
3,901 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/registers.v | 107,499,099 | registers.v | v | 278 | 73 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 590: invalid continuation byte | data/verilator_xmls/ea86482c-601b-4fb7-8c99-9489d1f140bb.xml | null | 1,689 | module | module registers (clock, reset,
reg_read_idx1, reg_read_idx2,
reg_write_idx, reg_write_enable, reg_write_data,
reg_read_data1, reg_read_data2);
input clock, reset;
input [4:0] reg_read_idx1;
input [4:0] reg_read_idx2;
input [4:0] reg_write_idx;
input reg_write_enable;
input [31:0] reg_write_data;
output [31:0] reg_read_data1;
output [31:0] reg_read_data2;
reg [31:0] regs_1;
reg [31:0] regs_2;
reg [31:0] regs_3;
reg [31:0] regs_4;
reg [31:0] regs_5;
reg [31:0] regs_6;
reg [31:0] regs_7;
reg [31:0] regs_8;
reg [31:0] regs_9;
reg [31:0] regs_10;
reg [31:0] regs_11;
reg [31:0] regs_12;
reg [31:0] regs_13;
reg [31:0] regs_14;
reg [31:0] regs_15;
reg [31:0] regs_16;
reg [31:0] regs_17;
reg [31:0] regs_18;
reg [31:0] regs_19;
reg [31:0] regs_20;
reg [31:0] regs_21;
reg [31:0] regs_22;
reg [31:0] regs_23;
reg [31:0] regs_24;
reg [31:0] regs_25;
reg [31:0] regs_26;
reg [31:0] regs_27;
reg [31:0] regs_28;
reg [31:0] regs_29;
reg [31:0] regs_30;
reg [31:0] regs_31;
assign reg_read_data1 = (reg_read_idx1 == 5'b00000) ? 0 : (
(reg_read_idx1 == 5'b00001) ? regs_1 : (
(reg_read_idx1 == 5'b00010) ? regs_2 : (
(reg_read_idx1 == 5'b00011) ? regs_3 : (
(reg_read_idx1 == 5'b00100) ? regs_4 : (
(reg_read_idx1 == 5'b00101) ? regs_5 : (
(reg_read_idx1 == 5'b00110) ? regs_6 : (
(reg_read_idx1 == 5'b00111) ? regs_7 : (
(reg_read_idx1 == 5'b01000) ? regs_8 : (
(reg_read_idx1 == 5'b01001) ? regs_9 : (
(reg_read_idx1 == 5'b01010) ? regs_10 : (
(reg_read_idx1 == 5'b01011) ? regs_11 : (
(reg_read_idx1 == 5'b01100) ? regs_12 : (
(reg_read_idx1 == 5'b01101) ? regs_13 : (
(reg_read_idx1 == 5'b01110) ? regs_14 : (
(reg_read_idx1 == 5'b01111) ? regs_15 : (
(reg_read_idx1 == 5'b10000) ? regs_16 : (
(reg_read_idx1 == 5'b10001) ? regs_17 : (
(reg_read_idx1 == 5'b10010) ? regs_18 : (
(reg_read_idx1 == 5'b10011) ? regs_19 : (
(reg_read_idx1 == 5'b10100) ? regs_20 : (
(reg_read_idx1 == 5'b10101) ? regs_21 : (
(reg_read_idx1 == 5'b10110) ? regs_22 : (
(reg_read_idx1 == 5'b10111) ? regs_23 : (
(reg_read_idx1 == 5'b11000) ? regs_24 : (
(reg_read_idx1 == 5'b11001) ? regs_25 : (
(reg_read_idx1 == 5'b11010) ? regs_26 : (
(reg_read_idx1 == 5'b11011) ? regs_27 : (
(reg_read_idx1 == 5'b11100) ? regs_28 : (
(reg_read_idx1 == 5'b11101) ? regs_29 : (
(reg_read_idx1 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));
assign reg_read_data2 = (reg_read_idx2 == 5'b00000) ? 0 : (
(reg_read_idx2 == 5'b00001) ? regs_1 : (
(reg_read_idx2 == 5'b00010) ? regs_2 : (
(reg_read_idx2 == 5'b00011) ? regs_3 : (
(reg_read_idx2 == 5'b00100) ? regs_4 : (
(reg_read_idx2 == 5'b00101) ? regs_5 : (
(reg_read_idx2 == 5'b00110) ? regs_6 : (
(reg_read_idx2 == 5'b00111) ? regs_7 : (
(reg_read_idx2 == 5'b01000) ? regs_8 : (
(reg_read_idx2 == 5'b01001) ? regs_9 : (
(reg_read_idx2 == 5'b01010) ? regs_10 : (
(reg_read_idx2 == 5'b01011) ? regs_11 : (
(reg_read_idx2 == 5'b01100) ? regs_12 : (
(reg_read_idx2 == 5'b01101) ? regs_13 : (
(reg_read_idx2 == 5'b01110) ? regs_14 : (
(reg_read_idx2 == 5'b01111) ? regs_15 : (
(reg_read_idx2 == 5'b10000) ? regs_16 : (
(reg_read_idx2 == 5'b10001) ? regs_17 : (
(reg_read_idx2 == 5'b10010) ? regs_18 : (
(reg_read_idx2 == 5'b10011) ? regs_19 : (
(reg_read_idx2 == 5'b10100) ? regs_20 : (
(reg_read_idx2 == 5'b10101) ? regs_21 : (
(reg_read_idx2 == 5'b10110) ? regs_22 : (
(reg_read_idx2 == 5'b10111) ? regs_23 : (
(reg_read_idx2 == 5'b11000) ? regs_24 : (
(reg_read_idx2 == 5'b11001) ? regs_25 : (
(reg_read_idx2 == 5'b11010) ? regs_26 : (
(reg_read_idx2 == 5'b11011) ? regs_27 : (
(reg_read_idx2 == 5'b11100) ? regs_28 : (
(reg_read_idx2 == 5'b11101) ? regs_29 : (
(reg_read_idx2 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
regs_1 <= 0;
regs_2 <= 0;
regs_3 <= 0;
regs_4 <= 0;
regs_5 <= 0;
regs_6 <= 0;
regs_7 <= 0;
regs_8 <= 0;
regs_9 <= 0;
regs_10 <= 0;
regs_11 <= 0;
regs_12 <= 0;
regs_13 <= 0;
regs_14 <= 0;
regs_15 <= 0;
regs_16 <= 0;
regs_17 <= 0;
regs_18 <= 0;
regs_19 <= 0;
regs_20 <= 0;
regs_21 <= 0;
regs_22 <= 0;
regs_23 <= 0;
regs_24 <= 0;
regs_25 <= 0;
regs_26 <= 0;
regs_27 <= 0;
regs_28 <= 0;
regs_29 <= 0;
regs_30 <= 0;
regs_31 <= 0;
end else begin
if (reg_write_enable == 1'b1) begin
if (reg_write_idx == 5'b00001) begin
regs_1 <= reg_write_data;
end
if (reg_write_idx == 5'b00010) begin
regs_2 <= reg_write_data;
end
if (reg_write_idx == 5'b00011) begin
regs_3 <= reg_write_data;
end
if (reg_write_idx == 5'b00100) begin
regs_4 <= reg_write_data;
end
if (reg_write_idx == 5'b00101) begin
regs_5 <= reg_write_data;
end
if (reg_write_idx == 5'b00110) begin
regs_6 <= reg_write_data;
end
if (reg_write_idx == 5'b00111) begin
regs_7 <= reg_write_data;
end
if (reg_write_idx == 5'b01000) begin
regs_8 <= reg_write_data;
end
if (reg_write_idx == 5'b01001) begin
regs_9 <= reg_write_data;
end
if (reg_write_idx == 5'b01010) begin
regs_10 <= reg_write_data;
end
if (reg_write_idx == 5'b01011) begin
regs_11 <= reg_write_data;
end
if (reg_write_idx == 5'b01100) begin
regs_12 <= reg_write_data;
end
if (reg_write_idx == 5'b01101) begin
regs_13 <= reg_write_data;
end
if (reg_write_idx == 5'b01110) begin
regs_14 <= reg_write_data;
end
if (reg_write_idx == 5'b01111) begin
regs_15 <= reg_write_data;
end
if (reg_write_idx == 5'b10000) begin
regs_16 <= reg_write_data;
end
if (reg_write_idx == 5'b10001) begin
regs_17 <= reg_write_data;
end
if (reg_write_idx == 5'b10010) begin
regs_18 <= reg_write_data;
end
if (reg_write_idx == 5'b10011) begin
regs_19 <= reg_write_data;
end
if (reg_write_idx == 5'b10100) begin
regs_20 <= reg_write_data;
end
if (reg_write_idx == 5'b10101) begin
regs_21 <= reg_write_data;
end
if (reg_write_idx == 5'b10110) begin
regs_22 <= reg_write_data;
end
if (reg_write_idx == 5'b10111) begin
regs_23 <= reg_write_data;
end
if (reg_write_idx == 5'b11000) begin
regs_24 <= reg_write_data;
end
if (reg_write_idx == 5'b11001) begin
regs_25 <= reg_write_data;
end
if (reg_write_idx == 5'b11010) begin
regs_26 <= reg_write_data;
end
if (reg_write_idx == 5'b11011) begin
regs_27 <= reg_write_data;
end
if (reg_write_idx == 5'b11100) begin
regs_28 <= reg_write_data;
end
if (reg_write_idx == 5'b11101) begin
regs_29 <= reg_write_data;
end
if (reg_write_idx == 5'b11110) begin
regs_30 <= reg_write_data;
end
if (reg_write_idx == 5'b11111) begin
regs_31 <= reg_write_data;
end
end
end
end
endmodule | module registers (clock, reset,
reg_read_idx1, reg_read_idx2,
reg_write_idx, reg_write_enable, reg_write_data,
reg_read_data1, reg_read_data2); |
input clock, reset;
input [4:0] reg_read_idx1;
input [4:0] reg_read_idx2;
input [4:0] reg_write_idx;
input reg_write_enable;
input [31:0] reg_write_data;
output [31:0] reg_read_data1;
output [31:0] reg_read_data2;
reg [31:0] regs_1;
reg [31:0] regs_2;
reg [31:0] regs_3;
reg [31:0] regs_4;
reg [31:0] regs_5;
reg [31:0] regs_6;
reg [31:0] regs_7;
reg [31:0] regs_8;
reg [31:0] regs_9;
reg [31:0] regs_10;
reg [31:0] regs_11;
reg [31:0] regs_12;
reg [31:0] regs_13;
reg [31:0] regs_14;
reg [31:0] regs_15;
reg [31:0] regs_16;
reg [31:0] regs_17;
reg [31:0] regs_18;
reg [31:0] regs_19;
reg [31:0] regs_20;
reg [31:0] regs_21;
reg [31:0] regs_22;
reg [31:0] regs_23;
reg [31:0] regs_24;
reg [31:0] regs_25;
reg [31:0] regs_26;
reg [31:0] regs_27;
reg [31:0] regs_28;
reg [31:0] regs_29;
reg [31:0] regs_30;
reg [31:0] regs_31;
assign reg_read_data1 = (reg_read_idx1 == 5'b00000) ? 0 : (
(reg_read_idx1 == 5'b00001) ? regs_1 : (
(reg_read_idx1 == 5'b00010) ? regs_2 : (
(reg_read_idx1 == 5'b00011) ? regs_3 : (
(reg_read_idx1 == 5'b00100) ? regs_4 : (
(reg_read_idx1 == 5'b00101) ? regs_5 : (
(reg_read_idx1 == 5'b00110) ? regs_6 : (
(reg_read_idx1 == 5'b00111) ? regs_7 : (
(reg_read_idx1 == 5'b01000) ? regs_8 : (
(reg_read_idx1 == 5'b01001) ? regs_9 : (
(reg_read_idx1 == 5'b01010) ? regs_10 : (
(reg_read_idx1 == 5'b01011) ? regs_11 : (
(reg_read_idx1 == 5'b01100) ? regs_12 : (
(reg_read_idx1 == 5'b01101) ? regs_13 : (
(reg_read_idx1 == 5'b01110) ? regs_14 : (
(reg_read_idx1 == 5'b01111) ? regs_15 : (
(reg_read_idx1 == 5'b10000) ? regs_16 : (
(reg_read_idx1 == 5'b10001) ? regs_17 : (
(reg_read_idx1 == 5'b10010) ? regs_18 : (
(reg_read_idx1 == 5'b10011) ? regs_19 : (
(reg_read_idx1 == 5'b10100) ? regs_20 : (
(reg_read_idx1 == 5'b10101) ? regs_21 : (
(reg_read_idx1 == 5'b10110) ? regs_22 : (
(reg_read_idx1 == 5'b10111) ? regs_23 : (
(reg_read_idx1 == 5'b11000) ? regs_24 : (
(reg_read_idx1 == 5'b11001) ? regs_25 : (
(reg_read_idx1 == 5'b11010) ? regs_26 : (
(reg_read_idx1 == 5'b11011) ? regs_27 : (
(reg_read_idx1 == 5'b11100) ? regs_28 : (
(reg_read_idx1 == 5'b11101) ? regs_29 : (
(reg_read_idx1 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));
assign reg_read_data2 = (reg_read_idx2 == 5'b00000) ? 0 : (
(reg_read_idx2 == 5'b00001) ? regs_1 : (
(reg_read_idx2 == 5'b00010) ? regs_2 : (
(reg_read_idx2 == 5'b00011) ? regs_3 : (
(reg_read_idx2 == 5'b00100) ? regs_4 : (
(reg_read_idx2 == 5'b00101) ? regs_5 : (
(reg_read_idx2 == 5'b00110) ? regs_6 : (
(reg_read_idx2 == 5'b00111) ? regs_7 : (
(reg_read_idx2 == 5'b01000) ? regs_8 : (
(reg_read_idx2 == 5'b01001) ? regs_9 : (
(reg_read_idx2 == 5'b01010) ? regs_10 : (
(reg_read_idx2 == 5'b01011) ? regs_11 : (
(reg_read_idx2 == 5'b01100) ? regs_12 : (
(reg_read_idx2 == 5'b01101) ? regs_13 : (
(reg_read_idx2 == 5'b01110) ? regs_14 : (
(reg_read_idx2 == 5'b01111) ? regs_15 : (
(reg_read_idx2 == 5'b10000) ? regs_16 : (
(reg_read_idx2 == 5'b10001) ? regs_17 : (
(reg_read_idx2 == 5'b10010) ? regs_18 : (
(reg_read_idx2 == 5'b10011) ? regs_19 : (
(reg_read_idx2 == 5'b10100) ? regs_20 : (
(reg_read_idx2 == 5'b10101) ? regs_21 : (
(reg_read_idx2 == 5'b10110) ? regs_22 : (
(reg_read_idx2 == 5'b10111) ? regs_23 : (
(reg_read_idx2 == 5'b11000) ? regs_24 : (
(reg_read_idx2 == 5'b11001) ? regs_25 : (
(reg_read_idx2 == 5'b11010) ? regs_26 : (
(reg_read_idx2 == 5'b11011) ? regs_27 : (
(reg_read_idx2 == 5'b11100) ? regs_28 : (
(reg_read_idx2 == 5'b11101) ? regs_29 : (
(reg_read_idx2 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
regs_1 <= 0;
regs_2 <= 0;
regs_3 <= 0;
regs_4 <= 0;
regs_5 <= 0;
regs_6 <= 0;
regs_7 <= 0;
regs_8 <= 0;
regs_9 <= 0;
regs_10 <= 0;
regs_11 <= 0;
regs_12 <= 0;
regs_13 <= 0;
regs_14 <= 0;
regs_15 <= 0;
regs_16 <= 0;
regs_17 <= 0;
regs_18 <= 0;
regs_19 <= 0;
regs_20 <= 0;
regs_21 <= 0;
regs_22 <= 0;
regs_23 <= 0;
regs_24 <= 0;
regs_25 <= 0;
regs_26 <= 0;
regs_27 <= 0;
regs_28 <= 0;
regs_29 <= 0;
regs_30 <= 0;
regs_31 <= 0;
end else begin
if (reg_write_enable == 1'b1) begin
if (reg_write_idx == 5'b00001) begin
regs_1 <= reg_write_data;
end
if (reg_write_idx == 5'b00010) begin
regs_2 <= reg_write_data;
end
if (reg_write_idx == 5'b00011) begin
regs_3 <= reg_write_data;
end
if (reg_write_idx == 5'b00100) begin
regs_4 <= reg_write_data;
end
if (reg_write_idx == 5'b00101) begin
regs_5 <= reg_write_data;
end
if (reg_write_idx == 5'b00110) begin
regs_6 <= reg_write_data;
end
if (reg_write_idx == 5'b00111) begin
regs_7 <= reg_write_data;
end
if (reg_write_idx == 5'b01000) begin
regs_8 <= reg_write_data;
end
if (reg_write_idx == 5'b01001) begin
regs_9 <= reg_write_data;
end
if (reg_write_idx == 5'b01010) begin
regs_10 <= reg_write_data;
end
if (reg_write_idx == 5'b01011) begin
regs_11 <= reg_write_data;
end
if (reg_write_idx == 5'b01100) begin
regs_12 <= reg_write_data;
end
if (reg_write_idx == 5'b01101) begin
regs_13 <= reg_write_data;
end
if (reg_write_idx == 5'b01110) begin
regs_14 <= reg_write_data;
end
if (reg_write_idx == 5'b01111) begin
regs_15 <= reg_write_data;
end
if (reg_write_idx == 5'b10000) begin
regs_16 <= reg_write_data;
end
if (reg_write_idx == 5'b10001) begin
regs_17 <= reg_write_data;
end
if (reg_write_idx == 5'b10010) begin
regs_18 <= reg_write_data;
end
if (reg_write_idx == 5'b10011) begin
regs_19 <= reg_write_data;
end
if (reg_write_idx == 5'b10100) begin
regs_20 <= reg_write_data;
end
if (reg_write_idx == 5'b10101) begin
regs_21 <= reg_write_data;
end
if (reg_write_idx == 5'b10110) begin
regs_22 <= reg_write_data;
end
if (reg_write_idx == 5'b10111) begin
regs_23 <= reg_write_data;
end
if (reg_write_idx == 5'b11000) begin
regs_24 <= reg_write_data;
end
if (reg_write_idx == 5'b11001) begin
regs_25 <= reg_write_data;
end
if (reg_write_idx == 5'b11010) begin
regs_26 <= reg_write_data;
end
if (reg_write_idx == 5'b11011) begin
regs_27 <= reg_write_data;
end
if (reg_write_idx == 5'b11100) begin
regs_28 <= reg_write_data;
end
if (reg_write_idx == 5'b11101) begin
regs_29 <= reg_write_data;
end
if (reg_write_idx == 5'b11110) begin
regs_30 <= reg_write_data;
end
if (reg_write_idx == 5'b11111) begin
regs_31 <= reg_write_data;
end
end
end
end
endmodule | 0 |
3,902 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/rom8x1024_DE2.v | 107,499,099 | rom8x1024_DE2.v | v | 38 | 65 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/rom8x1024_DE2.v:26: Cannot find file containing module: 'lpm_rom'\n lpm_rom lpm_rom_component (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/lpm_rom\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/lpm_rom.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/lpm_rom.sv\n lpm_rom\n lpm_rom.v\n lpm_rom.sv\n obj_dir/lpm_rom\n obj_dir/lpm_rom.v\n obj_dir/lpm_rom.sv\n%Error: Exiting due to 1 error(s)\n" | 1,690 | module | module rom8x1024_DE2 (clock, rom_addr, rom_data);
input clock;
input [11:0] rom_addr;
output [31:0] rom_data;
wire [9:0] word_addr;
assign word_addr = rom_addr[11:2];
lpm_rom lpm_rom_component (
.address(word_addr),
.inclock(clock),
.outclock(clock),
.q(rom_data));
defparam lpm_rom_component.LPM_WIDTH = 32,
lpm_rom_component.LPM_WIDTHAD = 10,
lpm_rom_component.LPM_ADDRESS_CONTROL = "REGISTERED",
lpm_rom_component.LPM_OUTDATA = "REGISTERED",
lpm_rom_component.LPM_FILE = "rom8x1024_DE2.mif";
endmodule | module rom8x1024_DE2 (clock, rom_addr, rom_data); |
input clock;
input [11:0] rom_addr;
output [31:0] rom_data;
wire [9:0] word_addr;
assign word_addr = rom_addr[11:2];
lpm_rom lpm_rom_component (
.address(word_addr),
.inclock(clock),
.outclock(clock),
.q(rom_data));
defparam lpm_rom_component.LPM_WIDTH = 32,
lpm_rom_component.LPM_WIDTHAD = 10,
lpm_rom_component.LPM_ADDRESS_CONTROL = "REGISTERED",
lpm_rom_component.LPM_OUTDATA = "REGISTERED",
lpm_rom_component.LPM_FILE = "rom8x1024_DE2.mif";
endmodule | 0 |
3,903 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/shifter32_32_l2.v | 107,499,099 | shifter32_32_l2.v | v | 17 | 52 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 191: invalid continuation byte | data/verilator_xmls/0ba45889-fbb7-493e-ad73-eab04874cbf0.xml | null | 1,692 | module | module shifter32_32_l2 (sh_a, sh_y);
input [31:0] sh_a;
output [31:0] sh_y;
assign sh_y = {sh_a[29:0], 2'b00};
endmodule | module shifter32_32_l2 (sh_a, sh_y); |
input [31:0] sh_a;
output [31:0] sh_y;
assign sh_y = {sh_a[29:0], 2'b00};
endmodule | 0 |
3,904 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/shifter32_8_l2.v | 107,499,099 | shifter32_8_l2.v | v | 17 | 51 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 188: invalid continuation byte | data/verilator_xmls/a61fc039-50e3-4097-adb8-caddeefd4ae9.xml | null | 1,693 | module | module shifter32_8_l2 (sh_a, sh_y);
input [31:0] sh_a;
output [7:0] sh_y;
assign sh_y = {sh_a[5:0], 2'b00};
endmodule | module shifter32_8_l2 (sh_a, sh_y); |
input [31:0] sh_a;
output [7:0] sh_y;
assign sh_y = {sh_a[5:0], 2'b00};
endmodule | 0 |
3,905 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/signext16_32.v | 107,499,099 | signext16_32.v | v | 25 | 57 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc6 in position 206: invalid continuation byte | data/verilator_xmls/7fc0bbff-814d-4811-af0f-f81f2869dd20.xml | null | 1,694 | module | module signext16_32 (sign_ext, a16, y32);
input sign_ext;
input [15:0] a16;
output [31:0] y32;
assign y32 = (sign_ext == 1'b1) ?
{a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15:0]}
: {16'h0000, a16[15:0]};
endmodule | module signext16_32 (sign_ext, a16, y32); |
input sign_ext;
input [15:0] a16;
output [31:0] y32;
assign y32 = (sign_ext == 1'b1) ?
{a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15], a16[15], a16[15], a16[15],
a16[15:0]}
: {16'h0000, a16[15:0]};
endmodule | 0 |
3,906 | data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v | 107,499,099 | test_cpu.v | v | 78 | 78 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:8: Cannot find include file: cpu.v\n`include "cpu.v" // cpu.v \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v.v\n data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v.sv\n cpu.v\n cpu.v.v\n cpu.v.sv\n obj_dir/cpu.v\n obj_dir/cpu.v.v\n obj_dir/cpu.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:61: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:64: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ! clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_ctrl_clk = ! clk_ctrl_clk;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 1,695 | module | module test_cpu ;
reg clk;
reg reset;
reg clk_ctrl0;
reg clk_ctrl1;
reg clk_ctrl_clk;
reg [12:0] i_ram_addr;
reg [31:0] i_ram_wdata;
reg i_ram_wen;
wire o_clock;
wire [7:0] o_pc;
wire [31:0] o_alu_y;
wire [31:0] o_alu_a;
wire [31:0] o_alu_b;
wire [3:0] o_alu_ctrl;
wire [1:0] o_alu_comp;
wire [31:0] o_reg_data1;
wire [4:0] o_reg_idx1;
wire [31:0] o_reg_data2;
wire [4:0] o_reg_idx2;
wire [31:0] o_reg_wdata;
wire [4:0] o_reg_widx;
wire o_reg_wen;
wire [12:0] o_ram_addr;
wire [31:0] o_ram_rdata;
wire [31:0] o_ram_wdata;
wire o_ram_wen;
cpu cpua (clk, reset,
clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata,
o_reg_widx, o_reg_wen,
o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
i_ram_addr, i_ram_wdata, i_ram_wen
);
initial begin
clk = 0; reset = 1;
clk_ctrl0 = 1; clk_ctrl1 = 1;
clk_ctrl_clk = 0;
#20 reset = 0;
#20 reset = 1;
#100000 $finish;
end
always begin
#10 clk = ! clk;
end
always begin
#10 clk_ctrl_clk = ! clk_ctrl_clk;
end
endmodule | module test_cpu ; |
reg clk;
reg reset;
reg clk_ctrl0;
reg clk_ctrl1;
reg clk_ctrl_clk;
reg [12:0] i_ram_addr;
reg [31:0] i_ram_wdata;
reg i_ram_wen;
wire o_clock;
wire [7:0] o_pc;
wire [31:0] o_alu_y;
wire [31:0] o_alu_a;
wire [31:0] o_alu_b;
wire [3:0] o_alu_ctrl;
wire [1:0] o_alu_comp;
wire [31:0] o_reg_data1;
wire [4:0] o_reg_idx1;
wire [31:0] o_reg_data2;
wire [4:0] o_reg_idx2;
wire [31:0] o_reg_wdata;
wire [4:0] o_reg_widx;
wire o_reg_wen;
wire [12:0] o_ram_addr;
wire [31:0] o_ram_rdata;
wire [31:0] o_ram_wdata;
wire o_ram_wen;
cpu cpua (clk, reset,
clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata,
o_reg_widx, o_reg_wen,
o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
i_ram_addr, i_ram_wdata, i_ram_wen
);
initial begin
clk = 0; reset = 1;
clk_ctrl0 = 1; clk_ctrl1 = 1;
clk_ctrl_clk = 0;
#20 reset = 0;
#20 reset = 1;
#100000 $finish;
end
always begin
#10 clk = ! clk;
end
always begin
#10 clk_ctrl_clk = ! clk_ctrl_clk;
end
endmodule | 0 |
3,907 | data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v | 107,499,099 | AUDIO_DAC.v | v | 326 | 68 | [] | [] | [] | [(1, 321)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:86: Operator GTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'BCK_DIV\' generates 4 bits.\n : ... In instance AUDIO_DAC\n if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:111: Operator GTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'LRCK_1X_DIV\' generates 9 bits.\n : ... In instance AUDIO_DAC\n if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:119: Operator GTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'LRCK_2X_DIV\' generates 8 bits.\n : ... In instance AUDIO_DAC\n if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:127: Operator GTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'LRCK_4X_DIV\' generates 7 bits.\n : ... In instance AUDIO_DAC\n if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )\n ^~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:159: Operator LT expects 32 or 21 bits on the LHS, but LHS\'s VARREF \'FLASH_Cont\' generates 20 bits.\n : ... In instance AUDIO_DAC\n if(FLASH_Cont < FLASH_DATA_NUM-1 )\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:195: Operator LT expects 32 or 23 bits on the LHS, but LHS\'s VARREF \'SDRAM_Cont\' generates 22 bits.\n : ... In instance AUDIO_DAC\n if(SDRAM_Cont < SDRAM_DATA_NUM-1 )\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:201: Operator ASSIGNW expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'SDRAM_Cont\' generates 22 bits.\n : ... In instance AUDIO_DAC\nassign oSDRAM_ADDR = SDRAM_Cont;\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:226: Operator LT expects 32 or 19 bits on the LHS, but LHS\'s VARREF \'SRAM_Cont\' generates 18 bits.\n : ... In instance AUDIO_DAC\n if(SRAM_Cont < SRAM_DATA_NUM-1 )\n ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/V/AUDIO_DAC.v:232: Operator ASSIGNW expects 19 bits on the Assign RHS, but Assign RHS\'s VARREF \'SRAM_Cont\' generates 18 bits.\n : ... In instance AUDIO_DAC\nassign oSRAM_ADDR = SRAM_Cont;\n ^\n%Error: Exiting due to 9 warning(s)\n' | 1,696 | module | module AUDIO_DAC (
oFLASH_ADDR,iFLASH_DATA,
oSDRAM_ADDR,iSDRAM_DATA,
oSRAM_ADDR,iSRAM_DATA,
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
iSrc_Select,
iCLK_18_4,
iRST_N );
parameter REF_CLK = 18432000;
parameter SAMPLE_RATE = 48000;
parameter DATA_WIDTH = 16;
parameter CHANNEL_NUM = 2;
parameter SIN_SAMPLE_DATA = 48;
parameter FLASH_DATA_NUM = 1048576;
parameter SDRAM_DATA_NUM = 4194304;
parameter SRAM_DATA_NUM = 262144;
parameter FLASH_ADDR_WIDTH= 20;
parameter SDRAM_ADDR_WIDTH= 22;
parameter SRAM_ADDR_WIDTH= 18;
parameter FLASH_DATA_WIDTH= 8;
parameter SDRAM_DATA_WIDTH= 16;
parameter SRAM_DATA_WIDTH= 16;
parameter SIN_SANPLE = 0;
parameter FLASH_DATA = 1;
parameter SDRAM_DATA = 2;
parameter SRAM_DATA = 3;
output [FLASH_ADDR_WIDTH-1:0] oFLASH_ADDR;
input [FLASH_DATA_WIDTH-1:0] iFLASH_DATA;
output [SDRAM_ADDR_WIDTH:0] oSDRAM_ADDR;
input [SDRAM_DATA_WIDTH-1:0] iSDRAM_DATA;
output [SRAM_ADDR_WIDTH:0] oSRAM_ADDR;
input [SRAM_DATA_WIDTH-1:0] iSRAM_DATA;
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
input [1:0] iSrc_Select;
input iCLK_18_4;
input iRST_N;
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
reg [5:0] SIN_Cont;
reg [FLASH_ADDR_WIDTH-1:0] FLASH_Cont;
reg [SDRAM_ADDR_WIDTH-1:0] SDRAM_Cont;
reg [SRAM_ADDR_WIDTH-1:0] SRAM_Cont;
reg [DATA_WIDTH-1:0] Sin_Out;
reg [DATA_WIDTH-1:0] FLASH_Out;
reg [DATA_WIDTH-1:0] SDRAM_Out;
reg [DATA_WIDTH-1:0] SRAM_Out;
reg [DATA_WIDTH-1:0] FLASH_Out_Tmp;
reg [DATA_WIDTH-1:0] SDRAM_Out_Tmp;
reg [DATA_WIDTH-1:0] SRAM_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
always@(negedge LRCK_1X or negedge iRST_N)
begin
if(!iRST_N)
SIN_Cont <= 0;
else
begin
if(SIN_Cont < SIN_SAMPLE_DATA-1 )
SIN_Cont <= SIN_Cont+1;
else
SIN_Cont <= 0;
end
end
always@(negedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Cont <= 0;
else
begin
if(FLASH_Cont < FLASH_DATA_NUM-1 )
FLASH_Cont <= FLASH_Cont+1;
else
FLASH_Cont <= 0;
end
end
assign oFLASH_ADDR = FLASH_Cont;
always@(posedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out_Tmp <= 0;
else
begin
if(FLASH_Cont[0])
FLASH_Out_Tmp[15:8] <= iFLASH_DATA;
else
FLASH_Out_Tmp[7:0] <= iFLASH_DATA;
end
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out <= 0;
else
FLASH_Out <= FLASH_Out_Tmp;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Cont <= 0;
else
begin
if(SDRAM_Cont < SDRAM_DATA_NUM-1 )
SDRAM_Cont <= SDRAM_Cont+1;
else
SDRAM_Cont <= 0;
end
end
assign oSDRAM_ADDR = SDRAM_Cont;
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out_Tmp <= 0;
else
SDRAM_Out_Tmp <= iSDRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out <= 0;
else
SDRAM_Out <= SDRAM_Out_Tmp;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Cont <= 0;
else
begin
if(SRAM_Cont < SRAM_DATA_NUM-1 )
SRAM_Cont <= SRAM_Cont+1;
else
SRAM_Cont <= 0;
end
end
assign oSRAM_ADDR = SRAM_Cont;
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out_Tmp <= 0;
else
SRAM_Out_Tmp <= iSRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out <= 0;
else
SRAM_Out <= SRAM_Out_Tmp;
end
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = (iSrc_Select==SIN_SANPLE) ? Sin_Out[~SEL_Cont] :
(iSrc_Select==FLASH_DATA) ? FLASH_Out[~SEL_Cont]:
(iSrc_Select==SDRAM_DATA) ? SDRAM_Out[~SEL_Cont]:
SRAM_Out[~SEL_Cont] ;
always@(SIN_Cont)
begin
case(SIN_Cont)
0 : Sin_Out <= 0 ;
1 : Sin_Out <= 4276 ;
2 : Sin_Out <= 8480 ;
3 : Sin_Out <= 12539 ;
4 : Sin_Out <= 16383 ;
5 : Sin_Out <= 19947 ;
6 : Sin_Out <= 23169 ;
7 : Sin_Out <= 25995 ;
8 : Sin_Out <= 28377 ;
9 : Sin_Out <= 30272 ;
10 : Sin_Out <= 31650 ;
11 : Sin_Out <= 32486 ;
12 : Sin_Out <= 32767 ;
13 : Sin_Out <= 32486 ;
14 : Sin_Out <= 31650 ;
15 : Sin_Out <= 30272 ;
16 : Sin_Out <= 28377 ;
17 : Sin_Out <= 25995 ;
18 : Sin_Out <= 23169 ;
19 : Sin_Out <= 19947 ;
20 : Sin_Out <= 16383 ;
21 : Sin_Out <= 12539 ;
22 : Sin_Out <= 8480 ;
23 : Sin_Out <= 4276 ;
24 : Sin_Out <= 0 ;
25 : Sin_Out <= 61259 ;
26 : Sin_Out <= 57056 ;
27 : Sin_Out <= 52997 ;
28 : Sin_Out <= 49153 ;
29 : Sin_Out <= 45589 ;
30 : Sin_Out <= 42366 ;
31 : Sin_Out <= 39540 ;
32 : Sin_Out <= 37159 ;
33 : Sin_Out <= 35263 ;
34 : Sin_Out <= 33885 ;
35 : Sin_Out <= 33049 ;
36 : Sin_Out <= 32768 ;
37 : Sin_Out <= 33049 ;
38 : Sin_Out <= 33885 ;
39 : Sin_Out <= 35263 ;
40 : Sin_Out <= 37159 ;
41 : Sin_Out <= 39540 ;
42 : Sin_Out <= 42366 ;
43 : Sin_Out <= 45589 ;
44 : Sin_Out <= 49152 ;
45 : Sin_Out <= 52997 ;
46 : Sin_Out <= 57056 ;
47 : Sin_Out <= 61259 ;
default :
Sin_Out <= 0 ;
endcase
end
endmodule | module AUDIO_DAC (
oFLASH_ADDR,iFLASH_DATA,
oSDRAM_ADDR,iSDRAM_DATA,
oSRAM_ADDR,iSRAM_DATA,
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
iSrc_Select,
iCLK_18_4,
iRST_N ); |
parameter REF_CLK = 18432000;
parameter SAMPLE_RATE = 48000;
parameter DATA_WIDTH = 16;
parameter CHANNEL_NUM = 2;
parameter SIN_SAMPLE_DATA = 48;
parameter FLASH_DATA_NUM = 1048576;
parameter SDRAM_DATA_NUM = 4194304;
parameter SRAM_DATA_NUM = 262144;
parameter FLASH_ADDR_WIDTH= 20;
parameter SDRAM_ADDR_WIDTH= 22;
parameter SRAM_ADDR_WIDTH= 18;
parameter FLASH_DATA_WIDTH= 8;
parameter SDRAM_DATA_WIDTH= 16;
parameter SRAM_DATA_WIDTH= 16;
parameter SIN_SANPLE = 0;
parameter FLASH_DATA = 1;
parameter SDRAM_DATA = 2;
parameter SRAM_DATA = 3;
output [FLASH_ADDR_WIDTH-1:0] oFLASH_ADDR;
input [FLASH_DATA_WIDTH-1:0] iFLASH_DATA;
output [SDRAM_ADDR_WIDTH:0] oSDRAM_ADDR;
input [SDRAM_DATA_WIDTH-1:0] iSDRAM_DATA;
output [SRAM_ADDR_WIDTH:0] oSRAM_ADDR;
input [SRAM_DATA_WIDTH-1:0] iSRAM_DATA;
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
input [1:0] iSrc_Select;
input iCLK_18_4;
input iRST_N;
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
reg [5:0] SIN_Cont;
reg [FLASH_ADDR_WIDTH-1:0] FLASH_Cont;
reg [SDRAM_ADDR_WIDTH-1:0] SDRAM_Cont;
reg [SRAM_ADDR_WIDTH-1:0] SRAM_Cont;
reg [DATA_WIDTH-1:0] Sin_Out;
reg [DATA_WIDTH-1:0] FLASH_Out;
reg [DATA_WIDTH-1:0] SDRAM_Out;
reg [DATA_WIDTH-1:0] SRAM_Out;
reg [DATA_WIDTH-1:0] FLASH_Out_Tmp;
reg [DATA_WIDTH-1:0] SDRAM_Out_Tmp;
reg [DATA_WIDTH-1:0] SRAM_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
always@(negedge LRCK_1X or negedge iRST_N)
begin
if(!iRST_N)
SIN_Cont <= 0;
else
begin
if(SIN_Cont < SIN_SAMPLE_DATA-1 )
SIN_Cont <= SIN_Cont+1;
else
SIN_Cont <= 0;
end
end
always@(negedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Cont <= 0;
else
begin
if(FLASH_Cont < FLASH_DATA_NUM-1 )
FLASH_Cont <= FLASH_Cont+1;
else
FLASH_Cont <= 0;
end
end
assign oFLASH_ADDR = FLASH_Cont;
always@(posedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out_Tmp <= 0;
else
begin
if(FLASH_Cont[0])
FLASH_Out_Tmp[15:8] <= iFLASH_DATA;
else
FLASH_Out_Tmp[7:0] <= iFLASH_DATA;
end
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out <= 0;
else
FLASH_Out <= FLASH_Out_Tmp;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Cont <= 0;
else
begin
if(SDRAM_Cont < SDRAM_DATA_NUM-1 )
SDRAM_Cont <= SDRAM_Cont+1;
else
SDRAM_Cont <= 0;
end
end
assign oSDRAM_ADDR = SDRAM_Cont;
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out_Tmp <= 0;
else
SDRAM_Out_Tmp <= iSDRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out <= 0;
else
SDRAM_Out <= SDRAM_Out_Tmp;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Cont <= 0;
else
begin
if(SRAM_Cont < SRAM_DATA_NUM-1 )
SRAM_Cont <= SRAM_Cont+1;
else
SRAM_Cont <= 0;
end
end
assign oSRAM_ADDR = SRAM_Cont;
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out_Tmp <= 0;
else
SRAM_Out_Tmp <= iSRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out <= 0;
else
SRAM_Out <= SRAM_Out_Tmp;
end
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = (iSrc_Select==SIN_SANPLE) ? Sin_Out[~SEL_Cont] :
(iSrc_Select==FLASH_DATA) ? FLASH_Out[~SEL_Cont]:
(iSrc_Select==SDRAM_DATA) ? SDRAM_Out[~SEL_Cont]:
SRAM_Out[~SEL_Cont] ;
always@(SIN_Cont)
begin
case(SIN_Cont)
0 : Sin_Out <= 0 ;
1 : Sin_Out <= 4276 ;
2 : Sin_Out <= 8480 ;
3 : Sin_Out <= 12539 ;
4 : Sin_Out <= 16383 ;
5 : Sin_Out <= 19947 ;
6 : Sin_Out <= 23169 ;
7 : Sin_Out <= 25995 ;
8 : Sin_Out <= 28377 ;
9 : Sin_Out <= 30272 ;
10 : Sin_Out <= 31650 ;
11 : Sin_Out <= 32486 ;
12 : Sin_Out <= 32767 ;
13 : Sin_Out <= 32486 ;
14 : Sin_Out <= 31650 ;
15 : Sin_Out <= 30272 ;
16 : Sin_Out <= 28377 ;
17 : Sin_Out <= 25995 ;
18 : Sin_Out <= 23169 ;
19 : Sin_Out <= 19947 ;
20 : Sin_Out <= 16383 ;
21 : Sin_Out <= 12539 ;
22 : Sin_Out <= 8480 ;
23 : Sin_Out <= 4276 ;
24 : Sin_Out <= 0 ;
25 : Sin_Out <= 61259 ;
26 : Sin_Out <= 57056 ;
27 : Sin_Out <= 52997 ;
28 : Sin_Out <= 49153 ;
29 : Sin_Out <= 45589 ;
30 : Sin_Out <= 42366 ;
31 : Sin_Out <= 39540 ;
32 : Sin_Out <= 37159 ;
33 : Sin_Out <= 35263 ;
34 : Sin_Out <= 33885 ;
35 : Sin_Out <= 33049 ;
36 : Sin_Out <= 32768 ;
37 : Sin_Out <= 33049 ;
38 : Sin_Out <= 33885 ;
39 : Sin_Out <= 35263 ;
40 : Sin_Out <= 37159 ;
41 : Sin_Out <= 39540 ;
42 : Sin_Out <= 42366 ;
43 : Sin_Out <= 45589 ;
44 : Sin_Out <= 49152 ;
45 : Sin_Out <= 52997 ;
46 : Sin_Out <= 57056 ;
47 : Sin_Out <= 61259 ;
default :
Sin_Out <= 0 ;
endcase
end
endmodule | 0 |
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