Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
4,498 | data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v | 110,151,336 | testbench.v | v | 43 | 95 | [] | [] | [] | [(3, 42)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:11: Unsupported or unknown PLI call: $dumpvars\n initial $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:18: Unsupported or unknown PLI call: $monitor\n $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 4\'h0; rst_n = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 4\'h1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 4\'h2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 4\'h3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 4\'h4; rst_n = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 4\'h5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 0; d = 4\'h6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n # 20; clk = 1; d = 4\'h7; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 4\'h8; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 4\'h9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 4\'ha; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 4\'hb; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 4\'hc; rst_n = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 4\'hd;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 0; d = 4\'he;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 4\'hf;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n # 10; clk = 1; d = 4\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n # 20;\n ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,786 | module | module testbench;
reg clk, rst_n;
reg [3:0] d;
wire [3:0] q;
dff_async_rst_n_param #(.WIDTH(4), .RESET(4'ha)) dff_async_rst_n_param (clk, rst_n, d, q);
initial $dumpvars;
initial
begin
rst_n = 1;
clk = 1;
$monitor ("%0d clk %b d %b q %b", $time, clk, d, q);
# 20; clk = 0; d = 4'h0; rst_n = 0;
# 20; clk = 1; d = 4'h1;
# 20; clk = 0; d = 4'h2;
# 20; clk = 1; d = 4'h3;
# 20; clk = 0; d = 4'h4; rst_n = 1;
# 20; clk = 1; d = 4'h5;
# 20; clk = 0; d = 4'h6;
# 20; clk = 1; d = 4'h7;
# 10; clk = 1; d = 4'h8;
# 10; clk = 0; d = 4'h9;
# 10; clk = 0; d = 4'ha;
# 10; clk = 1; d = 4'hb;
# 10; clk = 1; d = 4'hc; rst_n = 0;
# 10; clk = 0; d = 4'hd;
# 10; clk = 0; d = 4'he;
# 10; clk = 1; d = 4'hf;
# 10; clk = 1; d = 4'h0;
# 20;
$finish;
end
endmodule | module testbench; |
reg clk, rst_n;
reg [3:0] d;
wire [3:0] q;
dff_async_rst_n_param #(.WIDTH(4), .RESET(4'ha)) dff_async_rst_n_param (clk, rst_n, d, q);
initial $dumpvars;
initial
begin
rst_n = 1;
clk = 1;
$monitor ("%0d clk %b d %b q %b", $time, clk, d, q);
# 20; clk = 0; d = 4'h0; rst_n = 0;
# 20; clk = 1; d = 4'h1;
# 20; clk = 0; d = 4'h2;
# 20; clk = 1; d = 4'h3;
# 20; clk = 0; d = 4'h4; rst_n = 1;
# 20; clk = 1; d = 4'h5;
# 20; clk = 0; d = 4'h6;
# 20; clk = 1; d = 4'h7;
# 10; clk = 1; d = 4'h8;
# 10; clk = 0; d = 4'h9;
# 10; clk = 0; d = 4'ha;
# 10; clk = 1; d = 4'hb;
# 10; clk = 1; d = 4'hc; rst_n = 0;
# 10; clk = 0; d = 4'hd;
# 10; clk = 0; d = 4'he;
# 10; clk = 1; d = 4'hf;
# 10; clk = 1; d = 4'h0;
# 20;
$finish;
end
endmodule | 16 |
4,499 | data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite/de10_lite.v | 110,151,336 | de10_lite.v | v | 27 | 33 | [] | [] | [] | [(1, 26)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite/de10_lite.v:13: Cannot find file containing module: 'dff_async_rst_n_param'\n dff_async_rst_n_param \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param\n data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param.v\n data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param.sv\n dff_async_rst_n_param\n dff_async_rst_n_param.v\n dff_async_rst_n_param.sv\n obj_dir/dff_async_rst_n_param\n obj_dir/dff_async_rst_n_param.v\n obj_dir/dff_async_rst_n_param.sv\n%Error: Exiting due to 1 error(s)\n" | 2,787 | module | module de10_lite
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
);
assign LEDR[0] = 1'b0;
dff_async_rst_n_param
#(
.WIDTH ( 8 ),
.RESET ( 8'hf0 )
)
dff_async_rst_n_param
(
.clk ( ~KEY [0] ),
.rst_n ( SW [0] ),
.d ( SW [9:1] ),
.q ( LEDR [9:1] )
);
endmodule | module de10_lite
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
); |
assign LEDR[0] = 1'b0;
dff_async_rst_n_param
#(
.WIDTH ( 8 ),
.RESET ( 8'hf0 )
)
dff_async_rst_n_param
(
.clk ( ~KEY [0] ),
.rst_n ( SW [0] ),
.d ( SW [9:1] ),
.q ( LEDR [9:1] )
);
endmodule | 16 |
4,500 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_comb_incorrect
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
);
assign y = (sel & d1) | ((~sel) & d0);
endmodule | module b2_mux_2_1_comb_incorrect
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
); |
assign y = (sel & d1) | ((~sel) & d0);
endmodule | 16 |
4,501 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_comb_correct1
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
);
assign y[0] = (sel & d1[0]) | ((~sel) & d0[0]);
assign y[1] = (sel & d1[1]) | ((~sel) & d0[1]);
endmodule | module b2_mux_2_1_comb_correct1
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
); |
assign y[0] = (sel & d1[0]) | ((~sel) & d0[0]);
assign y[1] = (sel & d1[1]) | ((~sel) & d0[1]);
endmodule | 16 |
4,502 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_comb_correct2
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
);
wire [1:0] select;
assign select = {sel,sel};
assign y = (select & d1) | (~select & d0);
endmodule | module b2_mux_2_1_comb_correct2
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
); |
wire [1:0] select;
assign select = {sel,sel};
assign y = (select & d1) | (~select & d0);
endmodule | 16 |
4,503 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_sel
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
);
assign y = sel ? d1 : d0;
endmodule | module b2_mux_2_1_sel
(
input [1:0] d0,
input [1:0] d1,
input sel,
output [1:0] y
); |
assign y = sel ? d1 : d0;
endmodule | 16 |
4,504 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_if
(
input [1:0] d0,
input [1:0] d1,
input sel,
output reg [1:0] y
);
always@(*)
begin
if(sel)
y = d1;
else
y = d0;
end
endmodule | module b2_mux_2_1_if
(
input [1:0] d0,
input [1:0] d1,
input sel,
output reg [1:0] y
); |
always@(*)
begin
if(sel)
y = d1;
else
y = d0;
end
endmodule | 16 |
4,505 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module b2_mux_2_1_case
(
input [1:0] d0,
input [1:0] d1,
input sel,
output reg [1:0] y
);
always@(*)
begin
case (sel)
0: y = d0;
1: y = d1;
endcase
end
endmodule | module b2_mux_2_1_case
(
input [1:0] d0,
input [1:0] d1,
input sel,
output reg [1:0] y
); |
always@(*)
begin
case (sel)
0: y = d0;
1: y = d1;
endcase
end
endmodule | 16 |
4,506 | data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v | 110,151,336 | lab4.v | v | 99 | 108 | [] | [] | [] | [(1, 11), (13, 24), (26, 37), (39, 49), (51, 66), (68, 83), (86, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n ^~~~~~~~~~~~~~~\n : ... Top module \'lab4\'\nmodule lab4\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n : ... In instance lab4.b2_mux_2_1_comb_incorrect\n assign y = (sel & d1) | ((~sel) & d0);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 2,790 | module | module lab4
(
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
);
b2_mux_2_1_sel b2_mux_2_1_sel(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[1:0]));
b2_mux_2_1_if b2_mux_2_1_if(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[3:2]));
b2_mux_2_1_comb_correct1 b2_mux_2_1_comb_correct1(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[5:4]));
b2_mux_2_1_comb_correct2 b2_mux_2_1_comb_correct2(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[7:6]));
b2_mux_2_1_comb_incorrect b2_mux_2_1_comb_incorrect(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[9:8]));
endmodule | module lab4
(
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
); |
b2_mux_2_1_sel b2_mux_2_1_sel(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[1:0]));
b2_mux_2_1_if b2_mux_2_1_if(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[3:2]));
b2_mux_2_1_comb_correct1 b2_mux_2_1_comb_correct1(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[5:4]));
b2_mux_2_1_comb_correct2 b2_mux_2_1_comb_correct2(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[7:6]));
b2_mux_2_1_comb_incorrect b2_mux_2_1_comb_incorrect(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[9:8]));
endmodule | 16 |
4,516 | data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v | 110,151,336 | testbench.v | v | 54 | 169 | [] | [] | [] | [(4, 53)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:48: Unsupported or unknown PLI call: $monitor\n $monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b", \n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars; \n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,797 | module | module testbench;
parameter DATA_CASE_WIDTH = 8;
parameter DATA_BLOCK_WIDTH = 2;
wire [DATA_CASE_WIDTH-1:0] dout0_case;
wire [DATA_CASE_WIDTH-1:0] dout1_case;
wire [DATA_CASE_WIDTH-1:0] dout2_case;
wire [DATA_CASE_WIDTH-1:0] dout3_case;
wire [DATA_BLOCK_WIDTH-1:0] dout0_block;
wire [DATA_BLOCK_WIDTH-1:0] dout1_block;
wire [DATA_BLOCK_WIDTH-1:0] dout2_block;
wire [DATA_BLOCK_WIDTH-1:0] dout3_block;
reg [1:0] sel;
reg [DATA_CASE_WIDTH-1:0] din_case;
reg [DATA_BLOCK_WIDTH-1:0] din_block;
bn_demux_1_4_case #(DATA_CASE_WIDTH) bn_demux_1_4_case (.din(din_case), .sel(sel), .dout0(dout0_case), .dout1(dout1_case), .dout2(dout2_case), .dout3(dout3_case));
b2_demux_1_4_block b2_demux_1_4_block (.din(din_block), .sel(sel), .dout0(dout0_block), .dout1(dout1_block), .dout2(dout2_block), .dout3(dout3_block));
initial
begin
din_case=8'b11111111;
din_block=din_case;
#5;
sel = 2'b00;
#10;
sel = 2'b01;
#10
sel = 2'b10;
#10;
sel = 2'b11;
#10;
din_case=8'b10101010;
din_block=din_case;
#10;
din_case=8'b01010101;
din_block=din_case;
#10;
end
initial
$monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b",
sel, din_case, din_block, dout0_case, dout1_case, dout2_case, dout3_case, dout0_block, dout1_block, dout2_block, dout3_block);
initial
$dumpvars;
endmodule | module testbench; |
parameter DATA_CASE_WIDTH = 8;
parameter DATA_BLOCK_WIDTH = 2;
wire [DATA_CASE_WIDTH-1:0] dout0_case;
wire [DATA_CASE_WIDTH-1:0] dout1_case;
wire [DATA_CASE_WIDTH-1:0] dout2_case;
wire [DATA_CASE_WIDTH-1:0] dout3_case;
wire [DATA_BLOCK_WIDTH-1:0] dout0_block;
wire [DATA_BLOCK_WIDTH-1:0] dout1_block;
wire [DATA_BLOCK_WIDTH-1:0] dout2_block;
wire [DATA_BLOCK_WIDTH-1:0] dout3_block;
reg [1:0] sel;
reg [DATA_CASE_WIDTH-1:0] din_case;
reg [DATA_BLOCK_WIDTH-1:0] din_block;
bn_demux_1_4_case #(DATA_CASE_WIDTH) bn_demux_1_4_case (.din(din_case), .sel(sel), .dout0(dout0_case), .dout1(dout1_case), .dout2(dout2_case), .dout3(dout3_case));
b2_demux_1_4_block b2_demux_1_4_block (.din(din_block), .sel(sel), .dout0(dout0_block), .dout1(dout1_block), .dout2(dout2_block), .dout3(dout3_block));
initial
begin
din_case=8'b11111111;
din_block=din_case;
#5;
sel = 2'b00;
#10;
sel = 2'b01;
#10
sel = 2'b10;
#10;
sel = 2'b11;
#10;
din_case=8'b10101010;
din_block=din_case;
#10;
din_case=8'b01010101;
din_block=din_case;
#10;
end
initial
$monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b",
sel, din_case, din_block, dout0_case, dout1_case, dout2_case, dout3_case, dout0_block, dout1_block, dout2_block, dout3_block);
initial
$dumpvars;
endmodule | 16 |
4,517 | data/full_repos/permissive/110151336/lab_04/src/6_lab4_hdl_nbit_8in1_selector/lab4.v | 110,151,336 | lab4.v | v | 43 | 102 | [] | [] | [] | [(1, 29), (31, 43)] | null | data/verilator_xmls/08b4fca5-1df5-4b4e-8dcd-120a9f5c56e7.xml | null | 2,798 | module | module bn_select_8_1_case
#(parameter DATA_WIDTH=8)
(
input [DATA_WIDTH-1:0] d0,
input [DATA_WIDTH-1:0] d1,
input [DATA_WIDTH-1:0] d2,
input [DATA_WIDTH-1:0] d3,
input [DATA_WIDTH-1:0] d4,
input [DATA_WIDTH-1:0] d5,
input [DATA_WIDTH-1:0] d6,
input [DATA_WIDTH-1:0] d7,
input [7:0] sel,
output reg [DATA_WIDTH-1:0] y
);
always @(*)
case (sel)
8'b00000001: y=d0;
8'b00000010: y=d1;
8'b00000100: y=d2;
8'b00001000: y=d3;
8'b00010000: y=d4;
8'b00100000: y=d5;
8'b01000000: y=d6;
8'b10000000: y=d7;
default: y={DATA_WIDTH{1'bz}};
endcase
endmodule | module bn_select_8_1_case
#(parameter DATA_WIDTH=8)
(
input [DATA_WIDTH-1:0] d0,
input [DATA_WIDTH-1:0] d1,
input [DATA_WIDTH-1:0] d2,
input [DATA_WIDTH-1:0] d3,
input [DATA_WIDTH-1:0] d4,
input [DATA_WIDTH-1:0] d5,
input [DATA_WIDTH-1:0] d6,
input [DATA_WIDTH-1:0] d7,
input [7:0] sel,
output reg [DATA_WIDTH-1:0] y
); |
always @(*)
case (sel)
8'b00000001: y=d0;
8'b00000010: y=d1;
8'b00000100: y=d2;
8'b00001000: y=d3;
8'b00010000: y=d4;
8'b00100000: y=d5;
8'b01000000: y=d6;
8'b10000000: y=d7;
default: y={DATA_WIDTH{1'bz}};
endcase
endmodule | 16 |
4,518 | data/full_repos/permissive/110151336/lab_04/src/6_lab4_hdl_nbit_8in1_selector/lab4.v | 110,151,336 | lab4.v | v | 43 | 102 | [] | [] | [] | [(1, 29), (31, 43)] | null | data/verilator_xmls/08b4fca5-1df5-4b4e-8dcd-120a9f5c56e7.xml | null | 2,798 | module | module lab4
(
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
);
bn_select_8_1_case #(3) bn_select_8_1_case (.d0(SW[2:0]), .d1(SW[3:1]), .d2(SW[4:2]),
.d3(SW[5:3]), .d4(SW[6:4]), .d5(SW[7:5]),
.d6(SW[8:6]), .d7(SW[9:7]), .sel(SW[7:0]), .y(LEDR[2:0]));
endmodule | module lab4
(
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR
); |
bn_select_8_1_case #(3) bn_select_8_1_case (.d0(SW[2:0]), .d1(SW[3:1]), .d2(SW[4:2]),
.d3(SW[5:3]), .d4(SW[6:4]), .d5(SW[7:5]),
.d6(SW[8:6]), .d7(SW[9:7]), .sel(SW[7:0]), .y(LEDR[2:0]));
endmodule | 16 |
4,522 | data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v | 110,151,336 | testbench.v | v | 55 | 136 | [] | [] | [] | null | line:35: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:49: Unsupported or unknown PLI call: $monitor\n $monitor("sel=%b sel2=%b d0=%d d1=%d d2=%d d3=%d d4=%d d5=%d d6=%d d7=%d y=%d y2=%d", \n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_04/src/7_lab4_hdl_Nbit_Nin1_mux/simulation/testbench.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars; \n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,801 | module | module testbench;
parameter DATA_WIDTH = 8;
parameter SEL_WIDTH = 3;
parameter INPUT_CHANNELS = 8;
wire [DATA_WIDTH-1:0] y;
wire [DATA_WIDTH-1:0] y2;
reg [SEL_WIDTH-1:0] sel;
reg [INPUT_CHANNELS-1:0] sel2;
reg [DATA_WIDTH-1:0] d0;
reg [DATA_WIDTH-1:0] d1;
reg [DATA_WIDTH-1:0] d2;
reg [DATA_WIDTH-1:0] d3;
reg [DATA_WIDTH-1:0] d4;
reg [DATA_WIDTH-1:0] d5;
reg [DATA_WIDTH-1:0] d6;
reg [DATA_WIDTH-1:0] d7;
bn_mux_n_1_generate #(DATA_WIDTH,SEL_WIDTH) bn_mux_n_1_generate (.data({d7,d6,d5,d4,d3,d2,d1,d0}), .sel(sel), .y(y));
bn_selector_n_1_generate #(DATA_WIDTH,INPUT_CHANNELS) bn_selector_n_1_generate (.data({d7,d6,d5,d4,d3,d2,d1,d0}), .sel(sel2), .y(y2));
initial
begin
d0=0; d1=1; d2=2; d3=3; d4=4; d5=5; d6=6; d7=7;
#5;
sel = 0;
sel2 = 8'b00000001;
#10;
repeat (2**SEL_WIDTH-1)
begin
sel=sel+1;
sel2=sel2<<1;
#10;
end
d7=123;
#10;
d7=77;
#10;
end
initial
$monitor("sel=%b sel2=%b d0=%d d1=%d d2=%d d3=%d d4=%d d5=%d d6=%d d7=%d y=%d y2=%d",
sel, sel2, d0, d1, d2, d3, d4, d5, d6, d7, y, y2);
initial
$dumpvars;
endmodule | module testbench; |
parameter DATA_WIDTH = 8;
parameter SEL_WIDTH = 3;
parameter INPUT_CHANNELS = 8;
wire [DATA_WIDTH-1:0] y;
wire [DATA_WIDTH-1:0] y2;
reg [SEL_WIDTH-1:0] sel;
reg [INPUT_CHANNELS-1:0] sel2;
reg [DATA_WIDTH-1:0] d0;
reg [DATA_WIDTH-1:0] d1;
reg [DATA_WIDTH-1:0] d2;
reg [DATA_WIDTH-1:0] d3;
reg [DATA_WIDTH-1:0] d4;
reg [DATA_WIDTH-1:0] d5;
reg [DATA_WIDTH-1:0] d6;
reg [DATA_WIDTH-1:0] d7;
bn_mux_n_1_generate #(DATA_WIDTH,SEL_WIDTH) bn_mux_n_1_generate (.data({d7,d6,d5,d4,d3,d2,d1,d0}), .sel(sel), .y(y));
bn_selector_n_1_generate #(DATA_WIDTH,INPUT_CHANNELS) bn_selector_n_1_generate (.data({d7,d6,d5,d4,d3,d2,d1,d0}), .sel(sel2), .y(y2));
initial
begin
d0=0; d1=1; d2=2; d3=3; d4=4; d5=5; d6=6; d7=7;
#5;
sel = 0;
sel2 = 8'b00000001;
#10;
repeat (2**SEL_WIDTH-1)
begin
sel=sel+1;
sel2=sel2<<1;
#10;
end
d7=123;
#10;
d7=77;
#10;
end
initial
$monitor("sel=%b sel2=%b d0=%d d1=%d d2=%d d3=%d d4=%d d5=%d d6=%d d7=%d y=%d y2=%d",
sel, sel2, d0, d1, d2, d3, d4, d5, d6, d7, y, y2);
initial
$dumpvars;
endmodule | 16 |
4,523 | data/full_repos/permissive/110151336/lab_05/src/01_adder/lab5.v | 110,151,336 | lab5.v | v | 21 | 46 | [] | [] | [] | [(1, 21)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/lab5.v:10: Cannot find file containing module: 'adder'\n adder #(.WIDTH(WIDTH)) i_adder\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/01_adder,data/full_repos/permissive/110151336/adder\n data/full_repos/permissive/110151336/lab_05/src/01_adder,data/full_repos/permissive/110151336/adder.v\n data/full_repos/permissive/110151336/lab_05/src/01_adder,data/full_repos/permissive/110151336/adder.sv\n adder\n adder.v\n adder.sv\n obj_dir/adder\n obj_dir/adder.v\n obj_dir/adder.sv\n%Error: Exiting due to 1 error(s)\n" | 2,802 | module | module lab5
(
input [9:0] SW,
output [9:0] LEDR
);
parameter WIDTH = 2;
adder #(.WIDTH(WIDTH)) i_adder
(
.carry_in (SW [0] ),
.x (SW [WIDTH:1] ),
.y (SW [2 * WIDTH:WIDTH + 1]),
.z (LEDR[2 * WIDTH - 1:0] ),
.carry_out(LEDR[9] )
);
assign LEDR[8:2 * WIDTH] = 0;
endmodule | module lab5
(
input [9:0] SW,
output [9:0] LEDR
); |
parameter WIDTH = 2;
adder #(.WIDTH(WIDTH)) i_adder
(
.carry_in (SW [0] ),
.x (SW [WIDTH:1] ),
.y (SW [2 * WIDTH:WIDTH + 1]),
.z (LEDR[2 * WIDTH - 1:0] ),
.carry_out(LEDR[9] )
);
assign LEDR[8:2 * WIDTH] = 0;
endmodule | 16 |
4,525 | data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v | 110,151,336 | testbench.v | v | 59 | 72 | [] | [] | [] | null | line:27: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #8\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:33: Unsupported or unknown PLI call: $urandom_range\n x = $urandom_range(0, 2 ** WIDTH - 1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:34: Unsupported or unknown PLI call: $urandom_range\n y = $urandom_range(0, 2 ** WIDTH - 1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:36: Unsupported or unknown PLI call: $urandom_range\n c_in = $urandom_range(0, 1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:42: Unsupported or unknown PLI call: $monitor\n $monitor("Time:\\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:54: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:55: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1); \n ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,804 | module | module testbench;
parameter WIDTH = 8;
reg c_in;
reg [WIDTH - 1:0] x, y;
wire [WIDTH - 1:0] z;
wire c_out;
adder #(.WIDTH(WIDTH)) adder_dut(
.carry_in (c_in ),
.x (x ),
.y (y ),
.z (z ),
.carry_out(c_out)
);
initial begin
x = 0;
y = 0;
c_in = 0;
#8
$stop;
end
initial
forever begin
#1;
x = $urandom_range(0, 2 ** WIDTH - 1);
y = $urandom_range(0, 2 ** WIDTH - 1);
c_in = $urandom_range(0, 1);
end
initial
$monitor("Time:\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",
$time,
x,
y,
c_in,
z,
c_out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | module testbench; |
parameter WIDTH = 8;
reg c_in;
reg [WIDTH - 1:0] x, y;
wire [WIDTH - 1:0] z;
wire c_out;
adder #(.WIDTH(WIDTH)) adder_dut(
.carry_in (c_in ),
.x (x ),
.y (y ),
.z (z ),
.carry_out(c_out)
);
initial begin
x = 0;
y = 0;
c_in = 0;
#8
$stop;
end
initial
forever begin
#1;
x = $urandom_range(0, 2 ** WIDTH - 1);
y = $urandom_range(0, 2 ** WIDTH - 1);
c_in = $urandom_range(0, 1);
end
initial
$monitor("Time:\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",
$time,
x,
y,
c_in,
z,
c_out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | 16 |
4,526 | data/full_repos/permissive/110151336/lab_05/src/02_adder_synchronized/common/register.v | 110,151,336 | register.v | v | 19 | 44 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/722f6514-58ad-4d2a-be65-3494bbea2949.xml | null | 2,807 | module | module register
# (
parameter WIDTH = 8
)
(
input clock,
input reset,
input load,
input [ WIDTH - 1:0 ] data_in,
output reg [ WIDTH - 1:0 ] data_out
);
always @ ( posedge clock, negedge reset )
if ( ~reset )
data_out <= { WIDTH { 1'b0 } };
else if ( load )
data_out <= data_in;
endmodule | module register
# (
parameter WIDTH = 8
)
(
input clock,
input reset,
input load,
input [ WIDTH - 1:0 ] data_in,
output reg [ WIDTH - 1:0 ] data_out
); |
always @ ( posedge clock, negedge reset )
if ( ~reset )
data_out <= { WIDTH { 1'b0 } };
else if ( load )
data_out <= data_in;
endmodule | 16 |
4,528 | data/full_repos/permissive/110151336/lab_05/src/03_comparator/lab5.v | 110,151,336 | lab5.v | v | 23 | 41 | [] | [] | [] | [(1, 23)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/03_comparator/lab5.v:9: Cannot find file containing module: 'comparator'\n comparator #(.WIDTH(4)) i_comparator\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/03_comparator,data/full_repos/permissive/110151336/comparator\n data/full_repos/permissive/110151336/lab_05/src/03_comparator,data/full_repos/permissive/110151336/comparator.v\n data/full_repos/permissive/110151336/lab_05/src/03_comparator,data/full_repos/permissive/110151336/comparator.sv\n comparator\n comparator.v\n comparator.sv\n obj_dir/comparator\n obj_dir/comparator.v\n obj_dir/comparator.sv\n%Error: Exiting due to 1 error(s)\n" | 2,809 | module | module lab5
(
input [1:0] KEY,
input [9:0] SW,
output [9:0] LEDR
);
comparator #(.WIDTH(4)) i_comparator
(
.x (SW [3:0]),
.y (SW [7:4]),
.eq (LEDR[0] ),
.neq(LEDR[1] ),
.lt (LEDR[2] ),
.lte(LEDR[3] ),
.gt (LEDR[4] ),
.gte(LEDR[5] )
);
assign LEDR[9:6] = 0;
endmodule | module lab5
(
input [1:0] KEY,
input [9:0] SW,
output [9:0] LEDR
); |
comparator #(.WIDTH(4)) i_comparator
(
.x (SW [3:0]),
.y (SW [7:4]),
.eq (LEDR[0] ),
.neq(LEDR[1] ),
.lt (LEDR[2] ),
.lte(LEDR[3] ),
.gt (LEDR[4] ),
.gte(LEDR[5] )
);
assign LEDR[9:6] = 0;
endmodule | 16 |
4,534 | data/full_repos/permissive/110151336/lab_05/src/05_rotators/lab5.v | 110,151,336 | lab5.v | v | 24 | 47 | [] | [] | [] | [(1, 24)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/lab5.v:8: Cannot find file containing module: 'left_rotator'\n left_rotator #(.WIDTH(4)) i_left_rotator\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/05_rotators,data/full_repos/permissive/110151336/left_rotator\n data/full_repos/permissive/110151336/lab_05/src/05_rotators,data/full_repos/permissive/110151336/left_rotator.v\n data/full_repos/permissive/110151336/lab_05/src/05_rotators,data/full_repos/permissive/110151336/left_rotator.sv\n left_rotator\n left_rotator.v\n left_rotator.sv\n obj_dir/left_rotator\n obj_dir/left_rotator.v\n obj_dir/left_rotator.sv\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/lab5.v:16: Cannot find file containing module: 'right_rotator'\n right_rotator #(.WIDTH(4)) i_right_rotator\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,816 | module | module lab5
(
input [9:0] SW,
output [9:0] LEDR
);
left_rotator #(.WIDTH(4)) i_left_rotator
(
.x (SW [3:0]),
.shamt(SW [9:8]),
.z (LEDR[3:0])
);
right_rotator #(.WIDTH(4)) i_right_rotator
(
.x (SW [7:4]),
.shamt(SW [9:8]),
.z (LEDR[9:6])
);
assign LEDR[5:4] = 0;
endmodule | module lab5
(
input [9:0] SW,
output [9:0] LEDR
); |
left_rotator #(.WIDTH(4)) i_left_rotator
(
.x (SW [3:0]),
.shamt(SW [9:8]),
.z (LEDR[3:0])
);
right_rotator #(.WIDTH(4)) i_right_rotator
(
.x (SW [7:4]),
.shamt(SW [9:8]),
.z (LEDR[9:6])
);
assign LEDR[5:4] = 0;
endmodule | 16 |
4,535 | data/full_repos/permissive/110151336/lab_05/src/05_rotators/common/right_rotator.v | 110,151,336 | right_rotator.v | v | 15 | 80 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/f13d10f3-7306-45c2-b0dc-35bf1f68e869.xml | null | 2,818 | module | module right_rotator
#(
parameter WIDTH = 8,
parameter SHIFT = 3
)
(
input [WIDTH - 1:0] x,
input [SHIFT - 1:0] shamt,
output [WIDTH - 1:0] z
);
wire [2 * WIDTH - 1:0] temp;
assign temp = {x, x} >> shamt;
assign z = temp[WIDTH - 1: 0];
endmodule | module right_rotator
#(
parameter WIDTH = 8,
parameter SHIFT = 3
)
(
input [WIDTH - 1:0] x,
input [SHIFT - 1:0] shamt,
output [WIDTH - 1:0] z
); |
wire [2 * WIDTH - 1:0] temp;
assign temp = {x, x} >> shamt;
assign z = temp[WIDTH - 1: 0];
endmodule | 16 |
4,536 | data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v | 110,151,336 | testbench.v | v | 72 | 72 | [] | [] | [] | null | line:43: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #8\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:49: Unsupported or unknown PLI call: $urandom_range\n x = $urandom_range(0, 2 ** WIDTH - 1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:50: Unsupported or unknown PLI call: $urandom_range\n shamt = $urandom_range(0, 2 ** SHIFT - 1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:56: Unsupported or unknown PLI call: $monitor\n $monitor("Time:\\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:67: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:68: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1); \n ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,819 | module | module testbench;
parameter WIDTH = 8;
parameter SHIFT = 3;
reg [WIDTH - 1:0] x;
reg [SHIFT - 1:0] shamt;
wire [WIDTH - 1:0] lr_out;
wire [WIDTH - 1:0] rr_out;
left_rotator
#(
.WIDTH(WIDTH),
.SHIFT(SHIFT)
)
left_rotator_dut
(
.x (x ),
.shamt(shamt ),
.z (lr_out)
);
right_rotator
#(
.WIDTH(WIDTH),
.SHIFT(SHIFT)
)
right_rotator_dut
(
.x (x ),
.shamt(shamt ),
.z (rr_out)
);
initial begin
x = 0;
shamt = 0;
#8
$stop;
end
initial
forever begin
#1;
x = $urandom_range(0, 2 ** WIDTH - 1);
shamt = $urandom_range(0, 2 ** SHIFT - 1);
end
initial
$monitor("Time:\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",
$time,
x,
shamt,
lr_out,
rr_out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | module testbench; |
parameter WIDTH = 8;
parameter SHIFT = 3;
reg [WIDTH - 1:0] x;
reg [SHIFT - 1:0] shamt;
wire [WIDTH - 1:0] lr_out;
wire [WIDTH - 1:0] rr_out;
left_rotator
#(
.WIDTH(WIDTH),
.SHIFT(SHIFT)
)
left_rotator_dut
(
.x (x ),
.shamt(shamt ),
.z (lr_out)
);
right_rotator
#(
.WIDTH(WIDTH),
.SHIFT(SHIFT)
)
right_rotator_dut
(
.x (x ),
.shamt(shamt ),
.z (rr_out)
);
initial begin
x = 0;
shamt = 0;
#8
$stop;
end
initial
forever begin
#1;
x = $urandom_range(0, 2 ** WIDTH - 1);
shamt = $urandom_range(0, 2 ** SHIFT - 1);
end
initial
$monitor("Time:\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",
$time,
x,
shamt,
lr_out,
rr_out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | 16 |
4,537 | data/full_repos/permissive/110151336/lab_05/src/06_alu/lab5.v | 110,151,336 | lab5.v | v | 58 | 52 | [] | [] | [] | [(1, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/06_alu/lab5.v:18: Cannot find file containing module: 'register'\n register #(.WIDTH(4)) x_register\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/06_alu,data/full_repos/permissive/110151336/register\n data/full_repos/permissive/110151336/lab_05/src/06_alu,data/full_repos/permissive/110151336/register.v\n data/full_repos/permissive/110151336/lab_05/src/06_alu,data/full_repos/permissive/110151336/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/110151336/lab_05/src/06_alu/lab5.v:27: Cannot find file containing module: 'register'\n register #(.WIDTH(4)) y_register\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/06_alu/lab5.v:41: Cannot find file containing module: 'alu'\n alu\n ^~~\n%Error: Exiting due to 3 error(s)\n" | 2,820 | module | module lab5
(
input MAX10_CLK1_50,
input [1:0] KEY,
input [9:0] SW,
output [9:0] LEDR
);
wire [3:0] x_bus, y_bus;
wire load_x, load_y;
wire clock;
wire reset;
assign clock = MAX10_CLK1_50;
assign reset = KEY[1];
register #(.WIDTH(4)) x_register
(
.clock (clock ),
.reset (reset ),
.load (load_x ),
.data_in (SW[4:1]),
.data_out(x_bus )
);
register #(.WIDTH(4)) y_register
(
.clock (clock ),
.reset (reset ),
.load (load_y ),
.data_in (SW[4:1]),
.data_out(y_bus )
);
assign load_x = SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
assign load_y = ~SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
alu
#(
.WIDTH(4),
.SHIFT(2)
)
i_alu
(
.x ( x_bus ),
.y ( y_bus ),
.shamt ( SW[6:5] ),
.operation( SW[9:8] ),
.zero ( LEDR[9] ),
.result ( LEDR[3:0] )
);
assign LEDR[8:4] = 0;
endmodule | module lab5
(
input MAX10_CLK1_50,
input [1:0] KEY,
input [9:0] SW,
output [9:0] LEDR
); |
wire [3:0] x_bus, y_bus;
wire load_x, load_y;
wire clock;
wire reset;
assign clock = MAX10_CLK1_50;
assign reset = KEY[1];
register #(.WIDTH(4)) x_register
(
.clock (clock ),
.reset (reset ),
.load (load_x ),
.data_in (SW[4:1]),
.data_out(x_bus )
);
register #(.WIDTH(4)) y_register
(
.clock (clock ),
.reset (reset ),
.load (load_y ),
.data_in (SW[4:1]),
.data_out(y_bus )
);
assign load_x = SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
assign load_y = ~SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
alu
#(
.WIDTH(4),
.SHIFT(2)
)
i_alu
(
.x ( x_bus ),
.y ( y_bus ),
.shamt ( SW[6:5] ),
.operation( SW[9:8] ),
.zero ( LEDR[9] ),
.result ( LEDR[3:0] )
);
assign LEDR[8:4] = 0;
endmodule | 16 |
4,538 | data/full_repos/permissive/110151336/lab_05/src/06_alu/common/alu.v | 110,151,336 | alu.v | v | 32 | 49 | [] | [] | [] | [(7, 32)] | null | data/verilator_xmls/a111c935-462f-4c85-855f-2296c62b66ff.xml | null | 2,821 | module | module alu
#(
parameter WIDTH = 4,
parameter SHIFT = 2
)
(
input [WIDTH - 1:0] x, y,
input [SHIFT - 1:0] shamt,
input [ 1:0] operation,
output zero,
output reg [WIDTH - 1:0] result
);
always @ (*) begin
case (operation)
`ALU_AND : result = x & y;
`ALU_ADD : result = x + y;
`ALU_SLL : result = y << shamt;
`ALU_SLT : result = (x < y) ? 1 : 0;
endcase
end
assign zero = (result == 0);
endmodule | module alu
#(
parameter WIDTH = 4,
parameter SHIFT = 2
)
(
input [WIDTH - 1:0] x, y,
input [SHIFT - 1:0] shamt,
input [ 1:0] operation,
output zero,
output reg [WIDTH - 1:0] result
); |
always @ (*) begin
case (operation)
`ALU_AND : result = x & y;
`ALU_ADD : result = x + y;
`ALU_SLL : result = y << shamt;
`ALU_SLT : result = (x < y) ? 1 : 0;
endcase
end
assign zero = (result == 0);
endmodule | 16 |
4,540 | data/full_repos/permissive/110151336/lab_05/src/07_alu_structural/common/bn_mux_n_1_generate.v | 110,151,336 | bn_mux_n_1_generate.v | v | 19 | 74 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/d083a74e-ecf5-4628-b110-d233ba3a6fe9.xml | null | 2,828 | module | module bn_mux_n_1_generate
#( parameter DATA_WIDTH = 8,
parameter SEL_WIDTH = 2)
(
input [((2**SEL_WIDTH)*DATA_WIDTH)-1:0] data,
input [SEL_WIDTH-1:0] sel,
output [DATA_WIDTH-1:0] y
);
wire [DATA_WIDTH-1:0] tmp_array [0:(2**SEL_WIDTH)-1];
genvar i;
generate
for(i=0; i<2**SEL_WIDTH; i=i+1)
begin: gen_array
assign tmp_array[i] = data[((i+1)*DATA_WIDTH)-1:(i*DATA_WIDTH)];
end
endgenerate
assign y = tmp_array[sel];
endmodule | module bn_mux_n_1_generate
#( parameter DATA_WIDTH = 8,
parameter SEL_WIDTH = 2)
(
input [((2**SEL_WIDTH)*DATA_WIDTH)-1:0] data,
input [SEL_WIDTH-1:0] sel,
output [DATA_WIDTH-1:0] y
); |
wire [DATA_WIDTH-1:0] tmp_array [0:(2**SEL_WIDTH)-1];
genvar i;
generate
for(i=0; i<2**SEL_WIDTH; i=i+1)
begin: gen_array
assign tmp_array[i] = data[((i+1)*DATA_WIDTH)-1:(i*DATA_WIDTH)];
end
endgenerate
assign y = tmp_array[sel];
endmodule | 16 |
4,541 | data/full_repos/permissive/110151336/lab_05/src/07_alu_structural/common/slt.v | 110,151,336 | slt.v | v | 10 | 32 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/5ddcec64-d869-4b44-a2e9-07e039b2c39f.xml | null | 2,831 | module | module slt
#(
parameter WIDTH = 8
)
(
input [WIDTH - 1:0] x,y,
output [WIDTH - 1:0] z
);
assign z = (x < y) ? 1 : 0;
endmodule | module slt
#(
parameter WIDTH = 8
)
(
input [WIDTH - 1:0] x,y,
output [WIDTH - 1:0] z
); |
assign z = (x < y) ? 1 : 0;
endmodule | 16 |
4,543 | data/full_repos/permissive/110151336/lab_05/src/08_half_adder/lab5.v | 110,151,336 | lab5.v | v | 26 | 50 | [] | [] | [] | [(1, 25)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/lab5.v:7: Cannot find file containing module: 'half_adder'\n half_adder i_half_adder_behavioral\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/08_half_adder,data/full_repos/permissive/110151336/half_adder\n data/full_repos/permissive/110151336/lab_05/src/08_half_adder,data/full_repos/permissive/110151336/half_adder.v\n data/full_repos/permissive/110151336/lab_05/src/08_half_adder,data/full_repos/permissive/110151336/half_adder.sv\n half_adder\n half_adder.v\n half_adder.sv\n obj_dir/half_adder\n obj_dir/half_adder.v\n obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/lab5.v:15: Cannot find file containing module: 'half_adder_structural'\n half_adder_structural i_half_adder_structural\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,833 | module | module lab5
(
input [9:0] SW,
output [9:0] LEDR
);
half_adder i_half_adder_behavioral
(
.x (SW[0] ),
.y (SW[1] ),
.z (LEDR[0]),
.carry_out(LEDR[1])
);
half_adder_structural i_half_adder_structural
(
.x ( SW[2] ),
.y ( SW[3] ),
.z ( LEDR[2]),
.carry_out( LEDR[3])
);
assign LEDR[9:4] = 0;
endmodule | module lab5
(
input [9:0] SW,
output [9:0] LEDR
); |
half_adder i_half_adder_behavioral
(
.x (SW[0] ),
.y (SW[1] ),
.z (LEDR[0]),
.carry_out(LEDR[1])
);
half_adder_structural i_half_adder_structural
(
.x ( SW[2] ),
.y ( SW[3] ),
.z ( LEDR[2]),
.carry_out( LEDR[3])
);
assign LEDR[9:4] = 0;
endmodule | 16 |
4,544 | data/full_repos/permissive/110151336/lab_05/src/08_half_adder/common/half_adder.v | 110,151,336 | half_adder.v | v | 8 | 32 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/3e584ecd-be95-4fbe-b520-5ee6a915e932.xml | null | 2,834 | module | module half_adder
(
input wire x, y,
output wire z,
output wire carry_out
);
assign {carry_out, z} = x + y;
endmodule | module half_adder
(
input wire x, y,
output wire z,
output wire carry_out
); |
assign {carry_out, z} = x + y;
endmodule | 16 |
4,546 | data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v | 110,151,336 | testbench.v | v | 66 | 88 | [] | [] | [] | null | line:30: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v:48: Unsupported or unknown PLI call: $monitor\n $monitor("Time:\\t%g, x: %b, y: %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v:61: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/08_half_adder/simulation/testbench.v:62: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1); \n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,836 | module | module testbench;
reg x, y;
wire z_behavioral, z_structural;
wire c_out_behavioral, c_out_structural;
half_adder half_adder_behavioral_dut(
.x ( x ),
.y ( y ),
.z ( z_behavioral ),
.carry_out( c_out_behavioral )
);
half_adder_structural half_adder_structural_dut(
.x ( x ),
.y ( y ),
.z ( z_structural ),
.carry_out( c_out_structural )
);
initial begin
x = 2'b00;
y = 2'b00;
#4
$stop;
end
initial
forever begin
#1;
if( x == 1'b1 ) begin
x = 1'b0;
y = y + 1;
end
else begin
x = x + 1;
end
end
initial
$monitor("Time:\t%g, x: %b, y: %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
$time,
x,
y,
z_behavioral,
z_structural,
c_out_behavioral,
c_out_structural
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | module testbench; |
reg x, y;
wire z_behavioral, z_structural;
wire c_out_behavioral, c_out_structural;
half_adder half_adder_behavioral_dut(
.x ( x ),
.y ( y ),
.z ( z_behavioral ),
.carry_out( c_out_behavioral )
);
half_adder_structural half_adder_structural_dut(
.x ( x ),
.y ( y ),
.z ( z_structural ),
.carry_out( c_out_structural )
);
initial begin
x = 2'b00;
y = 2'b00;
#4
$stop;
end
initial
forever begin
#1;
if( x == 1'b1 ) begin
x = 1'b0;
y = y + 1;
end
else begin
x = x + 1;
end
end
initial
$monitor("Time:\t%g, x: %b, y: %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
$time,
x,
y,
z_behavioral,
z_structural,
c_out_behavioral,
c_out_structural
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | 16 |
4,548 | data/full_repos/permissive/110151336/lab_05/src/09_full_adder/common/full_adder.v | 110,151,336 | full_adder.v | v | 7 | 46 | [] | [] | [] | [(1, 7)] | null | data/verilator_xmls/173ca92a-53dd-45b9-9b88-1cb8d10fbca4.xml | null | 2,838 | module | module full_adder
(
input wire x, y, carry_in,
output wire z, carry_out
);
assign {carry_out, z} = x + y + carry_in;
endmodule | module full_adder
(
input wire x, y, carry_in,
output wire z, carry_out
); |
assign {carry_out, z} = x + y + carry_in;
endmodule | 16 |
4,549 | data/full_repos/permissive/110151336/lab_05/src/09_full_adder/common/full_adder_structural.v | 110,151,336 | full_adder_structural.v | v | 15 | 32 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/404f5445-1820-4d67-b541-16dec7a26261.xml | null | 2,839 | module | module full_adder_structural
(
input wire x, y, carry_in,
output wire z, carry_out
);
wire [2:0] t;
xor(t[0], x, y);
xor(z, t[0], carry_in);
and(t[1], x, y);
and(t[2], t[0], carry_in);
or (carry_out, t[1], t[2]);
endmodule | module full_adder_structural
(
input wire x, y, carry_in,
output wire z, carry_out
); |
wire [2:0] t;
xor(t[0], x, y);
xor(z, t[0], carry_in);
and(t[1], x, y);
and(t[2], t[0], carry_in);
or (carry_out, t[1], t[2]);
endmodule | 16 |
4,550 | data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v | 110,151,336 | testbench.v | v | 76 | 97 | [] | [] | [] | null | line:34: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #8\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n #4 c_in = c_in + 1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:57: Unsupported or unknown PLI call: $monitor\n $monitor("Time:\\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:72: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1); \n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,840 | module | module testbench;
reg c_in;
reg x, y;
wire z_behavioral, z_structural;
wire c_out_behavioral, c_out_structural;
full_adder full_adder_behavioral_dut(
.carry_in ( c_in ),
.x ( x ),
.y ( y ),
.z ( z_behavioral ),
.carry_out( c_out_behavioral )
);
full_adder_structural full_adder_structural_dut(
.carry_in ( c_in ),
.x ( x ),
.y ( y ),
.z ( z_structural ),
.carry_out( c_out_structural )
);
initial begin
x = 1'b0;
y = 1'b0;
c_in = 1'b0;
#8
$stop;
end
initial
forever begin
#1;
if( x == 1'b1 ) begin
x = 1'b0;
y = y + 1;
end
else begin
x = x + 1;
end
end
initial
forever begin
#4 c_in = c_in + 1;
end
initial
$monitor("Time:\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
$time,
x,
y,
c_in,
z_behavioral,
z_structural,
c_out_behavioral,
c_out_structural
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | module testbench; |
reg c_in;
reg x, y;
wire z_behavioral, z_structural;
wire c_out_behavioral, c_out_structural;
full_adder full_adder_behavioral_dut(
.carry_in ( c_in ),
.x ( x ),
.y ( y ),
.z ( z_behavioral ),
.carry_out( c_out_behavioral )
);
full_adder_structural full_adder_structural_dut(
.carry_in ( c_in ),
.x ( x ),
.y ( y ),
.z ( z_structural ),
.carry_out( c_out_structural )
);
initial begin
x = 1'b0;
y = 1'b0;
c_in = 1'b0;
#8
$stop;
end
initial
forever begin
#1;
if( x == 1'b1 ) begin
x = 1'b0;
y = y + 1;
end
else begin
x = x + 1;
end
end
initial
forever begin
#4 c_in = c_in + 1;
end
initial
$monitor("Time:\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
$time,
x,
y,
c_in,
z_behavioral,
z_structural,
c_out_behavioral,
c_out_structural
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule | 16 |
4,552 | data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common/ripple_carry_adder.v | 110,151,336 | ripple_carry_adder.v | v | 36 | 47 | [] | [] | [] | [(1, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common/ripple_carry_adder.v:22: Cannot find file containing module: 'full_adder'\n full_adder FA\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder\n data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder.v\n data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder.sv\n full_adder\n full_adder.v\n full_adder.sv\n obj_dir/full_adder\n obj_dir/full_adder.v\n obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n" | 2,844 | module | module ripple_carry_adder
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] x,
input [WIDTH - 1 : 0] y,
output [WIDTH - 1 : 0] z,
output carry_out
);
wire [WIDTH : 0] carry;
assign carry[0] = carry_in;
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
full_adder FA
(
.x (x [i] ),
.y (y [i] ),
.z (z [i] ),
.carry_in (carry[i] ),
.carry_out (carry[i + 1])
);
end
endgenerate
assign carry_out = carry[WIDTH];
endmodule | module ripple_carry_adder
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] x,
input [WIDTH - 1 : 0] y,
output [WIDTH - 1 : 0] z,
output carry_out
); |
wire [WIDTH : 0] carry;
assign carry[0] = carry_in;
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
full_adder FA
(
.x (x [i] ),
.y (y [i] ),
.z (z [i] ),
.carry_in (carry[i] ),
.carry_out (carry[i + 1])
);
end
endgenerate
assign carry_out = carry[WIDTH];
endmodule | 16 |
4,555 | data/full_repos/permissive/110151336/lab_05/src/12_carry_lookahead_adder/common/carry_lookahead_generator.v | 110,151,336 | carry_lookahead_generator.v | v | 23 | 79 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/aae497d9-7d18-4cf3-b209-6d7f81c5190e.xml | null | 2,855 | module | module carry_lookahead_generator
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] generate_in, propagate_in,
output [WIDTH : 0] carry
);
assign carry[0] = carry_in;
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign carry[i + 1] = generate_in[i] | propagate_in[i] & carry[i];
end
endgenerate
endmodule | module carry_lookahead_generator
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] generate_in, propagate_in,
output [WIDTH : 0] carry
); |
assign carry[0] = carry_in;
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign carry[i + 1] = generate_in[i] | propagate_in[i] & carry[i];
end
endgenerate
endmodule | 16 |
4,556 | data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common/carry_lookahead_adder.v | 110,151,336 | carry_lookahead_adder.v | v | 46 | 57 | [] | [] | [] | [(1, 45)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common/carry_lookahead_adder.v:19: Cannot find file containing module: 'carry_lookahead_generator'\n carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator\n data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator.v\n data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator.sv\n carry_lookahead_generator\n carry_lookahead_generator.v\n carry_lookahead_generator.sv\n obj_dir/carry_lookahead_generator\n obj_dir/carry_lookahead_generator.v\n obj_dir/carry_lookahead_generator.sv\n%Error: Exiting due to 1 error(s)\n" | 2,860 | module | module carry_lookahead_adder
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] x,
input [WIDTH - 1 : 0] y,
output [WIDTH - 1 : 0] z,
output carry_out,
output group_generate,
output group_propagate
);
wire [WIDTH : 0] carry;
wire [WIDTH - 1 : 0] generate_wire, propagate_wire;
assign carry[0] = carry_in;
carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG
(
.carry_in (carry_in ),
.generate_in (generate_wire ),
.propagate_in (propagate_wire ),
.carry (carry[WIDTH : 1]),
.group_generate (group_generate ),
.group_propagate(group_propagate )
);
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign generate_wire [i] = x[i] & y[i];
assign propagate_wire[i] = x[i] ^ y[i];
assign z[i] = carry[i] ^ propagate_wire[i];
end
endgenerate
assign carry_out = carry[WIDTH];
endmodule | module carry_lookahead_adder
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] x,
input [WIDTH - 1 : 0] y,
output [WIDTH - 1 : 0] z,
output carry_out,
output group_generate,
output group_propagate
); |
wire [WIDTH : 0] carry;
wire [WIDTH - 1 : 0] generate_wire, propagate_wire;
assign carry[0] = carry_in;
carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG
(
.carry_in (carry_in ),
.generate_in (generate_wire ),
.propagate_in (propagate_wire ),
.carry (carry[WIDTH : 1]),
.group_generate (group_generate ),
.group_propagate(group_propagate )
);
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign generate_wire [i] = x[i] & y[i];
assign propagate_wire[i] = x[i] ^ y[i];
assign z[i] = carry[i] ^ propagate_wire[i];
end
endgenerate
assign carry_out = carry[WIDTH];
endmodule | 16 |
4,557 | data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common/carry_lookahead_generator.v | 110,151,336 | carry_lookahead_generator.v | v | 44 | 118 | [] | [] | [] | null | line:26: before: "case" | data/verilator_xmls/be924c11-7a4e-46a3-b4cc-5acee530fc79.xml | null | 2,861 | module | module carry_lookahead_generator
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] generate_in, propagate_in,
output [WIDTH : 1] carry,
output group_generate, group_propagate
);
wire [((WIDTH + 1) * WIDTH) / 2 - 1 : 0] p_temp, g_temp;
wire [WIDTH - 1 : 0] c_temp, pg_temp;
generate
genvar i, j;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
for (j = 0; j <= i; j = j + 1)
begin : block
assign p_temp[((i + 1) * i) / 2 + j] = & propagate_in[i : j];
case(j)
0 : assign g_temp[((i + 1) * i) / 2 + j] = generate_in[i];
default : assign g_temp[((i + 1) * i) / 2 + j] = p_temp[((i + 1) * i) / 2 + j] & generate_in[j - 1];
endcase
end
assign c_temp [i] = p_temp[((i + 1) * i) / 2] & carry_in;
assign pg_temp[i] = | g_temp[(( i + 2) * (i + 1)) / 2 - 1 : ((i + 1) * i) / 2];
assign carry [i + 1] = pg_temp[i] | c_temp[i];
end
endgenerate
assign group_propagate = p_temp [(WIDTH * (WIDTH - 1)) / 2];
assign group_generate = pg_temp[WIDTH - 1];
endmodule | module carry_lookahead_generator
# (
parameter WIDTH = 8
)
(
input carry_in,
input [WIDTH - 1 : 0] generate_in, propagate_in,
output [WIDTH : 1] carry,
output group_generate, group_propagate
); |
wire [((WIDTH + 1) * WIDTH) / 2 - 1 : 0] p_temp, g_temp;
wire [WIDTH - 1 : 0] c_temp, pg_temp;
generate
genvar i, j;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
for (j = 0; j <= i; j = j + 1)
begin : block
assign p_temp[((i + 1) * i) / 2 + j] = & propagate_in[i : j];
case(j)
0 : assign g_temp[((i + 1) * i) / 2 + j] = generate_in[i];
default : assign g_temp[((i + 1) * i) / 2 + j] = p_temp[((i + 1) * i) / 2 + j] & generate_in[j - 1];
endcase
end
assign c_temp [i] = p_temp[((i + 1) * i) / 2] & carry_in;
assign pg_temp[i] = | g_temp[(( i + 2) * (i + 1)) / 2 - 1 : ((i + 1) * i) / 2];
assign carry [i + 1] = pg_temp[i] | c_temp[i];
end
endgenerate
assign group_propagate = p_temp [(WIDTH * (WIDTH - 1)) / 2];
assign group_generate = pg_temp[WIDTH - 1];
endmodule | 16 |
4,560 | data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common/two_level_CLA.v | 110,151,336 | two_level_CLA.v | v | 56 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common/two_level_CLA.v:27: Cannot find file containing module: 'carry_lookahead_adder'\n carry_lookahead_adder #(.WIDTH(WIDTH_0)) i_CLA\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common,data/full_repos/permissive/110151336/carry_lookahead_adder\n data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common,data/full_repos/permissive/110151336/carry_lookahead_adder.v\n data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common,data/full_repos/permissive/110151336/carry_lookahead_adder.sv\n carry_lookahead_adder\n carry_lookahead_adder.v\n carry_lookahead_adder.sv\n obj_dir/carry_lookahead_adder\n obj_dir/carry_lookahead_adder.v\n obj_dir/carry_lookahead_adder.sv\n%Error: data/full_repos/permissive/110151336/lab_05/src/15_two_level_carry_lookahead_adder/common/two_level_CLA.v:41: Cannot find file containing module: 'carry_lookahead_generator'\n carry_lookahead_generator #(.WIDTH(WIDTH_1)) i_CLG\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 2,876 | module | module two_level_CLA
# (
parameter WIDTH_0 = 2,
parameter WIDTH_1 = 2,
parameter GROUP_COUNT = 2
)
(
input carry_in,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] x,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] y,
output [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] z,
output carry_out
);
wire [GROUP_COUNT * WIDTH_1 - 1 : 0] p_temp, g_temp;
wire [GROUP_COUNT * WIDTH_1 : 0] c_temp;
assign c_temp[0] = carry_in;
generate
genvar i;
genvar j;
for (i = 0; i <= GROUP_COUNT * WIDTH_1 - 1; i = i + 1)
begin : stage
carry_lookahead_adder #(.WIDTH(WIDTH_0)) i_CLA
(
.carry_in (c_temp[i] ),
.x (x[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.y (y[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.z (z[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.group_propagate(p_temp[i] ),
.group_generate (g_temp[i] ),
.carry_out ()
);
end
for (j = 0; j <= GROUP_COUNT - 1; j = j + 1)
begin : clg_stage
carry_lookahead_generator #(.WIDTH(WIDTH_1)) i_CLG
(
.carry_in (c_temp[WIDTH_1 * j] ),
.generate_in (g_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
.propagate_in (p_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
.carry (c_temp[WIDTH_1 * (j + 1) : WIDTH_1 * j + 1]),
.group_propagate(),
.group_generate ()
);
end
endgenerate
assign carry_out = c_temp[GROUP_COUNT * WIDTH_1];
endmodule | module two_level_CLA
# (
parameter WIDTH_0 = 2,
parameter WIDTH_1 = 2,
parameter GROUP_COUNT = 2
)
(
input carry_in,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] x,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] y,
output [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] z,
output carry_out
); |
wire [GROUP_COUNT * WIDTH_1 - 1 : 0] p_temp, g_temp;
wire [GROUP_COUNT * WIDTH_1 : 0] c_temp;
assign c_temp[0] = carry_in;
generate
genvar i;
genvar j;
for (i = 0; i <= GROUP_COUNT * WIDTH_1 - 1; i = i + 1)
begin : stage
carry_lookahead_adder #(.WIDTH(WIDTH_0)) i_CLA
(
.carry_in (c_temp[i] ),
.x (x[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.y (y[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.z (z[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
.group_propagate(p_temp[i] ),
.group_generate (g_temp[i] ),
.carry_out ()
);
end
for (j = 0; j <= GROUP_COUNT - 1; j = j + 1)
begin : clg_stage
carry_lookahead_generator #(.WIDTH(WIDTH_1)) i_CLG
(
.carry_in (c_temp[WIDTH_1 * j] ),
.generate_in (g_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
.propagate_in (p_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
.carry (c_temp[WIDTH_1 * (j + 1) : WIDTH_1 * j + 1]),
.group_propagate(),
.group_generate ()
);
end
endgenerate
assign carry_out = c_temp[GROUP_COUNT * WIDTH_1];
endmodule | 16 |
4,562 | data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common/prefix_adder.v | 110,151,336 | prefix_adder.v | v | 43 | 62 | [] | [] | [] | null | line:43: before: "THER" | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common/prefix_adder.v:17: Cannot find file containing module: 'prefix_carry_generator'\n prefix_carry_generator\n ^~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator\n data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator.v\n data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator.sv\n prefix_carry_generator\n prefix_carry_generator.v\n prefix_carry_generator.sv\n obj_dir/prefix_carry_generator\n obj_dir/prefix_carry_generator.v\n obj_dir/prefix_carry_generator.sv\n%Error: Exiting due to 1 error(s)\n" | 2,881 | module | module prefix_adder
# (
parameter LEVELS = 3,
parameter WIDTH = 2 ** LEVELS
)
(
input carry_in,
input [ WIDTH - 1 : 0 ] x,
input [ WIDTH - 1 : 0 ] y,
output [ WIDTH - 1 : 0 ] z,
output carry_out
);
wire [ WIDTH - 1 : 0 ] carry;
wire [ WIDTH - 1 : 0 ] generate_wire, propagate_wire;
prefix_carry_generator
# ( .LEVELS(LEVELS), .WIDTH(WIDTH) )
i_PCG
(
.carry_in ( carry_in ),
.generate_in ( generate_wire ),
.propagate_in( propagate_wire ),
.carry ( carry ),
.carry_out ( carry_out )
);
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign generate_wire [ i ] = x[ i ] & y[ i ];
assign propagate_wire[ i ] = x[ i ] ^ y[ i ];
assign z[ i ] = carry[ i ] ^ propagate_wire[ i ];
end
endgenerate
endmodule | module prefix_adder
# (
parameter LEVELS = 3,
parameter WIDTH = 2 ** LEVELS
)
(
input carry_in,
input [ WIDTH - 1 : 0 ] x,
input [ WIDTH - 1 : 0 ] y,
output [ WIDTH - 1 : 0 ] z,
output carry_out
); |
wire [ WIDTH - 1 : 0 ] carry;
wire [ WIDTH - 1 : 0 ] generate_wire, propagate_wire;
prefix_carry_generator
# ( .LEVELS(LEVELS), .WIDTH(WIDTH) )
i_PCG
(
.carry_in ( carry_in ),
.generate_in ( generate_wire ),
.propagate_in( propagate_wire ),
.carry ( carry ),
.carry_out ( carry_out )
);
generate
genvar i;
for (i = 0; i <= WIDTH - 1; i = i + 1)
begin : stage
assign generate_wire [ i ] = x[ i ] & y[ i ];
assign propagate_wire[ i ] = x[ i ] ^ y[ i ];
assign z[ i ] = carry[ i ] ^ propagate_wire[ i ];
end
endgenerate
endmodule | 16 |
4,564 | data/full_repos/permissive/110151336/lab_06/src/01_counter_simple/simple_counter.v | 110,151,336 | simple_counter.v | v | 25 | 41 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/077298fa-acf7-4834-94f3-2f0718f9cd31.xml | null | 2,886 | module | module simple_counter
#(
parameter WIDTH=8
)
(
input clk,
input rst_n,
output reg [WIDTH-1:0] cnt
);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= {WIDTH{1'b0}};
else
cnt <= cnt + 1'b1;
end
endmodule | module simple_counter
#(
parameter WIDTH=8
)
(
input clk,
input rst_n,
output reg [WIDTH-1:0] cnt
); |
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= {WIDTH{1'b0}};
else
cnt <= cnt + 1'b1;
end
endmodule | 16 |
4,565 | data/full_repos/permissive/110151336/lab_06/src/02_counter_with_load/cnt_load.v | 110,151,336 | cnt_load.v | v | 26 | 41 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/8f956c81-6eeb-4d9b-b070-ae841afb7d1a.xml | null | 2,889 | module | module cnt_load
#(
parameter WIDTH=16
)
(
input clk,
input rst_n,
input load,
input [WIDTH-1:0] data_load,
output reg [WIDTH-1:0] cnt
);
always@(posedge clk or negedge rst_n)
begin:cnt_with_load
if(!rst_n)
cnt <= {WIDTH{1'b0}};
else if(load)
cnt <= data_load;
else
cnt <= cnt + 1'b1;
end
endmodule | module cnt_load
#(
parameter WIDTH=16
)
(
input clk,
input rst_n,
input load,
input [WIDTH-1:0] data_load,
output reg [WIDTH-1:0] cnt
); |
always@(posedge clk or negedge rst_n)
begin:cnt_with_load
if(!rst_n)
cnt <= {WIDTH{1'b0}};
else if(load)
cnt <= data_load;
else
cnt <= cnt + 1'b1;
end
endmodule | 16 |
4,571 | data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v | 110,151,336 | shift_reg_tb.v | v | 78 | 81 | [] | [] | [] | null | line:39: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n forever #4 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:40: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:41: Unsupported or unknown PLI call: $urandom\n data_in = $urandom%2;\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 rst_n = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10 rst_n = 1\'b1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:61: Unsupported or unknown PLI call: $monitor\n $monitor("@time=%0t\\t data_out=0x%h\\t",$time,data_out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #50 push;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,902 | module | module shift_reg_tb;
localparam WIDTH=8;
reg clk;
reg rst_n;
reg shift_en;
reg data_in;
wire [7:0] data_out;
wire serial_out;
shift_reg #(.WIDTH(WIDTH)) shft
(
.data_out ( data_out ),
.serial_out ( serial_out ),
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in ),
.shift_en ( shift_en )
);
initial begin
clk = 0;
forever #4 clk = ~clk;
end
task push;
begin
$display("########## Shift enable active ##########");
shift_en = 1'b1;
repeat(9)begin
@(negedge clk)
data_in = $urandom%2;
end
shift_en = 1'b0;
$display("########## Shift enable disable ##########\n");
end
endtask
task async_rst;
begin
$display("########## RESET start! ##########");
#10 rst_n = 1'b0;
#10 rst_n = 1'b1;
$display("########## RESET finish!\n ##########");
end
endtask
initial begin
$dumpvars();
$display("#################### Starting simulation ####################");
$monitor("@time=%0t\t data_out=0x%h\t",$time,data_out);
shift_en = 1'b0;
rst_n = 1'b1;
data_in = 1'b0;
async_rst();
repeat(10) begin
#50 push;
end
#200 $finish;
end
endmodule | module shift_reg_tb; |
localparam WIDTH=8;
reg clk;
reg rst_n;
reg shift_en;
reg data_in;
wire [7:0] data_out;
wire serial_out;
shift_reg #(.WIDTH(WIDTH)) shft
(
.data_out ( data_out ),
.serial_out ( serial_out ),
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in ),
.shift_en ( shift_en )
);
initial begin
clk = 0;
forever #4 clk = ~clk;
end
task push;
begin
$display("########## Shift enable active ##########");
shift_en = 1'b1;
repeat(9)begin
@(negedge clk)
data_in = $urandom%2;
end
shift_en = 1'b0;
$display("########## Shift enable disable ##########\n");
end
endtask
task async_rst;
begin
$display("########## RESET start! ##########");
#10 rst_n = 1'b0;
#10 rst_n = 1'b1;
$display("########## RESET finish!\n ##########");
end
endtask
initial begin
$dumpvars();
$display("#################### Starting simulation ####################");
$monitor("@time=%0t\t data_out=0x%h\t",$time,data_out);
shift_en = 1'b0;
rst_n = 1'b1;
data_in = 1'b0;
async_rst();
repeat(10) begin
#50 push;
end
#200 $finish;
end
endmodule | 16 |
4,573 | data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v | 110,151,336 | lfsr_tb.v | v | 57 | 90 | [] | [] | [] | null | line:40: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n forever #2 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #13 rst_n = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #14 rst_n = 1\'b1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:37: Unsupported or unknown PLI call: $monitor\n $monitor("Time=%0t ns\\t LFSR=0x%h",$time,prg_out);\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:45: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:54: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 2,905 | module | module lfsr_tb;
reg clk;
reg rst_n;
wire [7:0] prg_out;
integer seq_len;
lfsr l_inst
(
.prg_out ( prg_out ),
.clk ( clk ),
.rst_n ( rst_n )
);
initial begin
clk = 0;
forever #2 clk = ~clk;
end
task async_rst;
begin
$display("---------- Start async_reset at %0t ns ----------\n",$time);
#13 rst_n = 1'b0;
#14 rst_n = 1'b1;
$display("---------- Finish async_reset at %0t ns ----------\n",$time);
end
endtask
initial begin
$dumpvars();
$monitor("Time=%0t ns\t LFSR=0x%h",$time,prg_out);
rst_n = 1'b1;
seq_len = 0;
async_rst();
#20
forever
begin
@(negedge clk)
begin
seq_len = seq_len+1;
if(prg_out == 8'hfc)begin
$display("---------- Sequence lenght =%0d ----------\n",seq_len);
$finish;
end
end
end
end
endmodule | module lfsr_tb; |
reg clk;
reg rst_n;
wire [7:0] prg_out;
integer seq_len;
lfsr l_inst
(
.prg_out ( prg_out ),
.clk ( clk ),
.rst_n ( rst_n )
);
initial begin
clk = 0;
forever #2 clk = ~clk;
end
task async_rst;
begin
$display("---------- Start async_reset at %0t ns ----------\n",$time);
#13 rst_n = 1'b0;
#14 rst_n = 1'b1;
$display("---------- Finish async_reset at %0t ns ----------\n",$time);
end
endtask
initial begin
$dumpvars();
$monitor("Time=%0t ns\t LFSR=0x%h",$time,prg_out);
rst_n = 1'b1;
seq_len = 0;
async_rst();
#20
forever
begin
@(negedge clk)
begin
seq_len = seq_len+1;
if(prg_out == 8'hfc)begin
$display("---------- Sequence lenght =%0d ----------\n",seq_len);
$finish;
end
end
end
end
endmodule | 16 |
4,576 | data/full_repos/permissive/110151336/lab_07/src/lab7_1/lab7_1.v | 110,151,336 | lab7_1.v | v | 34 | 50 | [] | [] | [] | [(21, 153)] | null | data/verilator_xmls/9487ffed-db7d-4999-9626-e746a61ce57b.xml | null | 2,909 | module | module lab7_1
#(parameter DATA_WIDTH=6, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data_in,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] data_out,
output [(ADDR_WIDTH-1):0] addr_out
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
wire w_we = ~ we;
wire w_clk = ~ clk;
always @ (posedge w_clk)
begin
if (w_we)
ram[addr] <= data_in;
addr_reg <= addr;
end
assign data_out = ram[addr_reg];
assign addr_out = addr_reg;
endmodule | module lab7_1
#(parameter DATA_WIDTH=6, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data_in,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] data_out,
output [(ADDR_WIDTH-1):0] addr_out
); |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
wire w_we = ~ we;
wire w_clk = ~ clk;
always @ (posedge w_clk)
begin
if (w_we)
ram[addr] <= data_in;
addr_reg <= addr;
end
assign data_out = ram[addr_reg];
assign addr_out = addr_reg;
endmodule | 16 |
4,577 | data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v | 110,151,336 | testbench.v | v | 73 | 76 | [] | [] | [] | null | line:60: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n #300 $finish;\n ^\n%Error: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:65: Unsupported or unknown PLI call: $monitor\n $monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b", \n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:70: Unsupported or unknown PLI call: $dumpvars\n $dumpvars; \n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,910 | module | module testbench;
reg [5:0] data_in;
reg [3:0] addr;
reg we;
reg clk;
wire [5:0] data_out;
wire [3:0] addr_out;
lab7_1 dut (data_in, addr, we, clk, data_out, addr_out);
initial
begin
clk = 0;
we = 1;
addr = 4'b0000;
data_in = 6'b000000;
#20;
we = 0;
#20;
addr = 4'b0001; data_in = 6'b000001;
#20;
addr = 4'b0010; data_in = 6'b000010;
#20;
addr = 4'b0011; data_in = 6'b000011;
#20;
addr = 4'b0100; data_in = 6'b000100;
#20;
addr = 4'b0101; data_in = 6'b000101;
#20;
we = 1;
#20;
addr = 4'b0000;
#20;
addr = 4'b0010;
#20;
addr = 4'b0011;
#20;
addr = 4'b0100;
#20;
addr = 4'b0101;
end
always #10 clk = ~clk;
initial
#300 $finish;
initial
$monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b",
data_in, addr, we, clk, data_out, addr_out);
initial
$dumpvars;
endmodule | module testbench; |
reg [5:0] data_in;
reg [3:0] addr;
reg we;
reg clk;
wire [5:0] data_out;
wire [3:0] addr_out;
lab7_1 dut (data_in, addr, we, clk, data_out, addr_out);
initial
begin
clk = 0;
we = 1;
addr = 4'b0000;
data_in = 6'b000000;
#20;
we = 0;
#20;
addr = 4'b0001; data_in = 6'b000001;
#20;
addr = 4'b0010; data_in = 6'b000010;
#20;
addr = 4'b0011; data_in = 6'b000011;
#20;
addr = 4'b0100; data_in = 6'b000100;
#20;
addr = 4'b0101; data_in = 6'b000101;
#20;
we = 1;
#20;
addr = 4'b0000;
#20;
addr = 4'b0010;
#20;
addr = 4'b0011;
#20;
addr = 4'b0100;
#20;
addr = 4'b0101;
end
always #10 clk = ~clk;
initial
#300 $finish;
initial
$monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b",
data_in, addr, we, clk, data_out, addr_out);
initial
$dumpvars;
endmodule | 16 |
4,582 | data/full_repos/permissive/110151336/lab_08/src/lab8.v | 110,151,336 | lab8.v | v | 235 | 79 | [] | [] | [] | [(1, 55), (57, 78), (80, 101), (109, 169), (173, 234)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,919 | module | module pattern_fsm_moore
(
input clock,
input reset_n,
input enable,
input a,
output y
);
parameter [1:0] S0 = 0, S1 = 1, S2 = 2;
reg [1:0] state, next_state;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
state <= S0;
else if (enable)
state <= next_state;
always @*
case (state)
S0:
if (a)
next_state = S0;
else
next_state = S1;
S1:
if (a)
next_state = S2;
else
next_state = S1;
S2:
if (a)
next_state = S0;
else
next_state = S1;
default:
next_state = S0;
endcase
assign y = (state == S2);
endmodule | module pattern_fsm_moore
(
input clock,
input reset_n,
input enable,
input a,
output y
); |
parameter [1:0] S0 = 0, S1 = 1, S2 = 2;
reg [1:0] state, next_state;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
state <= S0;
else if (enable)
state <= next_state;
always @*
case (state)
S0:
if (a)
next_state = S0;
else
next_state = S1;
S1:
if (a)
next_state = S2;
else
next_state = S1;
S2:
if (a)
next_state = S0;
else
next_state = S1;
default:
next_state = S0;
endcase
assign y = (state == S2);
endmodule | 16 |
4,583 | data/full_repos/permissive/110151336/lab_08/src/lab8.v | 110,151,336 | lab8.v | v | 235 | 79 | [] | [] | [] | [(1, 55), (57, 78), (80, 101), (109, 169), (173, 234)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,919 | module | module timer
# ( parameter timer_divider = 24 )
(
input clock_50_mhz,
input reset_n,
output strobe
);
reg [timer_divider - 1:0] counter;
always @ (posedge clock_50_mhz or negedge reset_n)
begin
if (! reset_n)
counter <= { timer_divider { 1'b0 } };
else
counter <= counter + { { timer_divider - 1 { 1'b0 } }, 1'b1 };
end
assign strobe
= (counter [timer_divider - 1:0] == { timer_divider { 1'b0 } } );
endmodule | module timer
# ( parameter timer_divider = 24 )
(
input clock_50_mhz,
input reset_n,
output strobe
); |
reg [timer_divider - 1:0] counter;
always @ (posedge clock_50_mhz or negedge reset_n)
begin
if (! reset_n)
counter <= { timer_divider { 1'b0 } };
else
counter <= counter + { { timer_divider - 1 { 1'b0 } }, 1'b1 };
end
assign strobe
= (counter [timer_divider - 1:0] == { timer_divider { 1'b0 } } );
endmodule | 16 |
4,584 | data/full_repos/permissive/110151336/lab_08/src/lab8.v | 110,151,336 | lab8.v | v | 235 | 79 | [] | [] | [] | [(1, 55), (57, 78), (80, 101), (109, 169), (173, 234)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,919 | module | module shift
# ( parameter width = 10 )
(
input clock,
input reset_n,
input shift_enable,
input button,
output reg [width - 1:0] shift_reg,
output out
);
always @ (posedge clock or negedge reset_n)
begin
if (! reset_n)
shift_reg <= { width { 1'b0 } };
else if (shift_enable)
shift_reg <= { button, shift_reg [width - 1:1] };
end
assign out = shift_reg [0];
endmodule | module shift
# ( parameter width = 10 )
(
input clock,
input reset_n,
input shift_enable,
input button,
output reg [width - 1:0] shift_reg,
output out
); |
always @ (posedge clock or negedge reset_n)
begin
if (! reset_n)
shift_reg <= { width { 1'b0 } };
else if (shift_enable)
shift_reg <= { button, shift_reg [width - 1:1] };
end
assign out = shift_reg [0];
endmodule | 16 |
4,585 | data/full_repos/permissive/110151336/lab_08/src/lab8.v | 110,151,336 | lab8.v | v | 235 | 79 | [] | [] | [] | [(1, 55), (57, 78), (80, 101), (109, 169), (173, 234)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,919 | module | module pattern_fsm_mealy
(
input clock,
input reset_n,
input enable,
input a,
output y
);
parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;
reg [1:0] state, next_state;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
state <= S0;
else if (enable)
state <= next_state;
always @*
case (state)
S0:
if (a)
next_state = S0;
else
next_state = S1;
S1:
if (a)
next_state = S1;
else
next_state = S2;
S2:
if (a)
next_state = S0;
else
next_state = S3;
S3:
if (a)
next_state = S2;
else
next_state = S0;
default:
next_state = S0;
endcase
assign y = (a & state == S1);
endmodule | module pattern_fsm_mealy
(
input clock,
input reset_n,
input enable,
input a,
output y
); |
parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;
reg [1:0] state, next_state;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
state <= S0;
else if (enable)
state <= next_state;
always @*
case (state)
S0:
if (a)
next_state = S0;
else
next_state = S1;
S1:
if (a)
next_state = S1;
else
next_state = S2;
S2:
if (a)
next_state = S0;
else
next_state = S3;
S3:
if (a)
next_state = S2;
else
next_state = S0;
default:
next_state = S0;
endcase
assign y = (a & state == S1);
endmodule | 16 |
4,586 | data/full_repos/permissive/110151336/lab_08/src/lab8.v | 110,151,336 | lab8.v | v | 235 | 79 | [] | [] | [] | [(1, 55), (57, 78), (80, 101), (109, 169), (173, 234)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance lab8\n assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 2,919 | module | module lab8
(
input clock,
input reset_n,
input key,
output [9:0] led,
output [6:0] hex0,
output [6:0] hex1
);
wire button = ~ key;
wire enable;
wire [9:0] shift_data;
wire shift_out;
wire moore_fsm_out;
wire mealy_fsm_out;
timer
# ( .timer_divider ( 24 ))
timer_i
(
.clock_50_mhz ( clock ),
.reset_n ( reset_n ),
.strobe ( enable )
);
shift
# ( .width ( 10 ))
shift_i
(
.clock ( clock ),
.reset_n ( reset_n ),
.shift_enable ( enable ),
.button ( button ),
.shift_reg ( shift_data ),
.out ( shift_out )
);
pattern_fsm_moore fsm_moore
(
.clock ( clock ),
.reset_n ( reset_n ),
.enable ( enable ),
.a ( shift_out ),
.y ( moore_fsm_out )
);
pattern_fsm_mealy fsm_mealy
(
.clock ( clock ),
.reset_n ( reset_n ),
.enable ( enable ),
.a ( shift_out ),
.y ( mealy_fsm_out )
);
assign led = shift_data;
assign hex0 = moore_fsm_out ? 8'b10100011 : 8'b11111111;
assign hex1 = mealy_fsm_out ? 8'b10011100 : 8'b11111111;
endmodule | module lab8
(
input clock,
input reset_n,
input key,
output [9:0] led,
output [6:0] hex0,
output [6:0] hex1
); |
wire button = ~ key;
wire enable;
wire [9:0] shift_data;
wire shift_out;
wire moore_fsm_out;
wire mealy_fsm_out;
timer
# ( .timer_divider ( 24 ))
timer_i
(
.clock_50_mhz ( clock ),
.reset_n ( reset_n ),
.strobe ( enable )
);
shift
# ( .width ( 10 ))
shift_i
(
.clock ( clock ),
.reset_n ( reset_n ),
.shift_enable ( enable ),
.button ( button ),
.shift_reg ( shift_data ),
.out ( shift_out )
);
pattern_fsm_moore fsm_moore
(
.clock ( clock ),
.reset_n ( reset_n ),
.enable ( enable ),
.a ( shift_out ),
.y ( moore_fsm_out )
);
pattern_fsm_mealy fsm_mealy
(
.clock ( clock ),
.reset_n ( reset_n ),
.enable ( enable ),
.a ( shift_out ),
.y ( mealy_fsm_out )
);
assign led = shift_data;
assign hex0 = moore_fsm_out ? 8'b10100011 : 8'b11111111;
assign hex1 = mealy_fsm_out ? 8'b10011100 : 8'b11111111;
endmodule | 16 |
4,588 | data/full_repos/permissive/110151336/lab_09/src/01_badstyle/pmod_als.v | 110,151,336 | pmod_als.v | v | 140 | 80 | [] | [] | [] | [(9, 86), (89, 138)] | null | data/verilator_xmls/c751f67b-c762-4b26-9b8c-851b7dee9429.xml | null | 2,922 | module | module pmod_als
#(
parameter QUERY_DELAY = 40
)
(
input clk,
input rst_n,
output reg cs,
output sck,
input sdo,
output reg [7:0] value
);
localparam S_IDLE = 0,
S_PREFIX = 1,
S_DATA = 2,
S_POSTFIX = 3;
localparam IDLE_SIZE = QUERY_DELAY,
PREFIX_SIZE = 2,
DATA_SIZE = 7,
POSTFIX_SIZE = 4;
wire sck_edge;
sck_clk_divider scd
(
.clk ( clk ),
.rst_n ( rst_n ),
.sck ( sck ),
.sck_edge ( sck_edge )
);
reg [ 1:0] State;
reg [23:0] cnt;
reg [ 7:0] buffer;
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
State <= S_IDLE;
cnt <= 24'b0;
buffer <= 8'b0;
value <= 8'b0;
cs <= 1'b1;
end
else begin
if (sck_edge)
case(State)
S_IDLE : begin
if(cnt == IDLE_SIZE) begin
State <= S_PREFIX;
cs <= 1'b0;
end
cnt <= (cnt == IDLE_SIZE) ? 0 : cnt + 1;
end
S_PREFIX : begin
if(cnt == PREFIX_SIZE) State <= S_DATA;
cnt <= (cnt == PREFIX_SIZE) ? 0 : cnt + 1;
end
S_DATA : begin
if(cnt == DATA_SIZE) State <= S_POSTFIX;
cnt <= (cnt == DATA_SIZE) ? 0 : cnt + 1;
buffer <= { buffer[6:0], sdo };
end
S_POSTFIX : begin
if(cnt == POSTFIX_SIZE) begin
State <= S_IDLE;
cs <= 1'b1;
end
cnt <= (cnt == POSTFIX_SIZE) ? 0 : cnt + 1;
value <= buffer;
end
endcase
end
endmodule | module pmod_als
#(
parameter QUERY_DELAY = 40
)
(
input clk,
input rst_n,
output reg cs,
output sck,
input sdo,
output reg [7:0] value
); |
localparam S_IDLE = 0,
S_PREFIX = 1,
S_DATA = 2,
S_POSTFIX = 3;
localparam IDLE_SIZE = QUERY_DELAY,
PREFIX_SIZE = 2,
DATA_SIZE = 7,
POSTFIX_SIZE = 4;
wire sck_edge;
sck_clk_divider scd
(
.clk ( clk ),
.rst_n ( rst_n ),
.sck ( sck ),
.sck_edge ( sck_edge )
);
reg [ 1:0] State;
reg [23:0] cnt;
reg [ 7:0] buffer;
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
State <= S_IDLE;
cnt <= 24'b0;
buffer <= 8'b0;
value <= 8'b0;
cs <= 1'b1;
end
else begin
if (sck_edge)
case(State)
S_IDLE : begin
if(cnt == IDLE_SIZE) begin
State <= S_PREFIX;
cs <= 1'b0;
end
cnt <= (cnt == IDLE_SIZE) ? 0 : cnt + 1;
end
S_PREFIX : begin
if(cnt == PREFIX_SIZE) State <= S_DATA;
cnt <= (cnt == PREFIX_SIZE) ? 0 : cnt + 1;
end
S_DATA : begin
if(cnt == DATA_SIZE) State <= S_POSTFIX;
cnt <= (cnt == DATA_SIZE) ? 0 : cnt + 1;
buffer <= { buffer[6:0], sdo };
end
S_POSTFIX : begin
if(cnt == POSTFIX_SIZE) begin
State <= S_IDLE;
cs <= 1'b1;
end
cnt <= (cnt == POSTFIX_SIZE) ? 0 : cnt + 1;
value <= buffer;
end
endcase
end
endmodule | 16 |
4,589 | data/full_repos/permissive/110151336/lab_09/src/01_badstyle/pmod_als.v | 110,151,336 | pmod_als.v | v | 140 | 80 | [] | [] | [] | [(9, 86), (89, 138)] | null | data/verilator_xmls/c751f67b-c762-4b26-9b8c-851b7dee9429.xml | null | 2,922 | module | module sck_clk_divider
(
input clk,
input rst_n,
output reg sck,
output reg sck_edge
);
localparam S_DOWN = 0,
S_EDGE = 1,
S_UP = 2;
localparam DOWN_SIZE = 7,
UP_SIZE = DOWN_SIZE - 1;
reg [1:0] State;
reg [2:0] cnt;
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
State <= S_DOWN;
cnt <= 3'b0;
end
else begin
case(State)
S_DOWN : begin
if(cnt == DOWN_SIZE) begin
State <= S_EDGE;
sck_edge <= 1'b1;
sck <= 1'b1;
end
cnt <= (cnt == DOWN_SIZE) ? 0 : cnt + 1;
end
S_EDGE : begin
State <= S_UP;
cnt <= 0;
sck_edge <= 1'b0;
end
S_UP : begin
if(cnt == UP_SIZE) begin
State <= S_DOWN;
sck <= 1'b0;
end
cnt <= (cnt == UP_SIZE) ? 0 : cnt + 1;
end
endcase
end
endmodule | module sck_clk_divider
(
input clk,
input rst_n,
output reg sck,
output reg sck_edge
); |
localparam S_DOWN = 0,
S_EDGE = 1,
S_UP = 2;
localparam DOWN_SIZE = 7,
UP_SIZE = DOWN_SIZE - 1;
reg [1:0] State;
reg [2:0] cnt;
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
State <= S_DOWN;
cnt <= 3'b0;
end
else begin
case(State)
S_DOWN : begin
if(cnt == DOWN_SIZE) begin
State <= S_EDGE;
sck_edge <= 1'b1;
sck <= 1'b1;
end
cnt <= (cnt == DOWN_SIZE) ? 0 : cnt + 1;
end
S_EDGE : begin
State <= S_UP;
cnt <= 0;
sck_edge <= 1'b0;
end
S_UP : begin
if(cnt == UP_SIZE) begin
State <= S_DOWN;
sck <= 1'b0;
end
cnt <= (cnt == UP_SIZE) ? 0 : cnt + 1;
end
endcase
end
endmodule | 16 |
4,590 | data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v | 110,151,336 | de10_lite.v | v | 82 | 60 | [] | [] | [] | [(1, 81)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:49: Cannot find file containing module: \'pmod_als\'\n pmod_als \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als\n data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als.v\n data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als.sv\n pmod_als\n pmod_als.v\n pmod_als.sv\n obj_dir/pmod_als\n obj_dir/pmod_als.v\n obj_dir/pmod_als.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:63: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance de10_lite\n assign LEDR[9:1] = 8\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n : ... In instance de10_lite\n wire [ 31:0 ] h7segment = { 16\'b0, value };\n ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:74: Cannot find file containing module: \'hex_display\'\n hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:75: Cannot find file containing module: \'hex_display\'\n hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:76: Cannot find file containing module: \'hex_display\'\n hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:77: Cannot find file containing module: \'hex_display\'\n hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:78: Cannot find file containing module: \'hex_display\'\n hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:79: Cannot find file containing module: \'hex_display\'\n hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 2 warning(s)\n' | 2,923 | module | module de10_lite
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
output [ 7:0 ] HEX0,
output [ 7:0 ] HEX1,
output [ 7:0 ] HEX2,
output [ 7:0 ] HEX3,
output [ 7:0 ] HEX4,
output [ 7:0 ] HEX5,
input [ 1:0 ] KEY,
output [ 9:0 ] LEDR,
input [ 9:0 ] SW,
inout [ 35:0 ] GPIO
);
wire cs;
wire sck;
wire sdo;
assign GPIO[26] = 1'b0;
assign GPIO[28] = sck;
assign sdo = GPIO[30];
assign GPIO[32] = 1'bz;
assign GPIO[34] = cs;
wire clk = MAX10_CLK1_50;
wire rst_n = KEY[0];
wire [7:0] value;
pmod_als
#( .QUERY_DELAY(1 << 21) )
als
(
.clk ( clk ),
.rst_n ( rst_n ),
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo ),
.value ( value )
);
assign LEDR[0] = ~cs;
assign LEDR[9:1] = 8'b0;
wire [ 31:0 ] h7segment = { 16'b0, value };
assign HEX0 [7] = 1'b1;
assign HEX1 [7] = 1'b1;
assign HEX2 [7] = 1'b1;
assign HEX3 [7] = 1'b1;
assign HEX4 [7] = 1'b1;
assign HEX5 [7] = 1'b1;
hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | module de10_lite
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
output [ 7:0 ] HEX0,
output [ 7:0 ] HEX1,
output [ 7:0 ] HEX2,
output [ 7:0 ] HEX3,
output [ 7:0 ] HEX4,
output [ 7:0 ] HEX5,
input [ 1:0 ] KEY,
output [ 9:0 ] LEDR,
input [ 9:0 ] SW,
inout [ 35:0 ] GPIO
); |
wire cs;
wire sck;
wire sdo;
assign GPIO[26] = 1'b0;
assign GPIO[28] = sck;
assign sdo = GPIO[30];
assign GPIO[32] = 1'bz;
assign GPIO[34] = cs;
wire clk = MAX10_CLK1_50;
wire rst_n = KEY[0];
wire [7:0] value;
pmod_als
#( .QUERY_DELAY(1 << 21) )
als
(
.clk ( clk ),
.rst_n ( rst_n ),
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo ),
.value ( value )
);
assign LEDR[0] = ~cs;
assign LEDR[9:1] = 8'b0;
wire [ 31:0 ] h7segment = { 16'b0, value };
assign HEX0 [7] = 1'b1;
assign HEX1 [7] = 1'b1;
assign HEX2 [7] = 1'b1;
assign HEX3 [7] = 1'b1;
assign HEX4 [7] = 1'b1;
assign HEX5 [7] = 1'b1;
hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | 16 |
4,595 | data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v | 110,151,336 | pmod_als.v | v | 39 | 79 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:23: Cannot find file containing module: \'register\'\n register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register\n data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register.v\n data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:32: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'sdo\' generates 1 bits.\n : ... In instance pmod_als\n wire [7:0] shiftNext = (shift << 1) | sdo;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:33: Cannot find file containing module: \'register_we\'\n register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:36: Cannot find file containing module: \'register_we\'\n register_we #(.SIZE(8)) r_value(clk, rst_n, valueDone, valueNext, value);\n ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 2,938 | module | module pmod_als
#(
parameter CNTSIZE = 11
)
(
input clk,
input rst_n,
output cs,
output sck,
input sdo,
output [7:0] value
);
wire [ CNTSIZE - 1:0] cnt;
wire [ CNTSIZE - 1:0] cntNext = cnt + 1;
register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);
assign sck = cnt [3];
assign cs = ~(cnt[CNTSIZE - 1:8] == { (CNTSIZE - 8) { 1'b1 }});
wire sampleBit = ( cs == 1'b0 && cnt [3:0] == 4'b1000 );
wire valueDone = ( cs == 1'b0 && cnt [7:0] == 8'b10101001 );
wire [7:0] shift;
wire [7:0] shiftNext = (shift << 1) | sdo;
register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);
wire [7:0] valueNext = shift;
register_we #(.SIZE(8)) r_value(clk, rst_n, valueDone, valueNext, value);
endmodule | module pmod_als
#(
parameter CNTSIZE = 11
)
(
input clk,
input rst_n,
output cs,
output sck,
input sdo,
output [7:0] value
); |
wire [ CNTSIZE - 1:0] cnt;
wire [ CNTSIZE - 1:0] cntNext = cnt + 1;
register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);
assign sck = cnt [3];
assign cs = ~(cnt[CNTSIZE - 1:8] == { (CNTSIZE - 8) { 1'b1 }});
wire sampleBit = ( cs == 1'b0 && cnt [3:0] == 4'b1000 );
wire valueDone = ( cs == 1'b0 && cnt [7:0] == 8'b10101001 );
wire [7:0] shift;
wire [7:0] shiftNext = (shift << 1) | sdo;
register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);
wire [7:0] valueNext = shift;
register_we #(.SIZE(8)) r_value(clk, rst_n, valueDone, valueNext, value);
endmodule | 16 |
4,597 | data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v | 110,151,336 | testbench.v | v | 77 | 41 | [] | [] | [] | null | line:58: before: "(" | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:58: syntax error, unexpected \'@\'\n repeat (4) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:64: syntax error, unexpected \'@\'\n repeat (Cycles) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:71: Unsupported or unknown PLI call: $monitor\n $monitor("value=%h", value);\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:74: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 2,943 | module | module testbench;
parameter Tt = 20;
parameter Cycles = 4000;
reg clk;
reg rst_n;
wire cs;
wire sck;
wire sdo;
wire [7:0] value;
pmod_als als
(
.clk ( clk ),
.rst_n ( rst_n ),
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo ),
.value ( value )
);
pmod_als_stub stub
(
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo )
);
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
initial begin
repeat (Cycles) @(posedge clk);
$display ("Timeout");
$stop;
end
initial
$monitor("value=%h", value);
initial
$dumpvars;
endmodule | module testbench; |
parameter Tt = 20;
parameter Cycles = 4000;
reg clk;
reg rst_n;
wire cs;
wire sck;
wire sdo;
wire [7:0] value;
pmod_als als
(
.clk ( clk ),
.rst_n ( rst_n ),
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo ),
.value ( value )
);
pmod_als_stub stub
(
.cs ( cs ),
.sck ( sck ),
.sdo ( sdo )
);
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
initial begin
repeat (Cycles) @(posedge clk);
$display ("Timeout");
$stop;
end
initial
$monitor("value=%h", value);
initial
$dumpvars;
endmodule | 16 |
4,598 | data/full_repos/permissive/110151336/lab_09/src/common/synthesis/hex_display.v | 110,151,336 | hex_display.v | v | 29 | 59 | [] | [] | [] | [(2, 28)] | null | data/verilator_xmls/6ce01ae9-065e-4fcc-a84f-a4358aef8788.xml | null | 2,944 | module | module hex_display
(
input [3:0] digit,
output reg [6:0] seven_segments
);
always @*
case (digit)
'h0: seven_segments = 'b1000000;
'h1: seven_segments = 'b1111001;
'h2: seven_segments = 'b0100100;
'h3: seven_segments = 'b0110000;
'h4: seven_segments = 'b0011001;
'h5: seven_segments = 'b0010010;
'h6: seven_segments = 'b0000010;
'h7: seven_segments = 'b1111000;
'h8: seven_segments = 'b0000000;
'h9: seven_segments = 'b0011000;
'ha: seven_segments = 'b0001000;
'hb: seven_segments = 'b0000011;
'hc: seven_segments = 'b1000110;
'hd: seven_segments = 'b0100001;
'he: seven_segments = 'b0000110;
'hf: seven_segments = 'b0001110;
endcase
endmodule | module hex_display
(
input [3:0] digit,
output reg [6:0] seven_segments
); |
always @*
case (digit)
'h0: seven_segments = 'b1000000;
'h1: seven_segments = 'b1111001;
'h2: seven_segments = 'b0100100;
'h3: seven_segments = 'b0110000;
'h4: seven_segments = 'b0011001;
'h5: seven_segments = 'b0010010;
'h6: seven_segments = 'b0000010;
'h7: seven_segments = 'b1111000;
'h8: seven_segments = 'b0000000;
'h9: seven_segments = 'b0011000;
'ha: seven_segments = 'b0001000;
'hb: seven_segments = 'b0000011;
'hc: seven_segments = 'b1000110;
'hd: seven_segments = 'b0100001;
'he: seven_segments = 'b0000110;
'hf: seven_segments = 'b0001110;
endcase
endmodule | 16 |
4,599 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v | 110,151,336 | testbench.v | v | 568 | 79 | [] | [] | [] | null | line:439: before: "checks" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:380: Unsupported: Ignoring delay on this delayed statement.\n # 10 clk = ! clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:388: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:390: syntax error, unexpected \'@\'\n repeat (2) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:405: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:404: Unsupported: Ignoring delay on this delayed statement.\n #0\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:407: syntax error, unexpected \'@\'\n @ (posedge rst_n);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:409: syntax error, unexpected \'@\'\n repeat (10) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:414: syntax error, unexpected \'@\'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:418: syntax error, unexpected \'@\'\n repeat (10) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:427: syntax error, unexpected \'@\'\n @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:430: syntax error, unexpected \'@\'\n repeat (10) @ (posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/01_sim_pow_5/testbench.v:437: syntax error, unexpected \'@\'\n @ (posedge clk);\n ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 2,945 | module | module testbench
# (
parameter w = 8,
n = 5
);
reg clk;
reg rst_n;
reg clk_en;
reg arg_vld;
reg [ w - 1:0 ] arg;
wire res_vld_pow_5_single_cycle_struct;
wire res_vld_pow_5_single_cycle_always;
wire res_vld_pow_5_multi_cycle_struct_todo;
wire res_vld_pow_5_multi_cycle_struct;
wire res_vld_pow_5_multi_cycle_always;
wire [ n - 1:0 ] res_vld_pow_5_pipe_struct;
wire [ 5 - 1:0 ] res_vld_pow_n_pipe_struct_5;
wire [ n - 1:0 ] res_vld_pow_5_pipe_always;
wire [ n - 1:0 ] res_vld_pow_5_pipe_always_with_array;
wire [ 5 - 1:0 ] res_vld_pow_n_pipe_always_5;
wire [ 6 - 1:0 ] res_vld_pow_n_pipe_struct_6;
wire [ 6 - 1:0 ] res_vld_pow_n_pipe_always_6;
wire [ w - 1:0 ] res_pow_5_single_cycle_struct;
wire [ w - 1:0 ] res_pow_5_single_cycle_always;
wire [ w - 1:0 ] res_pow_5_multi_cycle_struct_todo;
wire [ w - 1:0 ] res_pow_5_multi_cycle_struct;
wire [ w - 1:0 ] res_pow_5_multi_cycle_always;
wire [ n * w - 1:0 ] res_pow_5_pipe_struct;
wire [ 5 * w - 1:0 ] res_pow_n_pipe_struct_5;
wire [ n * w - 1:0 ] res_pow_5_pipe_always;
wire [ n * w - 1:0 ] res_pow_5_pipe_always_with_array;
wire [ 5 * w - 1:0 ] res_pow_n_pipe_always_5;
wire [ 6 * w - 1:0 ] res_pow_n_pipe_struct_6;
wire [ 6 * w - 1:0 ] res_pow_n_pipe_always_6;
wire res_vld_pow_5_en_single_cycle_struct;
wire res_vld_pow_5_en_single_cycle_always;
wire res_vld_pow_5_en_multi_cycle_struct;
wire res_vld_pow_5_en_multi_cycle_always;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_struct;
wire [ 5 - 1:0 ] res_vld_pow_n_en_pipe_struct_5;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_always;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_always_with_array;
wire [ 5 - 1:0 ] res_vld_pow_n_en_pipe_always_5;
wire [ 6 - 1:0 ] res_vld_pow_n_en_pipe_struct_6;
wire [ 6 - 1:0 ] res_vld_pow_n_en_pipe_always_6;
wire [ w - 1:0 ] res_pow_5_en_single_cycle_struct;
wire [ w - 1:0 ] res_pow_5_en_single_cycle_always;
wire [ w - 1:0 ] res_pow_5_en_multi_cycle_struct;
wire [ w - 1:0 ] res_pow_5_en_multi_cycle_always;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_struct;
wire [ 5 * w - 1:0 ] res_pow_n_en_pipe_struct_5;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_always;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_always_with_array;
wire [ 5 * w - 1:0 ] res_pow_n_en_pipe_always_5;
wire [ 6 * w - 1:0 ] res_pow_n_en_pipe_struct_6;
wire [ 6 * w - 1:0 ] res_pow_n_en_pipe_always_6;
pow_5_single_cycle_struct
# (.w (w))
i_pow_5_single_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_single_cycle_struct ),
.res ( res_pow_5_single_cycle_struct )
);
pow_5_single_cycle_always
# (.w (w))
i_pow_5_single_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_single_cycle_always ),
.res ( res_pow_5_single_cycle_always )
);
pow_5_multi_cycle_struct_todo
# (.w (w))
i_pow_5_multi_cycle_struct_todo
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_struct_todo ),
.res ( res_pow_5_multi_cycle_struct_todo )
);
pow_5_multi_cycle_struct
# (.w (w))
i_pow_5_multi_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_struct ),
.res ( res_pow_5_multi_cycle_struct )
);
pow_5_multi_cycle_always
# (.w (w))
i_pow_5_multi_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_always ),
.res ( res_pow_5_multi_cycle_always )
);
pow_5_pipe_struct
# (.w (w))
i_pow_5_pipe_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_struct ),
.res ( res_pow_5_pipe_struct )
);
pow_n_pipe_struct
# (.w (w), .n (5))
i_pow_n_pipe_struct_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_struct_5 ),
.res ( res_pow_n_pipe_struct_5 )
);
pow_5_pipe_always
# (.w (w))
i_pow_5_pipe_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_always ),
.res ( res_pow_5_pipe_always )
);
pow_5_pipe_always_with_array
# (.w (w))
i_pow_5_pipe_always_with_array
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_always_with_array ),
.res ( res_pow_5_pipe_always_with_array )
);
pow_n_pipe_always
# (.w (w), .n (5))
i_pow_n_pipe_always_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_always_5 ),
.res ( res_pow_n_pipe_always_5 )
);
pow_n_pipe_struct
# (.w (w), .n (6))
i_pow_n_pipe_struct_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_struct_6 ),
.res ( res_pow_n_pipe_struct_6 )
);
pow_n_pipe_always
# (.w (w), .n (6))
i_pow_n_pipe_always_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_always_6 ),
.res ( res_pow_n_pipe_always_6 )
);
pow_5_en_single_cycle_struct
# (.w (w))
i_pow_5_en_single_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_single_cycle_struct ),
.res ( res_pow_5_en_single_cycle_struct )
);
pow_5_en_single_cycle_always
# (.w (w))
i_pow_5_en_single_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_single_cycle_always ),
.res ( res_pow_5_en_single_cycle_always )
);
pow_5_en_multi_cycle_struct
# (.w (w))
i_pow_5_en_multi_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_multi_cycle_struct ),
.res ( res_pow_5_en_multi_cycle_struct )
);
pow_5_en_multi_cycle_always
# (.w (w))
i_pow_5_en_multi_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_multi_cycle_always ),
.res ( res_pow_5_en_multi_cycle_always )
);
pow_5_en_pipe_struct
# (.w (w))
i_pow_5_en_pipe_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_struct ),
.res ( res_pow_5_en_pipe_struct )
);
pow_n_en_pipe_struct
# (.w (w), .n (5))
i_pow_n_en_pipe_struct_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_struct_5 ),
.res ( res_pow_n_en_pipe_struct_5 )
);
pow_5_en_pipe_always
# (.w (w))
i_pow_5_en_pipe_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_always ),
.res ( res_pow_5_en_pipe_always )
);
pow_5_en_pipe_always_with_array
# (.w (w))
i_pow_5_en_pipe_always_with_array
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_always_with_array ),
.res ( res_pow_5_en_pipe_always_with_array )
);
pow_n_en_pipe_always
# (.w (w), .n (5))
i_pow_n_en_pipe_always_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_always_5 ),
.res ( res_pow_n_en_pipe_always_5 )
);
pow_n_en_pipe_struct
# (.w (w), .n (6))
i_pow_n_en_pipe_struct_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_struct_6 ),
.res ( res_pow_n_en_pipe_struct_6 )
);
pow_n_en_pipe_always
# (.w (w), .n (6))
i_pow_n_en_pipe_always_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_always_6 ),
.res ( res_pow_n_en_pipe_always_6 )
);
initial
begin
clk = 0;
forever
# 10 clk = ! clk;
end
initial
begin
clk_en <= 1'b1;
arg_vld <= 1'b0;
repeat (2) @ (posedge clk);
rst_n <= 0;
repeat (2) @ (posedge clk);
rst_n <= 1;
end
integer i;
initial
begin
#0
$dumpvars;
@ (posedge rst_n);
repeat (10) @ (posedge clk);
arg <= 3;
arg_vld <= 1;
@ (posedge clk);
arg_vld <= 0;
repeat (10) @ (posedge clk);
@ (posedge clk);
for (i = 0; i < 50; i = i + 1)
begin
arg <= i & 7;
arg_vld <= (i == 0 || res_vld_pow_5_en_multi_cycle_struct);
@ (posedge clk);
end
repeat (10) @ (posedge clk);
for (i = 0; i < 50; i = i + 1)
begin
arg <= i & 7;
arg_vld <= 1;
@ (posedge clk);
end
$stop;
end
reg [31:0] checks;
always @ (posedge clk)
begin
checks [ 0] = ( res_vld_pow_5_single_cycle_struct
=== res_vld_pow_5_single_cycle_always );
checks [ 1] = ( res_vld_pow_5_multi_cycle_struct
=== res_vld_pow_5_multi_cycle_always );
checks [ 2] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_n_pipe_struct_5 );
checks [ 3] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_pipe_always );
checks [ 4] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_pipe_always_with_array );
checks [ 5] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_n_pipe_always_5 );
checks [ 6] = ( res_vld_pow_n_pipe_struct_6
=== res_vld_pow_n_pipe_always_6 );
checks [ 7] = ( res_pow_5_single_cycle_struct
=== res_pow_5_single_cycle_always );
checks [ 8] = ( res_pow_5_multi_cycle_struct
=== res_pow_5_multi_cycle_always );
checks [ 9] = ( res_pow_5_pipe_struct
=== res_pow_n_pipe_struct_5 );
checks [10] = ( res_pow_5_pipe_struct
=== res_pow_5_pipe_always );
checks [11] = ( res_pow_5_pipe_struct
=== res_pow_5_pipe_always_with_array );
checks [12] = ( res_pow_5_pipe_struct
=== res_pow_n_pipe_always_5 );
checks [13] = ( res_pow_n_pipe_struct_6
=== res_pow_n_pipe_always_6 );
checks [14] = ( res_vld_pow_5_en_single_cycle_struct
=== res_vld_pow_5_en_single_cycle_always );
checks [15] = ( res_vld_pow_5_en_multi_cycle_struct
=== res_vld_pow_5_en_multi_cycle_always );
checks [16] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_n_en_pipe_struct_5 );
checks [17] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_5_en_pipe_always );
checks [18] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_5_en_pipe_always_with_array );
checks [19] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_n_en_pipe_always_5 );
checks [20] = ( res_vld_pow_n_en_pipe_struct_6
=== res_vld_pow_n_en_pipe_always_6 );
checks [21] = ( res_pow_5_en_single_cycle_struct
=== res_pow_5_en_single_cycle_always );
checks [22] = ( res_pow_5_en_multi_cycle_struct
=== res_pow_5_en_multi_cycle_always );
checks [23] = ( res_pow_5_en_pipe_struct
=== res_pow_n_en_pipe_struct_5 );
checks [24] = ( res_pow_5_en_pipe_struct
=== res_pow_5_en_pipe_always );
checks [25] = ( res_pow_5_en_pipe_struct
=== res_pow_5_en_pipe_always_with_array );
checks [26] = ( res_pow_5_en_pipe_struct
=== res_pow_n_en_pipe_always_5 );
checks [27] = ( res_pow_n_en_pipe_struct_6
=== res_pow_n_en_pipe_always_6 );
checks [28] = ( res_vld_pow_5_single_cycle_struct
=== res_vld_pow_5_en_single_cycle_struct );
checks [29] = ( res_vld_pow_5_multi_cycle_struct
=== res_vld_pow_5_en_multi_cycle_struct );
checks [30] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_en_pipe_struct );
checks [31] = ( res_vld_pow_n_pipe_struct_6
=== res_vld_pow_n_en_pipe_struct_6 );
if ((~ checks) != 0)
$display ("Something went wrong %b", checks);
end
endmodule | module testbench
# (
parameter w = 8,
n = 5
); |
reg clk;
reg rst_n;
reg clk_en;
reg arg_vld;
reg [ w - 1:0 ] arg;
wire res_vld_pow_5_single_cycle_struct;
wire res_vld_pow_5_single_cycle_always;
wire res_vld_pow_5_multi_cycle_struct_todo;
wire res_vld_pow_5_multi_cycle_struct;
wire res_vld_pow_5_multi_cycle_always;
wire [ n - 1:0 ] res_vld_pow_5_pipe_struct;
wire [ 5 - 1:0 ] res_vld_pow_n_pipe_struct_5;
wire [ n - 1:0 ] res_vld_pow_5_pipe_always;
wire [ n - 1:0 ] res_vld_pow_5_pipe_always_with_array;
wire [ 5 - 1:0 ] res_vld_pow_n_pipe_always_5;
wire [ 6 - 1:0 ] res_vld_pow_n_pipe_struct_6;
wire [ 6 - 1:0 ] res_vld_pow_n_pipe_always_6;
wire [ w - 1:0 ] res_pow_5_single_cycle_struct;
wire [ w - 1:0 ] res_pow_5_single_cycle_always;
wire [ w - 1:0 ] res_pow_5_multi_cycle_struct_todo;
wire [ w - 1:0 ] res_pow_5_multi_cycle_struct;
wire [ w - 1:0 ] res_pow_5_multi_cycle_always;
wire [ n * w - 1:0 ] res_pow_5_pipe_struct;
wire [ 5 * w - 1:0 ] res_pow_n_pipe_struct_5;
wire [ n * w - 1:0 ] res_pow_5_pipe_always;
wire [ n * w - 1:0 ] res_pow_5_pipe_always_with_array;
wire [ 5 * w - 1:0 ] res_pow_n_pipe_always_5;
wire [ 6 * w - 1:0 ] res_pow_n_pipe_struct_6;
wire [ 6 * w - 1:0 ] res_pow_n_pipe_always_6;
wire res_vld_pow_5_en_single_cycle_struct;
wire res_vld_pow_5_en_single_cycle_always;
wire res_vld_pow_5_en_multi_cycle_struct;
wire res_vld_pow_5_en_multi_cycle_always;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_struct;
wire [ 5 - 1:0 ] res_vld_pow_n_en_pipe_struct_5;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_always;
wire [ n - 1:0 ] res_vld_pow_5_en_pipe_always_with_array;
wire [ 5 - 1:0 ] res_vld_pow_n_en_pipe_always_5;
wire [ 6 - 1:0 ] res_vld_pow_n_en_pipe_struct_6;
wire [ 6 - 1:0 ] res_vld_pow_n_en_pipe_always_6;
wire [ w - 1:0 ] res_pow_5_en_single_cycle_struct;
wire [ w - 1:0 ] res_pow_5_en_single_cycle_always;
wire [ w - 1:0 ] res_pow_5_en_multi_cycle_struct;
wire [ w - 1:0 ] res_pow_5_en_multi_cycle_always;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_struct;
wire [ 5 * w - 1:0 ] res_pow_n_en_pipe_struct_5;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_always;
wire [ n * w - 1:0 ] res_pow_5_en_pipe_always_with_array;
wire [ 5 * w - 1:0 ] res_pow_n_en_pipe_always_5;
wire [ 6 * w - 1:0 ] res_pow_n_en_pipe_struct_6;
wire [ 6 * w - 1:0 ] res_pow_n_en_pipe_always_6;
pow_5_single_cycle_struct
# (.w (w))
i_pow_5_single_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_single_cycle_struct ),
.res ( res_pow_5_single_cycle_struct )
);
pow_5_single_cycle_always
# (.w (w))
i_pow_5_single_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_single_cycle_always ),
.res ( res_pow_5_single_cycle_always )
);
pow_5_multi_cycle_struct_todo
# (.w (w))
i_pow_5_multi_cycle_struct_todo
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_struct_todo ),
.res ( res_pow_5_multi_cycle_struct_todo )
);
pow_5_multi_cycle_struct
# (.w (w))
i_pow_5_multi_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_struct ),
.res ( res_pow_5_multi_cycle_struct )
);
pow_5_multi_cycle_always
# (.w (w))
i_pow_5_multi_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_multi_cycle_always ),
.res ( res_pow_5_multi_cycle_always )
);
pow_5_pipe_struct
# (.w (w))
i_pow_5_pipe_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_struct ),
.res ( res_pow_5_pipe_struct )
);
pow_n_pipe_struct
# (.w (w), .n (5))
i_pow_n_pipe_struct_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_struct_5 ),
.res ( res_pow_n_pipe_struct_5 )
);
pow_5_pipe_always
# (.w (w))
i_pow_5_pipe_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_always ),
.res ( res_pow_5_pipe_always )
);
pow_5_pipe_always_with_array
# (.w (w))
i_pow_5_pipe_always_with_array
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_pipe_always_with_array ),
.res ( res_pow_5_pipe_always_with_array )
);
pow_n_pipe_always
# (.w (w), .n (5))
i_pow_n_pipe_always_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_always_5 ),
.res ( res_pow_n_pipe_always_5 )
);
pow_n_pipe_struct
# (.w (w), .n (6))
i_pow_n_pipe_struct_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_struct_6 ),
.res ( res_pow_n_pipe_struct_6 )
);
pow_n_pipe_always
# (.w (w), .n (6))
i_pow_n_pipe_always_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_pipe_always_6 ),
.res ( res_pow_n_pipe_always_6 )
);
pow_5_en_single_cycle_struct
# (.w (w))
i_pow_5_en_single_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_single_cycle_struct ),
.res ( res_pow_5_en_single_cycle_struct )
);
pow_5_en_single_cycle_always
# (.w (w))
i_pow_5_en_single_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_single_cycle_always ),
.res ( res_pow_5_en_single_cycle_always )
);
pow_5_en_multi_cycle_struct
# (.w (w))
i_pow_5_en_multi_cycle_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_multi_cycle_struct ),
.res ( res_pow_5_en_multi_cycle_struct )
);
pow_5_en_multi_cycle_always
# (.w (w))
i_pow_5_en_multi_cycle_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_multi_cycle_always ),
.res ( res_pow_5_en_multi_cycle_always )
);
pow_5_en_pipe_struct
# (.w (w))
i_pow_5_en_pipe_struct
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_struct ),
.res ( res_pow_5_en_pipe_struct )
);
pow_n_en_pipe_struct
# (.w (w), .n (5))
i_pow_n_en_pipe_struct_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_struct_5 ),
.res ( res_pow_n_en_pipe_struct_5 )
);
pow_5_en_pipe_always
# (.w (w))
i_pow_5_en_pipe_always
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_always ),
.res ( res_pow_5_en_pipe_always )
);
pow_5_en_pipe_always_with_array
# (.w (w))
i_pow_5_en_pipe_always_with_array
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_5_en_pipe_always_with_array ),
.res ( res_pow_5_en_pipe_always_with_array )
);
pow_n_en_pipe_always
# (.w (w), .n (5))
i_pow_n_en_pipe_always_5
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_always_5 ),
.res ( res_pow_n_en_pipe_always_5 )
);
pow_n_en_pipe_struct
# (.w (w), .n (6))
i_pow_n_en_pipe_struct_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_struct_6 ),
.res ( res_pow_n_en_pipe_struct_6 )
);
pow_n_en_pipe_always
# (.w (w), .n (6))
i_pow_n_en_pipe_always_6
(
.clk ( clk ),
.rst_n ( rst_n ),
.clk_en ( clk_en ),
.arg_vld ( arg_vld ),
.arg ( arg ),
.res_vld ( res_vld_pow_n_en_pipe_always_6 ),
.res ( res_pow_n_en_pipe_always_6 )
);
initial
begin
clk = 0;
forever
# 10 clk = ! clk;
end
initial
begin
clk_en <= 1'b1;
arg_vld <= 1'b0;
repeat (2) @ (posedge clk);
rst_n <= 0;
repeat (2) @ (posedge clk);
rst_n <= 1;
end
integer i;
initial
begin
#0
$dumpvars;
@ (posedge rst_n);
repeat (10) @ (posedge clk);
arg <= 3;
arg_vld <= 1;
@ (posedge clk);
arg_vld <= 0;
repeat (10) @ (posedge clk);
@ (posedge clk);
for (i = 0; i < 50; i = i + 1)
begin
arg <= i & 7;
arg_vld <= (i == 0 || res_vld_pow_5_en_multi_cycle_struct);
@ (posedge clk);
end
repeat (10) @ (posedge clk);
for (i = 0; i < 50; i = i + 1)
begin
arg <= i & 7;
arg_vld <= 1;
@ (posedge clk);
end
$stop;
end
reg [31:0] checks;
always @ (posedge clk)
begin
checks [ 0] = ( res_vld_pow_5_single_cycle_struct
=== res_vld_pow_5_single_cycle_always );
checks [ 1] = ( res_vld_pow_5_multi_cycle_struct
=== res_vld_pow_5_multi_cycle_always );
checks [ 2] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_n_pipe_struct_5 );
checks [ 3] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_pipe_always );
checks [ 4] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_pipe_always_with_array );
checks [ 5] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_n_pipe_always_5 );
checks [ 6] = ( res_vld_pow_n_pipe_struct_6
=== res_vld_pow_n_pipe_always_6 );
checks [ 7] = ( res_pow_5_single_cycle_struct
=== res_pow_5_single_cycle_always );
checks [ 8] = ( res_pow_5_multi_cycle_struct
=== res_pow_5_multi_cycle_always );
checks [ 9] = ( res_pow_5_pipe_struct
=== res_pow_n_pipe_struct_5 );
checks [10] = ( res_pow_5_pipe_struct
=== res_pow_5_pipe_always );
checks [11] = ( res_pow_5_pipe_struct
=== res_pow_5_pipe_always_with_array );
checks [12] = ( res_pow_5_pipe_struct
=== res_pow_n_pipe_always_5 );
checks [13] = ( res_pow_n_pipe_struct_6
=== res_pow_n_pipe_always_6 );
checks [14] = ( res_vld_pow_5_en_single_cycle_struct
=== res_vld_pow_5_en_single_cycle_always );
checks [15] = ( res_vld_pow_5_en_multi_cycle_struct
=== res_vld_pow_5_en_multi_cycle_always );
checks [16] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_n_en_pipe_struct_5 );
checks [17] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_5_en_pipe_always );
checks [18] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_5_en_pipe_always_with_array );
checks [19] = ( res_vld_pow_5_en_pipe_struct
=== res_vld_pow_n_en_pipe_always_5 );
checks [20] = ( res_vld_pow_n_en_pipe_struct_6
=== res_vld_pow_n_en_pipe_always_6 );
checks [21] = ( res_pow_5_en_single_cycle_struct
=== res_pow_5_en_single_cycle_always );
checks [22] = ( res_pow_5_en_multi_cycle_struct
=== res_pow_5_en_multi_cycle_always );
checks [23] = ( res_pow_5_en_pipe_struct
=== res_pow_n_en_pipe_struct_5 );
checks [24] = ( res_pow_5_en_pipe_struct
=== res_pow_5_en_pipe_always );
checks [25] = ( res_pow_5_en_pipe_struct
=== res_pow_5_en_pipe_always_with_array );
checks [26] = ( res_pow_5_en_pipe_struct
=== res_pow_n_en_pipe_always_5 );
checks [27] = ( res_pow_n_en_pipe_struct_6
=== res_pow_n_en_pipe_always_6 );
checks [28] = ( res_vld_pow_5_single_cycle_struct
=== res_vld_pow_5_en_single_cycle_struct );
checks [29] = ( res_vld_pow_5_multi_cycle_struct
=== res_vld_pow_5_en_multi_cycle_struct );
checks [30] = ( res_vld_pow_5_pipe_struct
=== res_vld_pow_5_en_pipe_struct );
checks [31] = ( res_vld_pow_n_pipe_struct_6
=== res_vld_pow_n_en_pipe_struct_6 );
if ((~ checks) != 0)
$display ("Something went wrong %b", checks);
end
endmodule | 16 |
4,604 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/06_syn_pow_5_multi_cycle_always/pow_5_multi_cycle_always.v | 110,151,336 | pow_5_multi_cycle_always.v | v | 51 | 64 | [] | [] | [] | [(1, 50)] | null | data/verilator_xmls/e962838f-1fbf-4949-b2ef-8908bd6a58b9.xml | null | 2,955 | module | module pow_5_multi_cycle_always
# (
parameter w = 8
)
(
input clk,
input rst_n,
input arg_vld,
input [w - 1:0] arg,
output res_vld,
output [w - 1:0] res
);
reg arg_vld_q;
reg [w - 1:0] arg_q;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
arg_vld_q <= 1'b0;
else
arg_vld_q <= arg_vld;
always @ (posedge clk)
if (arg_vld)
arg_q <= arg;
reg [3:0] shift;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
shift <= 4'b0;
else if (arg_vld_q)
shift <= 4'b1000;
else
shift <= shift >> 1;
assign res_vld = shift [0];
reg [w - 1:0] mul_q;
wire [w - 1:0] mul_d = (arg_vld_q ? arg_q : mul_q) * arg_q;
always @(posedge clk)
if (arg_vld_q || shift [3:1] != 3'b0)
mul_q <= mul_d;
assign res = mul_q;
endmodule | module pow_5_multi_cycle_always
# (
parameter w = 8
)
(
input clk,
input rst_n,
input arg_vld,
input [w - 1:0] arg,
output res_vld,
output [w - 1:0] res
); |
reg arg_vld_q;
reg [w - 1:0] arg_q;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
arg_vld_q <= 1'b0;
else
arg_vld_q <= arg_vld;
always @ (posedge clk)
if (arg_vld)
arg_q <= arg;
reg [3:0] shift;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
shift <= 4'b0;
else if (arg_vld_q)
shift <= 4'b1000;
else
shift <= shift >> 1;
assign res_vld = shift [0];
reg [w - 1:0] mul_q;
wire [w - 1:0] mul_d = (arg_vld_q ? arg_q : mul_q) * arg_q;
always @(posedge clk)
if (arg_vld_q || shift [3:1] != 3'b0)
mul_q <= mul_d;
assign res = mul_q;
endmodule | 16 |
4,613 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/reg_rst_n.v | 110,151,336 | reg_rst_n.v | v | 19 | 44 | [] | [] | [] | [(1, 18)] | null | data/verilator_xmls/f8b0bca5-ca99-4e97-b9c9-d4c93cc1de65.xml | null | 2,986 | module | module reg_rst_n
# (
parameter w = 1
)
(
input clk,
input rst_n,
input [w - 1:0] d,
output reg [w - 1:0] q
);
always @ (posedge clk or negedge rst_n)
if (! rst_n)
q <= { w { 1'b0 } };
else
q <= d;
endmodule | module reg_rst_n
# (
parameter w = 1
)
(
input clk,
input rst_n,
input [w - 1:0] d,
output reg [w - 1:0] q
); |
always @ (posedge clk or negedge rst_n)
if (! rst_n)
q <= { w { 1'b0 } };
else
q <= d;
endmodule | 16 |
4,615 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/display_driver.v | 110,151,336 | display_driver.v | v | 50 | 58 | [] | [] | [] | [(1, 49)] | null | data/verilator_xmls/1ea171c7-1084-4fc0-899a-e907ed66c16d.xml | null | 2,989 | module | module display_driver
(
input en,
input [3:0] dig,
input dot,
output [7:0] _gfedcba
);
reg [6:0] gfedcba;
always @*
if (! en)
gfedcba = 7'b1111111;
else
case (dig)
4'h0: gfedcba = 7'b1000000;
4'h1: gfedcba = 7'b1111001;
4'h2: gfedcba = 7'b0100100;
4'h3: gfedcba = 7'b0110000;
4'h4: gfedcba = 7'b0011001;
4'h5: gfedcba = 7'b0010010;
4'h6: gfedcba = 7'b0000010;
4'h7: gfedcba = 7'b1111000;
4'h8: gfedcba = 7'b0000000;
4'h9: gfedcba = 7'b0010000;
4'ha: gfedcba = 7'b0001000;
4'hb: gfedcba = 7'b0000011;
4'hc: gfedcba = 7'b1000110;
4'hd: gfedcba = 7'b0100001;
4'he: gfedcba = 7'b0000110;
4'hf: gfedcba = 7'b0001110;
endcase
assign _gfedcba = { ~ dot, gfedcba };
endmodule | module display_driver
(
input en,
input [3:0] dig,
input dot,
output [7:0] _gfedcba
); |
reg [6:0] gfedcba;
always @*
if (! en)
gfedcba = 7'b1111111;
else
case (dig)
4'h0: gfedcba = 7'b1000000;
4'h1: gfedcba = 7'b1111001;
4'h2: gfedcba = 7'b0100100;
4'h3: gfedcba = 7'b0110000;
4'h4: gfedcba = 7'b0011001;
4'h5: gfedcba = 7'b0010010;
4'h6: gfedcba = 7'b0000010;
4'h7: gfedcba = 7'b1111000;
4'h8: gfedcba = 7'b0000000;
4'h9: gfedcba = 7'b0010000;
4'ha: gfedcba = 7'b0001000;
4'hb: gfedcba = 7'b0000011;
4'hc: gfedcba = 7'b1000110;
4'hd: gfedcba = 7'b0100001;
4'he: gfedcba = 7'b0000110;
4'hf: gfedcba = 7'b0001110;
endcase
assign _gfedcba = { ~ dot, gfedcba };
endmodule | 16 |
4,616 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/strobe_generator.v | 110,151,336 | strobe_generator.v | v | 26 | 47 | [] | [] | [] | [(1, 25)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/strobe_generator.v:23: Operator EQ expects 24 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance strobe_generator\n strobe <= (cnt [w - 1:0] == 1\'b0);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,990 | module | module strobe_generator
# (
parameter w = 24
)
(
input clk,
input rst_n,
output reg strobe
);
reg [w - 1:0] cnt;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
cnt <= { w { 1'b0 } };
else
cnt <= cnt + 1'b1;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
strobe <= 1'b0;
else
strobe <= (cnt [w - 1:0] == 1'b0);
endmodule | module strobe_generator
# (
parameter w = 24
)
(
input clk,
input rst_n,
output reg strobe
); |
reg [w - 1:0] cnt;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
cnt <= { w { 1'b0 } };
else
cnt <= cnt + 1'b1;
always @ (posedge clk or negedge rst_n)
if (! rst_n)
strobe <= 1'b0;
else
strobe <= (cnt [w - 1:0] == 1'b0);
endmodule | 16 |
4,617 | data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v | 110,151,336 | board_wrapper.v | v | 77 | 79 | [] | [] | [] | [(1, 76)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:27: Cannot find file containing module: 'clk_divider'\n clk_divider # (.w (24)) i_clk_divider\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite,data/full_repos/permissive/110151336/clk_divider\n data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite,data/full_repos/permissive/110151336/clk_divider.v\n data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite,data/full_repos/permissive/110151336/clk_divider.sv\n clk_divider\n clk_divider.v\n clk_divider.sv\n obj_dir/clk_divider\n obj_dir/clk_divider.v\n obj_dir/clk_divider.sv\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:34: Cannot find file containing module: 'global'\n global gclk (divided_clk, slow_clk);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:38: Cannot find file containing module: 'strobe_generator'\n strobe_generator # (.w (24)) i_strobe_generator\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:49: Cannot find file containing module: 'board_independent_wrapper'\n board_independent_wrapper i_board_independent_wrapper\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:69: Cannot find file containing module: 'display_driver'\n display_driver i_digit_5 (disp_en [5], disp [23:20], disp_dot [5] , HEX5);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:70: Cannot find file containing module: 'display_driver'\n display_driver i_digit_4 (disp_en [4], disp [19:16], disp_dot [4] , HEX4);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:71: Cannot find file containing module: 'display_driver'\n display_driver i_digit_3 (disp_en [3], disp [15:12], disp_dot [3] , HEX3);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:72: Cannot find file containing module: 'display_driver'\n display_driver i_digit_2 (disp_en [2], disp [11: 8], disp_dot [2] , HEX2);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:73: Cannot find file containing module: 'display_driver'\n display_driver i_digit_1 (disp_en [1], disp [ 7: 4], disp_dot [1] , HEX1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/de10_lite/board_wrapper.v:74: Cannot find file containing module: 'display_driver'\n display_driver i_digit_0 (disp_en [0], disp [ 3: 0], disp_dot [0] , HEX0);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n" | 2,991 | module | module board_wrapper
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
output [ 7:0] HEX5,
inout [35:0] GPIO
);
wire fast_clk = MAX10_CLK1_50;
wire rst_n = ~ SW [9];
wire divided_clk, slow_clk;
clk_divider # (.w (24)) i_clk_divider
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.divided_clk ( divided_clk )
);
global gclk (divided_clk, slow_clk);
wire fast_clk_en;
strobe_generator # (.w (24)) i_strobe_generator
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.strobe ( fast_clk_en )
);
wire [ 7:0] disp_en;
wire [31:0] disp;
wire [ 7:0] disp_dot;
board_independent_wrapper i_board_independent_wrapper
(
.fast_clk ( fast_clk ),
.slow_clk ( slow_clk ),
.rst_n ( rst_n ),
.fast_clk_en ( fast_clk_en ),
.key ( { 2'b0, ~ KEY [ 1:0] } ),
.sw ( SW [ 7:0] ),
.led ( LEDR [ 7:0] ),
.disp_en ( disp_en [ 7:0] ),
.disp ( disp [31:0] ),
.disp_dot ( disp_dot [ 7:0] )
);
wire unused = ADC_CLK_10
& MAX10_CLK2_50
& SW [8]
& (GPIO == 36'b0);
display_driver i_digit_5 (disp_en [5], disp [23:20], disp_dot [5] , HEX5);
display_driver i_digit_4 (disp_en [4], disp [19:16], disp_dot [4] , HEX4);
display_driver i_digit_3 (disp_en [3], disp [15:12], disp_dot [3] , HEX3);
display_driver i_digit_2 (disp_en [2], disp [11: 8], disp_dot [2] , HEX2);
display_driver i_digit_1 (disp_en [1], disp [ 7: 4], disp_dot [1] , HEX1);
display_driver i_digit_0 (disp_en [0], disp [ 3: 0], disp_dot [0] , HEX0);
endmodule | module board_wrapper
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
output [ 7:0] HEX5,
inout [35:0] GPIO
); |
wire fast_clk = MAX10_CLK1_50;
wire rst_n = ~ SW [9];
wire divided_clk, slow_clk;
clk_divider # (.w (24)) i_clk_divider
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.divided_clk ( divided_clk )
);
global gclk (divided_clk, slow_clk);
wire fast_clk_en;
strobe_generator # (.w (24)) i_strobe_generator
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.strobe ( fast_clk_en )
);
wire [ 7:0] disp_en;
wire [31:0] disp;
wire [ 7:0] disp_dot;
board_independent_wrapper i_board_independent_wrapper
(
.fast_clk ( fast_clk ),
.slow_clk ( slow_clk ),
.rst_n ( rst_n ),
.fast_clk_en ( fast_clk_en ),
.key ( { 2'b0, ~ KEY [ 1:0] } ),
.sw ( SW [ 7:0] ),
.led ( LEDR [ 7:0] ),
.disp_en ( disp_en [ 7:0] ),
.disp ( disp [31:0] ),
.disp_dot ( disp_dot [ 7:0] )
);
wire unused = ADC_CLK_10
& MAX10_CLK2_50
& SW [8]
& (GPIO == 36'b0);
display_driver i_digit_5 (disp_en [5], disp [23:20], disp_dot [5] , HEX5);
display_driver i_digit_4 (disp_en [4], disp [19:16], disp_dot [4] , HEX4);
display_driver i_digit_3 (disp_en [3], disp [15:12], disp_dot [3] , HEX3);
display_driver i_digit_2 (disp_en [2], disp [11: 8], disp_dot [2] , HEX2);
display_driver i_digit_1 (disp_en [1], disp [ 7: 4], disp_dot [1] , HEX1);
display_driver i_digit_0 (disp_en [0], disp [ 3: 0], disp_dot [0] , HEX0);
endmodule | 16 |
4,618 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/002_combinational_unstructured/isqrt.v | 110,151,336 | isqrt.v | v | 35 | 30 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/002_combinational_unstructured/isqrt.v:13: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h40000000\' generates 31 bits.\n : ... In instance isqrt\n m = 31\'h4000_0000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,992 | module | module isqrt
(
input [31:0] x,
output reg [15:0] y
);
reg [31:0] m, tx, ty, b;
always @*
begin
m = 31'h4000_0000;
tx = x;
ty = 0;
repeat (16)
begin
b = ty | m;
ty = ty >> 1;
if (tx >= b)
begin
tx = tx - b;
ty = ty | m;
end
m = m >> 2;
end
y = ty [15:0];
end
endmodule | module isqrt
(
input [31:0] x,
output reg [15:0] y
); |
reg [31:0] m, tx, ty, b;
always @*
begin
m = 31'h4000_0000;
tx = x;
ty = 0;
repeat (16)
begin
b = ty | m;
ty = ty >> 1;
if (tx >= b)
begin
tx = tx - b;
ty = ty | m;
end
m = m >> 2;
end
y = ty [15:0];
end
endmodule | 16 |
4,620 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/003_sequential/isqrt.v | 110,151,336 | isqrt.v | v | 74 | 47 | [] | [] | [] | null | line:75: before: "parameter" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/003_sequential/isqrt.v:24: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h40000000\' generates 31 bits.\n : ... In instance isqrt\n m = 31\'h4000_0000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 2,995 | module | module isqrt
(
input clock,
input reset_n,
input run,
input [31:0] x,
output reg ready,
output reg [15:0] y
);
reg [31:0] m, r_m;
reg [31:0] tx, r_tx;
reg [31:0] ty, r_ty;
reg [31:0] b, r_b;
reg new_ready;
always @*
begin
if (run)
begin
m = 31'h4000_0000;
tx = x;
ty = 0;
end
else
begin
m = r_m;
tx = r_tx;
ty = r_ty;
end
b = ty | m;
ty = ty >> 1;
if (tx >= b)
begin
tx = tx - b;
ty = ty | m;
end
new_ready = m [0];
m = m >> 2;
end
always @(posedge clock or negedge reset_n)
begin
if (! reset_n)
begin
ready <= 0;
y <= 0;
end
else if (new_ready)
begin
ready <= 1;
y <= ty [15:0];
end
else
begin
ready <= 0;
r_m <= m;
r_tx <= tx;
r_ty <= ty;
r_b <= b;
end
end
endmodule | module isqrt
(
input clock,
input reset_n,
input run,
input [31:0] x,
output reg ready,
output reg [15:0] y
); |
reg [31:0] m, r_m;
reg [31:0] tx, r_tx;
reg [31:0] ty, r_ty;
reg [31:0] b, r_b;
reg new_ready;
always @*
begin
if (run)
begin
m = 31'h4000_0000;
tx = x;
ty = 0;
end
else
begin
m = r_m;
tx = r_tx;
ty = r_ty;
end
b = ty | m;
ty = ty >> 1;
if (tx >= b)
begin
tx = tx - b;
ty = ty | m;
end
new_ready = m [0];
m = m >> 2;
end
always @(posedge clock or negedge reset_n)
begin
if (! reset_n)
begin
ready <= 0;
y <= 0;
end
else if (new_ready)
begin
ready <= 1;
y <= ty [15:0];
end
else
begin
ready <= 0;
r_m <= m;
r_tx <= tx;
r_ty <= ty;
r_b <= b;
end
end
endmodule | 16 |
4,621 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v | 110,151,336 | isqrt.v | v | 36 | 73 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:16: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 0 * 2) i00 (wx [ 0], wy [ 0], wx [ 1], wy [ 1]);\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate,data/full_repos/permissive/110151336/isqrt_slice\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate,data/full_repos/permissive/110151336/isqrt_slice.v\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate,data/full_repos/permissive/110151336/isqrt_slice.sv\n isqrt_slice\n isqrt_slice.v\n isqrt_slice.sv\n obj_dir/isqrt_slice\n obj_dir/isqrt_slice.v\n obj_dir/isqrt_slice.sv\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:17: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 1 * 2) i01 (wx [ 1], wy [ 1], wx [ 2], wy [ 2]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:18: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 2 * 2) i02 (wx [ 2], wy [ 2], wx [ 3], wy [ 3]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:19: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 3 * 2) i03 (wx [ 3], wy [ 3], wx [ 4], wy [ 4]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:20: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 4 * 2) i04 (wx [ 4], wy [ 4], wx [ 5], wy [ 5]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:21: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 5 * 2) i05 (wx [ 5], wy [ 5], wx [ 6], wy [ 6]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:22: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 6 * 2) i06 (wx [ 6], wy [ 6], wx [ 7], wy [ 7]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:23: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 7 * 2) i07 (wx [ 7], wy [ 7], wx [ 8], wy [ 8]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:24: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 8 * 2) i08 (wx [ 8], wy [ 8], wx [ 9], wy [ 9]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:25: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 9 * 2) i09 (wx [ 9], wy [ 9], wx [10], wy [10]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:26: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 10 * 2) i10 (wx [10], wy [10], wx [11], wy [11]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:27: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 11 * 2) i11 (wx [11], wy [11], wx [12], wy [12]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:28: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 12 * 2) i12 (wx [12], wy [12], wx [13], wy [13]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:29: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 13 * 2) i13 (wx [13], wy [13], wx [14], wy [14]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:30: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 14 * 2) i14 (wx [14], wy [14], wx [15], wy [15]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:31: Cannot find file containing module: \'isqrt_slice\'\n isqrt_slice #(m >> 15 * 2) i15 (wx [15], wy [15], wx [16], wy [16]);\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt.v:33: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n : ... In instance isqrt\n assign y = wy [16];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 16 error(s), 1 warning(s)\n' | 2,998 | module | module isqrt
(
input [31:0] x,
output [15:0] y
);
localparam [31:0] m = 32'h4000_0000;
wire [31:0] wx [0:16], wy [0:16];
assign wx [0] = x;
assign wy [0] = 0;
isqrt_slice #(m >> 0 * 2) i00 (wx [ 0], wy [ 0], wx [ 1], wy [ 1]);
isqrt_slice #(m >> 1 * 2) i01 (wx [ 1], wy [ 1], wx [ 2], wy [ 2]);
isqrt_slice #(m >> 2 * 2) i02 (wx [ 2], wy [ 2], wx [ 3], wy [ 3]);
isqrt_slice #(m >> 3 * 2) i03 (wx [ 3], wy [ 3], wx [ 4], wy [ 4]);
isqrt_slice #(m >> 4 * 2) i04 (wx [ 4], wy [ 4], wx [ 5], wy [ 5]);
isqrt_slice #(m >> 5 * 2) i05 (wx [ 5], wy [ 5], wx [ 6], wy [ 6]);
isqrt_slice #(m >> 6 * 2) i06 (wx [ 6], wy [ 6], wx [ 7], wy [ 7]);
isqrt_slice #(m >> 7 * 2) i07 (wx [ 7], wy [ 7], wx [ 8], wy [ 8]);
isqrt_slice #(m >> 8 * 2) i08 (wx [ 8], wy [ 8], wx [ 9], wy [ 9]);
isqrt_slice #(m >> 9 * 2) i09 (wx [ 9], wy [ 9], wx [10], wy [10]);
isqrt_slice #(m >> 10 * 2) i10 (wx [10], wy [10], wx [11], wy [11]);
isqrt_slice #(m >> 11 * 2) i11 (wx [11], wy [11], wx [12], wy [12]);
isqrt_slice #(m >> 12 * 2) i12 (wx [12], wy [12], wx [13], wy [13]);
isqrt_slice #(m >> 13 * 2) i13 (wx [13], wy [13], wx [14], wy [14]);
isqrt_slice #(m >> 14 * 2) i14 (wx [14], wy [14], wx [15], wy [15]);
isqrt_slice #(m >> 15 * 2) i15 (wx [15], wy [15], wx [16], wy [16]);
assign y = wy [16];
endmodule | module isqrt
(
input [31:0] x,
output [15:0] y
); |
localparam [31:0] m = 32'h4000_0000;
wire [31:0] wx [0:16], wy [0:16];
assign wx [0] = x;
assign wy [0] = 0;
isqrt_slice #(m >> 0 * 2) i00 (wx [ 0], wy [ 0], wx [ 1], wy [ 1]);
isqrt_slice #(m >> 1 * 2) i01 (wx [ 1], wy [ 1], wx [ 2], wy [ 2]);
isqrt_slice #(m >> 2 * 2) i02 (wx [ 2], wy [ 2], wx [ 3], wy [ 3]);
isqrt_slice #(m >> 3 * 2) i03 (wx [ 3], wy [ 3], wx [ 4], wy [ 4]);
isqrt_slice #(m >> 4 * 2) i04 (wx [ 4], wy [ 4], wx [ 5], wy [ 5]);
isqrt_slice #(m >> 5 * 2) i05 (wx [ 5], wy [ 5], wx [ 6], wy [ 6]);
isqrt_slice #(m >> 6 * 2) i06 (wx [ 6], wy [ 6], wx [ 7], wy [ 7]);
isqrt_slice #(m >> 7 * 2) i07 (wx [ 7], wy [ 7], wx [ 8], wy [ 8]);
isqrt_slice #(m >> 8 * 2) i08 (wx [ 8], wy [ 8], wx [ 9], wy [ 9]);
isqrt_slice #(m >> 9 * 2) i09 (wx [ 9], wy [ 9], wx [10], wy [10]);
isqrt_slice #(m >> 10 * 2) i10 (wx [10], wy [10], wx [11], wy [11]);
isqrt_slice #(m >> 11 * 2) i11 (wx [11], wy [11], wx [12], wy [12]);
isqrt_slice #(m >> 12 * 2) i12 (wx [12], wy [12], wx [13], wy [13]);
isqrt_slice #(m >> 13 * 2) i13 (wx [13], wy [13], wx [14], wy [14]);
isqrt_slice #(m >> 14 * 2) i14 (wx [14], wy [14], wx [15], wy [15]);
isqrt_slice #(m >> 15 * 2) i15 (wx [15], wy [15], wx [16], wy [16]);
assign y = wy [16];
endmodule | 16 |
4,622 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/004_combinational_structured_no_generate/isqrt_slice.v | 110,151,336 | isqrt_slice.v | v | 18 | 46 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/7a2e7879-7fcd-40bf-9efb-410a91320b57.xml | null | 2,999 | module | module isqrt_slice
(
input [31:0] ix,
input [31:0] iy,
output [31:0] ox,
output [31:0] oy
);
parameter [31:0] m = 32'h4000_0000;
wire [31:0] b = iy | m;
wire x_ge_b = ix >= b;
assign ox = x_ge_b ? ix - b : ix;
assign oy = (iy >> 1) | (x_ge_b ? m : 0);
endmodule | module isqrt_slice
(
input [31:0] ix,
input [31:0] iy,
output [31:0] ox,
output [31:0] oy
); |
parameter [31:0] m = 32'h4000_0000;
wire [31:0] b = iy | m;
wire x_ge_b = ix >= b;
assign ox = x_ge_b ? ix - b : ix;
assign oy = (iy >> 1) | (x_ge_b ? m : 0);
endmodule | 16 |
4,624 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/isqrt.v | 110,151,336 | isqrt.v | v | 47 | 52 | [] | [] | [] | [(3, 46)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/isqrt.v:21: Cannot find file containing module: \'isqrt_slice_reg\'\n isqrt_slice_reg #(.m (m >> i * 2)) inst\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages,data/full_repos/permissive/110151336/isqrt_slice_reg\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages,data/full_repos/permissive/110151336/isqrt_slice_reg.v\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages,data/full_repos/permissive/110151336/isqrt_slice_reg.sv\n isqrt_slice_reg\n isqrt_slice_reg.v\n isqrt_slice_reg.sv\n obj_dir/isqrt_slice_reg\n obj_dir/isqrt_slice_reg.v\n obj_dir/isqrt_slice_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/isqrt.v:44: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n : ... In instance isqrt\n assign y = oy [15];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 3,010 | module | module isqrt
(
input clock,
input reset_n,
input [31:0] x,
output [15:0] y
);
localparam [31:0] m = 32'h4000_0000;
wire [31:0] ix [0:15], iy [0:15];
wire [31:0] ox [0:15], oy [0:15];
generate
genvar i;
for (i = 0; i < 16; i = i + 1)
begin : u
isqrt_slice_reg #(.m (m >> i * 2)) inst
(
.clock ( clock ),
.reset_n ( reset_n ),
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
for (i = 1; i < 16; i = i + 1)
begin : v
assign ix [i] = ox [i - 1];
assign iy [i] = oy [i - 1];
end
endgenerate
assign ix [0] = x;
assign iy [0] = 0;
assign y = oy [15];
endmodule | module isqrt
(
input clock,
input reset_n,
input [31:0] x,
output [15:0] y
); |
localparam [31:0] m = 32'h4000_0000;
wire [31:0] ix [0:15], iy [0:15];
wire [31:0] ox [0:15], oy [0:15];
generate
genvar i;
for (i = 0; i < 16; i = i + 1)
begin : u
isqrt_slice_reg #(.m (m >> i * 2)) inst
(
.clock ( clock ),
.reset_n ( reset_n ),
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
for (i = 1; i < 16; i = i + 1)
begin : v
assign ix [i] = ox [i - 1];
assign iy [i] = oy [i - 1];
end
endgenerate
assign ix [0] = x;
assign iy [0] = 0;
assign y = oy [15];
endmodule | 16 |
4,627 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v | 110,151,336 | de1.v | v | 250 | 78 | [] | [] | [] | [(43, 249)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:238: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SW\' generates 10 bits.\n : ... In instance de1\nassign x = SW;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:239: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'y\' generates 16 bits.\n : ... In instance de1\nassign LEDR = y;\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:241: Cannot find file containing module: \'isqrt\'\nisqrt isqrt\n^~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt.v\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt.sv\n isqrt\n isqrt.v\n isqrt.sv\n obj_dir/isqrt\n obj_dir/isqrt.v\n obj_dir/isqrt.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 3,014 | module | module de1
(
CLOCK_24,
CLOCK_27,
CLOCK_50,
EXT_CLOCK,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
LEDG,
LEDR,
UART_TXD,
UART_RXD,
DRAM_DQ,
DRAM_ADDR,
DRAM_LDQM,
DRAM_UDQM,
DRAM_WE_N,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CS_N,
DRAM_BA_0,
DRAM_BA_1,
DRAM_CLK,
DRAM_CKE,
FL_DQ,
FL_ADDR,
FL_WE_N,
FL_RST_N,
FL_OE_N,
FL_CE_N,
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N,
SD_DAT,
SD_DAT3,
SD_CMD,
SD_CLK,
TDI,
TCK,
TCS,
TDO,
I2C_SDAT,
I2C_SCLK,
PS2_DAT,
PS2_CLK,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B,
AUD_ADCLRCK,
AUD_ADCDAT,
AUD_DACLRCK,
AUD_DACDAT,
AUD_BCLK,
AUD_XCK,
GPIO_0,
GPIO_1
);
input [1:0] CLOCK_24;
input [1:0] CLOCK_27;
input CLOCK_50;
input EXT_CLOCK;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [7:0] LEDG;
output [9:0] LEDR;
output UART_TXD;
input UART_RXD;
inout [15:0] DRAM_DQ;
output [11:0] DRAM_ADDR;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_WE_N;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CS_N;
output DRAM_BA_0;
output DRAM_BA_1;
output DRAM_CLK;
output DRAM_CKE;
inout [7:0] FL_DQ;
output [21:0] FL_ADDR;
output FL_WE_N;
output FL_RST_N;
output FL_OE_N;
output FL_CE_N;
inout [15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
output SRAM_UB_N;
output SRAM_LB_N;
output SRAM_WE_N;
output SRAM_CE_N;
output SRAM_OE_N;
inout SD_DAT;
inout SD_DAT3;
inout SD_CMD;
output SD_CLK;
inout I2C_SDAT;
output I2C_SCLK;
input PS2_DAT;
input PS2_CLK;
input TDI;
input TCK;
input TCS;
output TDO;
output VGA_HS;
output VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
inout AUD_ADCLRCK;
input AUD_ADCDAT;
inout AUD_DACLRCK;
output AUD_DACDAT;
inout AUD_BCLK;
output AUD_XCK;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
`ifdef COMMENTED_OUT
assign HEX0 = 7'h00;
assign HEX1 = 7'h00;
assign HEX2 = 7'h00;
assign HEX3 = 7'h00;
assign LEDG = 8'hFF;
assign LEDR = 10'h3FF;
`endif
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 1'bz;
assign I2C_SDAT = 1'bz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_BCLK = 1'bz;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire [31:0] x;
wire [15:0] y;
assign x = SW;
assign LEDR = y;
isqrt isqrt
(
.clock ( CLOCK_50 ),
.reset_n ( KEY [3] ),
.x ( x ),
.y ( y )
);
endmodule | module de1
(
CLOCK_24,
CLOCK_27,
CLOCK_50,
EXT_CLOCK,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
LEDG,
LEDR,
UART_TXD,
UART_RXD,
DRAM_DQ,
DRAM_ADDR,
DRAM_LDQM,
DRAM_UDQM,
DRAM_WE_N,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CS_N,
DRAM_BA_0,
DRAM_BA_1,
DRAM_CLK,
DRAM_CKE,
FL_DQ,
FL_ADDR,
FL_WE_N,
FL_RST_N,
FL_OE_N,
FL_CE_N,
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N,
SD_DAT,
SD_DAT3,
SD_CMD,
SD_CLK,
TDI,
TCK,
TCS,
TDO,
I2C_SDAT,
I2C_SCLK,
PS2_DAT,
PS2_CLK,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B,
AUD_ADCLRCK,
AUD_ADCDAT,
AUD_DACLRCK,
AUD_DACDAT,
AUD_BCLK,
AUD_XCK,
GPIO_0,
GPIO_1
); |
input [1:0] CLOCK_24;
input [1:0] CLOCK_27;
input CLOCK_50;
input EXT_CLOCK;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [7:0] LEDG;
output [9:0] LEDR;
output UART_TXD;
input UART_RXD;
inout [15:0] DRAM_DQ;
output [11:0] DRAM_ADDR;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_WE_N;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CS_N;
output DRAM_BA_0;
output DRAM_BA_1;
output DRAM_CLK;
output DRAM_CKE;
inout [7:0] FL_DQ;
output [21:0] FL_ADDR;
output FL_WE_N;
output FL_RST_N;
output FL_OE_N;
output FL_CE_N;
inout [15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
output SRAM_UB_N;
output SRAM_LB_N;
output SRAM_WE_N;
output SRAM_CE_N;
output SRAM_OE_N;
inout SD_DAT;
inout SD_DAT3;
inout SD_CMD;
output SD_CLK;
inout I2C_SDAT;
output I2C_SCLK;
input PS2_DAT;
input PS2_CLK;
input TDI;
input TCK;
input TCS;
output TDO;
output VGA_HS;
output VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
inout AUD_ADCLRCK;
input AUD_ADCDAT;
inout AUD_DACLRCK;
output AUD_DACDAT;
inout AUD_BCLK;
output AUD_XCK;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
`ifdef COMMENTED_OUT
assign HEX0 = 7'h00;
assign HEX1 = 7'h00;
assign HEX2 = 7'h00;
assign HEX3 = 7'h00;
assign LEDG = 8'hFF;
assign LEDR = 10'h3FF;
`endif
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 1'bz;
assign I2C_SDAT = 1'bz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_BCLK = 1'bz;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire [31:0] x;
wire [15:0] y;
assign x = SW;
assign LEDR = y;
isqrt isqrt
(
.clock ( CLOCK_50 ),
.reset_n ( KEY [3] ),
.x ( x ),
.y ( y )
);
endmodule | 16 |
4,628 | data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v | 110,151,336 | isqrt.v | v | 65 | 66 | [] | [] | [] | [(3, 64)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v:38: Cannot find file containing module: \'isqrt_slice_reg\'\n isqrt_slice_reg #(.m (m >> i * 2)) inst\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg.v\n data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg.sv\n isqrt_slice_reg\n isqrt_slice_reg.v\n isqrt_slice_reg.sv\n obj_dir/isqrt_slice_reg\n obj_dir/isqrt_slice_reg.v\n obj_dir/isqrt_slice_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v:62: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n : ... In instance isqrt\n assign y = oy [15];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 3,015 | module | module isqrt
(
input clock,
input reset_n,
input [31:0] x,
output [15:0] y
);
parameter n_pipe_stages = 16;
localparam n_slices = 16;
localparam n_slices_per_stage = n_slices / n_pipe_stages;
localparam [31:0] m = 32'h4000_0000;
wire [31:0] ix [0:15], iy [0:15];
wire [31:0] ox [0:15], oy [0:15];
generate
genvar i;
for (i = 0; i < 16; i = i + 1)
begin : u
if (i % n_slices_per_stage != n_slices_per_stage - 1)
begin
isqrt_slice_comb #(.m (m >> i * 2)) inst
(
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
else
begin
isqrt_slice_reg #(.m (m >> i * 2)) inst
(
.clock ( clock ),
.reset_n ( reset_n ),
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
end
for (i = 1; i < 16; i = i + 1)
begin : v
assign ix [i] = ox [i - 1];
assign iy [i] = oy [i - 1];
end
endgenerate
assign ix [0] = x;
assign iy [0] = 0;
assign y = oy [15];
endmodule | module isqrt
(
input clock,
input reset_n,
input [31:0] x,
output [15:0] y
); |
parameter n_pipe_stages = 16;
localparam n_slices = 16;
localparam n_slices_per_stage = n_slices / n_pipe_stages;
localparam [31:0] m = 32'h4000_0000;
wire [31:0] ix [0:15], iy [0:15];
wire [31:0] ox [0:15], oy [0:15];
generate
genvar i;
for (i = 0; i < 16; i = i + 1)
begin : u
if (i % n_slices_per_stage != n_slices_per_stage - 1)
begin
isqrt_slice_comb #(.m (m >> i * 2)) inst
(
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
else
begin
isqrt_slice_reg #(.m (m >> i * 2)) inst
(
.clock ( clock ),
.reset_n ( reset_n ),
.ix ( ix [i] ),
.iy ( iy [i] ),
.ox ( ox [i] ),
.oy ( oy [i] )
);
end
end
for (i = 1; i < 16; i = i + 1)
begin : v
assign ix [i] = ox [i - 1];
assign iy [i] = oy [i - 1];
end
endgenerate
assign ix [0] = x;
assign iy [0] = 0;
assign y = oy [15];
endmodule | 16 |
4,630 | data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv | 110,151,336 | tb.sv | sv | 190 | 54 | [] | [] | [] | null | line:19: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n # (clock_period / 2) clock = ~ clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:48: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:52: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:58: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:62: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:69: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:79: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:83: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:90: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:100: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:104: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:111: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:121: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:125: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:132: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:142: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:146: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:153: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:163: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:167: Unsupported: for loop initialization after the first comma\n for (i = 0, n = 0; i < 10; i ++)\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:169: Unsupported or unknown PLI call: $urandom_range\n up_valid <= $urandom_range (1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:170: Unsupported or unknown PLI call: $urandom_range\n down_ready <= $urandom_range (1);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:174: syntax error, unexpected \'@\'\n @ (posedge clock);\n ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:184: syntax error, unexpected \'@\'\n repeat (5) @ (posedge clock);\n ^\n%Error: Exiting due to 23 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,020 | module | module tb;
localparam width = 8,
clock_period = 100;
reg clock;
reg reset_n;
reg [width - 1:0] up_data;
reg up_valid;
wire up_ready;
wire [width - 1:0] down_data;
wire down_valid;
reg down_ready;
top
#(.width (width))
top_inst (.*);
initial
begin
clock = 1'b1;
forever
# (clock_period / 2) clock = ~ clock;
end
wire [width - 1:0] up_data_x
= up_valid & up_ready ? up_data : 8'hx;
wire [width - 1:0] down_data_x
= down_valid & down_ready ? down_data : 8'hx;
int i, n;
initial
begin
up_valid <= 1'b0;
down_ready <= 1'b0;
reset_n <= 1'b0;
repeat (5) @ (posedge clock);
reset_n <= 1'b1;
repeat (5) @ (posedge clock);
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= 1'b1;
down_ready <= 1'b1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= 1'b1;
down_ready <= i & 1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= 1'b1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= i & 1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= ! (i & 1);
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= $urandom_range (1);
down_ready <= $urandom_range (1);
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
$finish;
end
endmodule | module tb; |
localparam width = 8,
clock_period = 100;
reg clock;
reg reset_n;
reg [width - 1:0] up_data;
reg up_valid;
wire up_ready;
wire [width - 1:0] down_data;
wire down_valid;
reg down_ready;
top
#(.width (width))
top_inst (.*);
initial
begin
clock = 1'b1;
forever
# (clock_period / 2) clock = ~ clock;
end
wire [width - 1:0] up_data_x
= up_valid & up_ready ? up_data : 8'hx;
wire [width - 1:0] down_data_x
= down_valid & down_ready ? down_data : 8'hx;
int i, n;
initial
begin
up_valid <= 1'b0;
down_ready <= 1'b0;
reset_n <= 1'b0;
repeat (5) @ (posedge clock);
reset_n <= 1'b1;
repeat (5) @ (posedge clock);
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= 1'b1;
down_ready <= 1'b1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= 1'b1;
down_ready <= i & 1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= 1'b1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= i & 1;
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= i & 1;
down_ready <= ! (i & 1);
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
for (i = 0, n = 0; i < 10; i ++)
begin
up_valid <= $urandom_range (1);
down_ready <= $urandom_range (1);
up_data <= n;
@ (posedge clock);
if (up_valid & up_ready)
n ++;
end
up_data <= 8'b0;
up_valid <= 1'b0;
down_ready <= 1'b1;
repeat (5) @ (posedge clock);
$finish;
end
endmodule | 16 |
4,631 | data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/top.sv | 110,151,336 | top.sv | sv | 170 | 72 | [] | [] | [] | null | line:154: before: "*" | data/verilator_xmls/6d4d6c1a-9578-4059-8d92-7bd9bd1e27a3.xml | null | 3,021 | module | module pipeline_stomach
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
wire stomach_load, dataout_load, dataout_unload;
reg mux_select;
wire [width - 1:0] data_in;
reg [width - 1:0] stomach_out, mux_out, data_out;
reg data_in_dataout, data_in_stomach;
assign data_in = up_data;
assign down_valid = data_in_dataout;
assign dataout_unload = down_valid & down_ready;
assign dataout_load =
(up_valid & (! data_in_dataout | dataout_unload))
| (data_in_stomach & dataout_unload);
assign stomach_load =
up_valid
& ! data_in_stomach
& (data_in_dataout & ! dataout_unload);
assign up_ready = ! data_in_stomach;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
begin
data_in_stomach <= 1'b0;
data_in_dataout <= 1'b0;
end
else
begin
data_in_stomach <= stomach_load
| (data_in_stomach & ! dataout_unload);
data_in_dataout <= dataout_load
| data_in_stomach
| (data_in_dataout & ! dataout_unload);
end
always @ (posedge clock or negedge reset_n)
if (! reset_n)
mux_select <= 1'b0;
else
mux_select <= stomach_load | (mux_select & ! dataout_load);
always @ (posedge clock or negedge reset_n)
if (! reset_n)
stomach_out <= { width { 1'b0 } };
else if (stomach_load)
stomach_out <= data_in;
always @*
mux_out = mux_select ? stomach_out : data_in;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
data_out <= { width { 1'b0 } };
else if (dataout_load)
data_out <= mux_out;
assign down_data = data_out;
endmodule | module pipeline_stomach
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
); |
wire stomach_load, dataout_load, dataout_unload;
reg mux_select;
wire [width - 1:0] data_in;
reg [width - 1:0] stomach_out, mux_out, data_out;
reg data_in_dataout, data_in_stomach;
assign data_in = up_data;
assign down_valid = data_in_dataout;
assign dataout_unload = down_valid & down_ready;
assign dataout_load =
(up_valid & (! data_in_dataout | dataout_unload))
| (data_in_stomach & dataout_unload);
assign stomach_load =
up_valid
& ! data_in_stomach
& (data_in_dataout & ! dataout_unload);
assign up_ready = ! data_in_stomach;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
begin
data_in_stomach <= 1'b0;
data_in_dataout <= 1'b0;
end
else
begin
data_in_stomach <= stomach_load
| (data_in_stomach & ! dataout_unload);
data_in_dataout <= dataout_load
| data_in_stomach
| (data_in_dataout & ! dataout_unload);
end
always @ (posedge clock or negedge reset_n)
if (! reset_n)
mux_select <= 1'b0;
else
mux_select <= stomach_load | (mux_select & ! dataout_load);
always @ (posedge clock or negedge reset_n)
if (! reset_n)
stomach_out <= { width { 1'b0 } };
else if (stomach_load)
stomach_out <= data_in;
always @*
mux_out = mux_select ? stomach_out : data_in;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
data_out <= { width { 1'b0 } };
else if (dataout_load)
data_out <= mux_out;
assign down_data = data_out;
endmodule | 16 |
4,632 | data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/top.sv | 110,151,336 | top.sv | sv | 170 | 72 | [] | [] | [] | null | line:154: before: "*" | data/verilator_xmls/6d4d6c1a-9578-4059-8d92-7bd9bd1e27a3.xml | null | 3,021 | module | module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
pipeline_stomach # (.width (width))
pipeline_stomach_inst (.*);
endmodule | module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
); |
pipeline_stomach # (.width (width))
pipeline_stomach_inst (.*);
endmodule | 16 |
4,633 | data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/top.sv | 110,151,336 | top.sv | sv | 170 | 72 | [] | [] | [] | null | line:154: before: "*" | data/verilator_xmls/6d4d6c1a-9578-4059-8d92-7bd9bd1e27a3.xml | null | 3,021 | module | module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
wire [width - 1:0] i12_data;
wire i12_valid;
wire i12_ready;
pipeline_stomach # (.width (width))
pipeline_stomach_inst_1
(
.down_data ( i12_data ),
.down_valid ( i12_valid ),
.down_ready ( i12_ready ),
.*
);
pipeline_stomach # (.width (width))
pipeline_stomach_inst_2
(
.up_data ( i12_data ),
.up_valid ( i12_valid ),
.up_ready ( i12_ready ),
.*
);
endmodule | module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
); |
wire [width - 1:0] i12_data;
wire i12_valid;
wire i12_ready;
pipeline_stomach # (.width (width))
pipeline_stomach_inst_1
(
.down_data ( i12_data ),
.down_valid ( i12_valid ),
.down_ready ( i12_ready ),
.*
);
pipeline_stomach # (.width (width))
pipeline_stomach_inst_2
(
.up_data ( i12_data ),
.up_valid ( i12_valid ),
.up_ready ( i12_ready ),
.*
);
endmodule | 16 |
4,635 | data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v | 110,151,336 | de0_cv.v | v | 89 | 63 | [] | [] | [] | [(2, 88)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:64: Cannot find file containing module: 'sm_top'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/de0_cv,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/de0_cv,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/de0_cv,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:81: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:82: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:83: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:84: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:85: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de0_cv/de0_cv.v:86: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 3,023 | module | module de0_cv
(
input CLOCK2_50,
input CLOCK3_50,
inout CLOCK4_50,
input CLOCK_50,
input RESET_N,
input [ 3:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 6:0] HEX0,
output [ 6:0] HEX1,
output [ 6:0] HEX2,
output [ 6:0] HEX3,
output [ 6:0] HEX4,
output [ 6:0] HEX5,
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
output [ 3:0] VGA_B,
output [ 3:0] VGA_G,
output VGA_HS,
output [ 3:0] VGA_R,
output VGA_VS,
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
output SD_CLK,
inout SD_CMD,
inout [ 3:0] SD_DATA,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1
);
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0] & RESET_N;
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | module de0_cv
(
input CLOCK2_50,
input CLOCK3_50,
inout CLOCK4_50,
input CLOCK_50,
input RESET_N,
input [ 3:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 6:0] HEX0,
output [ 6:0] HEX1,
output [ 6:0] HEX2,
output [ 6:0] HEX3,
output [ 6:0] HEX4,
output [ 6:0] HEX5,
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
output [ 3:0] VGA_B,
output [ 3:0] VGA_G,
output VGA_HS,
output [ 3:0] VGA_R,
output VGA_VS,
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
output SD_CLK,
inout SD_CMD,
inout [ 3:0] SD_DATA,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1
); |
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0] & RESET_N;
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | 16 |
4,639 | data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v | 110,151,336 | de10_standard.v | v | 59 | 63 | [] | [] | [] | [(3, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:34: Cannot find file containing module: 'sm_top'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:51: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:52: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:53: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:54: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:55: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:56: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 3,027 | module | module de10_standard
(
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
input [3:0] KEY,
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
);
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | module de10_standard
(
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
input [3:0] KEY,
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
); |
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | 16 |
4,640 | data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v | 110,151,336 | de1_soc.v | v | 227 | 63 | [] | [] | [] | [(22, 226)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:202: Cannot find file containing module: 'sm_top'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/de1_soc,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/de1_soc,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/de1_soc,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:219: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:220: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:221: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:222: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:223: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de1_soc/de1_soc.v:224: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 3,028 | module | module de1_soc(
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
`endif
`ifdef ENABLE_SW
input [9:0] SW
`endif
);
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | module de1_soc(
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
`endif
`ifdef ENABLE_SW
input [9:0] SW
`endif
); |
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | 16 |
4,642 | data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek/max_10_neek.v | 110,151,336 | max_10_neek.v | v | 281 | 63 | [] | [] | [] | [(27, 280)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek/max_10_neek.v:260: Cannot find file containing module: 'sm_top'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek/max_10_neek.v:277: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/max_10_neek/max_10_neek.v:278: Cannot find file containing module: 'sm_hex_display'\n sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 3,032 | module | module golden_top(
`ifdef ENABLE_ADC
input ADC_CLK_10,
`endif
`ifdef ENABLE_AUDIO
inout AUDIO_BCLK,
output AUDIO_DIN_MFP1,
input AUDIO_DOUT_MFP2,
inout AUDIO_GPIO_MFP5,
output AUDIO_MCLK,
input AUDIO_MISO_MFP4,
inout AUDIO_RESET_n,
output AUDIO_SCLK_MFP3,
output AUDIO_SCL_SS_n,
inout AUDIO_SDA_MOSI,
output AUDIO_SPI_SELECT,
inout AUDIO_WCLK,
`endif
`ifdef ENABLE_CAMERA
output CAMERA_I2C_SCL,
inout CAMERA_I2C_SDA,
output CAMERA_PWDN_n,
`endif
`ifdef ENABLE_DAC
inout DAC_DATA,
output DAC_SCLK,
output DAC_SYNC_n,
`endif
`ifdef ENABLE_DDR3
output [14:0] DDR3_A,
output [2:0] DDR3_BA,
output DDR3_CKE,
output DDR3_CAS_n,
output DDR3_CS_n,
output [2:0] DDR3_DM,
inout [23:0] DDR3_DQ,
output DDR3_ODT,
output DDR3_RAS_n,
output DDR3_RESET_n,
output DDR3_WE_n,
inout DDR3_CK_n,
inout DDR3_CK_p,
inout [2:0] DDR3_DQS_n,
inout [2:0] DDR3_DQS_p,
`endif
`ifdef ENABLE_FLASH
inout [3:0] FLASH_DATA,
output FLASH_DCLK,
output FLASH_NCSO,
output FLASH_RESET_n,
`endif
`ifdef ENABLE_GPIO
inout [7:0] GPIO,
`endif
`ifdef ENABLE_GSENSOR
output GSENSOR_CS_n,
input [2:1] GSENSOR_INT,
inout GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
`ifdef ENABLE_HDMI
input HDMI_AP,
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_LRCLK,
inout HDMI_MCLK,
input HDMI_RX_CLK,
input [23:0] HDMI_RX_D,
input HDMI_RX_DE,
inout HDMI_RX_HS,
input HDMI_RX_INT1,
inout HDMI_RX_RESET_n,
input HDMI_RX_VS,
inout HDMI_SCLK,
`endif
`ifdef ENABLE_HEX0
output [6:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [6:0] HEX1,
`endif
`ifdef ENABLE_KEY
input [4:0] KEY,
`endif
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
`ifdef ENABLE_LSENSOR
inout LSENSOR_INT,
output LSENSOR_SCL,
inout LSENSOR_SDA,
`endif
`ifdef ENABLE_MAX10
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input MAX10_CLK3_50,
`endif
`ifdef ENABLE_MIPI
output MIPI_CS_n,
output MIPI_I2C_SCL,
inout MIPI_I2C_SDA,
input MIPI_PIXEL_CLK,
input [23:0] MIPI_PIXEL_D,
input MIPI_PIXEL_HS,
input MIPI_PIXEL_VS,
output MIPI_REFCLK,
output MIPI_RESET_n,
`endif
`ifdef ENABLE_MTL2
output [7:0] MTL2_B,
inout MTL2_BL_ON_n,
output MTL2_DCLK,
output [7:0] MTL2_G,
output MTL2_HSD,
output MTL2_I2C_SCL,
inout MTL2_I2C_SDA,
input MTL2_INT,
output [7:0] MTL2_R,
output MTL2_VSD,
`endif
`ifdef ENABLE_NET
output NET_GTX_CLK,
input NET_INT_n,
input NET_LINK100,
output NET_MDC,
inout NET_MDIO,
output NET_RST_N,
input NET_RX_CLK,
input NET_RX_COL,
input NET_RX_CRS,
input [3:0] NET_RX_D,
input NET_RX_DV,
input NET_RX_ER,
input NET_TX_CLK,
output [3:0] NET_TX_D,
output NET_TX_EN,
output NET_TX_ER,
`endif
`ifdef ENABLE_PM
output PM_I2C_SCL,
inout PM_I2C_SDA,
`endif
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
`ifdef ENABLE_RH
input RH_TEMP_DRDY_n,
output RH_TEMP_I2C_SCL,
inout RH_TEMP_I2C_SDA,
`endif
`ifdef ENABLE_SD
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DATA,
`endif
`ifdef ENABLE_SW
input [9:0] SW,
`endif
`ifdef ENABLE_UART
output UART_RESET_n,
input UART_RX,
output UART_TX,
`endif
input FPGA_RESET_n
);
wire clk;
wire clkIn = MAX10_CLK1_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | module golden_top(
`ifdef ENABLE_ADC
input ADC_CLK_10,
`endif
`ifdef ENABLE_AUDIO
inout AUDIO_BCLK,
output AUDIO_DIN_MFP1,
input AUDIO_DOUT_MFP2,
inout AUDIO_GPIO_MFP5,
output AUDIO_MCLK,
input AUDIO_MISO_MFP4,
inout AUDIO_RESET_n,
output AUDIO_SCLK_MFP3,
output AUDIO_SCL_SS_n,
inout AUDIO_SDA_MOSI,
output AUDIO_SPI_SELECT,
inout AUDIO_WCLK,
`endif
`ifdef ENABLE_CAMERA
output CAMERA_I2C_SCL,
inout CAMERA_I2C_SDA,
output CAMERA_PWDN_n,
`endif
`ifdef ENABLE_DAC
inout DAC_DATA,
output DAC_SCLK,
output DAC_SYNC_n,
`endif
`ifdef ENABLE_DDR3
output [14:0] DDR3_A,
output [2:0] DDR3_BA,
output DDR3_CKE,
output DDR3_CAS_n,
output DDR3_CS_n,
output [2:0] DDR3_DM,
inout [23:0] DDR3_DQ,
output DDR3_ODT,
output DDR3_RAS_n,
output DDR3_RESET_n,
output DDR3_WE_n,
inout DDR3_CK_n,
inout DDR3_CK_p,
inout [2:0] DDR3_DQS_n,
inout [2:0] DDR3_DQS_p,
`endif
`ifdef ENABLE_FLASH
inout [3:0] FLASH_DATA,
output FLASH_DCLK,
output FLASH_NCSO,
output FLASH_RESET_n,
`endif
`ifdef ENABLE_GPIO
inout [7:0] GPIO,
`endif
`ifdef ENABLE_GSENSOR
output GSENSOR_CS_n,
input [2:1] GSENSOR_INT,
inout GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
`ifdef ENABLE_HDMI
input HDMI_AP,
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_LRCLK,
inout HDMI_MCLK,
input HDMI_RX_CLK,
input [23:0] HDMI_RX_D,
input HDMI_RX_DE,
inout HDMI_RX_HS,
input HDMI_RX_INT1,
inout HDMI_RX_RESET_n,
input HDMI_RX_VS,
inout HDMI_SCLK,
`endif
`ifdef ENABLE_HEX0
output [6:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [6:0] HEX1,
`endif
`ifdef ENABLE_KEY
input [4:0] KEY,
`endif
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
`ifdef ENABLE_LSENSOR
inout LSENSOR_INT,
output LSENSOR_SCL,
inout LSENSOR_SDA,
`endif
`ifdef ENABLE_MAX10
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input MAX10_CLK3_50,
`endif
`ifdef ENABLE_MIPI
output MIPI_CS_n,
output MIPI_I2C_SCL,
inout MIPI_I2C_SDA,
input MIPI_PIXEL_CLK,
input [23:0] MIPI_PIXEL_D,
input MIPI_PIXEL_HS,
input MIPI_PIXEL_VS,
output MIPI_REFCLK,
output MIPI_RESET_n,
`endif
`ifdef ENABLE_MTL2
output [7:0] MTL2_B,
inout MTL2_BL_ON_n,
output MTL2_DCLK,
output [7:0] MTL2_G,
output MTL2_HSD,
output MTL2_I2C_SCL,
inout MTL2_I2C_SDA,
input MTL2_INT,
output [7:0] MTL2_R,
output MTL2_VSD,
`endif
`ifdef ENABLE_NET
output NET_GTX_CLK,
input NET_INT_n,
input NET_LINK100,
output NET_MDC,
inout NET_MDIO,
output NET_RST_N,
input NET_RX_CLK,
input NET_RX_COL,
input NET_RX_CRS,
input [3:0] NET_RX_D,
input NET_RX_DV,
input NET_RX_ER,
input NET_TX_CLK,
output [3:0] NET_TX_D,
output NET_TX_EN,
output NET_TX_ER,
`endif
`ifdef ENABLE_PM
output PM_I2C_SCL,
inout PM_I2C_SDA,
`endif
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
`ifdef ENABLE_RH
input RH_TEMP_DRDY_n,
output RH_TEMP_I2C_SCL,
inout RH_TEMP_I2C_SDA,
`endif
`ifdef ENABLE_SD
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DATA,
`endif
`ifdef ENABLE_SW
input [9:0] SW,
`endif
`ifdef ENABLE_UART
output UART_RESET_n,
input UART_RX,
output UART_TX,
`endif
input FPGA_RESET_n
); |
wire clk;
wire clkIn = MAX10_CLK1_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule | 16 |
4,644 | data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr/nexys4_ddr.v | 110,151,336 | nexys4_ddr.v | v | 98 | 60 | [] | [] | [] | [(2, 97)] | null | null | 1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr/nexys4_ddr.v:51: Cannot find file containing module: 'sm_top'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr/nexys4_ddr.v:70: Cannot find file containing module: 'sm_clk_divider'\n sm_clk_divider hex_clk_divider\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/nexys4_ddr/nexys4_ddr.v:79: Cannot find file containing module: 'sm_hex_display_8'\n sm_hex_display_8 sm_hex_display_8\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 3,034 | module | module nexys4_ddr
(
input CLK100MHZ,
input CPU_RESETN,
input BTNC,
input BTNU,
input BTNL,
input BTNR,
input BTND,
input [15:0] SW,
output [15:0] LED,
output LED16_B,
output LED16_G,
output LED16_R,
output LED17_B,
output LED17_G,
output LED17_R,
output CA,
output CB,
output CC,
output CD,
output CE,
output CF,
output CG,
output DP,
output [ 7:0] AN,
inout [12:1] JA,
inout [12:1] JB,
input UART_TXD_IN
);
wire clk;
wire clkIn = CLK100MHZ;
wire rst_n = CPU_RESETN;
wire clkEnable = SW [9] | BTNU;
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LED[0] = clk;
assign LED[15:1] = regData[14:0];
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b1 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( { CG, CF, CE, CD, CC, CB, CA } ),
.dot ( DP ),
.anodes ( AN )
);
assign LED16_B = 1'b0;
assign LED16_G = 1'b0;
assign LED16_R = 1'b0;
assign LED17_B = 1'b0;
assign LED17_G = 1'b0;
assign LED17_R = 1'b0;
endmodule | module nexys4_ddr
(
input CLK100MHZ,
input CPU_RESETN,
input BTNC,
input BTNU,
input BTNL,
input BTNR,
input BTND,
input [15:0] SW,
output [15:0] LED,
output LED16_B,
output LED16_G,
output LED16_R,
output LED17_B,
output LED17_G,
output LED17_R,
output CA,
output CB,
output CC,
output CD,
output CE,
output CF,
output CG,
output DP,
output [ 7:0] AN,
inout [12:1] JA,
inout [12:1] JB,
input UART_TXD_IN
); |
wire clk;
wire clkIn = CLK100MHZ;
wire rst_n = CPU_RESETN;
wire clkEnable = SW [9] | BTNU;
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign LED[0] = clk;
assign LED[15:1] = regData[14:0];
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b1 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( { CG, CF, CE, CD, CC, CB, CA } ),
.dot ( DP ),
.anodes ( AN )
);
assign LED16_B = 1'b0;
assign LED16_G = 1'b0;
assign LED16_R = 1'b0;
assign LED17_B = 1'b0;
assign LED17_G = 1'b0;
assign LED17_R = 1'b0;
endmodule | 16 |
4,646 | data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v | 110,151,336 | zeowaa.v | v | 63 | 52 | [] | [] | [] | [(2, 62)] | null | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:22: Cannot find file containing module: \'sm_top\'\n sm_top sm_top\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top\n data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top.v\n data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top.sv\n sm_top\n sm_top.v\n sm_top.sv\n obj_dir/sm_top\n obj_dir/sm_top.v\n obj_dir/sm_top.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:35: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s NOT generates 12 bits.\n : ... In instance zeowaa\n assign led[11:1] = ~regData[11:0];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:41: Cannot find file containing module: \'sm_clk_divider\'\n sm_clk_divider hex_clk_divider\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:50: Cannot find file containing module: \'sm_hex_display_8\'\n sm_hex_display_8 sm_hex_display_8\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 3,036 | module | module zeowaa
(
input clk_50,
input [ 5:2] key,
input [ 7:0] sw,
output [11:0] led,
output [ 7:0] hex,
output [ 7:0] digit,
output buzzer
);
wire clkCpu;
wire clkIn = clk_50;
wire rst_n = key[4];
wire clkEnable = ~sw[ 7] | ~key[5];
wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
wire [ 4:0 ] regAddr = ~sw[4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign led[0] = ~clkCpu;
assign led[11:1] = ~regData[11:0];
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b0 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( hex[6:0] ),
.dot ( hex[7] ),
.anodes ( digit )
);
assign buzzer = 1'b1;
endmodule | module zeowaa
(
input clk_50,
input [ 5:2] key,
input [ 7:0] sw,
output [11:0] led,
output [ 7:0] hex,
output [ 7:0] digit,
output buzzer
); |
wire clkCpu;
wire clkIn = clk_50;
wire rst_n = key[4];
wire clkEnable = ~sw[ 7] | ~key[5];
wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
wire [ 4:0 ] regAddr = ~sw[4:0];
wire [ 31:0 ] regData;
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
assign led[0] = ~clkCpu;
assign led[11:1] = ~regData[11:0];
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b0 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( hex[6:0] ),
.dot ( hex[7] ),
.anodes ( digit )
);
assign buzzer = 1'b1;
endmodule | 16 |
4,647 | data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v | 110,151,336 | testbench.v | v | 138 | 101 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:4: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh\n data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh.v\n data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:34: syntax error, unexpected \'.\', expecting \'=\'\n defparam sm_top.sm_clk_divider.bypass = 1;\n ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:55: syntax error, unexpected \'@\'\n repeat (4) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: Define or directive not defined: \'`F_ADDU\'\n { `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:98: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:98: Define or directive not defined: \'`F_OR\'\n { `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:99: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:99: Define or directive not defined: \'`F_SRL\'\n { `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:100: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:100: Define or directive not defined: \'`F_SLTU\'\n { `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:101: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:101: Define or directive not defined: \'`F_SUBU\'\n { `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:103: Define or directive not defined: \'`C_ADDIU\'\n { `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);\n ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:103: Define or directive not defined: \'`F_ANY\'\n { `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:104: Define or directive not defined: \'`C_LUI\'\n { `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:104: Define or directive not defined: \'`F_ANY\'\n { `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:106: Define or directive not defined: \'`C_BEQ\'\n { `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:106: Define or directive not defined: \'`F_ANY\'\n { `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:107: Define or directive not defined: \'`C_BNE\'\n { `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:107: Define or directive not defined: \'`F_ANY\'\n { `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:137: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 3,043 | module | module sm_testbench;
parameter Tt = 20;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
wire cpuClk;
sm_top sm_top
(
.clkIn ( clk ),
.rst_n ( rst_n ),
.clkDevide ( 4'b0 ),
.clkEnable ( 1'b1 ),
.clk ( cpuClk ),
.regAddr ( regAddr ),
.regData ( regData )
);
defparam sm_top.sm_clk_divider.bypass = 1;
`ifdef ICARUS
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
end
`endif
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_top.sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
integer cycle; initial cycle = 0;
initial regAddr = 0;
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);
disasmInstr(sm_top.sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > `SIMULATION_CYCLES)
begin
$display ("Timeout");
$stop;
end
end
endmodule | module sm_testbench; |
parameter Tt = 20;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
wire cpuClk;
sm_top sm_top
(
.clkIn ( clk ),
.rst_n ( rst_n ),
.clkDevide ( 4'b0 ),
.clkEnable ( 1'b1 ),
.clk ( cpuClk ),
.regAddr ( regAddr ),
.regData ( regData )
);
defparam sm_top.sm_clk_divider.bypass = 1;
`ifdef ICARUS
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
end
`endif
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_top.sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
integer cycle; initial cycle = 0;
initial regAddr = 0;
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);
disasmInstr(sm_top.sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > `SIMULATION_CYCLES)
begin
$display ("Timeout");
$stop;
end
end
endmodule | 16 |
4,648 | data/full_repos/permissive/110372367/marioProj/FPU.v | 110,372,367 | FPU.v | v | 177 | 104 | [] | [] | [] | null | line:5: before: "shift" | null | 1: b'%Error: data/full_repos/permissive/110372367/marioProj/FPU.v:5: syntax error, unexpected IDENTIFIER\nshift( dir ,\n^~~~~\n%Error: Exiting due to 1 error(s)\n' | 3,044 | module | module sctrl(
opcode ,
sdiff ,
s1 ,
s2 ,
inv1 ,
inv2
);
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input opcode ;
input sdiff ;
input s1 ;
input s2 ;
output inv1 ;
output inv2 ;
endmodule | module sctrl(
opcode ,
sdiff ,
s1 ,
s2 ,
inv1 ,
inv2
); |
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input opcode ;
input sdiff ;
input s1 ;
input s2 ;
output inv1 ;
output inv2 ;
endmodule | 0 |
4,649 | data/full_repos/permissive/110372367/marioProj/FPU.v | 110,372,367 | FPU.v | v | 177 | 104 | [] | [] | [] | null | line:5: before: "shift" | null | 1: b'%Error: data/full_repos/permissive/110372367/marioProj/FPU.v:5: syntax error, unexpected IDENTIFIER\nshift( dir ,\n^~~~~\n%Error: Exiting due to 1 error(s)\n' | 3,044 | module | module adder( a ,
b ,
c );
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input [M-1:0] a;
input [M-1:0] b;
output [M-1:0] c;
endmodule | module adder( a ,
b ,
c ); |
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input [M-1:0] a;
input [M-1:0] b;
output [M-1:0] c;
endmodule | 0 |
4,650 | data/full_repos/permissive/110372367/marioProj/FPU.v | 110,372,367 | FPU.v | v | 177 | 104 | [] | [] | [] | null | line:5: before: "shift" | null | 1: b'%Error: data/full_repos/permissive/110372367/marioProj/FPU.v:5: syntax error, unexpected IDENTIFIER\nshift( dir ,\n^~~~~\n%Error: Exiting due to 1 error(s)\n' | 3,044 | module | module complement(
in,
out,
enable
);
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input enable ;
input [M-1:0] in ;
output [M-1:0] out ;
wire enable ;
wire [M-1:0] in ;
wire [M-1:0] out ;
assign out[M-1:0] = (enable) ? (~in[M-1:0] + 1'b1) : in[M-1:0];
endmodule | module complement(
in,
out,
enable
); |
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input enable ;
input [M-1:0] in ;
output [M-1:0] out ;
wire enable ;
wire [M-1:0] in ;
wire [M-1:0] out ;
assign out[M-1:0] = (enable) ? (~in[M-1:0] + 1'b1) : in[M-1:0];
endmodule | 0 |
4,651 | data/full_repos/permissive/110372367/marioProj/FPU.v | 110,372,367 | FPU.v | v | 177 | 104 | [] | [] | [] | null | line:5: before: "shift" | null | 1: b'%Error: data/full_repos/permissive/110372367/marioProj/FPU.v:5: syntax error, unexpected IDENTIFIER\nshift( dir ,\n^~~~~\n%Error: Exiting due to 1 error(s)\n' | 3,044 | module | module fpu(
operand1 ,
operand2 ,
opcode ,
result
);
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input opcode ;
input [S+E+M-1:0] op1 ;
input [S+E+M-1:0] op2 ;
output [S+E+M-1:0] result ;
wire opcode ;
wire [S+E+M-1:0] op1 ;
wire [S+E+M-1:0] op2 ;
wire [S+E+M-1:0] result ;
sctrl #( .S(S), .E(E), .M(M)) fpu_sctrl (
.opcode ( opcode ) ,
.sdiff ( sdiff ) ,
.s1 ( s1 ) ,
.s2 ( s2 ) ,
.inv1 ( inv1 ) ,
.inv2 ( inv2 ) ,
);
wire [M-1:0] m1;
wire [M-1:0] m2;
wire [M-1:0] m1_muxed;
wire [M-1:0] m2_muxed;
assign m1_muxed = (sdiff) ? m1 : m2;
assign m2_muxed = (sdiff) ? m2 : m1;
rshift #( .S(S), .E(E), .M(M)) fpu_rshift (
.dir ( 0 ) ,
.val ( rshift_val ) ,
.in ( m2_muxed ) ,
.out ( rshift_out )
);
complement #( .S(S), .E(E), .M(M)) m1_complement (
.enable ( inv1 ) ,
.in ( m1_muxed ) ,
.out ( m1_complement_out )
);
complement #( .S(S), .E(E), .M(M)) m2_complement (
.enable ( inv2 ) ,
.in ( rshift_out ) ,
.out ( m2_complement_out )
);
endmodule | module fpu(
operand1 ,
operand2 ,
opcode ,
result
); |
parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;
input opcode ;
input [S+E+M-1:0] op1 ;
input [S+E+M-1:0] op2 ;
output [S+E+M-1:0] result ;
wire opcode ;
wire [S+E+M-1:0] op1 ;
wire [S+E+M-1:0] op2 ;
wire [S+E+M-1:0] result ;
sctrl #( .S(S), .E(E), .M(M)) fpu_sctrl (
.opcode ( opcode ) ,
.sdiff ( sdiff ) ,
.s1 ( s1 ) ,
.s2 ( s2 ) ,
.inv1 ( inv1 ) ,
.inv2 ( inv2 ) ,
);
wire [M-1:0] m1;
wire [M-1:0] m2;
wire [M-1:0] m1_muxed;
wire [M-1:0] m2_muxed;
assign m1_muxed = (sdiff) ? m1 : m2;
assign m2_muxed = (sdiff) ? m2 : m1;
rshift #( .S(S), .E(E), .M(M)) fpu_rshift (
.dir ( 0 ) ,
.val ( rshift_val ) ,
.in ( m2_muxed ) ,
.out ( rshift_out )
);
complement #( .S(S), .E(E), .M(M)) m1_complement (
.enable ( inv1 ) ,
.in ( m1_muxed ) ,
.out ( m1_complement_out )
);
complement #( .S(S), .E(E), .M(M)) m2_complement (
.enable ( inv2 ) ,
.in ( rshift_out ) ,
.out ( m2_complement_out )
);
endmodule | 0 |
4,652 | data/full_repos/permissive/110381502/src/mojo_top.v | 110,381,502 | mojo_top.v | v | 146 | 99 | [] | [] | [] | [(1, 146)] | null | null | 1: b'%Error: data/full_repos/permissive/110381502/src/mojo_top.v:31: Cannot find file containing module: \'vga_clock\'\nvga_clock vga_clock(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock\n data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock.v\n data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock.sv\n vga_clock\n vga_clock.v\n vga_clock.sv\n obj_dir/vga_clock\n obj_dir/vga_clock.v\n obj_dir/vga_clock.sv\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:81: Operator AND expects 10 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance mojo_top\n red_out <= (vsync_count >> 2) & 4\'hF;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:81: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 10 bits.\n : ... In instance mojo_top\n red_out <= (vsync_count >> 2) & 4\'hF;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:82: Operator AND expects 11 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance mojo_top\n green_out <= (hsync_count >> 2) & 4\'hF;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:82: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 11 bits.\n : ... In instance mojo_top\n green_out <= (hsync_count >> 2) & 4\'hF;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:83: Operator AND expects 11 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance mojo_top\n blue_out <= (hsync_count >> 4) & 4\'hF;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:83: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 11 bits.\n : ... In instance mojo_top\n blue_out <= (hsync_count >> 4) & 4\'hF;\n ^~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 3,049 | module | module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output reg hsync,
output reg vsync,
output reg[3:0] red_out,
output reg[3:0] green_out,
output reg[3:0] blue_out
);
wire vgaclk;
vga_clock vga_clock(
.CLK_IN1(clk),
.CLK_VGA(vgaclk)
);
wire rst = ~rst_n;
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[6:0] = 7'b0;
assign led[7] = rst;
reg[10:0] hsync_count;
reg[9:0] vsync_count;
parameter VGA_HORIZ_RES = 800;
parameter VGA_VERT_RES = 600;
parameter VGA_HORIZ_FRONT_PORCH_END = 840;
parameter VGA_HORIZ_SYNC_END = 968;
parameter VGA_HORIZ_BACK_PORCH_END = 1055;
parameter VGA_VERT_FRONT_PORCH_END = 601;
parameter VGA_VERT_SYNC_END = 606;
parameter VGA_VERT_BACK_PORCH_END = 627;
always @(posedge vgaclk) begin
if (hsync_count < VGA_HORIZ_RES) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
if (vsync_count < VGA_VERT_RES) begin
red_out <= (vsync_count >> 2) & 4'hF;
green_out <= (hsync_count >> 2) & 4'hF;
blue_out <= (hsync_count >> 4) & 4'hF;
end else begin
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end
end else if (hsync_count >= VGA_HORIZ_RES && hsync_count < VGA_HORIZ_FRONT_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (hsync_count >= VGA_HORIZ_FRONT_PORCH_END && hsync_count < VGA_HORIZ_SYNC_END) begin
hsync <= 1'b0;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (hsync_count >= VGA_HORIZ_SYNC_END && hsync_count < VGA_HORIZ_BACK_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (vsync_count < VGA_VERT_BACK_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= 11'b0;
vsync_count <= vsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else begin
hsync <= 1'b1;
hsync_count <= 11'b0;
vsync_count <= 10'b0;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end
if (vsync_count > VGA_VERT_FRONT_PORCH_END && vsync_count < VGA_VERT_SYNC_END) begin
vsync <= 1'b0;
end else begin
vsync <= 1'b1;
end
end
endmodule | module mojo_top(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output reg hsync,
output reg vsync,
output reg[3:0] red_out,
output reg[3:0] green_out,
output reg[3:0] blue_out
); |
wire vgaclk;
vga_clock vga_clock(
.CLK_IN1(clk),
.CLK_VGA(vgaclk)
);
wire rst = ~rst_n;
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[6:0] = 7'b0;
assign led[7] = rst;
reg[10:0] hsync_count;
reg[9:0] vsync_count;
parameter VGA_HORIZ_RES = 800;
parameter VGA_VERT_RES = 600;
parameter VGA_HORIZ_FRONT_PORCH_END = 840;
parameter VGA_HORIZ_SYNC_END = 968;
parameter VGA_HORIZ_BACK_PORCH_END = 1055;
parameter VGA_VERT_FRONT_PORCH_END = 601;
parameter VGA_VERT_SYNC_END = 606;
parameter VGA_VERT_BACK_PORCH_END = 627;
always @(posedge vgaclk) begin
if (hsync_count < VGA_HORIZ_RES) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
if (vsync_count < VGA_VERT_RES) begin
red_out <= (vsync_count >> 2) & 4'hF;
green_out <= (hsync_count >> 2) & 4'hF;
blue_out <= (hsync_count >> 4) & 4'hF;
end else begin
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end
end else if (hsync_count >= VGA_HORIZ_RES && hsync_count < VGA_HORIZ_FRONT_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (hsync_count >= VGA_HORIZ_FRONT_PORCH_END && hsync_count < VGA_HORIZ_SYNC_END) begin
hsync <= 1'b0;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (hsync_count >= VGA_HORIZ_SYNC_END && hsync_count < VGA_HORIZ_BACK_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= hsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else if (vsync_count < VGA_VERT_BACK_PORCH_END) begin
hsync <= 1'b1;
hsync_count <= 11'b0;
vsync_count <= vsync_count + 1;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end else begin
hsync <= 1'b1;
hsync_count <= 11'b0;
vsync_count <= 10'b0;
red_out <= 4'b0;
green_out <= 4'b0;
blue_out <= 4'b0;
end
if (vsync_count > VGA_VERT_FRONT_PORCH_END && vsync_count < VGA_VERT_SYNC_END) begin
vsync <= 1'b0;
end else begin
vsync <= 1'b1;
end
end
endmodule | 0 |
4,653 | data/full_repos/permissive/110381502/src/serial_rx.v | 110,381,502 | serial_rx.v | v | 94 | 99 | [] | [] | [] | null | line:24: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_rx.v:41: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_rx\n ctr_d = 1\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_rx.v:49: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_rx\n ctr_d = 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_rx.v:58: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_rx\n ctr_d = 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_rx.v:79: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_rx\n ctr_q <= 1\'b0;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 3,050 | module | module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule | module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
); |
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule | 0 |
4,654 | data/full_repos/permissive/110381502/src/serial_tx.v | 110,381,502 | serial_tx.v | v | 109 | 99 | [] | [] | [] | null | line:25: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_tx.v:50: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_tx\n ctr_d = 1\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_tx.v:63: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_tx\n ctr_d = 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/serial_tx.v:72: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance serial_tx\n ctr_d = 1\'b0;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 3,051 | module | module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
);
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
START_BIT = 2'd1,
DATA = 2'd2,
STOP_BIT = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg tx_d, tx_q;
reg busy_d, busy_q;
reg block_d, block_q;
assign tx = tx_q;
assign busy = busy_q;
always @(*) begin
block_d = block;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
state_d = state_q;
busy_d = busy_q;
case (state_q)
IDLE: begin
if (block_q) begin
busy_d = 1'b1;
tx_d = 1'b1;
end else begin
busy_d = 1'b0;
tx_d = 1'b1;
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (new_data) begin
data_d = data;
state_d = START_BIT;
busy_d = 1'b1;
end
end
end
START_BIT: begin
busy_d = 1'b1;
ctr_d = ctr_q + 1'b1;
tx_d = 1'b0;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
state_d = DATA;
end
end
DATA: begin
busy_d = 1'b1;
tx_d = data_q[bit_ctr_q];
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
bit_ctr_d = bit_ctr_q + 1'b1;
if (bit_ctr_q == 7) begin
state_d = STOP_BIT;
end
end
end
STOP_BIT: begin
busy_d = 1'b1;
tx_d = 1'b1;
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
tx_q <= 1'b1;
end else begin
state_q <= state_d;
tx_q <= tx_d;
end
block_q <= block_d;
data_q <= data_d;
bit_ctr_q <= bit_ctr_d;
ctr_q <= ctr_d;
busy_q <= busy_d;
end
endmodule | module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
); |
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
START_BIT = 2'd1,
DATA = 2'd2,
STOP_BIT = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg tx_d, tx_q;
reg busy_d, busy_q;
reg block_d, block_q;
assign tx = tx_q;
assign busy = busy_q;
always @(*) begin
block_d = block;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
state_d = state_q;
busy_d = busy_q;
case (state_q)
IDLE: begin
if (block_q) begin
busy_d = 1'b1;
tx_d = 1'b1;
end else begin
busy_d = 1'b0;
tx_d = 1'b1;
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (new_data) begin
data_d = data;
state_d = START_BIT;
busy_d = 1'b1;
end
end
end
START_BIT: begin
busy_d = 1'b1;
ctr_d = ctr_q + 1'b1;
tx_d = 1'b0;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
state_d = DATA;
end
end
DATA: begin
busy_d = 1'b1;
tx_d = data_q[bit_ctr_q];
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
bit_ctr_d = bit_ctr_q + 1'b1;
if (bit_ctr_q == 7) begin
state_d = STOP_BIT;
end
end
end
STOP_BIT: begin
busy_d = 1'b1;
tx_d = 1'b1;
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
tx_q <= 1'b1;
end else begin
state_q <= state_d;
tx_q <= tx_d;
end
block_q <= block_d;
data_q <= data_d;
bit_ctr_q <= bit_ctr_d;
ctr_q <= ctr_d;
busy_q <= busy_d;
end
endmodule | 0 |
4,655 | data/full_repos/permissive/111021593/ClockDivider.v | 111,021,593 | ClockDivider.v | v | 24 | 46 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/d67c762c-d7be-46f3-b7f7-51a087184909.xml | null | 3,053 | module | module ClockDivider (clk, reset, newClock);
input wire clk, reset;
output reg newClock;
reg counterClock;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1)
begin
newClock <= 1'b0;
counterClock <= 1'b0;
end
else begin
counterClock <= counterClock + 1'b1;
if (counterClock == 1'b0)
begin
newClock <= ~newClock;
end
end
end
endmodule | module ClockDivider (clk, reset, newClock); |
input wire clk, reset;
output reg newClock;
reg counterClock;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1)
begin
newClock <= 1'b0;
counterClock <= 1'b0;
end
else begin
counterClock <= counterClock + 1'b1;
if (counterClock == 1'b0)
begin
newClock <= ~newClock;
end
end
end
endmodule | 0 |
4,656 | data/full_repos/permissive/111021593/horizontal_counter_generator.v | 111,021,593 | horizontal_counter_generator.v | v | 73 | 89 | [] | [] | [] | [(1, 72)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/111021593/horizontal_counter_generator.v:48: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance horizontal_counter_generator\n next_scl_hor_cnt <= 6\'b000000;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111021593/horizontal_counter_generator.v:54: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance horizontal_counter_generator\n next_scl_hor_cnt <= 6\'b000000;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 3,054 | module | module horizontal_counter_generator (clk, reset, hor_cnt, scl_hor_cnt, new_line, HSYNC);
input wire clk, reset;
output wire [6:0]scl_hor_cnt;
output wire [9:0]hor_cnt;
output reg new_line, HSYNC;
wire [2:0]int_cnt;
reg [2:0]next_int_cnt;
reg [6:0]next_scl_hor_cnt;
reg [9:0]next_hor_cnt;
assign int_cnt = next_int_cnt;
assign scl_hor_cnt = next_scl_hor_cnt;
assign hor_cnt = next_hor_cnt;
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
HSYNC <=1'b0;
end
else begin
if (hor_cnt < 10'd95 || hor_cnt == 10'd799) begin
HSYNC <= 1'b0;
end
else begin
HSYNC <=1'b1;
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
new_line <=1'b0;
end
else begin
if (hor_cnt == 10'd798) begin
new_line <= 1'b1;
end
else begin
new_line <=1'b0;
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
next_int_cnt <= 3'b000;
next_scl_hor_cnt <= 6'b000000;
next_hor_cnt <= 10'b0000000000;
end
else begin
if (hor_cnt == 10'd799) begin
next_int_cnt <= 3'b000;
next_scl_hor_cnt <= 6'b000000;
next_hor_cnt <= 10'b0000000000;
end
else begin
next_hor_cnt <= hor_cnt + 1;
if (int_cnt == 3'b100) begin
next_int_cnt <= 3'b000;
if (hor_cnt > 10'd144 && hor_cnt < 10'd784)begin
next_scl_hor_cnt <= scl_hor_cnt + 6'b000001;
end
end
else begin
next_int_cnt <= int_cnt + 1;
end
end
end
end
endmodule | module horizontal_counter_generator (clk, reset, hor_cnt, scl_hor_cnt, new_line, HSYNC); |
input wire clk, reset;
output wire [6:0]scl_hor_cnt;
output wire [9:0]hor_cnt;
output reg new_line, HSYNC;
wire [2:0]int_cnt;
reg [2:0]next_int_cnt;
reg [6:0]next_scl_hor_cnt;
reg [9:0]next_hor_cnt;
assign int_cnt = next_int_cnt;
assign scl_hor_cnt = next_scl_hor_cnt;
assign hor_cnt = next_hor_cnt;
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
HSYNC <=1'b0;
end
else begin
if (hor_cnt < 10'd95 || hor_cnt == 10'd799) begin
HSYNC <= 1'b0;
end
else begin
HSYNC <=1'b1;
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
new_line <=1'b0;
end
else begin
if (hor_cnt == 10'd798) begin
new_line <= 1'b1;
end
else begin
new_line <=1'b0;
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1) begin
next_int_cnt <= 3'b000;
next_scl_hor_cnt <= 6'b000000;
next_hor_cnt <= 10'b0000000000;
end
else begin
if (hor_cnt == 10'd799) begin
next_int_cnt <= 3'b000;
next_scl_hor_cnt <= 6'b000000;
next_hor_cnt <= 10'b0000000000;
end
else begin
next_hor_cnt <= hor_cnt + 1;
if (int_cnt == 3'b100) begin
next_int_cnt <= 3'b000;
if (hor_cnt > 10'd144 && hor_cnt < 10'd784)begin
next_scl_hor_cnt <= scl_hor_cnt + 6'b000001;
end
end
else begin
next_int_cnt <= int_cnt + 1;
end
end
end
end
endmodule | 0 |
4,657 | data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v | 111,021,593 | horizontal_counter_generator_tb.v | v | 28 | 43 | [] | [] | [] | [(1, 27)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:9: Cannot find file containing module: \'horizontal_counter_generator\'\nhorizontal_counter_generator DUT(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator.v\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator.sv\n horizontal_counter_generator\n horizontal_counter_generator.v\n horizontal_counter_generator.sv\n obj_dir/horizontal_counter_generator\n obj_dir/horizontal_counter_generator.v\n obj_dir/horizontal_counter_generator.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,055 | module | module horizontal_counter_generator_tb ();
reg clk, reset;
wire [9:0]hor_cnt;
wire [7:0]scl_hor_cnt;
wire new_line;
horizontal_counter_generator DUT(
.clk(clk),
.reset(reset),
.hor_cnt(hor_cnt),
.scl_hor_cnt(scl_hor_cnt),
.new_line(new_line)
);
initial begin
clk = 0;
reset = 1;
#100 reset = 0;
end
always begin
#20 clk = ~clk;
end
endmodule | module horizontal_counter_generator_tb (); |
reg clk, reset;
wire [9:0]hor_cnt;
wire [7:0]scl_hor_cnt;
wire new_line;
horizontal_counter_generator DUT(
.clk(clk),
.reset(reset),
.hor_cnt(hor_cnt),
.scl_hor_cnt(scl_hor_cnt),
.new_line(new_line)
);
initial begin
clk = 0;
reset = 1;
#100 reset = 0;
end
always begin
#20 clk = ~clk;
end
endmodule | 0 |
4,658 | data/full_repos/permissive/111021593/RGB.v | 111,021,593 | RGB.v | v | 29 | 109 | [] | [] | [] | [(1, 29)] | null | data/verilator_xmls/afef5474-385f-4d31-b027-7ad310fce898.xml | null | 3,056 | module | module RGB (clk, reset, hor_cnt, ver_cnt, red, green, blue, VGA_RED, VGA_GREEN, VGA_BLUE);
input wire clk, reset;
input wire [9:0]hor_cnt;
input wire [9:0]ver_cnt;
input wire red, green, blue;
output reg VGA_RED, VGA_GREEN, VGA_BLUE;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
VGA_RED <= 1'b0;
VGA_GREEN <= 1'b0;
VGA_BLUE <= 1'b0;
end
else begin
if (((hor_cnt >= 10'd144) && (hor_cnt <= 10'd784)) && ((ver_cnt >= 10'd35) && (ver_cnt <= 10'd515))) begin
VGA_RED <= red;
VGA_GREEN <= green;
VGA_BLUE <= blue;
end
else begin
VGA_RED <= 1'b0;
VGA_GREEN <= 1'b0;
VGA_BLUE <= 1'b0;
end
end
end
endmodule | module RGB (clk, reset, hor_cnt, ver_cnt, red, green, blue, VGA_RED, VGA_GREEN, VGA_BLUE); |
input wire clk, reset;
input wire [9:0]hor_cnt;
input wire [9:0]ver_cnt;
input wire red, green, blue;
output reg VGA_RED, VGA_GREEN, VGA_BLUE;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
VGA_RED <= 1'b0;
VGA_GREEN <= 1'b0;
VGA_BLUE <= 1'b0;
end
else begin
if (((hor_cnt >= 10'd144) && (hor_cnt <= 10'd784)) && ((ver_cnt >= 10'd35) && (ver_cnt <= 10'd515))) begin
VGA_RED <= red;
VGA_GREEN <= green;
VGA_BLUE <= blue;
end
else begin
VGA_RED <= 1'b0;
VGA_GREEN <= 1'b0;
VGA_BLUE <= 1'b0;
end
end
end
endmodule | 0 |
4,659 | data/full_repos/permissive/111021593/vertical_counter_generator.v | 111,021,593 | vertical_counter_generator.v | v | 136 | 110 | [] | [] | [] | [(1, 135)] | null | data/verilator_xmls/8979f4fc-d31d-49cc-b843-9913ab342f99.xml | null | 3,057 | module | module vertical_counter_generator (clk, reset, new_line, ver_cnt, scl_ver_cnt, VSYNC);
input wire clk, reset, new_line;
output wire [6:0]scl_ver_cnt;
output wire [9:0]ver_cnt;
output reg VSYNC;
wire [2:0]scale_cnt;
wire [18:0]clock_cnt;
reg [2:0]next_scale_cnt;
reg [6:0]next_scl_ver_cnt;
reg [9:0]next_ver_cnt;
reg [18:0]next_clock_cnt;
assign scale_cnt = next_scale_cnt;
assign scl_ver_cnt = next_scl_ver_cnt;
assign ver_cnt = next_ver_cnt;
assign clock_cnt = next_clock_cnt;
always @ ( posedge clk or posedge reset ) begin
if (reset == 1'b1) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= 7'b000000;
next_ver_cnt <= 10'b0000000000;
VSYNC <=1'b0;
end
else begin
if (new_line == 1'b1) begin
if (ver_cnt == 10'd520) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= 7'b000000;
next_ver_cnt <= 10'b0000000000;
VSYNC <= 1'b0;
end
else begin
if (ver_cnt < 10'd1) begin
VSYNC <= 1'b0;
end
else begin
VSYNC <= 1'b1;
end
next_ver_cnt <= ver_cnt + 10'b0000000001;
if (ver_cnt >= 10'd31 && ver_cnt < 10'd511) begin
if (scale_cnt == 3'b100) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= scl_ver_cnt + 7'b0000001;
end else begin
next_scale_cnt <= scale_cnt + 3'b001;
end
end
end
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_clock_cnt <= 19'b0000000000000000000;
end else begin
if (clock_cnt == 19'd416799) begin
next_clock_cnt <= 19'b0000000000000000000;
end
next_clock_cnt <= clock_cnt + 19'b0000000000000000001;
end
end
endmodule | module vertical_counter_generator (clk, reset, new_line, ver_cnt, scl_ver_cnt, VSYNC); |
input wire clk, reset, new_line;
output wire [6:0]scl_ver_cnt;
output wire [9:0]ver_cnt;
output reg VSYNC;
wire [2:0]scale_cnt;
wire [18:0]clock_cnt;
reg [2:0]next_scale_cnt;
reg [6:0]next_scl_ver_cnt;
reg [9:0]next_ver_cnt;
reg [18:0]next_clock_cnt;
assign scale_cnt = next_scale_cnt;
assign scl_ver_cnt = next_scl_ver_cnt;
assign ver_cnt = next_ver_cnt;
assign clock_cnt = next_clock_cnt;
always @ ( posedge clk or posedge reset ) begin
if (reset == 1'b1) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= 7'b000000;
next_ver_cnt <= 10'b0000000000;
VSYNC <=1'b0;
end
else begin
if (new_line == 1'b1) begin
if (ver_cnt == 10'd520) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= 7'b000000;
next_ver_cnt <= 10'b0000000000;
VSYNC <= 1'b0;
end
else begin
if (ver_cnt < 10'd1) begin
VSYNC <= 1'b0;
end
else begin
VSYNC <= 1'b1;
end
next_ver_cnt <= ver_cnt + 10'b0000000001;
if (ver_cnt >= 10'd31 && ver_cnt < 10'd511) begin
if (scale_cnt == 3'b100) begin
next_scale_cnt <= 3'b000;
next_scl_ver_cnt <= scl_ver_cnt + 7'b0000001;
end else begin
next_scale_cnt <= scale_cnt + 3'b001;
end
end
end
end
end
end
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
next_clock_cnt <= 19'b0000000000000000000;
end else begin
if (clock_cnt == 19'd416799) begin
next_clock_cnt <= 19'b0000000000000000000;
end
next_clock_cnt <= clock_cnt + 19'b0000000000000000001;
end
end
endmodule | 0 |
4,660 | data/full_repos/permissive/111021593/VGA_controller.v | 111,021,593 | VGA_controller.v | v | 69 | 88 | [] | [] | [] | [(1, 68)] | null | null | 1: b"%Error: data/full_repos/permissive/111021593/VGA_controller.v:22: Cannot find file containing module: 'ClockDivider'\nClockDivider ClockDivider(\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/ClockDivider\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/ClockDivider.v\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/ClockDivider.sv\n ClockDivider\n ClockDivider.v\n ClockDivider.sv\n obj_dir/ClockDivider\n obj_dir/ClockDivider.v\n obj_dir/ClockDivider.sv\n%Error: data/full_repos/permissive/111021593/VGA_controller.v:28: Cannot find file containing module: 'horizontal_counter_generator'\nhorizontal_counter_generator horizontal_counter_generator(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111021593/VGA_controller.v:37: Cannot find file containing module: 'vertical_counter_generator'\nvertical_counter_generator vertical_counter_generator(\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111021593/VGA_controller.v:46: Cannot find file containing module: 'vram'\nvram vram (\n^~~~\n%Error: data/full_repos/permissive/111021593/VGA_controller.v:55: Cannot find file containing module: 'RGB'\nRGB RGB (\n^~~\n%Error: Exiting due to 5 error(s)\n" | 3,058 | module | module VGA_controller (clk, reset, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC);
input wire clk, reset;
output wire VGA_RED, VGA_GREEN, VGA_BLUE;
output wire VGA_HSYNC, VGA_VSYNC;
wire red, green, blue;
wire newClock;
wire [9:0]hor_cnt;
wire [6:0]scl_hor_cnt;
wire new_line;
wire [9:0]ver_cnt;
wire [6:0]scl_ver_cnt;
wire [13:0]VRAM_address;
assign VRAM_address = {scl_ver_cnt, scl_hor_cnt};
ClockDivider ClockDivider(
.clk(clk),
.reset(reset),
.newClock(newClock)
);
horizontal_counter_generator horizontal_counter_generator(
.clk(newClock),
.reset(reset),
.hor_cnt(hor_cnt),
.scl_hor_cnt(scl_hor_cnt),
.new_line(new_line),
.HSYNC(VGA_HSYNC)
);
vertical_counter_generator vertical_counter_generator(
.clk(newClock),
.reset(reset),
.new_line(new_line),
.ver_cnt(ver_cnt),
.scl_ver_cnt(scl_ver_cnt),
.VSYNC(VGA_VSYNC)
);
vram vram (
.CLK(newClock),
.SSR(reset),
.ADDR(VRAM_address),
.VGA_RED(red),
.VGA_GREEN(green),
.VGA_BLUE(blue)
);
RGB RGB (
.clk(newClock),
.reset(reset),
.hor_cnt(hor_cnt),
.ver_cnt(ver_cnt),
.red(red),
.green(green),
.blue(blue),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE)
);
endmodule | module VGA_controller (clk, reset, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC); |
input wire clk, reset;
output wire VGA_RED, VGA_GREEN, VGA_BLUE;
output wire VGA_HSYNC, VGA_VSYNC;
wire red, green, blue;
wire newClock;
wire [9:0]hor_cnt;
wire [6:0]scl_hor_cnt;
wire new_line;
wire [9:0]ver_cnt;
wire [6:0]scl_ver_cnt;
wire [13:0]VRAM_address;
assign VRAM_address = {scl_ver_cnt, scl_hor_cnt};
ClockDivider ClockDivider(
.clk(clk),
.reset(reset),
.newClock(newClock)
);
horizontal_counter_generator horizontal_counter_generator(
.clk(newClock),
.reset(reset),
.hor_cnt(hor_cnt),
.scl_hor_cnt(scl_hor_cnt),
.new_line(new_line),
.HSYNC(VGA_HSYNC)
);
vertical_counter_generator vertical_counter_generator(
.clk(newClock),
.reset(reset),
.new_line(new_line),
.ver_cnt(ver_cnt),
.scl_ver_cnt(scl_ver_cnt),
.VSYNC(VGA_VSYNC)
);
vram vram (
.CLK(newClock),
.SSR(reset),
.ADDR(VRAM_address),
.VGA_RED(red),
.VGA_GREEN(green),
.VGA_BLUE(blue)
);
RGB RGB (
.clk(newClock),
.reset(reset),
.hor_cnt(hor_cnt),
.ver_cnt(ver_cnt),
.red(red),
.green(green),
.blue(blue),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE)
);
endmodule | 0 |
4,661 | data/full_repos/permissive/111021593/VGA_controller_tb.v | 111,021,593 | VGA_controller_tb.v | v | 28 | 57 | [] | [] | [] | [(1, 27)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111021593/VGA_controller_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111021593/VGA_controller_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/111021593/VGA_controller_tb.v:7: Cannot find file containing module: \'VGA_controller\'\nVGA_controller DUT(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller.v\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller.sv\n VGA_controller\n VGA_controller.v\n VGA_controller.sv\n obj_dir/VGA_controller\n obj_dir/VGA_controller.v\n obj_dir/VGA_controller.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,059 | module | module VGA_controller_tb();
reg clk, reset;
wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
VGA_controller DUT(
.clk (clk),
.reset (reset),
.VGA_RED (VGA_RED),
.VGA_GREEN (VGA_GREEN),
.VGA_BLUE (VGA_BLUE),
.VGA_HSYNC (VGA_HSYNC),
.VGA_VSYNC (VGA_VSYNC)
);
initial begin
clk = 0;
reset = 1;
#100 reset = 0;
end
always begin
#5 clk = ~clk;
end
endmodule | module VGA_controller_tb(); |
reg clk, reset;
wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
VGA_controller DUT(
.clk (clk),
.reset (reset),
.VGA_RED (VGA_RED),
.VGA_GREEN (VGA_GREEN),
.VGA_BLUE (VGA_BLUE),
.VGA_HSYNC (VGA_HSYNC),
.VGA_VSYNC (VGA_VSYNC)
);
initial begin
clk = 0;
reset = 1;
#100 reset = 0;
end
always begin
#5 clk = ~clk;
end
endmodule | 0 |
4,662 | data/full_repos/permissive/111021593/vram.v | 111,021,593 | vram.v | v | 463 | 156 | [] | [] | [] | [(1, 463)] | null | null | 1: b"%Error: data/full_repos/permissive/111021593/vram.v:11: Cannot find file containing module: 'RAMB16_S1'\nRAMB16_S1 #(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/RAMB16_S1\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/RAMB16_S1.v\n data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/RAMB16_S1.sv\n RAMB16_S1\n RAMB16_S1.v\n RAMB16_S1.sv\n obj_dir/RAMB16_S1\n obj_dir/RAMB16_S1.v\n obj_dir/RAMB16_S1.sv\n%Error: data/full_repos/permissive/111021593/vram.v:163: Cannot find file containing module: 'RAMB16_S1'\nRAMB16_S1 #(\n^~~~~~~~~\n%Error: data/full_repos/permissive/111021593/vram.v:315: Cannot find file containing module: 'RAMB16_S1'\nRAMB16_S1 #(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 3,060 | module | module vram (CLK, SSR, ADDR, VGA_RED, VGA_GREEN, VGA_BLUE);
input wire CLK, SSR;
input wire [13:0]ADDR;
output VGA_RED, VGA_GREEN, VGA_BLUE;
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_31({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_32({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_33({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_34({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_35({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_36({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_37({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_38({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_39({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3A({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3B({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3C({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3D({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3E({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3F({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111})
) RAMB16_S1_RED (
.DO(VGA_RED),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_31({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_32({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_33({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_34({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_35({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_36({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_37({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_38({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_39({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3A({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3B({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3C({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3D({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3E({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3F({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111})
) RAMB16_S1_GREEN (
.DO(VGA_GREEN),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_31({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_32({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_33({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_34({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_35({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_36({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_37({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_38({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_39({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3A({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3B({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3C({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3D({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3E({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3F({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111})
) RAMB16_S1_BLUE (
.DO(VGA_BLUE),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
endmodule | module vram (CLK, SSR, ADDR, VGA_RED, VGA_GREEN, VGA_BLUE); |
input wire CLK, SSR;
input wire [13:0]ADDR;
output VGA_RED, VGA_GREEN, VGA_BLUE;
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_31({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_32({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_33({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_34({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_35({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_36({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_37({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_38({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_39({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3A({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3B({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3C({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3D({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3E({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111}),
.INIT_3F({128'h0000_0000_0000_0000_1111_1111_1111_1111,
128'h0000_0000_0000_0000_1111_1111_1111_1111})
) RAMB16_S1_RED (
.DO(VGA_RED),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_31({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_32({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_33({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_34({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_35({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_36({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_37({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_38({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_39({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3A({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3B({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3C({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3D({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3E({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111}),
.INIT_3F({128'h0000_0000_1111_1111_0000_0000_1111_1111,
128'h0000_0000_1111_1111_0000_0000_1111_1111})
) RAMB16_S1_GREEN (
.DO(VGA_GREEN),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
RAMB16_S1 #(
.INIT(1'b0),
.SRVAL(1'b0),
.WRITE_MODE("WRITE_FIRST"),
.INIT_00({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_01({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_02({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_03({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_04({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_05({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_06({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_07({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_08({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_09({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_0F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_10({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_11({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_12({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_13({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_14({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_15({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_16({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_17({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_18({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_19({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1A({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1C({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1E({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_1F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_20({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_21({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_22({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_23({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_24({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_25({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_26({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_27({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_28({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_29({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2A({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2B({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2C({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2D({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_2E({128'h11111111111111111111111111111111,
128'h11111111111111111111111111111111}),
.INIT_2F({128'h00000000000000000000000000000000,
128'h00000000000000000000000000000000}),
.INIT_30({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_31({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_32({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_33({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_34({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_35({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_36({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_37({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_38({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_39({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3A({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3B({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3C({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3D({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3E({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111}),
.INIT_3F({128'h0000_1111_0000_1111_0000_1111_0000_1111,
128'h0000_1111_0000_1111_0000_1111_0000_1111})
) RAMB16_S1_BLUE (
.DO(VGA_BLUE),
.ADDR(ADDR),
.CLK(CLK),
.DI(1'b0),
.EN(1'b1),
.SSR(SSR),
.WE(1'b0)
);
endmodule | 0 |
4,664 | data/full_repos/permissive/111042295/nand_controller.v | 111,042,295 | nand_controller.v | v | 343 | 101 | [] | [] | [] | [(9, 343)] | null | null | 1: b'%Error: data/full_repos/permissive/111042295/nand_controller.v:26: Cannot find file containing module: \'uds_counter\'\n uds_counter #(12, 4096) addr_counter(ram_addr_up, 1\'b0, ram_addr_set, \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111042295,data/full_repos/permissive/111042295/uds_counter\n data/full_repos/permissive/111042295,data/full_repos/permissive/111042295/uds_counter.v\n data/full_repos/permissive/111042295,data/full_repos/permissive/111042295/uds_counter.sv\n uds_counter\n uds_counter.v\n uds_counter.sv\n obj_dir/uds_counter\n obj_dir/uds_counter.v\n obj_dir/uds_counter.sv\n%Error: data/full_repos/permissive/111042295/nand_controller.v:32: Cannot find file containing module: \'up_counter\'\n up_counter delay_counter(dly_cnt_en, dly_cnt_clr, dly_cnt, clk);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111042295/nand_controller.v:37: Cannot find file containing module: \'uds_counter\'\n uds_counter cmd_pos_counter(cmd_pos_up, 1\'b0, cmd_pos_set, \n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/111042295/nand_controller.v:79: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance nand_controller\n cyc_time <= 3\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111042295/nand_controller.v:91: Bit extraction of array[6:0] requires 3 bit index, not 12 bits.\n : ... In instance nand_controller\n cmd_reg[ram_addr] <= ram_in; \n ^\n%Warning-WIDTH: data/full_repos/permissive/111042295/nand_controller.v:119: Operator GTE expects 8 bits on the RHS, but RHS\'s VARREF \'terminal_pos\' generates 4 bits.\n : ... In instance nand_controller\n if(cmd_pos >= terminal_pos) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/111042295/nand_controller.v:236: Bit extraction of array[6:0] requires 3 bit index, not 8 bits.\n : ... In instance nand_controller\n assign curr_cmd_val = cmd_reg[cmd_pos];\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 3,062 | module | module nand_controller(ram_in, ram_addr, ram_re, ram_we, ram_out,
cle, ce, re, ale, we, rb, io, io_write,
ready, clk, rst, io_drive_en, comm_done);
input [7:0] ram_in;
input [7:0] io;
output [7:0] ram_out;
input ready;
input clk, rst, rb;
output [11:0] ram_addr;
output reg ram_re, ram_we;
output reg ce, cle, re, ale, we, comm_done;
reg [7:0] cmd_reg [0:6];
reg ram_addr_up, ram_addr_set;
reg [11:0] ram_addr_in;
uds_counter #(12, 4096) addr_counter(ram_addr_up, 1'b0, ram_addr_set,
ram_addr_in, ram_addr, clk);
reg dly_cnt_en, dly_cnt_clr;
wire [7:0] dly_cnt;
up_counter delay_counter(dly_cnt_en, dly_cnt_clr, dly_cnt, clk);
reg cmd_pos_up, cmd_pos_set;
reg [7:0] cmd_pos_in;
wire [7:0] cmd_pos;
uds_counter cmd_pos_counter(cmd_pos_up, 1'b0, cmd_pos_set,
cmd_pos_in, cmd_pos, clk);
output reg io_drive_en;
output reg [7:0] io_write;
reg [7:0] prog_register;
assign ram_out = io;
reg [3:0] terminal_pos;
reg [5:0] cyc_time;
reg [4:0] state;
reg [11:0] num_read_cycles;
parameter init = 0, wait_for_ready = 1, ram_req_cmd_read = 2,
read_cmd_to_reg = 3, cmd_cyc_1_0 = 4, cmd_cyc_1_1 = 5,
cmd_cyc_1_2 = 6, addr_cyc_lo = 7, addr_cyc_hi = 8,
cmd_cyc_2_pre = 9, cmd_cyc_2_0 = 10, cmd_cyc_2_1 = 11,
cmd_cyc_2_2 = 12, rb_wait_lo = 13, rb_wait_hi = 14,
read_cycle_hi = 15, read_cycle_lo = 16, write_to_ram = 17,
done = 18, prog_addr_delay = 19, prog_write_delay = 20,
prog_cycle_low = 21, prog_hi_before_lo = 22,
prog_read_ram = 23, prog_latch_ram = 24, prog_hi_after_lo = 25;
initial begin
state <= init;
end
always @(posedge clk) begin
if(rst) state <= init;
else case(state)
init: begin
prog_register <= 8'h0;
num_read_cycles <= 12'h000;
state <= wait_for_ready;
cyc_time <= 3'b0;
end
wait_for_ready: begin
if(ready) state <= ram_req_cmd_read;
else state <= wait_for_ready;
end
ram_req_cmd_read: begin
if(ram_addr >= `CMD_SIZE) state <= cmd_cyc_1_0;
else state <= read_cmd_to_reg;
end
read_cmd_to_reg: begin
state <= ram_req_cmd_read;
cmd_reg[ram_addr] <= ram_in;
end
cmd_cyc_1_0: state <= cmd_cyc_1_1;
cmd_cyc_1_1: begin
if (cyc_time >= 7) begin
state <= cmd_cyc_1_2;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
cmd_cyc_1_2: begin
if(cyc_time >= 2) begin
if(cmd_reg[0] == 8'h50) state <= prog_addr_delay;
else state <= addr_cyc_hi;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
prog_addr_delay: begin
if(dly_cnt >= 20) state <= addr_cyc_hi;
else state <= prog_addr_delay;
end
addr_cyc_lo: begin
if(dly_cnt >= 15) state <= addr_cyc_hi;
else state <= addr_cyc_lo;
end
addr_cyc_hi: begin
if(dly_cnt >= 15) begin
if(cmd_pos >= terminal_pos) begin
if(cmd_reg[0] == 8'h50) state <= prog_write_delay;
else state <= cmd_cyc_2_pre;
end
else state <= addr_cyc_lo;
end
else state <= addr_cyc_hi;
end
cmd_cyc_2_pre: begin
if((cmd_reg[0] == 8'h45) && (dly_cnt >= 17)) state <= cmd_cyc_2_0;
else if(dly_cnt >= 100) state <= cmd_cyc_2_0;
else state <= cmd_cyc_2_pre;
end
prog_write_delay: begin
if(dly_cnt >= 20) state <= prog_read_ram;
else state <= prog_write_delay;
end
prog_hi_before_lo: begin
if(cyc_time > 10) begin
state <= prog_cycle_low;
cyc_time <= 0;
end
else begin
cyc_time <= cyc_time + 1;
state <= prog_hi_before_lo;
end
end
prog_cycle_low: begin
if(cyc_time > 15) begin
state <= prog_hi_after_lo;
cyc_time <= 0;
end
else begin
state <= prog_cycle_low;
cyc_time <= cyc_time + 1;
end
end
prog_hi_after_lo: begin
if(cyc_time >= 10) begin
if(num_read_cycles >= `NUM_ADDR) state <= cmd_cyc_2_pre;
else state <= prog_read_ram;
cyc_time <= 0;
end else begin
state <= prog_hi_after_lo;
cyc_time <= cyc_time + 1;
end
end
prog_read_ram: begin
state <= prog_latch_ram;
end
prog_latch_ram: begin
num_read_cycles <= num_read_cycles + 1;
prog_register <= ram_in;
state <= prog_hi_before_lo;
end
cmd_cyc_2_0: state <= cmd_cyc_2_1;
cmd_cyc_2_1: begin
if(cyc_time >= 7) begin
state <= cmd_cyc_2_2;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
cmd_cyc_2_2: begin
if(cyc_time >= 2) begin
state <= rb_wait_lo;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
rb_wait_lo: begin
if(rb == 0) state <= rb_wait_hi;
else state <= rb_wait_lo;
end
rb_wait_hi: begin
if(rb == 1) begin
if(cmd_reg[0] == 8'h52) state <= read_cycle_hi;
else state <= done;
end else state <= rb_wait_hi;
end
read_cycle_hi: begin
if(num_read_cycles == `NUM_ADDR ) state <= done;
else if(cyc_time > 10) begin
state <= read_cycle_lo;
cyc_time <= 0;
end
else begin
state <= read_cycle_hi;
cyc_time <= cyc_time + 1;
end
end
read_cycle_lo: begin
if(cyc_time > 10) begin
cyc_time <= 0;
state <= write_to_ram;
num_read_cycles <= num_read_cycles + 1;
end
else begin
state <= read_cycle_lo;
cyc_time <= cyc_time + 1;
end
end
write_to_ram: state <= read_cycle_hi;
done: begin
state <= init;
prog_register <= 8'h0;
end
default: state <= init;
endcase
end
wire [7:0] curr_cmd_val;
assign curr_cmd_val = cmd_reg[cmd_pos];
reg [7:0] cmd_byte_0, cmd_byte_1;
always @* begin
if((state == ram_req_cmd_read) ||
(state == read_cmd_to_reg)) ram_re = 1;
else if(state == prog_read_ram) ram_re = 1;
else ram_re = 0;
if((cmd_cyc_1_0 <= state) &&
(state <= cmd_cyc_2_2)) io_drive_en = 1;
else if((state == prog_hi_before_lo) || (state == prog_hi_after_lo)
|| (state == prog_cycle_low) || (state == prog_latch_ram)
|| (state == prog_read_ram)) io_drive_en = 1;
else io_drive_en = 0;
if( cmd_reg[0] == 8'h45) begin
cmd_byte_0 = 8'h60;
cmd_byte_1 = 8'hD0;
end else if(cmd_reg[0] == 8'h50) begin
cmd_byte_0 = 8'h80;
cmd_byte_1 = 8'h10;
end else if(cmd_reg[0] == 8'h52) begin
cmd_byte_0 = 8'h00;
cmd_byte_1 = 8'h30;
end else begin
cmd_byte_0 = 8'h00;
cmd_byte_1 = 8'h00;
end
if((cmd_cyc_1_0 <= state) &&
(state <= cmd_cyc_1_2)) io_write = cmd_byte_0;
else if((cmd_cyc_2_0 <= state) &&
(state <= cmd_cyc_2_2)) io_write = cmd_byte_1;
else if((addr_cyc_lo <= state) &&
(state <= addr_cyc_hi)) io_write = curr_cmd_val;
else if((state == prog_hi_before_lo) || (state == prog_cycle_low)
|| (state == prog_hi_after_lo) || (state == prog_read_ram)
|| (state == prog_latch_ram)) io_write = prog_register;
else io_write = 8'h00;
if((state == read_cmd_to_reg) || (state == write_to_ram)) ram_addr_up = 1;
else if(state == prog_read_ram) ram_addr_up = 1;
else ram_addr_up = 0;
if((state == init) || (state == rb_wait_hi)) ram_addr_set = 1;
else if(state == prog_write_delay) ram_addr_set = 1;
else ram_addr_set = 0;
if(state == rb_wait_hi) ram_addr_in = `CMD_SIZE + 1;
else if(state == prog_write_delay) ram_addr_in = `CMD_SIZE + 1;
else ram_addr_in = 12'h000;
if((addr_cyc_lo <= state) &&
(state <= cmd_cyc_2_pre)) dly_cnt_en = 1;
else if(state == prog_addr_delay) dly_cnt_en = 1;
else if(state == prog_write_delay) dly_cnt_en = 1;
else dly_cnt_en = 0;
if(state == init) dly_cnt_clr = 1;
else if((state == addr_cyc_lo) && (dly_cnt >= 15)) dly_cnt_clr = 1;
else if((state == addr_cyc_hi) && (dly_cnt >= 15)) dly_cnt_clr = 1;
else if((state == prog_addr_delay) && (dly_cnt >= 20)) dly_cnt_clr = 1;
else if((state == prog_write_delay) && (dly_cnt >= 20)) dly_cnt_clr = 1;
else dly_cnt_clr = 0;
if((state == addr_cyc_lo) && (dly_cnt == 15)) cmd_pos_up = 1;
else cmd_pos_up = 0;
if(state == init) cmd_pos_set = 1;
else cmd_pos_set = 0;
cmd_pos_in = 2;
if(((cmd_cyc_1_0 <= state) && (state <= cmd_cyc_1_2)) ||
((cmd_cyc_2_0 <= state) && (state <= cmd_cyc_2_2))) cle = 1;
else cle = 0;
if(state > read_cmd_to_reg) ce = 0;
else ce = 1;
if(state == read_cycle_lo) re = 0;
else re = 1;
if((cmd_cyc_1_2 < state) && (state < cmd_cyc_2_pre)) ale = 1;
else ale = 0;
if(state == addr_cyc_lo) we = 0;
else if(state == cmd_cyc_1_1) we = 0;
else if(state == cmd_cyc_2_1) we = 0;
else if(state == prog_cycle_low) we = 0;
else we = 1;
if(cmd_reg[0] == 8'h45) terminal_pos = (`CMD_SIZE - 2);
else terminal_pos = `CMD_SIZE;
if(state == write_to_ram) ram_we = 1;
else ram_we = 0;
if(state == done) comm_done = 1;
else comm_done = 0;
end
endmodule | module nand_controller(ram_in, ram_addr, ram_re, ram_we, ram_out,
cle, ce, re, ale, we, rb, io, io_write,
ready, clk, rst, io_drive_en, comm_done); |
input [7:0] ram_in;
input [7:0] io;
output [7:0] ram_out;
input ready;
input clk, rst, rb;
output [11:0] ram_addr;
output reg ram_re, ram_we;
output reg ce, cle, re, ale, we, comm_done;
reg [7:0] cmd_reg [0:6];
reg ram_addr_up, ram_addr_set;
reg [11:0] ram_addr_in;
uds_counter #(12, 4096) addr_counter(ram_addr_up, 1'b0, ram_addr_set,
ram_addr_in, ram_addr, clk);
reg dly_cnt_en, dly_cnt_clr;
wire [7:0] dly_cnt;
up_counter delay_counter(dly_cnt_en, dly_cnt_clr, dly_cnt, clk);
reg cmd_pos_up, cmd_pos_set;
reg [7:0] cmd_pos_in;
wire [7:0] cmd_pos;
uds_counter cmd_pos_counter(cmd_pos_up, 1'b0, cmd_pos_set,
cmd_pos_in, cmd_pos, clk);
output reg io_drive_en;
output reg [7:0] io_write;
reg [7:0] prog_register;
assign ram_out = io;
reg [3:0] terminal_pos;
reg [5:0] cyc_time;
reg [4:0] state;
reg [11:0] num_read_cycles;
parameter init = 0, wait_for_ready = 1, ram_req_cmd_read = 2,
read_cmd_to_reg = 3, cmd_cyc_1_0 = 4, cmd_cyc_1_1 = 5,
cmd_cyc_1_2 = 6, addr_cyc_lo = 7, addr_cyc_hi = 8,
cmd_cyc_2_pre = 9, cmd_cyc_2_0 = 10, cmd_cyc_2_1 = 11,
cmd_cyc_2_2 = 12, rb_wait_lo = 13, rb_wait_hi = 14,
read_cycle_hi = 15, read_cycle_lo = 16, write_to_ram = 17,
done = 18, prog_addr_delay = 19, prog_write_delay = 20,
prog_cycle_low = 21, prog_hi_before_lo = 22,
prog_read_ram = 23, prog_latch_ram = 24, prog_hi_after_lo = 25;
initial begin
state <= init;
end
always @(posedge clk) begin
if(rst) state <= init;
else case(state)
init: begin
prog_register <= 8'h0;
num_read_cycles <= 12'h000;
state <= wait_for_ready;
cyc_time <= 3'b0;
end
wait_for_ready: begin
if(ready) state <= ram_req_cmd_read;
else state <= wait_for_ready;
end
ram_req_cmd_read: begin
if(ram_addr >= `CMD_SIZE) state <= cmd_cyc_1_0;
else state <= read_cmd_to_reg;
end
read_cmd_to_reg: begin
state <= ram_req_cmd_read;
cmd_reg[ram_addr] <= ram_in;
end
cmd_cyc_1_0: state <= cmd_cyc_1_1;
cmd_cyc_1_1: begin
if (cyc_time >= 7) begin
state <= cmd_cyc_1_2;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
cmd_cyc_1_2: begin
if(cyc_time >= 2) begin
if(cmd_reg[0] == 8'h50) state <= prog_addr_delay;
else state <= addr_cyc_hi;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
prog_addr_delay: begin
if(dly_cnt >= 20) state <= addr_cyc_hi;
else state <= prog_addr_delay;
end
addr_cyc_lo: begin
if(dly_cnt >= 15) state <= addr_cyc_hi;
else state <= addr_cyc_lo;
end
addr_cyc_hi: begin
if(dly_cnt >= 15) begin
if(cmd_pos >= terminal_pos) begin
if(cmd_reg[0] == 8'h50) state <= prog_write_delay;
else state <= cmd_cyc_2_pre;
end
else state <= addr_cyc_lo;
end
else state <= addr_cyc_hi;
end
cmd_cyc_2_pre: begin
if((cmd_reg[0] == 8'h45) && (dly_cnt >= 17)) state <= cmd_cyc_2_0;
else if(dly_cnt >= 100) state <= cmd_cyc_2_0;
else state <= cmd_cyc_2_pre;
end
prog_write_delay: begin
if(dly_cnt >= 20) state <= prog_read_ram;
else state <= prog_write_delay;
end
prog_hi_before_lo: begin
if(cyc_time > 10) begin
state <= prog_cycle_low;
cyc_time <= 0;
end
else begin
cyc_time <= cyc_time + 1;
state <= prog_hi_before_lo;
end
end
prog_cycle_low: begin
if(cyc_time > 15) begin
state <= prog_hi_after_lo;
cyc_time <= 0;
end
else begin
state <= prog_cycle_low;
cyc_time <= cyc_time + 1;
end
end
prog_hi_after_lo: begin
if(cyc_time >= 10) begin
if(num_read_cycles >= `NUM_ADDR) state <= cmd_cyc_2_pre;
else state <= prog_read_ram;
cyc_time <= 0;
end else begin
state <= prog_hi_after_lo;
cyc_time <= cyc_time + 1;
end
end
prog_read_ram: begin
state <= prog_latch_ram;
end
prog_latch_ram: begin
num_read_cycles <= num_read_cycles + 1;
prog_register <= ram_in;
state <= prog_hi_before_lo;
end
cmd_cyc_2_0: state <= cmd_cyc_2_1;
cmd_cyc_2_1: begin
if(cyc_time >= 7) begin
state <= cmd_cyc_2_2;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
cmd_cyc_2_2: begin
if(cyc_time >= 2) begin
state <= rb_wait_lo;
cyc_time <= 0;
end
else cyc_time <= cyc_time + 1;
end
rb_wait_lo: begin
if(rb == 0) state <= rb_wait_hi;
else state <= rb_wait_lo;
end
rb_wait_hi: begin
if(rb == 1) begin
if(cmd_reg[0] == 8'h52) state <= read_cycle_hi;
else state <= done;
end else state <= rb_wait_hi;
end
read_cycle_hi: begin
if(num_read_cycles == `NUM_ADDR ) state <= done;
else if(cyc_time > 10) begin
state <= read_cycle_lo;
cyc_time <= 0;
end
else begin
state <= read_cycle_hi;
cyc_time <= cyc_time + 1;
end
end
read_cycle_lo: begin
if(cyc_time > 10) begin
cyc_time <= 0;
state <= write_to_ram;
num_read_cycles <= num_read_cycles + 1;
end
else begin
state <= read_cycle_lo;
cyc_time <= cyc_time + 1;
end
end
write_to_ram: state <= read_cycle_hi;
done: begin
state <= init;
prog_register <= 8'h0;
end
default: state <= init;
endcase
end
wire [7:0] curr_cmd_val;
assign curr_cmd_val = cmd_reg[cmd_pos];
reg [7:0] cmd_byte_0, cmd_byte_1;
always @* begin
if((state == ram_req_cmd_read) ||
(state == read_cmd_to_reg)) ram_re = 1;
else if(state == prog_read_ram) ram_re = 1;
else ram_re = 0;
if((cmd_cyc_1_0 <= state) &&
(state <= cmd_cyc_2_2)) io_drive_en = 1;
else if((state == prog_hi_before_lo) || (state == prog_hi_after_lo)
|| (state == prog_cycle_low) || (state == prog_latch_ram)
|| (state == prog_read_ram)) io_drive_en = 1;
else io_drive_en = 0;
if( cmd_reg[0] == 8'h45) begin
cmd_byte_0 = 8'h60;
cmd_byte_1 = 8'hD0;
end else if(cmd_reg[0] == 8'h50) begin
cmd_byte_0 = 8'h80;
cmd_byte_1 = 8'h10;
end else if(cmd_reg[0] == 8'h52) begin
cmd_byte_0 = 8'h00;
cmd_byte_1 = 8'h30;
end else begin
cmd_byte_0 = 8'h00;
cmd_byte_1 = 8'h00;
end
if((cmd_cyc_1_0 <= state) &&
(state <= cmd_cyc_1_2)) io_write = cmd_byte_0;
else if((cmd_cyc_2_0 <= state) &&
(state <= cmd_cyc_2_2)) io_write = cmd_byte_1;
else if((addr_cyc_lo <= state) &&
(state <= addr_cyc_hi)) io_write = curr_cmd_val;
else if((state == prog_hi_before_lo) || (state == prog_cycle_low)
|| (state == prog_hi_after_lo) || (state == prog_read_ram)
|| (state == prog_latch_ram)) io_write = prog_register;
else io_write = 8'h00;
if((state == read_cmd_to_reg) || (state == write_to_ram)) ram_addr_up = 1;
else if(state == prog_read_ram) ram_addr_up = 1;
else ram_addr_up = 0;
if((state == init) || (state == rb_wait_hi)) ram_addr_set = 1;
else if(state == prog_write_delay) ram_addr_set = 1;
else ram_addr_set = 0;
if(state == rb_wait_hi) ram_addr_in = `CMD_SIZE + 1;
else if(state == prog_write_delay) ram_addr_in = `CMD_SIZE + 1;
else ram_addr_in = 12'h000;
if((addr_cyc_lo <= state) &&
(state <= cmd_cyc_2_pre)) dly_cnt_en = 1;
else if(state == prog_addr_delay) dly_cnt_en = 1;
else if(state == prog_write_delay) dly_cnt_en = 1;
else dly_cnt_en = 0;
if(state == init) dly_cnt_clr = 1;
else if((state == addr_cyc_lo) && (dly_cnt >= 15)) dly_cnt_clr = 1;
else if((state == addr_cyc_hi) && (dly_cnt >= 15)) dly_cnt_clr = 1;
else if((state == prog_addr_delay) && (dly_cnt >= 20)) dly_cnt_clr = 1;
else if((state == prog_write_delay) && (dly_cnt >= 20)) dly_cnt_clr = 1;
else dly_cnt_clr = 0;
if((state == addr_cyc_lo) && (dly_cnt == 15)) cmd_pos_up = 1;
else cmd_pos_up = 0;
if(state == init) cmd_pos_set = 1;
else cmd_pos_set = 0;
cmd_pos_in = 2;
if(((cmd_cyc_1_0 <= state) && (state <= cmd_cyc_1_2)) ||
((cmd_cyc_2_0 <= state) && (state <= cmd_cyc_2_2))) cle = 1;
else cle = 0;
if(state > read_cmd_to_reg) ce = 0;
else ce = 1;
if(state == read_cycle_lo) re = 0;
else re = 1;
if((cmd_cyc_1_2 < state) && (state < cmd_cyc_2_pre)) ale = 1;
else ale = 0;
if(state == addr_cyc_lo) we = 0;
else if(state == cmd_cyc_1_1) we = 0;
else if(state == cmd_cyc_2_1) we = 0;
else if(state == prog_cycle_low) we = 0;
else we = 1;
if(cmd_reg[0] == 8'h45) terminal_pos = (`CMD_SIZE - 2);
else terminal_pos = `CMD_SIZE;
if(state == write_to_ram) ram_we = 1;
else ram_we = 0;
if(state == done) comm_done = 1;
else comm_done = 0;
end
endmodule | 20 |
4,667 | data/full_repos/permissive/111258339/src/mips.v | 111,258,339 | mips.v | v | 195 | 97 | [] | [] | [] | [(23, 215)] | null | null | 1: b'%Error: data/full_repos/permissive/111258339/src/mips.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n src/Define/ctrl_encode_def.v\n src/Define/ctrl_encode_def.v.v\n src/Define/ctrl_encode_def.v.sv\n obj_dir/src/Define/ctrl_encode_def.v\n obj_dir/src/Define/ctrl_encode_def.v.v\n obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/mips.v:54: Define or directive not defined: \'`ALUOP_ADDU\'\n .ALUOp(`ALUOP_ADDU),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/mips.v:76: Define or directive not defined: \'`EXTOP_SIGNED\'\n .EXTOp(`EXTOP_SIGNED),\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 3,080 | module | module mips(
input wire clk,
input wire reset
);
wire[31:0] pc_current;
wire[31:0] pc_temp;
wire[31:0] pc_next;
wire[31:0] pc_add4;
wire[31:0] pc_branch;
wire[31:0] instr;
wire[31:0] rf_read_data1;
wire[31:0] rf_read_data2;
wire[4:0] write_addr;
wire[4:0] final_write_addr;
wire[31:0] ext_output;
wire[31:0] alu_num_1;
wire[31:0] alu_num_2;
wire Zero;
wire[31:0] alu_result;
wire[31:0] dm_write_data;
wire[31:0] dm_read_data;
wire[31:0] mem2reg_data;
wire[31:0] final_mem2reg_data;
wire[1:0] ALUOp;
wire ALUSrc;
wire RegWrite;
wire RegDst;
wire MemWrite;
wire MemRead;
wire Mem2Reg;
wire Branch;
wire Jump;
wire isJal;
assign pc_add4 = pc_current + 4;
pc pc(
.clk(clk),
.reset(reset),
.data(pc_next),
.dout(pc_current)
);
alu pc_branch_alu(
.ALUOp(`ALUOP_ADDU),
.num_1(pc_add4),
.num_2({ext_output[29:0], 2'b00}),
.result(pc_branch)
);
mux branch_mux(
.d0(pc_add4),
.d1(pc_branch),
.signal(Branch & Zero),
.output_data(pc_temp)
);
mux jump_mux(
.d0({pc_add4[31:28], instr[25:0], 2'b00}),
.d1(pc_temp),
.signal(Jump),
.output_data(pc_next)
);
EXT ext(
.Immediate16(instr[15:0]),
.EXTOp(`EXTOP_SIGNED),
.Immediate32(ext_output)
);
im im(
.addr(pc_current[11:2]),
.dout(instr)
);
ctrl ctrl(
.OP(instr[31:26]),
.funct(instr[5:0]),
.ALUOp(ALUOp),
.ALUSrc(ALUSrc),
.RegWrite(RegWrite),
.RegDst(RegDst),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Mem2Reg(Mem2Reg),
.Branch(Branch),
.Jump(Jump)
);
mux write_addr_mux(
.d0(instr[20:16]),
.d1(instr[15:11]),
.signal(RegDst),
.output_data(write_addr)
);
mux jal_addr_mux(
.d0(31),
.d1(write_addr),
.signal(Jump),
.output_data(final_write_addr)
);
mux jal_data_mux(
.d0(pc_add4),
.d1(mem2reg_data),
.signal(Jump),
.output_data(final_mem2reg_data)
);
RF rf(
.clk(clk),
.RA1(instr[25:21]),
.RA2(instr[20:16]),
.WA1(final_write_addr),
.WD(final_mem2reg_data),
.RD1(rf_read_data1),
.RD2(rf_read_data2),
.RegWrite(RegWrite)
);
assign alu_num_1 = rf_read_data1;
mux alu_src_mux(
.d0(rf_read_data2),
.d1(ext_output),
.signal(ALUSrc),
.output_data(alu_num_2)
);
alu alu(
.num_1(alu_num_1),
.num_2(alu_num_2),
.ALUOp(ALUOp),
.Zero(Zero),
.result(alu_result)
);
assign dm_write_data = rf_read_data2;
dm dm(
.clk(clk),
.addr(alu_result),
.write_data(dm_write_data),
.MemWrite(MemWrite),
.read_data(dm_read_data)
);
mux mem2reg_mux(
.d0(alu_result),
.d1(dm_read_data),
.signal(Mem2Reg),
.output_data(mem2reg_data)
);
always @(clk) begin
if (!clk) begin
$stop;
end
end
endmodule | module mips(
input wire clk,
input wire reset
); |
wire[31:0] pc_current;
wire[31:0] pc_temp;
wire[31:0] pc_next;
wire[31:0] pc_add4;
wire[31:0] pc_branch;
wire[31:0] instr;
wire[31:0] rf_read_data1;
wire[31:0] rf_read_data2;
wire[4:0] write_addr;
wire[4:0] final_write_addr;
wire[31:0] ext_output;
wire[31:0] alu_num_1;
wire[31:0] alu_num_2;
wire Zero;
wire[31:0] alu_result;
wire[31:0] dm_write_data;
wire[31:0] dm_read_data;
wire[31:0] mem2reg_data;
wire[31:0] final_mem2reg_data;
wire[1:0] ALUOp;
wire ALUSrc;
wire RegWrite;
wire RegDst;
wire MemWrite;
wire MemRead;
wire Mem2Reg;
wire Branch;
wire Jump;
wire isJal;
assign pc_add4 = pc_current + 4;
pc pc(
.clk(clk),
.reset(reset),
.data(pc_next),
.dout(pc_current)
);
alu pc_branch_alu(
.ALUOp(`ALUOP_ADDU),
.num_1(pc_add4),
.num_2({ext_output[29:0], 2'b00}),
.result(pc_branch)
);
mux branch_mux(
.d0(pc_add4),
.d1(pc_branch),
.signal(Branch & Zero),
.output_data(pc_temp)
);
mux jump_mux(
.d0({pc_add4[31:28], instr[25:0], 2'b00}),
.d1(pc_temp),
.signal(Jump),
.output_data(pc_next)
);
EXT ext(
.Immediate16(instr[15:0]),
.EXTOp(`EXTOP_SIGNED),
.Immediate32(ext_output)
);
im im(
.addr(pc_current[11:2]),
.dout(instr)
);
ctrl ctrl(
.OP(instr[31:26]),
.funct(instr[5:0]),
.ALUOp(ALUOp),
.ALUSrc(ALUSrc),
.RegWrite(RegWrite),
.RegDst(RegDst),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Mem2Reg(Mem2Reg),
.Branch(Branch),
.Jump(Jump)
);
mux write_addr_mux(
.d0(instr[20:16]),
.d1(instr[15:11]),
.signal(RegDst),
.output_data(write_addr)
);
mux jal_addr_mux(
.d0(31),
.d1(write_addr),
.signal(Jump),
.output_data(final_write_addr)
);
mux jal_data_mux(
.d0(pc_add4),
.d1(mem2reg_data),
.signal(Jump),
.output_data(final_mem2reg_data)
);
RF rf(
.clk(clk),
.RA1(instr[25:21]),
.RA2(instr[20:16]),
.WA1(final_write_addr),
.WD(final_mem2reg_data),
.RD1(rf_read_data1),
.RD2(rf_read_data2),
.RegWrite(RegWrite)
);
assign alu_num_1 = rf_read_data1;
mux alu_src_mux(
.d0(rf_read_data2),
.d1(ext_output),
.signal(ALUSrc),
.output_data(alu_num_2)
);
alu alu(
.num_1(alu_num_1),
.num_2(alu_num_2),
.ALUOp(ALUOp),
.Zero(Zero),
.result(alu_result)
);
assign dm_write_data = rf_read_data2;
dm dm(
.clk(clk),
.addr(alu_result),
.write_data(dm_write_data),
.MemWrite(MemWrite),
.read_data(dm_read_data)
);
mux mem2reg_mux(
.d0(alu_result),
.d1(dm_read_data),
.signal(Mem2Reg),
.output_data(mem2reg_data)
);
always @(clk) begin
if (!clk) begin
$stop;
end
end
endmodule | 6 |
4,669 | data/full_repos/permissive/111258339/src/Control/ctrl.v | 111,258,339 | ctrl.v | v | 134 | 59 | [] | [] | [] | [(23, 152)] | null | null | 1: b'%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n src/Define/ctrl_encode_def.v\n src/Define/ctrl_encode_def.v.v\n src/Define/ctrl_encode_def.v.sv\n obj_dir/src/Define/ctrl_encode_def.v\n obj_dir/src/Define/ctrl_encode_def.v.v\n obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:46: Define or directive not defined: \'`CTRL_OP_RTYPE\'\n `CTRL_OP_RTYPE: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:46: syntax error, unexpected \':\', expecting endcase\n `CTRL_OP_RTYPE: begin\n ^\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:48: Define or directive not defined: \'`CTRL_FUNCT_ADDU\'\n `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:48: Define or directive not defined: \'`ALUOP_ADDU\'\n `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:49: Define or directive not defined: \'`CTRL_FUNCT_SUBU\'\n `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:49: Define or directive not defined: \'`ALUOP_SUBU\'\n `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:50: Define or directive not defined: \'`ALUOP_ADDU\'\n default: ALUOp = `ALUOP_ADDU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:63: Define or directive not defined: \'`CTRL_OP_ORI\'\n `CTRL_OP_ORI: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CTRL_OP_ORI: begin\n ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:64: Define or directive not defined: \'`ALUOP_ORI\'\n ALUOp = `ALUOP_ORI;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:75: Define or directive not defined: \'`CTRL_OP_LW\'\n `CTRL_OP_LW: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:75: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CTRL_OP_LW: begin\n ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:86: Define or directive not defined: \'`CTRL_OP_SW\'\n `CTRL_OP_SW: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:86: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CTRL_OP_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:97: Define or directive not defined: \'`CTRL_OP_BEQ\'\n `CTRL_OP_BEQ: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CTRL_OP_BEQ: begin\n ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:108: Define or directive not defined: \'`CTRL_OP_JAL\'\n `CTRL_OP_JAL: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:108: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CTRL_OP_JAL: begin\n ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:120: syntax error, unexpected \':\', expecting clocking\n default: begin\n ^\n%Error: Cannot continue\n' | 3,082 | module | module ctrl(
input wire clk,
input wire reset,
input wire[5:0] OP,
input wire[5:0] funct,
input wire Zero,
output reg RegWrite,
output reg RegDst,
output reg[1:0] EXTOp,
output reg MemWrite,
output reg MemRead,
output reg ALUSrc,
output reg[1:0] ALUOp,
output reg Mem2Reg,
output reg Branch,
output reg Jump
);
initial begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
always @(*) begin
case (OP)
`CTRL_OP_RTYPE: begin
case(funct)
`CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;
`CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;
default: ALUOp = `ALUOP_ADDU;
endcase
ALUSrc = 0;
RegWrite = 1;
RegDst = 1;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_ORI: begin
ALUOp = `ALUOP_ORI;
ALUSrc = 1;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_LW: begin
ALUSrc = 1;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 1;
Mem2Reg = 1;
Branch = 0;
Jump = 1;
end
`CTRL_OP_SW: begin
ALUSrc = 1;
RegWrite = 0;
RegDst = 0;
MemWrite = 1;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_BEQ: begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 1;
Jump = 1;
end
`CTRL_OP_JAL: begin
ALUSrc = 0;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 0;
$display("Jump!---------------");
end
default: begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
endcase
end
endmodule | module ctrl(
input wire clk,
input wire reset,
input wire[5:0] OP,
input wire[5:0] funct,
input wire Zero,
output reg RegWrite,
output reg RegDst,
output reg[1:0] EXTOp,
output reg MemWrite,
output reg MemRead,
output reg ALUSrc,
output reg[1:0] ALUOp,
output reg Mem2Reg,
output reg Branch,
output reg Jump
); |
initial begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
always @(*) begin
case (OP)
`CTRL_OP_RTYPE: begin
case(funct)
`CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;
`CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;
default: ALUOp = `ALUOP_ADDU;
endcase
ALUSrc = 0;
RegWrite = 1;
RegDst = 1;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_ORI: begin
ALUOp = `ALUOP_ORI;
ALUSrc = 1;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_LW: begin
ALUSrc = 1;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 1;
Mem2Reg = 1;
Branch = 0;
Jump = 1;
end
`CTRL_OP_SW: begin
ALUSrc = 1;
RegWrite = 0;
RegDst = 0;
MemWrite = 1;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
`CTRL_OP_BEQ: begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 1;
Jump = 1;
end
`CTRL_OP_JAL: begin
ALUSrc = 0;
RegWrite = 1;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 0;
$display("Jump!---------------");
end
default: begin
ALUSrc = 0;
RegWrite = 0;
RegDst = 0;
MemWrite = 0;
MemRead = 0;
Mem2Reg = 0;
Branch = 0;
Jump = 1;
end
endcase
end
endmodule | 6 |
4,672 | data/full_repos/permissive/111258339/src/Datapath/EXT.v | 111,258,339 | EXT.v | v | 22 | 86 | [] | [] | [] | [(22, 41)] | null | null | 1: b'%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n src/Define/ctrl_encode_def.v\n src/Define/ctrl_encode_def.v.v\n src/Define/ctrl_encode_def.v.sv\n obj_dir/src/Define/ctrl_encode_def.v\n obj_dir/src/Define/ctrl_encode_def.v.v\n obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:14: Define or directive not defined: \'`EXTOP_ZERO\'\n `EXTOP_ZERO: Immediate32 <= {{16\'b0}, Immediate16[15:0]};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:14: syntax error, unexpected \':\', expecting endcase\n `EXTOP_ZERO: Immediate32 <= {{16\'b0}, Immediate16[15:0]};\n ^\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:15: Define or directive not defined: \'`EXTOP_SIGNED\'\n `EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:16: Define or directive not defined: \'`EXTOP_INST\'\n `EXTOP_INST: Immediate32 <= 32\'b0;\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 3,085 | module | module EXT(
input wire[15:0] Immediate16,
input wire[1:0] EXTOp,
output reg[31:0] Immediate32
);
initial begin
Immediate32 = 32'b00;
end
always @(Immediate16) begin
case(EXTOp)
`EXTOP_ZERO: Immediate32 <= {{16'b0}, Immediate16[15:0]};
`EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};
`EXTOP_INST: Immediate32 <= 32'b0;
default: Immediate32 <= {{16'b0}, Immediate16[15:0]};
endcase
$display("EXT in: %x, out: %x", Immediate16, Immediate32);
end
endmodule | module EXT(
input wire[15:0] Immediate16,
input wire[1:0] EXTOp,
output reg[31:0] Immediate32
); |
initial begin
Immediate32 = 32'b00;
end
always @(Immediate16) begin
case(EXTOp)
`EXTOP_ZERO: Immediate32 <= {{16'b0}, Immediate16[15:0]};
`EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};
`EXTOP_INST: Immediate32 <= 32'b0;
default: Immediate32 <= {{16'b0}, Immediate16[15:0]};
endcase
$display("EXT in: %x, out: %x", Immediate16, Immediate32);
end
endmodule | 6 |
4,674 | data/full_repos/permissive/111258339/src/Datapath/RF.v | 111,258,339 | RF.v | v | 48 | 107 | [] | [] | [] | [(1, 47)] | null | data/verilator_xmls/7d547fb6-a561-4f6e-90ea-66e5518e35af.xml | null | 3,090 | module | module RF(
input clk,
input RegWrite,
input [4:0]WA1,
input [4:0]RA1,
input [4:0]RA2,
input [31:0]WD,
output [31:0]RD1,
output [31:0]RD2
);
reg[31:0] register[31:0];
integer i, fd, cycles;
initial begin
fd = $fopen("RF_Results.txt","w");
cycles = 0;
for(i = 0; i < 32; i = i + 1)
register[i] = 0;
end
always@(posedge clk) begin
if (WA1 != 0 && RegWrite) begin
register[WA1] = WD[31:0];
$display("RF Write: %x to %d", WD[31:0], WA1);
end
$display("----------------------------------- RF info -----------------------------------");
$fwrite(fd, "--------------------------------- Cycle%d ------------------------------\n", cycles);
cycles = cycles + 1;
for(i = 0; i < 32; i = i + 1)
if (register[i] != 0) begin
$display("RF %d: %x", i, register[i]);
$fwrite(fd, "RF %d: %x\n", i, register[i]);
end
$display("----------------------------------- RF fin -----------------------------------");
end
assign RD1 = register[RA1];
assign RD2 = register[RA2];
endmodule | module RF(
input clk,
input RegWrite,
input [4:0]WA1,
input [4:0]RA1,
input [4:0]RA2,
input [31:0]WD,
output [31:0]RD1,
output [31:0]RD2
); |
reg[31:0] register[31:0];
integer i, fd, cycles;
initial begin
fd = $fopen("RF_Results.txt","w");
cycles = 0;
for(i = 0; i < 32; i = i + 1)
register[i] = 0;
end
always@(posedge clk) begin
if (WA1 != 0 && RegWrite) begin
register[WA1] = WD[31:0];
$display("RF Write: %x to %d", WD[31:0], WA1);
end
$display("----------------------------------- RF info -----------------------------------");
$fwrite(fd, "--------------------------------- Cycle%d ------------------------------\n", cycles);
cycles = cycles + 1;
for(i = 0; i < 32; i = i + 1)
if (register[i] != 0) begin
$display("RF %d: %x", i, register[i]);
$fwrite(fd, "RF %d: %x\n", i, register[i]);
end
$display("----------------------------------- RF fin -----------------------------------");
end
assign RD1 = register[RA1];
assign RD2 = register[RA2];
endmodule | 6 |
4,676 | data/full_repos/permissive/111258339/test/Datapath/alu_tb.v | 111,258,339 | alu_tb.v | v | 80 | 89 | [] | [] | [] | [(7, 79)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111258339/test/Datapath/alu_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #1 clk<=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111258339/test/Datapath/alu_tb.v:39: Cannot find file containing module: \'alu\'\n alu alu0(\n ^~~\n ... Looked in:\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu.v\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,097 | module | module alu_tb();
`timescale 1ns/1ps
reg clk;
reg [31:0] num_1;
reg [31:0] num_2;
reg [1:0] ALUOp;
reg Zero_output;
reg[31:0] result_output;
wire Zero;
wire[31:0] result;
integer fd;
initial
begin
clk = 1;
num_1 = 32'b0;
num_2 = 32'b0;
ALUOp = 2'b0;
Zero_output = 1;
result_output = 32'b0;
fd=$fopen("test/data/Datapath/alu_td.txt","r");
end
always
#1 clk<=~clk;
alu alu0(
.num_1(num_1),
.num_2(num_2),
.ALUOp(ALUOp),
.Zero(Zero),
.result(result)
);
always@(posedge clk)
begin
if (result != result_output)
begin
$display("testcase failed! result: %x, result_data: %x", result, result_output);
$stop;
end
if (Zero != Zero_output)
begin
$display("testcase failed! Zero: %x, Zero_output: %x", Zero, Zero_output);
$stop;
end
$fscanf(
fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
num_1, num_2, ALUOp, Zero_output, result_output
);
$display(
"testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
num_1, num_2, ALUOp, Zero, Zero_output, result, result_output
);
if ($feof(fd))
begin
$fclose(fd);
$display("pass!");
$stop;
end
end
endmodule | module alu_tb(); |
`timescale 1ns/1ps
reg clk;
reg [31:0] num_1;
reg [31:0] num_2;
reg [1:0] ALUOp;
reg Zero_output;
reg[31:0] result_output;
wire Zero;
wire[31:0] result;
integer fd;
initial
begin
clk = 1;
num_1 = 32'b0;
num_2 = 32'b0;
ALUOp = 2'b0;
Zero_output = 1;
result_output = 32'b0;
fd=$fopen("test/data/Datapath/alu_td.txt","r");
end
always
#1 clk<=~clk;
alu alu0(
.num_1(num_1),
.num_2(num_2),
.ALUOp(ALUOp),
.Zero(Zero),
.result(result)
);
always@(posedge clk)
begin
if (result != result_output)
begin
$display("testcase failed! result: %x, result_data: %x", result, result_output);
$stop;
end
if (Zero != Zero_output)
begin
$display("testcase failed! Zero: %x, Zero_output: %x", Zero, Zero_output);
$stop;
end
$fscanf(
fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
num_1, num_2, ALUOp, Zero_output, result_output
);
$display(
"testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
num_1, num_2, ALUOp, Zero, Zero_output, result, result_output
);
if ($feof(fd))
begin
$fclose(fd);
$display("pass!");
$stop;
end
end
endmodule | 6 |
4,677 | data/full_repos/permissive/111258339/test/Datapath/RF_tb.v | 111,258,339 | RF_tb.v | v | 92 | 112 | [] | [] | [] | [(7, 92)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #1 clk<=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n RFWr = 4\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n WA1 = 4\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n RA1 = 4\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:38: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n RA2 = 4\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n RD1_output = 4\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance RF_tb\n RD2_output = 4\'b0;\n ^\n%Error: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:49: Cannot find file containing module: \'RF\'\n RF RF0(\n ^~\n ... Looked in:\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF.v\n data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF.sv\n RF\n RF.v\n RF.sv\n obj_dir/RF\n obj_dir/RF.v\n obj_dir/RF.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,098 | module | module RF_tb();
`timescale 1ns/1ps
reg clk;
reg RFWr;
reg [4:0]WA1;
reg [4:0]RA1;
reg [4:0]RA2;
reg [31:0]WD;
wire [31:0]RD1;
wire [31:0]RD2;
reg [31:0]RD1_tmp;
reg [31:0]RD2_tmp;
reg [31:0]RD1_output;
reg [31:0]RD2_output;
integer fd, line_count;
initial
begin
clk = 1;
line_count = 0;
RFWr = 4'b0;
WA1 = 4'b0;
RA1 = 4'b0;
RA2 = 4'b0;
WD = 32'b0;
RD1_output = 4'b0;
RD2_output = 4'b0;
fd=$fopen("test/data/Datapath/rf_td.txt","r");
end
always
#1 clk<=~clk;
RF RF0(
.clk(clk),
.RFWr(RFWr),
.WA1(WA1),
.RA1(RA1),
.RA2(RA2),
.WD(WD),
.RD1(RD1),
.RD2(RD2)
);
always@(posedge clk)
begin
line_count <= line_count + 1;
RD1_tmp = RD1[31:0];
RD2_tmp = RD2[31:0];
if (RD1_output != RD1_tmp)
begin
$display("testcase failed! RD1: %x, RD1_output: %x", RD1_tmp, RD1_output);
$stop;
end
if (RD2_output != RD2_tmp)
begin
$display("testcase failed! RD2: %x, RD2_output: %x", RD2_tmp, RD2_output);
$stop;
end
$fscanf(fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output);
$display(
"testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t Getdata: 0x%x\t0x%x",
RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output, RD1_tmp, RD2_tmp
);
if ($feof(fd))
begin
$fclose(fd);
$display("pass!");
$stop;
end
end
endmodule | module RF_tb(); |
`timescale 1ns/1ps
reg clk;
reg RFWr;
reg [4:0]WA1;
reg [4:0]RA1;
reg [4:0]RA2;
reg [31:0]WD;
wire [31:0]RD1;
wire [31:0]RD2;
reg [31:0]RD1_tmp;
reg [31:0]RD2_tmp;
reg [31:0]RD1_output;
reg [31:0]RD2_output;
integer fd, line_count;
initial
begin
clk = 1;
line_count = 0;
RFWr = 4'b0;
WA1 = 4'b0;
RA1 = 4'b0;
RA2 = 4'b0;
WD = 32'b0;
RD1_output = 4'b0;
RD2_output = 4'b0;
fd=$fopen("test/data/Datapath/rf_td.txt","r");
end
always
#1 clk<=~clk;
RF RF0(
.clk(clk),
.RFWr(RFWr),
.WA1(WA1),
.RA1(RA1),
.RA2(RA2),
.WD(WD),
.RD1(RD1),
.RD2(RD2)
);
always@(posedge clk)
begin
line_count <= line_count + 1;
RD1_tmp = RD1[31:0];
RD2_tmp = RD2[31:0];
if (RD1_output != RD1_tmp)
begin
$display("testcase failed! RD1: %x, RD1_output: %x", RD1_tmp, RD1_output);
$stop;
end
if (RD2_output != RD2_tmp)
begin
$display("testcase failed! RD2: %x, RD2_output: %x", RD2_tmp, RD2_output);
$stop;
end
$fscanf(fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output);
$display(
"testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t Getdata: 0x%x\t0x%x",
RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output, RD1_tmp, RD2_tmp
);
if ($feof(fd))
begin
$fclose(fd);
$display("pass!");
$stop;
end
end
endmodule | 6 |
4,684 | data/full_repos/permissive/111285134/src/IM.v | 111,285,134 | IM.v | v | 31 | 40 | [] | [] | [] | [(1, 31)] | null | data/verilator_xmls/f6a8befd-b6c7-4760-946f-50d36cbe72b2.xml | null | 3,106 | module | module IM(OpCode,ImAdress);
input [31:0] ImAdress;
output reg [31:0] OpCode;
reg [31:0] IMem[1024:0];
initial
begin
IMem[0]=32'h341d000c;
IMem[1]=32'h34021234;
IMem[2]=32'h34033456;
IMem[3]=32'h00432021;
IMem[4]=32'h00643023;
IMem[5]=32'hac020000;
IMem[6]=32'hac030004;
IMem[7]=32'hafa40004;
IMem[8]=32'h8c050000;
IMem[9]=32'h10450001;
IMem[10]=32'h8fa30004;
IMem[11]=32'h8c050004;
IMem[12]=32'h1065fffd;
IMem[13]=32'h0c10000e;
IMem[14]=32'h00c23023;
IMem[15]=32'hafa6fffc;
IMem[16]=32'h1064ffff;
end
always@(ImAdress)
begin
OpCode = IMem[(ImAdress-4194304)>>2];
end
endmodule | module IM(OpCode,ImAdress); |
input [31:0] ImAdress;
output reg [31:0] OpCode;
reg [31:0] IMem[1024:0];
initial
begin
IMem[0]=32'h341d000c;
IMem[1]=32'h34021234;
IMem[2]=32'h34033456;
IMem[3]=32'h00432021;
IMem[4]=32'h00643023;
IMem[5]=32'hac020000;
IMem[6]=32'hac030004;
IMem[7]=32'hafa40004;
IMem[8]=32'h8c050000;
IMem[9]=32'h10450001;
IMem[10]=32'h8fa30004;
IMem[11]=32'h8c050004;
IMem[12]=32'h1065fffd;
IMem[13]=32'h0c10000e;
IMem[14]=32'h00c23023;
IMem[15]=32'hafa6fffc;
IMem[16]=32'h1064ffff;
end
always@(ImAdress)
begin
OpCode = IMem[(ImAdress-4194304)>>2];
end
endmodule | 1 |
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