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4,685 | data/full_repos/permissive/111285134/src/mips.v | 111,285,134 | mips.v | v | 67 | 137 | [] | [] | [] | [(1, 67)] | null | null | 1: b"%Error: data/full_repos/permissive/111285134/src/mips.v:10: Cannot find file containing module: 'RF'\n RF RegisteFile(Read_Addr_1, Read_Addr_2, Write_Addr,Write_Data, RFWr, clk, Read_Data_1, Read_Data_2);\n ^~\n ... Looked in:\n data/full_repos/permissive/111285134/src,data/full_repos/permissive/111285134/RF\n data/full_repos/permissive/111285134/src,data/full_repos/permissive/111285134/RF.v\n data/full_repos/permissive/111285134/src,data/full_repos/permissive/111285134/RF.sv\n RF\n RF.v\n RF.sv\n obj_dir/RF\n obj_dir/RF.v\n obj_dir/RF.sv\n%Error: data/full_repos/permissive/111285134/src/mips.v:17: Cannot find file containing module: 'alu'\n alu AALLUU(ALU_C, Zero, ALU_A, ALU_B, ALUOp);\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:21: Cannot find file containing module: 'IM'\n IM InstructionMemory(Instruction, Read_Address);\n ^~\n%Error: data/full_repos/permissive/111285134/src/mips.v:27: Cannot find file containing module: 'PcUnit'\n PcUnit pppccc(PC, PcReSet,NPCOp, clk, Adress);\n ^~~~~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:32: Cannot find file containing module: 'EXT'\n EXT eexxtt(Imm16, EXTOp, Imm32);\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:38: Cannot find file containing module: 'DM'\n DM DataMemory(dout,addr,din,DMWr,clk);\n ^~\n%Error: data/full_repos/permissive/111285134/src/mips.v:41: Cannot find file containing module: 'addpc'\n addpc addppcc(PC,Imm32,adder);\n ^~~~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:44: Cannot find file containing module: 'mux'\n mux ALUsec(Bsel,ALU_B,Read_Data_2,Imm32);\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:47: Cannot find file containing module: 'mux'\n mux #(4,2,32) RFWsec(WDSel,Write_Data,ALU_C,dout,PC);\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:50: Cannot find file containing module: 'mux'\n mux #(4,2,5) RFWAsec(GPRSel,Write_Addr,Instruction[15:11],Instruction[20:16],5'b11111);\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:53: Cannot find file containing module: 'mux'\n mux #(4,2,32) PCsssel(NPCOp,Adress,32'b0,adder,{6'b0,Instruction[25:0]});\n ^~~\n%Error: data/full_repos/permissive/111285134/src/mips.v:56: Cannot find file containing module: 'ctrl'\n ctrl Control(clk, rst, Instruction[31:26], Instruction[5:0], Zero, Bsel, WDSel, RFWr, DMWr, NPCOp, EXTOp, ALUOp,PCWr, IRWr, GPRSel);\n ^~~~\n%Error: Exiting due to 12 error(s)\n" | 3,107 | module | module mips(clk,PcReSet,PC,Instruction);
wire [4:0]Read_Addr_1;
wire [4:0]Read_Addr_2;
wire [4:0]Write_Addr;
wire [31:0]Write_Data;
wire RFWr;
input clk;
wire [31:0]Read_Data_1;
wire [31:0]Read_Data_2;
RF RegisteFile(Read_Addr_1, Read_Addr_2, Write_Addr,Write_Data, RFWr, clk, Read_Data_1, Read_Data_2);
wire [31:0]ALU_A;
wire [31:0]ALU_B;
wire Zero;
wire [1:0]ALUOp;
wire [31:0]ALU_C;
alu AALLUU(ALU_C, Zero, ALU_A, ALU_B, ALUOp);
output wire [31:0]Instruction;
wire [31:0] Read_Address;
IM InstructionMemory(Instruction, Read_Address);
output wire [31:0]PC;
input PcReSet;
wire [31:0]Adress;
wire [1:0] NPCOp;
PcUnit pppccc(PC, PcReSet,NPCOp, clk, Adress);
wire [15:0]Imm16;
wire [1:0]EXTOp;
wire [31:0]Imm32;
EXT eexxtt(Imm16, EXTOp, Imm32);
wire [31:0]dout;
wire [31:0]addr;
wire [31:0]din;
wire DMWr;
DM DataMemory(dout,addr,din,DMWr,clk);
wire [31:0]adder;
addpc addppcc(PC,Imm32,adder);
wire Bsel;
mux ALUsec(Bsel,ALU_B,Read_Data_2,Imm32);
wire [1:0]WDSel;
mux #(4,2,32) RFWsec(WDSel,Write_Data,ALU_C,dout,PC);
wire [1:0]GPRSel;
mux #(4,2,5) RFWAsec(GPRSel,Write_Addr,Instruction[15:11],Instruction[20:16],5'b11111);
mux #(4,2,32) PCsssel(NPCOp,Adress,32'b0,adder,{6'b0,Instruction[25:0]});
wire rst,IRWr,PCWr;
ctrl Control(clk, rst, Instruction[31:26], Instruction[5:0], Zero, Bsel, WDSel, RFWr, DMWr, NPCOp, EXTOp, ALUOp,PCWr, IRWr, GPRSel);
assign Read_Addr_1 = Instruction[25:21];
assign Read_Addr_2 = Instruction[20:16];
assign ALU_A = Read_Data_1;
assign din = Read_Data_2;
assign addr = ALU_C;
assign Read_Address = PC;
assign Imm16 = Instruction[15:0];
endmodule | module mips(clk,PcReSet,PC,Instruction); |
wire [4:0]Read_Addr_1;
wire [4:0]Read_Addr_2;
wire [4:0]Write_Addr;
wire [31:0]Write_Data;
wire RFWr;
input clk;
wire [31:0]Read_Data_1;
wire [31:0]Read_Data_2;
RF RegisteFile(Read_Addr_1, Read_Addr_2, Write_Addr,Write_Data, RFWr, clk, Read_Data_1, Read_Data_2);
wire [31:0]ALU_A;
wire [31:0]ALU_B;
wire Zero;
wire [1:0]ALUOp;
wire [31:0]ALU_C;
alu AALLUU(ALU_C, Zero, ALU_A, ALU_B, ALUOp);
output wire [31:0]Instruction;
wire [31:0] Read_Address;
IM InstructionMemory(Instruction, Read_Address);
output wire [31:0]PC;
input PcReSet;
wire [31:0]Adress;
wire [1:0] NPCOp;
PcUnit pppccc(PC, PcReSet,NPCOp, clk, Adress);
wire [15:0]Imm16;
wire [1:0]EXTOp;
wire [31:0]Imm32;
EXT eexxtt(Imm16, EXTOp, Imm32);
wire [31:0]dout;
wire [31:0]addr;
wire [31:0]din;
wire DMWr;
DM DataMemory(dout,addr,din,DMWr,clk);
wire [31:0]adder;
addpc addppcc(PC,Imm32,adder);
wire Bsel;
mux ALUsec(Bsel,ALU_B,Read_Data_2,Imm32);
wire [1:0]WDSel;
mux #(4,2,32) RFWsec(WDSel,Write_Data,ALU_C,dout,PC);
wire [1:0]GPRSel;
mux #(4,2,5) RFWAsec(GPRSel,Write_Addr,Instruction[15:11],Instruction[20:16],5'b11111);
mux #(4,2,32) PCsssel(NPCOp,Adress,32'b0,adder,{6'b0,Instruction[25:0]});
wire rst,IRWr,PCWr;
ctrl Control(clk, rst, Instruction[31:26], Instruction[5:0], Zero, Bsel, WDSel, RFWr, DMWr, NPCOp, EXTOp, ALUOp,PCWr, IRWr, GPRSel);
assign Read_Addr_1 = Instruction[25:21];
assign Read_Addr_2 = Instruction[20:16];
assign ALU_A = Read_Data_1;
assign din = Read_Data_2;
assign addr = ALU_C;
assign Read_Address = PC;
assign Imm16 = Instruction[15:0];
endmodule | 1 |
4,688 | data/full_repos/permissive/111285134/src/RF.v | 111,285,134 | RF.v | v | 43 | 48 | [] | [] | [] | [(1, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/111285134/src/RF.v:17: Bit extraction of array[31:0] requires 5 bit index, not 6 bits.\n : ... In instance RF\n data[i]=32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111285134/src/RF.v:37: Bit extraction of array[31:0] requires 5 bit index, not 6 bits.\n : ... In instance RF\n $display("%h",data[i]);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 3,111 | module | module RF(A1, A2, A3, WD, RFWr, clk, RD1, RD2);
input [4:0]A1;
input [4:0]A2;
input [4:0]A3;
input [31:0]WD;
input RFWr;
input clk;
output reg [31:0]RD1;
output reg [31:0]RD2;
reg[5:0] i;
reg [31:0] data[31:0];
initial
begin
for (i=0;i<32;i=i+1)
data[i]=32'b0;
end
always @(A1 or A2 or data[RD1] or data[RD2])
begin
RD1<=data[A1];
RD2<=data[A2];
end
always @(negedge clk)
begin
if ((RFWr) && (A3!=5'b11111))
data[A3]<=WD;
if ((RFWr) && (A3==5'b11111))
data[A3]<=WD+4;
for (i=0;i<32;i=i+1)
begin
$display("RegNum : %d",i);
$display("%h",data[i]);
end
$display("---Run---");
end
endmodule | module RF(A1, A2, A3, WD, RFWr, clk, RD1, RD2); |
input [4:0]A1;
input [4:0]A2;
input [4:0]A3;
input [31:0]WD;
input RFWr;
input clk;
output reg [31:0]RD1;
output reg [31:0]RD2;
reg[5:0] i;
reg [31:0] data[31:0];
initial
begin
for (i=0;i<32;i=i+1)
data[i]=32'b0;
end
always @(A1 or A2 or data[RD1] or data[RD2])
begin
RD1<=data[A1];
RD2<=data[A2];
end
always @(negedge clk)
begin
if ((RFWr) && (A3!=5'b11111))
data[A3]<=WD;
if ((RFWr) && (A3==5'b11111))
data[A3]<=WD+4;
for (i=0;i<32;i=i+1)
begin
$display("RegNum : %d",i);
$display("%h",data[i]);
end
$display("---Run---");
end
endmodule | 1 |
4,704 | data/full_repos/permissive/111393021/bs_adder.v | 111,393,021 | bs_adder.v | v | 38 | 461 | [] | [] | [] | [(17, 37)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/111393021/bs_adder.v:33: Signal definition not found, creating implicitly: \'cout_int\'\n cin_int <= cout_int;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111393021/bs_adder.v:23: Cannot find file containing module: \'fa\'\n fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));\n ^~\n ... Looked in:\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa.v\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa.sv\n fa\n fa.v\n fa.sv\n obj_dir/fa\n obj_dir/fa.v\n obj_dir/fa.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 3,122 | module | module bs_adder(x, y, clk, z, rst);
input x, y, clk, rst;
output reg z;
reg cin_int;
wire sum_int;
fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
always @ (posedge clk)
begin
if(rst)
begin
cin_int <= 1'b0;
z <= 1'b0;
end
else
begin
cin_int <= cout_int;
z <= sum_int;
end
end
endmodule | module bs_adder(x, y, clk, z, rst); |
input x, y, clk, rst;
output reg z;
reg cin_int;
wire sum_int;
fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
always @ (posedge clk)
begin
if(rst)
begin
cin_int <= 1'b0;
z <= 1'b0;
end
else
begin
cin_int <= cout_int;
z <= sum_int;
end
end
endmodule | 102 |
4,706 | data/full_repos/permissive/111393021/bs_mult_slice.v | 111,393,021 | bs_mult_slice.v | v | 59 | 461 | [] | [] | [] | [(15, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/111393021/bs_mult_slice.v:30: Cannot find file containing module: 'counter_5to3'\n counter_5to3 I0(.x({a, b, pin_delay, cin, cout1_delay}), .y(cout_int)); \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/counter_5to3\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/counter_5to3.v\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/counter_5to3.sv\n counter_5to3\n counter_5to3.v\n counter_5to3.sv\n obj_dir/counter_5to3\n obj_dir/counter_5to3.v\n obj_dir/counter_5to3.sv\n%Error: Exiting due to 1 error(s)\n" | 3,124 | module | module bs_mult_slice(clk, xy, pin, cin, rin, x, y, pout, cout, rout, lastbit);
input clk;
input xy, pin, cin, rin, x, y, lastbit;
output pout, cout, rout;
wire [2:0] cout_int;
reg cout;
reg rout;
wire a, b;
reg pin_delay;
reg x_delay;
reg y_delay;
reg cout1_delay;
assign a = x_delay & y;
assign b = x & y_delay;
assign pout = (rin == 1'b1) ? xy : cout_int[0];
counter_5to3 I0(.x({a, b, pin_delay, cin, cout1_delay}), .y(cout_int));
always @ (posedge clk)
begin
if(lastbit)
begin
x_delay <= 1'b0;
y_delay <= 1'b0;
pin_delay <= 1'b0;
cout1_delay <= 1'b0;
cout <= 1'b0;
rout <= 1'b0;
end
else
begin
if(rin)
begin
x_delay <= x;
y_delay <= y;
end
pin_delay <= pin;
cout1_delay <= cout_int[1];
cout <= cout_int[2];
rout <= rin;
end
end
endmodule | module bs_mult_slice(clk, xy, pin, cin, rin, x, y, pout, cout, rout, lastbit); |
input clk;
input xy, pin, cin, rin, x, y, lastbit;
output pout, cout, rout;
wire [2:0] cout_int;
reg cout;
reg rout;
wire a, b;
reg pin_delay;
reg x_delay;
reg y_delay;
reg cout1_delay;
assign a = x_delay & y;
assign b = x & y_delay;
assign pout = (rin == 1'b1) ? xy : cout_int[0];
counter_5to3 I0(.x({a, b, pin_delay, cin, cout1_delay}), .y(cout_int));
always @ (posedge clk)
begin
if(lastbit)
begin
x_delay <= 1'b0;
y_delay <= 1'b0;
pin_delay <= 1'b0;
cout1_delay <= 1'b0;
cout <= 1'b0;
rout <= 1'b0;
end
else
begin
if(rin)
begin
x_delay <= x;
y_delay <= y;
end
pin_delay <= pin;
cout1_delay <= cout_int[1];
cout <= cout_int[2];
rout <= rin;
end
end
endmodule | 102 |
4,707 | data/full_repos/permissive/111393021/CLA.v | 111,393,021 | CLA.v | v | 21 | 461 | [] | [] | [] | [(17, 20)] | null | null | 1: b"%Error: data/full_repos/permissive/111393021/CLA.v:17: Input/output/inout declaration not found for port: 'clk_ram'\nmodule CLA(clk_ram, clk_core, ram_iobus);\n ^~~~~~~\n%Error: data/full_repos/permissive/111393021/CLA.v:17: Input/output/inout declaration not found for port: 'clk_core'\nmodule CLA(clk_ram, clk_core, ram_iobus);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 3,125 | module | module CLA(clk_ram, clk_core, ram_iobus);
input [31:0] ram_iobus;
endmodule | module CLA(clk_ram, clk_core, ram_iobus); |
input [31:0] ram_iobus;
endmodule | 102 |
4,709 | data/full_repos/permissive/111393021/counter_5to3.v | 111,393,021 | counter_5to3.v | v | 51 | 461 | [] | [] | [] | [(15, 50)] | null | data/verilator_xmls/447a92c8-3f9b-4454-8ba8-4c341dc90c78.xml | null | 3,127 | module | module counter_5to3(x, y);
input [4:0] x;
output [2:0] y;
assign y[2:0] = (x[4:0] == 5'b00000) ? 3'b000 :
( x[4:0] == 5'b00001) ? 3'b001 :
( x[4:0] == 5'b00010) ? 3'b001 :
( x[4:0] == 5'b00100) ? 3'b001 :
( x[4:0] == 5'b01000) ? 3'b001 :
( x[4:0] == 5'b10000) ? 3'b001 :
( x[4:0] == 5'b00011) ? 3'b010 :
( x[4:0] == 5'b00110) ? 3'b010 :
( x[4:0] == 5'b01100) ? 3'b010 :
( x[4:0] == 5'b11000) ? 3'b010 :
( x[4:0] == 5'b00101) ? 3'b010 :
( x[4:0] == 5'b01010) ? 3'b010 :
( x[4:0] == 5'b10100) ? 3'b010 :
( x[4:0] == 5'b01001) ? 3'b010 :
( x[4:0] == 5'b10010) ? 3'b010 :
( x[4:0] == 5'b10001) ? 3'b010 :
( x[4:0] == 5'b11100) ? 3'b011 :
( x[4:0] == 5'b11001) ? 3'b011 :
( x[4:0] == 5'b10011) ? 3'b011 :
( x[4:0] == 5'b00111) ? 3'b011 :
( x[4:0] == 5'b11010) ? 3'b011 :
( x[4:0] == 5'b10101) ? 3'b011 :
( x[4:0] == 5'b01011) ? 3'b011 :
( x[4:0] == 5'b10110) ? 3'b011 :
( x[4:0] == 5'b01101) ? 3'b011 :
( x[4:0] == 5'b01110) ? 3'b011 :
( x[4:0] == 5'b01111) ? 3'b100 :
( x[4:0] == 5'b10111) ? 3'b100 :
( x[4:0] == 5'b11011) ? 3'b100 :
( x[4:0] == 5'b11101) ? 3'b100 :
( x[4:0] == 5'b11110) ? 3'b100 :
( x[4:0] == 5'b11111) ? 3'b101 : 3'b111;
endmodule | module counter_5to3(x, y); |
input [4:0] x;
output [2:0] y;
assign y[2:0] = (x[4:0] == 5'b00000) ? 3'b000 :
( x[4:0] == 5'b00001) ? 3'b001 :
( x[4:0] == 5'b00010) ? 3'b001 :
( x[4:0] == 5'b00100) ? 3'b001 :
( x[4:0] == 5'b01000) ? 3'b001 :
( x[4:0] == 5'b10000) ? 3'b001 :
( x[4:0] == 5'b00011) ? 3'b010 :
( x[4:0] == 5'b00110) ? 3'b010 :
( x[4:0] == 5'b01100) ? 3'b010 :
( x[4:0] == 5'b11000) ? 3'b010 :
( x[4:0] == 5'b00101) ? 3'b010 :
( x[4:0] == 5'b01010) ? 3'b010 :
( x[4:0] == 5'b10100) ? 3'b010 :
( x[4:0] == 5'b01001) ? 3'b010 :
( x[4:0] == 5'b10010) ? 3'b010 :
( x[4:0] == 5'b10001) ? 3'b010 :
( x[4:0] == 5'b11100) ? 3'b011 :
( x[4:0] == 5'b11001) ? 3'b011 :
( x[4:0] == 5'b10011) ? 3'b011 :
( x[4:0] == 5'b00111) ? 3'b011 :
( x[4:0] == 5'b11010) ? 3'b011 :
( x[4:0] == 5'b10101) ? 3'b011 :
( x[4:0] == 5'b01011) ? 3'b011 :
( x[4:0] == 5'b10110) ? 3'b011 :
( x[4:0] == 5'b01101) ? 3'b011 :
( x[4:0] == 5'b01110) ? 3'b011 :
( x[4:0] == 5'b01111) ? 3'b100 :
( x[4:0] == 5'b10111) ? 3'b100 :
( x[4:0] == 5'b11011) ? 3'b100 :
( x[4:0] == 5'b11101) ? 3'b100 :
( x[4:0] == 5'b11110) ? 3'b100 :
( x[4:0] == 5'b11111) ? 3'b101 : 3'b111;
endmodule | 102 |
4,712 | data/full_repos/permissive/111393021/fa.v | 111,393,021 | fa.v | v | 24 | 461 | [] | [] | [] | [(15, 23)] | null | null | 1: b"%Error: data/full_repos/permissive/111393021/fa.v:20: Cannot find file containing module: 'ha'\n ha I0(.x(x), .y(y), .cout(cout_int), .sum(sum_int));\n ^~\n ... Looked in:\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/ha\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/ha.v\n data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/ha.sv\n ha\n ha.v\n ha.sv\n obj_dir/ha\n obj_dir/ha.v\n obj_dir/ha.sv\n%Error: data/full_repos/permissive/111393021/fa.v:21: Cannot find file containing module: 'ha'\n ha I1(.x(sum_int), .y(cin), .cout(cout_int2), .sum(sum));\n ^~\n%Error: Exiting due to 2 error(s)\n" | 3,129 | module | module fa(x, y, cin, cout, sum);
input x, y, cin;
output cout, sum;
wire cout_int, cout_int2;
wire sum_int;
ha I0(.x(x), .y(y), .cout(cout_int), .sum(sum_int));
ha I1(.x(sum_int), .y(cin), .cout(cout_int2), .sum(sum));
assign cout = cout_int | cout_int2;
endmodule | module fa(x, y, cin, cout, sum); |
input x, y, cin;
output cout, sum;
wire cout_int, cout_int2;
wire sum_int;
ha I0(.x(x), .y(y), .cout(cout_int), .sum(sum_int));
ha I1(.x(sum_int), .y(cin), .cout(cout_int2), .sum(sum));
assign cout = cout_int | cout_int2;
endmodule | 102 |
4,713 | data/full_repos/permissive/111393021/filter_spad.v | 111,393,021 | filter_spad.v | v | 38 | 461 | [] | [] | [] | [(16, 37)] | null | data/verilator_xmls/c5573243-23fe-4c30-8eb5-b09193cd20ed.xml | null | 3,130 | module | module filter_spad(clk, addr, we, data_port);
input clk;
input [7:0] addr;
input we;
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [223:0];
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule | module filter_spad(clk, addr, we, data_port); |
input clk;
input [7:0] addr;
input we;
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [223:0];
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule | 102 |
4,715 | data/full_repos/permissive/111393021/ifmap_spad.v | 111,393,021 | ifmap_spad.v | v | 37 | 461 | [] | [] | [] | [(15, 36)] | null | data/verilator_xmls/991f273f-7c45-41e1-bf57-16033f7cc4fb.xml | null | 3,133 | module | module ifmap_spad(clk, addr, we, data_port);
input clk;
input [3:0] addr;
input we;
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [11:0];
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule | module ifmap_spad(clk, addr, we, data_port); |
input clk;
input [3:0] addr;
input we;
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [11:0];
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule | 102 |
4,716 | data/full_repos/permissive/111393021/mult_pipe2.v | 111,393,021 | mult_pipe2.v | v | 47 | 461 | [] | [] | [] | [(15, 46)] | null | data/verilator_xmls/01c9553c-448c-42e4-878a-a647166acd01.xml | null | 3,134 | module | module mult_pipe2 #(
parameter SIZE = 16,
parameter LVL = 2
)
( a, b, clk, pdt) ;
input [SIZE-1 : 0] a;
input [SIZE-1 : 0] b;
input clk;
output wire [2*SIZE-1 : 0] pdt;
reg [SIZE-1 : 0] a_int, b_int;
reg [2*SIZE-1 : 0] pdt_int [LVL-1 : 0];
integer i;
assign pdt = pdt_int [LVL-1];
always @ (posedge clk)
begin
a_int <= a;
b_int <= b;
for(i=1; i <LVL ; i = i + 1)
pdt_int[i] <= pdt_int [i-1];
pdt_int[0] <= a_int * b_int;
end
endmodule | module mult_pipe2 #(
parameter SIZE = 16,
parameter LVL = 2
)
( a, b, clk, pdt) ; |
input [SIZE-1 : 0] a;
input [SIZE-1 : 0] b;
input clk;
output wire [2*SIZE-1 : 0] pdt;
reg [SIZE-1 : 0] a_int, b_int;
reg [2*SIZE-1 : 0] pdt_int [LVL-1 : 0];
integer i;
assign pdt = pdt_int [LVL-1];
always @ (posedge clk)
begin
a_int <= a;
b_int <= b;
for(i=1; i <LVL ; i = i + 1)
pdt_int[i] <= pdt_int [i-1];
pdt_int[0] <= a_int * b_int;
end
endmodule | 102 |
4,721 | data/full_repos/permissive/111393021/test/CLA_tb.v | 111,393,021 | CLA_tb.v | v | 216 | 131 | [] | [] | [] | null | line:89: before: "reset" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n always begin #(30/2) clk = ~clk; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:82: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("CLA.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:84: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:89: syntax error, unexpected \'@\'\n @(negedge clk) reset = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #(30*2); reset = 1\'b0; \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:91: syntax error, unexpected \'@\'\n @(negedge clk) gray_ready = 1\'b1; \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:111: syntax error, unexpected \'@\'\n @(negedge clk); \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:114: syntax error, unexpected \'@\'\n @(posedge clk) result_compare = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #(30*3); \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:122: Unsupported: wait statements\n wait( finish ) ;\n ^~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:123: syntax error, unexpected \'@\'\n @(posedge clk); @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10000000 ;\n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:175: syntax error, unexpected \'@\'\n @(posedge over) \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:192: syntax error, unexpected \'#\'\n #(30/2); $finish;\n ^\n%Error: Exiting due to 10 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,139 | module | module CLA_tb;
parameter N_EXP = 16384;
parameter N_PAT = N_EXP;
reg [7:0] gray_mem [0:N_PAT-1];
reg [7:0] exp_mem [0:N_EXP-1];
reg [7:0] ipf_dbg;
reg [7:0] exp_dbg;
wire [7:0] ipf_data;
reg clk = 0;
reg reset = 0;
reg [1:0] mode;
reg result_compare = 0;
integer err = 0;
integer times = 0;
reg over = 0;
integer exp_num = 0;
wire [13:0] gray_addr;
wire [13:0] ipf_addr;
reg [7:0] gray_data;
reg gray_ready = 0;
integer i;
CLA CLA( .clk(clk),
.reset(reset),
.mode(mode),
.gray_addr(gray_addr),
.gray_req(gray_req),
.gray_ready(gray_ready),
.gray_data(gray_data),
.ipf_addr(ipf_addr),
.ipf_valid(ipf_valid),
.ipf_data(ipf_data),
.finish(finish));
ipf_mem u_ipf_mem(.ipf_valid(ipf_valid), .ipf_data(ipf_data), .ipf_addr(ipf_addr), .clk(clk));
initial begin
$readmemh (`PAT, gray_mem);
end
initial begin
`ifdef MODE0
$readmemh (`EXP0, exp_mem);
`endif
`ifdef MODE1
$readmemh (`EXP1, exp_mem);
`endif
`ifdef MODE2
$readmemh (`EXP2, exp_mem);
`endif
end
always begin #(`CYCLE/2) clk = ~clk; end
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, CLA);
$fsdbDumpfile("CLA_syn.fsdb");
`else
$fsdbDumpfile("CLA.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
@(negedge clk) reset = 1'b1;
#(`CYCLE*2); reset = 1'b0;
@(negedge clk) gray_ready = 1'b1;
mode = 2'd0;
`ifdef MODE1
mode = 2'd1;
`endif
`ifdef MODE2
mode = 2'd2;
`endif
while (finish == 0) begin
if( gray_req ) begin
gray_data = gray_mem[gray_addr];
end
else begin
gray_data = 'hz;
end
@(negedge clk);
end
gray_ready = 0; gray_data='hz;
@(posedge clk) result_compare = 1;
end
initial begin
$display("-----------------------------------------------------\n");
$display("START!!! Simulation Start .....\n");
$display("-----------------------------------------------------\n");
#(`CYCLE*3);
wait( finish ) ;
@(posedge clk); @(posedge clk);
for (i=0; i <N_PAT ; i=i+1) begin
exp_dbg = exp_mem[i]; ipf_dbg = u_ipf_mem.ipf_M[i];
if (exp_mem[i] == u_ipf_mem.ipf_M[i]) begin
err = err;
end
else begin
err = err+1;
if (err <= 10) $display("Output pixel %d are wrong!", i);
if (err == 11) begin $display("Find the wrong pixel reached a total of more than 10 !, Please check the code .....\n"); end
end
if( ((i%1000) === 0) || (i == 16383))begin
if ( err === 0)
$display("Output pixel: 0 ~ %d are correct!\n", i);
else
$display("Output Pixel: 0 ~ %d are wrong ! The wrong pixel reached a total of %d or more ! \n", i, err);
end
exp_num = exp_num + 1;
end
over = 1;
end
initial begin
#`End_CYCLE ;
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
integer f;
reg check;
initial begin
`ifdef MODE0
f = $fopen("pattern0.txt","w");
`endif
`ifdef MODE1
f = $fopen("pattern1.txt","w");
`endif
`ifdef MODE2
f = $fopen("pattern2.txt","w");
`endif
@(posedge over)
if((over) && (exp_num!='d0)) begin
$display("-----------------------------------------------------\n");
if (err == 0) begin
$display("Congratulations! All data have been generated successfully!\n");
$display("-------------------------PASS------------------------\n");
check = 1;
$fwrite(f, "%d\n", check);
end
else begin
$display("There are %d errors!\n", err);
$display("-----------------------------------------------------\n");
check = 0;
$fwrite(f, "%d\n", check);
end
end
#(`CYCLE/2); $finish;
end
endmodule | module CLA_tb; |
parameter N_EXP = 16384;
parameter N_PAT = N_EXP;
reg [7:0] gray_mem [0:N_PAT-1];
reg [7:0] exp_mem [0:N_EXP-1];
reg [7:0] ipf_dbg;
reg [7:0] exp_dbg;
wire [7:0] ipf_data;
reg clk = 0;
reg reset = 0;
reg [1:0] mode;
reg result_compare = 0;
integer err = 0;
integer times = 0;
reg over = 0;
integer exp_num = 0;
wire [13:0] gray_addr;
wire [13:0] ipf_addr;
reg [7:0] gray_data;
reg gray_ready = 0;
integer i;
CLA CLA( .clk(clk),
.reset(reset),
.mode(mode),
.gray_addr(gray_addr),
.gray_req(gray_req),
.gray_ready(gray_ready),
.gray_data(gray_data),
.ipf_addr(ipf_addr),
.ipf_valid(ipf_valid),
.ipf_data(ipf_data),
.finish(finish));
ipf_mem u_ipf_mem(.ipf_valid(ipf_valid), .ipf_data(ipf_data), .ipf_addr(ipf_addr), .clk(clk));
initial begin
$readmemh (`PAT, gray_mem);
end
initial begin
`ifdef MODE0
$readmemh (`EXP0, exp_mem);
`endif
`ifdef MODE1
$readmemh (`EXP1, exp_mem);
`endif
`ifdef MODE2
$readmemh (`EXP2, exp_mem);
`endif
end
always begin #(`CYCLE/2) clk = ~clk; end
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, CLA);
$fsdbDumpfile("CLA_syn.fsdb");
`else
$fsdbDumpfile("CLA.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
@(negedge clk) reset = 1'b1;
#(`CYCLE*2); reset = 1'b0;
@(negedge clk) gray_ready = 1'b1;
mode = 2'd0;
`ifdef MODE1
mode = 2'd1;
`endif
`ifdef MODE2
mode = 2'd2;
`endif
while (finish == 0) begin
if( gray_req ) begin
gray_data = gray_mem[gray_addr];
end
else begin
gray_data = 'hz;
end
@(negedge clk);
end
gray_ready = 0; gray_data='hz;
@(posedge clk) result_compare = 1;
end
initial begin
$display("-----------------------------------------------------\n");
$display("START!!! Simulation Start .....\n");
$display("-----------------------------------------------------\n");
#(`CYCLE*3);
wait( finish ) ;
@(posedge clk); @(posedge clk);
for (i=0; i <N_PAT ; i=i+1) begin
exp_dbg = exp_mem[i]; ipf_dbg = u_ipf_mem.ipf_M[i];
if (exp_mem[i] == u_ipf_mem.ipf_M[i]) begin
err = err;
end
else begin
err = err+1;
if (err <= 10) $display("Output pixel %d are wrong!", i);
if (err == 11) begin $display("Find the wrong pixel reached a total of more than 10 !, Please check the code .....\n"); end
end
if( ((i%1000) === 0) || (i == 16383))begin
if ( err === 0)
$display("Output pixel: 0 ~ %d are correct!\n", i);
else
$display("Output Pixel: 0 ~ %d are wrong ! The wrong pixel reached a total of %d or more ! \n", i, err);
end
exp_num = exp_num + 1;
end
over = 1;
end
initial begin
#`End_CYCLE ;
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
integer f;
reg check;
initial begin
`ifdef MODE0
f = $fopen("pattern0.txt","w");
`endif
`ifdef MODE1
f = $fopen("pattern1.txt","w");
`endif
`ifdef MODE2
f = $fopen("pattern2.txt","w");
`endif
@(posedge over)
if((over) && (exp_num!='d0)) begin
$display("-----------------------------------------------------\n");
if (err == 0) begin
$display("Congratulations! All data have been generated successfully!\n");
$display("-------------------------PASS------------------------\n");
check = 1;
$fwrite(f, "%d\n", check);
end
else begin
$display("There are %d errors!\n", err);
$display("-----------------------------------------------------\n");
check = 0;
$fwrite(f, "%d\n", check);
end
end
#(`CYCLE/2); $finish;
end
endmodule | 102 |
4,722 | data/full_repos/permissive/111393021/test/CLA_tb.v | 111,393,021 | CLA_tb.v | v | 216 | 131 | [] | [] | [] | null | line:89: before: "reset" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n always begin #(30/2) clk = ~clk; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:82: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("CLA.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:84: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:89: syntax error, unexpected \'@\'\n @(negedge clk) reset = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #(30*2); reset = 1\'b0; \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:91: syntax error, unexpected \'@\'\n @(negedge clk) gray_ready = 1\'b1; \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:111: syntax error, unexpected \'@\'\n @(negedge clk); \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:114: syntax error, unexpected \'@\'\n @(posedge clk) result_compare = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #(30*3); \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:122: Unsupported: wait statements\n wait( finish ) ;\n ^~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:123: syntax error, unexpected \'@\'\n @(posedge clk); @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10000000 ;\n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:175: syntax error, unexpected \'@\'\n @(posedge over) \n ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:192: syntax error, unexpected \'#\'\n #(30/2); $finish;\n ^\n%Error: Exiting due to 10 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,139 | module | module ipf_mem (ipf_valid, ipf_data, ipf_addr, clk);
input ipf_valid;
input [13:0] ipf_addr;
input [7:0] ipf_data;
input clk;
reg [7:0] ipf_M [0:16383];
integer i;
initial begin
for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
end
always@(negedge clk)
if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;
endmodule | module ipf_mem (ipf_valid, ipf_data, ipf_addr, clk); |
input ipf_valid;
input [13:0] ipf_addr;
input [7:0] ipf_data;
input clk;
reg [7:0] ipf_M [0:16383];
integer i;
initial begin
for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
end
always@(negedge clk)
if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;
endmodule | 102 |
4,723 | data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v | 111,393,021 | dual_clock_fifo_tb.v | v | 126 | 77 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:23: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("dual_clock_fifo");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:24: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars;\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #11000 slow_clk <= ~slow_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #7000 fast_clk <= ~fast_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n initial #95000 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #95000 rst = 0;\n ^\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:96: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:102: Unsupported: fork statements\n fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #123 rst = 1\'b0;\n ^\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:112: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:118: Unsupported: fork statements\n fork\n ^~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,140 | module | module dual_clock_fifo_tb
#(parameter data_width = 16,
parameter depth_width = 8);
initial begin
$fsdbDumpfile("dual_clock_fifo");
$fsdbDumpvars;
end
localparam DEPTH = 1<<depth_width;
reg slow_clk = 1'b1;
reg fast_clk = 1'b1;
reg rst = 1'b1;
reg faster_write_clk = 1'b0;
wire wr_clk;
wire rd_clk;
always #11000 slow_clk <= ~slow_clk;
always #7000 fast_clk <= ~fast_clk;
initial #95000 rst <= 0;
assign wr_clk = faster_write_clk ? fast_clk : slow_clk;
assign rd_clk = faster_write_clk ? slow_clk : fast_clk;
wire [data_width-1:0] wr_data;
wire wr_en;
wire [data_width-1:0] rd_data;
wire rd_en;
wire full;
wire empty;
dual_clock_fifo
#(.ADDR_WIDTH (depth_width),
.DATA_WIDTH (data_width))
dut
(
.wr_clk_i (wr_clk),
.wr_rst_i (rst),
.wr_en_i (wr_en & !full),
.wr_data_i (wr_data),
.full_o (full),
.rd_clk_i (rd_clk),
.rd_rst_i (rst),
.rd_en_i (rd_en & !empty),
.rd_data_o (rd_data),
.empty_o (empty));
fifo_tester
#(.DEPTH (DEPTH),
.DW (data_width))
tester
(.rst_i (rst),
.wr_clk_i (wr_clk),
.wr_en_o (wr_en),
.wr_data_o (wr_data),
.full_i (full),
.rd_clk_i (rd_clk),
.rd_en_o (rd_en),
.rd_data_i (rd_data),
.empty_i (empty));
integer transactions = 10000;
integer errors;
initial begin
if($value$plusargs("transactions=%d", transactions)) begin
$display("Setting number of transactions to %0d", transactions);
end
#95000 rst = 0;
$display("Testing slow write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.9);
tester.fifo_verify(transactions, 0.1, errors);
join
$display("Testing slow write clock, slow write rate");
fork
tester.fifo_write(transactions , 0.1);
tester.fifo_verify(transactions, 0.9, errors);
join
rst = 1'b1;
faster_write_clk = 1;
#123 rst = 1'b0;
$display("Testing fast write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.9);
tester.fifo_verify(transactions, 0.1, errors);
join
$display("Testing fast write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.1);
tester.fifo_verify(transactions, 0.9, errors);
join
$finish;
end
endmodule | module dual_clock_fifo_tb
#(parameter data_width = 16,
parameter depth_width = 8); |
initial begin
$fsdbDumpfile("dual_clock_fifo");
$fsdbDumpvars;
end
localparam DEPTH = 1<<depth_width;
reg slow_clk = 1'b1;
reg fast_clk = 1'b1;
reg rst = 1'b1;
reg faster_write_clk = 1'b0;
wire wr_clk;
wire rd_clk;
always #11000 slow_clk <= ~slow_clk;
always #7000 fast_clk <= ~fast_clk;
initial #95000 rst <= 0;
assign wr_clk = faster_write_clk ? fast_clk : slow_clk;
assign rd_clk = faster_write_clk ? slow_clk : fast_clk;
wire [data_width-1:0] wr_data;
wire wr_en;
wire [data_width-1:0] rd_data;
wire rd_en;
wire full;
wire empty;
dual_clock_fifo
#(.ADDR_WIDTH (depth_width),
.DATA_WIDTH (data_width))
dut
(
.wr_clk_i (wr_clk),
.wr_rst_i (rst),
.wr_en_i (wr_en & !full),
.wr_data_i (wr_data),
.full_o (full),
.rd_clk_i (rd_clk),
.rd_rst_i (rst),
.rd_en_i (rd_en & !empty),
.rd_data_o (rd_data),
.empty_o (empty));
fifo_tester
#(.DEPTH (DEPTH),
.DW (data_width))
tester
(.rst_i (rst),
.wr_clk_i (wr_clk),
.wr_en_o (wr_en),
.wr_data_o (wr_data),
.full_i (full),
.rd_clk_i (rd_clk),
.rd_en_o (rd_en),
.rd_data_i (rd_data),
.empty_i (empty));
integer transactions = 10000;
integer errors;
initial begin
if($value$plusargs("transactions=%d", transactions)) begin
$display("Setting number of transactions to %0d", transactions);
end
#95000 rst = 0;
$display("Testing slow write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.9);
tester.fifo_verify(transactions, 0.1, errors);
join
$display("Testing slow write clock, slow write rate");
fork
tester.fifo_write(transactions , 0.1);
tester.fifo_verify(transactions, 0.9, errors);
join
rst = 1'b1;
faster_write_clk = 1;
#123 rst = 1'b0;
$display("Testing fast write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.9);
tester.fifo_verify(transactions, 0.1, errors);
join
$display("Testing fast write clock, fast write rate");
fork
tester.fifo_write(transactions , 0.1);
tester.fifo_verify(transactions, 0.9, errors);
join
$finish;
end
endmodule | 102 |
4,724 | data/full_repos/permissive/111393021/test/fifo_reader.v | 111,393,021 | fifo_reader.v | v | 68 | 77 | [] | [] | [] | null | line:25: before: "=" | null | 1: b"%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:39: Unsupported or unknown PLI call: $dist_uniform\n randval = $dist_uniform(seed, 0, 1000) / 1000.0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:52: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:63: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: Exiting due to 3 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 3,141 | module | module fifo_reader
#(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024)
(
input clk,
input [WIDTH-1:0] din,
output reg rden = 1'b0,
input empty);
real rate = 0.5;
integer seed = 0;
time timeout = 0;
reg err_timeout = 0;
reg valid = 1'b0;
real randval;
always @(posedge clk) begin
valid <= rden & !empty;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
rden <= (randval <= rate) & !empty;
end
task read_word;
output [WIDTH-1:0] data_o;
reg rd;
time t0;
begin
t0 = $time;
while(!valid & !err_timeout) begin
@(posedge clk);
if(timeout > 0)
err_timeout = ($time-t0) > timeout;
end
if(err_timeout) begin
$display("%0d : Timeout in FIFO reader", $time);
$finish;
end
data_o = din;
err_timeout = 1'b0;
@(posedge clk);
end
endtask
endmodule | module fifo_reader
#(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024)
(
input clk,
input [WIDTH-1:0] din,
output reg rden = 1'b0,
input empty); |
real rate = 0.5;
integer seed = 0;
time timeout = 0;
reg err_timeout = 0;
reg valid = 1'b0;
real randval;
always @(posedge clk) begin
valid <= rden & !empty;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
rden <= (randval <= rate) & !empty;
end
task read_word;
output [WIDTH-1:0] data_o;
reg rd;
time t0;
begin
t0 = $time;
while(!valid & !err_timeout) begin
@(posedge clk);
if(timeout > 0)
err_timeout = ($time-t0) > timeout;
end
if(err_timeout) begin
$display("%0d : Timeout in FIFO reader", $time);
$finish;
end
data_o = din;
err_timeout = 1'b0;
@(posedge clk);
end
endtask
endmodule | 102 |
4,725 | data/full_repos/permissive/111393021/test/fifo_tester.v | 111,393,021 | fifo_tester.v | v | 125 | 94 | [] | [] | [] | null | line:33: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/111393021/test/fifo_tester.v:78: syntax error, unexpected '@'\n @(posedge wr_clk_i);\n ^\n%Error: data/full_repos/permissive/111393021/test/fifo_tester.v:108: syntax error, unexpected '@'\n @(posedge rd_clk_i);\n ^\n%Error: Exiting due to 2 error(s)\n" | 3,142 | module | module fifo_tester
#(parameter DEPTH = 0,
parameter DW = 0)
(input wire rst_i,
input wire wr_clk_i,
output wire wr_en_o,
output wire [DW-1:0] wr_data_o,
input wire full_i,
input wire rd_clk_i,
output wire rd_en_o,
input wire [DW-1:0] rd_data_i,
input wire empty_i);
function [DW-1:0] randvec;
input integer seed;
integer idx;
for (idx = DW ; idx>0 ; idx=idx-32)
randvec = (randvec << 32)| $random();
endfunction
reg [DW-1:0] mem [0:DEPTH-1];
integer seed = 10;
fifo_writer
#(.WIDTH (DW))
writer
(.clk (wr_clk_i),
.dout (wr_data_o),
.wren (wr_en_o),
.full (full_i));
fifo_reader
#(.WIDTH (DW))
reader
(.clk (rd_clk_i),
.din (rd_data_i),
.rden (rd_en_o),
.empty (empty_i));
task fifo_write;
input integer transactions_i;
input real write_rate;
integer index;
integer tmp;
reg [DW-1:0] data;
integer dw_idx;
begin
if(write_rate > 1.0) write_rate = 1.0;
if(write_rate < 0.0) write_rate = 0.0;
writer.rate = write_rate;
index = 0;
@(posedge wr_clk_i);
while(index < transactions_i) begin
data = randvec(seed);
mem[index % DEPTH] = data;
writer.write_word(data);
index = index + 1;
end
end
endtask
task fifo_verify;
input integer transactions_i;
input real read_rate;
output integer errors;
integer index ;
reg [DW-1:0] received;
reg [DW-1:0] expected;
begin
errors = 0;
if(read_rate > 1.0) read_rate = 1.0;
if(read_rate < 0.0) read_rate = 0.0;
reader.rate = read_rate;
index = 0;
@(posedge rd_clk_i);
while (index < transactions_i) begin
reader.read_word(received);
expected = mem[index % DEPTH];
if(expected !==
received) begin
$display("Error at index %0d. Expected 0x%4x, got 0x%4x", index, expected, received);
errors = errors + 1;
end
index = index + 1;
end
end
endtask
endmodule | module fifo_tester
#(parameter DEPTH = 0,
parameter DW = 0)
(input wire rst_i,
input wire wr_clk_i,
output wire wr_en_o,
output wire [DW-1:0] wr_data_o,
input wire full_i,
input wire rd_clk_i,
output wire rd_en_o,
input wire [DW-1:0] rd_data_i,
input wire empty_i); |
function [DW-1:0] randvec;
input integer seed;
integer idx;
for (idx = DW ; idx>0 ; idx=idx-32)
randvec = (randvec << 32)| $random();
endfunction
reg [DW-1:0] mem [0:DEPTH-1];
integer seed = 10;
fifo_writer
#(.WIDTH (DW))
writer
(.clk (wr_clk_i),
.dout (wr_data_o),
.wren (wr_en_o),
.full (full_i));
fifo_reader
#(.WIDTH (DW))
reader
(.clk (rd_clk_i),
.din (rd_data_i),
.rden (rd_en_o),
.empty (empty_i));
task fifo_write;
input integer transactions_i;
input real write_rate;
integer index;
integer tmp;
reg [DW-1:0] data;
integer dw_idx;
begin
if(write_rate > 1.0) write_rate = 1.0;
if(write_rate < 0.0) write_rate = 0.0;
writer.rate = write_rate;
index = 0;
@(posedge wr_clk_i);
while(index < transactions_i) begin
data = randvec(seed);
mem[index % DEPTH] = data;
writer.write_word(data);
index = index + 1;
end
end
endtask
task fifo_verify;
input integer transactions_i;
input real read_rate;
output integer errors;
integer index ;
reg [DW-1:0] received;
reg [DW-1:0] expected;
begin
errors = 0;
if(read_rate > 1.0) read_rate = 1.0;
if(read_rate < 0.0) read_rate = 0.0;
reader.rate = read_rate;
index = 0;
@(posedge rd_clk_i);
while (index < transactions_i) begin
reader.read_word(received);
expected = mem[index % DEPTH];
if(expected !==
received) begin
$display("Error at index %0d. Expected 0x%4x, got 0x%4x", index, expected, received);
errors = errors + 1;
end
index = index + 1;
end
end
endtask
endmodule | 102 |
4,726 | data/full_repos/permissive/111393021/test/fifo_tester.v | 111,393,021 | fifo_tester.v | v | 125 | 94 | [] | [] | [] | null | line:33: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/111393021/test/fifo_tester.v:78: syntax error, unexpected '@'\n @(posedge wr_clk_i);\n ^\n%Error: data/full_repos/permissive/111393021/test/fifo_tester.v:108: syntax error, unexpected '@'\n @(posedge rd_clk_i);\n ^\n%Error: Exiting due to 2 error(s)\n" | 3,142 | function | function [DW-1:0] randvec;
input integer seed;
integer idx;
for (idx = DW ; idx>0 ; idx=idx-32)
randvec = (randvec << 32)| $random();
endfunction | function [DW-1:0] randvec; |
input integer seed;
integer idx;
for (idx = DW ; idx>0 ; idx=idx-32)
randvec = (randvec << 32)| $random();
endfunction | 102 |
4,727 | data/full_repos/permissive/111393021/test/fifo_writer.v | 111,393,021 | fifo_writer.v | v | 70 | 54 | [] | [] | [] | null | line:8: before: "=" | null | 1: b"%Error: data/full_repos/permissive/111393021/test/fifo_writer.v:26: Unsupported or unknown PLI call: $dist_uniform\n randval = $dist_uniform(seed, 0, 1000) / 1000.0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/fifo_writer.v:32: Unsupported or unknown PLI call: $dist_uniform\n randval = $dist_uniform(seed, 0, 1000) / 1000.0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/fifo_writer.v:34: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/111393021/test/fifo_writer.v:40: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: Exiting due to 4 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 3,143 | module | module fifo_writer
#(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024)
(
input clk,
output reg [WIDTH-1:0] dout,
output reg wren = 1'b0,
input full);
real rate = 0.5;
integer seed = 0;
initial begin
rate = 0.5;
end
task write_word;
input [WIDTH-1:0] word_i;
reg wr;
real randval;
begin
wren = 1'b0;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
dout <= word_i;
while(!wr) begin
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
@(posedge clk);
end
wren <= 1'b1;
wr = 1'b0;
while(!wr) begin
@(posedge clk);
wr = !full;
end
wren <= 1'b0;
end
endtask
task write_block;
input [WIDTH*MAX_BLOCK_SIZE-1:0] data_i;
input integer length_i;
integer index;
begin
if(rate > 1.0) rate = 1.0;
if(rate < 0.0) rate = 0.0;
index = 0;
while(index < length_i) begin
write_word(data_i[index*WIDTH+:WIDTH]);
index = index + 1;
end
end
endtask
endmodule | module fifo_writer
#(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024)
(
input clk,
output reg [WIDTH-1:0] dout,
output reg wren = 1'b0,
input full); |
real rate = 0.5;
integer seed = 0;
initial begin
rate = 0.5;
end
task write_word;
input [WIDTH-1:0] word_i;
reg wr;
real randval;
begin
wren = 1'b0;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
dout <= word_i;
while(!wr) begin
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
@(posedge clk);
end
wren <= 1'b1;
wr = 1'b0;
while(!wr) begin
@(posedge clk);
wr = !full;
end
wren <= 1'b0;
end
endtask
task write_block;
input [WIDTH*MAX_BLOCK_SIZE-1:0] data_i;
input integer length_i;
integer index;
begin
if(rate > 1.0) rate = 1.0;
if(rate < 0.0) rate = 0.0;
index = 0;
while(index < length_i) begin
write_word(data_i[index*WIDTH+:WIDTH]);
index = index + 1;
end
end
endtask
endmodule | 102 |
4,732 | data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v | 111,433,415 | descripciones.v | v | 188 | 81 | [] | [] | [] | null | line:142: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:126: Unsupported: Ignoring delay on this delayed statement.\n #10 a = ~a;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:128: Unsupported: Ignoring delay on this delayed statement.\n #20 b = ~b;\n ^\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:134: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("descripciones.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:135: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, descripciones);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:143: Unsupported or unknown PLI call: $timeformat\n $timeformat(-9, 0, "ns", 5);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:145: Unsupported or unknown PLI call: $monitor\n $monitor("%t\\t%b\\t%b\\t%b\\t%b\\t%b", $stime, a, b, f_func, f_proc, f_est);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,149 | module | module descripciones ();
reg a = 0, b = 0;
wire f_func = a & ~b | ~a & b;
reg f_proc;
always @(a, b)
begin
if (a == 0)
f_proc = b;
else
f_proc = ~b;
end
wire f_est;
wire not_a, not_b, and1_out, and2_out;
not not1 (not_a, a);
not not2 (not_b, b);
and and1 (and1_out, a, not_b);
and and2 (and2_out, not_a, b);
or or1 (f_est, and1_out, and2_out);
always
#10 a = ~a;
always
#20 b = ~b;
initial
begin
$dumpfile("descripciones.vcd");
$dumpvars(0, descripciones);
$timeformat(-9, 0, "ns", 5);
$display("t\ta\tb\tf_func\tf_proc\tf_est");
$monitor("%t\t%b\t%b\t%b\t%b\t%b", $stime, a, b, f_func, f_proc, f_est);
#100 $finish;
end
endmodule | module descripciones (); |
reg a = 0, b = 0;
wire f_func = a & ~b | ~a & b;
reg f_proc;
always @(a, b)
begin
if (a == 0)
f_proc = b;
else
f_proc = ~b;
end
wire f_est;
wire not_a, not_b, and1_out, and2_out;
not not1 (not_a, a);
not not2 (not_b, b);
and and1 (and1_out, a, not_b);
and and2 (and2_out, not_a, b);
or or1 (f_est, and1_out, and2_out);
always
#10 a = ~a;
always
#20 b = ~b;
initial
begin
$dumpfile("descripciones.vcd");
$dumpvars(0, descripciones);
$timeformat(-9, 0, "ns", 5);
$display("t\ta\tb\tf_func\tf_proc\tf_est");
$monitor("%t\t%b\t%b\t%b\t%b\t%b", $stime, a, b, f_func, f_proc, f_est);
#100 $finish;
end
endmodule | 10 |
4,733 | data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador.v | 111,433,415 | votador.v | v | 99 | 81 | [] | [] | [] | [(67, 88)] | null | data/verilator_xmls/78509003-d249-4c49-a2a7-b6ec2290711b.xml | null | 3,150 | module | module votador (
output reg v,
input wire a,
input wire b,
input wire c
);
always @(a, b, c)
case(a)
1:
v = b | c;
default:
v = b & c;
endcase
endmodule | module votador (
output reg v,
input wire a,
input wire b,
input wire c
); |
always @(a, b, c)
case(a)
1:
v = b | c;
default:
v = b & c;
endcase
endmodule | 10 |
4,734 | data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v | 111,433,415 | votador_tb.v | v | 107 | 79 | [] | [] | [] | null | line:62: before: "$" | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("votador_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #5 a = ~a;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10 b = ~b;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #20 c = ~c;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,151 | module | module test ();
reg a, b, c;
wire v;
votador uut (.v(v), .a(a), .b(b), .c(c));
initial begin
a = 0;
b = 0;
c = 0;
$dumpfile("votador_tb.vcd");
$dumpvars(0, test);
#100 $finish;
end
always
#5 a = ~a;
always
#10 b = ~b;
always
#20 c = ~c;
endmodule | module test (); |
reg a, b, c;
wire v;
votador uut (.v(v), .a(a), .b(b), .c(c));
initial begin
a = 0;
b = 0;
c = 0;
$dumpfile("votador_tb.vcd");
$dumpvars(0, test);
#100 $finish;
end
always
#5 a = ~a;
always
#10 b = ~b;
always
#20 c = ~c;
endmodule | 10 |
4,735 | data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v | 111,433,415 | votador-f_tb.v | v | 95 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:46: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("votador-f_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:47: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test2);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 a = ~a;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10 b = ~b;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #20 c = ~c;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,153 | module | module test2 ();
reg a, b, c;
wire v, v_f;
votador uut (.v(v), .a(a), .b(b), .c(c));
votador_f uutf (.v(v_f), .a(a), .b(b), .c(c));
initial begin
a = 0;
b = 0;
c = 0;
$dumpfile("votador-f_tb.vcd");
$dumpvars(0, test2);
#100 $finish;
end
always
#5 a = ~a;
always
#10 b = ~b;
always
#20 c = ~c;
endmodule | module test2 (); |
reg a, b, c;
wire v, v_f;
votador uut (.v(v), .a(a), .b(b), .c(c));
votador_f uutf (.v(v_f), .a(a), .b(b), .c(c));
initial begin
a = 0;
b = 0;
c = 0;
$dumpfile("votador-f_tb.vcd");
$dumpvars(0, test2);
#100 $finish;
end
always
#5 a = ~a;
always
#10 b = ~b;
always
#20 c = ~c;
endmodule | 10 |
4,737 | data/full_repos/permissive/111433415/verilog/03_combinacionales/03-1_florencio/florencio.v | 111,433,415 | florencio.v | v | 142 | 80 | [] | [] | [] | [(28, 53)] | null | data/verilator_xmls/132d4b06-1559-4b27-99c9-8cde0894c082.xml | null | 3,155 | module | module florencio (
output reg f,
input wire a,
input wire b,
input wire c,
input wire d
);
always @(a, b, c, d)
begin
f = 1;
if (a && b && c && d)
f = 0;
if (!a && !b && !c && !d)
f = 0;
if (b && !c)
f = 0;
if (a && c)
if (!b && !d)
f = 0;
if ((c || d || !a) && !b)
f = 0;
end
endmodule | module florencio (
output reg f,
input wire a,
input wire b,
input wire c,
input wire d
); |
always @(a, b, c, d)
begin
f = 1;
if (a && b && c && d)
f = 0;
if (!a && !b && !c && !d)
f = 0;
if (b && !c)
f = 0;
if (a && c)
if (!b && !d)
f = 0;
if ((c || d || !a) && !b)
f = 0;
end
endmodule | 10 |
4,738 | data/full_repos/permissive/111433415/verilog/03_combinacionales/03-1_florencio/florencio.v | 111,433,415 | florencio.v | v | 142 | 80 | [] | [] | [] | [(28, 53)] | null | data/verilator_xmls/132d4b06-1559-4b27-99c9-8cde0894c082.xml | null | 3,155 | module | module test ();
reg a = 0, b = 0, c = 0, d = 0;
wire f;
florencio uut(f, a, b, c, d);
initial begin
$display("d c b a | f");
$monitor("%b %b %b %b | %b", d, c, b, a, f);
#(16 * `BTIME) $finish;
end
always
#(`BTIME) a = ~a;
always
#(2 * `BTIME) b = ~b;
always
#(4 * `BTIME) c = ~c;
always
#(8 * `BTIME) d = ~d;
endmodule | module test (); |
reg a = 0, b = 0, c = 0, d = 0;
wire f;
florencio uut(f, a, b, c, d);
initial begin
$display("d c b a | f");
$monitor("%b %b %b %b | %b", d, c, b, a, f);
#(16 * `BTIME) $finish;
end
always
#(`BTIME) a = ~a;
always
#(2 * `BTIME) b = ~b;
always
#(4 * `BTIME) c = ~c;
always
#(8 * `BTIME) d = ~d;
endmodule | 10 |
4,739 | data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v | 111,433,415 | azar.v | v | 107 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v:65: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hazard_f\'\nmodule hazard_f (\n ^~~~~~~~\n : ... Top module \'hazard_e\'\nmodule hazard_e #(\n ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 3,156 | module | module hazard_f (
input wire a,
input wire b,
output wire f
);
assign f = ~a & b | a & b;
endmodule | module hazard_f (
input wire a,
input wire b,
output wire f
); |
assign f = ~a & b | a & b;
endmodule | 10 |
4,740 | data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v | 111,433,415 | azar.v | v | 107 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v:65: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hazard_f\'\nmodule hazard_f (\n ^~~~~~~~\n : ... Top module \'hazard_e\'\nmodule hazard_e #(\n ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 3,156 | module | module hazard_e #(
parameter delay = 5
)(
input wire a,
input wire b,
output wire f
);
wire x, y, z;
not #delay inv(x, a);
and #delay and1(y, a, b);
and #delay and2(z, x, b);
or #delay or1(f, y, z);
endmodule | module hazard_e #(
parameter delay = 5
)(
input wire a,
input wire b,
output wire f
); |
wire x, y, z;
not #delay inv(x, a);
and #delay and1(y, a, b);
and #delay and2(z, x, b);
or #delay or1(f, y, z);
endmodule | 10 |
4,743 | data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v | 111,433,415 | alarma_tb.v | v | 115 | 77 | [] | [] | [] | null | line:73: before: "$" | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:66: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("alarma_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:67: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #(64*10) $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #(10) x = x + 1;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,159 | module | module test ();
reg [5:0] x;
wire a;
alarma uut (x[5], x[4], x[3], x[2], x[1], x[0], a);
initial begin
x = 6'b000000;
$dumpfile("alarma_tb.vcd");
$dumpvars(0,test);
#(64*`BTIME) $finish;
end
always
#(`BTIME) x = x + 1;
endmodule | module test (); |
reg [5:0] x;
wire a;
alarma uut (x[5], x[4], x[3], x[2], x[1], x[0], a);
initial begin
x = 6'b000000;
$dumpfile("alarma_tb.vcd");
$dumpvars(0,test);
#(64*`BTIME) $finish;
end
always
#(`BTIME) x = x + 1;
endmodule | 10 |
4,754 | data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-2_7segmentos/bcd-7.v | 111,433,415 | bcd-7.v | v | 26 | 75 | [] | [] | [] | [(17, 25)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-2_7segmentos/bcd-7.v:20: Little bit endian vector: MSB < LSB of bit range: 1:7\n output reg [1:7] y \n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,162 | module | module bcd7 (
input wire e,
input wire [3:0] x,
output reg [1:7] y
);
endmodule | module bcd7 (
input wire e,
input wire [3:0] x,
output reg [1:7] y
); |
endmodule | 10 |
4,755 | data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v | 111,433,415 | analisis.v | v | 64 | 79 | [] | [] | [] | [(30, 37), (39, 48), (50, 63)] | null | null | 1: b"%Error: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n nand nand_1( );\n ^\n%Error: Exiting due to 1 error(s)\n" | 3,163 | module | module dec4 (
input wire [1:0] in,
output reg [3:0] out
);
endmodule | module dec4 (
input wire [1:0] in,
output reg [3:0] out
); |
endmodule | 10 |
4,756 | data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v | 111,433,415 | analisis.v | v | 64 | 79 | [] | [] | [] | [(30, 37), (39, 48), (50, 63)] | null | null | 1: b"%Error: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n nand nand_1( );\n ^\n%Error: Exiting due to 1 error(s)\n" | 3,163 | module | module mux2 (
input wire [1:0] in,
input wire sel,
input wire en,
output reg out
);
endmodule | module mux2 (
input wire [1:0] in,
input wire sel,
input wire en,
output reg out
); |
endmodule | 10 |
4,757 | data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v | 111,433,415 | analisis.v | v | 64 | 79 | [] | [] | [] | [(30, 37), (39, 48), (50, 63)] | null | null | 1: b"%Error: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n nand nand_1( );\n ^\n%Error: Exiting due to 1 error(s)\n" | 3,163 | module | module sistema (
input wire x,
input wire y,
input wire z,
output wire f
);
dec4 dec4_1();
nand nand_1();
mux2 mux2_1();
endmodule | module sistema (
input wire x,
input wire y,
input wire z,
output wire f
); |
dec4 dec4_1();
nand nand_1();
mux2 mux2_1();
endmodule | 10 |
4,758 | data/full_repos/permissive/111433415/verilog/05_aritmeticos/aritmeticos.v | 111,433,415 | aritmeticos.v | v | 32 | 79 | [] | [] | [] | [(26, 31)] | null | data/verilator_xmls/f8f4f300-2fec-42dd-adc5-3852764ad8fe.xml | null | 3,164 | module | module aritmeticos();
initial
$display("Circuitos aritméticos");
endmodule | module aritmeticos(); |
initial
$display("Circuitos aritméticos");
endmodule | 10 |
4,766 | data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v | 111,433,415 | sumsub_tb.v | v | 118 | 81 | [] | [] | [] | [(34, 83)] | null | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:56: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:57: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:65: Unsupported or unknown PLI call: $monitor\n $monitor("%d %d %d %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:77: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n a = $random(seed);\n ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:77: ../V3Ast.cpp:358: Null item passed to setOp1p\n a = $random(seed);\n ^\n ... See the manual and https://verilator.org for more assistance.\n' | 3,168 | module | module test ();
reg signed [7:0] a;
reg signed [7:0] b;
reg op = `OP;
wire signed [7:0] f;
wire ov;
integer np;
integer seed = `SEED;
sumsub1 #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));
initial begin
np = `NP;
$dumpfile("test.vcd");
$dumpvars(0, test);
if (op == 0)
$display("Operacion: SUMA");
else
$display("Operacion: RESTA");
$display(" A B f ov");
$monitor("%d %d %d %b",
a, b, f, ov);
end
always begin
#20
a = $random(seed);
b = $random(seed);
np = np - 1;
if (np == 0)
$finish;
end
endmodule | module test (); |
reg signed [7:0] a;
reg signed [7:0] b;
reg op = `OP;
wire signed [7:0] f;
wire ov;
integer np;
integer seed = `SEED;
sumsub1 #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));
initial begin
np = `NP;
$dumpfile("test.vcd");
$dumpvars(0, test);
if (op == 0)
$display("Operacion: SUMA");
else
$display("Operacion: RESTA");
$display(" A B f ov");
$monitor("%d %d %d %b",
a, b, f, ov);
end
always begin
#20
a = $random(seed);
b = $random(seed);
np = np - 1;
if (np == 0)
$finish;
end
endmodule | 10 |
4,768 | data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v | 111,433,415 | alu_tb.v | v | 135 | 79 | [] | [] | [] | [(33, 90)] | null | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:54: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("alu_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:55: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:72: Unsupported or unknown PLI call: $monitor\n $monitor("%b (%d) %b (%d) %b (%d) %b",\n ^~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:84: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n a = $random(seed);\n ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:84: ../V3Ast.cpp:358: Null item passed to setOp1p\n a = $random(seed);\n ^\n ... See the manual and https://verilator.org for more assistance.\n' | 3,170 | module | module test ();
reg signed [7:0] a;
reg signed [7:0] b;
reg [2:0] op = `OP;
wire signed [7:0] f;
wire ov;
integer np;
integer seed = `SEED;
alu #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));
initial begin
np = `NP;
$dumpfile("alu_tb.vcd");
$dumpvars(0, test);
$write("Operacion: %d ", op);
case (op)
0: $display("SUMA");
1: $display("RESTA");
2: $display("INCREMENTO");
3: $display("DECREMENTO");
4: $display("AND");
5: $display("OR");
6: $display("XOR");
default: $display("NOT");
endcase
$display(" A B",
" F ov");
$monitor("%b (%d) %b (%d) %b (%d) %b",
a, a, b, b, f, f, ov);
end
always begin
#20
a = $random(seed);
b = $random(seed);
np = np - 1;
if (np == 0)
$finish;
end
endmodule | module test (); |
reg signed [7:0] a;
reg signed [7:0] b;
reg [2:0] op = `OP;
wire signed [7:0] f;
wire ov;
integer np;
integer seed = `SEED;
alu #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));
initial begin
np = `NP;
$dumpfile("alu_tb.vcd");
$dumpvars(0, test);
$write("Operacion: %d ", op);
case (op)
0: $display("SUMA");
1: $display("RESTA");
2: $display("INCREMENTO");
3: $display("DECREMENTO");
4: $display("AND");
5: $display("OR");
6: $display("XOR");
default: $display("NOT");
endcase
$display(" A B",
" F ov");
$monitor("%b (%d) %b (%d) %b (%d) %b",
a, a, b, b, f, f, ov);
end
always begin
#20
a = $random(seed);
b = $random(seed);
np = np - 1;
if (np == 0)
$finish;
end
endmodule | 10 |
4,774 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v | 111,433,415 | flip-flops.v | v | 114 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v:47: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'srff\'\nmodule srff (\n ^~~~\n : ... Top module \'jkff\'\nmodule jkff (\n ^~~~\n : ... Top module \'dff\'\nmodule dff (\n ^~~\n : ... Top module \'tff\'\nmodule tff (\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 3,173 | module | module srff (
input wire ck,
input wire s,
input wire r,
input wire cl,
input wire pr,
output reg q
);
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
case ({s, r})
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
endcase
endmodule | module srff (
input wire ck,
input wire s,
input wire r,
input wire cl,
input wire pr,
output reg q
); |
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
case ({s, r})
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
endcase
endmodule | 10 |
4,775 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v | 111,433,415 | flip-flops.v | v | 114 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v:47: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'srff\'\nmodule srff (\n ^~~~\n : ... Top module \'jkff\'\nmodule jkff (\n ^~~~\n : ... Top module \'dff\'\nmodule dff (\n ^~~\n : ... Top module \'tff\'\nmodule tff (\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 3,173 | module | module jkff (
input wire ck,
input wire j,
input wire k,
input wire cl,
input wire pr,
output reg q
);
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
case ({j, k})
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
endcase
endmodule | module jkff (
input wire ck,
input wire j,
input wire k,
input wire cl,
input wire pr,
output reg q
); |
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
case ({j, k})
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
endcase
endmodule | 10 |
4,776 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v | 111,433,415 | flip-flops.v | v | 114 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v:47: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'srff\'\nmodule srff (\n ^~~~\n : ... Top module \'jkff\'\nmodule jkff (\n ^~~~\n : ... Top module \'dff\'\nmodule dff (\n ^~~\n : ... Top module \'tff\'\nmodule tff (\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 3,173 | module | module dff (
input wire ck,
input wire d,
input wire cl,
input wire pr,
output reg q
);
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
q <= d;
endmodule | module dff (
input wire ck,
input wire d,
input wire cl,
input wire pr,
output reg q
); |
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else
q <= d;
endmodule | 10 |
4,777 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v | 111,433,415 | flip-flops.v | v | 114 | 79 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v:47: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'srff\'\nmodule srff (\n ^~~~\n : ... Top module \'jkff\'\nmodule jkff (\n ^~~~\n : ... Top module \'dff\'\nmodule dff (\n ^~~\n : ... Top module \'tff\'\nmodule tff (\n ^~~\n%Error: Exiting due to 1 warning(s)\n' | 3,173 | module | module tff (
input wire ck,
input wire t,
input wire cl,
input wire pr,
output reg q
);
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else if (t)
q <= ~q;
endmodule | module tff (
input wire ck,
input wire t,
input wire cl,
input wire pr,
output reg q
); |
always @(posedge ck, negedge cl, negedge pr)
if (!cl)
q <= 1'b0;
else if (!pr)
q <= 1'b1;
else if (t)
q <= ~q;
endmodule | 10 |
4,778 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v | 111,433,415 | flip-flops_tb.v | v | 110 | 80 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:47: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("flip-flops_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:48: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #180 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:54: Unsupported: fork statements\n initial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 cl = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20 cl = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #140 pr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #160 pr = 1;\n ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:62: Unsupported: fork statements\n initial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #20 j = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #40 j = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #60 k = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #80 k = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100 j = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100 k = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #160 j = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #160 k = 0;\n ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:74: Unsupported: fork statements\n initial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #20 d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #40 d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #80 d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #140 d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #10 ck = ~ck;\n ^\n%Error: Exiting due to 5 error(s), 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,174 | module | module test ();
reg ck = 0;
reg j = 0;
reg k = 0;
reg d = 0;
wire s;
wire r;
wire t;
reg cl = 1;
reg pr = 1;
wire qsr, qjk, qd, qt;
srff uut_srff(ck, s, r, cl, pr, qsr);
jkff uut_jkff(ck, j, k, cl, pr, qjk);
dff uut_dff(ck, d, cl, pr, qd);
tff uut_tff(ck, t, cl, pr, qt);
assign s = j;
assign r = k;
assign t = d;
initial begin
$dumpfile("flip-flops_tb.vcd");
$dumpvars(0, test);
#180 $finish;
end
initial fork
#5 cl = 0;
#20 cl = 1;
#140 pr = 0;
#160 pr = 1;
join
initial fork
#20 j = 1;
#40 j = 0;
#60 k = 1;
#80 k = 0;
#100 j = 1;
#100 k = 1;
#160 j = 0;
#160 k = 0;
join
initial fork
#20 d = 1;
#40 d = 0;
#80 d = 1;
#140 d = 0;
join
always
#10 ck = ~ck;
endmodule | module test (); |
reg ck = 0;
reg j = 0;
reg k = 0;
reg d = 0;
wire s;
wire r;
wire t;
reg cl = 1;
reg pr = 1;
wire qsr, qjk, qd, qt;
srff uut_srff(ck, s, r, cl, pr, qsr);
jkff uut_jkff(ck, j, k, cl, pr, qjk);
dff uut_dff(ck, d, cl, pr, qd);
tff uut_tff(ck, t, cl, pr, qt);
assign s = j;
assign r = k;
assign t = d;
initial begin
$dumpfile("flip-flops_tb.vcd");
$dumpvars(0, test);
#180 $finish;
end
initial fork
#5 cl = 0;
#20 cl = 1;
#140 pr = 0;
#160 pr = 1;
join
initial fork
#20 j = 1;
#40 j = 0;
#60 k = 1;
#80 k = 0;
#100 j = 1;
#100 k = 1;
#160 j = 0;
#160 k = 0;
join
initial fork
#20 d = 1;
#40 d = 0;
#80 d = 1;
#140 d = 0;
join
always
#10 ck = ~ck;
endmodule | 10 |
4,784 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v | 111,433,415 | secuencia_tb.v | v | 105 | 77 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("secuencia_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #15 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #450 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,178 | module | module test ();
reg ck = 0;
reg reset = 0;
reg x = 0;
wire z_mealy;
wire z_moore;
reg [0:31] in = 32'b00100111_00001110_10010010_01010011;
integer n = 32;
integer i = 0;
seq_mealy uut_mealy (ck, reset, x, z_mealy);
seq_moore uut_moore (ck, reset, x, z_moore);
initial begin
$dumpfile("secuencia_tb.vcd");
$dumpvars(0, test);
end
always begin
#10
ck = 0;
x = in[i];
#10
ck = 1;
i = i + 1;
if (i == n)
$finish;
end
initial begin
#5 reset = 1;
#15 reset = 0;
#450 reset = 1;
#20 reset = 0;
end
endmodule | module test (); |
reg ck = 0;
reg reset = 0;
reg x = 0;
wire z_mealy;
wire z_moore;
reg [0:31] in = 32'b00100111_00001110_10010010_01010011;
integer n = 32;
integer i = 0;
seq_mealy uut_mealy (ck, reset, x, z_mealy);
seq_moore uut_moore (ck, reset, x, z_moore);
initial begin
$dumpfile("secuencia_tb.vcd");
$dumpvars(0, test);
end
always begin
#10
ck = 0;
x = in[i];
#10
ck = 1;
i = i + 1;
if (i == n)
$finish;
end
initial begin
#5 reset = 1;
#15 reset = 0;
#450 reset = 1;
#20 reset = 0;
end
endmodule | 10 |
4,787 | data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v | 111,433,415 | arbiter_tb.v | v | 85 | 76 | [] | [] | [] | null | line:32: before: "$" | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("arbiter_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #180 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 ck = ~ck;\n ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:48: Unsupported: fork statements\n initial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20 r1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #40 r1 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100 r1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #120 r1 = 0;\n ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:56: Unsupported: fork statements\n initial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #60 r2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #80 r2 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100 r2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #140 r2 = 0;\n ^\n%Error: Exiting due to 4 error(s), 10 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,180 | module | module test ();
reg ck = 0;
reg r1 = 0;
reg r2 = 0;
wire g1;
wire g2;
arbiter1 uut(ck, r1, r2, g1, g2);
initial begin
$dumpfile("arbiter_tb.vcd");
$dumpvars(0, test);
#180 $finish;
end
always
#10 ck = ~ck;
initial fork
#20 r1 = 1;
#40 r1 = 0;
#100 r1 = 1;
#120 r1 = 0;
join
initial fork
#60 r2 = 1;
#80 r2 = 0;
#100 r2 = 1;
#140 r2 = 0;
join
endmodule | module test (); |
reg ck = 0;
reg r1 = 0;
reg r2 = 0;
wire g1;
wire g2;
arbiter1 uut(ck, r1, r2, g1, g2);
initial begin
$dumpfile("arbiter_tb.vcd");
$dumpvars(0, test);
#180 $finish;
end
always
#10 ck = ~ck;
initial fork
#20 r1 = 1;
#40 r1 = 0;
#100 r1 = 1;
#120 r1 = 0;
join
initial fork
#60 r2 = 1;
#80 r2 = 0;
#100 r2 = 1;
#140 r2 = 0;
join
endmodule | 10 |
4,791 | data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter.v | 111,433,415 | counter.v | v | 89 | 79 | [] | [] | [] | [(44, 84)] | null | data/verilator_xmls/d1da7fd7-7dc9-4636-a57a-c97396b3f19b.xml | null | 3,183 | module | module counter #(
parameter W = 8
)(
input wire ck,
input wire cl,
input wire en,
input wire ud,
output wire [W-1:0] q,
output reg c
);
reg [W-1:0] count;
always @(posedge ck) begin
if (cl)
count <= 0;
else if (en)
if (ud == 0)
count = count + 1;
else
count = count - 1;
end
always @* begin
if (ud == 0)
c = &count;
else
c = ~(|count);
end
assign q = count;
endmodule | module counter #(
parameter W = 8
)(
input wire ck,
input wire cl,
input wire en,
input wire ud,
output wire [W-1:0] q,
output reg c
); |
reg [W-1:0] count;
always @(posedge ck) begin
if (cl)
count <= 0;
else if (en)
if (ud == 0)
count = count + 1;
else
count = count - 1;
end
always @* begin
if (ud == 0)
c = &count;
else
c = ~(|count);
end
assign q = count;
endmodule | 10 |
4,792 | data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v | 111,433,415 | counter_tb.v | v | 86 | 82 | [] | [] | [] | null | line:49: before: "cl" | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("counter_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 ck = ~ck;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:48: syntax error, unexpected \'@\'\n @(negedge ck)\n ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:53: syntax error, unexpected \'@\'\n repeat(20) @(negedge ck);\n ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:55: syntax error, unexpected \'@\'\n repeat(8) @(negedge ck);\n ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:58: syntax error, unexpected \'@\'\n @(negedge ck);\n ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:60: syntax error, unexpected \'@\'\n repeat(2) @(negedge ck);\n ^\n%Error: Exiting due to 7 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,184 | module | module test ();
reg ck = 0;
reg cl = 0;
reg en = 0;
reg ud = 0;
wire [3:0] q;
wire c;
counter #(4) uut(.ck(ck), .cl(cl), .en(en), .ud(ud), .q(q), .c(c));
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0, test);
end
always
#10 ck = ~ck;
initial begin
@(negedge ck)
cl = 1;
@(negedge ck)
cl = 0;
en = 1;
repeat(20) @(negedge ck);
ud = 1;
repeat(8) @(negedge ck);
en = 0;
cl = 1;
@(negedge ck);
cl = 0;
repeat(2) @(negedge ck);
$finish;
end
endmodule | module test (); |
reg ck = 0;
reg cl = 0;
reg en = 0;
reg ud = 0;
wire [3:0] q;
wire c;
counter #(4) uut(.ck(ck), .cl(cl), .en(en), .ud(ud), .q(q), .c(c));
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0, test);
end
always
#10 ck = ~ck;
initial begin
@(negedge ck)
cl = 1;
@(negedge ck)
cl = 0;
en = 1;
repeat(20) @(negedge ck);
ud = 1;
repeat(8) @(negedge ck);
en = 0;
cl = 1;
@(negedge ck);
cl = 0;
repeat(2) @(negedge ck);
$finish;
end
endmodule | 10 |
4,793 | data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v | 111,433,415 | chrono1.v | v | 189 | 80 | [] | [] | [] | [(60, 184)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:107: Signal definition not found, creating implicitly: \'cnt\'\n assign cnt = ~|dcount;\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:175: Signal definition not found, creating implicitly: \'s1end\'\n : ... Suggested alternative: \'c1end\'\n if (s1end)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:101: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance chrono1\n dcount <= FDIV - 1;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 3,185 | module | module chrono1 #(
parameter FREQ = 50000000
)(
input wire ck,
input wire cl,
input wire start,
output reg [3:0] c0,
output reg [3:0] c1,
output reg [3:0] s0,
output reg [3:0] s1
);
localparam FDIV = FREQ/100;
reg [23:0] dcount;
wire c0end;
wire c1end;
wire s0end;
always @(posedge ck) begin
if (start == 0 || cl == 1 || dcount == 0)
dcount <= FDIV - 1;
else
dcount <= dcount - 1;
end
assign cnt = ~|dcount;
always @(posedge ck) begin
if (cl)
c0 <= 0;
else if (cnt) begin
if (c0end)
c0 <= 0;
else
c0 <= c0 + 1;
end
end
assign c0end = (c0 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
c1 <= 0;
else if (cnt & c0end) begin
if (c1end)
c1 <= 0;
else
c1 <= c1 + 1;
end
end
assign c1end = (c1 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
s0 <= 0;
else if (cnt & c1end & c0end) begin
if (s0end)
s0 <= 0;
else
s0 <= s0 + 1;
end
end
assign s0end = (s0 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
s1 <= 0;
else if (cnt & s0end & c1end & c0end) begin
if (s1end)
s1 <= 0;
else
s1 <= s1 + 1;
end
end
assign s1end = (s1 == 5)? 1:0;
endmodule | module chrono1 #(
parameter FREQ = 50000000
)(
input wire ck,
input wire cl,
input wire start,
output reg [3:0] c0,
output reg [3:0] c1,
output reg [3:0] s0,
output reg [3:0] s1
); |
localparam FDIV = FREQ/100;
reg [23:0] dcount;
wire c0end;
wire c1end;
wire s0end;
always @(posedge ck) begin
if (start == 0 || cl == 1 || dcount == 0)
dcount <= FDIV - 1;
else
dcount <= dcount - 1;
end
assign cnt = ~|dcount;
always @(posedge ck) begin
if (cl)
c0 <= 0;
else if (cnt) begin
if (c0end)
c0 <= 0;
else
c0 <= c0 + 1;
end
end
assign c0end = (c0 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
c1 <= 0;
else if (cnt & c0end) begin
if (c1end)
c1 <= 0;
else
c1 <= c1 + 1;
end
end
assign c1end = (c1 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
s0 <= 0;
else if (cnt & c1end & c0end) begin
if (s0end)
s0 <= 0;
else
s0 <= s0 + 1;
end
end
assign s0end = (s0 == 9)? 1:0;
always @(posedge ck) begin
if (cl)
s1 <= 0;
else if (cnt & s0end & c1end & c0end) begin
if (s1end)
s1 <= 0;
else
s1 <= s1 + 1;
end
end
assign s1end = (s1 == 5)? 1:0;
endmodule | 10 |
4,794 | data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v | 111,433,415 | chrono2.v | v | 90 | 79 | [] | [] | [] | [(20, 89)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v:50: Signal definition not found, creating implicitly: \'cnt\'\n assign cnt = ~|dcount;\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v:44: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n : ... In instance chrono2\n dcount <= FDIV - 1;\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 3,186 | module | module chrono2 #(
parameter FREQ = 50000000
)(
input wire ck,
input wire cl,
input wire start,
output reg [3:0] c0,
output reg [3:0] c1,
output reg [3:0] s0,
output reg [3:0] s1
);
localparam FDIV = FREQ/100;
reg [23:0] dcount;
always @(posedge ck) begin
if (start == 0 || cl == 1 || dcount == 0)
dcount <= FDIV - 1;
else
dcount <= dcount - 1;
end
assign cnt = ~|dcount;
always @(posedge ck) begin
if (cl) begin
c0 <= 0;
c1 <= 0;
s0 <= 0;
s1 <= 0;
end else if (cnt) begin
if (c0 < 9)
c0 <= c0 + 1;
else begin
c0 <= 0;
if (c1 < 9)
c1 <= c1 + 1;
else begin
c1 <= 0;
if (s0 < 9)
s0 <= s0 + 1;
else begin
s0 <= 0;
if (s1 < 5)
s1 = s1 + 1;
else
s1 <= 0;
end
end
end
end
end
endmodule | module chrono2 #(
parameter FREQ = 50000000
)(
input wire ck,
input wire cl,
input wire start,
output reg [3:0] c0,
output reg [3:0] c1,
output reg [3:0] s0,
output reg [3:0] s1
); |
localparam FDIV = FREQ/100;
reg [23:0] dcount;
always @(posedge ck) begin
if (start == 0 || cl == 1 || dcount == 0)
dcount <= FDIV - 1;
else
dcount <= dcount - 1;
end
assign cnt = ~|dcount;
always @(posedge ck) begin
if (cl) begin
c0 <= 0;
c1 <= 0;
s0 <= 0;
s1 <= 0;
end else if (cnt) begin
if (c0 < 9)
c0 <= c0 + 1;
else begin
c0 <= 0;
if (c1 < 9)
c1 <= c1 + 1;
else begin
c1 <= 0;
if (s0 < 9)
s0 <= s0 + 1;
else begin
s0 <= 0;
if (s1 < 5)
s1 = s1 + 1;
else
s1 <= 0;
end
end
end
end
end
endmodule | 10 |
4,796 | data/full_repos/permissive/111433415/verilog/08_memorias/memorias.v | 111,433,415 | memorias.v | v | 31 | 486 | [] | [] | [] | null | line:28: before: "$" | null | 1: b'%Error: data/full_repos/permissive/111433415/verilog/08_memorias/memorias.v:28: syntax error, unexpected $finish\n $finish;\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n' | 3,188 | module | module memorias ();
initial
$display("Memorias");
$finish;
endmodule | module memorias (); |
initial
$display("Memorias");
$finish;
endmodule | 10 |
4,797 | data/full_repos/permissive/111433415/verilog/08_memorias/08-1_rom/rom_mul.v | 111,433,415 | rom_mul.v | v | 181 | 84 | [] | [] | [] | [(38, 154), (157, 168)] | null | data/verilator_xmls/20787d07-9cb2-4655-a2ba-222e9741989f.xml | null | 3,189 | module | module rom256x8 (
input wire [7:0] a,
output reg [7:0] d
);
always @(*)
case (a)
8'h00: d = 8'h00;
8'h01: d = 8'h00;
8'h02: d = 8'h00;
8'h03: d = 8'h00;
8'h04: d = 8'h00;
8'h05: d = 8'h00;
8'h06: d = 8'h00;
8'h07: d = 8'h00;
8'h08: d = 8'h00;
8'h09: d = 8'h00;
8'h10: d = 8'h00;
8'h11: d = 8'h01;
8'h12: d = 8'h02;
8'h13: d = 8'h03;
8'h14: d = 8'h04;
8'h15: d = 8'h05;
8'h16: d = 8'h06;
8'h17: d = 8'h07;
8'h18: d = 8'h08;
8'h19: d = 8'h09;
8'h20: d = 8'h00;
8'h21: d = 8'h02;
8'h22: d = 8'h04;
8'h23: d = 8'h06;
8'h24: d = 8'h08;
8'h25: d = 8'h10;
8'h26: d = 8'h12;
8'h27: d = 8'h14;
8'h28: d = 8'h16;
8'h29: d = 8'h18;
8'h30: d = 8'h00;
8'h31: d = 8'h03;
8'h32: d = 8'h00;
8'h33: d = 8'h09;
8'h34: d = 8'h12;
8'h35: d = 8'h15;
8'h36: d = 8'h18;
8'h37: d = 8'h21;
8'h38: d = 8'h24;
8'h39: d = 8'h27;
8'h40: d = 8'h00;
8'h41: d = 8'h04;
8'h42: d = 8'h08;
8'h43: d = 8'h12;
8'h44: d = 8'h16;
8'h45: d = 8'h20;
8'h46: d = 8'h24;
8'h47: d = 8'h28;
8'h48: d = 8'h32;
8'h49: d = 8'h36;
8'h50: d = 8'h00;
8'h51: d = 8'h05;
8'h52: d = 8'h10;
8'h53: d = 8'h15;
8'h54: d = 8'h20;
8'h55: d = 8'h25;
8'h56: d = 8'h30;
8'h57: d = 8'h55;
8'h58: d = 8'h40;
8'h59: d = 8'h45;
8'h60: d = 8'h00;
8'h61: d = 8'h06;
8'h62: d = 8'h12;
8'h63: d = 8'h18;
8'h64: d = 8'h24;
8'h65: d = 8'h30;
8'h66: d = 8'h36;
8'h67: d = 8'h42;
8'h68: d = 8'h48;
8'h69: d = 8'h63;
8'h70: d = 8'h00;
8'h71: d = 8'h07;
8'h72: d = 8'h14;
8'h73: d = 8'h21;
8'h74: d = 8'h28;
8'h75: d = 8'h35;
8'h76: d = 8'h42;
8'h77: d = 8'h49;
8'h78: d = 8'h56;
8'h79: d = 8'h73;
8'h80: d = 8'h00;
8'h81: d = 8'h08;
8'h82: d = 8'h16;
8'h83: d = 8'h24;
8'h84: d = 8'h32;
8'h85: d = 8'h40;
8'h86: d = 8'h48;
8'h87: d = 8'h56;
8'h88: d = 8'h64;
8'h89: d = 8'h72;
8'h90: d = 8'h00;
8'h91: d = 8'h09;
8'h92: d = 8'h18;
8'h93: d = 8'h27;
8'h94: d = 8'h36;
8'h95: d = 8'h45;
8'h96: d = 8'h54;
8'h97: d = 8'h63;
8'h98: d = 8'h72;
8'h99: d = 8'h81;
default: d = 8'hff;
endcase
endmodule | module rom256x8 (
input wire [7:0] a,
output reg [7:0] d
); |
always @(*)
case (a)
8'h00: d = 8'h00;
8'h01: d = 8'h00;
8'h02: d = 8'h00;
8'h03: d = 8'h00;
8'h04: d = 8'h00;
8'h05: d = 8'h00;
8'h06: d = 8'h00;
8'h07: d = 8'h00;
8'h08: d = 8'h00;
8'h09: d = 8'h00;
8'h10: d = 8'h00;
8'h11: d = 8'h01;
8'h12: d = 8'h02;
8'h13: d = 8'h03;
8'h14: d = 8'h04;
8'h15: d = 8'h05;
8'h16: d = 8'h06;
8'h17: d = 8'h07;
8'h18: d = 8'h08;
8'h19: d = 8'h09;
8'h20: d = 8'h00;
8'h21: d = 8'h02;
8'h22: d = 8'h04;
8'h23: d = 8'h06;
8'h24: d = 8'h08;
8'h25: d = 8'h10;
8'h26: d = 8'h12;
8'h27: d = 8'h14;
8'h28: d = 8'h16;
8'h29: d = 8'h18;
8'h30: d = 8'h00;
8'h31: d = 8'h03;
8'h32: d = 8'h00;
8'h33: d = 8'h09;
8'h34: d = 8'h12;
8'h35: d = 8'h15;
8'h36: d = 8'h18;
8'h37: d = 8'h21;
8'h38: d = 8'h24;
8'h39: d = 8'h27;
8'h40: d = 8'h00;
8'h41: d = 8'h04;
8'h42: d = 8'h08;
8'h43: d = 8'h12;
8'h44: d = 8'h16;
8'h45: d = 8'h20;
8'h46: d = 8'h24;
8'h47: d = 8'h28;
8'h48: d = 8'h32;
8'h49: d = 8'h36;
8'h50: d = 8'h00;
8'h51: d = 8'h05;
8'h52: d = 8'h10;
8'h53: d = 8'h15;
8'h54: d = 8'h20;
8'h55: d = 8'h25;
8'h56: d = 8'h30;
8'h57: d = 8'h55;
8'h58: d = 8'h40;
8'h59: d = 8'h45;
8'h60: d = 8'h00;
8'h61: d = 8'h06;
8'h62: d = 8'h12;
8'h63: d = 8'h18;
8'h64: d = 8'h24;
8'h65: d = 8'h30;
8'h66: d = 8'h36;
8'h67: d = 8'h42;
8'h68: d = 8'h48;
8'h69: d = 8'h63;
8'h70: d = 8'h00;
8'h71: d = 8'h07;
8'h72: d = 8'h14;
8'h73: d = 8'h21;
8'h74: d = 8'h28;
8'h75: d = 8'h35;
8'h76: d = 8'h42;
8'h77: d = 8'h49;
8'h78: d = 8'h56;
8'h79: d = 8'h73;
8'h80: d = 8'h00;
8'h81: d = 8'h08;
8'h82: d = 8'h16;
8'h83: d = 8'h24;
8'h84: d = 8'h32;
8'h85: d = 8'h40;
8'h86: d = 8'h48;
8'h87: d = 8'h56;
8'h88: d = 8'h64;
8'h89: d = 8'h72;
8'h90: d = 8'h00;
8'h91: d = 8'h09;
8'h92: d = 8'h18;
8'h93: d = 8'h27;
8'h94: d = 8'h36;
8'h95: d = 8'h45;
8'h96: d = 8'h54;
8'h97: d = 8'h63;
8'h98: d = 8'h72;
8'h99: d = 8'h81;
default: d = 8'hff;
endcase
endmodule | 10 |
4,798 | data/full_repos/permissive/111433415/verilog/08_memorias/08-1_rom/rom_mul.v | 111,433,415 | rom_mul.v | v | 181 | 84 | [] | [] | [] | [(38, 154), (157, 168)] | null | data/verilator_xmls/20787d07-9cb2-4655-a2ba-222e9741989f.xml | null | 3,189 | module | module rommul_bcd (
input wire [3:0] x,
input wire [3:0] y,
output wire [7:0] z
);
rom256x8 rom (.a({x, y}), .d(z));
endmodule | module rommul_bcd (
input wire [3:0] x,
input wire [3:0] y,
output wire [7:0] z
); |
rom256x8 rom (.a({x, y}), .d(z));
endmodule | 10 |
4,806 | data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v | 111,499,712 | spi_ram_slave.v | v | 161 | 79 | [] | [] | [] | null | line:148: before: "$" | null | 1: b'%Error: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:40: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("spi_ram_slave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:41: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:43: Unsupported: Ignoring delay on this delayed statement.\n #456 cs = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:47: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:48: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:50: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:51: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:53: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:54: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:56: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:57: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:59: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:60: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:62: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:63: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:65: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:66: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:68: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:69: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:71: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:72: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:74: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:75: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:77: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:78: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:80: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:81: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:83: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:84: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:86: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:87: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:89: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:90: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:92: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:93: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:98: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:99: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:101: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:102: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:104: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:105: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:107: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:108: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:110: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:111: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:113: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:114: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:116: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:117: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:119: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:120: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:122: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:123: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:125: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:126: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:128: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:129: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:131: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:132: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:134: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:135: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:137: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:138: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:140: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:141: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:143: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:144: Unsupported: Ignoring delay on this delayed statement.\n #32 sck = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:152: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = !clk;\n ^\n%Error: Exiting due to 2 error(s), 67 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,196 | module | module test;
parameter ClkFreq = 50000000;
reg cs = 1;
reg sck = 0;
reg mosi = 0;
initial begin
$dumpfile("spi_ram_slave.vcd");
$dumpvars(0, test);
#456 cs = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
cs = 1;
#100 $finish;
end
reg clk = 0;
always #10 clk = !clk;
wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;
spi_ram_slave spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);
endmodule | module test; |
parameter ClkFreq = 50000000;
reg cs = 1;
reg sck = 0;
reg mosi = 0;
initial begin
$dumpfile("spi_ram_slave.vcd");
$dumpvars(0, test);
#456 cs = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b0;
#32 sck = 1;
#32 sck = 0;
mosi = 1'b1;
cs = 1;
#100 $finish;
end
reg clk = 0;
always #10 clk = !clk;
wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;
spi_ram_slave spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);
endmodule | 8 |
4,814 | data/full_repos/permissive/111499712/fw/src/video_hack_1.v | 111,499,712 | video_hack_1.v | v | 61 | 79 | [] | [] | [] | [(33, 60)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:43: Operator ADD expects 11 bits on the LHS, but LHS\'s VARREF \'y\' generates 6 bits.\n : ... In instance video_hack_1\nwire [6:0] t_sum = y + (t >> 4);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:43: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s ADD generates 11 bits.\n : ... In instance video_hack_1\nwire [6:0] t_sum = y + (t >> 4);\n ^\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:44: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 7 bits.\n : ... In instance video_hack_1\nwire [5:0] a_sum = t_sum + x;\n ^\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:45: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 7 bits.\n : ... In instance video_hack_1\nwire [5:0] b_sum = t_sum - x;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 3,203 | module | module video_hack_1(clk, reset, frame_begin, x, y, pixel_data);
parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;
reg [10:0] t;
wire [6:0] t_sum = y + (t >> 4);
wire [5:0] a_sum = t_sum + x;
wire [5:0] b_sum = t_sum - x;
wire [4:0] r = a_sum[5] ? a_sum[4:0] : ~a_sum[4:0];
wire [5:0] g = t_sum[6] ? t_sum[5:0] : ~t_sum[5:0];
wire [4:0] b = b_sum[5] ? b_sum[4:0] : ~b_sum[4:0];
assign pixel_data = {r, g, b};
always @(negedge clk) begin
if (reset)
t <= 0;
else if (frame_begin)
t <= t + 1;
end
endmodule | module video_hack_1(clk, reset, frame_begin, x, y, pixel_data); |
parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;
reg [10:0] t;
wire [6:0] t_sum = y + (t >> 4);
wire [5:0] a_sum = t_sum + x;
wire [5:0] b_sum = t_sum - x;
wire [4:0] r = a_sum[5] ? a_sum[4:0] : ~a_sum[4:0];
wire [5:0] g = t_sum[6] ? t_sum[5:0] : ~t_sum[5:0];
wire [4:0] b = b_sum[5] ? b_sum[4:0] : ~b_sum[4:0];
assign pixel_data = {r, g, b};
always @(negedge clk) begin
if (reset)
t <= 0;
else if (frame_begin)
t <= t + 1;
end
endmodule | 8 |
4,815 | data/full_repos/permissive/111499712/fw/src/video_hack_2.v | 111,499,712 | video_hack_2.v | v | 55 | 79 | [] | [] | [] | [(33, 54)] | null | data/verilator_xmls/0baae946-f3ae-4e51-b009-28ce38d905b3.xml | null | 3,204 | module | module video_hack_2(clk, reset, frame_begin, x, y, pixel_data);
parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;
reg [26:0] t;
wire [4:0] digit = {x[6:4], y[5:4]};
wire [23:0] count = t[26:3];
assign pixel_data = count[digit] ? {5'd0, 6'd48, 5'd24} : {5'd0, 6'd16, 5'd8};
always @(negedge clk) begin
if (reset)
t <= 0;
else if (frame_begin)
t <= t + 1;
end
endmodule | module video_hack_2(clk, reset, frame_begin, x, y, pixel_data); |
parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;
reg [26:0] t;
wire [4:0] digit = {x[6:4], y[5:4]};
wire [23:0] count = t[26:3];
assign pixel_data = count[digit] ? {5'd0, 6'd48, 5'd24} : {5'd0, 6'd16, 5'd8};
always @(negedge clk) begin
if (reset)
t <= 0;
else if (frame_begin)
t <= t + 1;
end
endmodule | 8 |
4,816 | data/full_repos/permissive/111499712/fw/syn/top.v | 111,499,712 | top.v | v | 155 | 84 | [] | [] | [] | [(30, 154)] | null | null | 1: b'%Error: data/full_repos/permissive/111499712/fw/syn/top.v:44: Cannot find file containing module: \'SB_PLL40_PAD\'\nSB_PLL40_PAD #(\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD\n data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD.v\n data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD.sv\n SB_PLL40_PAD\n SB_PLL40_PAD.v\n SB_PLL40_PAD.sv\n obj_dir/SB_PLL40_PAD\n obj_dir/SB_PLL40_PAD.v\n obj_dir/SB_PLL40_PAD.sv\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/syn/top.v:71: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance top\n resetn_gen <= {resetn_gen, pll_locked};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:80: Cannot find file containing module: \'clock_generator\'\nclock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:122: Cannot find file containing module: \'coordinate_decoder\'\ncoordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:125: Cannot find file containing module: \'spi_ram_slave\'\nspi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:128: Cannot find file containing module: \'ram_source\'\nram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,\n^~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:131: Cannot find file containing module: \'prbs_source\'\nprbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:134: Cannot find file containing module: \'video_hack_1\'\nvideo_hack_1 video_hack_1(clk, reset, frame_begin, x, y,\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:137: Cannot find file containing module: \'video_hack_2\'\nvideo_hack_2 video_hack_2(clk, reset, frame_begin, x, y,\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:149: Cannot find file containing module: \'pmodoledrgb_controller\'\npmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n' | 3,205 | module | module top(clk_100mhz, pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8,
pmod1_9, pmod1_10, pmod2_7, pmod2_8, pmod2_9, pmod2_10, rpi_sck, rpi_cs,
rpi_mosi);
parameter ClkFreq = 50000000;
input clk_100mhz;
output pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8, pmod1_9, pmod1_10;
input pmod2_7, pmod2_8, pmod2_9, pmod2_10;
input rpi_sck, rpi_cs, rpi_mosi;
wire clk_50mhz;
wire pll_locked;
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b101)
) pll (
.PACKAGEPIN(clk_100mhz),
.PLLOUTGLOBAL(clk_50mhz),
.LOCK(pll_locked),
.BYPASS(1'b0),
.RESETB(1'b1)
);
wire clk = clk_50mhz;
reg [3:0] resetn_gen = 0;
reg reset;
always @(posedge clk) begin
reset <= !&resetn_gen;
resetn_gen <= {resetn_gen, pll_locked};
end
localparam SpiDesiredFreq = 6250000;
localparam SpiPeriod = (ClkFreq + (SpiDesiredFreq * 2) - 1) / (SpiDesiredFreq * 2);
localparam SpiFreq = ClkFreq / (SpiPeriod * 2);
wire spi_clk, spi_reset;
clock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);
wire [3:0] btns = {pmod2_10, pmod2_9, pmod2_8, pmod2_7};
reg [1:0] video_source;
always @(posedge spi_clk) begin
if (spi_reset)
video_source <= 0;
else if (frame_begin) begin
if (btns[0])
video_source <= 0;
else if(btns[1])
video_source <= 1;
else if (btns[2])
video_source <= 2;
else if(btns[3])
video_source <= 3;
end
end
wire pmodoldedrgb_cs = pmod1_1;
wire pmodoldedrgb_sdin = pmod1_2;
assign pmod1_3 = 0;
wire pmodoldedrgb_sclk = pmod1_4;
wire pmodoldedrgb_d_cn = pmod1_7;
wire pmodoldedrgb_resn = pmod1_8;
wire pmodoldedrgb_vccen = pmod1_9;
wire pmodoldedrgb_pmoden = pmod1_10;
wire frame_begin, sending_pixels, sample_pixel;
wire [12:0] pixel_index;
wire [15:0] pixel_data, ram_pixel_data, prbs_pixel_data,
video_hack_1_pixel_data, video_hack_2_pixel_data;
wire [6:0] x;
wire [5:0] y;
wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;
coordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,
x, y);
spi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,
ram_addr, ram_data, ram_wr);
ram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,
pixel_index, ram_pixel_data, clk, ram_wr, ram_addr, ram_data);
prbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,
prbs_pixel_data);
video_hack_1 video_hack_1(clk, reset, frame_begin, x, y,
video_hack_1_pixel_data);
video_hack_2 video_hack_2(clk, reset, frame_begin, x, y,
video_hack_2_pixel_data);
always @(*) begin
case (video_source)
0: pixel_data = ram_pixel_data;
1: pixel_data = prbs_pixel_data;
2: pixel_data = video_hack_1_pixel_data;
3: pixel_data = video_hack_2_pixel_data;
endcase
end
pmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,
frame_begin, sending_pixels, sample_pixel, pixel_index, pixel_data,
pmodoldedrgb_cs, pmodoldedrgb_sdin, pmodoldedrgb_sclk, pmodoldedrgb_d_cn,
pmodoldedrgb_resn, pmodoldedrgb_vccen, pmodoldedrgb_pmoden);
endmodule | module top(clk_100mhz, pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8,
pmod1_9, pmod1_10, pmod2_7, pmod2_8, pmod2_9, pmod2_10, rpi_sck, rpi_cs,
rpi_mosi); |
parameter ClkFreq = 50000000;
input clk_100mhz;
output pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8, pmod1_9, pmod1_10;
input pmod2_7, pmod2_8, pmod2_9, pmod2_10;
input rpi_sck, rpi_cs, rpi_mosi;
wire clk_50mhz;
wire pll_locked;
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b101)
) pll (
.PACKAGEPIN(clk_100mhz),
.PLLOUTGLOBAL(clk_50mhz),
.LOCK(pll_locked),
.BYPASS(1'b0),
.RESETB(1'b1)
);
wire clk = clk_50mhz;
reg [3:0] resetn_gen = 0;
reg reset;
always @(posedge clk) begin
reset <= !&resetn_gen;
resetn_gen <= {resetn_gen, pll_locked};
end
localparam SpiDesiredFreq = 6250000;
localparam SpiPeriod = (ClkFreq + (SpiDesiredFreq * 2) - 1) / (SpiDesiredFreq * 2);
localparam SpiFreq = ClkFreq / (SpiPeriod * 2);
wire spi_clk, spi_reset;
clock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);
wire [3:0] btns = {pmod2_10, pmod2_9, pmod2_8, pmod2_7};
reg [1:0] video_source;
always @(posedge spi_clk) begin
if (spi_reset)
video_source <= 0;
else if (frame_begin) begin
if (btns[0])
video_source <= 0;
else if(btns[1])
video_source <= 1;
else if (btns[2])
video_source <= 2;
else if(btns[3])
video_source <= 3;
end
end
wire pmodoldedrgb_cs = pmod1_1;
wire pmodoldedrgb_sdin = pmod1_2;
assign pmod1_3 = 0;
wire pmodoldedrgb_sclk = pmod1_4;
wire pmodoldedrgb_d_cn = pmod1_7;
wire pmodoldedrgb_resn = pmod1_8;
wire pmodoldedrgb_vccen = pmod1_9;
wire pmodoldedrgb_pmoden = pmod1_10;
wire frame_begin, sending_pixels, sample_pixel;
wire [12:0] pixel_index;
wire [15:0] pixel_data, ram_pixel_data, prbs_pixel_data,
video_hack_1_pixel_data, video_hack_2_pixel_data;
wire [6:0] x;
wire [5:0] y;
wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;
coordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,
x, y);
spi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,
ram_addr, ram_data, ram_wr);
ram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,
pixel_index, ram_pixel_data, clk, ram_wr, ram_addr, ram_data);
prbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,
prbs_pixel_data);
video_hack_1 video_hack_1(clk, reset, frame_begin, x, y,
video_hack_1_pixel_data);
video_hack_2 video_hack_2(clk, reset, frame_begin, x, y,
video_hack_2_pixel_data);
always @(*) begin
case (video_source)
0: pixel_data = ram_pixel_data;
1: pixel_data = prbs_pixel_data;
2: pixel_data = video_hack_1_pixel_data;
3: pixel_data = video_hack_2_pixel_data;
endcase
end
pmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,
frame_begin, sending_pixels, sample_pixel, pixel_index, pixel_data,
pmodoldedrgb_cs, pmodoldedrgb_sdin, pmodoldedrgb_sclk, pmodoldedrgb_d_cn,
pmodoldedrgb_resn, pmodoldedrgb_vccen, pmodoldedrgb_pmoden);
endmodule | 8 |
4,817 | data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v | 111,502,990 | test.v | v | 96 | 83 | [] | [] | [] | null | line:56: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n always #5 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v:66: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,206 | module | module test();
reg clk, rst;
reg [10:0] aux;
reg [4:0] r1_index;
reg [4:0] r2_index;
reg [4:0] w_index;
wire [31:0] r1_data;
wire [31:0] r2_data;
reg [31:0] w_data;
wire [31:0] result;
register r(
.clk(clk), .rst(rst),
.r1_index(r1_index), .r1_data(r1_data),
.r2_index(r2_index), .r2_data(r2_data),
.w_index(w_index), .w_data(w_data));
alu al(
.clk(clk), .aux(aux),
.ra(r1_data),
.rb(r2_data),
.rc(result));
initial begin
clk <= 0;
rst <= 0;
aux <= 0;
r1_index <= 0;
r2_index <= 0;
w_index <= 0;
w_data <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
wait_posedge_clk(4);
w_index <= 3;
w_data <= 14;
wait_posedge_clk(1);
w_index <= 4;
w_data <= 11;
wait_posedge_clk(4);
w_index <= 0;
w_data <= 0;
r1_index <= 3;
r2_index <= 4;
wait_posedge_clk(4);
aux <= 2;
wait_posedge_clk(4);
$finish;
end
endmodule | module test(); |
reg clk, rst;
reg [10:0] aux;
reg [4:0] r1_index;
reg [4:0] r2_index;
reg [4:0] w_index;
wire [31:0] r1_data;
wire [31:0] r2_data;
reg [31:0] w_data;
wire [31:0] result;
register r(
.clk(clk), .rst(rst),
.r1_index(r1_index), .r1_data(r1_data),
.r2_index(r2_index), .r2_data(r2_data),
.w_index(w_index), .w_data(w_data));
alu al(
.clk(clk), .aux(aux),
.ra(r1_data),
.rb(r2_data),
.rc(result));
initial begin
clk <= 0;
rst <= 0;
aux <= 0;
r1_index <= 0;
r2_index <= 0;
w_index <= 0;
w_data <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
wait_posedge_clk(4);
w_index <= 3;
w_data <= 14;
wait_posedge_clk(1);
w_index <= 4;
w_data <= 11;
wait_posedge_clk(4);
w_index <= 0;
w_data <= 0;
r1_index <= 3;
r2_index <= 4;
wait_posedge_clk(4);
aux <= 2;
wait_posedge_clk(4);
$finish;
end
endmodule | 0 |
4,818 | data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v | 111,502,990 | test_ic.v | v | 83 | 83 | [] | [] | [] | null | line:45: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #5 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v:55: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,207 | module | module test_ic();
reg clk, rst;
reg set_enabled;
reg next_enabled;
reg [31:0] set_addr;
wire [31:0] pc_addr;
instruction_counter ic(
.clk(clk), .rst(rst),
.set_enabled(set_enabled), .next_enabled(next_enabled),
.set_addr(set_addr), .pc_addr(pc_addr)
);
initial begin
clk <= 0;
rst <= 0;
set_enabled <= 0;
next_enabled <= 0;
set_addr <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
wait_posedge_clk(1);
next_enabled <= 1;
wait_posedge_clk(4);
next_enabled <= 0;
wait_posedge_clk(4);
set_enabled <= 1;
set_addr <= 'hffff0080;
wait_posedge_clk(1);
set_enabled <= 0;
wait_posedge_clk(1);
next_enabled <= 1;
wait_posedge_clk(16);
$finish;
end
endmodule | module test_ic(); |
reg clk, rst;
reg set_enabled;
reg next_enabled;
reg [31:0] set_addr;
wire [31:0] pc_addr;
instruction_counter ic(
.clk(clk), .rst(rst),
.set_enabled(set_enabled), .next_enabled(next_enabled),
.set_addr(set_addr), .pc_addr(pc_addr)
);
initial begin
clk <= 0;
rst <= 0;
set_enabled <= 0;
next_enabled <= 0;
set_addr <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
wait_posedge_clk(1);
next_enabled <= 1;
wait_posedge_clk(4);
next_enabled <= 0;
wait_posedge_clk(4);
set_enabled <= 1;
set_addr <= 'hffff0080;
wait_posedge_clk(1);
set_enabled <= 0;
wait_posedge_clk(1);
next_enabled <= 1;
wait_posedge_clk(16);
$finish;
end
endmodule | 0 |
4,819 | data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v | 111,502,990 | test_top.v | v | 67 | 83 | [] | [] | [] | null | line:38: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #5 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:48: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:60: syntax error, unexpected \'@\'\n @(posedge led[7])\n ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,208 | module | module test_top();
reg clk;
reg rst;
reg [7:0] sw;
wire [7:0] led;
top_module tm(
.sysclk(clk), .cpu_resetn(~rst),
.sw(sw), .led(led));
initial begin
clk <= 0;
rst <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
sw[0] = 1;
@(posedge led[7])
;
wait_posedge_clk(10);
$finish;
end
endmodule | module test_top(); |
reg clk;
reg rst;
reg [7:0] sw;
wire [7:0] led;
top_module tm(
.sysclk(clk), .cpu_resetn(~rst),
.sw(sw), .led(led));
initial begin
clk <= 0;
rst <= 0;
end
always #5 begin
clk <= ~clk;
end
task wait_posedge_clk;
input n;
integer n;
begin
for(n=n; n>0; n=n-1) begin
@(posedge clk)
;
end
end
endtask
initial begin
wait_posedge_clk(1);
rst <= 1;
wait_posedge_clk(1);
rst <= 0;
sw[0] = 1;
@(posedge led[7])
;
wait_posedge_clk(10);
$finish;
end
endmodule | 0 |
4,820 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v | 111,502,990 | alu.v | v | 45 | 51 | [] | [] | [] | null | line:62: before: "(" | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:1: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:5: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output [`ERRC_BITDEF] errno,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:12: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:19: Define or directive not defined: \'`ERRC_NOERR\'\n Rerrno <= `ERRC_NOERR; result <= Aresult;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Rerrno <= `ERRC_NOERR; result <= Aresult;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:23: syntax error, unexpected always\n always @ (posedge clk or posedge rst) begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:28: Define or directive not defined: \'`ALUC_ADD\'\n `ALUC_ADD: Treturn(ra + rb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:29: Define or directive not defined: \'`ALUC_SUB\'\n `ALUC_SUB: Treturn(ra - rb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`ALUC_AND\'\n `ALUC_AND: Treturn(ra & rb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`ALUC_OR\'\n `ALUC_OR: Treturn(ra | rb);\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:32: Define or directive not defined: \'`ALUC_XOR\'\n `ALUC_XOR: Treturn(ra ^ rb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:33: Define or directive not defined: \'`ALUC_NOR\'\n `ALUC_NOR: Treturn(~(ra | rb));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:34: Define or directive not defined: \'`ALUC_SLL\'\n `ALUC_SLL: Treturn(ra << shift_width);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:35: Define or directive not defined: \'`ALUC_SRL\'\n `ALUC_SRL: Treturn(ra >> shift_width);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:36: Define or directive not defined: \'`ALUC_SRA\'\n `ALUC_SRA: Treturn(ra >>> shift_width);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:37: Define or directive not defined: \'`ERRC_NOERR\'\n 31: Rerrno <= `ERRC_NOERR;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:38: Define or directive not defined: \'`ERRC_ILLAUX\'\n default: Rerrno <= `ERRC_ILLAUX;\n ^~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n' | 3,209 | module | module alu(
input clk, input rst,
output [`ERRC_BITDEF] errno,
input [10:0] aux,
input [31:0] ra,
input [31:0] rb,
output [31:0] rout
);
reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
reg [31:0] result;
wire [4:0] shift_width = aux[10:6];
wire [5:0] aux_type = aux[5:0];
task Treturn(input [31:0] Aresult);
begin
Rerrno <= `ERRC_NOERR; result <= Aresult;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst) begin
Rerrno <= 0; result <= 0;
end else begin
case (aux_type)
`ALUC_ADD: Treturn(ra + rb);
`ALUC_SUB: Treturn(ra - rb);
`ALUC_AND: Treturn(ra & rb);
`ALUC_OR: Treturn(ra | rb);
`ALUC_XOR: Treturn(ra ^ rb);
`ALUC_NOR: Treturn(~(ra | rb));
`ALUC_SLL: Treturn(ra << shift_width);
`ALUC_SRL: Treturn(ra >> shift_width);
`ALUC_SRA: Treturn(ra >>> shift_width);
31: Rerrno <= `ERRC_NOERR;
default: Rerrno <= `ERRC_ILLAUX;
endcase
end
end
assign rout = result;
endmodule | module alu(
input clk, input rst,
output [`ERRC_BITDEF] errno,
input [10:0] aux,
input [31:0] ra,
input [31:0] rb,
output [31:0] rout
); |
reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
reg [31:0] result;
wire [4:0] shift_width = aux[10:6];
wire [5:0] aux_type = aux[5:0];
task Treturn(input [31:0] Aresult);
begin
Rerrno <= `ERRC_NOERR; result <= Aresult;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst) begin
Rerrno <= 0; result <= 0;
end else begin
case (aux_type)
`ALUC_ADD: Treturn(ra + rb);
`ALUC_SUB: Treturn(ra - rb);
`ALUC_AND: Treturn(ra & rb);
`ALUC_OR: Treturn(ra | rb);
`ALUC_XOR: Treturn(ra ^ rb);
`ALUC_NOR: Treturn(~(ra | rb));
`ALUC_SLL: Treturn(ra << shift_width);
`ALUC_SRL: Treturn(ra >> shift_width);
`ALUC_SRA: Treturn(ra >>> shift_width);
31: Rerrno <= `ERRC_NOERR;
default: Rerrno <= `ERRC_ILLAUX;
endcase
end
end
assign rout = result;
endmodule | 0 |
4,821 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v | 111,502,990 | cpu.v | v | 161 | 100 | [] | [] | [] | [(69, 205)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:2: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:29: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] errno\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output [`ERRC_BITDEF] errno\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:34: syntax error, unexpected assign\n wire cpu_clk; assign cpu_clk = counter == 0;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:46: syntax error, unexpected assign\n assign ic_next_enabled = counter == 3;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:50: syntax error, unexpected IDENTIFIER\n instruction_counter ic0(\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:65: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] pdc_errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] pdc_errno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:69: Define or directive not defined: \'`OPTYPE_BITDEF\'\n wire [`OPTYPE_BITDEF] pdc_opt;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`OPTYPE_BITDEF] pdc_opt;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:76: syntax error, unexpected assign\n assign reg_r1_index = pdc_rar;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:87: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] dec_errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] dec_errno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:90: Define or directive not defined: \'`OPTYPE_BITDEF\'\n wire [`OPTYPE_BITDEF] dec_opt;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:90: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`OPTYPE_BITDEF] dec_opt;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:94: syntax error, unexpected assign\n assign dec_in_rav = pdc_rar != 0 ? reg_r1_data : pdc_rav;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:109: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] exec_errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] exec_errno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:120: syntax error, unexpected IDENTIFIER\n executor exec0(\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:130: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] wb_errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:130: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] wb_errno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:134: syntax error, unexpected IDENTIFIER\n writeback wb0(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/cpu.v:149: Define or directive not defined: \'`ERRC_NOERR\'\n assign halt = wb_errno != `ERRC_NOERR;\n ^~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n' | 3,210 | module | module cpu(
input sysclk,
input rst,
output halt,
output instruction_executed,
output [`ERRC_BITDEF] errno
);
wire clk;
reg [1:0] counter;
wire cpu_clk; assign cpu_clk = counter == 0;
assign instruction_executed = counter == 3 && ~rst;
wire mem_wenabled;
wire [31:0] mem_r1_addr, mem_r2_addr, mem_w_addr;
wire [31:0] mem_r1_data, mem_r2_data, mem_w_data;
wire [4:0] reg_r1_index, reg_r2_index, reg_w_index;
wire [31:0]reg_r1_data, reg_r2_data, reg_w_data;
wire ic_set_enabled;
wire ic_next_enabled;
assign ic_next_enabled = counter == 3;
wire [31:0] ic_set_addr;
wire [31:0] ic_next_addr;
instruction_counter ic0(
.clk(~clk), .rst(rst),
.set_enabled(ic_set_enabled), .next_enabled(ic_next_enabled),
.set_addr(ic_set_addr), .pc_addr(ic_next_addr));
ram ram0(
.clk(~clk), .we(mem_wenabled),
.r1_addr(mem_r1_addr), .r1_data(mem_r1_data),
.r2_addr(mem_r2_addr), .r2_data(mem_r2_data),
.w_addr(mem_w_addr), .w_data(mem_w_data));
register reg0(
.clk(~clk), .rst(rst),
.r1_index(reg_r1_index), .r1_data(reg_r1_data),
.r2_index(reg_r2_index), .r2_data(reg_r2_data),
.w_index(reg_w_index), .w_data(reg_w_data));
wire [`ERRC_BITDEF] pdc_errno;
wire [31:0] pdc_npc;
wire [31:0] pdc_inst;
wire [5:0] pdc_opc;
wire [`OPTYPE_BITDEF] pdc_opt;
wire [4:0] pdc_rar, pdc_rbr, pdc_ror;
wire [31:0] pdc_rav, pdc_rbv;
wire [10:0] pdc_aux;
wire [15:0] pdc_imm;
wire [25:0] pdc_addr;
wire [31:0] pdc_read_mem_addr;
assign reg_r1_index = pdc_rar;
assign reg_r2_index = pdc_rbr;
assign pdc_inst = mem_r1_data;
predecoder pdc0(
.clk(clk && (counter == 0 || rst)), .rst(rst), .errno(pdc_errno),
.in_npc(mem_r1_addr), .instruction(mem_r1_data),
.out_npc(pdc_npc), .opcode(pdc_opc), .optype(pdc_opt),
.rar(pdc_rar), .rav(pdc_rav), .rbr(pdc_rbr), .rbv(pdc_rbv),
.rout(pdc_ror), .aux(pdc_aux), .imm(pdc_imm), .addr(pdc_addr),
.mem_read_addr(pdc_read_mem_addr));
wire [`ERRC_BITDEF] dec_errno;
wire [31:0] dec_npc;
wire [5:0] dec_opc;
wire [`OPTYPE_BITDEF] dec_opt;
wire [4:0] dec_ror;
wire [31:0] dec_in_rav, dec_in_rbv, dec_rav, dec_rbv;
wire [10:0] dec_aux;
assign dec_in_rav = pdc_rar != 0 ? reg_r1_data : pdc_rav;
assign dec_in_rbv = pdc_rbr != 0 ? reg_r2_data : pdc_rbv;
decoder dec0(
.clk(clk && (counter == 1 || rst)), .rst(rst),
.in_errno(pdc_errno), .out_errno(dec_errno),
.in_npc(pdc_npc), .in_opc(pdc_opc), .in_opt(pdc_opt),
.in_rav(dec_in_rav), .in_rbv(dec_in_rbv),
.in_rout(pdc_ror), .in_aux(pdc_aux), .in_imm(pdc_imm), .in_addr(pdc_addr),
.in_mem_read_addr(pdc_read_mem_addr),
.out_npc(dec_npc), .out_opc(dec_opc), .out_opt(dec_opt),
.out_rav(dec_rav), .out_rbv(dec_rbv),
.out_rout(dec_ror), .out_aux(dec_aux),
.out_mem_read_addr(mem_r2_addr));
wire [`ERRC_BITDEF] exec_errno;
wire [31:0] exec_npc;
wire [31:0] exec_rav, exec_rbv;
wire [4:0] exec_reg_index;
wire [31:0] exec_reg_data;
wire exec_pc_enabled;
wire [31:0] exec_pc_addr;
wire exec_mem_enabled;
wire [31:0] exec_mem_addr;
wire [31:0] exec_mem_data;
executor exec0(
.clk(clk && (counter == 2 || rst)), .rst(rst),
.in_errno(dec_errno), .out_errno(exec_errno),
.in_npc(dec_npc), .opcode(dec_opc), .optype(dec_opt),
.rav(dec_rav), .rbv(dec_rbv), .rout(dec_ror),
.aux(dec_aux), .mem_v(mem_r2_data),
.out_npc(exec_npc), .out_reg_index(exec_reg_index), .out_reg_data(exec_reg_data),
.out_pc_enabled(exec_pc_enabled), .out_pc_addr(exec_pc_addr), .out_mem_enabled(exec_mem_enabled),
.out_mem_addr(exec_mem_addr), .out_mem_data(exec_mem_data));
wire [`ERRC_BITDEF] wb_errno;
wire wb_pc_enabled;
wire [31:0] wb_pc_addr;
writeback wb0(
.clk(clk && (counter == 3 || rst)), .rst(rst),
.in_errno(exec_errno), .out_errno(wb_errno),
.in_npc(exec_npc), .in_reg_index(exec_reg_index), .in_reg_data(exec_reg_data),
.in_pc_enabled(exec_pc_enabled), .in_pc_addr(exec_pc_addr),
.in_mem_enabled(exec_mem_enabled), .in_mem_addr(exec_mem_addr),
.in_mem_data(exec_mem_data),
.out_reg_index(reg_w_index), .out_reg_data(reg_w_data),
.out_pc_enabled(wb_pc_enabled), .out_pc_addr(wb_pc_addr),
.out_mem_enabled(mem_wenabled), .out_mem_addr(mem_w_addr),
.out_mem_data(mem_w_data));
assign mem_r1_addr = wb_pc_enabled ? wb_pc_addr : ic_next_addr;
assign ic_set_enabled = wb_pc_enabled;
assign ic_set_addr = wb_pc_addr;
assign halt = wb_errno != `ERRC_NOERR;
assign errno = wb_errno;
assign clk = sysclk & ~halt;
always @ (posedge clk or posedge rst) begin
if(rst) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
endmodule | module cpu(
input sysclk,
input rst,
output halt,
output instruction_executed,
output [`ERRC_BITDEF] errno
); |
wire clk;
reg [1:0] counter;
wire cpu_clk; assign cpu_clk = counter == 0;
assign instruction_executed = counter == 3 && ~rst;
wire mem_wenabled;
wire [31:0] mem_r1_addr, mem_r2_addr, mem_w_addr;
wire [31:0] mem_r1_data, mem_r2_data, mem_w_data;
wire [4:0] reg_r1_index, reg_r2_index, reg_w_index;
wire [31:0]reg_r1_data, reg_r2_data, reg_w_data;
wire ic_set_enabled;
wire ic_next_enabled;
assign ic_next_enabled = counter == 3;
wire [31:0] ic_set_addr;
wire [31:0] ic_next_addr;
instruction_counter ic0(
.clk(~clk), .rst(rst),
.set_enabled(ic_set_enabled), .next_enabled(ic_next_enabled),
.set_addr(ic_set_addr), .pc_addr(ic_next_addr));
ram ram0(
.clk(~clk), .we(mem_wenabled),
.r1_addr(mem_r1_addr), .r1_data(mem_r1_data),
.r2_addr(mem_r2_addr), .r2_data(mem_r2_data),
.w_addr(mem_w_addr), .w_data(mem_w_data));
register reg0(
.clk(~clk), .rst(rst),
.r1_index(reg_r1_index), .r1_data(reg_r1_data),
.r2_index(reg_r2_index), .r2_data(reg_r2_data),
.w_index(reg_w_index), .w_data(reg_w_data));
wire [`ERRC_BITDEF] pdc_errno;
wire [31:0] pdc_npc;
wire [31:0] pdc_inst;
wire [5:0] pdc_opc;
wire [`OPTYPE_BITDEF] pdc_opt;
wire [4:0] pdc_rar, pdc_rbr, pdc_ror;
wire [31:0] pdc_rav, pdc_rbv;
wire [10:0] pdc_aux;
wire [15:0] pdc_imm;
wire [25:0] pdc_addr;
wire [31:0] pdc_read_mem_addr;
assign reg_r1_index = pdc_rar;
assign reg_r2_index = pdc_rbr;
assign pdc_inst = mem_r1_data;
predecoder pdc0(
.clk(clk && (counter == 0 || rst)), .rst(rst), .errno(pdc_errno),
.in_npc(mem_r1_addr), .instruction(mem_r1_data),
.out_npc(pdc_npc), .opcode(pdc_opc), .optype(pdc_opt),
.rar(pdc_rar), .rav(pdc_rav), .rbr(pdc_rbr), .rbv(pdc_rbv),
.rout(pdc_ror), .aux(pdc_aux), .imm(pdc_imm), .addr(pdc_addr),
.mem_read_addr(pdc_read_mem_addr));
wire [`ERRC_BITDEF] dec_errno;
wire [31:0] dec_npc;
wire [5:0] dec_opc;
wire [`OPTYPE_BITDEF] dec_opt;
wire [4:0] dec_ror;
wire [31:0] dec_in_rav, dec_in_rbv, dec_rav, dec_rbv;
wire [10:0] dec_aux;
assign dec_in_rav = pdc_rar != 0 ? reg_r1_data : pdc_rav;
assign dec_in_rbv = pdc_rbr != 0 ? reg_r2_data : pdc_rbv;
decoder dec0(
.clk(clk && (counter == 1 || rst)), .rst(rst),
.in_errno(pdc_errno), .out_errno(dec_errno),
.in_npc(pdc_npc), .in_opc(pdc_opc), .in_opt(pdc_opt),
.in_rav(dec_in_rav), .in_rbv(dec_in_rbv),
.in_rout(pdc_ror), .in_aux(pdc_aux), .in_imm(pdc_imm), .in_addr(pdc_addr),
.in_mem_read_addr(pdc_read_mem_addr),
.out_npc(dec_npc), .out_opc(dec_opc), .out_opt(dec_opt),
.out_rav(dec_rav), .out_rbv(dec_rbv),
.out_rout(dec_ror), .out_aux(dec_aux),
.out_mem_read_addr(mem_r2_addr));
wire [`ERRC_BITDEF] exec_errno;
wire [31:0] exec_npc;
wire [31:0] exec_rav, exec_rbv;
wire [4:0] exec_reg_index;
wire [31:0] exec_reg_data;
wire exec_pc_enabled;
wire [31:0] exec_pc_addr;
wire exec_mem_enabled;
wire [31:0] exec_mem_addr;
wire [31:0] exec_mem_data;
executor exec0(
.clk(clk && (counter == 2 || rst)), .rst(rst),
.in_errno(dec_errno), .out_errno(exec_errno),
.in_npc(dec_npc), .opcode(dec_opc), .optype(dec_opt),
.rav(dec_rav), .rbv(dec_rbv), .rout(dec_ror),
.aux(dec_aux), .mem_v(mem_r2_data),
.out_npc(exec_npc), .out_reg_index(exec_reg_index), .out_reg_data(exec_reg_data),
.out_pc_enabled(exec_pc_enabled), .out_pc_addr(exec_pc_addr), .out_mem_enabled(exec_mem_enabled),
.out_mem_addr(exec_mem_addr), .out_mem_data(exec_mem_data));
wire [`ERRC_BITDEF] wb_errno;
wire wb_pc_enabled;
wire [31:0] wb_pc_addr;
writeback wb0(
.clk(clk && (counter == 3 || rst)), .rst(rst),
.in_errno(exec_errno), .out_errno(wb_errno),
.in_npc(exec_npc), .in_reg_index(exec_reg_index), .in_reg_data(exec_reg_data),
.in_pc_enabled(exec_pc_enabled), .in_pc_addr(exec_pc_addr),
.in_mem_enabled(exec_mem_enabled), .in_mem_addr(exec_mem_addr),
.in_mem_data(exec_mem_data),
.out_reg_index(reg_w_index), .out_reg_data(reg_w_data),
.out_pc_enabled(wb_pc_enabled), .out_pc_addr(wb_pc_addr),
.out_mem_enabled(mem_wenabled), .out_mem_addr(mem_w_addr),
.out_mem_data(mem_w_data));
assign mem_r1_addr = wb_pc_enabled ? wb_pc_addr : ic_next_addr;
assign ic_set_enabled = wb_pc_enabled;
assign ic_set_addr = wb_pc_addr;
assign halt = wb_errno != `ERRC_NOERR;
assign errno = wb_errno;
assign clk = sysclk & ~halt;
always @ (posedge clk or posedge rst) begin
if(rst) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
endmodule | 0 |
4,822 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v | 111,502,990 | decoder.v | v | 74 | 86 | [] | [] | [] | [(48, 118)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:1: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n input [`ERRC_BITDEF] in_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input [`ERRC_BITDEF] in_errno,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:7: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] out_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:10: Define or directive not defined: \'`OPTYPE_BITDEF\'\n input [`OPTYPE_BITDEF] in_opt,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:20: Define or directive not defined: \'`OPTYPE_BITDEF\'\n output [`OPTYPE_BITDEF] out_opt,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:28: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:29: syntax error, unexpected assign\n reg [31:0] Rnpc; assign out_npc = Rnpc;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:30: syntax error, unexpected assign\n reg [5:0] Ropc; assign out_opc = Ropc;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:31: Define or directive not defined: \'`OPTYPE_BITDEF\'\n reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:32: syntax error, unexpected assign\n reg [31:0] Rrav; assign out_rav = Rrav;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:33: syntax error, unexpected assign\n reg [31:0] Rrbv; assign out_rbv = Rrbv;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:34: syntax error, unexpected assign\n reg [4:0] Rrout; assign out_rout = Rrout;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:35: syntax error, unexpected assign\n reg [10:0] Raux; assign out_aux = Raux;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:36: syntax error, unexpected assign\n reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:40: Define or directive not defined: \'`PC_ILLEGAL\'\n Rerrno <= 0; Rnpc <= `PC_ILLEGAL;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:47: Define or directive not defined: \'`OPCODE_LW\'\n if (in_opc == `OPCODE_LW) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:48: Define or directive not defined: \'`EXTSGN16to32\'\n Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:49: Define or directive not defined: \'`OPCODE_SW\'\n end else if (in_opc == `OPCODE_SW) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:50: Define or directive not defined: \'`EXTSGN16to32\'\n Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:51: Define or directive not defined: \'`OPTYPE_VJ\'\n end else if (in_opt == `OPTYPE_VJ) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:52: Define or directive not defined: \'`OPCODE_J\'\n if (in_opc == `OPCODE_J) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:58: Define or directive not defined: \'`OPCODE_BEQ\'\n `OPCODE_BEQ: Rrav <= (in_rav == in_rbv);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:59: Define or directive not defined: \'`OPCODE_BNE\'\n `OPCODE_BNE: Rrav <= (in_rav != in_rbv);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:60: Define or directive not defined: \'`OPCODE_BLT\'\n `OPCODE_BLT: Rrav <= (in_rav < in_rbv);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:61: Define or directive not defined: \'`OPCODE_BLE\'\n `OPCODE_BLE: Rrav <= (in_rav <= in_rbv);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:64: Define or directive not defined: \'`EXTSGN16to32\'\n Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:66: Define or directive not defined: \'`OPCODE_JAL\'\n end else if (in_opc == `OPCODE_JAL) begin\n ^~~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n' | 3,211 | module | module decoder(
input clk,
input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [5:0] in_opc,
input [`OPTYPE_BITDEF] in_opt,
input [31:0] in_rav,
input [31:0] in_rbv,
input [4:0] in_rout,
input [10:0] in_aux,
input [15:0] in_imm,
input [25:0] in_addr,
input [31:0] in_mem_read_addr,
output [31:0] out_npc,
output [5:0] out_opc,
output [`OPTYPE_BITDEF] out_opt,
output [31:0] out_rav,
output [31:0] out_rbv,
output [4:0] out_rout,
output [10:0] out_aux,
output [31:0] out_mem_read_addr
);
reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
reg [31:0] Rnpc; assign out_npc = Rnpc;
reg [5:0] Ropc; assign out_opc = Ropc;
reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;
reg [31:0] Rrav; assign out_rav = Rrav;
reg [31:0] Rrbv; assign out_rbv = Rrbv;
reg [4:0] Rrout; assign out_rout = Rrout;
reg [10:0] Raux; assign out_aux = Raux;
reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;
always @ (posedge clk or posedge rst) begin
if (rst) begin
Rerrno <= 0; Rnpc <= `PC_ILLEGAL;
Ropc <= 0; Ropt <= 0; Rrav <= 0; Rrbv <= 0;
Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
end else begin
Rerrno <= in_errno; Rnpc <= in_npc;
Ropc <= in_opc; Ropt <= in_opt;
Rrout <= in_rout; Raux <= in_aux;
if (in_opc == `OPCODE_LW) begin
Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;
end else if (in_opc == `OPCODE_SW) begin
Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;
end else if (in_opt == `OPTYPE_VJ) begin
if (in_opc == `OPCODE_J) begin
Rrav <= 1;
Rrbv <= in_addr;
Rmem_read_addr <= 0;
end else begin
case (in_opc)
`OPCODE_BEQ: Rrav <= (in_rav == in_rbv);
`OPCODE_BNE: Rrav <= (in_rav != in_rbv);
`OPCODE_BLT: Rrav <= (in_rav < in_rbv);
`OPCODE_BLE: Rrav <= (in_rav <= in_rbv);
endcase
Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;
end
end else if (in_opc == `OPCODE_JAL) begin
Rrav <= in_addr; Rrbv <= 0; Rmem_read_addr <= 0;
end else begin
Rmem_read_addr <= in_mem_read_addr; Rrav <= in_rav; Rrbv <= in_rbv;
end
end
end
endmodule | module decoder(
input clk,
input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [5:0] in_opc,
input [`OPTYPE_BITDEF] in_opt,
input [31:0] in_rav,
input [31:0] in_rbv,
input [4:0] in_rout,
input [10:0] in_aux,
input [15:0] in_imm,
input [25:0] in_addr,
input [31:0] in_mem_read_addr,
output [31:0] out_npc,
output [5:0] out_opc,
output [`OPTYPE_BITDEF] out_opt,
output [31:0] out_rav,
output [31:0] out_rbv,
output [4:0] out_rout,
output [10:0] out_aux,
output [31:0] out_mem_read_addr
); |
reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
reg [31:0] Rnpc; assign out_npc = Rnpc;
reg [5:0] Ropc; assign out_opc = Ropc;
reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;
reg [31:0] Rrav; assign out_rav = Rrav;
reg [31:0] Rrbv; assign out_rbv = Rrbv;
reg [4:0] Rrout; assign out_rout = Rrout;
reg [10:0] Raux; assign out_aux = Raux;
reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;
always @ (posedge clk or posedge rst) begin
if (rst) begin
Rerrno <= 0; Rnpc <= `PC_ILLEGAL;
Ropc <= 0; Ropt <= 0; Rrav <= 0; Rrbv <= 0;
Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
end else begin
Rerrno <= in_errno; Rnpc <= in_npc;
Ropc <= in_opc; Ropt <= in_opt;
Rrout <= in_rout; Raux <= in_aux;
if (in_opc == `OPCODE_LW) begin
Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;
end else if (in_opc == `OPCODE_SW) begin
Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;
end else if (in_opt == `OPTYPE_VJ) begin
if (in_opc == `OPCODE_J) begin
Rrav <= 1;
Rrbv <= in_addr;
Rmem_read_addr <= 0;
end else begin
case (in_opc)
`OPCODE_BEQ: Rrav <= (in_rav == in_rbv);
`OPCODE_BNE: Rrav <= (in_rav != in_rbv);
`OPCODE_BLT: Rrav <= (in_rav < in_rbv);
`OPCODE_BLE: Rrav <= (in_rav <= in_rbv);
endcase
Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;
end
end else if (in_opc == `OPCODE_JAL) begin
Rrav <= in_addr; Rrbv <= 0; Rmem_read_addr <= 0;
end else begin
Rmem_read_addr <= in_mem_read_addr; Rrav <= in_rav; Rrbv <= in_rbv;
end
end
end
endmodule | 0 |
4,823 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v | 111,502,990 | executor.v | v | 121 | 81 | [] | [] | [] | null | line:95: before: "(" | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:1: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n input [`ERRC_BITDEF] in_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input [`ERRC_BITDEF] in_errno,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:7: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] out_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:10: Define or directive not defined: \'`OPTYPE_BITDEF\'\n input [`OPTYPE_BITDEF] optype, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:26: syntax error, unexpected assign\n reg [31:0] Rnpc; assign out_npc = Rnpc;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:28: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] Walu_errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] Walu_errno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:29: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:31: syntax error, unexpected assign\n assign out_errno = Rerrno ? Rerrno : (Ralu_enabled ? Walu_errno : 0);\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:32: syntax error, unexpected assign\n reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:34: syntax error, unexpected assign\n reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:35: syntax error, unexpected assign\n reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:36: syntax error, unexpected assign\n reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:37: syntax error, unexpected assign\n reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:38: syntax error, unexpected assign\n reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:86: syntax error, unexpected always\n always @ (posedge clk or posedge rst) begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:96: Define or directive not defined: \'`OPTYPE_VJ\'\n if (optype == `OPTYPE_VJ) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:99: Define or directive not defined: \'`OPCODE_AUX\'\n end else if (opcode == `OPCODE_AUX) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:102: Define or directive not defined: \'`OPCODE_LW\'\n end else if (opcode == `OPCODE_LW) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:105: Define or directive not defined: \'`OPCODE_SW\'\n end else if (opcode == `OPCODE_SW) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:108: Define or directive not defined: \'`OPCODE_JAL\'\n end else if (opcode == `OPCODE_JAL) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:112: Define or directive not defined: \'`OPCODE_JR\'\n end else if (opcode == `OPCODE_JR) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:115: Define or directive not defined: \'`OPCODE_HALT\'\n end else if (opcode == `OPCODE_HALT) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/executor.v:116: Define or directive not defined: \'`ERRC_HALTED\'\n Rerrno <= `ERRC_HALTED;\n ^~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n' | 3,213 | module | module executor(
input clk,
input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [5:0] opcode,
input [`OPTYPE_BITDEF] optype,
input [31:0] rav,
input [31:0] rbv,
input [4:0] rout,
input [10:0] aux,
input [31:0] mem_v,
output [31:0] out_npc,
output [4:0] out_reg_index,
output [31:0] out_reg_data,
output out_pc_enabled,
output [31:0] out_pc_addr,
output out_mem_enabled,
output [31:0] out_mem_addr,
output [31:0] out_mem_data
);
reg [31:0] Rnpc; assign out_npc = Rnpc;
wire [31:0] Walu_routv;
wire [`ERRC_BITDEF] Walu_errno;
reg [`ERRC_BITDEF] Rerrno;
reg Ralu_enabled;
assign out_errno = Rerrno ? Rerrno : (Ralu_enabled ? Walu_errno : 0);
reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;
reg [31:0] Rreg_data;
reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;
reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;
reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;
reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;
reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;
assign out_reg_data = Ralu_enabled ? Walu_routv : Rreg_data;
alu alu0(
.clk(clk), .rst(rst), .errno(Walu_errno), .aux(Ralu_enabled ? aux : 11'd31),
.ra(rav), .rb(rbv), .rout(Walu_routv));
task Tzalu;
begin
Ralu_enabled <= 0;
end
endtask
task Tualu(input Aenabled, input[4:0] Areg_index);
begin
Ralu_enabled = Aenabled; Rreg_index <= Areg_index;
end
endtask
task Tzreg;
begin
Rreg_index <= 0;
end
endtask
task Tureg(input[4:0] Areg_index, input[31:0] Areg_data);
begin
Rreg_index <= Areg_index; Rreg_data <= Areg_data;
end
endtask
task Tzpc;
begin
Rpc_enabled <= 0;
end
endtask
task Tupc(input Apc_enabled, input[31:0] Apc_addr);
begin
Rpc_enabled <= Apc_enabled; Rpc_addr <= Apc_addr;
end
endtask
task Tzmem;
begin
Rmem_enabled <= 0;
end
endtask
task Tumem(input Amem_enabled, input[31:0] Amem_addr, input[31:0] Amem_data);
begin
Rmem_enabled <= Amem_enabled; Rmem_addr <= Amem_addr; Rmem_data <= Amem_data;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst || Rerrno) begin
if (rst) begin
Rerrno <= 0;
end
Ralu_enabled <= 0;
Rreg_index <= 0; Rpc_enabled <= 0; Rmem_enabled <= 0;
Rreg_data <= 0; Rpc_addr <= 0; Rmem_addr <= 0; Rmem_data <= 0;
end else if (in_errno == 0) begin
Rnpc <= in_npc;
if (optype == `OPTYPE_VJ) begin
Tzalu; Tzreg; Tzmem;
Tupc(rav != 0, rbv);
end else if (opcode == `OPCODE_AUX) begin
Tzpc; Tzmem;
Tualu(1, rout);
end else if (opcode == `OPCODE_LW) begin
Tzalu; Tzpc; Tzmem;
Tureg(rout, mem_v);
end else if (opcode == `OPCODE_SW) begin
Tzalu; Tzreg; Tzpc;
Tumem(1, rbv, rav);
end else if (opcode == `OPCODE_JAL) begin
Tzalu; Tzmem;
Tureg(31, in_npc+4);
Tupc(1, rav);
end else if (opcode == `OPCODE_JR) begin
Tzalu; Tzreg; Tzmem;
Tupc(1, rav);
end else if (opcode == `OPCODE_HALT) begin
Rerrno <= `ERRC_HALTED;
end
end
end
endmodule | module executor(
input clk,
input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [5:0] opcode,
input [`OPTYPE_BITDEF] optype,
input [31:0] rav,
input [31:0] rbv,
input [4:0] rout,
input [10:0] aux,
input [31:0] mem_v,
output [31:0] out_npc,
output [4:0] out_reg_index,
output [31:0] out_reg_data,
output out_pc_enabled,
output [31:0] out_pc_addr,
output out_mem_enabled,
output [31:0] out_mem_addr,
output [31:0] out_mem_data
); |
reg [31:0] Rnpc; assign out_npc = Rnpc;
wire [31:0] Walu_routv;
wire [`ERRC_BITDEF] Walu_errno;
reg [`ERRC_BITDEF] Rerrno;
reg Ralu_enabled;
assign out_errno = Rerrno ? Rerrno : (Ralu_enabled ? Walu_errno : 0);
reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;
reg [31:0] Rreg_data;
reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;
reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;
reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;
reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;
reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;
assign out_reg_data = Ralu_enabled ? Walu_routv : Rreg_data;
alu alu0(
.clk(clk), .rst(rst), .errno(Walu_errno), .aux(Ralu_enabled ? aux : 11'd31),
.ra(rav), .rb(rbv), .rout(Walu_routv));
task Tzalu;
begin
Ralu_enabled <= 0;
end
endtask
task Tualu(input Aenabled, input[4:0] Areg_index);
begin
Ralu_enabled = Aenabled; Rreg_index <= Areg_index;
end
endtask
task Tzreg;
begin
Rreg_index <= 0;
end
endtask
task Tureg(input[4:0] Areg_index, input[31:0] Areg_data);
begin
Rreg_index <= Areg_index; Rreg_data <= Areg_data;
end
endtask
task Tzpc;
begin
Rpc_enabled <= 0;
end
endtask
task Tupc(input Apc_enabled, input[31:0] Apc_addr);
begin
Rpc_enabled <= Apc_enabled; Rpc_addr <= Apc_addr;
end
endtask
task Tzmem;
begin
Rmem_enabled <= 0;
end
endtask
task Tumem(input Amem_enabled, input[31:0] Amem_addr, input[31:0] Amem_data);
begin
Rmem_enabled <= Amem_enabled; Rmem_addr <= Amem_addr; Rmem_data <= Amem_data;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst || Rerrno) begin
if (rst) begin
Rerrno <= 0;
end
Ralu_enabled <= 0;
Rreg_index <= 0; Rpc_enabled <= 0; Rmem_enabled <= 0;
Rreg_data <= 0; Rpc_addr <= 0; Rmem_addr <= 0; Rmem_data <= 0;
end else if (in_errno == 0) begin
Rnpc <= in_npc;
if (optype == `OPTYPE_VJ) begin
Tzalu; Tzreg; Tzmem;
Tupc(rav != 0, rbv);
end else if (opcode == `OPCODE_AUX) begin
Tzpc; Tzmem;
Tualu(1, rout);
end else if (opcode == `OPCODE_LW) begin
Tzalu; Tzpc; Tzmem;
Tureg(rout, mem_v);
end else if (opcode == `OPCODE_SW) begin
Tzalu; Tzreg; Tzpc;
Tumem(1, rbv, rav);
end else if (opcode == `OPCODE_JAL) begin
Tzalu; Tzmem;
Tureg(31, in_npc+4);
Tupc(1, rav);
end else if (opcode == `OPCODE_JR) begin
Tzalu; Tzreg; Tzmem;
Tupc(1, rav);
end else if (opcode == `OPCODE_HALT) begin
Rerrno <= `ERRC_HALTED;
end
end
end
endmodule | 0 |
4,824 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v | 111,502,990 | hardware_counter.v | v | 38 | 60 | [] | [] | [] | null | line:90: before: "(" | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:1: Cannot find include file: display_src/char_def.vh\n`include "display_src/char_def.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh.sv\n display_src/char_def.vh\n display_src/char_def.vh.v\n display_src/char_def.vh.sv\n obj_dir/display_src/char_def.vh\n obj_dir/display_src/char_def.vh.v\n obj_dir/display_src/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:14: Define or directive not defined: \'`Num0\'\n decoded_byte = hex_byte+`Num0;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:14: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n decoded_byte = hex_byte+`Num0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:16: Define or directive not defined: \'`UpA\'\n decoded_byte = hex_byte+`UpA-4\'d10;\n ^~~~\n%Error: Exiting due to 4 error(s)\n' | 3,214 | module | module hardware_counter(
input CLK_IP,
input RSTN_IP,
output [63:0] COUNTER_OP
);
function [7:0] decoded_byte(
input [3:0] hex_byte
);
begin
if(hex_byte<4'd10) begin
decoded_byte = hex_byte+`Num0;
end else begin
decoded_byte = hex_byte+`UpA-4'd10;
end
end
endfunction
reg [31:0] cycles;
always @(posedge CLK_IP or negedge RSTN_IP) begin
if(!RSTN_IP)begin
cycles <= 32'h0;
end else begin
cycles <= cycles + 1;
end
end
assign COUNTER_OP ={
decoded_byte(cycles[31:28]), decoded_byte(cycles[27:24]),
decoded_byte(cycles[23:20]), decoded_byte(cycles[19:16]),
decoded_byte(cycles[15:12]), decoded_byte(cycles[11:8]),
decoded_byte(cycles[7:4]), decoded_byte(cycles[3:0]) };
endmodule | module hardware_counter(
input CLK_IP,
input RSTN_IP,
output [63:0] COUNTER_OP
); |
function [7:0] decoded_byte(
input [3:0] hex_byte
);
begin
if(hex_byte<4'd10) begin
decoded_byte = hex_byte+`Num0;
end else begin
decoded_byte = hex_byte+`UpA-4'd10;
end
end
endfunction
reg [31:0] cycles;
always @(posedge CLK_IP or negedge RSTN_IP) begin
if(!RSTN_IP)begin
cycles <= 32'h0;
end else begin
cycles <= cycles + 1;
end
end
assign COUNTER_OP ={
decoded_byte(cycles[31:28]), decoded_byte(cycles[27:24]),
decoded_byte(cycles[23:20]), decoded_byte(cycles[19:16]),
decoded_byte(cycles[15:12]), decoded_byte(cycles[11:8]),
decoded_byte(cycles[7:4]), decoded_byte(cycles[3:0]) };
endmodule | 0 |
4,825 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v | 111,502,990 | hardware_counter.v | v | 38 | 60 | [] | [] | [] | null | line:90: before: "(" | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:1: Cannot find include file: display_src/char_def.vh\n`include "display_src/char_def.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/display_src/char_def.vh.sv\n display_src/char_def.vh\n display_src/char_def.vh.v\n display_src/char_def.vh.sv\n obj_dir/display_src/char_def.vh\n obj_dir/display_src/char_def.vh.v\n obj_dir/display_src/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:14: Define or directive not defined: \'`Num0\'\n decoded_byte = hex_byte+`Num0;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:14: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n decoded_byte = hex_byte+`Num0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/hardware_counter.v:16: Define or directive not defined: \'`UpA\'\n decoded_byte = hex_byte+`UpA-4\'d10;\n ^~~~\n%Error: Exiting due to 4 error(s)\n' | 3,214 | function | function [7:0] decoded_byte(
input [3:0] hex_byte
);
begin
if(hex_byte<4'd10) begin
decoded_byte = hex_byte+`Num0;
end else begin
decoded_byte = hex_byte+`UpA-4'd10;
end
end
endfunction | function [7:0] decoded_byte(
input [3:0] hex_byte
); |
begin
if(hex_byte<4'd10) begin
decoded_byte = hex_byte+`Num0;
end else begin
decoded_byte = hex_byte+`UpA-4'd10;
end
end
endfunction | 0 |
4,826 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/instruction_counter.v | 111,502,990 | instruction_counter.v | v | 26 | 44 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/2181ac77-41e0-4e7c-8f8b-587788101c30.xml | null | 3,215 | module | module instruction_counter(
input clk,
input rst,
input set_enabled,
input next_enabled,
input [31:0] set_addr,
output [31:0] pc_addr
);
reg [31:0] pc;
always @(posedge rst or posedge clk) begin
if (rst) begin
pc <= 0;
end else begin
if (set_enabled) begin
pc <= set_addr;
end else if (next_enabled) begin
pc <= pc + 4;
end
end
end
assign pc_addr = pc;
endmodule | module instruction_counter(
input clk,
input rst,
input set_enabled,
input next_enabled,
input [31:0] set_addr,
output [31:0] pc_addr
); |
reg [31:0] pc;
always @(posedge rst or posedge clk) begin
if (rst) begin
pc <= 0;
end else begin
if (set_enabled) begin
pc <= set_addr;
end else if (next_enabled) begin
pc <= pc + 4;
end
end
end
assign pc_addr = pc;
endmodule | 0 |
4,827 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v | 111,502,990 | predecoder.v | v | 144 | 94 | [] | [] | [] | null | line:93: before: "(" | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:1: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output [`ERRC_BITDEF] errno,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:11: Define or directive not defined: \'`OPTYPE_BITDEF\'\n output [`OPTYPE_BITDEF] optype, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:23: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:24: syntax error, unexpected assign\n reg [31:0] Rnpc; assign out_npc = Rnpc;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:25: syntax error, unexpected assign\n reg [5:0] Ropc; assign opcode = Ropc;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:26: Define or directive not defined: \'`OPTYPE_BITDEF\'\n reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:27: syntax error, unexpected assign\n reg [4:0] Rrar; assign rar = Rrar;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:28: syntax error, unexpected assign\n reg [31:0] Rrav; assign rav = Rrav;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:29: syntax error, unexpected assign\n reg [4:0] Rrbr; assign rbr = Rrbr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:30: syntax error, unexpected assign\n reg [31:0] Rrbv; assign rbv = Rrbv;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:31: syntax error, unexpected assign\n reg [4:0] Rrout; assign rout = Rrout;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:32: syntax error, unexpected assign\n reg [10:0] Raux; assign aux = Raux;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:33: syntax error, unexpected assign\n reg [15:0] Rimm; assign imm = Rimm;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:34: syntax error, unexpected assign\n reg [25:0] Raddr; assign addr = Raddr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:35: syntax error, unexpected assign\n reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:37: syntax error, unexpected assign\n wire [5:0] WOopc; assign WOopc = instruction[31:26];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:38: syntax error, unexpected assign\n wire [4:0] WOrs; assign WOrs = instruction[25:21];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:39: syntax error, unexpected assign\n wire [4:0] WOrt; assign WOrt = instruction[20:16];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:40: syntax error, unexpected assign\n wire [4:0] WOrd; assign WOrd = instruction[15:11];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:41: syntax error, unexpected assign\n wire [10:0]WOaux; assign WOaux = instruction[10:0];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:42: syntax error, unexpected assign\n wire [15:0]WOimm; assign WOimm = instruction[15:0];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:43: syntax error, unexpected assign\n wire [25:0]WOaddr; assign WOaddr = instruction[25:0];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:45: syntax error, unexpected assign\n wire [4:0] Wshift; assign Wshift = Raux[10:6];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:46: syntax error, unexpected assign\n wire [5:0] WauxV; assign WauxV = Raux[5:0];\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:58: Define or directive not defined: \'`OPTYPE_R\'\n Ropc <= Aopc; Ropt <= `OPTYPE_R;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Ropc <= Aopc; Ropt <= `OPTYPE_R;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:65: Define or directive not defined: \'`OPTYPE_I\'\n Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:71: Define or directive not defined: \'`OPTYPE_I\'\n Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:75: Define or directive not defined: \'`OPTYPE_BITDEF\'\n task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:81: Define or directive not defined: \'`OPTYPE_BITDEF\'\n task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:81: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:93: Define or directive not defined: \'`PC_ILLEGAL\'\n Rnpc <= `PC_ILLEGAL;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:98: Define or directive not defined: \'`OPCODE_AUX\'\n if(WOopc == `OPCODE_AUX) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:100: Define or directive not defined: \'`OPCODE_ADDI\'\n end else if(WOopc == `OPCODE_ADDI) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:101: Define or directive not defined: \'`OPCODE_AUX\'\n TopR(`OPCODE_AUX, WOrs, 0, 0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:102: Define or directive not defined: \'`EXTSGN16to32\'\n `EXTSGN16to32(WOimm),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:103: Define or directive not defined: \'`ALUC_ADD\'\n WOrt, `ALUC_ADD);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:104: Define or directive not defined: \'`OPCODE_LUI\'\n end else if(WOopc == `OPCODE_LUI) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:105: Define or directive not defined: \'`OPCODE_AUX\'\n TopR(`OPCODE_AUX, 0, 0, 0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:107: Define or directive not defined: \'`ALUC_OR\'\n WOrt, `ALUC_OR);\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:108: Define or directive not defined: \'`OPCODE_ANDI\'\n end else if(WOopc == `OPCODE_ANDI) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:109: Define or directive not defined: \'`OPCODE_AUX\'\n TopR(`OPCODE_AUX, WOrs, 0, 0,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:110: Define or directive not defined: \'`EXTZER16to32\'\n `EXTZER16to32(WOimm),\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 3,216 | module | module predecoder(
input clk,
input rst,
output [`ERRC_BITDEF] errno,
input [31:0] in_npc,
input [31:0] instruction,
output [31:0] out_npc,
output [5:0] opcode,
output [`OPTYPE_BITDEF] optype,
output [4:0] rar,
output [31:0] rav,
output [4:0] rbr,
output [31:0] rbv,
output [4:0] rout,
output [10:0] aux,
output [15:0] imm,
output [25:0] addr,
output [31:0] mem_read_addr
);
reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
reg [31:0] Rnpc; assign out_npc = Rnpc;
reg [5:0] Ropc; assign opcode = Ropc;
reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;
reg [4:0] Rrar; assign rar = Rrar;
reg [31:0] Rrav; assign rav = Rrav;
reg [4:0] Rrbr; assign rbr = Rrbr;
reg [31:0] Rrbv; assign rbv = Rrbv;
reg [4:0] Rrout; assign rout = Rrout;
reg [10:0] Raux; assign aux = Raux;
reg [15:0] Rimm; assign imm = Rimm;
reg [25:0] Raddr; assign addr = Raddr;
reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;
wire [5:0] WOopc; assign WOopc = instruction[31:26];
wire [4:0] WOrs; assign WOrs = instruction[25:21];
wire [4:0] WOrt; assign WOrt = instruction[20:16];
wire [4:0] WOrd; assign WOrd = instruction[15:11];
wire [10:0]WOaux; assign WOaux = instruction[10:0];
wire [15:0]WOimm; assign WOimm = instruction[15:0];
wire [25:0]WOaddr; assign WOaddr = instruction[25:0];
wire [4:0] Wshift; assign Wshift = Raux[10:6];
wire [5:0] WauxV; assign WauxV = Raux[5:0];
task Tset_register(input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv);
begin
Rrar <= Arar; Rrav <= Arav; Rrbr <= Arbr; Rrbv <= Arbv;
end
endtask
task TopR(
input [5:0] Aopc,
input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv,
input [4:0] Arout, input [10:0] Aaux);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_R;
Tset_register(Arar, Arav, Arbr, Arbv);
Rrout <= Arout; Raux <= Aaux; Rimm <= 0; Raddr <= 0; Rmem_read_addr <= 0;
end
endtask
task TopImemread_offset(input [5:0] Aopc, input [5:0] Arar, input [4:0] Arout);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);
Rrout <= Arout; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopImemwrite_offset(input [5:0] Aopc, input [5:0] Arsrc, input [4:0] Araddr);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);
Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
begin
Ropc <= Aopc; Ropt <= Aopt; Tset_register(WOrs, 0, WOrt, 0);
Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
begin
Ropc <= Aopc; Ropt <= Aopt; Tset_register(0, 0, 0, 0);
Rrout <= 0; Raux <= 0; Rimm <= 0; Raddr <= WOaddr;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst || Rerrno) begin
if (rst) begin
Rerrno <= 0;
end
Rnpc <= `PC_ILLEGAL;
Ropc <= 0; Ropt <= 0; Rrar <= 0; Rrav <= 0; Rrbr <= 0; Rrbv <= 0;
Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
end else if(Rerrno == 0) begin
Rnpc <= in_npc;
if(WOopc == `OPCODE_AUX) begin
TopR(WOopc, WOrs, 0, WOrt, 0, WOrd, WOaux);
end else if(WOopc == `OPCODE_ADDI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTSGN16to32(WOimm),
WOrt, `ALUC_ADD);
end else if(WOopc == `OPCODE_LUI) begin
TopR(`OPCODE_AUX, 0, 0, 0,
WOimm << 16,
WOrt, `ALUC_OR);
end else if(WOopc == `OPCODE_ANDI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_AND);
end else if(WOopc == `OPCODE_ORI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_OR);
end else if(WOopc == `OPCODE_XORI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_XOR);
end else if(WOopc == `OPCODE_HALT) begin
Ropc <= WOopc;
Ropt <= `OPTYPE_A;
Rrar <= 0; Rrav <= 0; Rrbv <= 0; Rrbr <= 0; Rrout <= 0;
end else if(WOopc == `OPCODE_LW) begin
TopImemread_offset(WOopc, WOrs, WOrt);
end else if(WOopc == `OPCODE_SW) begin
TopImemwrite_offset(WOopc, WOrt, WOrs);
end else if(WOopc == `OPCODE_BEQ || WOopc == `OPCODE_BNE
|| WOopc == `OPCODE_BLT || WOopc == `OPCODE_BLE) begin
TopIpass(WOopc, `OPTYPE_VJ);
end else if(WOopc == `OPCODE_J) begin
TopApass(WOopc, `OPTYPE_VJ);
end else if(WOopc == `OPCODE_JAL) begin
TopApass(WOopc, `OPTYPE_A);
end else if(WOopc == `OPCODE_JR) begin
TopR(WOopc, WOrs, 0, 0, 0, 0, `ALUC_NONE);
end else begin
Rerrno <= `ERRC_ILL;
end
end
end
endmodule | module predecoder(
input clk,
input rst,
output [`ERRC_BITDEF] errno,
input [31:0] in_npc,
input [31:0] instruction,
output [31:0] out_npc,
output [5:0] opcode,
output [`OPTYPE_BITDEF] optype,
output [4:0] rar,
output [31:0] rav,
output [4:0] rbr,
output [31:0] rbv,
output [4:0] rout,
output [10:0] aux,
output [15:0] imm,
output [25:0] addr,
output [31:0] mem_read_addr
); |
reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
reg [31:0] Rnpc; assign out_npc = Rnpc;
reg [5:0] Ropc; assign opcode = Ropc;
reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;
reg [4:0] Rrar; assign rar = Rrar;
reg [31:0] Rrav; assign rav = Rrav;
reg [4:0] Rrbr; assign rbr = Rrbr;
reg [31:0] Rrbv; assign rbv = Rrbv;
reg [4:0] Rrout; assign rout = Rrout;
reg [10:0] Raux; assign aux = Raux;
reg [15:0] Rimm; assign imm = Rimm;
reg [25:0] Raddr; assign addr = Raddr;
reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;
wire [5:0] WOopc; assign WOopc = instruction[31:26];
wire [4:0] WOrs; assign WOrs = instruction[25:21];
wire [4:0] WOrt; assign WOrt = instruction[20:16];
wire [4:0] WOrd; assign WOrd = instruction[15:11];
wire [10:0]WOaux; assign WOaux = instruction[10:0];
wire [15:0]WOimm; assign WOimm = instruction[15:0];
wire [25:0]WOaddr; assign WOaddr = instruction[25:0];
wire [4:0] Wshift; assign Wshift = Raux[10:6];
wire [5:0] WauxV; assign WauxV = Raux[5:0];
task Tset_register(input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv);
begin
Rrar <= Arar; Rrav <= Arav; Rrbr <= Arbr; Rrbv <= Arbv;
end
endtask
task TopR(
input [5:0] Aopc,
input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv,
input [4:0] Arout, input [10:0] Aaux);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_R;
Tset_register(Arar, Arav, Arbr, Arbv);
Rrout <= Arout; Raux <= Aaux; Rimm <= 0; Raddr <= 0; Rmem_read_addr <= 0;
end
endtask
task TopImemread_offset(input [5:0] Aopc, input [5:0] Arar, input [4:0] Arout);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);
Rrout <= Arout; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopImemwrite_offset(input [5:0] Aopc, input [5:0] Arsrc, input [4:0] Araddr);
begin
Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);
Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
begin
Ropc <= Aopc; Ropt <= Aopt; Tset_register(WOrs, 0, WOrt, 0);
Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
end
endtask
task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
begin
Ropc <= Aopc; Ropt <= Aopt; Tset_register(0, 0, 0, 0);
Rrout <= 0; Raux <= 0; Rimm <= 0; Raddr <= WOaddr;
end
endtask
always @ (posedge clk or posedge rst) begin
if (rst || Rerrno) begin
if (rst) begin
Rerrno <= 0;
end
Rnpc <= `PC_ILLEGAL;
Ropc <= 0; Ropt <= 0; Rrar <= 0; Rrav <= 0; Rrbr <= 0; Rrbv <= 0;
Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
end else if(Rerrno == 0) begin
Rnpc <= in_npc;
if(WOopc == `OPCODE_AUX) begin
TopR(WOopc, WOrs, 0, WOrt, 0, WOrd, WOaux);
end else if(WOopc == `OPCODE_ADDI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTSGN16to32(WOimm),
WOrt, `ALUC_ADD);
end else if(WOopc == `OPCODE_LUI) begin
TopR(`OPCODE_AUX, 0, 0, 0,
WOimm << 16,
WOrt, `ALUC_OR);
end else if(WOopc == `OPCODE_ANDI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_AND);
end else if(WOopc == `OPCODE_ORI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_OR);
end else if(WOopc == `OPCODE_XORI) begin
TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
WOrt, `ALUC_XOR);
end else if(WOopc == `OPCODE_HALT) begin
Ropc <= WOopc;
Ropt <= `OPTYPE_A;
Rrar <= 0; Rrav <= 0; Rrbv <= 0; Rrbr <= 0; Rrout <= 0;
end else if(WOopc == `OPCODE_LW) begin
TopImemread_offset(WOopc, WOrs, WOrt);
end else if(WOopc == `OPCODE_SW) begin
TopImemwrite_offset(WOopc, WOrt, WOrs);
end else if(WOopc == `OPCODE_BEQ || WOopc == `OPCODE_BNE
|| WOopc == `OPCODE_BLT || WOopc == `OPCODE_BLE) begin
TopIpass(WOopc, `OPTYPE_VJ);
end else if(WOopc == `OPCODE_J) begin
TopApass(WOopc, `OPTYPE_VJ);
end else if(WOopc == `OPCODE_JAL) begin
TopApass(WOopc, `OPTYPE_A);
end else if(WOopc == `OPCODE_JR) begin
TopR(WOopc, WOrs, 0, 0, 0, 0, `ALUC_NONE);
end else begin
Rerrno <= `ERRC_ILL;
end
end
end
endmodule | 0 |
4,828 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v | 111,502,990 | ram.v | v | 59 | 83 | [] | [] | [] | [(24, 58)] | null | null | 1: b"%Error-ASSIGNIN: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v:56: Assigning to input/const variable: 'r1_data'\n assign r1_data = mem[addr1_reg];\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v:57: Assigning to input/const variable: 'r2_data'\n assign r2_data = mem[addr2_reg];\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 3,217 | module | module ram(
input clk,
input we,
input [31:0] r1_addr,
input [31:0] r1_data,
input [31:0] r2_addr,
input [31:0] r2_data,
input [31:0] w_addr,
input [31:0] w_data
);
reg [13:0] addr1_reg;
reg [13:0] addr2_reg;
reg [31:0] mem [0:(`MEM_SIZE-1)];
wire [13:0] Wr1_index, Wr2_index, Ww_index;
assign Wr1_index = r1_addr[15:2];
assign Wr2_index = r2_addr[15:2];
assign Ww_index = w_addr[15:2];
integer i;
initial begin
for(i = 0; i < `MEM_SIZE; i=i+1) mem[i] = 0;
$readmemb("../../../../init.ram", mem);
end
always @(posedge clk) begin
if(we) mem[Ww_index] <= w_data;
addr1_reg <= Wr1_index;
addr2_reg <= Wr2_index;
end
assign r1_data = mem[addr1_reg];
assign r2_data = mem[addr2_reg];
endmodule | module ram(
input clk,
input we,
input [31:0] r1_addr,
input [31:0] r1_data,
input [31:0] r2_addr,
input [31:0] r2_data,
input [31:0] w_addr,
input [31:0] w_data
); |
reg [13:0] addr1_reg;
reg [13:0] addr2_reg;
reg [31:0] mem [0:(`MEM_SIZE-1)];
wire [13:0] Wr1_index, Wr2_index, Ww_index;
assign Wr1_index = r1_addr[15:2];
assign Wr2_index = r2_addr[15:2];
assign Ww_index = w_addr[15:2];
integer i;
initial begin
for(i = 0; i < `MEM_SIZE; i=i+1) mem[i] = 0;
$readmemb("../../../../init.ram", mem);
end
always @(posedge clk) begin
if(we) mem[Ww_index] <= w_data;
addr1_reg <= Wr1_index;
addr2_reg <= Wr2_index;
end
assign r1_data = mem[addr1_reg];
assign r2_data = mem[addr2_reg];
endmodule | 0 |
4,829 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/register.v | 111,502,990 | register.v | v | 31 | 44 | [] | [] | [] | [(1, 30)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/register.v:22: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'w_index\' generates 5 bits.\n : ... In instance register\n if(w_index) files[w_index] <= w_data;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,218 | module | module register(
input clk,
input rst,
input [4:0] r1_index,
output [31:0] r1_data,
input [4:0] r2_index,
output [31:0] r2_data,
input [4:0] w_index,
input [31:0] w_data
);
reg [4:0] r1_i;
reg [4:0] r2_i;
reg [31:0] files [0:31];
integer i;
always @(posedge clk or posedge rst) begin
if(rst) begin
for (i = 0; i<32; i=i+1) begin
files[i] <= 0;
end
end else begin
if(w_index) files[w_index] <= w_data;
r1_i <= r1_index;
r2_i <= r2_index;
end
end
assign r1_data = files[r1_i];
assign r2_data = files[r2_i];
endmodule | module register(
input clk,
input rst,
input [4:0] r1_index,
output [31:0] r1_data,
input [4:0] r2_index,
output [31:0] r2_data,
input [4:0] w_index,
input [31:0] w_data
); |
reg [4:0] r1_i;
reg [4:0] r2_i;
reg [31:0] files [0:31];
integer i;
always @(posedge clk or posedge rst) begin
if(rst) begin
for (i = 0; i<32; i=i+1) begin
files[i] <= 0;
end
end else begin
if(w_index) files[w_index] <= w_data;
r1_i <= r1_index;
r2_i <= r2_index;
end
end
assign r1_data = files[r1_i];
assign r2_data = files[r2_i];
endmodule | 0 |
4,830 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/top_module.v | 111,502,990 | top_module.v | v | 82 | 83 | [] | [] | [] | [(69, 126)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/top_module.v:2: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/top_module.v:39: Define or directive not defined: \'`ERRC_BITDEF\'\n wire [`ERRC_BITDEF] errno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/top_module.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`ERRC_BITDEF] errno;\n ^\n%Error: Exiting due to 3 error(s)\n' | 3,219 | module | module top_module(
input sysclk,
input cpu_resetn,
input [7:0] sw,
output [7:0] led,
output oled_dc,
output oled_res,
output oled_sclk,
output oled_sdin,
output oled_vbat,
output oled_vdd
);
wire halt;
wire instruction_executed;
wire [`ERRC_BITDEF] errno;
cpu c0(
.sysclk(sysclk), .rst(~cpu_resetn),
.halt(halt), .instruction_executed(instruction_executed), .errno(errno));
wire [63:0] hcsc_counter;
hardware_counter hc_sysclk(
.CLK_IP(sysclk & ~halt), .RSTN_IP(cpu_resetn),
.COUNTER_OP(hcsc_counter));
wire [63:0] hccc_counter;
hardware_counter hc_cpuclk(
.CLK_IP(instruction_executed), .RSTN_IP(cpu_resetn),
.COUNTER_OP(hccc_counter));
reg [2:0] counter;
reg dt_we;
reg [5:0] dt_waddr;
reg [7:0] dt_wdata;
wire [7:0] dt_led;
display_top dt(
.SYSCLK_IP(sysclk), .SW_IP(sw), .CPU_RESETN_IP(cpu_resetn),
.LED_OP(dt_led), .OLED_DC_OP(oled_dc), .OLED_RES_OP(oled_res),
.OLED_SCLK_OP(oled_sclk), .OLED_SDIN_OP(oled_sdin),
.OLED_VBAT_OP(oled_vbat), .OLED_VDD_OP(oled_vdd),
.WE_IP(ms_we), .WRITE_ADDR_IP(ms_addr), .WRITE_DATA_IP(ms_data));
assign led[7] = errno != 0;
assign led[6:0] = 7'b0 | errno;
always @ (posedge sysclk) begin
if (~cpu_resetn) begin
counter <= 0;
dt_we <= 0; dt_waddr <= 0; dt_wdata <= 0;
end else if (halt) begin
if (counter[2] == 0) begin
counter <= counter + 1;
end else begin
dt_we <= 0;
end
end
end
endmodule | module top_module(
input sysclk,
input cpu_resetn,
input [7:0] sw,
output [7:0] led,
output oled_dc,
output oled_res,
output oled_sclk,
output oled_sdin,
output oled_vbat,
output oled_vdd
); |
wire halt;
wire instruction_executed;
wire [`ERRC_BITDEF] errno;
cpu c0(
.sysclk(sysclk), .rst(~cpu_resetn),
.halt(halt), .instruction_executed(instruction_executed), .errno(errno));
wire [63:0] hcsc_counter;
hardware_counter hc_sysclk(
.CLK_IP(sysclk & ~halt), .RSTN_IP(cpu_resetn),
.COUNTER_OP(hcsc_counter));
wire [63:0] hccc_counter;
hardware_counter hc_cpuclk(
.CLK_IP(instruction_executed), .RSTN_IP(cpu_resetn),
.COUNTER_OP(hccc_counter));
reg [2:0] counter;
reg dt_we;
reg [5:0] dt_waddr;
reg [7:0] dt_wdata;
wire [7:0] dt_led;
display_top dt(
.SYSCLK_IP(sysclk), .SW_IP(sw), .CPU_RESETN_IP(cpu_resetn),
.LED_OP(dt_led), .OLED_DC_OP(oled_dc), .OLED_RES_OP(oled_res),
.OLED_SCLK_OP(oled_sclk), .OLED_SDIN_OP(oled_sdin),
.OLED_VBAT_OP(oled_vbat), .OLED_VDD_OP(oled_vdd),
.WE_IP(ms_we), .WRITE_ADDR_IP(ms_addr), .WRITE_DATA_IP(ms_data));
assign led[7] = errno != 0;
assign led[6:0] = 7'b0 | errno;
always @ (posedge sysclk) begin
if (~cpu_resetn) begin
counter <= 0;
dt_we <= 0; dt_waddr <= 0; dt_wdata <= 0;
end else if (halt) begin
if (counter[2] == 0) begin
counter <= counter + 1;
end else begin
dt_we <= 0;
end
end
end
endmodule | 0 |
4,831 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v | 111,502,990 | writeback.v | v | 50 | 58 | [] | [] | [] | [(48, 94)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:1: Cannot find include file: def.vh\n`include "def.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n def.vh\n def.vh.v\n def.vh.sv\n obj_dir/def.vh\n obj_dir/def.vh.v\n obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:5: Define or directive not defined: \'`ERRC_BITDEF\'\n input [`ERRC_BITDEF] in_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input [`ERRC_BITDEF] in_errno,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] out_errno,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:24: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:25: syntax error, unexpected assign\n reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:26: syntax error, unexpected assign\n reg [31:0] Rreg_data; assign out_reg_data = Rreg_data;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:27: syntax error, unexpected assign\n reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:28: syntax error, unexpected assign\n reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:29: syntax error, unexpected assign\n reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:30: syntax error, unexpected assign\n reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/writeback.v:31: syntax error, unexpected assign\n reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;\n ^~~~~~\n%Error: Exiting due to 13 error(s)\n' | 3,220 | module | module writeback(
input clk, input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [4:0] in_reg_index,
input [31:0] in_reg_data,
input in_pc_enabled,
input [31:0] in_pc_addr,
input in_mem_enabled,
input [31:0] in_mem_addr,
input [31:0] in_mem_data,
output [4:0] out_reg_index,
output [31:0] out_reg_data,
output out_pc_enabled,
output [31:0] out_pc_addr,
output out_mem_enabled,
output [31:0] out_mem_addr,
output [31:0] out_mem_data
);
reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;
reg [31:0] Rreg_data; assign out_reg_data = Rreg_data;
reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;
reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;
reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;
reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;
reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;
always @ (posedge clk or posedge rst) begin
if(rst) begin
Rerrno <= 0;
Rreg_index <= 0; Rpc_enabled <= 0; Rmem_enabled <= 0;
end else begin
Rerrno <= in_errno;
Rreg_index <= in_reg_index;
Rreg_data <= in_reg_data;
Rpc_enabled <= in_pc_enabled;
Rpc_addr <= in_pc_addr;
Rmem_enabled <= in_mem_enabled;
Rmem_addr <= in_mem_addr;
Rmem_data <= in_mem_data;
end
end
endmodule | module writeback(
input clk, input rst,
input [`ERRC_BITDEF] in_errno,
output [`ERRC_BITDEF] out_errno,
input [31:0] in_npc,
input [4:0] in_reg_index,
input [31:0] in_reg_data,
input in_pc_enabled,
input [31:0] in_pc_addr,
input in_mem_enabled,
input [31:0] in_mem_addr,
input [31:0] in_mem_data,
output [4:0] out_reg_index,
output [31:0] out_reg_data,
output out_pc_enabled,
output [31:0] out_pc_addr,
output out_mem_enabled,
output [31:0] out_mem_addr,
output [31:0] out_mem_data
); |
reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
reg [4:0] Rreg_index; assign out_reg_index = Rreg_index;
reg [31:0] Rreg_data; assign out_reg_data = Rreg_data;
reg Rpc_enabled; assign out_pc_enabled = Rpc_enabled;
reg [31:0] Rpc_addr; assign out_pc_addr = Rpc_addr;
reg Rmem_enabled; assign out_mem_enabled = Rmem_enabled;
reg [31:0] Rmem_addr; assign out_mem_addr = Rmem_addr;
reg [31:0] Rmem_data; assign out_mem_data = Rmem_data;
always @ (posedge clk or posedge rst) begin
if(rst) begin
Rerrno <= 0;
Rreg_index <= 0; Rpc_enabled <= 0; Rmem_enabled <= 0;
end else begin
Rerrno <= in_errno;
Rreg_index <= in_reg_index;
Rreg_data <= in_reg_data;
Rpc_enabled <= in_pc_enabled;
Rpc_addr <= in_pc_addr;
Rmem_enabled <= in_mem_enabled;
Rmem_addr <= in_mem_addr;
Rmem_data <= in_mem_data;
end
end
endmodule | 0 |
4,832 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v | 111,502,990 | char_test.v | v | 123 | 122 | [] | [] | [] | [(186, 284)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`UpH\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowA\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowV\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowE\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowA\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowF\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowU\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`LowN\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Excl\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:44: Define or directive not defined: \'`Null\'\n c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:45: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/char_test.v:46: Define or directive not defined: \'`Null\'\n `Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 3,223 | module | module char_test(
clk,
rst,
print_fin,
dout,
we,
wr_addr,
din
);
input wire clk, rst, print_fin, we;
input wire [5:0] wr_addr;
input wire [7:0] din;
output wire [64*8-1:0] dout;
reg [64*8-1:0] c_data;
assign dout = c_data;
always @(posedge clk or posedge rst) begin
if(rst) begin
c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null};
end else begin
if(we) begin
case(wr_addr)
6'd0 : c_data[64*8-1:63*8] <= din;
6'd1 : c_data[63*8-1:62*8] <= din;
6'd2 : c_data[62*8-1:61*8] <= din;
6'd3 : c_data[61*8-1:60*8] <= din;
6'd4 : c_data[60*8-1:59*8] <= din;
6'd5 : c_data[59*8-1:58*8] <= din;
6'd6 : c_data[58*8-1:57*8] <= din;
6'd7 : c_data[57*8-1:56*8] <= din;
6'd8 : c_data[56*8-1:55*8] <= din;
6'd9 : c_data[55*8-1:54*8] <= din;
6'd10 : c_data[54*8-1:53*8] <= din;
6'd11 : c_data[53*8-1:52*8] <= din;
6'd12 : c_data[52*8-1:51*8] <= din;
6'd13 : c_data[51*8-1:50*8] <= din;
6'd14 : c_data[50*8-1:49*8] <= din;
6'd15 : c_data[49*8-1:48*8] <= din;
6'd16 : c_data[48*8-1:47*8] <= din;
6'd17 : c_data[47*8-1:46*8] <= din;
6'd18 : c_data[46*8-1:45*8] <= din;
6'd19 : c_data[45*8-1:44*8] <= din;
6'd20 : c_data[44*8-1:43*8] <= din;
6'd21 : c_data[43*8-1:42*8] <= din;
6'd22 : c_data[42*8-1:41*8] <= din;
6'd23 : c_data[41*8-1:40*8] <= din;
6'd24 : c_data[40*8-1:39*8] <= din;
6'd25 : c_data[39*8-1:38*8] <= din;
6'd26 : c_data[38*8-1:37*8] <= din;
6'd27 : c_data[37*8-1:36*8] <= din;
6'd28 : c_data[36*8-1:35*8] <= din;
6'd29 : c_data[35*8-1:34*8] <= din;
6'd30 : c_data[34*8-1:33*8] <= din;
6'd31 : c_data[33*8-1:32*8] <= din;
6'd32 : c_data[32*8-1:31*8] <= din;
6'd33 : c_data[31*8-1:30*8] <= din;
6'd34 : c_data[30*8-1:29*8] <= din;
6'd35 : c_data[29*8-1:28*8] <= din;
6'd36 : c_data[28*8-1:27*8] <= din;
6'd37 : c_data[27*8-1:26*8] <= din;
6'd38 : c_data[26*8-1:25*8] <= din;
6'd39 : c_data[25*8-1:24*8] <= din;
6'd40 : c_data[24*8-1:23*8] <= din;
6'd41 : c_data[23*8-1:22*8] <= din;
6'd42 : c_data[22*8-1:21*8] <= din;
6'd43 : c_data[21*8-1:20*8] <= din;
6'd44 : c_data[20*8-1:19*8] <= din;
6'd45 : c_data[19*8-1:18*8] <= din;
6'd46 : c_data[18*8-1:17*8] <= din;
6'd47 : c_data[17*8-1:16*8] <= din;
6'd48 : c_data[16*8-1:15*8] <= din;
6'd49 : c_data[15*8-1:14*8] <= din;
6'd50 : c_data[14*8-1:13*8] <= din;
6'd51 : c_data[13*8-1:12*8] <= din;
6'd52 : c_data[12*8-1:11*8] <= din;
6'd53 : c_data[11*8-1:10*8] <= din;
6'd54 : c_data[10*8-1:9*8] <= din;
6'd55 : c_data[9*8-1:8*8] <= din;
6'd56 : c_data[8*8-1:7*8] <= din;
6'd57 : c_data[7*8-1:6*8] <= din;
6'd58 : c_data[6*8-1:5*8] <= din;
6'd59 : c_data[5*8-1:4*8] <= din;
6'd60 : c_data[4*8-1:3*8] <= din;
6'd61 : c_data[3*8-1:2*8] <= din;
6'd62 : c_data[2*8-1:1*8] <= din;
6'd63 : c_data[1*8-1:0] <= din;
endcase
end
end
end
endmodule | module char_test(
clk,
rst,
print_fin,
dout,
we,
wr_addr,
din
); |
input wire clk, rst, print_fin, we;
input wire [5:0] wr_addr;
input wire [7:0] din;
output wire [64*8-1:0] dout;
reg [64*8-1:0] c_data;
assign dout = c_data;
always @(posedge clk or posedge rst) begin
if(rst) begin
c_data <= {`UpH,`LowA,`LowV,`LowE,`Null,`LowA,`Null,`LowF,`LowU,`LowN,`Excl,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,
`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null,`Null};
end else begin
if(we) begin
case(wr_addr)
6'd0 : c_data[64*8-1:63*8] <= din;
6'd1 : c_data[63*8-1:62*8] <= din;
6'd2 : c_data[62*8-1:61*8] <= din;
6'd3 : c_data[61*8-1:60*8] <= din;
6'd4 : c_data[60*8-1:59*8] <= din;
6'd5 : c_data[59*8-1:58*8] <= din;
6'd6 : c_data[58*8-1:57*8] <= din;
6'd7 : c_data[57*8-1:56*8] <= din;
6'd8 : c_data[56*8-1:55*8] <= din;
6'd9 : c_data[55*8-1:54*8] <= din;
6'd10 : c_data[54*8-1:53*8] <= din;
6'd11 : c_data[53*8-1:52*8] <= din;
6'd12 : c_data[52*8-1:51*8] <= din;
6'd13 : c_data[51*8-1:50*8] <= din;
6'd14 : c_data[50*8-1:49*8] <= din;
6'd15 : c_data[49*8-1:48*8] <= din;
6'd16 : c_data[48*8-1:47*8] <= din;
6'd17 : c_data[47*8-1:46*8] <= din;
6'd18 : c_data[46*8-1:45*8] <= din;
6'd19 : c_data[45*8-1:44*8] <= din;
6'd20 : c_data[44*8-1:43*8] <= din;
6'd21 : c_data[43*8-1:42*8] <= din;
6'd22 : c_data[42*8-1:41*8] <= din;
6'd23 : c_data[41*8-1:40*8] <= din;
6'd24 : c_data[40*8-1:39*8] <= din;
6'd25 : c_data[39*8-1:38*8] <= din;
6'd26 : c_data[38*8-1:37*8] <= din;
6'd27 : c_data[37*8-1:36*8] <= din;
6'd28 : c_data[36*8-1:35*8] <= din;
6'd29 : c_data[35*8-1:34*8] <= din;
6'd30 : c_data[34*8-1:33*8] <= din;
6'd31 : c_data[33*8-1:32*8] <= din;
6'd32 : c_data[32*8-1:31*8] <= din;
6'd33 : c_data[31*8-1:30*8] <= din;
6'd34 : c_data[30*8-1:29*8] <= din;
6'd35 : c_data[29*8-1:28*8] <= din;
6'd36 : c_data[28*8-1:27*8] <= din;
6'd37 : c_data[27*8-1:26*8] <= din;
6'd38 : c_data[26*8-1:25*8] <= din;
6'd39 : c_data[25*8-1:24*8] <= din;
6'd40 : c_data[24*8-1:23*8] <= din;
6'd41 : c_data[23*8-1:22*8] <= din;
6'd42 : c_data[22*8-1:21*8] <= din;
6'd43 : c_data[21*8-1:20*8] <= din;
6'd44 : c_data[20*8-1:19*8] <= din;
6'd45 : c_data[19*8-1:18*8] <= din;
6'd46 : c_data[18*8-1:17*8] <= din;
6'd47 : c_data[17*8-1:16*8] <= din;
6'd48 : c_data[16*8-1:15*8] <= din;
6'd49 : c_data[15*8-1:14*8] <= din;
6'd50 : c_data[14*8-1:13*8] <= din;
6'd51 : c_data[13*8-1:12*8] <= din;
6'd52 : c_data[12*8-1:11*8] <= din;
6'd53 : c_data[11*8-1:10*8] <= din;
6'd54 : c_data[10*8-1:9*8] <= din;
6'd55 : c_data[9*8-1:8*8] <= din;
6'd56 : c_data[8*8-1:7*8] <= din;
6'd57 : c_data[7*8-1:6*8] <= din;
6'd58 : c_data[6*8-1:5*8] <= din;
6'd59 : c_data[5*8-1:4*8] <= din;
6'd60 : c_data[4*8-1:3*8] <= din;
6'd61 : c_data[3*8-1:2*8] <= din;
6'd62 : c_data[2*8-1:1*8] <= din;
6'd63 : c_data[1*8-1:0] <= din;
endcase
end
end
end
endmodule | 0 |
4,833 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v | 111,502,990 | delay_gen.v | v | 89 | 83 | [] | [] | [] | [(186, 250)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:39: Define or directive not defined: \'`Delay_done\'\n assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:39: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:43: Define or directive not defined: \'`Delay_idle\'\n current_state <= `Delay_idle;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Delay_idle;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:46: Define or directive not defined: \'`Delay_idle\'\n `Delay_idle: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:46: syntax error, unexpected \':\', expecting endcase\n `Delay_idle: begin\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:48: Define or directive not defined: \'`Delay_hold\'\n current_state <= `Delay_hold;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:51: Define or directive not defined: \'`Delay_hold\'\n `Delay_hold: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:51: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Delay_hold: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:53: Define or directive not defined: \'`Delay_done\'\n current_state <= `Delay_done;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:56: Define or directive not defined: \'`Delay_done\'\n `Delay_done: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:58: Define or directive not defined: \'`Delay_idle\'\n current_state <= `Delay_idle;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:62: Define or directive not defined: \'`Delay_idle\'\n current_state <= `Delay_idle;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:73: Define or directive not defined: \'`Delay_hold\'\n if(current_state == `Delay_hold) begin\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 3,224 | module | module delay_gen(
clk,
rst,
delay_ms,
delay_en,
delay_fin
);
input clk, rst, delay_en;
input [11:0] delay_ms;
output delay_fin;
reg [16:0] clk_counter;
reg [11:0] ms_counter;
reg [1:0] current_state;
assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Delay_idle;
end else begin
case(current_state)
`Delay_idle: begin
if(delay_en) begin
current_state <= `Delay_hold;
end
end
`Delay_hold: begin
if(ms_counter == delay_ms) begin
current_state <= `Delay_done;
end
end
`Delay_done: begin
if(!delay_en) begin
current_state <= `Delay_idle;
end
end
default: begin
current_state <= `Delay_idle;
end
endcase
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
clk_counter <= 17'b0;
ms_counter <= 12'b0;
end else begin
if(current_state == `Delay_hold) begin
if(clk_counter == 17'b11000011010100000) begin
clk_counter <= 17'b0;
ms_counter <= ms_counter + 1;
end else begin
clk_counter <= clk_counter + 1;
end
end else begin
clk_counter <= 17'b0;
ms_counter <= 12'b0;
end
end
end
endmodule | module delay_gen(
clk,
rst,
delay_ms,
delay_en,
delay_fin
); |
input clk, rst, delay_en;
input [11:0] delay_ms;
output delay_fin;
reg [16:0] clk_counter;
reg [11:0] ms_counter;
reg [1:0] current_state;
assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Delay_idle;
end else begin
case(current_state)
`Delay_idle: begin
if(delay_en) begin
current_state <= `Delay_hold;
end
end
`Delay_hold: begin
if(ms_counter == delay_ms) begin
current_state <= `Delay_done;
end
end
`Delay_done: begin
if(!delay_en) begin
current_state <= `Delay_idle;
end
end
default: begin
current_state <= `Delay_idle;
end
endcase
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
clk_counter <= 17'b0;
ms_counter <= 12'b0;
end else begin
if(current_state == `Delay_hold) begin
if(clk_counter == 17'b11000011010100000) begin
clk_counter <= 17'b0;
ms_counter <= ms_counter + 1;
end else begin
clk_counter <= clk_counter + 1;
end
end else begin
clk_counter <= 17'b0;
ms_counter <= 12'b0;
end
end
end
endmodule | 0 |
4,834 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v | 111,502,990 | display_top.v | v | 73 | 83 | [] | [] | [] | [(186, 234)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 3,225 | module | module display_top(
input SYSCLK_IP,
input [7:0] SW_IP,
input CPU_RESETN_IP,
output [7:0] LED_OP,
output OLED_DC_OP,
output OLED_RES_OP,
output OLED_SCLK_OP,
output OLED_SDIN_OP,
output OLED_VBAT_OP,
output OLED_VDD_OP,
input WE_IP,
input [5:0] WRITE_ADDR_IP,
input [7:0] WRITE_DATA_IP
);
reg [7:0] sw_r;
wire [64*8-1:0] char_data;
wire print_fin;
oled_ctrl o_ctrl(
.clk(SYSCLK_IP),
.rst(~CPU_RESETN_IP),
.dc(OLED_DC_OP),
.res(OLED_RES_OP),
.sclk(OLED_SCLK_OP),
.sdo(OLED_SDIN_OP),
.vbat(OLED_VBAT_OP),
.vdd(OLED_VDD_OP),
.char_data(char_data),
.print_fin(print_fin)
);
char_test c_test(
.clk(SYSCLK_IP),
.rst(~CPU_RESETN_IP),
.dout(char_data),
.print_fin(print_fin),
.we(WE_IP),
.wr_addr(WRITE_ADDR_IP),
.din(WRITE_DATA_IP)
);
assign LED_OP = sw_r;
always @(posedge SYSCLK_IP)
sw_r <= SW_IP;
endmodule | module display_top(
input SYSCLK_IP,
input [7:0] SW_IP,
input CPU_RESETN_IP,
output [7:0] LED_OP,
output OLED_DC_OP,
output OLED_RES_OP,
output OLED_SCLK_OP,
output OLED_SDIN_OP,
output OLED_VBAT_OP,
output OLED_VDD_OP,
input WE_IP,
input [5:0] WRITE_ADDR_IP,
input [7:0] WRITE_DATA_IP
); |
reg [7:0] sw_r;
wire [64*8-1:0] char_data;
wire print_fin;
oled_ctrl o_ctrl(
.clk(SYSCLK_IP),
.rst(~CPU_RESETN_IP),
.dc(OLED_DC_OP),
.res(OLED_RES_OP),
.sclk(OLED_SCLK_OP),
.sdo(OLED_SDIN_OP),
.vbat(OLED_VBAT_OP),
.vdd(OLED_VDD_OP),
.char_data(char_data),
.print_fin(print_fin)
);
char_test c_test(
.clk(SYSCLK_IP),
.rst(~CPU_RESETN_IP),
.dout(char_data),
.print_fin(print_fin),
.we(WE_IP),
.wr_addr(WRITE_ADDR_IP),
.din(WRITE_DATA_IP)
);
assign LED_OP = sw_r;
always @(posedge SYSCLK_IP)
sw_r <= SW_IP;
endmodule | 0 |
4,835 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v | 111,502,990 | oled_ctrl.v | v | 111 | 83 | [] | [] | [] | [(186, 272)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:46: Define or directive not defined: \'`Octrl_init\'\n assign cs = (current_state == `Octrl_init) ? init_cs : exam_cs;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign cs = (current_state == `Octrl_init) ? init_cs : exam_cs;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:47: Define or directive not defined: \'`Octrl_init\'\n assign sdo = (current_state == `Octrl_init) ? init_sdo : exam_sdo;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign sdo = (current_state == `Octrl_init) ? init_sdo : exam_sdo;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:48: Define or directive not defined: \'`Octrl_init\'\n assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:49: Define or directive not defined: \'`Octrl_init\'\n assign dc = (current_state == `Octrl_init) ? init_dc : exam_dc;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign dc = (current_state == `Octrl_init) ? init_dc : exam_dc;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:52: Define or directive not defined: \'`Octrl_init\'\n assign init_en = (current_state == `Octrl_init) ? 1 : 0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign init_en = (current_state == `Octrl_init) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:53: Define or directive not defined: \'`Octrl_exam\'\n assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:53: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:83: Define or directive not defined: \'`Octrl_idle\'\n current_state <= `Octrl_idle;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Octrl_idle;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:86: Define or directive not defined: \'`Octrl_idle\'\n `Octrl_idle: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:86: syntax error, unexpected \':\', expecting endcase\n `Octrl_idle: begin\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:87: Define or directive not defined: \'`Octrl_init\'\n current_state <= `Octrl_init;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:89: Define or directive not defined: \'`Octrl_init\'\n `Octrl_init: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:89: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Octrl_init: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:91: Define or directive not defined: \'`Octrl_exam\'\n current_state <= `Octrl_exam;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:94: Define or directive not defined: \'`Octrl_exam\'\n `Octrl_exam: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Octrl_exam: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:97: Define or directive not defined: \'`Octrl_exam\'\n current_state <= `Octrl_exam;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:100: Define or directive not defined: \'`Octrl_done\'\n `Octrl_done: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:101: Define or directive not defined: \'`Octrl_done\'\n current_state <= `Octrl_done;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:104: Define or directive not defined: \'`Octrl_idle\'\n current_state <= `Octrl_idle;\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 3,226 | module | module oled_ctrl(
clk,
rst,
cs,
sdo,
sclk,
dc,
res,
vbat,
vdd,
char_data,
print_fin
);
input clk, rst;
output cs, sdo, sclk, dc, res, vbat, vdd;
input [64*8-1:0] char_data;
output print_fin;
wire init_cs, init_sdo, init_sclk, init_dc, init_en, init_done;
wire exam_cs, exam_sdo, exam_sclk, exam_dc, exam_en, exam_done;
reg [1:0] current_state;
assign cs = (current_state == `Octrl_init) ? init_cs : exam_cs;
assign sdo = (current_state == `Octrl_init) ? init_sdo : exam_sdo;
assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;
assign dc = (current_state == `Octrl_init) ? init_dc : exam_dc;
assign print_fin = exam_done;
assign init_en = (current_state == `Octrl_init) ? 1 : 0;
assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;
oled_init o_init(
.clk(clk),
.rst(rst),
.en(init_en),
.cs(init_cs),
.sdo(init_sdo),
.sclk(init_sclk),
.dc(init_dc),
.res(res),
.vbat(vbat),
.vdd(vdd),
.fin(init_done)
);
oled_exam o_exam(
.clk(clk),
.rst(rst),
.en(exam_en),
.cs(exam_cs),
.sdo(exam_sdo),
.sclk(exam_sclk),
.dc(exam_dc),
.fin(exam_done),
.char_data(char_data)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Octrl_idle;
end else begin
case(current_state)
`Octrl_idle: begin
current_state <= `Octrl_init;
end
`Octrl_init: begin
if(init_done) begin
current_state <= `Octrl_exam;
end
end
`Octrl_exam: begin
if(exam_done) begin
current_state <= `Octrl_exam;
end
end
`Octrl_done: begin
current_state <= `Octrl_done;
end
default: begin
current_state <= `Octrl_idle;
end
endcase
end
end
endmodule | module oled_ctrl(
clk,
rst,
cs,
sdo,
sclk,
dc,
res,
vbat,
vdd,
char_data,
print_fin
); |
input clk, rst;
output cs, sdo, sclk, dc, res, vbat, vdd;
input [64*8-1:0] char_data;
output print_fin;
wire init_cs, init_sdo, init_sclk, init_dc, init_en, init_done;
wire exam_cs, exam_sdo, exam_sclk, exam_dc, exam_en, exam_done;
reg [1:0] current_state;
assign cs = (current_state == `Octrl_init) ? init_cs : exam_cs;
assign sdo = (current_state == `Octrl_init) ? init_sdo : exam_sdo;
assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;
assign dc = (current_state == `Octrl_init) ? init_dc : exam_dc;
assign print_fin = exam_done;
assign init_en = (current_state == `Octrl_init) ? 1 : 0;
assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;
oled_init o_init(
.clk(clk),
.rst(rst),
.en(init_en),
.cs(init_cs),
.sdo(init_sdo),
.sclk(init_sclk),
.dc(init_dc),
.res(res),
.vbat(vbat),
.vdd(vdd),
.fin(init_done)
);
oled_exam o_exam(
.clk(clk),
.rst(rst),
.en(exam_en),
.cs(exam_cs),
.sdo(exam_sdo),
.sclk(exam_sclk),
.dc(exam_dc),
.fin(exam_done),
.char_data(char_data)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Octrl_idle;
end else begin
case(current_state)
`Octrl_idle: begin
current_state <= `Octrl_init;
end
`Octrl_init: begin
if(init_done) begin
current_state <= `Octrl_exam;
end
end
`Octrl_exam: begin
if(exam_done) begin
current_state <= `Octrl_exam;
end
end
`Octrl_done: begin
current_state <= `Octrl_done;
end
default: begin
current_state <= `Octrl_idle;
end
endcase
end
end
endmodule | 0 |
4,836 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v | 111,502,990 | oled_exam.v | v | 256 | 83 | [] | [] | [] | [(186, 417)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:58: Define or directive not defined: \'`Wait1_e\'\n assign fin = (current_state == `Wait1_e) ? 1 : 0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign fin = (current_state == `Wait1_e) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:87: Define or directive not defined: \'`Idle_e\'\n current_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Idle_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:88: Define or directive not defined: \'`Idle_e\'\n after_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `Idle_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:89: Define or directive not defined: \'`Idle_e\'\n after_page_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_page_state <= `Idle_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:90: Define or directive not defined: \'`Idle_e\'\n after_char_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_char_state <= `Idle_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:91: Define or directive not defined: \'`Idle_e\'\n after_update_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_update_state <= `Idle_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:103: Define or directive not defined: \'`Idle_e\'\n `Idle_e: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:103: syntax error, unexpected \':\', expecting endcase\n `Idle_e: begin\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:105: Define or directive not defined: \'`ClearDC\'\n current_state <= `ClearDC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:106: Define or directive not defined: \'`STR1\'\n after_page_state <= `STR1;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_page_state <= `STR1;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:111: Define or directive not defined: \'`STR1\'\n `STR1: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:111: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `STR1: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:112: Define or directive not defined: \'`UpdateScreen\'\n current_state <= `UpdateScreen;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:113: Define or directive not defined: \'`Wait1_e\'\n after_update_state <= `Wait1_e;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_update_state <= `Wait1_e;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:118: Define or directive not defined: \'`Wait1_e\'\n `Wait1_e: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:118: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Wait1_e: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:120: Define or directive not defined: \'`Idle_e\'\n current_state <= `Idle_e;\n ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:123: Define or directive not defined: \'`Transition3_e\'\n current_state <= `Transition3_e;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:124: Define or directive not defined: \'`STR1\'\n after_state <= `STR1;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:128: Define or directive not defined: \'`UpdateScreen\'\n `UpdateScreen: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:130: Define or directive not defined: \'`SendChar1\'\n current_state <= `SendChar1;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:132: syntax error, unexpected <=, expecting IDENTIFIER\n t_index <= 0;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:134: Define or directive not defined: \'`ClearDC\'\n after_char_state <= `ClearDC;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:136: syntax error, unexpected <=, expecting IDENTIFIER\n after_page_state <= after_update_state;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:138: syntax error, unexpected <=, expecting IDENTIFIER\n after_page_state <= `UpdateScreen;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:138: Define or directive not defined: \'`UpdateScreen\'\n after_page_state <= `UpdateScreen;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:141: syntax error, unexpected <=, expecting IDENTIFIER\n t_index <= t_index + 1;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:142: Define or directive not defined: \'`UpdateScreen\'\n after_char_state <= `UpdateScreen;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:146: Define or directive not defined: \'`ClearDC\'\n `ClearDC: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:148: Define or directive not defined: \'`SetPage\'\n current_state <= `SetPage;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:150: Define or directive not defined: \'`SetPage\'\n `SetPage: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:152: Define or directive not defined: \'`Transition1_e\'\n current_state <= `Transition1_e;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:153: Define or directive not defined: \'`PageNum\'\n after_state <= `PageNum;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:155: Define or directive not defined: \'`PageNum\'\n `PageNum: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:157: Define or directive not defined: \'`Transition1_e\'\n current_state <= `Transition1_e;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:158: Define or directive not defined: \'`LeftColumn1\'\n after_state <= `LeftColumn1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:160: Define or directive not defined: \'`LeftColumn1\'\n `LeftColumn1: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:162: Define or directive not defined: \'`Transition1_e\'\n current_state <= `Transition1_e;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:163: Define or directive not defined: \'`LeftColumn2\'\n after_state <= `LeftColumn2;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:165: Define or directive not defined: \'`LeftColumn2\'\n `LeftColumn2: begin\n ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 3,227 | module | module oled_exam(
clk,
rst,
en,
cs,
sdo,
sclk,
dc,
fin,
char_data
);
input wire clk, rst, en;
output wire cs, sdo, sclk, dc, fin;
input wire [64*8-1:0] char_data;
reg t_dc;
reg [4:0] current_state, after_state, after_page_state,
after_char_state, after_update_state;
reg spi_en, delay_en;
reg [7:0] spi_data;
reg [7:0] current_screen [0:63];
reg [11:0] delay_ms;
reg [7:0] t_char;
reg [10:0] t_addr;
wire [7:0] dout;
reg [1:0] t_page;
reg [3:0] t_index;
wire spi_fin, delay_fin;
integer i;
assign dc = t_dc;
assign fin = (current_state == `Wait1_e) ? 1 : 0;
spi_ctrl sctrl(
.clk(clk),
.rst(rst),
.spi_en(spi_en),
.spi_data(spi_data),
.cs(cs),
.sdo(sdo),
.sclk(sclk),
.spi_fin(spi_fin)
);
delay_gen dgen(
.clk(clk),
.rst(rst),
.delay_ms(delay_ms),
.delay_en(delay_en),
.delay_fin(delay_fin)
);
char_rom crom(
.rst(rst),
.addr(t_addr),
.dout(dout)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Idle_e;
after_state <= `Idle_e;
after_page_state <= `Idle_e;
after_char_state <= `Idle_e;
after_update_state <= `Idle_e;
spi_data <= 8'b0;
delay_ms <= 12'b0;
t_char <= 8'b0;
t_addr <= 11'b0;
t_page <= 2'b0;
t_index <= 4'b0;
t_dc <= 0;
spi_en <= 0;
delay_en <= 0;
end else begin
case(current_state)
`Idle_e: begin
if(en) begin
current_state <= `ClearDC;
after_page_state <= `STR1;
t_page <= 2'b0;
t_index <= 4'b0;
end
end
`STR1: begin
current_state <= `UpdateScreen;
after_update_state <= `Wait1_e;
for(i=63;i>=0;i=i-1) begin
current_screen[63-i] <= char_data[(8*i) +: 7];
end
end
`Wait1_e: begin
if(!en) begin
current_state <= `Idle_e;
end else begin
delay_ms <= 12'b000001100100;
current_state <= `Transition3_e;
after_state <= `STR1;
end
end
`UpdateScreen: begin
t_char <= current_screen[t_page*16+t_index];
current_state <= `SendChar1;
if(t_index == 4'b1111) begin
t_index <= 0;
t_page <= t_page + 1;
after_char_state <= `ClearDC;
if(t_page == 2'b11) begin
after_page_state <= after_update_state;
end else begin
after_page_state <= `UpdateScreen;
end
end else begin
t_index <= t_index + 1;
after_char_state <= `UpdateScreen;
end
end
`ClearDC: begin
t_dc <= 0;
current_state <= `SetPage;
end
`SetPage: begin
spi_data <= 8'b00100010;
current_state <= `Transition1_e;
after_state <= `PageNum;
end
`PageNum: begin
spi_data <= {6'b000000, t_page};
current_state <= `Transition1_e;
after_state <= `LeftColumn1;
end
`LeftColumn1: begin
spi_data <= 8'b00000000;
current_state <= `Transition1_e;
after_state <= `LeftColumn2;
end
`LeftColumn2: begin
spi_data <= 8'b00010000;
current_state <= `Transition1_e;
after_state <= `SetDC;
end
`SetDC: begin
t_dc <= 1;
current_state <= after_page_state;
end
`SendChar1: begin
t_addr <= {t_char, 3'b000};
current_state <= `ReadMem;
after_state <= `SendChar2;
end
`SendChar2: begin
t_addr <= {t_char, 3'b001};
current_state <= `ReadMem;
after_state <= `SendChar3;
end
`SendChar3: begin
t_addr <= {t_char, 3'b010};
current_state <= `ReadMem;
after_state <= `SendChar4;
end
`SendChar4: begin
t_addr <= {t_char, 3'b011};
current_state <= `ReadMem;
after_state <= `SendChar5;
end
`SendChar5: begin
t_addr <= {t_char, 3'b100};
current_state <= `ReadMem;
after_state <= `SendChar6;
end
`SendChar6: begin
t_addr <= {t_char, 3'b101};
current_state <= `ReadMem;
after_state <= `SendChar7;
end
`SendChar7: begin
t_addr <= {t_char, 3'b110};
current_state <= `ReadMem;
after_state <= `SendChar8;
end
`SendChar8: begin
t_addr <= {t_char, 3'b111};
current_state <= `ReadMem;
after_state <= after_char_state;
end
`ReadMem: begin
current_state <= `ReadMem2;
end
`ReadMem2: begin
spi_data <= dout;
current_state <= `Transition1_e;
end
`Transition1_e: begin
spi_en <= 1;
current_state <= `Transition2_e;
end
`Transition2_e: begin
if(spi_fin) begin
current_state <= `Transition5_e;
end
end
`Transition3_e: begin
delay_en <= 1;
current_state <= `Transition4_e;
end
`Transition4_e: begin
if(delay_fin) begin
current_state <= `Transition5_e;
end
end
`Transition5_e: begin
spi_en <= 0;
delay_en <= 0;
current_state <= after_state;
end
default: begin
current_state <= `Idle_e;
end
endcase
end
end
endmodule | module oled_exam(
clk,
rst,
en,
cs,
sdo,
sclk,
dc,
fin,
char_data
); |
input wire clk, rst, en;
output wire cs, sdo, sclk, dc, fin;
input wire [64*8-1:0] char_data;
reg t_dc;
reg [4:0] current_state, after_state, after_page_state,
after_char_state, after_update_state;
reg spi_en, delay_en;
reg [7:0] spi_data;
reg [7:0] current_screen [0:63];
reg [11:0] delay_ms;
reg [7:0] t_char;
reg [10:0] t_addr;
wire [7:0] dout;
reg [1:0] t_page;
reg [3:0] t_index;
wire spi_fin, delay_fin;
integer i;
assign dc = t_dc;
assign fin = (current_state == `Wait1_e) ? 1 : 0;
spi_ctrl sctrl(
.clk(clk),
.rst(rst),
.spi_en(spi_en),
.spi_data(spi_data),
.cs(cs),
.sdo(sdo),
.sclk(sclk),
.spi_fin(spi_fin)
);
delay_gen dgen(
.clk(clk),
.rst(rst),
.delay_ms(delay_ms),
.delay_en(delay_en),
.delay_fin(delay_fin)
);
char_rom crom(
.rst(rst),
.addr(t_addr),
.dout(dout)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Idle_e;
after_state <= `Idle_e;
after_page_state <= `Idle_e;
after_char_state <= `Idle_e;
after_update_state <= `Idle_e;
spi_data <= 8'b0;
delay_ms <= 12'b0;
t_char <= 8'b0;
t_addr <= 11'b0;
t_page <= 2'b0;
t_index <= 4'b0;
t_dc <= 0;
spi_en <= 0;
delay_en <= 0;
end else begin
case(current_state)
`Idle_e: begin
if(en) begin
current_state <= `ClearDC;
after_page_state <= `STR1;
t_page <= 2'b0;
t_index <= 4'b0;
end
end
`STR1: begin
current_state <= `UpdateScreen;
after_update_state <= `Wait1_e;
for(i=63;i>=0;i=i-1) begin
current_screen[63-i] <= char_data[(8*i) +: 7];
end
end
`Wait1_e: begin
if(!en) begin
current_state <= `Idle_e;
end else begin
delay_ms <= 12'b000001100100;
current_state <= `Transition3_e;
after_state <= `STR1;
end
end
`UpdateScreen: begin
t_char <= current_screen[t_page*16+t_index];
current_state <= `SendChar1;
if(t_index == 4'b1111) begin
t_index <= 0;
t_page <= t_page + 1;
after_char_state <= `ClearDC;
if(t_page == 2'b11) begin
after_page_state <= after_update_state;
end else begin
after_page_state <= `UpdateScreen;
end
end else begin
t_index <= t_index + 1;
after_char_state <= `UpdateScreen;
end
end
`ClearDC: begin
t_dc <= 0;
current_state <= `SetPage;
end
`SetPage: begin
spi_data <= 8'b00100010;
current_state <= `Transition1_e;
after_state <= `PageNum;
end
`PageNum: begin
spi_data <= {6'b000000, t_page};
current_state <= `Transition1_e;
after_state <= `LeftColumn1;
end
`LeftColumn1: begin
spi_data <= 8'b00000000;
current_state <= `Transition1_e;
after_state <= `LeftColumn2;
end
`LeftColumn2: begin
spi_data <= 8'b00010000;
current_state <= `Transition1_e;
after_state <= `SetDC;
end
`SetDC: begin
t_dc <= 1;
current_state <= after_page_state;
end
`SendChar1: begin
t_addr <= {t_char, 3'b000};
current_state <= `ReadMem;
after_state <= `SendChar2;
end
`SendChar2: begin
t_addr <= {t_char, 3'b001};
current_state <= `ReadMem;
after_state <= `SendChar3;
end
`SendChar3: begin
t_addr <= {t_char, 3'b010};
current_state <= `ReadMem;
after_state <= `SendChar4;
end
`SendChar4: begin
t_addr <= {t_char, 3'b011};
current_state <= `ReadMem;
after_state <= `SendChar5;
end
`SendChar5: begin
t_addr <= {t_char, 3'b100};
current_state <= `ReadMem;
after_state <= `SendChar6;
end
`SendChar6: begin
t_addr <= {t_char, 3'b101};
current_state <= `ReadMem;
after_state <= `SendChar7;
end
`SendChar7: begin
t_addr <= {t_char, 3'b110};
current_state <= `ReadMem;
after_state <= `SendChar8;
end
`SendChar8: begin
t_addr <= {t_char, 3'b111};
current_state <= `ReadMem;
after_state <= after_char_state;
end
`ReadMem: begin
current_state <= `ReadMem2;
end
`ReadMem2: begin
spi_data <= dout;
current_state <= `Transition1_e;
end
`Transition1_e: begin
spi_en <= 1;
current_state <= `Transition2_e;
end
`Transition2_e: begin
if(spi_fin) begin
current_state <= `Transition5_e;
end
end
`Transition3_e: begin
delay_en <= 1;
current_state <= `Transition4_e;
end
`Transition4_e: begin
if(delay_fin) begin
current_state <= `Transition5_e;
end
end
`Transition5_e: begin
spi_en <= 0;
delay_en <= 0;
current_state <= after_state;
end
default: begin
current_state <= `Idle_e;
end
endcase
end
end
endmodule | 0 |
4,837 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v | 111,502,990 | oled_init.v | v | 240 | 83 | [] | [] | [] | [(186, 401)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:44: Define or directive not defined: \'`DispContrast1\'\n wire [11:0] delay_ms = (after_state == `DispContrast1) ?\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:44: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [11:0] delay_ms = (after_state == `DispContrast1) ?\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:76: Define or directive not defined: \'`Idle\'\n current_state <= `Idle;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Idle;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:77: Define or directive not defined: \'`Idle\'\n after_state <= `Idle;\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `Idle;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:88: Define or directive not defined: \'`Idle\'\n `Idle: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:88: syntax error, unexpected \':\', expecting endcase\n `Idle: begin\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:91: Define or directive not defined: \'`VddOn\'\n current_state <= `VddOn;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `VddOn;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:94: Define or directive not defined: \'`VddOn\'\n `VddOn: begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `VddOn: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:96: Define or directive not defined: \'`Wait1\'\n current_state <= `Wait1;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Wait1;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:98: Define or directive not defined: \'`Wait1\'\n `Wait1: begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:98: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Wait1: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:99: Define or directive not defined: \'`Transition3\'\n current_state <= `Transition3;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:100: Define or directive not defined: \'`DispOff\'\n after_state <= `DispOff;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `DispOff;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:102: Define or directive not defined: \'`DispOff\'\n `DispOff: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `DispOff: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:104: Define or directive not defined: \'`Transition1\'\n current_state <= `Transition1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Transition1;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:105: Define or directive not defined: \'`ResetOn\'\n after_state <= `ResetOn;\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `ResetOn;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:107: Define or directive not defined: \'`ResetOn\'\n `ResetOn: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:107: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ResetOn: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:109: Define or directive not defined: \'`Wait2\'\n current_state <= `Wait2;\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Wait2;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:111: Define or directive not defined: \'`Wait2\'\n `Wait2: begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:111: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `Wait2: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:112: Define or directive not defined: \'`Transition3\'\n current_state <= `Transition3;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:113: Define or directive not defined: \'`ResetOff\'\n after_state <= `ResetOff;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `ResetOff;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:115: Define or directive not defined: \'`ResetOff\'\n `ResetOff: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:115: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ResetOff: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:117: Define or directive not defined: \'`Transition3\'\n current_state <= `Transition3;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Transition3;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:118: Define or directive not defined: \'`ChargePump1\'\n after_state <= `ChargePump1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:118: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `ChargePump1;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:120: Define or directive not defined: \'`ChargePump1\'\n `ChargePump1: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:120: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ChargePump1: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:122: Define or directive not defined: \'`Transition1\'\n current_state <= `Transition1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `Transition1;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:123: Define or directive not defined: \'`ChargePump2\'\n after_state <= `ChargePump2;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n after_state <= `ChargePump2;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:125: Define or directive not defined: \'`ChargePump2\'\n `ChargePump2: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_init.v:125: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ChargePump2: begin\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 3,228 | module | module oled_init(
clk,
rst,
en,
cs,
sdo,
sclk,
dc,
res,
vbat,
vdd,
fin
);
input wire clk, rst, en;
output wire cs, dc, res, sclk, sdo, vbat, vdd, fin;
reg t_dc, t_res, t_vbat, t_vdd, t_fin;
reg [4:0] current_state, after_state;
reg spi_en, delay_en;
reg [7:0] spi_data;
wire [11:0] delay_ms = (after_state == `DispContrast1) ?
12'b000001100100 : 12'b000000000001;
wire spi_fin, delay_fin;
assign dc = t_dc;
assign res = t_res;
assign vbat = t_vbat;
assign vdd = t_vdd;
assign fin = t_fin;
spi_ctrl sctrl(
.clk(clk),
.rst(rst),
.spi_en(spi_en),
.spi_data(spi_data),
.cs(cs),
.sdo(sdo),
.sclk(sclk),
.spi_fin(spi_fin)
);
delay_gen dgen(
.clk(clk),
.rst(rst),
.delay_ms(delay_ms),
.delay_en(delay_en),
.delay_fin(delay_fin)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Idle;
after_state <= `Idle;
spi_data <= 8'b0;
t_dc <= 0;
t_res <= 0;
t_vbat <= 1;
t_vdd <= 1;
t_fin <= 0;
spi_en <= 0;
delay_en <= 0;
end else begin
case(current_state)
`Idle: begin
if(en) begin
t_res <= 1;
current_state <= `VddOn;
end
end
`VddOn: begin
t_vdd <= 0;
current_state <= `Wait1;
end
`Wait1: begin
current_state <= `Transition3;
after_state <= `DispOff;
end
`DispOff: begin
spi_data <= 8'b10101110;
current_state <= `Transition1;
after_state <= `ResetOn;
end
`ResetOn: begin
t_res <= 0;
current_state <= `Wait2;
end
`Wait2: begin
current_state <= `Transition3;
after_state <= `ResetOff;
end
`ResetOff: begin
t_res <= 1;
current_state <= `Transition3;
after_state <= `ChargePump1;
end
`ChargePump1: begin
spi_data <= 8'b10001101;
current_state <= `Transition1;
after_state <= `ChargePump2;
end
`ChargePump2: begin
spi_data <= 8'b00010100;
current_state <= `Transition1;
after_state <= `PreCharge1;
end
`PreCharge1: begin
spi_data <= 8'b11011001;
current_state <= `Transition1;
after_state <= `PreCharge2;
end
`PreCharge2: begin
spi_data <= 8'b11110001;
current_state <= `Transition1;
after_state <= `VbatOn;
end
`VbatOn: begin
t_vbat <= 0;
current_state <= `Wait3;
end
`Wait3: begin
current_state <= `Transition3;
after_state <= `DispContrast1;
end
`DispContrast1: begin
spi_data <= 8'b10000001;
current_state <= `Transition1;
after_state <= `InvertDisp1;
end
`DispContrast2: begin
spi_data <= 8'b00001111;
current_state <= `Transition1;
after_state <= `InvertDisp1;
end
`InvertDisp1: begin
spi_data <= 8'b10100000;
current_state <= `Transition1;
after_state <= `InvertDisp2;
end
`InvertDisp2: begin
spi_data <= 8'b11000000;
current_state <= `Transition1;
after_state <= `ComConfig1;
end
`ComConfig1: begin
spi_data <= 8'b11011010;
current_state <= `Transition1;
after_state <= `ComConfig2;
end
`ComConfig2: begin
spi_data <= 8'b00000000;
current_state <= `Transition1;
after_state <= `ComConfig3;
end
`ComConfig3: begin
spi_data <= 8'b11000000;
current_state <= `Transition1;
after_state <= `ComConfig4;
end
`ComConfig4: begin
spi_data <= 8'b00100000;
current_state <= `Transition1;
after_state <= `ComConfig5;
end
`ComConfig5: begin
spi_data <= 8'b00000000;
current_state <= `Transition1;
after_state <= `DispOn;
end
`DispOn: begin
spi_data <= 8'b10101111;
current_state <= `Transition1;
after_state <= `Done;
end
`Done: begin
if(!en) begin
t_fin <= 0;
current_state <= `Idle;
end else begin
t_fin <= 1;
end
end
`Transition1: begin
spi_en <= 1;
current_state <= `Transition2;
end
`Transition2: begin
if(spi_fin) begin
current_state <= `Transition5;
end
end
`Transition3: begin
delay_en <= 1;
current_state <= `Transition4;
end
`Transition4: begin
if(delay_fin) begin
current_state <= `Transition5;
end
end
`Transition5: begin
spi_en <= 0;
delay_en <= 0;
current_state <= after_state;
end
default: begin
current_state <= `Idle;
end
endcase
end
end
endmodule | module oled_init(
clk,
rst,
en,
cs,
sdo,
sclk,
dc,
res,
vbat,
vdd,
fin
); |
input wire clk, rst, en;
output wire cs, dc, res, sclk, sdo, vbat, vdd, fin;
reg t_dc, t_res, t_vbat, t_vdd, t_fin;
reg [4:0] current_state, after_state;
reg spi_en, delay_en;
reg [7:0] spi_data;
wire [11:0] delay_ms = (after_state == `DispContrast1) ?
12'b000001100100 : 12'b000000000001;
wire spi_fin, delay_fin;
assign dc = t_dc;
assign res = t_res;
assign vbat = t_vbat;
assign vdd = t_vdd;
assign fin = t_fin;
spi_ctrl sctrl(
.clk(clk),
.rst(rst),
.spi_en(spi_en),
.spi_data(spi_data),
.cs(cs),
.sdo(sdo),
.sclk(sclk),
.spi_fin(spi_fin)
);
delay_gen dgen(
.clk(clk),
.rst(rst),
.delay_ms(delay_ms),
.delay_en(delay_en),
.delay_fin(delay_fin)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `Idle;
after_state <= `Idle;
spi_data <= 8'b0;
t_dc <= 0;
t_res <= 0;
t_vbat <= 1;
t_vdd <= 1;
t_fin <= 0;
spi_en <= 0;
delay_en <= 0;
end else begin
case(current_state)
`Idle: begin
if(en) begin
t_res <= 1;
current_state <= `VddOn;
end
end
`VddOn: begin
t_vdd <= 0;
current_state <= `Wait1;
end
`Wait1: begin
current_state <= `Transition3;
after_state <= `DispOff;
end
`DispOff: begin
spi_data <= 8'b10101110;
current_state <= `Transition1;
after_state <= `ResetOn;
end
`ResetOn: begin
t_res <= 0;
current_state <= `Wait2;
end
`Wait2: begin
current_state <= `Transition3;
after_state <= `ResetOff;
end
`ResetOff: begin
t_res <= 1;
current_state <= `Transition3;
after_state <= `ChargePump1;
end
`ChargePump1: begin
spi_data <= 8'b10001101;
current_state <= `Transition1;
after_state <= `ChargePump2;
end
`ChargePump2: begin
spi_data <= 8'b00010100;
current_state <= `Transition1;
after_state <= `PreCharge1;
end
`PreCharge1: begin
spi_data <= 8'b11011001;
current_state <= `Transition1;
after_state <= `PreCharge2;
end
`PreCharge2: begin
spi_data <= 8'b11110001;
current_state <= `Transition1;
after_state <= `VbatOn;
end
`VbatOn: begin
t_vbat <= 0;
current_state <= `Wait3;
end
`Wait3: begin
current_state <= `Transition3;
after_state <= `DispContrast1;
end
`DispContrast1: begin
spi_data <= 8'b10000001;
current_state <= `Transition1;
after_state <= `InvertDisp1;
end
`DispContrast2: begin
spi_data <= 8'b00001111;
current_state <= `Transition1;
after_state <= `InvertDisp1;
end
`InvertDisp1: begin
spi_data <= 8'b10100000;
current_state <= `Transition1;
after_state <= `InvertDisp2;
end
`InvertDisp2: begin
spi_data <= 8'b11000000;
current_state <= `Transition1;
after_state <= `ComConfig1;
end
`ComConfig1: begin
spi_data <= 8'b11011010;
current_state <= `Transition1;
after_state <= `ComConfig2;
end
`ComConfig2: begin
spi_data <= 8'b00000000;
current_state <= `Transition1;
after_state <= `ComConfig3;
end
`ComConfig3: begin
spi_data <= 8'b11000000;
current_state <= `Transition1;
after_state <= `ComConfig4;
end
`ComConfig4: begin
spi_data <= 8'b00100000;
current_state <= `Transition1;
after_state <= `ComConfig5;
end
`ComConfig5: begin
spi_data <= 8'b00000000;
current_state <= `Transition1;
after_state <= `DispOn;
end
`DispOn: begin
spi_data <= 8'b10101111;
current_state <= `Transition1;
after_state <= `Done;
end
`Done: begin
if(!en) begin
t_fin <= 0;
current_state <= `Idle;
end else begin
t_fin <= 1;
end
end
`Transition1: begin
spi_en <= 1;
current_state <= `Transition2;
end
`Transition2: begin
if(spi_fin) begin
current_state <= `Transition5;
end
end
`Transition3: begin
delay_en <= 1;
current_state <= `Transition4;
end
`Transition4: begin
if(delay_fin) begin
current_state <= `Transition5;
end
end
`Transition5: begin
spi_en <= 0;
delay_en <= 0;
current_state <= after_state;
end
default: begin
current_state <= `Idle;
end
endcase
end
end
endmodule | 0 |
4,838 | data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v | 111,502,990 | spi_ctrl.v | v | 127 | 83 | [] | [] | [] | [(186, 288)] | null | null | 1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n char_def.vh\n char_def.vh.v\n char_def.vh.sv\n obj_dir/char_def.vh\n obj_dir/char_def.vh.v\n obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:48: Define or directive not defined: \'`spi_idle\'\n assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:48: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;\n ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:49: Define or directive not defined: \'`spi_done\'\n assign spi_fin = (current_state == `spi_done) ? 1 : 0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign spi_fin = (current_state == `spi_done) ? 1 : 0;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:53: Define or directive not defined: \'`spi_idle\'\n current_state <= `spi_idle;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n current_state <= `spi_idle;\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:56: Define or directive not defined: \'`spi_idle\'\n `spi_idle: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:56: syntax error, unexpected \':\', expecting endcase\n `spi_idle: begin\n ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:58: Define or directive not defined: \'`spi_send\'\n current_state <= `spi_send;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:61: Define or directive not defined: \'`spi_send\'\n `spi_send: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:61: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `spi_send: begin\n ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:63: Define or directive not defined: \'`spi_hold1\'\n current_state <= `spi_hold1;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:66: Define or directive not defined: \'`spi_hold1\'\n `spi_hold1: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:67: Define or directive not defined: \'`spi_hold2\'\n current_state <= `spi_hold2;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:69: Define or directive not defined: \'`spi_hold2\'\n `spi_hold2: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:70: Define or directive not defined: \'`spi_hold3\'\n current_state <= `spi_hold3;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:72: Define or directive not defined: \'`spi_hold3\'\n `spi_hold3: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:73: Define or directive not defined: \'`spi_hold4\'\n current_state <= `spi_hold4;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:75: Define or directive not defined: \'`spi_hold4\'\n `spi_hold4: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:76: Define or directive not defined: \'`spi_done\'\n current_state <= `spi_done;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:78: Define or directive not defined: \'`spi_done\'\n `spi_done: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:80: Define or directive not defined: \'`spi_idle\'\n current_state <= `spi_idle;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:84: Define or directive not defined: \'`spi_idle\'\n current_state <= `spi_idle;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:94: Define or directive not defined: \'`spi_send\'\n else if(current_state == `spi_send) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:108: Define or directive not defined: \'`spi_idle\'\n else if(current_state == `spi_idle) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:113: Define or directive not defined: \'`spi_send\'\n else if(current_state == `spi_send) begin\n ^~~~~~~~~\n%Error: Cannot continue\n' | 3,229 | module | module spi_ctrl(
clk,
rst,
spi_en,
spi_data,
cs,
sdo,
sclk,
spi_fin
);
input clk, rst, spi_en;
input [7:0] spi_data;
output cs, sdo, sclk, spi_fin;
reg t_sdo, falling;
reg [2:0] current_state;
reg [7:0] shift_register;
reg [3:0] shift_counter;
reg [4:0] counter;
wire clk_divided = ~counter[4];
assign sclk = clk_divided;
assign sdo = t_sdo;
assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;
assign spi_fin = (current_state == `spi_done) ? 1 : 0;
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `spi_idle;
end else begin
case(current_state)
`spi_idle: begin
if(spi_en) begin
current_state <= `spi_send;
end
end
`spi_send: begin
if(shift_counter == 4'b1000 && falling == 0) begin
current_state <= `spi_hold1;
end
end
`spi_hold1: begin
current_state <= `spi_hold2;
end
`spi_hold2: begin
current_state <= `spi_hold3;
end
`spi_hold3: begin
current_state <= `spi_hold4;
end
`spi_hold4: begin
current_state <= `spi_done;
end
`spi_done: begin
if(spi_en == 0) begin
current_state <= `spi_idle;
end
end
default: begin
current_state <= `spi_idle;
end
endcase
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
counter <= 5'b0;
end
else if(current_state == `spi_send) begin
counter <= counter + 1;
end
else begin
counter <= 5'b0;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
falling <= 0;
shift_counter <= 4'b0;
shift_register <= 8'b0;
end
else if(current_state == `spi_idle) begin
shift_counter <= 4'b0;
shift_register <= spi_data;
t_sdo <= 1;
end
else if(current_state == `spi_send) begin
if(clk_divided == 0 && falling == 0) begin
falling <= 1;
t_sdo <= shift_register[7];
shift_register <= {shift_register[6:0], 1'b0};
shift_counter <= shift_counter + 1;
end
else if(clk_divided == 1) begin
falling <= 0;
end
end
end
endmodule | module spi_ctrl(
clk,
rst,
spi_en,
spi_data,
cs,
sdo,
sclk,
spi_fin
); |
input clk, rst, spi_en;
input [7:0] spi_data;
output cs, sdo, sclk, spi_fin;
reg t_sdo, falling;
reg [2:0] current_state;
reg [7:0] shift_register;
reg [3:0] shift_counter;
reg [4:0] counter;
wire clk_divided = ~counter[4];
assign sclk = clk_divided;
assign sdo = t_sdo;
assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;
assign spi_fin = (current_state == `spi_done) ? 1 : 0;
always @(posedge clk or posedge rst) begin
if(rst) begin
current_state <= `spi_idle;
end else begin
case(current_state)
`spi_idle: begin
if(spi_en) begin
current_state <= `spi_send;
end
end
`spi_send: begin
if(shift_counter == 4'b1000 && falling == 0) begin
current_state <= `spi_hold1;
end
end
`spi_hold1: begin
current_state <= `spi_hold2;
end
`spi_hold2: begin
current_state <= `spi_hold3;
end
`spi_hold3: begin
current_state <= `spi_hold4;
end
`spi_hold4: begin
current_state <= `spi_done;
end
`spi_done: begin
if(spi_en == 0) begin
current_state <= `spi_idle;
end
end
default: begin
current_state <= `spi_idle;
end
endcase
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
counter <= 5'b0;
end
else if(current_state == `spi_send) begin
counter <= counter + 1;
end
else begin
counter <= 5'b0;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
falling <= 0;
shift_counter <= 4'b0;
shift_register <= 8'b0;
end
else if(current_state == `spi_idle) begin
shift_counter <= 4'b0;
shift_register <= spi_data;
t_sdo <= 1;
end
else if(current_state == `spi_send) begin
if(clk_divided == 0 && falling == 0) begin
falling <= 1;
t_sdo <= shift_register[7];
shift_register <= {shift_register[6:0], 1'b0};
shift_counter <= shift_counter + 1;
end
else if(clk_divided == 1) begin
falling <= 0;
end
end
end
endmodule | 0 |
4,839 | data/full_repos/permissive/111901713/rtl/round.v | 111,901,713 | round.v | v | 82 | 76 | [] | [] | [] | [(18, 47), (50, 80)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111901713/rtl/round.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'one_round\'\nmodule one_round (clk, state_in, key, state_out);\n ^~~~~~~~~\n : ... Top module \'final_round\'\nmodule final_round (clk, state_in, key_in, state_out);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111901713/rtl/round.v:67: Cannot find file containing module: \'S4\'\n S4\n ^~\n ... Looked in:\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4.v\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4.sv\n S4\n S4.v\n S4.sv\n obj_dir/S4\n obj_dir/S4.v\n obj_dir/S4.sv\n%Error: data/full_repos/permissive/111901713/rtl/round.v:34: Cannot find file containing module: \'table_lookup\'\n table_lookup\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 3,234 | module | module one_round (clk, state_in, key, state_out);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, s0, p00, p01, p02, p03),
t1 (clk, s1, p10, p11, p12, p13),
t2 (clk, s2, p20, p21, p22, p23),
t3 (clk, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule | module one_round (clk, state_in, key, state_out); |
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, s0, p00, p01, p02, p03),
t1 (clk, s1, p10, p11, p12, p13),
t2 (clk, s2, p20, p21, p22, p23),
t3 (clk, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule | 10 |
4,840 | data/full_repos/permissive/111901713/rtl/round.v | 111,901,713 | round.v | v | 82 | 76 | [] | [] | [] | [(18, 47), (50, 80)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/111901713/rtl/round.v:50: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'one_round\'\nmodule one_round (clk, state_in, key, state_out);\n ^~~~~~~~~\n : ... Top module \'final_round\'\nmodule final_round (clk, state_in, key_in, state_out);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111901713/rtl/round.v:67: Cannot find file containing module: \'S4\'\n S4\n ^~\n ... Looked in:\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4.v\n data/full_repos/permissive/111901713/rtl,data/full_repos/permissive/111901713/S4.sv\n S4\n S4.v\n S4.sv\n obj_dir/S4\n obj_dir/S4.v\n obj_dir/S4.sv\n%Error: data/full_repos/permissive/111901713/rtl/round.v:34: Cannot find file containing module: \'table_lookup\'\n table_lookup\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 3,234 | module | module final_round (clk, state_in, key_in, state_out);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, s0, {p00, p01, p02, p03}),
S4_2 (clk, s1, {p10, p11, p12, p13}),
S4_3 (clk, s2, {p20, p21, p22, p23}),
S4_4 (clk, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule | module final_round (clk, state_in, key_in, state_out); |
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, s0, {p00, p01, p02, p03}),
S4_2 (clk, s1, {p10, p11, p12, p13}),
S4_3 (clk, s2, {p20, p21, p22, p23}),
S4_4 (clk, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule | 10 |
4,841 | data/full_repos/permissive/111901713/rtl/sbox.v | 111,901,713 | sbox.v | v | 179 | 176 | [] | [] | [] | [(19, 156), (159, 177)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/111901713/rtl/sbox.v:25: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire[0:7] s, x;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,235 | module | module S(
input clk,
input [7:0] in,
output reg [7:0] out
);
wire[0:7] s, x;
assign x = in;
always @ (posedge clk)
out <= s;
wire [21:0] y;
wire [67:0] t;
wire [17:0] z;
assign y[14] = x[3] ^ x[5];
assign y[13] = x[0] ^ x[6];
assign y[9] = x[0] ^ x[3];
assign y[8] = x[0] ^ x[5];
assign t[0] = x[1] ^ x[2];
assign y[1] = t[0] ^ x[7];
assign y[4] = y[1] ^ x[3];
assign y[12] = y[13] ^ y[14];
assign y[2] = y[1] ^ x[0];
assign y[5] = y[1] ^ x[6];
assign y[3] = y[5] ^ y[8];
assign t[1] = x[4] ^ y[12];
assign y[15] = t[1] ^ x[5];
assign y[20] = t[1] ^ x[1];
assign y[6] = y[15] ^ x[7];
assign y[10] = y[15] ^ t[0];
assign y[11] = y[20] ^ y[9];
assign y[7] = x[7] ^ y[11];
assign y[17] = y[10] ^ y[11];
assign y[19] = y[10] ^ y[8];
assign y[16] = t[0] ^ y[11];
assign y[21] = y[13] ^ y[16];
assign y[18] = x[0] ^ y[16];
assign t[2] = y[12] & y[15];
assign t[3] = y[3] & y[6];
assign t[4] = t[3] ^ t[2];
assign t[5] = y[4] & x[7];
assign t[6] = t[5] ^ t[2];
assign t[7] = y[13] & y[16];
assign t[8] = y[5] & y[1];
assign t[9] = t[8] ^ t[7];
assign t[10] = y[2] & y[7];
assign t[11] = t[10] ^ t[7];
assign t[12] = y[9] & y[11];
assign t[13] = y[14] & y[17];
assign t[14] = t[13] ^ t[12];
assign t[15] = y[8] & y[10];
assign t[16] = t[15] ^ t[12];
assign t[17] = t[4] ^ t[14];
assign t[18] = t[6] ^ t[16];
assign t[19] = t[9] ^ t[14];
assign t[20] = t[11] ^ t[16];
assign t[21] = t[17] ^ y[20];
assign t[22] = t[18] ^ y[19];
assign t[23] = t[19] ^ y[21];
assign t[24] = t[20] ^ y[18];
assign t[25] = t[21] ^ t[22];
assign t[26] = t[21] & t[23];
assign t[27] = t[24] ^ t[26];
assign t[28] = t[25] & t[27];
assign t[29] = t[28] ^ t[22];
assign t[30] = t[23] ^ t[24];
assign t[31] = t[22] ^ t[26];
assign t[32] = t[31] & t[30];
assign t[33] = t[32] ^ t[24];
assign t[34] = t[23] ^ t[33];
assign t[35] = t[27] ^ t[33];
assign t[36] = t[24] & t[35];
assign t[37] = t[36] ^ t[34];
assign t[38] = t[27] ^ t[36];
assign t[39] = t[29] & t[38];
assign t[40] = t[25] ^ t[39];
assign t[41] = t[40] ^ t[37];
assign t[42] = t[29] ^ t[33];
assign t[43] = t[29] ^ t[40];
assign t[44] = t[33] ^ t[37];
assign t[45] = t[42] ^ t[41];
assign z[0] = t[44] & y[15];
assign z[1] = t[37] & y[6];
assign z[2] = t[33] & x[7];
assign z[3] = t[43] & y[16];
assign z[4] = t[40] & y[1];
assign z[5] = t[29] & y[7];
assign z[6] = t[42] & y[11];
assign z[7] = t[45] & y[17];
assign z[8] = t[41] & y[10];
assign z[9] = t[44] & y[12];
assign z[10] = t[37] & y[3];
assign z[11] = t[33] & y[4];
assign z[12] = t[43] & y[13];
assign z[13] = t[40] & y[5];
assign z[14] = t[29] & y[2];
assign z[15] = t[42] & y[9];
assign z[16] = t[45] & y[14];
assign z[17] = t[41] & y[8];
assign t[46] = z[15] ^ z[16];
assign t[47] = z[10] ^ z[11];
assign t[48] = z[5] ^ z[13];
assign t[49] = z[9] ^ z[10];
assign t[50] = z[2] ^ z[12];
assign t[51] = z[2] ^ z[5];
assign t[52] = z[7] ^ z[8];
assign t[53] = z[0] ^ z[3];
assign t[54] = z[6] ^ z[7];
assign t[55] = z[16] ^ z[17];
assign t[56] = z[12] ^ t[48];
assign t[57] = t[50] ^ t[53];
assign t[58] = z[4] ^ t[46];
assign t[59] = z[3] ^ t[54];
assign t[60] = t[46] ^ t[57];
assign t[61] = z[14] ^ t[57];
assign t[62] = t[52] ^ t[58];
assign t[63] = t[49] ^ t[58];
assign t[64] = z[4] ^ t[59];
assign t[65] = t[61] ^ t[62];
assign t[66] = z[1] ^ t[63];
assign s[0] = t[59] ^ t[63];
assign s[6] = ~t[56 ] ^ t[62];
assign s[7] = ~t[48 ] ^ t[60];
assign t[67] = t[64] ^ t[65];
assign s[3] = t[53] ^ t[66];
assign s[4] = t[51] ^ t[66];
assign s[5] = t[47] ^ t[65];
assign s[1] = ~t[64 ] ^ s[3];
assign s[2] = ~t[55 ] ^ t[67];
endmodule | module S(
input clk,
input [7:0] in,
output reg [7:0] out
); |
wire[0:7] s, x;
assign x = in;
always @ (posedge clk)
out <= s;
wire [21:0] y;
wire [67:0] t;
wire [17:0] z;
assign y[14] = x[3] ^ x[5];
assign y[13] = x[0] ^ x[6];
assign y[9] = x[0] ^ x[3];
assign y[8] = x[0] ^ x[5];
assign t[0] = x[1] ^ x[2];
assign y[1] = t[0] ^ x[7];
assign y[4] = y[1] ^ x[3];
assign y[12] = y[13] ^ y[14];
assign y[2] = y[1] ^ x[0];
assign y[5] = y[1] ^ x[6];
assign y[3] = y[5] ^ y[8];
assign t[1] = x[4] ^ y[12];
assign y[15] = t[1] ^ x[5];
assign y[20] = t[1] ^ x[1];
assign y[6] = y[15] ^ x[7];
assign y[10] = y[15] ^ t[0];
assign y[11] = y[20] ^ y[9];
assign y[7] = x[7] ^ y[11];
assign y[17] = y[10] ^ y[11];
assign y[19] = y[10] ^ y[8];
assign y[16] = t[0] ^ y[11];
assign y[21] = y[13] ^ y[16];
assign y[18] = x[0] ^ y[16];
assign t[2] = y[12] & y[15];
assign t[3] = y[3] & y[6];
assign t[4] = t[3] ^ t[2];
assign t[5] = y[4] & x[7];
assign t[6] = t[5] ^ t[2];
assign t[7] = y[13] & y[16];
assign t[8] = y[5] & y[1];
assign t[9] = t[8] ^ t[7];
assign t[10] = y[2] & y[7];
assign t[11] = t[10] ^ t[7];
assign t[12] = y[9] & y[11];
assign t[13] = y[14] & y[17];
assign t[14] = t[13] ^ t[12];
assign t[15] = y[8] & y[10];
assign t[16] = t[15] ^ t[12];
assign t[17] = t[4] ^ t[14];
assign t[18] = t[6] ^ t[16];
assign t[19] = t[9] ^ t[14];
assign t[20] = t[11] ^ t[16];
assign t[21] = t[17] ^ y[20];
assign t[22] = t[18] ^ y[19];
assign t[23] = t[19] ^ y[21];
assign t[24] = t[20] ^ y[18];
assign t[25] = t[21] ^ t[22];
assign t[26] = t[21] & t[23];
assign t[27] = t[24] ^ t[26];
assign t[28] = t[25] & t[27];
assign t[29] = t[28] ^ t[22];
assign t[30] = t[23] ^ t[24];
assign t[31] = t[22] ^ t[26];
assign t[32] = t[31] & t[30];
assign t[33] = t[32] ^ t[24];
assign t[34] = t[23] ^ t[33];
assign t[35] = t[27] ^ t[33];
assign t[36] = t[24] & t[35];
assign t[37] = t[36] ^ t[34];
assign t[38] = t[27] ^ t[36];
assign t[39] = t[29] & t[38];
assign t[40] = t[25] ^ t[39];
assign t[41] = t[40] ^ t[37];
assign t[42] = t[29] ^ t[33];
assign t[43] = t[29] ^ t[40];
assign t[44] = t[33] ^ t[37];
assign t[45] = t[42] ^ t[41];
assign z[0] = t[44] & y[15];
assign z[1] = t[37] & y[6];
assign z[2] = t[33] & x[7];
assign z[3] = t[43] & y[16];
assign z[4] = t[40] & y[1];
assign z[5] = t[29] & y[7];
assign z[6] = t[42] & y[11];
assign z[7] = t[45] & y[17];
assign z[8] = t[41] & y[10];
assign z[9] = t[44] & y[12];
assign z[10] = t[37] & y[3];
assign z[11] = t[33] & y[4];
assign z[12] = t[43] & y[13];
assign z[13] = t[40] & y[5];
assign z[14] = t[29] & y[2];
assign z[15] = t[42] & y[9];
assign z[16] = t[45] & y[14];
assign z[17] = t[41] & y[8];
assign t[46] = z[15] ^ z[16];
assign t[47] = z[10] ^ z[11];
assign t[48] = z[5] ^ z[13];
assign t[49] = z[9] ^ z[10];
assign t[50] = z[2] ^ z[12];
assign t[51] = z[2] ^ z[5];
assign t[52] = z[7] ^ z[8];
assign t[53] = z[0] ^ z[3];
assign t[54] = z[6] ^ z[7];
assign t[55] = z[16] ^ z[17];
assign t[56] = z[12] ^ t[48];
assign t[57] = t[50] ^ t[53];
assign t[58] = z[4] ^ t[46];
assign t[59] = z[3] ^ t[54];
assign t[60] = t[46] ^ t[57];
assign t[61] = z[14] ^ t[57];
assign t[62] = t[52] ^ t[58];
assign t[63] = t[49] ^ t[58];
assign t[64] = z[4] ^ t[59];
assign t[65] = t[61] ^ t[62];
assign t[66] = z[1] ^ t[63];
assign s[0] = t[59] ^ t[63];
assign s[6] = ~t[56 ] ^ t[62];
assign s[7] = ~t[48 ] ^ t[60];
assign t[67] = t[64] ^ t[65];
assign s[3] = t[53] ^ t[66];
assign s[4] = t[51] ^ t[66];
assign s[5] = t[47] ^ t[65];
assign s[1] = ~t[64 ] ^ s[3];
assign s[2] = ~t[55 ] ^ t[67];
endmodule | 10 |
4,842 | data/full_repos/permissive/111901713/rtl/sbox.v | 111,901,713 | sbox.v | v | 179 | 176 | [] | [] | [] | [(19, 156), (159, 177)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/111901713/rtl/sbox.v:25: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire[0:7] s, x;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 3,235 | module | module xS (clk, in, out);
input clk;
input [7:0] in;
output [7:0] out;
wire [7:0] out_2;
S S_(
.clk(clk),
.in(in),
.out(out_2)
);
wire dummy;
assign {dummy, out} = out_2[7]? {out_2, 1'b0}^9'h11b : {out_2, 1'b0};
endmodule | module xS (clk, in, out); |
input clk;
input [7:0] in;
output [7:0] out;
wire [7:0] out_2;
S S_(
.clk(clk),
.in(in),
.out(out_2)
);
wire dummy;
assign {dummy, out} = out_2[7]? {out_2, 1'b0}^9'h11b : {out_2, 1'b0};
endmodule | 10 |
4,843 | data/full_repos/permissive/111901713/testbench/test_aes_192.v | 111,901,713 | test_aes_192.v | v | 71 | 76 | [] | [] | [] | [(19, 69)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111901713/testbench/test_aes_192.v:48: syntax error, unexpected \'@\'\n @ (negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:49: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:58: Unsupported: Ignoring delay on this delayed statement.\n #230;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:68: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,238 | module | module test_aes_192;
reg clk;
reg [127:0] state;
reg [191:0] key;
wire [127:0] out;
aes_192 uut (
.clk(clk),
.state(state),
.key(key),
.out(out)
);
initial begin
clk = 0;
state = 0;
key = 0;
#100;
@ (negedge clk);
#2;
state = 128'h3243f6a8885a308d313198a2e0370734;
key = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
#10;
state = 128'h00112233445566778899aabbccddeeff;
key = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
#10;
state = 128'h0;
key = 192'h0;
#230;
if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
begin $display("E"); $finish; end
#10;
if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule | module test_aes_192; |
reg clk;
reg [127:0] state;
reg [191:0] key;
wire [127:0] out;
aes_192 uut (
.clk(clk),
.state(state),
.key(key),
.out(out)
);
initial begin
clk = 0;
state = 0;
key = 0;
#100;
@ (negedge clk);
#2;
state = 128'h3243f6a8885a308d313198a2e0370734;
key = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
#10;
state = 128'h00112233445566778899aabbccddeeff;
key = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
#10;
state = 128'h0;
key = 192'h0;
#230;
if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
begin $display("E"); $finish; end
#10;
if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule | 10 |
4,845 | data/full_repos/permissive/111901713/testbench/test_endian.v | 111,901,713 | test_endian.v | v | 33 | 76 | [] | [] | [] | [(19, 31)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_endian.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 3,240 | module | module test_endian;
reg [31:0] i;
initial begin
i = 32'h12345678;
#100;
$display("%h %h %h %h", i[31:24], i[23:16], i[15:8], i[7:0]);
$finish;
end
endmodule | module test_endian; |
reg [31:0] i;
initial begin
i = 32'h12345678;
#100;
$display("%h %h %h %h", i[31:24], i[23:16], i[15:8], i[7:0]);
$finish;
end
endmodule | 10 |
4,846 | data/full_repos/permissive/111973973/vgaCharGen.v | 111,973,973 | vgaCharGen.v | v | 153 | 93 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/111973973/vgaCharGen.v:58: Cannot find include file: 480.vh\n `include "480.vh" //Load the 640x480 parameters \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111973973,data/full_repos/permissive/111973973/480.vh\n data/full_repos/permissive/111973973,data/full_repos/permissive/111973973/480.vh.v\n data/full_repos/permissive/111973973,data/full_repos/permissive/111973973/480.vh.sv\n 480.vh\n 480.vh.v\n 480.vh.sv\n obj_dir/480.vh\n obj_dir/480.vh.v\n obj_dir/480.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 3,242 | module | module vgaCharGen(
input rst_p,
input pixel_clk,
input pixel_clkEn,
input cpu_clk,
input[15:0] cpu_addr,
input cpu_we,
input cpu_oe,
input[15:0] cpu_dataIn,
output[15:0] cpu_dataOut,
output vBlank,
output[3:0] VGA_R,
output[3:0] VGA_G,
output[3:0] VGA_B,
output VGA_HS,
output VGA_VS);
`include "480.vh"
parameter SINGLE_CYCLE_DESIGN = 1;
parameter FONT_PAGES = 1;
parameter FONT_H = 16;
parameter FONT_W = 8;
parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP;
parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP;
parameter H_WIDTH = $clog2(H_TOTAL);
parameter V_WIDTH = $clog2(V_TOTAL);
parameter TEXTADDR_WIDTH = $clog2(N_COL*N_ROW);
wire[H_WIDTH-1:0] horizPixelPos;
wire[V_WIDTH-1:0] vertPixelPos;
wire[15:0] curChar;
reg[7:0] charAttribute[0:1];
reg[TEXTADDR_WIDTH-1:0] effectiveCharAddr;
reg[2:0] glyphHorizCoord[0:1];
reg[3:0] glyphVertCoord[0:1];
wire glyphPixel;
wire[3:0] pixel_r;
wire[3:0] pixel_g;
wire[3:0] pixel_b;
integer i;
always @(posedge pixel_clk) begin
effectiveCharAddr <= (vertPixelPos>>4)*N_COL + (horizPixelPos>>3);
end
characterRAM #(.SINGLE_CYCLE_RAM(SINGLE_CYCLE_DESIGN),
.N_COL(N_COL), .N_ROW(N_ROW),
.TEXTADDR_WIDTH(TEXTADDR_WIDTH))
charRam1 (.cpu_clk(cpu_clk), .cpu_we(cpu_we), .cpu_addr(cpu_addr[TEXTADDR_WIDTH-1:0]),
.cpu_charIn(cpu_dataIn), .cpu_charOut(cpu_dataOut), .cpu_oe(cpu_oe),
.vid_clk(pixel_clk), .vid_addr(effectiveCharAddr),
.vid_charOut(curChar));
always @(posedge pixel_clk) begin
glyphHorizCoord[0] <= horizPixelPos[2:0];
glyphVertCoord[0] <= vertPixelPos[3:0];
glyphHorizCoord[1] <= glyphHorizCoord[0];
glyphVertCoord[1] <= glyphVertCoord[0];
end
fontROM #(.FONT_PAGES(FONT_PAGES), .FONT_H(FONT_H), .FONT_W(FONT_W))
fontRom1 (.clk(pixel_clk), .en(1'b1), .page(1'b0), .char(curChar[7:0]),
.horizPos(glyphHorizCoord[1]), .vertPos(glyphVertCoord[1]),
.pixel(glyphPixel));
always @(posedge pixel_clk) begin
charAttribute[0] <= curChar[15:8];
charAttribute[1] <= charAttribute[0];
end
attributeMap
attrib1 (.clk(pixel_clk), .rst_p(rst_p), .pixel(glyphPixel),
.attribute(charAttribute[1]), .pixel_r(pixel_r), .pixel_g(pixel_g),
.pixel_b(pixel_b));
vgaEngine #(.EXT_PIPELINE_DELAY(5), .H_ACTIVE(H_ACTIVE), .H_FP(H_FP),
.H_SYN(H_SYN), .H_BP(H_BP), .H_TOTAL(H_TOTAL),
.V_ACTIVE(V_ACTIVE), .V_FP(V_FP), .V_SYN(V_SYN), .V_BP(V_BP),
.V_TOTAL(V_TOTAL), .H_WIDTH(H_WIDTH), .V_WIDTH(V_WIDTH))
vga1 (.clk(pixel_clk), .rst_p(rst_p), .clk_en(pixel_clkEn),
.r(pixel_r), .g(pixel_g), .b(pixel_b), .vertBlanking(vBlank),
.horizPos(horizPixelPos), .vertPos(vertPixelPos), .v_sync(VGA_VS),
.h_sync(VGA_HS), .redOut(VGA_R), .greenOut(VGA_G), .blueOut(VGA_B));
endmodule | module vgaCharGen(
input rst_p,
input pixel_clk,
input pixel_clkEn,
input cpu_clk,
input[15:0] cpu_addr,
input cpu_we,
input cpu_oe,
input[15:0] cpu_dataIn,
output[15:0] cpu_dataOut,
output vBlank,
output[3:0] VGA_R,
output[3:0] VGA_G,
output[3:0] VGA_B,
output VGA_HS,
output VGA_VS); |
`include "480.vh"
parameter SINGLE_CYCLE_DESIGN = 1;
parameter FONT_PAGES = 1;
parameter FONT_H = 16;
parameter FONT_W = 8;
parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP;
parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP;
parameter H_WIDTH = $clog2(H_TOTAL);
parameter V_WIDTH = $clog2(V_TOTAL);
parameter TEXTADDR_WIDTH = $clog2(N_COL*N_ROW);
wire[H_WIDTH-1:0] horizPixelPos;
wire[V_WIDTH-1:0] vertPixelPos;
wire[15:0] curChar;
reg[7:0] charAttribute[0:1];
reg[TEXTADDR_WIDTH-1:0] effectiveCharAddr;
reg[2:0] glyphHorizCoord[0:1];
reg[3:0] glyphVertCoord[0:1];
wire glyphPixel;
wire[3:0] pixel_r;
wire[3:0] pixel_g;
wire[3:0] pixel_b;
integer i;
always @(posedge pixel_clk) begin
effectiveCharAddr <= (vertPixelPos>>4)*N_COL + (horizPixelPos>>3);
end
characterRAM #(.SINGLE_CYCLE_RAM(SINGLE_CYCLE_DESIGN),
.N_COL(N_COL), .N_ROW(N_ROW),
.TEXTADDR_WIDTH(TEXTADDR_WIDTH))
charRam1 (.cpu_clk(cpu_clk), .cpu_we(cpu_we), .cpu_addr(cpu_addr[TEXTADDR_WIDTH-1:0]),
.cpu_charIn(cpu_dataIn), .cpu_charOut(cpu_dataOut), .cpu_oe(cpu_oe),
.vid_clk(pixel_clk), .vid_addr(effectiveCharAddr),
.vid_charOut(curChar));
always @(posedge pixel_clk) begin
glyphHorizCoord[0] <= horizPixelPos[2:0];
glyphVertCoord[0] <= vertPixelPos[3:0];
glyphHorizCoord[1] <= glyphHorizCoord[0];
glyphVertCoord[1] <= glyphVertCoord[0];
end
fontROM #(.FONT_PAGES(FONT_PAGES), .FONT_H(FONT_H), .FONT_W(FONT_W))
fontRom1 (.clk(pixel_clk), .en(1'b1), .page(1'b0), .char(curChar[7:0]),
.horizPos(glyphHorizCoord[1]), .vertPos(glyphVertCoord[1]),
.pixel(glyphPixel));
always @(posedge pixel_clk) begin
charAttribute[0] <= curChar[15:8];
charAttribute[1] <= charAttribute[0];
end
attributeMap
attrib1 (.clk(pixel_clk), .rst_p(rst_p), .pixel(glyphPixel),
.attribute(charAttribute[1]), .pixel_r(pixel_r), .pixel_g(pixel_g),
.pixel_b(pixel_b));
vgaEngine #(.EXT_PIPELINE_DELAY(5), .H_ACTIVE(H_ACTIVE), .H_FP(H_FP),
.H_SYN(H_SYN), .H_BP(H_BP), .H_TOTAL(H_TOTAL),
.V_ACTIVE(V_ACTIVE), .V_FP(V_FP), .V_SYN(V_SYN), .V_BP(V_BP),
.V_TOTAL(V_TOTAL), .H_WIDTH(H_WIDTH), .V_WIDTH(V_WIDTH))
vga1 (.clk(pixel_clk), .rst_p(rst_p), .clk_en(pixel_clkEn),
.r(pixel_r), .g(pixel_g), .b(pixel_b), .vertBlanking(vBlank),
.horizPos(horizPixelPos), .vertPos(vertPixelPos), .v_sync(VGA_VS),
.h_sync(VGA_HS), .redOut(VGA_R), .greenOut(VGA_G), .blueOut(VGA_B));
endmodule | 5 |
4,847 | data/full_repos/permissive/111973973/vgacg/attributeMap.v | 111,973,973 | attributeMap.v | v | 67 | 81 | [] | [] | [] | null | line:59: before: "(" | data/verilator_xmls/1765b890-0c5b-49a9-ac90-e58772a98321.xml | null | 3,245 | module | module attributeMap(input clk,
input rst_p,
input pixel,
input[7:0] attribute,
output reg[3:0] pixel_r,
output reg[3:0] pixel_g,
output reg[3:0] pixel_b);
task setRGB;
input r, g, b, bright;
begin
if( (r|g|b) == 0 && bright) begin
pixel_r <= 4'h3;
pixel_g <= 4'h3;
pixel_b <= 4'h3;
end
if(b) pixel_b <= bright ? 4'hF : 4'h7;
if(g) pixel_g <= bright ? 4'hF : 4'h7;
if(r) pixel_r <= bright ? 4'hF : 4'h7;
end
endtask
always @(posedge clk, posedge rst_p) begin
if(rst_p) begin
pixel_r <= 0;
pixel_g <= 0;
pixel_b <= 0;
end else begin
pixel_r <= 0;
pixel_g <= 0;
pixel_b <= 0;
if(pixel) begin
setRGB(attribute[2],attribute[1],attribute[0],attribute[3]);
end else begin
setRGB(attribute[6],attribute[5],attribute[4],attribute[7]);
end
end
end
endmodule | module attributeMap(input clk,
input rst_p,
input pixel,
input[7:0] attribute,
output reg[3:0] pixel_r,
output reg[3:0] pixel_g,
output reg[3:0] pixel_b); |
task setRGB;
input r, g, b, bright;
begin
if( (r|g|b) == 0 && bright) begin
pixel_r <= 4'h3;
pixel_g <= 4'h3;
pixel_b <= 4'h3;
end
if(b) pixel_b <= bright ? 4'hF : 4'h7;
if(g) pixel_g <= bright ? 4'hF : 4'h7;
if(r) pixel_r <= bright ? 4'hF : 4'h7;
end
endtask
always @(posedge clk, posedge rst_p) begin
if(rst_p) begin
pixel_r <= 0;
pixel_g <= 0;
pixel_b <= 0;
end else begin
pixel_r <= 0;
pixel_g <= 0;
pixel_b <= 0;
if(pixel) begin
setRGB(attribute[2],attribute[1],attribute[0],attribute[3]);
end else begin
setRGB(attribute[6],attribute[5],attribute[4],attribute[7]);
end
end
end
endmodule | 5 |
4,850 | data/full_repos/permissive/111973973/vgacg/vgaEngine.v | 111,973,973 | vgaEngine.v | v | 138 | 129 | [] | [] | [] | [(26, 138)] | null | data/verilator_xmls/6bf4d99d-d84f-4543-8373-9bf6d9086e15.xml | null | 3,249 | module | module vgaEngine #(
parameter H_WIDTH = 10,
parameter V_WIDTH = 9,
parameter H_ACTIVE = 640,
parameter H_FP = 16,
parameter H_SYN = 96,
parameter H_BP = 48,
parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP,
parameter V_ACTIVE = 480,
parameter V_FP = 10,
parameter V_SYN = 2,
parameter V_BP = 29,
parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP,
parameter EXT_PIPELINE_DELAY = 0)
(input clk,
input rst_p,
input clk_en,
input[3:0] r,
input[3:0] g,
input[3:0] b,
output vertBlanking,
output[H_WIDTH-1:0] horizPos,
output[V_WIDTH-1:0] vertPos,
output reg v_sync,
output reg h_sync,
output reg[3:0] redOut,
output reg[3:0] greenOut,
output reg[3:0] blueOut);
integer i;
reg[H_WIDTH-1:0] horiz_position_pipeline [0:EXT_PIPELINE_DELAY];
reg[V_WIDTH-1:0] vert_position_pipeline [0:EXT_PIPELINE_DELAY];
wire v_sync_pre;
wire h_sync_pre;
assign horizPos = horiz_position_pipeline[0];
assign vertPos = vert_position_pipeline[0];
always @(posedge clk, posedge rst_p) begin
if(rst_p) begin
for(i = 0; i<=EXT_PIPELINE_DELAY; i=i+1) begin
horiz_position_pipeline[i] <= 0;
vert_position_pipeline[i] <= 0;
end
end else begin
for(i = 1; i<=EXT_PIPELINE_DELAY; i=i+1) begin
horiz_position_pipeline[i] <= horiz_position_pipeline[i-1];
vert_position_pipeline[i] <= vert_position_pipeline[i-1];
end
if (clk_en) begin
if(horiz_position_pipeline[0] == H_TOTAL-1) begin
if(vert_position_pipeline[0] == V_TOTAL-1) begin
vert_position_pipeline[0] <= 0;
end else begin
vert_position_pipeline[0] <= vert_position_pipeline[0] + 1;
end
horiz_position_pipeline[0] <= 0;
end else begin
horiz_position_pipeline[0] <= horiz_position_pipeline[0] + 1;
end
end
end
end
always @(posedge clk) begin
h_sync <= h_sync_pre;
v_sync <= v_sync_pre;
end
assign h_sync_pre = ~((horiz_position_pipeline[EXT_PIPELINE_DELAY] >= H_ACTIVE+H_FP) &
(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE+H_FP+H_SYN));
assign v_sync_pre = ~((vert_position_pipeline[EXT_PIPELINE_DELAY] >= V_ACTIVE+V_FP) &
(vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE+V_FP+V_SYN));
assign vertBlanking = (vert_position_pipeline[0] >= V_ACTIVE);
always @(posedge clk) begin
if(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE & vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE) begin
redOut <= r;
greenOut <= g;
blueOut <= b;
end else begin
redOut <= 0;
greenOut <= 0;
blueOut <= 0;
end
end
endmodule | module vgaEngine #(
parameter H_WIDTH = 10,
parameter V_WIDTH = 9,
parameter H_ACTIVE = 640,
parameter H_FP = 16,
parameter H_SYN = 96,
parameter H_BP = 48,
parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP,
parameter V_ACTIVE = 480,
parameter V_FP = 10,
parameter V_SYN = 2,
parameter V_BP = 29,
parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP,
parameter EXT_PIPELINE_DELAY = 0)
(input clk,
input rst_p,
input clk_en,
input[3:0] r,
input[3:0] g,
input[3:0] b,
output vertBlanking,
output[H_WIDTH-1:0] horizPos,
output[V_WIDTH-1:0] vertPos,
output reg v_sync,
output reg h_sync,
output reg[3:0] redOut,
output reg[3:0] greenOut,
output reg[3:0] blueOut); |
integer i;
reg[H_WIDTH-1:0] horiz_position_pipeline [0:EXT_PIPELINE_DELAY];
reg[V_WIDTH-1:0] vert_position_pipeline [0:EXT_PIPELINE_DELAY];
wire v_sync_pre;
wire h_sync_pre;
assign horizPos = horiz_position_pipeline[0];
assign vertPos = vert_position_pipeline[0];
always @(posedge clk, posedge rst_p) begin
if(rst_p) begin
for(i = 0; i<=EXT_PIPELINE_DELAY; i=i+1) begin
horiz_position_pipeline[i] <= 0;
vert_position_pipeline[i] <= 0;
end
end else begin
for(i = 1; i<=EXT_PIPELINE_DELAY; i=i+1) begin
horiz_position_pipeline[i] <= horiz_position_pipeline[i-1];
vert_position_pipeline[i] <= vert_position_pipeline[i-1];
end
if (clk_en) begin
if(horiz_position_pipeline[0] == H_TOTAL-1) begin
if(vert_position_pipeline[0] == V_TOTAL-1) begin
vert_position_pipeline[0] <= 0;
end else begin
vert_position_pipeline[0] <= vert_position_pipeline[0] + 1;
end
horiz_position_pipeline[0] <= 0;
end else begin
horiz_position_pipeline[0] <= horiz_position_pipeline[0] + 1;
end
end
end
end
always @(posedge clk) begin
h_sync <= h_sync_pre;
v_sync <= v_sync_pre;
end
assign h_sync_pre = ~((horiz_position_pipeline[EXT_PIPELINE_DELAY] >= H_ACTIVE+H_FP) &
(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE+H_FP+H_SYN));
assign v_sync_pre = ~((vert_position_pipeline[EXT_PIPELINE_DELAY] >= V_ACTIVE+V_FP) &
(vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE+V_FP+V_SYN));
assign vertBlanking = (vert_position_pipeline[0] >= V_ACTIVE);
always @(posedge clk) begin
if(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE & vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE) begin
redOut <= r;
greenOut <= g;
blueOut <= b;
end else begin
redOut <= 0;
greenOut <= 0;
blueOut <= 0;
end
end
endmodule | 5 |
4,851 | data/full_repos/permissive/111993107/freq/freq.v | 111,993,107 | freq.v | v | 61 | 82 | [] | [] | [] | [(16, 58)] | null | null | 1: b"%Error: data/full_repos/permissive/111993107/freq/freq.v:47: Cannot find file containing module: 'MERGE_TREE'\n MERGE_TREE #(5, 64, 32)\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/111993107/freq,data/full_repos/permissive/111993107/MERGE_TREE\n data/full_repos/permissive/111993107/freq,data/full_repos/permissive/111993107/MERGE_TREE.v\n data/full_repos/permissive/111993107/freq,data/full_repos/permissive/111993107/MERGE_TREE.sv\n MERGE_TREE\n MERGE_TREE.v\n MERGE_TREE.sv\n obj_dir/MERGE_TREE\n obj_dir/MERGE_TREE.v\n obj_dir/MERGE_TREE.sv\n%Error: Exiting due to 1 error(s)\n" | 3,250 | module | module freq(input wire CLK,
input wire RST_IN,
output wire OUT);
reg RST; always @(posedge CLK) RST <= RST_IN;
wire [(`DATW<<`E_LOG)-1:0] merge_tree_din;
wire [(1<<`E_LOG)-1:0] merge_tree_dinen;
wire [(1<<`E_LOG)-1:0] merge_tree_ful;
wire [(`DATW<<`E_LOG)-1:0] merge_tree_dot;
wire merge_tree_doten;
assign merge_tree_dinen = ~merge_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`E_LOG); i=i+1) begin: loop
reg [`KEYW-1:0] init_key;
reg [(`DATW-`KEYW)-1:0] init_payload;
always @(posedge CLK) begin
if (RST) init_key <= (1<<`E_LOG) - i;
else if (merge_tree_dinen[i]) init_key <= init_key + (1<<`E_LOG);
end
always @(posedge CLK) begin
if (RST) init_payload <= i + 1;
else if (merge_tree_dinen[i]) init_payload <= (init_payload << 1) + 1;
end
assign merge_tree_din[`DATW*(i+1)-1:`DATW*i] = {init_payload, init_key};
end
endgenerate
MERGE_TREE #(`E_LOG, `DATW, `KEYW)
merge_tree(CLK, RST, 1'b0, merge_tree_din, merge_tree_dinen,
merge_tree_ful, merge_tree_dot, merge_tree_doten);
reg [(`DATW<<`E_LOG)-1:0] dot_buf;
always @(posedge CLK) begin
if (merge_tree_doten) dot_buf <= merge_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | module freq(input wire CLK,
input wire RST_IN,
output wire OUT); |
reg RST; always @(posedge CLK) RST <= RST_IN;
wire [(`DATW<<`E_LOG)-1:0] merge_tree_din;
wire [(1<<`E_LOG)-1:0] merge_tree_dinen;
wire [(1<<`E_LOG)-1:0] merge_tree_ful;
wire [(`DATW<<`E_LOG)-1:0] merge_tree_dot;
wire merge_tree_doten;
assign merge_tree_dinen = ~merge_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`E_LOG); i=i+1) begin: loop
reg [`KEYW-1:0] init_key;
reg [(`DATW-`KEYW)-1:0] init_payload;
always @(posedge CLK) begin
if (RST) init_key <= (1<<`E_LOG) - i;
else if (merge_tree_dinen[i]) init_key <= init_key + (1<<`E_LOG);
end
always @(posedge CLK) begin
if (RST) init_payload <= i + 1;
else if (merge_tree_dinen[i]) init_payload <= (init_payload << 1) + 1;
end
assign merge_tree_din[`DATW*(i+1)-1:`DATW*i] = {init_payload, init_key};
end
endgenerate
MERGE_TREE #(`E_LOG, `DATW, `KEYW)
merge_tree(CLK, RST, 1'b0, merge_tree_din, merge_tree_dinen,
merge_tree_ful, merge_tree_dot, merge_tree_doten);
reg [(`DATW<<`E_LOG)-1:0] dot_buf;
always @(posedge CLK) begin
if (merge_tree_doten) dot_buf <= merge_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | 0 |
4,852 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module COMPARATOR #(parameter KEYW = 32)
(input wire [KEYW-1:0] DIN0,
input wire [KEYW-1:0] DIN1,
output wire RSLT);
assign RSLT = (DIN0 < DIN1);
endmodule | module COMPARATOR #(parameter KEYW = 32)
(input wire [KEYW-1:0] DIN0,
input wire [KEYW-1:0] DIN1,
output wire RSLT); |
assign RSLT = (DIN0 < DIN1);
endmodule | 0 |
4,853 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module EQUAL_DETECTOR #(parameter KEYW = 32)
(input wire [KEYW-1:0] DIN0,
input wire [KEYW-1:0] DIN1,
output wire RSLT);
assign RSLT = (DIN0 == DIN1);
endmodule | module EQUAL_DETECTOR #(parameter KEYW = 32)
(input wire [KEYW-1:0] DIN0,
input wire [KEYW-1:0] DIN1,
output wire RSLT); |
assign RSLT = (DIN0 == DIN1);
endmodule | 0 |
4,854 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MUX2 #(parameter DATW = 64)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire SEL,
output wire [DATW-1:0] DOUT);
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT = mux(DIN1, DIN0, SEL);
endmodule | module MUX2 #(parameter DATW = 64)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire SEL,
output wire [DATW-1:0] DOUT); |
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT = mux(DIN1, DIN0, SEL);
endmodule | 0 |
4,855 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MUX3 #(parameter DATW = 64)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire [DATW-1:0] DIN2,
input wire [1:0] SEL,
output wire [DATW-1:0] DOUT);
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input [DATW-1:0] c;
input [1:0] sel;
begin
casex (sel)
2'bx0: mux = a;
2'b01: mux = b;
2'b11: mux = c;
endcase
end
endfunction
assign DOUT = mux(DIN0, DIN2, DIN1, SEL);
endmodule | module MUX3 #(parameter DATW = 64)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire [DATW-1:0] DIN2,
input wire [1:0] SEL,
output wire [DATW-1:0] DOUT); |
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input [DATW-1:0] c;
input [1:0] sel;
begin
casex (sel)
2'bx0: mux = a;
2'b01: mux = b;
2'b11: mux = c;
endcase
end
endfunction
assign DOUT = mux(DIN0, DIN2, DIN1, SEL);
endmodule | 0 |
4,856 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module SORT_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
genvar i;
reg [(DATW<<E_LOG)-1:0] din_a;
reg dinen_a;
reg [DATW-1:0] fb_buf;
wire [DATW-1:0] fb_record;
wire [(1<<E_LOG)-1:0] comp_rslts;
always @(posedge CLK) if (!STALL) din_a <= DIN;
always @(posedge CLK) begin
if (RST) dinen_a <= 0;
else if (!STALL) dinen_a <= DINEN;
end
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: comparators
COMPARATOR #(KEYW)
comparator(din_a[(KEYW+DATW*i)-1:DATW*i], fb_buf[KEYW-1:0], comp_rslts[i]);
end
endgenerate
MUX2 #(DATW)
mux2(din_a[(DATW<<E_LOG)-1:(DATW<<E_LOG)-DATW], fb_buf, ~comp_rslts[(1<<E_LOG)-1], fb_record);
always @(posedge CLK) begin
if (RST) begin
fb_buf <= 0;
end else if (!STALL) begin
if (dinen_a) fb_buf <= fb_record;
end
end
reg [(DATW+(DATW<<E_LOG))-1:0] din_b;
reg dinen_b;
reg [(1<<E_LOG)-1:0] comp_rslts_buf;
wire [(DATW<<E_LOG)-1:0] remaining_records;
always @(posedge CLK) if (!STALL) din_b <= {fb_buf, din_a};
always @(posedge CLK) begin
if (RST) dinen_b <= 0;
else if (!STALL) dinen_b <= dinen_a;
end
always @(posedge CLK) if (!STALL) comp_rslts_buf <= comp_rslts;
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: multiplexers
if (i == 0) begin
MUX2 #(DATW)
mux2(din_b[DATW-1:0], din_b[(DATW+(DATW<<E_LOG))-1:(DATW<<E_LOG)], comp_rslts_buf[0], remaining_records[DATW-1:0]);
end else begin
MUX3 #(DATW)
mux3(din_b[DATW*i-1:DATW*(i-1)], din_b[DATW*(i+1)-1:DATW*i], din_b[(DATW+(DATW<<E_LOG))-1:(DATW<<E_LOG)], comp_rslts_buf[i:i-1], remaining_records[DATW*(i+1)-1:DATW*i]);
end
end
endgenerate
assign DOT = remaining_records;
assign DOTEN = dinen_b;
endmodule | module SORT_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
genvar i;
reg [(DATW<<E_LOG)-1:0] din_a;
reg dinen_a;
reg [DATW-1:0] fb_buf;
wire [DATW-1:0] fb_record;
wire [(1<<E_LOG)-1:0] comp_rslts;
always @(posedge CLK) if (!STALL) din_a <= DIN;
always @(posedge CLK) begin
if (RST) dinen_a <= 0;
else if (!STALL) dinen_a <= DINEN;
end
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: comparators
COMPARATOR #(KEYW)
comparator(din_a[(KEYW+DATW*i)-1:DATW*i], fb_buf[KEYW-1:0], comp_rslts[i]);
end
endgenerate
MUX2 #(DATW)
mux2(din_a[(DATW<<E_LOG)-1:(DATW<<E_LOG)-DATW], fb_buf, ~comp_rslts[(1<<E_LOG)-1], fb_record);
always @(posedge CLK) begin
if (RST) begin
fb_buf <= 0;
end else if (!STALL) begin
if (dinen_a) fb_buf <= fb_record;
end
end
reg [(DATW+(DATW<<E_LOG))-1:0] din_b;
reg dinen_b;
reg [(1<<E_LOG)-1:0] comp_rslts_buf;
wire [(DATW<<E_LOG)-1:0] remaining_records;
always @(posedge CLK) if (!STALL) din_b <= {fb_buf, din_a};
always @(posedge CLK) begin
if (RST) dinen_b <= 0;
else if (!STALL) dinen_b <= dinen_a;
end
always @(posedge CLK) if (!STALL) comp_rslts_buf <= comp_rslts;
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: multiplexers
if (i == 0) begin
MUX2 #(DATW)
mux2(din_b[DATW-1:0], din_b[(DATW+(DATW<<E_LOG))-1:(DATW<<E_LOG)], comp_rslts_buf[0], remaining_records[DATW-1:0]);
end else begin
MUX3 #(DATW)
mux3(din_b[DATW*i-1:DATW*(i-1)], din_b[DATW*(i+1)-1:DATW*i], din_b[(DATW+(DATW<<E_LOG))-1:(DATW<<E_LOG)], comp_rslts_buf[i:i-1], remaining_records[DATW*(i+1)-1:DATW*i]);
end
end
endgenerate
assign DOT = remaining_records;
assign DOTEN = dinen_b;
endmodule | 0 |
4,857 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MERGE_NETWORK #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
genvar i;
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: sort_logics
wire [(DATW<<E_LOG)-1:0] din;
wire dinen;
wire [(DATW<<E_LOG)-1:0] dot;
wire doten;
SORT_LOGIC #(E_LOG, DATW, KEYW)
sort_logic(CLK, RST, STALL, din, dinen, dot, doten);
end
endgenerate
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: connection
if (i == 0) begin
assign sort_logics[0].din = DIN;
assign sort_logics[0].dinen = DINEN;
end else begin
assign sort_logics[i].din = sort_logics[i-1].dot;
assign sort_logics[i].dinen = sort_logics[i-1].doten;
end
end
endgenerate
reg init_record_ejected;
always @(posedge CLK) begin
if (RST) init_record_ejected <= 0;
else if (sort_logics[(1<<E_LOG)-1].doten) init_record_ejected <= 1;
end
assign DOT = sort_logics[(1<<E_LOG)-1].dot;
assign DOTEN = &{sort_logics[(1<<E_LOG)-1].doten, init_record_ejected, (~STALL)};
endmodule | module MERGE_NETWORK #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
genvar i;
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: sort_logics
wire [(DATW<<E_LOG)-1:0] din;
wire dinen;
wire [(DATW<<E_LOG)-1:0] dot;
wire doten;
SORT_LOGIC #(E_LOG, DATW, KEYW)
sort_logic(CLK, RST, STALL, din, dinen, dot, doten);
end
endgenerate
generate
for (i=0; i<(1<<E_LOG); i=i+1) begin: connection
if (i == 0) begin
assign sort_logics[0].din = DIN;
assign sort_logics[0].dinen = DINEN;
end else begin
assign sort_logics[i].din = sort_logics[i-1].dot;
assign sort_logics[i].dinen = sort_logics[i-1].doten;
end
end
endgenerate
reg init_record_ejected;
always @(posedge CLK) begin
if (RST) init_record_ejected <= 0;
else if (sort_logics[(1<<E_LOG)-1].doten) init_record_ejected <= 1;
end
assign DOT = sort_logics[(1<<E_LOG)-1].dot;
assign DOTEN = &{sort_logics[(1<<E_LOG)-1].doten, init_record_ejected, (~STALL)};
endmodule | 0 |
4,858 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module SRL_FIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt == 0);
assign full = (cnt == (1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule | module SRL_FIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt); |
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt == 0);
assign full = (cnt == (1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule | 0 |
4,859 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module SELECTOR_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN_A,
input wire EMP_A,
input wire [(DATW<<E_LOG)-1:0] DIN_B,
input wire EMP_B,
output wire DEQ_A,
output wire DEQ_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
reg [(DATW<<E_LOG)-1:0] A0, A1, B0, B1;
reg A_in, B_in;
reg init_A_done, init_B_done;
reg comp_mux_buf;
reg comp_state;
reg flip_selector;
wire deq_A_initbefore, deq_B_initbefore;
wire deq_A_initafter, deq_B_initafter;
wire [(DATW<<E_LOG)-1:0] selected_records;
wire comp_rslt_A0B1, comp_rslt_A1B0;
wire is_equal_A0B1, is_equal_A1B0;
wire comp_mux_out;
wire is_equal_mux_out;
assign deq_A_initbefore = ~|{EMP_A,init_A_done};
assign deq_B_initbefore = ~|{EMP_B,init_B_done} && init_A_done;
assign deq_A_initafter = &{(~EMP_A), comp_mux_buf, init_B_done, (~STALL)};
assign deq_B_initafter = &{(~EMP_B), (~comp_mux_buf), init_B_done, (~STALL)};
always @(posedge CLK) begin
if (RST) begin
A_in <= 0;
B_in <= 0;
init_A_done <= 0;
init_B_done <= 0;
end else begin
if (!A_in) A_in <= deq_A_initbefore;
if (!B_in) B_in <= deq_B_initbefore;
if (deq_A_initbefore) init_A_done <= A_in;
if (deq_B_initbefore) init_B_done <= B_in;
end
end
always @(posedge CLK) if (DEQ_A) A0 <= DIN_A;
always @(posedge CLK) if (DEQ_B) B0 <= DIN_B;
COMPARATOR #(KEYW)
comparatorA0B1(A0[KEYW-1:0], B1[KEYW-1:0], comp_rslt_A0B1);
COMPARATOR #(KEYW)
comparatorA1B0(A1[KEYW-1:0], B0[KEYW-1:0], comp_rslt_A1B0);
EQUAL_DETECTOR #(KEYW)
equal_detectorA0B1(A0[KEYW-1:0], B1[KEYW-1:0], is_equal_A0B1);
EQUAL_DETECTOR #(KEYW)
equal_detectorA1B0(A1[KEYW-1:0], B0[KEYW-1:0], is_equal_A1B0);
MUX2 #(1) mux2_4_comprslt(comp_rslt_A0B1, comp_rslt_A1B0, comp_mux_buf, comp_mux_out);
MUX2 #(1) mux2_4_is_equal(is_equal_A0B1, is_equal_A1B0, comp_mux_buf, is_equal_mux_out);
always @(posedge CLK) if (DEQ_A) A1 <= A0;
always @(posedge CLK) if (DEQ_B) B1 <= B0;
always @(posedge CLK) begin
if (RST) begin
comp_mux_buf <= 0;
comp_state <= 0;
flip_selector <= 0;
end else begin
case (comp_state)
0: begin
if (B_in && deq_B_initbefore) begin
comp_mux_buf <= comp_mux_out;
comp_state <= 1;
end
end
1: begin
if (deq_A_initafter || deq_B_initafter) begin
if (is_equal_mux_out) begin comp_mux_buf <= flip_selector; flip_selector <= ~flip_selector; end
else begin comp_mux_buf <= comp_mux_out; end
end
end
endcase
end
end
MUX2 #((DATW<<E_LOG)) mux2_4_record(A1, B1, comp_mux_buf, selected_records);
assign DEQ_A = deq_A_initbefore || deq_A_initafter;
assign DEQ_B = deq_B_initbefore || deq_B_initafter;
assign DOT = selected_records;
assign DOTEN = deq_A_initafter || deq_B_initafter;
endmodule | module SELECTOR_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire STALL,
input wire [(DATW<<E_LOG)-1:0] DIN_A,
input wire EMP_A,
input wire [(DATW<<E_LOG)-1:0] DIN_B,
input wire EMP_B,
output wire DEQ_A,
output wire DEQ_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
reg [(DATW<<E_LOG)-1:0] A0, A1, B0, B1;
reg A_in, B_in;
reg init_A_done, init_B_done;
reg comp_mux_buf;
reg comp_state;
reg flip_selector;
wire deq_A_initbefore, deq_B_initbefore;
wire deq_A_initafter, deq_B_initafter;
wire [(DATW<<E_LOG)-1:0] selected_records;
wire comp_rslt_A0B1, comp_rslt_A1B0;
wire is_equal_A0B1, is_equal_A1B0;
wire comp_mux_out;
wire is_equal_mux_out;
assign deq_A_initbefore = ~|{EMP_A,init_A_done};
assign deq_B_initbefore = ~|{EMP_B,init_B_done} && init_A_done;
assign deq_A_initafter = &{(~EMP_A), comp_mux_buf, init_B_done, (~STALL)};
assign deq_B_initafter = &{(~EMP_B), (~comp_mux_buf), init_B_done, (~STALL)};
always @(posedge CLK) begin
if (RST) begin
A_in <= 0;
B_in <= 0;
init_A_done <= 0;
init_B_done <= 0;
end else begin
if (!A_in) A_in <= deq_A_initbefore;
if (!B_in) B_in <= deq_B_initbefore;
if (deq_A_initbefore) init_A_done <= A_in;
if (deq_B_initbefore) init_B_done <= B_in;
end
end
always @(posedge CLK) if (DEQ_A) A0 <= DIN_A;
always @(posedge CLK) if (DEQ_B) B0 <= DIN_B;
COMPARATOR #(KEYW)
comparatorA0B1(A0[KEYW-1:0], B1[KEYW-1:0], comp_rslt_A0B1);
COMPARATOR #(KEYW)
comparatorA1B0(A1[KEYW-1:0], B0[KEYW-1:0], comp_rslt_A1B0);
EQUAL_DETECTOR #(KEYW)
equal_detectorA0B1(A0[KEYW-1:0], B1[KEYW-1:0], is_equal_A0B1);
EQUAL_DETECTOR #(KEYW)
equal_detectorA1B0(A1[KEYW-1:0], B0[KEYW-1:0], is_equal_A1B0);
MUX2 #(1) mux2_4_comprslt(comp_rslt_A0B1, comp_rslt_A1B0, comp_mux_buf, comp_mux_out);
MUX2 #(1) mux2_4_is_equal(is_equal_A0B1, is_equal_A1B0, comp_mux_buf, is_equal_mux_out);
always @(posedge CLK) if (DEQ_A) A1 <= A0;
always @(posedge CLK) if (DEQ_B) B1 <= B0;
always @(posedge CLK) begin
if (RST) begin
comp_mux_buf <= 0;
comp_state <= 0;
flip_selector <= 0;
end else begin
case (comp_state)
0: begin
if (B_in && deq_B_initbefore) begin
comp_mux_buf <= comp_mux_out;
comp_state <= 1;
end
end
1: begin
if (deq_A_initafter || deq_B_initafter) begin
if (is_equal_mux_out) begin comp_mux_buf <= flip_selector; flip_selector <= ~flip_selector; end
else begin comp_mux_buf <= comp_mux_out; end
end
end
endcase
end
end
MUX2 #((DATW<<E_LOG)) mux2_4_record(A1, B1, comp_mux_buf, selected_records);
assign DEQ_A = deq_A_initbefore || deq_A_initafter;
assign DEQ_B = deq_B_initbefore || deq_B_initafter;
assign DOT = selected_records;
assign DOTEN = deq_A_initafter || deq_B_initafter;
endmodule | 0 |
4,860 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MERGE_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire ENQ_A,
input wire [(DATW<<E_LOG)-1:0] DIN_A,
input wire ENQ_B,
input wire [(DATW<<E_LOG)-1:0] DIN_B,
output wire FUL_A,
output wire FUL_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
reg stall;
always @(posedge CLK) stall <= IN_FULL;
wire fifo_4_regA_deq, fifo_4_regB_deq;
wire [(DATW<<E_LOG)-1:0] fifo_4_regA_dot, fifo_4_regB_dot;
wire fifo_4_regA_emp, fifo_4_regB_emp;
wire fifo_4_regA_ful, fifo_4_regB_ful;
wire [4:0] fifo_4_regA_cnt, fifo_4_regB_cnt;
wire [(DATW<<E_LOG)-1:0] selected_records;
wire selected_records_valid;
wire [(DATW<<E_LOG)-1:0] merge_network_dot;
wire merge_network_doten;
SRL_FIFO #(4, (DATW<<E_LOG))
fifo_4_regA(CLK, RST, ENQ_A, fifo_4_regA_deq, DIN_A,
fifo_4_regA_dot, fifo_4_regA_emp, fifo_4_regA_ful, fifo_4_regA_cnt);
SRL_FIFO #(4, (DATW<<E_LOG))
fifo_4_regB(CLK, RST, ENQ_B, fifo_4_regB_deq, DIN_B,
fifo_4_regB_dot, fifo_4_regB_emp, fifo_4_regB_ful, fifo_4_regB_cnt);
SELECTOR_LOGIC #(E_LOG, DATW, KEYW)
selector_logic(CLK, RST, stall, fifo_4_regA_dot, fifo_4_regA_emp, fifo_4_regB_dot, fifo_4_regB_emp,
fifo_4_regA_deq, fifo_4_regB_deq, selected_records, selected_records_valid);
MERGE_NETWORK #(E_LOG, DATW, KEYW)
merge_network(CLK, RST, stall, selected_records, selected_records_valid,
merge_network_dot, merge_network_doten);
assign FUL_A = fifo_4_regA_ful;
assign FUL_B = fifo_4_regB_ful;
assign DOT = merge_network_dot;
assign DOTEN = merge_network_doten;
endmodule | module MERGE_LOGIC #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire ENQ_A,
input wire [(DATW<<E_LOG)-1:0] DIN_A,
input wire ENQ_B,
input wire [(DATW<<E_LOG)-1:0] DIN_B,
output wire FUL_A,
output wire FUL_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
reg stall;
always @(posedge CLK) stall <= IN_FULL;
wire fifo_4_regA_deq, fifo_4_regB_deq;
wire [(DATW<<E_LOG)-1:0] fifo_4_regA_dot, fifo_4_regB_dot;
wire fifo_4_regA_emp, fifo_4_regB_emp;
wire fifo_4_regA_ful, fifo_4_regB_ful;
wire [4:0] fifo_4_regA_cnt, fifo_4_regB_cnt;
wire [(DATW<<E_LOG)-1:0] selected_records;
wire selected_records_valid;
wire [(DATW<<E_LOG)-1:0] merge_network_dot;
wire merge_network_doten;
SRL_FIFO #(4, (DATW<<E_LOG))
fifo_4_regA(CLK, RST, ENQ_A, fifo_4_regA_deq, DIN_A,
fifo_4_regA_dot, fifo_4_regA_emp, fifo_4_regA_ful, fifo_4_regA_cnt);
SRL_FIFO #(4, (DATW<<E_LOG))
fifo_4_regB(CLK, RST, ENQ_B, fifo_4_regB_deq, DIN_B,
fifo_4_regB_dot, fifo_4_regB_emp, fifo_4_regB_ful, fifo_4_regB_cnt);
SELECTOR_LOGIC #(E_LOG, DATW, KEYW)
selector_logic(CLK, RST, stall, fifo_4_regA_dot, fifo_4_regA_emp, fifo_4_regB_dot, fifo_4_regB_emp,
fifo_4_regA_deq, fifo_4_regB_deq, selected_records, selected_records_valid);
MERGE_NETWORK #(E_LOG, DATW, KEYW)
merge_network(CLK, RST, stall, selected_records, selected_records_valid,
merge_network_dot, merge_network_doten);
assign FUL_A = fifo_4_regA_ful;
assign FUL_B = fifo_4_regB_ful;
assign DOT = merge_network_dot;
assign DOTEN = merge_network_doten;
endmodule | 0 |
4,861 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module COUPLER #(parameter E_LOG = 2,
parameter DATW = 64)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<(E_LOG-1))-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
reg stall;
always @(posedge CLK) stall <= IN_FULL;
reg [(DATW<<E_LOG)-1:0] record_buf;
reg record_buf_cnt;
reg record_buf_en;
always @(posedge CLK) begin
if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
end
always @(posedge CLK) begin
if (RST) record_buf_cnt <= 0;
else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
end
always @(posedge CLK) if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};
assign DOT = record_buf;
assign DOTEN = &{record_buf_en, (~stall)};
endmodule | module COUPLER #(parameter E_LOG = 2,
parameter DATW = 64)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<(E_LOG-1))-1:0] DIN,
input wire DINEN,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
reg stall;
always @(posedge CLK) stall <= IN_FULL;
reg [(DATW<<E_LOG)-1:0] record_buf;
reg record_buf_cnt;
reg record_buf_en;
always @(posedge CLK) begin
if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
end
always @(posedge CLK) begin
if (RST) record_buf_cnt <= 0;
else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
end
always @(posedge CLK) if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};
assign DOT = record_buf;
assign DOTEN = &{record_buf_en, (~stall)};
endmodule | 0 |
4,862 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MERGE_NODE #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
input wire DINEN_A,
input wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
input wire DINEN_B,
output wire FUL_A,
output wire FUL_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
wire [(DATW<<E_LOG)-1:0] coupler_4_A_dot, coupler_4_B_dot;
wire coupler_4_A_doten, coupler_4_B_doten;
COUPLER #(E_LOG, DATW)
coupler_4_A(CLK, RST, FUL_A, DIN_A, DINEN_A, coupler_4_A_dot, coupler_4_A_doten);
COUPLER #(E_LOG, DATW)
coupler_4_B(CLK, RST, FUL_B, DIN_B, DINEN_B, coupler_4_B_dot, coupler_4_B_doten);
MERGE_LOGIC #(E_LOG, DATW, KEYW)
merge_logic(CLK, RST, IN_FULL, coupler_4_A_doten, coupler_4_A_dot, coupler_4_B_doten, coupler_4_B_dot,
FUL_A, FUL_B, DOT, DOTEN);
endmodule | module MERGE_NODE #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
input wire DINEN_A,
input wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
input wire DINEN_B,
output wire FUL_A,
output wire FUL_B,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
wire [(DATW<<E_LOG)-1:0] coupler_4_A_dot, coupler_4_B_dot;
wire coupler_4_A_doten, coupler_4_B_doten;
COUPLER #(E_LOG, DATW)
coupler_4_A(CLK, RST, FUL_A, DIN_A, DINEN_A, coupler_4_A_dot, coupler_4_A_doten);
COUPLER #(E_LOG, DATW)
coupler_4_B(CLK, RST, FUL_B, DIN_B, DINEN_B, coupler_4_B_dot, coupler_4_B_doten);
MERGE_LOGIC #(E_LOG, DATW, KEYW)
merge_logic(CLK, RST, IN_FULL, coupler_4_A_doten, coupler_4_A_dot, coupler_4_B_doten, coupler_4_B_dot,
FUL_A, FUL_B, DOT, DOTEN);
endmodule | 0 |
4,863 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | module | module MERGE_TREE #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire [(1<<E_LOG)-1:0] DINEN,
output wire [(1<<E_LOG)-1:0] FULL,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN);
genvar i, j;
generate
for (i=0; i<E_LOG; i=i+1) begin: level
wire [(1<<(E_LOG-(i+1)))-1:0] node_in_full;
wire [(DATW<<E_LOG)-1:0] node_din;
wire [(1<<(E_LOG-i))-1:0] node_dinen;
wire [(1<<(E_LOG-i))-1:0] node_full;
wire [(DATW<<E_LOG)-1:0] node_dot;
wire [(1<<(E_LOG-(i+1)))-1:0] node_doten;
for (j=0; j<(1<<(E_LOG-(i+1))); j=j+1) begin: nodes
MERGE_NODE #((i+1), DATW, KEYW)
merge_node(CLK, RST, node_in_full[j], node_din[(DATW<<(i))*(2*j+1)-1:(DATW<<(i))*(2*j)], node_dinen[2*j], node_din[(DATW<<(i))*(2*j+2)-1:(DATW<<(i))*(2*j+1)], node_dinen[2*j+1],
node_full[2*j], node_full[2*j+1], node_dot[(DATW<<(i+1))*(j+1)-1:(DATW<<(i+1))*j], node_doten[j]);
end
end
endgenerate
generate
for (i=0; i<E_LOG; i=i+1) begin: connection
if (i == 0) begin
assign level[0].node_din = DIN;
assign level[0].node_dinen = DINEN;
assign FULL = level[0].node_full;
end else begin
assign level[i].node_din = level[i-1].node_dot;
assign level[i].node_dinen = level[i-1].node_doten;
assign level[i-1].node_in_full = level[i].node_full;
end
end
endgenerate
assign level[E_LOG-1].node_in_full = IN_FULL;
assign DOT = level[E_LOG-1].node_dot;
assign DOTEN = level[E_LOG-1].node_doten;
endmodule | module MERGE_TREE #(parameter E_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<E_LOG)-1:0] DIN,
input wire [(1<<E_LOG)-1:0] DINEN,
output wire [(1<<E_LOG)-1:0] FULL,
output wire [(DATW<<E_LOG)-1:0] DOT,
output wire DOTEN); |
genvar i, j;
generate
for (i=0; i<E_LOG; i=i+1) begin: level
wire [(1<<(E_LOG-(i+1)))-1:0] node_in_full;
wire [(DATW<<E_LOG)-1:0] node_din;
wire [(1<<(E_LOG-i))-1:0] node_dinen;
wire [(1<<(E_LOG-i))-1:0] node_full;
wire [(DATW<<E_LOG)-1:0] node_dot;
wire [(1<<(E_LOG-(i+1)))-1:0] node_doten;
for (j=0; j<(1<<(E_LOG-(i+1))); j=j+1) begin: nodes
MERGE_NODE #((i+1), DATW, KEYW)
merge_node(CLK, RST, node_in_full[j], node_din[(DATW<<(i))*(2*j+1)-1:(DATW<<(i))*(2*j)], node_dinen[2*j], node_din[(DATW<<(i))*(2*j+2)-1:(DATW<<(i))*(2*j+1)], node_dinen[2*j+1],
node_full[2*j], node_full[2*j+1], node_dot[(DATW<<(i+1))*(j+1)-1:(DATW<<(i+1))*j], node_doten[j]);
end
end
endgenerate
generate
for (i=0; i<E_LOG; i=i+1) begin: connection
if (i == 0) begin
assign level[0].node_din = DIN;
assign level[0].node_dinen = DINEN;
assign FULL = level[0].node_full;
end else begin
assign level[i].node_din = level[i-1].node_dot;
assign level[i].node_dinen = level[i-1].node_doten;
assign level[i-1].node_in_full = level[i].node_full;
end
end
endgenerate
assign level[E_LOG-1].node_in_full = IN_FULL;
assign DOT = level[E_LOG-1].node_dot;
assign DOTEN = level[E_LOG-1].node_doten;
endmodule | 0 |
4,864 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | function | function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | function [DATW-1:0] mux; |
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | 0 |
4,865 | data/full_repos/permissive/111993107/src/hms.v | 111,993,107 | hms.v | v | 543 | 187 | [] | [] | [] | [(9, 16), (21, 28), (33, 53), (58, 81), (86, 161), (166, 211), (216, 255), (260, 363), (368, 420), (425, 456), (461, 488), (493, 540)] | null | data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml | null | 3,251 | function | function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input [DATW-1:0] c;
input [1:0] sel;
begin
casex (sel)
2'bx0: mux = a;
2'b01: mux = b;
2'b11: mux = c;
endcase
end
endfunction | function [DATW-1:0] mux; |
input [DATW-1:0] a;
input [DATW-1:0] b;
input [DATW-1:0] c;
input [1:0] sel;
begin
casex (sel)
2'bx0: mux = a;
2'b01: mux = b;
2'b11: mux = c;
endcase
end
endfunction | 0 |
4,866 | data/full_repos/permissive/112034627/source/icap.v | 112,034,627 | icap.v | v | 24 | 110 | [] | [] | [] | [(1, 23)] | null | null | 1: b"%Error: data/full_repos/permissive/112034627/source/icap.v:10: Cannot find file containing module: 'ICAP_SPARTAN6'\n ICAP_SPARTAN6 #(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/112034627/source,data/full_repos/permissive/112034627/ICAP_SPARTAN6\n data/full_repos/permissive/112034627/source,data/full_repos/permissive/112034627/ICAP_SPARTAN6.v\n data/full_repos/permissive/112034627/source,data/full_repos/permissive/112034627/ICAP_SPARTAN6.sv\n ICAP_SPARTAN6\n ICAP_SPARTAN6.v\n ICAP_SPARTAN6.sv\n obj_dir/ICAP_SPARTAN6\n obj_dir/ICAP_SPARTAN6.v\n obj_dir/ICAP_SPARTAN6.sv\n%Error: Exiting due to 1 error(s)\n" | 3,270 | module | module icap (
output BUSY,
input CE,
input CLK,
input [15:0] I,
output [15:0] O,
input WRITE
);
ICAP_SPARTAN6 #(
.DEVICE_ID(28'h4000093),
.SIM_CFG_FILE_NAME("NONE")
)
ICAP_SPARTAN6_inst (
.BUSY(BUSY),
.O(O),
.CE(CE),
.CLK(CLK),
.I(I),
.WRITE(WRITE)
);
endmodule | module icap (
output BUSY,
input CE,
input CLK,
input [15:0] I,
output [15:0] O,
input WRITE
); |
ICAP_SPARTAN6 #(
.DEVICE_ID(28'h4000093),
.SIM_CFG_FILE_NAME("NONE")
)
ICAP_SPARTAN6_inst (
.BUSY(BUSY),
.O(O),
.CE(CE),
.CLK(CLK),
.I(I),
.WRITE(WRITE)
);
endmodule | 0 |
4,868 | data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v | 112,176,817 | FP_to_Posit.v | v | 64 | 127 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:34: Cannot find file containing module: \'LOD_N\'\nLOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.v\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.sv\n LOD_N\n LOD_N.v\n LOD_N.sv\n obj_dir/LOD_N\n obj_dir/LOD_N.v\n obj_dir/LOD_N.sv\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:37: Cannot find file containing module: \'DSR_left_N_S\'\nDSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:39: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'Lshift\' generates 4 bits.\n : ... In instance FP_to_posit\nwire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:44: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 7 bits.\n : ... In instance FP_to_posit\nwire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1\'b0}},exp_N[E-1:es]} + 1\'b1 : {{Bs{1\'b0}},exp_N[E-1:es]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:54: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_o\' generates 3 bits.\n : ... In instance FP_to_posit\n else assign diff_b = r_o;\n ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:56: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 3,273 | module | module FP_to_posit(in, out);
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter E = 5;
parameter es = 2;
parameter M = N-E-1;
parameter BIAS = (2**(E-1))-1;
parameter Bs = log2(N);
input [N-1:0] in;
output [N-1:0] out;
wire s_in = in[N-1];
wire [E-1:0] exp_in = in[N-2:N-1-E];
wire [M-1:0] mant_in = in[M-1:0];
wire zero_in = ~|{exp_in,mant_in};
wire inf_in = &exp_in;
wire [M:0] mant = {|exp_in, mant_in};
wire [N-1:0] LOD_in = {mant,{E{1'b0}}};
wire[Bs-1:0] Lshift;
LOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));
wire[N-1:0] mant_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));
wire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;
wire [E:0] exp_N = exp[E] ? -exp : exp;
wire [es-1:0] e_o = (exp[E] & |exp_N[es-1:0]) ? exp[es-1:0] : exp_N[es-1:0];
wire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1'b0}},exp_N[E-1:es]} + 1'b1 : {{Bs{1'b0}},exp_N[E-1:es]};
wire [2*N-1:0]tmp_o = { {N{~exp[E]}}, exp[E], e_o, mant_tmp[N-2:es]};
wire [2*N-1:0] tmp1_o;
wire [Bs-1:0] diff_b;
generate
if(E-es > Bs) assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
else assign diff_b = r_o;
endgenerate
DSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));
wire [N-1:0] tmp1_oN = s_in ? -tmp1_o[N-1:0] : tmp1_o[N-1:0];
assign out = inf_in|zero_in|(~mant_tmp[N-1]) ? {inf_in,{N-1{1'b0}}} : {s_in, tmp1_oN[N-1:1]};
endmodule | module FP_to_posit(in, out); |
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
parameter N = 16;
parameter E = 5;
parameter es = 2;
parameter M = N-E-1;
parameter BIAS = (2**(E-1))-1;
parameter Bs = log2(N);
input [N-1:0] in;
output [N-1:0] out;
wire s_in = in[N-1];
wire [E-1:0] exp_in = in[N-2:N-1-E];
wire [M-1:0] mant_in = in[M-1:0];
wire zero_in = ~|{exp_in,mant_in};
wire inf_in = &exp_in;
wire [M:0] mant = {|exp_in, mant_in};
wire [N-1:0] LOD_in = {mant,{E{1'b0}}};
wire[Bs-1:0] Lshift;
LOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));
wire[N-1:0] mant_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));
wire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;
wire [E:0] exp_N = exp[E] ? -exp : exp;
wire [es-1:0] e_o = (exp[E] & |exp_N[es-1:0]) ? exp[es-1:0] : exp_N[es-1:0];
wire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1'b0}},exp_N[E-1:es]} + 1'b1 : {{Bs{1'b0}},exp_N[E-1:es]};
wire [2*N-1:0]tmp_o = { {N{~exp[E]}}, exp[E], e_o, mant_tmp[N-2:es]};
wire [2*N-1:0] tmp1_o;
wire [Bs-1:0] diff_b;
generate
if(E-es > Bs) assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
else assign diff_b = r_o;
endgenerate
DSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));
wire [N-1:0] tmp1_oN = s_in ? -tmp1_o[N-1:0] : tmp1_o[N-1:0];
assign out = inf_in|zero_in|(~mant_tmp[N-1]) ? {inf_in,{N-1{1'b0}}} : {s_in, tmp1_oN[N-1:1]};
endmodule | 36 |
4,869 | data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v | 112,176,817 | FP_to_Posit.v | v | 64 | 127 | [] | [] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:34: Cannot find file containing module: \'LOD_N\'\nLOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.v\n data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.sv\n LOD_N\n LOD_N.v\n LOD_N.sv\n obj_dir/LOD_N\n obj_dir/LOD_N.v\n obj_dir/LOD_N.sv\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:37: Cannot find file containing module: \'DSR_left_N_S\'\nDSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:39: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'Lshift\' generates 4 bits.\n : ... In instance FP_to_posit\nwire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:44: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 7 bits.\n : ... In instance FP_to_posit\nwire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1\'b0}},exp_N[E-1:es]} + 1\'b1 : {{Bs{1\'b0}},exp_N[E-1:es]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:54: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_o\' generates 3 bits.\n : ... In instance FP_to_posit\n else assign diff_b = r_o;\n ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:56: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 3,273 | function | function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function [31:0] log2; |
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 36 |
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