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5,029 | data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v | 112,978,342 | ring_counter.v | v | 82 | 182 | [] | [] | [] | [(1, 81)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'delay_counter\' generates 32 bits.\n : ... In instance ring_counter\n else out_delay[7:0] = delay_counter; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v:75: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance ring_counter\n if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,427 | module | module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay);
input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;
parameter DELAY=100;
wire [DELAY-1:0] delay_line;
output reg start;
reg freeze;
assign carryout = freeze;
wire freezeline;
assign freezeline = carryin;
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
begin : del
assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1];
end
endgenerate
assign delay_line[0] = start;
initial begin
start<=0;
freeze<=0;
end
integer delay_counter=0;
always @(posedge clk) begin
if (freeze) begin
if (delay_line[delay_counter]) delay_counter=delay_counter+1;
else out_delay[7:0] = delay_counter;
end
else delay_counter=0;
end
integer counter=0;
integer delayer=0;
always @(posedge clk) begin
counter = counter+1;
if (counter==200000000) begin
freeze=0;
start=0;
end
if (counter==200000050) begin
start=1;
end
if (counter==200000050+delayer) begin
freeze=1;
end
if (counter==200000050+delayer+ 100000) counter=0;
end
integer delay_counter2=1;
always @(posedge clk) begin
if (counter > 200000050+delayer + 10) begin
if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;
else delay_counter2=delay_counter2+1;
end
else delay_counter2=1;
end
endmodule | module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay); |
input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;
parameter DELAY=100;
wire [DELAY-1:0] delay_line;
output reg start;
reg freeze;
assign carryout = freeze;
wire freezeline;
assign freezeline = carryin;
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
begin : del
assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1];
end
endgenerate
assign delay_line[0] = start;
initial begin
start<=0;
freeze<=0;
end
integer delay_counter=0;
always @(posedge clk) begin
if (freeze) begin
if (delay_line[delay_counter]) delay_counter=delay_counter+1;
else out_delay[7:0] = delay_counter;
end
else delay_counter=0;
end
integer counter=0;
integer delayer=0;
always @(posedge clk) begin
counter = counter+1;
if (counter==200000000) begin
freeze=0;
start=0;
end
if (counter==200000050) begin
start=1;
end
if (counter==200000050+delayer) begin
freeze=1;
end
if (counter==200000050+delayer+ 100000) counter=0;
end
integer delay_counter2=1;
always @(posedge clk) begin
if (counter > 200000050+delayer + 10) begin
if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;
else delay_counter2=delay_counter2+1;
end
else delay_counter2=1;
end
endmodule | 93 |
5,031 | data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v | 112,978,342 | oscillo.v | v | 316 | 240 | [] | [] | [] | [(1, 315)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:136: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (Threshold3[i]>triggertot[ram_width-1:0]) begin \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:125: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n : ... In instance oscillo\n if (Threshold3[i]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:123: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (triggertot[ram_width-1:0]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:162: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (Threshold3[i]>triggertot[ram_width-1:0]) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:151: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n : ... In instance oscillo\n if (Threshold3[i]) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:149: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n : ... In instance oscillo\n if (triggertot[ram_width-1:0]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:221: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n : ... In instance oscillo\nassign downsamplego = downsamplecounter[downsample] || downsample==0; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:267: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash1_reg\' generates 8 bits.\n : ... In instance oscillo\n highres1=highres1+data_flash1_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:268: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash2_reg\' generates 8 bits.\n : ... In instance oscillo\n highres2=highres2+data_flash2_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:269: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash3_reg\' generates 8 bits.\n : ... In instance oscillo\n highres3=highres3+data_flash3_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:270: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash4_reg\' generates 8 bits.\n : ... In instance oscillo\n highres4=highres4+data_flash4_reg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:274: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout1=highres1>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:275: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout2=highres2>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:276: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout3=highres3>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:277: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout4=highres4>>maxhighres;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:280: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout1=highres1>>downsample;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:281: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout2=highres2>>downsample;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:282: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout3=highres3>>downsample;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:283: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n : ... In instance oscillo\n dout4=highres4>>downsample;\n ^\n%Error: Exiting due to 19 warning(s)\n' | 5,469 | module | module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthresh2,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp);
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthresh2;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
input [3:0] triggertype;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin
div_sclk_out=0;
outsel_cs_out=0;
format_sdin_out=SPIsenddata[SPIsendcounter];
SPIsendcounter=SPIsendcounter-4'b001;
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3;
else SPIstate=SPI1;
end
end
SPI3: begin
if (SPIcounter[2]) begin
outsel_cs_out=1;
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end
end
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;
reg [7:0] data_flash3_reg; always @(posedge clk_flash2) data_flash3_reg <= data_flash3;
reg [7:0] data_flash4_reg; always @(posedge clk_flash2) data_flash4_reg <= data_flash4;
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
if (trigchannels[i]) begin
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthresh2);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthresh2);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthresh2);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthresh2);
Threshold2[i] <= Threshold1[i];
if (triggertype[0]) begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
end
else begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (~Threshold1[i] & Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
end
end
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[12];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter;
always @(posedge clk_flash) if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
wire selftrig;
assign selftrig = (trigchannels[0]&&selftrigtemp[0])||(trigchannels[1]&&selftrigtemp[1])||(trigchannels[2]&&selftrigtemp[2])||(trigchannels[3]&&selftrigtemp[3]) ||(rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
always @(posedge clk_flash)
if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];
always @(posedge clk_flash)
if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;
always @(posedge clk_flash)
if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;
reg startAcquisition;
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger;
else if(AcquiringAndTriggered2) startAcquisition <= 0;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
integer state=INIT;
reg [31:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample] || downsample==0;
always @(posedge clk_flash) begin
case (state)
INIT: begin
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1;
HaveFullData <= 0;
PreOrPostAcquiring <= 1;
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin
AcquiringAndTriggered <= 1;
PreOrPostAcquiring <= 1;
wraddress_triggerpoint <= wraddress;
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp) begin
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres && downsample>0) begin
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample;
dout2=highres2>>downsample;
dout3=highres3>>downsample;
dout4=highres4>>downsample;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
if (startAcquisition) data_ready=0;
else if (HaveFullData2) data_ready=1;
end
endmodule | module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthresh2,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp); |
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthresh2;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
input [3:0] triggertype;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin
div_sclk_out=0;
outsel_cs_out=0;
format_sdin_out=SPIsenddata[SPIsendcounter];
SPIsendcounter=SPIsendcounter-4'b001;
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3;
else SPIstate=SPI1;
end
end
SPI3: begin
if (SPIcounter[2]) begin
outsel_cs_out=1;
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end
end
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;
reg [7:0] data_flash3_reg; always @(posedge clk_flash2) data_flash3_reg <= data_flash3;
reg [7:0] data_flash4_reg; always @(posedge clk_flash2) data_flash4_reg <= data_flash4;
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
if (trigchannels[i]) begin
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthresh2);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthresh2);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthresh2);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthresh2);
Threshold2[i] <= Threshold1[i];
if (triggertype[0]) begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
end
else begin
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
end
else begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
else Threshold3[i] <= 0;
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 1;
Threshold3[i] <= 0;
end
end
else if (~Threshold1[i] & Threshold2[i]) begin
Threshold3[i] <= 1;
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
end
end
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[12];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter;
always @(posedge clk_flash) if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
wire selftrig;
assign selftrig = (trigchannels[0]&&selftrigtemp[0])||(trigchannels[1]&&selftrigtemp[1])||(trigchannels[2]&&selftrigtemp[2])||(trigchannels[3]&&selftrigtemp[3]) ||(rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
always @(posedge clk_flash)
if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];
always @(posedge clk_flash)
if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;
always @(posedge clk_flash)
if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;
reg startAcquisition;
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger;
else if(AcquiringAndTriggered2) startAcquisition <= 0;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
integer state=INIT;
reg [31:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample] || downsample==0;
always @(posedge clk_flash) begin
case (state)
INIT: begin
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1;
HaveFullData <= 0;
PreOrPostAcquiring <= 1;
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin
AcquiringAndTriggered <= 1;
PreOrPostAcquiring <= 1;
wraddress_triggerpoint <= wraddress;
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp) begin
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres && downsample>0) begin
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample;
dout2=highres2>>downsample;
dout3=highres3>>downsample;
dout4=highres4>>downsample;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
if (startAcquisition) data_ready=0;
else if (HaveFullData2) data_ready=1;
end
endmodule | 93 |
5,032 | data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v | 112,978,342 | serialprocessor.v | v | 1,100 | 197 | [] | [] | [] | null | line:54: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:231: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h21\' generates 8 bits.\n : ... In instance processor\n i2c_addr=8\'h21; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:334: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n : ... In instance processor\n else getadcadr<=(readdata-110); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:345: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n nsamp=256*extradata[0]+extradata[1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:356: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n triggerpoint=256*extradata[0]+extradata[1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:368: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n nsmp=256*extradata[0]+extradata[1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:379: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n sendincrement=extradata[0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:390: Operator SUB expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n clockbitstowaitlockin = extradata[0]-2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:400: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n clockbitstowait=extradata[0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:428: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n triggertype=extradata[0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:438: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n triggertot=256*extradata[0]+extradata[1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:501: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance processor\n i2c_addr=8\'h20; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:519: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n serialdelaytimerwait=50*(256*extradata[0]+extradata[1]); \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:532: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n i2c_datacounttosend=extradata[0]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:533: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n i2c_addr=extradata[1]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:557: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n lockinnumtoshift = 256*extradata[0]+extradata[1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:589: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n : ... In instance processor\n i2c_addr=8\'h20; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:640: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n blockstosend = extradata[0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:650: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n : ... In instance processor\n i2c_addr=extradata[0]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:723: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output3\' generates 8 bits.\n : ... In instance processor\n chan2mean = chan2mean + ram_output3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:724: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output4\' generates 8 bits.\n : ... In instance processor\n chan3mean = chan3mean + ram_output4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:735: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n : ... In instance processor\n lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean); \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:735: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n : ... In instance processor\n lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean); \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:734: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n : ... In instance processor\n if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:734: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n : ... In instance processor\n if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:741: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n : ... In instance processor\n lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean); \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:741: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n : ... In instance processor\n lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean); \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:740: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n : ... In instance processor\n if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:740: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n : ... In instance processor\n if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:750: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'rdaddress\' generates 12 bits.\n : ... In instance processor\n if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:750: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n : ... In instance processor\n if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:795: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'numlockinbytes\' generates 8 bits.\n : ... In instance processor\n if (ioCount < numlockinbytes-1) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:853: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance processor\n if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:883: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'usb2counter\' generates 8 bits.\n : ... In instance processor\n if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:917: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance processor\n if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:903: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'usb2counter\' generates 8 bits.\n : ... In instance processor\n if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:945: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 12 bits.\n : ... In instance processor\n if (writesamp>=(nsamp-1)) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:961: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n : ... In instance processor\n if (writebyte) txData=adcramdata[11:8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:971: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 12 bits.\n : ... In instance processor\n if (writesamp>(nsamp-1)) state=READ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1043: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n : ... In instance processor\n i2c_datawr = i2cdata[i2c_datacount];\n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1081: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n : ... In instance processor\n if (columndata[2:0]>b) screendata[b]=1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1081: Operator GT expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n : ... In instance processor\n if (columndata[2:0]>b) screendata[b]=1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1077: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'row\' generates 3 bits.\n : ... In instance processor\n if (columndata>=8*(row+1)) screendata = 8\'hff; \n ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1092: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n : ... In instance processor\n if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1095: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n : ... In instance processor\n if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:852: Comparison is constant due to unsigned arithmetic\n : ... In instance processor\n if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:916: Comparison is constant due to unsigned arithmetic\n : ... In instance processor\n if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin \n ^~\n%Error: Exiting due to 46 warning(s)\n' | 5,478 | module | module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,spare1,spare2,spare3,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug,
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror, usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdaddress2,trigthresh2, debug1,debug2,chip_id, highres, use_ext_trig, digital_buffer1, nsmp);
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
output reg[7:0] readdata;
output reg spare1,spare2,spare3;
reg led1,led2,led3,led4,led5,led6,led7,led8;
output reg get_ext_data;
input ext_data_ready;
parameter ram_width=12;
input wire[ram_width-1:0] wraddress_triggerpoint;
output reg [ram_width-1:0] rdaddress;
output reg [ram_width-1:0] rdaddress2;
output reg [ram_width-1:0] triggerpoint;
output reg rden;
input wire [7:0] ram_output1;
input wire [7:0] ram_output2;
input wire [7:0] ram_output3;
input wire [7:0] ram_output4;
input wire [7:0] digital_buffer1;
output reg serial_passthrough;
output reg [1:0] master_clock;
output reg[7:0] comdata;
output reg newcomdata;
output reg imthelast;
output wire imthefirst;
output reg rollingtrigger;
input trigDebug;
input [11:0] adcdata;
input adcready;
input adcvalid;
output reg getadcdata;
output reg [4:0] getadcadr;
output reg adcreset;
output reg [11:0] writesamp;
output reg writeadc;
output reg [11:0] adctestout;
output reg [7:0] downsample;
output reg [7:0] screendata;
output reg screenwren=0;
output reg [9:0] screenaddr = 10'd0;
output reg screenreset=0;
output reg [7:0] trigthresh = 8'h80, trigthresh2=8'hff;
output reg [3:0] trigchannels = 4'b1111;
output reg [3:0] triggertype = 4'b0001;
output reg [ram_width:0] triggertot;
output reg [15:0] SPIsenddata;
output reg SPIsend;
input [7:0] delaycounter;
input [7:0] carrycounter;
input [3:0] SPIstate;
output wire[3:0] offset;
output reg[3:0] gainsw;
reg[3:0] oversamp;
output reg debug1,debug2;
input [63:0] chip_id;
output reg highres=0;
output reg use_ext_trig=0;
output reg i2c_ena;
output reg [6:0] i2c_addr;
output reg i2c_rw;
output reg [7:0] i2c_datawr;
input [7:0] i2c_datard;
input i2c_busy;
input i2c_ackerror;
reg [7:0] i2cdata[8];
reg [3:0] i2c_datacounttosend,i2c_datacount;
reg i2cgo=0;
reg i2cdoread=0;
localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9,
WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
WRITE_USB_EXT1=33, WRITE_USB_EXT2=34, WRITE_USB_EXT3=35, WRITE_USB_EXT4=36, WRITE_USB_EXT5=37;
integer state,i2cstate;
reg [7:0] myid;
assign imthefirst = (myid==0);
reg [7:0] extradata[10];
reg [ram_width+2:0] SendCount=0;
reg [2:0] blockstosend=4;
integer nsamp = 6;
input [11:0] adcramdata;
reg writebyte;
integer bytesread, byteswanted;
reg thecounterbit, thecounterbitlockin;
integer clockbitstowait=5, clockbitstowaitlockin=3;
reg [3:0] sendincrement = 0;
output reg [ram_width-1:0] nsmp = 0;
reg [7:0] chanforscreen=0;
reg autorearm=0;
integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
reg [7:0] usb2counter;
output reg do_usb=0;
input usb_clk60;
output reg [7:0] usb_dataio;
input usb_txe_busy;
output reg usb_wr, usb_siwu;
reg usb_txe_not_busy;
reg [5:0] screencolumndata [128];
integer ioCount, ioCountToSend;
reg[7:0] data[0:15];
reg [7:0] numlockinbytes=16;
integer lockinresult1;
integer lockinresult2;
reg [15:0] lockinnumtoshift = 0;
integer chan2mean, chan3mean;
reg calcmeans;
initial begin
state<=READ;
i2cstate<=READ;
myid<=200;
master_clock<=2'b00;
imthelast<=0;
rollingtrigger<=1;
triggerpoint<=(2**(ram_width-2));
downsample<=1;
serial_passthrough<=0;
usb_siwu<=1;
gainsw<=4'b0000;
oversamp<=4'b0011;
debug1<=0; debug2<=0;
spare1<=0;
spare2<=0;
spare3<=0;
led4<=1;
led5<=0;
led6<=0;
led7<=0;
led8<=0;
end
always @(posedge clk) begin
thecounter<=thecounter+1;
usb_txe_not_busy <= ~usb_txe_busy;
debug1 <= usb_txe_not_busy;
if ( imthelast & thecounter[26]==1'b1 ) begin
led1<=0; led2<=0; led3<=0;
end
else if (myid==0) begin
led1<=1; led2<=1; led3<=1;
end
else if (myid==1) begin
led1<=0; led2<=1; led3<=1;
end
else if (myid==2) begin
led1<=1; led2<=0; led3<=1;
end
else if (myid==3) begin
led1<=0; led2<=0; led3<=1;
end
else if (myid==4) begin
led1<=1; led2<=1; led3<=0;
end
else begin
led1<=0; led2<=0; led3<=0;
end
end
reg oldled1,oldled2,oldled3,oldled4,oldled5,oldled6,oldled7,oldled8;
always @(posedge clk) begin
case (state)
READ: begin
get_ext_data<=0;
adcreset<=1;
txStart<=0;
getadcdata<=0;
bytesread<=0;
byteswanted<=0;
newcomdata<=0;
SPIsend<=0;
i2cgo=0;
usb_wr<=1;
ioCount = 0;
if (rxReady) begin
readdata = rxData;
state = SOLVING;
end
if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldled5!=led5 || oldled6!=led6 || oldled7!=led7 || oldled8!=led8) begin
oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
oldled5=led5; oldled6=led6; oldled7=led7; oldled8=led8;
i2c_datacounttosend=2;
i2c_addr=8'h21;
i2cdata[0]=8'h12;
i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
i2cdata[1][4]=led5; i2cdata[1][5]=led6; i2cdata[1][6]=led7; i2cdata[1][7]=led8;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
end
end
READMORE: begin
newcomdata=0;
if (rxReady) begin
extradata[bytesread] = rxData;
comdata=rxData;
newcomdata=1;
bytesread = bytesread+1;
if (bytesread>=byteswanted) state=SOLVING;
end
end
SOLVING: begin
if (readdata < 10) begin
myid=readdata;
if (readdata==0) begin
master_clock=2'b00;
end
else master_clock=2'b01;
comdata=(readdata+1);
newcomdata=1;
state=READ;
end
else if (readdata > 9 && readdata < 20) begin
if (myid==(readdata-10)) begin
serial_passthrough=0;
timeoutcounter=0;
state=WAITING;
end
else begin
serial_passthrough=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
end
else if (readdata > 19 && readdata < 30) begin
if (myid==(readdata-20)) imthelast=1;
else imthelast=0;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata > 29 && readdata < 40) begin
if (myid==(readdata-30)) begin
serial_passthrough=0;
end
else begin
serial_passthrough=1;
comdata=readdata;
newcomdata=1;
end
state=READ;
end
else if (100==readdata) begin
get_ext_data=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (101==readdata) begin
led5=1;
rollingtrigger=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (102==readdata) begin
led5=0;
rollingtrigger=0;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata>109 && readdata<120) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
if (readdata==119) getadcadr<=17;
else getadcadr<=(readdata-110);
writesamp<=0;
state=WAIT_ADC1;
end
end
else if (readdata==120) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
nsamp=256*extradata[0]+extradata[1];
if (nsamp>4095) nsamp=4095;
state=READ;
end
end
else if (readdata==121) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggerpoint=256*extradata[0]+extradata[1];
if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
else if (triggerpoint<4) triggerpoint=4;
state=READ;
end
end
else if (readdata==122) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
nsmp=256*extradata[0]+extradata[1];
if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
state=READ;
end
end
else if (readdata==123) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
sendincrement=extradata[0];
state=READ;
end
end
else if (readdata==124) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]>30) extradata[0]=30;
downsample=extradata[0];
clockbitstowaitlockin = extradata[0]-2;
state=READ;
end
end
else if (readdata==125) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]>30) extradata[0]=30;
clockbitstowait=extradata[0];
state=READ;
end
end
else if (readdata==126) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
chanforscreen=extradata[0];
state=READ;
end
end
else if (readdata==127) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
trigthresh=extradata[0];
state=READ;
end
end
else if (readdata==128) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggertype=extradata[0];
state=READ;
end
end
else if (readdata==129) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggertot=256*extradata[0]+extradata[1];
state=READ;
end
end
else if (readdata==130) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
end
state=READ;
end
end
else if (readdata==131) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
SPIsenddata[15:8]=extradata[0];
SPIsenddata[7:0]=extradata[1];
SPIsenddata[15]=1'b0;
SPIsend=1;
state=SPIWAIT;
end
end
else if (readdata==132) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=delaycounter;
state=WRITE1;
end
end
else if (readdata==133) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=carrycounter;
state=WRITE1;
end
end
else if (readdata==134) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
end
i2c_datacounttosend=2;
i2c_addr=8'h20;
i2cdata[0]=8'h12;
i2cdata[1][3:0]=gainsw;
i2cdata[1][7:4]=oversamp;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (readdata==135) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
state=READ;
end
end
else if (readdata==136) begin
byteswanted=6;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
i2c_datacounttosend=extradata[0];
i2c_addr=extradata[1];
i2cdata[0]=extradata[2];
i2cdata[1]=extradata[3];
i2cdata[2]=extradata[4];
if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (137==readdata) begin
do_usb=~do_usb;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==138) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
lockinnumtoshift = 256*extradata[0]+extradata[1];
state=READ;
end
end
else if (139==readdata) begin
autorearm=~autorearm;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==140) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
trigthresh2 = extradata[0];
state=READ;
end
end
else if (readdata==141) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
end
i2c_datacounttosend=2;
i2c_addr=8'h20;
i2cdata[0]=8'h12;
i2cdata[1][3:0]=gainsw;
i2cdata[1][7:4]=oversamp;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (readdata==142) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
data[0]=chip_id[7+8*0:8*0];
data[1]=chip_id[7+8*1:8*1];
data[2]=chip_id[7+8*2:8*2];
data[3]=chip_id[7+8*3:8*3];
data[4]=chip_id[7+8*4:8*4];
data[5]=chip_id[7+8*5:8*5];
data[6]=chip_id[7+8*6:8*6];
data[7]=chip_id[7+8*7:8*7];
ioCountToSend = 8;
state=WRITE1;
end
end
else if (143==readdata) begin
highres=~highres;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (144==readdata) begin
use_ext_trig=~use_ext_trig;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==145) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
blockstosend = extradata[0];
state=READ;
end
end
else if (readdata==146) begin
byteswanted=3;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
i2c_addr=extradata[0];
i2c_datacounttosend=2;
i2cdata[0]=extradata[1];
i2cdata[1]=0;
if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
i2cdoread = 1;
i2cgo=1;
ioCountToSend = 1;
data[0] = i2c_datard;
state=WRITE1;
end
else state=READ;
end
end
else if (readdata==147) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=5;
state=WRITE1;
end
end
else state=READ;
end
SPIWAIT: begin
newcomdata<=0;
if (SPIstate==3) begin
state=READ;
end
end
WAITING: begin
timeoutcounter=timeoutcounter+1;
if (ext_data_ready) begin
SendCount= 0;
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
thecounterbit=thecounter[clockbitstowait];
thecounterbitlockin=thecounter[clockbitstowaitlockin];
if (lockinnumtoshift>0) begin
lockinresult1=0;
lockinresult2=0;
chan2mean=0;
chan3mean=0;
calcmeans=1;
state=LOCKIN1;
end
else begin
if (do_usb) state=WRITE_USB_EXT1;
else state=WRITE_EXT1;
end
end
if ( timeoutcounter > 100000000 ) begin
state=READ;
end
end
LOCKIN1: begin
rden = 1;
if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
case(SendCount[ram_width+1:ram_width])
0: begin
chan2mean = chan2mean + ram_output3;
chan3mean = chan3mean + ram_output4;
end
1: begin
if (calcmeans) begin
calcmeans=0;
chan2mean = chan2mean/4096;
chan3mean = chan3mean/4096;
end
if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
end
end
2: begin
if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
end
end
3: begin
end
endcase
SendCount = SendCount + 1;
rdaddress = rdaddress + 1;
if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;
else rdaddress2=rdaddress;
state=LOCKIN2;
end
end
LOCKIN2: begin
state=LOCKIN3;
end
LOCKIN3: begin
if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
if(SendCount[ram_width+1:0]==0) begin
ioCount = 0;
SendCount = 0;
state=LOCKINWRITE1;
end
else begin
state=LOCKIN1;
end
end
end
LOCKINWRITE1: begin
if (!txBusy) begin
if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];
else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
else txData = 0;
txStart = 1;
state = LOCKINWRITE2;
end
end
LOCKINWRITE2: begin
txStart = 0;
if (ioCount < numlockinbytes-1) begin
ioCount = ioCount + 1;
state = LOCKINWRITE1;
end
else begin
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
thecounterbit=thecounter[clockbitstowait];
if (do_usb) state=WRITE_USB_EXT1;
else state=WRITE_EXT1;
end
end
WRITE_EXT1: begin
timeoutcounter=timeoutcounter+1;
rden = 1;
case(SendCount[ram_width+2:ram_width])
0: txData<=ram_output1;
1: txData<=ram_output2;
2: txData<=ram_output3;
3: txData<=ram_output4;
4: txData<=digital_buffer1;
endcase
if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
txStart<= 1;
SendCount = SendCount + (2**sendincrement);
rdaddress = rdaddress + (2**sendincrement);
rdaddress2 = rdaddress;
if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
SendCount[ram_width-1:0]=0;
SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
end
state=WRITE_EXT2;
end
if ( timeoutcounter > 100000000 ) begin
rden = 0;
state=READ;
end
end
WRITE_EXT2: begin
if( thecounter[clockbitstowait]==thecounterbit ) begin
txStart<= 0;
if(SendCount[ram_width+2:ram_width]==blockstosend) begin
rden = 0;
if (autorearm) begin
get_ext_data=1;
end
state=READ;
end
else begin
if(SendCount[4:0]==0 && serialdelaytimer<serialdelaytimerwait) begin
serialdelaytimer=serialdelaytimer+1;
end
else begin
if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
screenwren = 1;
end
serialdelaytimer=0;
state=WRITE_EXT1;
end
end
end
end
WRITE_USB_EXT1: begin
if (usb_txe_not_busy) begin
thecounterbit=thecounter[clockbitstowait];
usb2counter<=0;
state=WRITE_USB_EXT2;
end
debug2<=1;
rden = 1;
end
WRITE_USB_EXT2: begin
debug2<=0;
usb2counter<=usb2counter+1;
case(SendCount[ram_width+2:ram_width])
0: usb_dataio<=ram_output1;
1: usb_dataio<=ram_output2;
2: usb_dataio<=ram_output3;
3: usb_dataio<=ram_output4;
4: usb_dataio<=digital_buffer1;
endcase
if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
SendCount = SendCount + (2**sendincrement);
rdaddress = rdaddress + (2**sendincrement);
rdaddress2 = rdaddress;
if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
SendCount[ram_width-1:0]=0;
SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
end
state=WRITE_USB_EXT3;
end
end
WRITE_USB_EXT3: begin
usb_wr<= 0;
usb2counter<=0;
state=WRITE_USB_EXT4;
end
WRITE_USB_EXT4: begin
usb2counter=usb2counter+1;
if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
usb_wr<= 1;
if(SendCount[ram_width+2:ram_width]==blockstosend) begin
rden = 0;
if (autorearm) begin
get_ext_data=1;
end
state=WRITE_USB_EXT5;
end
else begin
usb2counter=0;
state=WRITE_USB_EXT1;
if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
screenwren = 1;
end
end
end
end
WRITE_USB_EXT5: begin
usb_siwu=0;
usb2counter<=usb2counter+1;
if( (usb2counter>8) ) begin
state=READ;
usb_siwu=1;
end
end
WAIT_ADC1: begin
newcomdata<=0;
writeadc<=0;
getadcdata<=1;
state=WAIT_ADC2;
end
WAIT_ADC2: begin
if (adcvalid) begin
adctestout<=adcdata;
writeadc<=1;
getadcdata<=0;
if (writesamp>=(nsamp-1)) begin
writesamp<=0;
writebyte<=0;
thecounterbit=thecounter[clockbitstowait];
state<=WRITE_BYTE1;
end
else begin
writesamp=writesamp+1;
state=WAIT_ADC1;
end
end
end
WRITE_BYTE1: begin
newcomdata<=0;
writeadc<=0;
if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
if (writebyte) txData=adcramdata[11:8];
else txData=adcramdata[7:0];
txStart=1;
state=WRITE_BYTE2;
end
end
WRITE_BYTE2: begin
txStart=0;
if (writebyte) writesamp=writesamp+1;
writebyte = ~writebyte;
if (writesamp>(nsamp-1)) state=READ;
else state=WRITE_BYTE1;
end
WRITE1: begin
newcomdata<=0;
if (!txBusy) begin
txData = data[ioCount];
txStart = 1;
state = WRITE2;
end
end
WRITE2: begin
txStart = 0;
if (ioCount < ioCountToSend-1) begin
ioCount = ioCount + 1;
state = WRITE1;
end else begin
state = READ;
end
end
endcase
end
always @(posedge clk) begin
case (i2cstate)
READ: begin
i2c_ena<=0;
if (i2cgo) begin
i2cstate=I2CWAIT;
end
end
I2CWAIT: begin
if (~i2c_busy) begin
i2c_rw=0;
i2c_datawr = i2cdata[0];
i2c_datacount=1;
i2cstate=I2CSEND1;
end
end
I2CSEND1: begin
i2c_ena = 1;
if (i2c_datacount >= i2c_datacounttosend) begin
i2cstate=READ;
end
else if (i2c_busy) begin
i2c_datawr = i2cdata[i2c_datacount];
if (i2cdoread) begin
i2c_rw=1;
end
i2cstate=I2CSEND2;
end
end
I2CSEND2: begin
if (~i2c_busy) begin
i2c_datacount = i2c_datacount+1;
i2cstate=I2CSEND1;
end
end
endcase
end
reg [5:0] columndata;
reg [2:0] row;
reg [6:0] column;
reg [3:0] b;
always @(posedge clk) begin
if (screenaddr>1000) screenreset<=1;
screenaddr = screenaddr + 1;
row=7-screenaddr[9:7];
column=screenaddr[6:0];
columndata = screencolumndata[column];
if (columndata>=8*(row+1)) screendata = 8'hff;
else if (columndata>=8*row) begin
screendata=8'h00; b=0;
while (b<8) begin
if (columndata[2:0]>b) screendata[b]=1;
b=b+1;
end
end
else screendata = 8'h00;
if (row==7 & trigDebug) begin
if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
end
if (row==6 & !trigDebug) begin
if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
end
end
endmodule | module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,spare1,spare2,spare3,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug,
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror, usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdaddress2,trigthresh2, debug1,debug2,chip_id, highres, use_ext_trig, digital_buffer1, nsmp); |
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
output reg[7:0] readdata;
output reg spare1,spare2,spare3;
reg led1,led2,led3,led4,led5,led6,led7,led8;
output reg get_ext_data;
input ext_data_ready;
parameter ram_width=12;
input wire[ram_width-1:0] wraddress_triggerpoint;
output reg [ram_width-1:0] rdaddress;
output reg [ram_width-1:0] rdaddress2;
output reg [ram_width-1:0] triggerpoint;
output reg rden;
input wire [7:0] ram_output1;
input wire [7:0] ram_output2;
input wire [7:0] ram_output3;
input wire [7:0] ram_output4;
input wire [7:0] digital_buffer1;
output reg serial_passthrough;
output reg [1:0] master_clock;
output reg[7:0] comdata;
output reg newcomdata;
output reg imthelast;
output wire imthefirst;
output reg rollingtrigger;
input trigDebug;
input [11:0] adcdata;
input adcready;
input adcvalid;
output reg getadcdata;
output reg [4:0] getadcadr;
output reg adcreset;
output reg [11:0] writesamp;
output reg writeadc;
output reg [11:0] adctestout;
output reg [7:0] downsample;
output reg [7:0] screendata;
output reg screenwren=0;
output reg [9:0] screenaddr = 10'd0;
output reg screenreset=0;
output reg [7:0] trigthresh = 8'h80, trigthresh2=8'hff;
output reg [3:0] trigchannels = 4'b1111;
output reg [3:0] triggertype = 4'b0001;
output reg [ram_width:0] triggertot;
output reg [15:0] SPIsenddata;
output reg SPIsend;
input [7:0] delaycounter;
input [7:0] carrycounter;
input [3:0] SPIstate;
output wire[3:0] offset;
output reg[3:0] gainsw;
reg[3:0] oversamp;
output reg debug1,debug2;
input [63:0] chip_id;
output reg highres=0;
output reg use_ext_trig=0;
output reg i2c_ena;
output reg [6:0] i2c_addr;
output reg i2c_rw;
output reg [7:0] i2c_datawr;
input [7:0] i2c_datard;
input i2c_busy;
input i2c_ackerror;
reg [7:0] i2cdata[8];
reg [3:0] i2c_datacounttosend,i2c_datacount;
reg i2cgo=0;
reg i2cdoread=0;
localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9,
WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
WRITE_USB_EXT1=33, WRITE_USB_EXT2=34, WRITE_USB_EXT3=35, WRITE_USB_EXT4=36, WRITE_USB_EXT5=37;
integer state,i2cstate;
reg [7:0] myid;
assign imthefirst = (myid==0);
reg [7:0] extradata[10];
reg [ram_width+2:0] SendCount=0;
reg [2:0] blockstosend=4;
integer nsamp = 6;
input [11:0] adcramdata;
reg writebyte;
integer bytesread, byteswanted;
reg thecounterbit, thecounterbitlockin;
integer clockbitstowait=5, clockbitstowaitlockin=3;
reg [3:0] sendincrement = 0;
output reg [ram_width-1:0] nsmp = 0;
reg [7:0] chanforscreen=0;
reg autorearm=0;
integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
reg [7:0] usb2counter;
output reg do_usb=0;
input usb_clk60;
output reg [7:0] usb_dataio;
input usb_txe_busy;
output reg usb_wr, usb_siwu;
reg usb_txe_not_busy;
reg [5:0] screencolumndata [128];
integer ioCount, ioCountToSend;
reg[7:0] data[0:15];
reg [7:0] numlockinbytes=16;
integer lockinresult1;
integer lockinresult2;
reg [15:0] lockinnumtoshift = 0;
integer chan2mean, chan3mean;
reg calcmeans;
initial begin
state<=READ;
i2cstate<=READ;
myid<=200;
master_clock<=2'b00;
imthelast<=0;
rollingtrigger<=1;
triggerpoint<=(2**(ram_width-2));
downsample<=1;
serial_passthrough<=0;
usb_siwu<=1;
gainsw<=4'b0000;
oversamp<=4'b0011;
debug1<=0; debug2<=0;
spare1<=0;
spare2<=0;
spare3<=0;
led4<=1;
led5<=0;
led6<=0;
led7<=0;
led8<=0;
end
always @(posedge clk) begin
thecounter<=thecounter+1;
usb_txe_not_busy <= ~usb_txe_busy;
debug1 <= usb_txe_not_busy;
if ( imthelast & thecounter[26]==1'b1 ) begin
led1<=0; led2<=0; led3<=0;
end
else if (myid==0) begin
led1<=1; led2<=1; led3<=1;
end
else if (myid==1) begin
led1<=0; led2<=1; led3<=1;
end
else if (myid==2) begin
led1<=1; led2<=0; led3<=1;
end
else if (myid==3) begin
led1<=0; led2<=0; led3<=1;
end
else if (myid==4) begin
led1<=1; led2<=1; led3<=0;
end
else begin
led1<=0; led2<=0; led3<=0;
end
end
reg oldled1,oldled2,oldled3,oldled4,oldled5,oldled6,oldled7,oldled8;
always @(posedge clk) begin
case (state)
READ: begin
get_ext_data<=0;
adcreset<=1;
txStart<=0;
getadcdata<=0;
bytesread<=0;
byteswanted<=0;
newcomdata<=0;
SPIsend<=0;
i2cgo=0;
usb_wr<=1;
ioCount = 0;
if (rxReady) begin
readdata = rxData;
state = SOLVING;
end
if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldled5!=led5 || oldled6!=led6 || oldled7!=led7 || oldled8!=led8) begin
oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
oldled5=led5; oldled6=led6; oldled7=led7; oldled8=led8;
i2c_datacounttosend=2;
i2c_addr=8'h21;
i2cdata[0]=8'h12;
i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
i2cdata[1][4]=led5; i2cdata[1][5]=led6; i2cdata[1][6]=led7; i2cdata[1][7]=led8;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
end
end
READMORE: begin
newcomdata=0;
if (rxReady) begin
extradata[bytesread] = rxData;
comdata=rxData;
newcomdata=1;
bytesread = bytesread+1;
if (bytesread>=byteswanted) state=SOLVING;
end
end
SOLVING: begin
if (readdata < 10) begin
myid=readdata;
if (readdata==0) begin
master_clock=2'b00;
end
else master_clock=2'b01;
comdata=(readdata+1);
newcomdata=1;
state=READ;
end
else if (readdata > 9 && readdata < 20) begin
if (myid==(readdata-10)) begin
serial_passthrough=0;
timeoutcounter=0;
state=WAITING;
end
else begin
serial_passthrough=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
end
else if (readdata > 19 && readdata < 30) begin
if (myid==(readdata-20)) imthelast=1;
else imthelast=0;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata > 29 && readdata < 40) begin
if (myid==(readdata-30)) begin
serial_passthrough=0;
end
else begin
serial_passthrough=1;
comdata=readdata;
newcomdata=1;
end
state=READ;
end
else if (100==readdata) begin
get_ext_data=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (101==readdata) begin
led5=1;
rollingtrigger=1;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (102==readdata) begin
led5=0;
rollingtrigger=0;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata>109 && readdata<120) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
if (readdata==119) getadcadr<=17;
else getadcadr<=(readdata-110);
writesamp<=0;
state=WAIT_ADC1;
end
end
else if (readdata==120) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
nsamp=256*extradata[0]+extradata[1];
if (nsamp>4095) nsamp=4095;
state=READ;
end
end
else if (readdata==121) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggerpoint=256*extradata[0]+extradata[1];
if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
else if (triggerpoint<4) triggerpoint=4;
state=READ;
end
end
else if (readdata==122) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
nsmp=256*extradata[0]+extradata[1];
if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
state=READ;
end
end
else if (readdata==123) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
sendincrement=extradata[0];
state=READ;
end
end
else if (readdata==124) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]>30) extradata[0]=30;
downsample=extradata[0];
clockbitstowaitlockin = extradata[0]-2;
state=READ;
end
end
else if (readdata==125) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]>30) extradata[0]=30;
clockbitstowait=extradata[0];
state=READ;
end
end
else if (readdata==126) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
chanforscreen=extradata[0];
state=READ;
end
end
else if (readdata==127) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
trigthresh=extradata[0];
state=READ;
end
end
else if (readdata==128) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggertype=extradata[0];
state=READ;
end
end
else if (readdata==129) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
triggertot=256*extradata[0]+extradata[1];
state=READ;
end
end
else if (readdata==130) begin
comdata=readdata; newcomdata=1;
byteswanted=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
end
state=READ;
end
end
else if (readdata==131) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
SPIsenddata[15:8]=extradata[0];
SPIsenddata[7:0]=extradata[1];
SPIsenddata[15]=1'b0;
SPIsend=1;
state=SPIWAIT;
end
end
else if (readdata==132) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=delaycounter;
state=WRITE1;
end
end
else if (readdata==133) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=carrycounter;
state=WRITE1;
end
end
else if (readdata==134) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
end
i2c_datacounttosend=2;
i2c_addr=8'h20;
i2cdata[0]=8'h12;
i2cdata[1][3:0]=gainsw;
i2cdata[1][7:4]=oversamp;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (readdata==135) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
state=READ;
end
end
else if (readdata==136) begin
byteswanted=6;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
i2c_datacounttosend=extradata[0];
i2c_addr=extradata[1];
i2cdata[0]=extradata[2];
i2cdata[1]=extradata[3];
i2cdata[2]=extradata[4];
if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (137==readdata) begin
do_usb=~do_usb;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==138) begin
byteswanted=2;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
lockinnumtoshift = 256*extradata[0]+extradata[1];
state=READ;
end
end
else if (139==readdata) begin
autorearm=~autorearm;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==140) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
trigthresh2 = extradata[0];
state=READ;
end
end
else if (readdata==141) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
if (extradata[0]/4 ==myid) begin
oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
end
i2c_datacounttosend=2;
i2c_addr=8'h20;
i2cdata[0]=8'h12;
i2cdata[1][3:0]=gainsw;
i2cdata[1][7:4]=oversamp;
i2cdata[2]=0;
if (i2cstate==READ) begin
i2cdoread = 0;
i2cgo=1;
end
state=READ;
end
end
else if (readdata==142) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
data[0]=chip_id[7+8*0:8*0];
data[1]=chip_id[7+8*1:8*1];
data[2]=chip_id[7+8*2:8*2];
data[3]=chip_id[7+8*3:8*3];
data[4]=chip_id[7+8*4:8*4];
data[5]=chip_id[7+8*5:8*5];
data[6]=chip_id[7+8*6:8*6];
data[7]=chip_id[7+8*7:8*7];
ioCountToSend = 8;
state=WRITE1;
end
end
else if (143==readdata) begin
highres=~highres;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (144==readdata) begin
use_ext_trig=~use_ext_trig;
comdata=readdata;
newcomdata=1;
state=READ;
end
else if (readdata==145) begin
byteswanted=1;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
blockstosend = extradata[0];
state=READ;
end
end
else if (readdata==146) begin
byteswanted=3;
comdata=readdata;
newcomdata=1;
if (bytesread<byteswanted) state=READMORE;
else begin
i2c_addr=extradata[0];
i2c_datacounttosend=2;
i2cdata[0]=extradata[1];
i2cdata[1]=0;
if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
i2cdoread = 1;
i2cgo=1;
ioCountToSend = 1;
data[0] = i2c_datard;
state=WRITE1;
end
else state=READ;
end
end
else if (readdata==147) begin
if (serial_passthrough) begin
comdata=readdata;
newcomdata=1;
state=READ;
end
else begin
ioCountToSend = 1;
data[0]=5;
state=WRITE1;
end
end
else state=READ;
end
SPIWAIT: begin
newcomdata<=0;
if (SPIstate==3) begin
state=READ;
end
end
WAITING: begin
timeoutcounter=timeoutcounter+1;
if (ext_data_ready) begin
SendCount= 0;
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
thecounterbit=thecounter[clockbitstowait];
thecounterbitlockin=thecounter[clockbitstowaitlockin];
if (lockinnumtoshift>0) begin
lockinresult1=0;
lockinresult2=0;
chan2mean=0;
chan3mean=0;
calcmeans=1;
state=LOCKIN1;
end
else begin
if (do_usb) state=WRITE_USB_EXT1;
else state=WRITE_EXT1;
end
end
if ( timeoutcounter > 100000000 ) begin
state=READ;
end
end
LOCKIN1: begin
rden = 1;
if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
case(SendCount[ram_width+1:ram_width])
0: begin
chan2mean = chan2mean + ram_output3;
chan3mean = chan3mean + ram_output4;
end
1: begin
if (calcmeans) begin
calcmeans=0;
chan2mean = chan2mean/4096;
chan3mean = chan3mean/4096;
end
if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
end
end
2: begin
if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
end
end
3: begin
end
endcase
SendCount = SendCount + 1;
rdaddress = rdaddress + 1;
if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;
else rdaddress2=rdaddress;
state=LOCKIN2;
end
end
LOCKIN2: begin
state=LOCKIN3;
end
LOCKIN3: begin
if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
if(SendCount[ram_width+1:0]==0) begin
ioCount = 0;
SendCount = 0;
state=LOCKINWRITE1;
end
else begin
state=LOCKIN1;
end
end
end
LOCKINWRITE1: begin
if (!txBusy) begin
if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];
else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
else txData = 0;
txStart = 1;
state = LOCKINWRITE2;
end
end
LOCKINWRITE2: begin
txStart = 0;
if (ioCount < numlockinbytes-1) begin
ioCount = ioCount + 1;
state = LOCKINWRITE1;
end
else begin
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
thecounterbit=thecounter[clockbitstowait];
if (do_usb) state=WRITE_USB_EXT1;
else state=WRITE_EXT1;
end
end
WRITE_EXT1: begin
timeoutcounter=timeoutcounter+1;
rden = 1;
case(SendCount[ram_width+2:ram_width])
0: txData<=ram_output1;
1: txData<=ram_output2;
2: txData<=ram_output3;
3: txData<=ram_output4;
4: txData<=digital_buffer1;
endcase
if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
txStart<= 1;
SendCount = SendCount + (2**sendincrement);
rdaddress = rdaddress + (2**sendincrement);
rdaddress2 = rdaddress;
if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
SendCount[ram_width-1:0]=0;
SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
end
state=WRITE_EXT2;
end
if ( timeoutcounter > 100000000 ) begin
rden = 0;
state=READ;
end
end
WRITE_EXT2: begin
if( thecounter[clockbitstowait]==thecounterbit ) begin
txStart<= 0;
if(SendCount[ram_width+2:ram_width]==blockstosend) begin
rden = 0;
if (autorearm) begin
get_ext_data=1;
end
state=READ;
end
else begin
if(SendCount[4:0]==0 && serialdelaytimer<serialdelaytimerwait) begin
serialdelaytimer=serialdelaytimer+1;
end
else begin
if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
screenwren = 1;
end
serialdelaytimer=0;
state=WRITE_EXT1;
end
end
end
end
WRITE_USB_EXT1: begin
if (usb_txe_not_busy) begin
thecounterbit=thecounter[clockbitstowait];
usb2counter<=0;
state=WRITE_USB_EXT2;
end
debug2<=1;
rden = 1;
end
WRITE_USB_EXT2: begin
debug2<=0;
usb2counter<=usb2counter+1;
case(SendCount[ram_width+2:ram_width])
0: usb_dataio<=ram_output1;
1: usb_dataio<=ram_output2;
2: usb_dataio<=ram_output3;
3: usb_dataio<=ram_output4;
4: usb_dataio<=digital_buffer1;
endcase
if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
SendCount = SendCount + (2**sendincrement);
rdaddress = rdaddress + (2**sendincrement);
rdaddress2 = rdaddress;
if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
SendCount[ram_width-1:0]=0;
SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
rdaddress = wraddress_triggerpoint - triggerpoint;
rdaddress2 = rdaddress;
end
state=WRITE_USB_EXT3;
end
end
WRITE_USB_EXT3: begin
usb_wr<= 0;
usb2counter<=0;
state=WRITE_USB_EXT4;
end
WRITE_USB_EXT4: begin
usb2counter=usb2counter+1;
if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
usb_wr<= 1;
if(SendCount[ram_width+2:ram_width]==blockstosend) begin
rden = 0;
if (autorearm) begin
get_ext_data=1;
end
state=WRITE_USB_EXT5;
end
else begin
usb2counter=0;
state=WRITE_USB_EXT1;
if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
screenwren = 1;
end
end
end
end
WRITE_USB_EXT5: begin
usb_siwu=0;
usb2counter<=usb2counter+1;
if( (usb2counter>8) ) begin
state=READ;
usb_siwu=1;
end
end
WAIT_ADC1: begin
newcomdata<=0;
writeadc<=0;
getadcdata<=1;
state=WAIT_ADC2;
end
WAIT_ADC2: begin
if (adcvalid) begin
adctestout<=adcdata;
writeadc<=1;
getadcdata<=0;
if (writesamp>=(nsamp-1)) begin
writesamp<=0;
writebyte<=0;
thecounterbit=thecounter[clockbitstowait];
state<=WRITE_BYTE1;
end
else begin
writesamp=writesamp+1;
state=WAIT_ADC1;
end
end
end
WRITE_BYTE1: begin
newcomdata<=0;
writeadc<=0;
if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
if (writebyte) txData=adcramdata[11:8];
else txData=adcramdata[7:0];
txStart=1;
state=WRITE_BYTE2;
end
end
WRITE_BYTE2: begin
txStart=0;
if (writebyte) writesamp=writesamp+1;
writebyte = ~writebyte;
if (writesamp>(nsamp-1)) state=READ;
else state=WRITE_BYTE1;
end
WRITE1: begin
newcomdata<=0;
if (!txBusy) begin
txData = data[ioCount];
txStart = 1;
state = WRITE2;
end
end
WRITE2: begin
txStart = 0;
if (ioCount < ioCountToSend-1) begin
ioCount = ioCount + 1;
state = WRITE1;
end else begin
state = READ;
end
end
endcase
end
always @(posedge clk) begin
case (i2cstate)
READ: begin
i2c_ena<=0;
if (i2cgo) begin
i2cstate=I2CWAIT;
end
end
I2CWAIT: begin
if (~i2c_busy) begin
i2c_rw=0;
i2c_datawr = i2cdata[0];
i2c_datacount=1;
i2cstate=I2CSEND1;
end
end
I2CSEND1: begin
i2c_ena = 1;
if (i2c_datacount >= i2c_datacounttosend) begin
i2cstate=READ;
end
else if (i2c_busy) begin
i2c_datawr = i2cdata[i2c_datacount];
if (i2cdoread) begin
i2c_rw=1;
end
i2cstate=I2CSEND2;
end
end
I2CSEND2: begin
if (~i2c_busy) begin
i2c_datacount = i2c_datacount+1;
i2cstate=I2CSEND1;
end
end
endcase
end
reg [5:0] columndata;
reg [2:0] row;
reg [6:0] column;
reg [3:0] b;
always @(posedge clk) begin
if (screenaddr>1000) screenreset<=1;
screenaddr = screenaddr + 1;
row=7-screenaddr[9:7];
column=screenaddr[6:0];
columndata = screencolumndata[column];
if (columndata>=8*(row+1)) screendata = 8'hff;
else if (columndata>=8*row) begin
screendata=8'h00; b=0;
while (b<8) begin
if (columndata[2:0]>b) screendata[b]=1;
b=b+1;
end
end
else screendata = 8'h00;
if (row==7 & trigDebug) begin
if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
end
if (row==6 & !trigDebug) begin
if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
end
end
endmodule | 93 |
5,033 | data/full_repos/permissive/113002755/verilog/Asteroids.v | 113,002,755 | Asteroids.v | v | 1,243 | 242 | [] | [] | [] | null | line:597: before: "." | null | 1: b"%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:253: Cannot find file containing module: 'vgaClk'\nvgaClk u2\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/vgaClk\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/vgaClk.v\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/vgaClk.sv\n vgaClk\n vgaClk.v\n vgaClk.sv\n obj_dir/vgaClk\n obj_dir/vgaClk.v\n obj_dir/vgaClk.sv\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:274: Cannot find file containing module: 'VGA_Ctrl'\nVGA_Ctrl u3\n^~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:293: Cannot find file containing module: 'VGA_Drive'\nVGA_Drive u4\n^~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:373: Cannot find file containing module: 'Digit'\nDigit d1 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:391: Cannot find file containing module: 'Digit'\nDigit d2 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:409: Cannot find file containing module: 'Digit'\nDigit d3 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:427: Cannot find file containing module: 'Digit'\nDigit d4 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:445: Cannot find file containing module: 'Digit'\nDigit d5 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:463: Cannot find file containing module: 'Digit'\nDigit d6 (\n^~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:491: Cannot find file containing module: 'Hex2BCD'\nHex2BCD h2d(\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:521: Cannot find file containing module: 'memClk'\nmemClk mk (\n^~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:530: Cannot find file containing module: 'GameOver'\nGameOver go (\n^~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:549: Cannot find file containing module: 'keyboard'\n keyboard kb(mClk, PS2_KBCLK, PS2_KBDAT, RST, scancode, VB);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:581: Cannot find file containing module: 'CommandShip'\nCommandShip ship\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:600: Cannot find file containing module: 'CommandShip'\nCommandShip spare1\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:618: Cannot find file containing module: 'CommandShip'\nCommandShip spare2\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:636: Cannot find file containing module: 'CommandShip'\nCommandShip spare3\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:659: Cannot find file containing module: 'spareShipDecode'\nspareShipDecode ssd (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:731: Cannot find file containing module: 'oneshot'\noneshot os(fireBtn, mClk, fire);\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:750: Cannot find file containing module: 'fireDecode'\nfireDecode fd (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:762: Cannot find file containing module: 'Torpedo'\nTorpedo t0\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:777: Cannot find file containing module: 'Torpedo'\nTorpedo t1\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:792: Cannot find file containing module: 'Torpedo'\nTorpedo t2\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:807: Cannot find file containing module: 'Torpedo'\nTorpedo t3\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:822: Cannot find file containing module: 'Torpedo'\nTorpedo t4\n^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:837: Cannot find file containing module: 'Torpedo'\n Torpedo t5\n ^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:852: Cannot find file containing module: 'Torpedo'\n Torpedo t6\n ^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:867: Cannot find file containing module: 'Torpedo'\n Torpedo t7\n ^~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:889: Cannot find file containing module: 'asteroid_placer'\n asteroid_placer ap (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:911: Cannot find file containing module: 'asteroid_controller'\nasteroid_controller cont (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:925: Cannot find file containing module: 'asteroid_decode'\nasteroid_decode ast (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:951: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a0\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:969: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a1\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:988: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a2\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1007: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a3\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1025: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a4\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1043: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a5\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1061: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a6\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1079: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a7\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1097: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a8\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1115: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a9\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1134: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a10\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1153: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a11\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1171: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a12\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1189: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a13\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1207: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a14\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113002755/verilog/Asteroids.v:1225: Cannot find file containing module: 'asteroid_8x8'\n asteroid_8x8 a15\n ^~~~~~~~~~~~\n%Error: Exiting due to 47 error(s)\n" | 5,500 | module | module Asteroids (
CLOCK_50,
CLOCK_50_2,
BUTTON,
SW,
HEX0_D,
HEX0_DP,
HEX1_D,
HEX1_DP,
HEX2_D,
HEX2_DP,
HEX3_D,
HEX3_DP,
LEDG,
UART_TXD,
UART_RXD,
UART_CTS,
UART_RTS,
DRAM_DQ,
DRAM_ADDR,
DRAM_LDQM,
DRAM_UDQM,
DRAM_WE_N,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CS_N,
DRAM_BA_0,
DRAM_BA_1,
DRAM_CLK,
DRAM_CKE,
FL_DQ,
FL_DQ15_AM1,
FL_ADDR,
FL_WE_N,
FL_RST_N,
FL_OE_N,
FL_CE_N,
FL_WP_N,
FL_BYTE_N,
FL_RY,
LCD_BLON,
LCD_RW,
LCD_EN,
LCD_RS,
LCD_DATA,
SD_DAT0,
SD_DAT3,
SD_CMD,
SD_CLK,
SD_WP_N,
PS2_KBDAT,
PS2_KBCLK,
PS2_MSDAT,
PS2_MSCLK,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B,
GPIO0_CLKIN,
GPIO0_CLKOUT,
GPIO0_D,
GPIO1_CLKIN,
GPIO1_CLKOUT,
GPIO1_D
);
input CLOCK_50;
input CLOCK_50_2;
input [2:0] BUTTON;
input [9:0] SW;
output [6:0] HEX0_D;
output HEX0_DP;
output [6:0] HEX1_D;
output HEX1_DP;
output [6:0] HEX2_D;
output HEX2_DP;
output [6:0] HEX3_D;
output HEX3_DP;
output [9:0] LEDG;
output UART_TXD;
input UART_RXD;
output UART_CTS;
input UART_RTS;
inout [15:0] DRAM_DQ;
output [12:0] DRAM_ADDR;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_WE_N;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CS_N;
output DRAM_BA_0;
output DRAM_BA_1;
output DRAM_CLK;
output DRAM_CKE;
inout [14:0] FL_DQ;
inout FL_DQ15_AM1;
output [21:0] FL_ADDR;
output FL_WE_N;
output FL_RST_N;
output FL_OE_N;
output FL_CE_N;
output FL_WP_N;
output FL_BYTE_N;
input FL_RY;
inout [7:0] LCD_DATA;
output LCD_BLON;
output LCD_RW;
output LCD_EN;
output LCD_RS;
inout SD_DAT0;
inout SD_DAT3;
inout SD_CMD;
output SD_CLK;
input SD_WP_N;
inout PS2_KBDAT;
inout PS2_KBCLK;
inout PS2_MSDAT;
inout PS2_MSCLK;
output VGA_HS;
output VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
input [1:0] GPIO0_CLKIN;
output [1:0] GPIO0_CLKOUT;
inout [31:0] GPIO0_D;
input [1:0] GPIO1_CLKIN;
output [1:0] GPIO1_CLKOUT;
inout [31:0] GPIO1_D;
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 15'hzzzz;
assign LCD_DATA = 8'hzz;
assign SD_DAT0 = 1'hz;
assign SD_DAT3 = 1'hz;
assign SD_CMD = 1'hz;
assign PS2_MSDAT = 1'hz;
assign PS2_MSCLK = 1'hz;
assign GPIO0_D = 32'hzzzzzzzz;
assign GPIO1_D = 32'hzzzzzzzz;
assign HEX0_D = 7'h7F;
assign HEX0_DP = 1'h1;
assign HEX1_D = 7'h7F;
assign HEX1_DP = 1'h1;
assign HEX2_D = 7'h7F;
assign HEX2_DP = 1'h1;
assign HEX3_D = 7'h7F;
assign HEX3_DP = 1'h1;
wire RST;
assign RST = BUTTON[0];
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_HS;
wire VGA_VS;
wire pClk;
reg [2:0] angle;
initial
begin
fireCnt = 0;
rstcnt = 0;
end
vgaClk u2
(
.inclk0(CLOCK_50),
.c0(pClk)
);
wire [10:0] mVGA_X;
wire [10:0] mVGA_Y;
wire [3:0] mOSD_R;
wire [3:0] mOSD_G;
wire [3:0] mOSD_B;
wire [3:0] sVGA_R;
wire [3:0] sVGA_G;
wire [3:0] sVGA_B;
assign VGA_R = sVGA_R;
assign VGA_G = sVGA_G;
assign VGA_B = sVGA_B;
VGA_Ctrl u3
(
.oCurrent_X(mVGA_X),
.oCurrent_Y(mVGA_Y),
.iRed(mOSD_R),
.iGreen(mOSD_G),
.iBlue(mOSD_B),
.oVGA_R(sVGA_R),
.oVGA_G(sVGA_G),
.oVGA_B(sVGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.iCLK(pClk),
.iRST_N(RST)
);
VGA_Drive u4
(
.oRed(mOSD_R),
.oGreen(mOSD_G),
.oBlue(mOSD_B),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iVGA_CLK(pClk),
.iDrawPixel(drawPixel),
.iON_R(15),
.iON_G(15),
.iON_B(15),
.iOFF_R(0),
.iOFF_G(0),
.iOFF_B(8),
.iRST_n(RST)
);
wire spareShips;
wire spare1_PX, spare2_PX, spare3_PX;
assign spareShips = spare1_PX || spare2_PX || spare3_PX;
wire drawShip;
wire ship_PX;
assign drawShip = ship_PX;
wire drawTorpedo;
wire torp0_PX, torp1_PX, torp2_PX, torp3_PX, torp4_PX, torp5_PX, torp6_PX, torp7_PX;
assign drawTorpedo = torp0_PX || torp1_PX || torp2_PX || torp3_PX || torp4_PX || torp5_PX || torp6_PX || torp7_PX;
wire drawAstroid, drawAstroidU, drawAstroidL;
wire asto0_PX, asto1_PX, asto2_PX, asto3_PX, asto4_PX, asto5_PX, asto6_PX, asto7_PX;
wire asto8_PX, asto9_PX, asto10_PX, asto11_PX, asto12_PX, asto13_PX, asto14_PX, asto15_PX;
assign drawAstroidL = asto0_PX || asto1_PX || asto2_PX || asto3_PX || asto4_PX || asto5_PX || asto6_PX || asto7_PX;
assign drawAstroidU = asto8_PX || asto9_PX || asto10_PX || asto11_PX || asto12_PX || asto13_PX || asto14_PX || asto15_PX;
assign drawAstroid = drawAstroidL || drawAstroidU;
wire drawPixel;
assign drawPixel = drawShip || drawAstroid || drawTorpedo || spareShips || drawNum || endGame;
wire shipAstCol;
wire torpAstCol;
assign shipAstCol = drawShip && drawAstroid;
assign torpAstCol = drawAstroid && drawTorpedo;
wire [3:0] digit1, digit2, digit3, digit4, digit5, digit6;
Digit d1 (
.iClk(mClk),
.iPosX(600),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit1),
.oDrawNum(drawNum1),
.iBlank(1)
);
Digit d2 (
.iClk(mClk),
.iPosX(584),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit2),
.oDrawNum(drawNum2),
.iBlank(1)
);
Digit d3 (
.iClk(mClk),
.iPosX(568),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit3),
.oDrawNum(drawNum3),
.iBlank(1)
);
Digit d4 (
.iClk(mClk),
.iPosX(552),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit4),
.oDrawNum(drawNum4),
.iBlank(1)
);
Digit d5 (
.iClk(mClk),
.iPosX(536),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit5),
.oDrawNum(drawNum5),
.iBlank(1)
);
Digit d6 (
.iClk(mClk),
.iPosX(520),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit6),
.oDrawNum(drawNum6),
.iBlank(1)
);
wire drawNum1, drawNum2, drawNum3, drawNum4, drawNum5, drawNum6;
wire drawNum;
assign drawNum = drawNum1 || drawNum2 || drawNum3 || drawNum4 || drawNum5 || drawNum6;
wire points = addPoints0 || addPoints1 || addPoints2 || addPoints3 || addPoints4 || addPoints5 || addPoints6 || addPoints7 || addPoints8 || addPoints9 || addPoints10 || addPoints11 || addPoints12 || addPoints13 || addPoints14 || addPoints15;
wire addPoints0 , addPoints1 , addPoints2 , addPoints3 , addPoints4 , addPoints5 , addPoints6 , addPoints7 , addPoints8 , addPoints9 , addPoints10 , addPoints11 , addPoints12 , addPoints13 , addPoints14 , addPoints15;
reg [19:0] PointCount;
Hex2BCD h2d(
.iClk(mClk),
.iHexPoints(PointCount),
.oDigit1(digit1),
.oDigit2(digit2),
.oDigit3(digit3),
.oDigit4(digit4),
.oDigit5(digit5),
.oDigit6(digit6)
);
always@ (posedge points or negedge RST)
begin
if(!RST)
begin
PointCount = 0;
end
else
begin
PointCount = PointCount + 25;
end
end
memClk mk (
.inclk0(CLOCK_50),
.c0(mClk)
);
wire mClk;
GameOver go (
.iRst(RST),
.iClk(mClk),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iGameOver(gameOver),
.oDrawGameOver(endGame)
);
wire endGame;
wire VB;
wire [7:0] scancode;
keyboard kb(mClk, PS2_KBCLK, PS2_KBDAT, RST, scancode, VB);
reg [7:0] keyBrdOut;
reg fireUp, fireDn;
assign fireBtn = fireUp ^ fireDn;
always@(posedge VB)
begin
keyBrdOut = scancode;
case(keyBrdOut)
8'b01101011: angle = angle + 1'b1;
8'b01110100: angle = angle - 1'b1;
8'b00101001: fireUp = ~fireUp;
default: ;
endcase
end
always@(negedge VB)
begin
case(keyBrdOut)
8'b00101001: fireDn = ~fireDn;
default: ;
endcase
end
CommandShip ship
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(angle),
.iRestart(newShip),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(ship_PX),
.iCollision(shipAstCol),
.oActive(shipAlive)
);
defparam spare1.POS_X = 10;
defparam spare1.POS_Y = 10;
CommandShip spare1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare1_PX),
.iCollision(stopS1)
);
defparam spare2.POS_X = 30;
defparam spare2.POS_Y = 10;
CommandShip spare2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare2_PX),
.iCollision(stopS2)
);
defparam spare3.POS_X = 50;
defparam spare3.POS_Y = 10;
CommandShip spare3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare3_PX),
.iCollision(stopS3)
);
wire stopS0;
wire stopS1;
wire stopS2;
wire stopS3;
spareShipDecode ssd (
shipCnt,
stopS0,
stopS1,
stopS2,
stopS3
);
wire shipAlive;
reg newShip;
reg [1:0] shipCnt;
reg [31:0] rstcnt;
reg gameOver;
always@(posedge mClk or negedge RST)
begin
if(!RST)
begin
shipCnt = 0;
newShip = 1'b0;
rstcnt = 0;
gameOver = 1'b0;
end
else if(shipCnt != 2'b01)
begin
if(!shipAlive)
begin
rstcnt = rstcnt + 1'b1;
if (rstcnt == 32'h09ffffff)
begin
newShip = 1'b1;
end
else
begin
end
end
else if (newShip ==1)
begin
newShip = 1'b0;
rstcnt = 0;
shipCnt = shipCnt - 1'b1;
end
else
begin
end
end
else
begin
if(!shipAlive)
begin
gameOver = 1'b1;
end
else
begin
end
end
end
assign LEDG[1:0] = shipCnt;
oneshot os(fireBtn, mClk, fire);
wire fireBtn;
reg [2:0] fireCnt;
always@(posedge fire)
begin
if (shipAlive)
begin
fireCnt = fireCnt + 1'b1;
end
else
begin
end
end
wire fire, fire0, fire1, fire2, fire3, fire4, fire5, fire6, fire7;
fireDecode fd (
fireCnt,
fire0,
fire1,
fire2,
fire3,
fire4,
fire5,
fire6,
fire7
);
Torpedo t0
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp0_PX),
.iCollision(torpAstCol)
);
Torpedo t1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire1),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp1_PX),
.iCollision(torpAstCol)
);
Torpedo t2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire2),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp2_PX),
.iCollision(torpAstCol)
);
Torpedo t3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire3),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp3_PX),
.iCollision(torpAstCol)
);
Torpedo t4
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire4),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp4_PX),
.iCollision(torpAstCol)
);
Torpedo t5
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire5),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp5_PX),
.iCollision(torpAstCol)
);
Torpedo t6
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire6),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp6_PX),
.iCollision(torpAstCol)
);
Torpedo t7
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire7),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp7_PX),
.iCollision(torpAstCol)
);
asteroid_placer ap (
.iClk(mClk),
.iRst(RST),
.oDir(direction),
.oPosX(astoridX),
.oPosY(astoridY),
.oSize(astSize)
);
wire [2:0] direction;
wire [10:0] astoridX;
wire [10:0] astoridY;
wire [1:0] astSize;
reg [3:0] aID;
wire launch;
asteroid_controller cont (
.clk(mClk),
.rst(RST),
.fire_out(launch)
);
always@(posedge launch)
begin
aID = aID + 1'b1;
end
asteroid_decode ast (
aID,
aFire0,
aFire1,
aFire2,
aFire3,
aFire4,
aFire5,
aFire6,
aFire7,
aFire8,
aFire9,
aFire10,
aFire11,
aFire12,
aFire13,
aFire14,
aFire15
);
wire aFire0, aFire1, aFire2, aFire3, aFire4, aFire5, aFire6, aFire7, aFire8, aFire9;
wire aFire10, aFire11, aFire12, aFire13, aFire14, aFire15;
asteroid_8x8 a0
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire0),
.iTorpColl(torpAstCol),
.iCollision(torpAstCol || shipAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto0_PX),
.oCntPoints(addPoints0),
.iSize(astSize)
);
asteroid_8x8 a1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire1),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto1_PX),
.oCntPoints(addPoints1),
.iSize(astSize)
);
asteroid_8x8 a2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire2),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto2_PX),
.oCntPoints(addPoints2),
.iSize(astSize)
);
asteroid_8x8 a3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire3),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto3_PX),
.oCntPoints(addPoints3),
.iSize(astSize)
);
asteroid_8x8 a4
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire4),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto4_PX),
.oCntPoints(addPoints4),
.iSize(astSize)
);
asteroid_8x8 a5
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire5),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto5_PX),
.oCntPoints(addPoints5),
.iSize(astSize)
);
asteroid_8x8 a6
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire6),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto6_PX),
.oCntPoints(addPoints6),
.iSize(astSize)
);
asteroid_8x8 a7
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire7),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto7_PX),
.oCntPoints(addPoints7),
.iSize(astSize)
);
asteroid_8x8 a8
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire8),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto8_PX),
.oCntPoints(addPoints8),
.iSize(astSize)
);
asteroid_8x8 a9
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire9),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto9_PX),
.oCntPoints(addPoints9),
.iSize(astSize)
);
asteroid_8x8 a10
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire10),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto10_PX),
.oCntPoints(addPoints10),
.iSize(astSize)
);
asteroid_8x8 a11
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire11),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto11_PX),
.oCntPoints(addPoints11),
.iSize(astSize)
);
asteroid_8x8 a12
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire12),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto12_PX),
.oCntPoints(addPoints12),
.iSize(astSize)
);
asteroid_8x8 a13
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire13),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto13_PX),
.oCntPoints(addPoints13),
.iSize(astSize)
);
asteroid_8x8 a14
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire14),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto14_PX),
.oCntPoints(addPoints14),
.iSize(astSize)
);
asteroid_8x8 a15
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire15),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto15_PX),
.oCntPoints(addPoints15),
.iSize(astSize)
);
endmodule | module Asteroids (
CLOCK_50,
CLOCK_50_2,
BUTTON,
SW,
HEX0_D,
HEX0_DP,
HEX1_D,
HEX1_DP,
HEX2_D,
HEX2_DP,
HEX3_D,
HEX3_DP,
LEDG,
UART_TXD,
UART_RXD,
UART_CTS,
UART_RTS,
DRAM_DQ,
DRAM_ADDR,
DRAM_LDQM,
DRAM_UDQM,
DRAM_WE_N,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CS_N,
DRAM_BA_0,
DRAM_BA_1,
DRAM_CLK,
DRAM_CKE,
FL_DQ,
FL_DQ15_AM1,
FL_ADDR,
FL_WE_N,
FL_RST_N,
FL_OE_N,
FL_CE_N,
FL_WP_N,
FL_BYTE_N,
FL_RY,
LCD_BLON,
LCD_RW,
LCD_EN,
LCD_RS,
LCD_DATA,
SD_DAT0,
SD_DAT3,
SD_CMD,
SD_CLK,
SD_WP_N,
PS2_KBDAT,
PS2_KBCLK,
PS2_MSDAT,
PS2_MSCLK,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B,
GPIO0_CLKIN,
GPIO0_CLKOUT,
GPIO0_D,
GPIO1_CLKIN,
GPIO1_CLKOUT,
GPIO1_D
); |
input CLOCK_50;
input CLOCK_50_2;
input [2:0] BUTTON;
input [9:0] SW;
output [6:0] HEX0_D;
output HEX0_DP;
output [6:0] HEX1_D;
output HEX1_DP;
output [6:0] HEX2_D;
output HEX2_DP;
output [6:0] HEX3_D;
output HEX3_DP;
output [9:0] LEDG;
output UART_TXD;
input UART_RXD;
output UART_CTS;
input UART_RTS;
inout [15:0] DRAM_DQ;
output [12:0] DRAM_ADDR;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_WE_N;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CS_N;
output DRAM_BA_0;
output DRAM_BA_1;
output DRAM_CLK;
output DRAM_CKE;
inout [14:0] FL_DQ;
inout FL_DQ15_AM1;
output [21:0] FL_ADDR;
output FL_WE_N;
output FL_RST_N;
output FL_OE_N;
output FL_CE_N;
output FL_WP_N;
output FL_BYTE_N;
input FL_RY;
inout [7:0] LCD_DATA;
output LCD_BLON;
output LCD_RW;
output LCD_EN;
output LCD_RS;
inout SD_DAT0;
inout SD_DAT3;
inout SD_CMD;
output SD_CLK;
input SD_WP_N;
inout PS2_KBDAT;
inout PS2_KBCLK;
inout PS2_MSDAT;
inout PS2_MSCLK;
output VGA_HS;
output VGA_VS;
output [3:0] VGA_R;
output [3:0] VGA_G;
output [3:0] VGA_B;
input [1:0] GPIO0_CLKIN;
output [1:0] GPIO0_CLKOUT;
inout [31:0] GPIO0_D;
input [1:0] GPIO1_CLKIN;
output [1:0] GPIO1_CLKOUT;
inout [31:0] GPIO1_D;
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 15'hzzzz;
assign LCD_DATA = 8'hzz;
assign SD_DAT0 = 1'hz;
assign SD_DAT3 = 1'hz;
assign SD_CMD = 1'hz;
assign PS2_MSDAT = 1'hz;
assign PS2_MSCLK = 1'hz;
assign GPIO0_D = 32'hzzzzzzzz;
assign GPIO1_D = 32'hzzzzzzzz;
assign HEX0_D = 7'h7F;
assign HEX0_DP = 1'h1;
assign HEX1_D = 7'h7F;
assign HEX1_DP = 1'h1;
assign HEX2_D = 7'h7F;
assign HEX2_DP = 1'h1;
assign HEX3_D = 7'h7F;
assign HEX3_DP = 1'h1;
wire RST;
assign RST = BUTTON[0];
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_HS;
wire VGA_VS;
wire pClk;
reg [2:0] angle;
initial
begin
fireCnt = 0;
rstcnt = 0;
end
vgaClk u2
(
.inclk0(CLOCK_50),
.c0(pClk)
);
wire [10:0] mVGA_X;
wire [10:0] mVGA_Y;
wire [3:0] mOSD_R;
wire [3:0] mOSD_G;
wire [3:0] mOSD_B;
wire [3:0] sVGA_R;
wire [3:0] sVGA_G;
wire [3:0] sVGA_B;
assign VGA_R = sVGA_R;
assign VGA_G = sVGA_G;
assign VGA_B = sVGA_B;
VGA_Ctrl u3
(
.oCurrent_X(mVGA_X),
.oCurrent_Y(mVGA_Y),
.iRed(mOSD_R),
.iGreen(mOSD_G),
.iBlue(mOSD_B),
.oVGA_R(sVGA_R),
.oVGA_G(sVGA_G),
.oVGA_B(sVGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.iCLK(pClk),
.iRST_N(RST)
);
VGA_Drive u4
(
.oRed(mOSD_R),
.oGreen(mOSD_G),
.oBlue(mOSD_B),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iVGA_CLK(pClk),
.iDrawPixel(drawPixel),
.iON_R(15),
.iON_G(15),
.iON_B(15),
.iOFF_R(0),
.iOFF_G(0),
.iOFF_B(8),
.iRST_n(RST)
);
wire spareShips;
wire spare1_PX, spare2_PX, spare3_PX;
assign spareShips = spare1_PX || spare2_PX || spare3_PX;
wire drawShip;
wire ship_PX;
assign drawShip = ship_PX;
wire drawTorpedo;
wire torp0_PX, torp1_PX, torp2_PX, torp3_PX, torp4_PX, torp5_PX, torp6_PX, torp7_PX;
assign drawTorpedo = torp0_PX || torp1_PX || torp2_PX || torp3_PX || torp4_PX || torp5_PX || torp6_PX || torp7_PX;
wire drawAstroid, drawAstroidU, drawAstroidL;
wire asto0_PX, asto1_PX, asto2_PX, asto3_PX, asto4_PX, asto5_PX, asto6_PX, asto7_PX;
wire asto8_PX, asto9_PX, asto10_PX, asto11_PX, asto12_PX, asto13_PX, asto14_PX, asto15_PX;
assign drawAstroidL = asto0_PX || asto1_PX || asto2_PX || asto3_PX || asto4_PX || asto5_PX || asto6_PX || asto7_PX;
assign drawAstroidU = asto8_PX || asto9_PX || asto10_PX || asto11_PX || asto12_PX || asto13_PX || asto14_PX || asto15_PX;
assign drawAstroid = drawAstroidL || drawAstroidU;
wire drawPixel;
assign drawPixel = drawShip || drawAstroid || drawTorpedo || spareShips || drawNum || endGame;
wire shipAstCol;
wire torpAstCol;
assign shipAstCol = drawShip && drawAstroid;
assign torpAstCol = drawAstroid && drawTorpedo;
wire [3:0] digit1, digit2, digit3, digit4, digit5, digit6;
Digit d1 (
.iClk(mClk),
.iPosX(600),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit1),
.oDrawNum(drawNum1),
.iBlank(1)
);
Digit d2 (
.iClk(mClk),
.iPosX(584),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit2),
.oDrawNum(drawNum2),
.iBlank(1)
);
Digit d3 (
.iClk(mClk),
.iPosX(568),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit3),
.oDrawNum(drawNum3),
.iBlank(1)
);
Digit d4 (
.iClk(mClk),
.iPosX(552),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit4),
.oDrawNum(drawNum4),
.iBlank(1)
);
Digit d5 (
.iClk(mClk),
.iPosX(536),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit5),
.oDrawNum(drawNum5),
.iBlank(1)
);
Digit d6 (
.iClk(mClk),
.iPosX(520),
.iPosY(10),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iDigit(digit6),
.oDrawNum(drawNum6),
.iBlank(1)
);
wire drawNum1, drawNum2, drawNum3, drawNum4, drawNum5, drawNum6;
wire drawNum;
assign drawNum = drawNum1 || drawNum2 || drawNum3 || drawNum4 || drawNum5 || drawNum6;
wire points = addPoints0 || addPoints1 || addPoints2 || addPoints3 || addPoints4 || addPoints5 || addPoints6 || addPoints7 || addPoints8 || addPoints9 || addPoints10 || addPoints11 || addPoints12 || addPoints13 || addPoints14 || addPoints15;
wire addPoints0 , addPoints1 , addPoints2 , addPoints3 , addPoints4 , addPoints5 , addPoints6 , addPoints7 , addPoints8 , addPoints9 , addPoints10 , addPoints11 , addPoints12 , addPoints13 , addPoints14 , addPoints15;
reg [19:0] PointCount;
Hex2BCD h2d(
.iClk(mClk),
.iHexPoints(PointCount),
.oDigit1(digit1),
.oDigit2(digit2),
.oDigit3(digit3),
.oDigit4(digit4),
.oDigit5(digit5),
.oDigit6(digit6)
);
always@ (posedge points or negedge RST)
begin
if(!RST)
begin
PointCount = 0;
end
else
begin
PointCount = PointCount + 25;
end
end
memClk mk (
.inclk0(CLOCK_50),
.c0(mClk)
);
wire mClk;
GameOver go (
.iRst(RST),
.iClk(mClk),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iGameOver(gameOver),
.oDrawGameOver(endGame)
);
wire endGame;
wire VB;
wire [7:0] scancode;
keyboard kb(mClk, PS2_KBCLK, PS2_KBDAT, RST, scancode, VB);
reg [7:0] keyBrdOut;
reg fireUp, fireDn;
assign fireBtn = fireUp ^ fireDn;
always@(posedge VB)
begin
keyBrdOut = scancode;
case(keyBrdOut)
8'b01101011: angle = angle + 1'b1;
8'b01110100: angle = angle - 1'b1;
8'b00101001: fireUp = ~fireUp;
default: ;
endcase
end
always@(negedge VB)
begin
case(keyBrdOut)
8'b00101001: fireDn = ~fireDn;
default: ;
endcase
end
CommandShip ship
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(angle),
.iRestart(newShip),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(ship_PX),
.iCollision(shipAstCol),
.oActive(shipAlive)
);
defparam spare1.POS_X = 10;
defparam spare1.POS_Y = 10;
CommandShip spare1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare1_PX),
.iCollision(stopS1)
);
defparam spare2.POS_X = 30;
defparam spare2.POS_Y = 10;
CommandShip spare2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare2_PX),
.iCollision(stopS2)
);
defparam spare3.POS_X = 50;
defparam spare3.POS_Y = 10;
CommandShip spare3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iAngle(0),
.iRestart(0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(spare3_PX),
.iCollision(stopS3)
);
wire stopS0;
wire stopS1;
wire stopS2;
wire stopS3;
spareShipDecode ssd (
shipCnt,
stopS0,
stopS1,
stopS2,
stopS3
);
wire shipAlive;
reg newShip;
reg [1:0] shipCnt;
reg [31:0] rstcnt;
reg gameOver;
always@(posedge mClk or negedge RST)
begin
if(!RST)
begin
shipCnt = 0;
newShip = 1'b0;
rstcnt = 0;
gameOver = 1'b0;
end
else if(shipCnt != 2'b01)
begin
if(!shipAlive)
begin
rstcnt = rstcnt + 1'b1;
if (rstcnt == 32'h09ffffff)
begin
newShip = 1'b1;
end
else
begin
end
end
else if (newShip ==1)
begin
newShip = 1'b0;
rstcnt = 0;
shipCnt = shipCnt - 1'b1;
end
else
begin
end
end
else
begin
if(!shipAlive)
begin
gameOver = 1'b1;
end
else
begin
end
end
end
assign LEDG[1:0] = shipCnt;
oneshot os(fireBtn, mClk, fire);
wire fireBtn;
reg [2:0] fireCnt;
always@(posedge fire)
begin
if (shipAlive)
begin
fireCnt = fireCnt + 1'b1;
end
else
begin
end
end
wire fire, fire0, fire1, fire2, fire3, fire4, fire5, fire6, fire7;
fireDecode fd (
fireCnt,
fire0,
fire1,
fire2,
fire3,
fire4,
fire5,
fire6,
fire7
);
Torpedo t0
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire0),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp0_PX),
.iCollision(torpAstCol)
);
Torpedo t1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire1),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp1_PX),
.iCollision(torpAstCol)
);
Torpedo t2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire2),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp2_PX),
.iCollision(torpAstCol)
);
Torpedo t3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire3),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp3_PX),
.iCollision(torpAstCol)
);
Torpedo t4
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire4),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp4_PX),
.iCollision(torpAstCol)
);
Torpedo t5
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire5),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp5_PX),
.iCollision(torpAstCol)
);
Torpedo t6
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire6),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp6_PX),
.iCollision(torpAstCol)
);
Torpedo t7
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(angle),
.iFireTorpedo(fire7),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(torp7_PX),
.iCollision(torpAstCol)
);
asteroid_placer ap (
.iClk(mClk),
.iRst(RST),
.oDir(direction),
.oPosX(astoridX),
.oPosY(astoridY),
.oSize(astSize)
);
wire [2:0] direction;
wire [10:0] astoridX;
wire [10:0] astoridY;
wire [1:0] astSize;
reg [3:0] aID;
wire launch;
asteroid_controller cont (
.clk(mClk),
.rst(RST),
.fire_out(launch)
);
always@(posedge launch)
begin
aID = aID + 1'b1;
end
asteroid_decode ast (
aID,
aFire0,
aFire1,
aFire2,
aFire3,
aFire4,
aFire5,
aFire6,
aFire7,
aFire8,
aFire9,
aFire10,
aFire11,
aFire12,
aFire13,
aFire14,
aFire15
);
wire aFire0, aFire1, aFire2, aFire3, aFire4, aFire5, aFire6, aFire7, aFire8, aFire9;
wire aFire10, aFire11, aFire12, aFire13, aFire14, aFire15;
asteroid_8x8 a0
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire0),
.iTorpColl(torpAstCol),
.iCollision(torpAstCol || shipAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto0_PX),
.oCntPoints(addPoints0),
.iSize(astSize)
);
asteroid_8x8 a1
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire1),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto1_PX),
.oCntPoints(addPoints1),
.iSize(astSize)
);
asteroid_8x8 a2
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire2),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto2_PX),
.oCntPoints(addPoints2),
.iSize(astSize)
);
asteroid_8x8 a3
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire3),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto3_PX),
.oCntPoints(addPoints3),
.iSize(astSize)
);
asteroid_8x8 a4
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire4),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto4_PX),
.oCntPoints(addPoints4),
.iSize(astSize)
);
asteroid_8x8 a5
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire5),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto5_PX),
.oCntPoints(addPoints5),
.iSize(astSize)
);
asteroid_8x8 a6
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire6),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto6_PX),
.oCntPoints(addPoints6),
.iSize(astSize)
);
asteroid_8x8 a7
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire7),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto7_PX),
.oCntPoints(addPoints7),
.iSize(astSize)
);
asteroid_8x8 a8
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire8),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto8_PX),
.oCntPoints(addPoints8),
.iSize(astSize)
);
asteroid_8x8 a9
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire9),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto9_PX),
.oCntPoints(addPoints9),
.iSize(astSize)
);
asteroid_8x8 a10
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire10),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto10_PX),
.oCntPoints(addPoints10),
.iSize(astSize)
);
asteroid_8x8 a11
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire11),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto11_PX),
.oCntPoints(addPoints11),
.iSize(astSize)
);
asteroid_8x8 a12
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire12),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto12_PX),
.oCntPoints(addPoints12),
.iSize(astSize)
);
asteroid_8x8 a13
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire13),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto13_PX),
.oCntPoints(addPoints13),
.iSize(astSize)
);
asteroid_8x8 a14
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire14),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto14_PX),
.oCntPoints(addPoints14),
.iSize(astSize)
);
asteroid_8x8 a15
(
.iRst(RST),
.iMemClk(mClk),
.iPClk(pClk),
.iDir(direction),
.iPosY(astoridY),
.iPosX(astoridX),
.iFireAsteroid(aFire15),
.iCollision(torpAstCol || shipAstCol),
.iTorpColl(torpAstCol),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.oDrawPixel(asto15_PX),
.oCntPoints(addPoints15),
.iSize(astSize)
);
endmodule | 1 |
5,034 | data/full_repos/permissive/113002755/verilog/asteroid_8x8.v | 113,002,755 | asteroid_8x8.v | v | 265 | 72 | [] | [] | [] | [(14, 264)] | null | null | 1: b'%Error: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:38: Cannot find file containing module: \'asteroidSprites\'\nasteroidSprites as\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/asteroidSprites\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/asteroidSprites.v\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/asteroidSprites.sv\n asteroidSprites\n asteroidSprites.v\n asteroidSprites.sv\n obj_dir/asteroidSprites\n obj_dir/asteroidSprites.v\n obj_dir/asteroidSprites.sv\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:130: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance asteroid_8x8\nassign col = iVGA_X - pos_X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:133: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance asteroid_8x8\nassign row = iVGA_Y - pos_Y;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:147: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:148: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:175: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:176: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:182: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:183: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:222: Operator ADD expects 11 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance asteroid_8x8\n pos_X = pos_X + 3\'b101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:238: Operator ADD expects 11 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance asteroid_8x8\n pos_Y = pos_Y + 3\'b101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:187: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n if(pos_X == 10\'b1111111111)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:259: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/asteroid_8x8.v:260: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance asteroid_8x8\n pos_Y = 10\'b1111111111;\n ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n' | 5,504 | module | module asteroid_8x8 (
iRst,
iMemClk,
iPClk,
iDir,
iPosX,
iPosY,
iFireAsteroid,
iCollision,
iTorpColl,
iSize,
iVGA_X,
iVGA_Y,
oDrawPixel,
oFiring,
oCntPoints
);
asteroidSprites as
(
tAddr,
iMemClk,
current
);
input [2:0] iDir;
input [10:0] iPosX;
input [10:0] iPosY;
input iMemClk;
input iPClk;
input iRst;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iFireAsteroid;
input iCollision;
input iTorpColl;
input [1:0] iSize;
output oDrawPixel;
output oFiring;
output oCntPoints;
reg oCntPoints;
reg fired;
wire firing;
reg done;
reg [2:0] direction;
reg [10:0] init_pos_X;
reg [10:0] init_pos_Y;
reg [10:0] pos_X;
reg [10:0] pos_Y;
reg [1:0] size;
reg collided;
reg rstCollided;
wire didCollide;
reg collision;
assign didCollide = collided ^ rstCollided;
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
if(iTorpColl == 1)
begin
oCntPoints = 1'b1;
end
else
begin
end
end
else
begin
collision = 0;
oCntPoints = 1'b0;
end
end
always@(posedge collision)
begin
collided = ~collided;
end
assign firing = fired ^ done;
assign oFiring = firing;
always@(posedge iFireAsteroid)
begin
if(!firing)
begin
direction = iDir;
init_pos_X = iPosX;
init_pos_Y = iPosY;
fired = ~fired;
size = iSize%3;
end
else
begin
end
end
wire oDrawPixel;
wire [4:0] col;
assign col = iVGA_X - pos_X;
wire [4:0] row;
assign row = iVGA_Y - pos_Y;
wire inPosition;
assign inPosition = ((iVGA_X - pos_X)) < 20 && ((iVGA_Y - pos_Y) < 20);
wire drawAsteroid;
assign drawAsteroid = inPosition && firing;
assign oDrawPixel = (drawAsteroid) ? current[col] : 0 ;
initial
begin
fired = 0;
done = 0;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
wire [5:0] tAddr;
wire [19:0] current;
reg [18:0] cnt;
assign tAddr = (size * 20) + row;
always@(posedge iMemClk or negedge iRst)
begin
if(!iRst)
begin
if(didCollide)
begin
rstCollided = ~rstCollided;
end
else
begin
end
if(firing)
begin
done = ~done;
end
else
begin
end
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(didCollide)
begin
rstCollided = ~rstCollided;
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(firing)
begin
if(pos_X == 10'b1111111111)
begin
pos_X = init_pos_X;
pos_Y = init_pos_Y;
cnt = 0;
end
else
begin
cnt = cnt + 1'b1;
if (cnt == 0)
begin
case (direction)
3'b000 : pos_Y = pos_Y - 1'b1;
3'b001 : pos_Y = pos_Y - 1'b1;
3'b010 : pos_Y = pos_Y;
3'b011 : pos_Y = pos_Y + 1'b1;
3'b100 : pos_Y = pos_Y + 1'b1;
3'b101 : pos_Y = pos_Y + 1'b1;
3'b110 : pos_Y = pos_Y;
3'b111 : pos_Y = pos_Y - 1'b1;
endcase
case (direction)
3'b000 : pos_X = pos_X;
3'b001 : pos_X = pos_X - 1'b1;
3'b010 : pos_X = pos_X - 1'b1;
3'b011 : pos_X = pos_X - 1'b1;
3'b100 : pos_X = pos_X;
3'b101 : pos_X = pos_X + 1'b1;
3'b110 : pos_X = pos_X + 1'b1;
3'b111 : pos_X = pos_X + 1'b1;
endcase
if(pos_Y > 480)
begin
pos_X = pos_X + 3'b101;
if(direction == 1 || direction == 7)
begin
pos_Y = 479;
end
else
begin
pos_Y = 1;
end
end
else
begin
end
if(pos_X > 640)
begin
pos_Y = pos_Y + 3'b101;
if(direction == 1 || direction == 3)
begin
pos_X = 639;
end
else
begin
pos_X = 1;
end
end
else
begin
end
end
else
begin
end
end
end
else
begin
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
end
endmodule | module asteroid_8x8 (
iRst,
iMemClk,
iPClk,
iDir,
iPosX,
iPosY,
iFireAsteroid,
iCollision,
iTorpColl,
iSize,
iVGA_X,
iVGA_Y,
oDrawPixel,
oFiring,
oCntPoints
); |
asteroidSprites as
(
tAddr,
iMemClk,
current
);
input [2:0] iDir;
input [10:0] iPosX;
input [10:0] iPosY;
input iMemClk;
input iPClk;
input iRst;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iFireAsteroid;
input iCollision;
input iTorpColl;
input [1:0] iSize;
output oDrawPixel;
output oFiring;
output oCntPoints;
reg oCntPoints;
reg fired;
wire firing;
reg done;
reg [2:0] direction;
reg [10:0] init_pos_X;
reg [10:0] init_pos_Y;
reg [10:0] pos_X;
reg [10:0] pos_Y;
reg [1:0] size;
reg collided;
reg rstCollided;
wire didCollide;
reg collision;
assign didCollide = collided ^ rstCollided;
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
if(iTorpColl == 1)
begin
oCntPoints = 1'b1;
end
else
begin
end
end
else
begin
collision = 0;
oCntPoints = 1'b0;
end
end
always@(posedge collision)
begin
collided = ~collided;
end
assign firing = fired ^ done;
assign oFiring = firing;
always@(posedge iFireAsteroid)
begin
if(!firing)
begin
direction = iDir;
init_pos_X = iPosX;
init_pos_Y = iPosY;
fired = ~fired;
size = iSize%3;
end
else
begin
end
end
wire oDrawPixel;
wire [4:0] col;
assign col = iVGA_X - pos_X;
wire [4:0] row;
assign row = iVGA_Y - pos_Y;
wire inPosition;
assign inPosition = ((iVGA_X - pos_X)) < 20 && ((iVGA_Y - pos_Y) < 20);
wire drawAsteroid;
assign drawAsteroid = inPosition && firing;
assign oDrawPixel = (drawAsteroid) ? current[col] : 0 ;
initial
begin
fired = 0;
done = 0;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
wire [5:0] tAddr;
wire [19:0] current;
reg [18:0] cnt;
assign tAddr = (size * 20) + row;
always@(posedge iMemClk or negedge iRst)
begin
if(!iRst)
begin
if(didCollide)
begin
rstCollided = ~rstCollided;
end
else
begin
end
if(firing)
begin
done = ~done;
end
else
begin
end
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(didCollide)
begin
rstCollided = ~rstCollided;
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(firing)
begin
if(pos_X == 10'b1111111111)
begin
pos_X = init_pos_X;
pos_Y = init_pos_Y;
cnt = 0;
end
else
begin
cnt = cnt + 1'b1;
if (cnt == 0)
begin
case (direction)
3'b000 : pos_Y = pos_Y - 1'b1;
3'b001 : pos_Y = pos_Y - 1'b1;
3'b010 : pos_Y = pos_Y;
3'b011 : pos_Y = pos_Y + 1'b1;
3'b100 : pos_Y = pos_Y + 1'b1;
3'b101 : pos_Y = pos_Y + 1'b1;
3'b110 : pos_Y = pos_Y;
3'b111 : pos_Y = pos_Y - 1'b1;
endcase
case (direction)
3'b000 : pos_X = pos_X;
3'b001 : pos_X = pos_X - 1'b1;
3'b010 : pos_X = pos_X - 1'b1;
3'b011 : pos_X = pos_X - 1'b1;
3'b100 : pos_X = pos_X;
3'b101 : pos_X = pos_X + 1'b1;
3'b110 : pos_X = pos_X + 1'b1;
3'b111 : pos_X = pos_X + 1'b1;
endcase
if(pos_Y > 480)
begin
pos_X = pos_X + 3'b101;
if(direction == 1 || direction == 7)
begin
pos_Y = 479;
end
else
begin
pos_Y = 1;
end
end
else
begin
end
if(pos_X > 640)
begin
pos_Y = pos_Y + 3'b101;
if(direction == 1 || direction == 3)
begin
pos_X = 639;
end
else
begin
pos_X = 1;
end
end
else
begin
end
end
else
begin
end
end
end
else
begin
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
end
endmodule | 1 |
5,035 | data/full_repos/permissive/113002755/verilog/CommandShip.v | 113,002,755 | CommandShip.v | v | 133 | 72 | [] | [] | [] | [(15, 129)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/CommandShip.v:66: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance CommandShip\nassign col = iVGA_X - POS_X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/CommandShip.v:67: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance CommandShip\nassign row = iVGA_Y - POS_Y;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/CommandShip.v:77: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'row\' generates 5 bits.\n : ... In instance CommandShip\nassign rAddr = 20 * angle + row;\n ^\n%Error: data/full_repos/permissive/113002755/verilog/CommandShip.v:85: Cannot find file containing module: \'shipSprite\'\nshipSprite shipBitMaps(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/shipSprite\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/shipSprite.v\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/shipSprite.sv\n shipSprite\n shipSprite.v\n shipSprite.sv\n obj_dir/shipSprite\n obj_dir/shipSprite.v\n obj_dir/shipSprite.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 5,507 | module | module CommandShip (
iRst,
iPClk,
iMemClk,
iAngle,
iRestart,
iVGA_X,
iVGA_Y,
oDrawPixel,
iCollision,
oActive
);
input [2:0] iAngle;
input iMemClk;
input iPClk;
input iRst;
input iRestart;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iCollision;
output oDrawPixel;
wire oDrawPixel;
output oActive;
wire oActive;
wire [4:0] col;
wire [4:0] row;
wire inPosition;
wire drawShip;
wire [7:0] rAddr;
wire [19:0] current;
wire [2:0] angle;
reg intack;
reg collision;
parameter [10:0] POS_X = 311;
parameter [10:0] POS_Y = 231;
assign oActive = intack;
assign col = iVGA_X - POS_X;
assign row = iVGA_Y - POS_Y;
assign inPosition = ((iVGA_X - POS_X)) < 20 && ((iVGA_Y - POS_Y) < 20);
assign drawShip = inPosition && intack;
assign oDrawPixel = (drawShip) ? current[col] : 0 ;
assign rAddr = 20 * angle + row;
assign angle = iAngle;
shipSprite shipBitMaps(
rAddr,
iMemClk,
current
);
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
end
else
begin
collision = 0;
end
end
always@(posedge collision or posedge iRestart or negedge iRst)
begin
if(iRestart || !iRst)
begin
intack = 1'b1;
end
else if (collision)
begin
intack = 1'b0;
end
else
begin
end
end
initial
begin
intack = 1;
end
endmodule | module CommandShip (
iRst,
iPClk,
iMemClk,
iAngle,
iRestart,
iVGA_X,
iVGA_Y,
oDrawPixel,
iCollision,
oActive
); |
input [2:0] iAngle;
input iMemClk;
input iPClk;
input iRst;
input iRestart;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iCollision;
output oDrawPixel;
wire oDrawPixel;
output oActive;
wire oActive;
wire [4:0] col;
wire [4:0] row;
wire inPosition;
wire drawShip;
wire [7:0] rAddr;
wire [19:0] current;
wire [2:0] angle;
reg intack;
reg collision;
parameter [10:0] POS_X = 311;
parameter [10:0] POS_Y = 231;
assign oActive = intack;
assign col = iVGA_X - POS_X;
assign row = iVGA_Y - POS_Y;
assign inPosition = ((iVGA_X - POS_X)) < 20 && ((iVGA_Y - POS_Y) < 20);
assign drawShip = inPosition && intack;
assign oDrawPixel = (drawShip) ? current[col] : 0 ;
assign rAddr = 20 * angle + row;
assign angle = iAngle;
shipSprite shipBitMaps(
rAddr,
iMemClk,
current
);
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
end
else
begin
collision = 0;
end
end
always@(posedge collision or posedge iRestart or negedge iRst)
begin
if(iRestart || !iRst)
begin
intack = 1'b1;
end
else if (collision)
begin
intack = 1'b0;
end
else
begin
end
end
initial
begin
intack = 1;
end
endmodule | 1 |
5,038 | data/full_repos/permissive/113002755/verilog/Hex2BCD.v | 113,002,755 | Hex2BCD.v | v | 48 | 72 | [] | [] | [] | [(12, 48)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:40: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit6 = iHexPoints / 100000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:41: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit5 = (iHexPoints % 100000) / 10000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:42: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit4 = (iHexPoints % 10000) / 1000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:43: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit3 = (iHexPoints % 1000) / 100;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:44: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit2 = (iHexPoints % 100) / 10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:45: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 20 bits.\n : ... In instance Hex2BCD\nassign oDigit1 = (iHexPoints % 10);\n ^\n%Error: Exiting due to 6 warning(s)\n' | 5,514 | module | module Hex2BCD(
iClk,
iHexPoints,
oDigit1,
oDigit2,
oDigit3,
oDigit4,
oDigit5,
oDigit6
);
input iClk;
input [19:0] iHexPoints;
output [3:0] oDigit1;
output [3:0] oDigit2;
output [3:0] oDigit3;
output [3:0] oDigit4;
output [3:0] oDigit5;
output [3:0] oDigit6;
wire [3:0] oDigit1;
wire [3:0] oDigit2;
wire [3:0] oDigit3;
wire [3:0] oDigit4;
wire [3:0] oDigit5;
wire [3:0] oDigit6;
assign oDigit6 = iHexPoints / 100000;
assign oDigit5 = (iHexPoints % 100000) / 10000;
assign oDigit4 = (iHexPoints % 10000) / 1000;
assign oDigit3 = (iHexPoints % 1000) / 100;
assign oDigit2 = (iHexPoints % 100) / 10;
assign oDigit1 = (iHexPoints % 10);
endmodule | module Hex2BCD(
iClk,
iHexPoints,
oDigit1,
oDigit2,
oDigit3,
oDigit4,
oDigit5,
oDigit6
); |
input iClk;
input [19:0] iHexPoints;
output [3:0] oDigit1;
output [3:0] oDigit2;
output [3:0] oDigit3;
output [3:0] oDigit4;
output [3:0] oDigit5;
output [3:0] oDigit6;
wire [3:0] oDigit1;
wire [3:0] oDigit2;
wire [3:0] oDigit3;
wire [3:0] oDigit4;
wire [3:0] oDigit5;
wire [3:0] oDigit6;
assign oDigit6 = iHexPoints / 100000;
assign oDigit5 = (iHexPoints % 100000) / 10000;
assign oDigit4 = (iHexPoints % 10000) / 1000;
assign oDigit3 = (iHexPoints % 1000) / 100;
assign oDigit2 = (iHexPoints % 100) / 10;
assign oDigit1 = (iHexPoints % 10);
endmodule | 1 |
5,039 | data/full_repos/permissive/113002755/verilog/kbd_clk_debounce.v | 113,002,755 | kbd_clk_debounce.v | v | 83 | 72 | [] | [] | [] | [(20, 82)] | null | data/verilator_xmls/c87f8069-49a0-4261-878c-79a8227ac4ae.xml | null | 5,515 | module | module kbd_clk_debounce (
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
parameter preset_val = 0;
parameter counter_max = 5;
reg data_out;
reg data_in_0;
reg data_in_1;
reg data_in_2;
reg data_in_3;
reg [20:0] counter;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
data_out <= preset_val;
counter <= counter_max;
data_in_0 <= 0;
data_in_1 <= 0;
data_in_2 <= 0;
data_in_3 <= 0;
end
else
begin
if (counter == 0)
begin
data_out <= data_in_3;
counter <= counter_max;
end
else
begin
counter <= counter - 1;
end
data_in_0 <= data_in;
data_in_1 <= data_in_0;
data_in_2 <= data_in_1;
data_in_3 <= data_in_2;
end
end
endmodule | module kbd_clk_debounce (
clk,
rst_n,
data_in,
data_out
); |
input clk;
input rst_n;
input data_in;
output data_out;
parameter preset_val = 0;
parameter counter_max = 5;
reg data_out;
reg data_in_0;
reg data_in_1;
reg data_in_2;
reg data_in_3;
reg [20:0] counter;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
data_out <= preset_val;
counter <= counter_max;
data_in_0 <= 0;
data_in_1 <= 0;
data_in_2 <= 0;
data_in_3 <= 0;
end
else
begin
if (counter == 0)
begin
data_out <= data_in_3;
counter <= counter_max;
end
else
begin
counter <= counter - 1;
end
data_in_0 <= data_in;
data_in_1 <= data_in_0;
data_in_2 <= data_in_1;
data_in_3 <= data_in_2;
end
end
endmodule | 1 |
5,041 | data/full_repos/permissive/113002755/verilog/Letter.v | 113,002,755 | Letter.v | v | 79 | 72 | [] | [] | [] | [(13, 79)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:51: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance Letter\nassign col = iVGA_X - iPosX;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:53: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance Letter\nassign row = iVGA_Y - iPosY;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:56: Operator ADD expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'row\' generates 4 bits.\n : ... In instance Letter\nassign dAddr = (iLetter * 16) + row;\n ^\n%Error: data/full_repos/permissive/113002755/verilog/Letter.v:71: Cannot find file containing module: \'letter_bitmap\'\nletter_bitmap map(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap.v\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap.sv\n letter_bitmap\n letter_bitmap.v\n letter_bitmap.sv\n obj_dir/letter_bitmap\n obj_dir/letter_bitmap.v\n obj_dir/letter_bitmap.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n' | 5,517 | module | module Letter (
iClk,
iPosX,
iPosY,
iVGA_X,
iVGA_Y,
iLetter,
oDrawLet,
iBlank
);
input iClk;
input [10:0] iPosX;
input [10:0] iPosY;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iBlank;
input [3:0] iLetter;
output oDrawLet;
wire oDrawLet;
wire [15:0] rowBits;
wire [3:0] col;
wire [3:0] row;
wire [6:0] dAddr;
wire inPosition;
wire drawNum;
assign col = iVGA_X - iPosX;
assign row = iVGA_Y - iPosY;
assign dAddr = (iLetter * 16) + row;
assign inPosition = ((iVGA_X - iPosX)) < 16 && ((iVGA_Y - iPosY) < 16);
assign drawNum = inPosition && iBlank;
assign oDrawLet = (drawNum) ? rowBits[15-col] : 0 ;
letter_bitmap map(
.address(dAddr),
.clock(iClk),
.q(rowBits)
);
endmodule | module Letter (
iClk,
iPosX,
iPosY,
iVGA_X,
iVGA_Y,
iLetter,
oDrawLet,
iBlank
); |
input iClk;
input [10:0] iPosX;
input [10:0] iPosY;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iBlank;
input [3:0] iLetter;
output oDrawLet;
wire oDrawLet;
wire [15:0] rowBits;
wire [3:0] col;
wire [3:0] row;
wire [6:0] dAddr;
wire inPosition;
wire drawNum;
assign col = iVGA_X - iPosX;
assign row = iVGA_Y - iPosY;
assign dAddr = (iLetter * 16) + row;
assign inPosition = ((iVGA_X - iPosX)) < 16 && ((iVGA_Y - iPosY) < 16);
assign drawNum = inPosition && iBlank;
assign oDrawLet = (drawNum) ? rowBits[15-col] : 0 ;
letter_bitmap map(
.address(dAddr),
.clock(iClk),
.q(rowBits)
);
endmodule | 1 |
5,042 | data/full_repos/permissive/113002755/verilog/oneshot.v | 113,002,755 | oneshot.v | v | 47 | 80 | [] | [] | [] | [(15, 47)] | null | data/verilator_xmls/de1b30dd-e00f-4a06-9299-38cf5726124e.xml | null | 5,522 | module | module oneshot (
iTrig,
iClk,
oPulse
);
input iTrig;
input iClk;
output oPulse;
reg oPulse;
reg qState;
always@(posedge iTrig or posedge oPulse)
begin
if(oPulse)
qState <= 0;
else
qState <= 1;
end
always@(posedge iClk)
begin
oPulse <= qState;
end
endmodule | module oneshot (
iTrig,
iClk,
oPulse
); |
input iTrig;
input iClk;
output oPulse;
reg oPulse;
reg qState;
always@(posedge iTrig or posedge oPulse)
begin
if(oPulse)
qState <= 0;
else
qState <= 1;
end
always@(posedge iClk)
begin
oPulse <= qState;
end
endmodule | 1 |
5,043 | data/full_repos/permissive/113002755/verilog/Torpedo.v | 113,002,755 | Torpedo.v | v | 231 | 72 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/113002755/verilog/Torpedo.v:34: Cannot find file containing module: \'torpedoSprite\'\ntorpedoSprite ts\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite.v\n data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite.sv\n torpedoSprite\n torpedoSprite.v\n torpedoSprite.sv\n obj_dir/torpedoSprite\n obj_dir/torpedoSprite.v\n obj_dir/torpedoSprite.sv\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:117: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance Torpedo\nassign col = iVGA_X - pos_X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:118: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n : ... In instance Torpedo\nassign row = iVGA_Y - pos_Y;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:128: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:129: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:156: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:157: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:163: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:164: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:211: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:212: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:168: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n if(pos_X == 10\'b1111111111)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:226: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:227: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n' | 5,528 | module | module Torpedo (
iRst,
iMemClk,
iPClk,
iDir,
iFireTorpedo,
iVGA_X,
iVGA_Y,
oDrawPixel,
iCollision
);
torpedoSprite ts
(
tAddr,
iMemClk,
current
);
input [2:0] iDir;
input iMemClk;
input iPClk;
input iRst;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iFireTorpedo;
input iCollision;
output oDrawPixel;
wire oDrawPixel;
reg collided;
reg rstCollided;
reg collision;
wire didCollide;
reg fired;
wire firing;
reg done;
reg [2:0] direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
wire [2:0] col;
wire [2:0] row;
wire inPosition;
wire drawTorpedo;
wire [2:0] tAddr;
wire [4:0] current;
reg [19:0] cnt;
wire [19:0] maxCount;
parameter [10:0] INIT_X = 320;
parameter [10:0] INIT_Y = 240;
assign didCollide = collided ^ rstCollided;
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
end
else
begin
collision = 0;
end
end
always@(posedge collision)
begin
collided = ~collided;
end
assign firing = fired ^ done;
always@(posedge iFireTorpedo)
begin
if(!firing)
begin
direction = iDir;
fired = ~fired;
end
else
begin
end
end
assign col = iVGA_X - pos_X;
assign row = iVGA_Y - pos_Y;
assign inPosition = ((iVGA_X - pos_X)) < 5 && ((iVGA_Y - pos_Y) < 5);
assign drawTorpedo = inPosition && firing;
assign oDrawPixel = (drawTorpedo) ? current[col] : 0 ;
initial
begin
fired = 0;
done = 0;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
assign maxCount = ((direction%2) == 1) ? 20'h7FFFF : 20'h5A826 ;
assign tAddr = row;
always@(posedge iMemClk or negedge iRst)
begin
if(!iRst)
begin
if (didCollide)
begin
rstCollided = ~rstCollided;
end
else
begin
end
if(firing)
begin
done = ~done;
end
else
begin
end
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(didCollide)
begin
rstCollided = ~rstCollided;
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(firing)
begin
if(pos_X == 10'b1111111111)
begin
pos_X = INIT_X;
pos_Y = INIT_Y;
cnt = 0;
end
else
begin
if(cnt < maxCount)
cnt = cnt + 1'b1;
else
cnt = 0;
if (cnt == 0)
begin
case (direction)
3'b000 : pos_Y = pos_Y - 1'b1;
3'b001 : pos_Y = pos_Y - 1'b1;
3'b010 : pos_Y = pos_Y;
3'b011 : pos_Y = pos_Y + 1'b1;
3'b100 : pos_Y = pos_Y + 1'b1;
3'b101 : pos_Y = pos_Y + 1'b1;
3'b110 : pos_Y = pos_Y;
3'b111 : pos_Y = pos_Y - 1'b1;
default: begin end
endcase
case (direction)
3'b000 : pos_X = pos_X;
3'b001 : pos_X = pos_X - 1'b1;
3'b010 : pos_X = pos_X - 1'b1;
3'b011 : pos_X = pos_X - 1'b1;
3'b100 : pos_X = pos_X;
3'b101 : pos_X = pos_X + 1'b1;
3'b110 : pos_X = pos_X + 1'b1;
3'b111 : pos_X = pos_X + 1'b1;
default: begin end
endcase
if(pos_Y > 480 || pos_X > 640)
begin
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else
begin
end
end
else
begin
end
end
end
else
begin
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
end
endmodule | module Torpedo (
iRst,
iMemClk,
iPClk,
iDir,
iFireTorpedo,
iVGA_X,
iVGA_Y,
oDrawPixel,
iCollision
); |
torpedoSprite ts
(
tAddr,
iMemClk,
current
);
input [2:0] iDir;
input iMemClk;
input iPClk;
input iRst;
input [10:0] iVGA_X;
input [10:0] iVGA_Y;
input iFireTorpedo;
input iCollision;
output oDrawPixel;
wire oDrawPixel;
reg collided;
reg rstCollided;
reg collision;
wire didCollide;
reg fired;
wire firing;
reg done;
reg [2:0] direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
wire [2:0] col;
wire [2:0] row;
wire inPosition;
wire drawTorpedo;
wire [2:0] tAddr;
wire [4:0] current;
reg [19:0] cnt;
wire [19:0] maxCount;
parameter [10:0] INIT_X = 320;
parameter [10:0] INIT_Y = 240;
assign didCollide = collided ^ rstCollided;
always@( negedge iPClk)
begin
if(iCollision == 1 && oDrawPixel == 1)
begin
collision = 1;
end
else
begin
collision = 0;
end
end
always@(posedge collision)
begin
collided = ~collided;
end
assign firing = fired ^ done;
always@(posedge iFireTorpedo)
begin
if(!firing)
begin
direction = iDir;
fired = ~fired;
end
else
begin
end
end
assign col = iVGA_X - pos_X;
assign row = iVGA_Y - pos_Y;
assign inPosition = ((iVGA_X - pos_X)) < 5 && ((iVGA_Y - pos_Y) < 5);
assign drawTorpedo = inPosition && firing;
assign oDrawPixel = (drawTorpedo) ? current[col] : 0 ;
initial
begin
fired = 0;
done = 0;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
assign maxCount = ((direction%2) == 1) ? 20'h7FFFF : 20'h5A826 ;
assign tAddr = row;
always@(posedge iMemClk or negedge iRst)
begin
if(!iRst)
begin
if (didCollide)
begin
rstCollided = ~rstCollided;
end
else
begin
end
if(firing)
begin
done = ~done;
end
else
begin
end
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(didCollide)
begin
rstCollided = ~rstCollided;
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else if(firing)
begin
if(pos_X == 10'b1111111111)
begin
pos_X = INIT_X;
pos_Y = INIT_Y;
cnt = 0;
end
else
begin
if(cnt < maxCount)
cnt = cnt + 1'b1;
else
cnt = 0;
if (cnt == 0)
begin
case (direction)
3'b000 : pos_Y = pos_Y - 1'b1;
3'b001 : pos_Y = pos_Y - 1'b1;
3'b010 : pos_Y = pos_Y;
3'b011 : pos_Y = pos_Y + 1'b1;
3'b100 : pos_Y = pos_Y + 1'b1;
3'b101 : pos_Y = pos_Y + 1'b1;
3'b110 : pos_Y = pos_Y;
3'b111 : pos_Y = pos_Y - 1'b1;
default: begin end
endcase
case (direction)
3'b000 : pos_X = pos_X;
3'b001 : pos_X = pos_X - 1'b1;
3'b010 : pos_X = pos_X - 1'b1;
3'b011 : pos_X = pos_X - 1'b1;
3'b100 : pos_X = pos_X;
3'b101 : pos_X = pos_X + 1'b1;
3'b110 : pos_X = pos_X + 1'b1;
3'b111 : pos_X = pos_X + 1'b1;
default: begin end
endcase
if(pos_Y > 480 || pos_X > 640)
begin
done = ~done;
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
else
begin
end
end
else
begin
end
end
end
else
begin
pos_X = 10'b1111111111;
pos_Y = 10'b1111111111;
end
end
endmodule | 1 |
5,045 | data/full_repos/permissive/113002755/verilog/RNG/asteroid_placer.v | 113,002,755 | asteroid_placer.v | v | 168 | 92 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113002755/verilog/RNG/asteroid_placer.v:26: Cannot find file containing module: 'rng'\nrng R1(random1, iClk, iRst);\n^~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.v\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.sv\n rng\n rng.v\n rng.sv\n obj_dir/rng\n obj_dir/rng.v\n obj_dir/rng.sv\n%Error: data/full_repos/permissive/113002755/verilog/RNG/asteroid_placer.v:27: Cannot find file containing module: 'rng'\nrng R2(random2, iClk, iRst);\n^~~\n%Error: data/full_repos/permissive/113002755/verilog/RNG/asteroid_placer.v:28: Cannot find file containing module: 'rng'\nrng R3(random3, iClk, iRst);\n^~~\n%Error: Exiting due to 3 error(s)\n" | 5,539 | module | module asteroid_placer(
iClk,
iRst,
oDir,
oPosX,
oPosY,
oSize
);
rng R1(random1, iClk, iRst);
rng R2(random2, iClk, iRst);
rng R3(random3, iClk, iRst);
input iClk;
input iRst;
output [2:0] oDir;
output [10:0] oPosX;
output [10:0] oPosY;
output [1:0] oSize;
reg [10:0] oPosX;
reg [10:0] oPosY;
wire [2:0] random1;
wire [2:0] random2;
wire [2:0] random3;
wire [1:0] oSize;
wire [2:0] dir_sel;
assign dir_sel[2] = random1[2];
assign dir_sel[1] = random1[1];
assign dir_sel[0] = random2[0];
assign oSize = random3[1:0];
wire [2:0] position;
assign position[2] = random2[2];
assign position[1] = random2[1];
assign position[0] = random2[0];
wire [1:0] offset_sel;
assign offset_sel[1] = random2[2];
assign offset_sel[0] = random2[1];
reg [2:0] direction;
assign oDir = direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
reg [10:0] offset_X;
reg [10:0] offset_Y;
reg [10:0] total_X;
reg [10:0] total_Y;
always@(negedge iClk)
begin
oPosX = total_X;
oPosY = total_Y;
end
always @(negedge iClk or negedge iRst)
begin
case (dir_sel)
3'b000 : direction = 3'h5;
3'b001 : direction = 3'h3;
3'b010 : direction = 3'h3;
3'b011 : direction = 3'h1;
3'b100 : direction = 3'h1;
3'b101 : direction = 3'h7;
3'b110 : direction = 3'h7;
3'b111 : direction = 3'h5;
endcase
case (position)
3'b000 : pos_X = 175;
3'b001 : pos_X = 515;
3'b010 : pos_X = 640;
3'b011 : pos_X = 640;
3'b100 : pos_X = 475;
3'b101 : pos_X = 195;
3'b110 : pos_X = 0;
3'b111 : pos_X = 0;
endcase
case (position)
3'b000 : pos_Y = 0;
3'b001 : pos_Y = 0;
3'b010 : pos_Y = 115;
3'b011 : pos_Y = 375;
3'b100 : pos_Y = 480;
3'b101 : pos_Y = 480;
3'b110 : pos_Y = 355;
3'b111 : pos_Y = 125;
endcase
case (offset_sel[0])
0 : offset_X = 40;
1 : offset_X = 80;
endcase
case (offset_sel[0])
0 : offset_Y = 30;
1 : offset_Y = 60;
endcase
case (position)
3'b000 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b001 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b010 : total_X <= pos_X;
3'b011 : total_X <= pos_X;
3'b100 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b101 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b110 : total_X <= pos_X;
3'b111 : total_X <= pos_X;
endcase
case (position)
3'b000 : total_Y <= pos_Y;
3'b001 : total_Y <= pos_Y;
3'b010 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b011 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b100 : total_Y <= pos_Y;
3'b101 : total_Y <= pos_Y;
3'b110 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b111 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
endcase
end
endmodule | module asteroid_placer(
iClk,
iRst,
oDir,
oPosX,
oPosY,
oSize
); |
rng R1(random1, iClk, iRst);
rng R2(random2, iClk, iRst);
rng R3(random3, iClk, iRst);
input iClk;
input iRst;
output [2:0] oDir;
output [10:0] oPosX;
output [10:0] oPosY;
output [1:0] oSize;
reg [10:0] oPosX;
reg [10:0] oPosY;
wire [2:0] random1;
wire [2:0] random2;
wire [2:0] random3;
wire [1:0] oSize;
wire [2:0] dir_sel;
assign dir_sel[2] = random1[2];
assign dir_sel[1] = random1[1];
assign dir_sel[0] = random2[0];
assign oSize = random3[1:0];
wire [2:0] position;
assign position[2] = random2[2];
assign position[1] = random2[1];
assign position[0] = random2[0];
wire [1:0] offset_sel;
assign offset_sel[1] = random2[2];
assign offset_sel[0] = random2[1];
reg [2:0] direction;
assign oDir = direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
reg [10:0] offset_X;
reg [10:0] offset_Y;
reg [10:0] total_X;
reg [10:0] total_Y;
always@(negedge iClk)
begin
oPosX = total_X;
oPosY = total_Y;
end
always @(negedge iClk or negedge iRst)
begin
case (dir_sel)
3'b000 : direction = 3'h5;
3'b001 : direction = 3'h3;
3'b010 : direction = 3'h3;
3'b011 : direction = 3'h1;
3'b100 : direction = 3'h1;
3'b101 : direction = 3'h7;
3'b110 : direction = 3'h7;
3'b111 : direction = 3'h5;
endcase
case (position)
3'b000 : pos_X = 175;
3'b001 : pos_X = 515;
3'b010 : pos_X = 640;
3'b011 : pos_X = 640;
3'b100 : pos_X = 475;
3'b101 : pos_X = 195;
3'b110 : pos_X = 0;
3'b111 : pos_X = 0;
endcase
case (position)
3'b000 : pos_Y = 0;
3'b001 : pos_Y = 0;
3'b010 : pos_Y = 115;
3'b011 : pos_Y = 375;
3'b100 : pos_Y = 480;
3'b101 : pos_Y = 480;
3'b110 : pos_Y = 355;
3'b111 : pos_Y = 125;
endcase
case (offset_sel[0])
0 : offset_X = 40;
1 : offset_X = 80;
endcase
case (offset_sel[0])
0 : offset_Y = 30;
1 : offset_Y = 60;
endcase
case (position)
3'b000 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b001 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b010 : total_X <= pos_X;
3'b011 : total_X <= pos_X;
3'b100 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b101 : total_X <= (offset_sel[1] == 0)?pos_X - offset_X:pos_X + offset_X;
3'b110 : total_X <= pos_X;
3'b111 : total_X <= pos_X;
endcase
case (position)
3'b000 : total_Y <= pos_Y;
3'b001 : total_Y <= pos_Y;
3'b010 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b011 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b100 : total_Y <= pos_Y;
3'b101 : total_Y <= pos_Y;
3'b110 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
3'b111 : total_Y <= (offset_sel[1] == 0)?pos_Y - offset_Y:pos_Y + offset_Y;
endcase
end
endmodule | 1 |
5,046 | data/full_repos/permissive/113002755/verilog/RNG/asteroid_timer.v | 113,002,755 | asteroid_timer.v | v | 62 | 72 | [] | [] | [] | [(13, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/113002755/verilog/RNG/asteroid_timer.v:28: Cannot find file containing module: 'rng'\nrng R1(random, clk, rst);\n^~~\n ... Looked in:\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.v\n data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.sv\n rng\n rng.v\n rng.sv\n obj_dir/rng\n obj_dir/rng.v\n obj_dir/rng.sv\n%Error: Exiting due to 1 error(s)\n" | 5,540 | module | module asteroid_timer(clk, rst, delay, fire);
input clk, rst;
input [31:0] delay;
output reg fire;
reg [31:0] i;
wire [2:0] random;
rng R1(random, clk, rst);
always @(posedge clk or negedge rst)
begin
if (rst == 1'b0)
begin
i = 0;
fire = 0;
end
else
begin
i = i + 1;
fire = 0;
if (i >= delay)
begin
i = 0;
if (random < 2)
begin
fire = 1;
end
else
begin
fire = 0;
end
end
else
begin
end
end
end
endmodule | module asteroid_timer(clk, rst, delay, fire); |
input clk, rst;
input [31:0] delay;
output reg fire;
reg [31:0] i;
wire [2:0] random;
rng R1(random, clk, rst);
always @(posedge clk or negedge rst)
begin
if (rst == 1'b0)
begin
i = 0;
fire = 0;
end
else
begin
i = i + 1;
fire = 0;
if (i >= delay)
begin
i = 0;
if (random < 2)
begin
fire = 1;
end
else
begin
fire = 0;
end
end
else
begin
end
end
end
endmodule | 1 |
5,047 | data/full_repos/permissive/113002755/verilog/RNG/divider.v | 113,002,755 | divider.v | v | 37 | 72 | [] | [] | [] | [(12, 37)] | null | data/verilator_xmls/6994ad65-e7bc-4ab1-95b4-a64a0c039d96.xml | null | 5,541 | module | module divider(clk,rst,clk_out);
input clk,rst;
output reg clk_out;
reg [2:0] i;
always @(posedge clk or negedge rst)
begin
if (rst == 1'b0)
begin
i = 0;
clk_out = 0;
end
else
begin
i = i + 1;
if (i >= 5)
begin
clk_out = ~clk_out;
i = 0;
end
end
end
endmodule | module divider(clk,rst,clk_out); |
input clk,rst;
output reg clk_out;
reg [2:0] i;
always @(posedge clk or negedge rst)
begin
if (rst == 1'b0)
begin
i = 0;
clk_out = 0;
end
else
begin
i = i + 1;
if (i >= 5)
begin
clk_out = ~clk_out;
i = 0;
end
end
end
endmodule | 1 |
5,049 | data/full_repos/permissive/113002755/verilog/RNG/lfsr_4.v | 113,002,755 | lfsr_4.v | v | 43 | 72 | [] | [] | [] | [(16, 42)] | null | data/verilator_xmls/0a1f69af-570a-4c8c-ad28-15a6b143f874.xml | null | 5,544 | module | module lfsr_4(next_bit, state, seed, clk, rst);
output next_bit;
output [3:0] state;
reg [3:0] state;
input [3:0] seed;
input clk, rst;
wire linear_feedback;
assign linear_feedback = state[3] ^ state[2];
assign next_bit = linear_feedback;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= seed ;
end
else
begin
state <= {state[2],
state[1],
state[0],
linear_feedback};
end
endmodule | module lfsr_4(next_bit, state, seed, clk, rst); |
output next_bit;
output [3:0] state;
reg [3:0] state;
input [3:0] seed;
input clk, rst;
wire linear_feedback;
assign linear_feedback = state[3] ^ state[2];
assign next_bit = linear_feedback;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= seed ;
end
else
begin
state <= {state[2],
state[1],
state[0],
linear_feedback};
end
endmodule | 1 |
5,051 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module FA_1bit (input a,b,cin, output s,cout);
xor(o1,a,b);
xor(s,o1,cin);
and(o2,a,b);
and(o3,o1,cin);
or(cout,o2,o3);
endmodule | module FA_1bit (input a,b,cin, output s,cout); |
xor(o1,a,b);
xor(s,o1,cin);
and(o2,a,b);
and(o3,o1,cin);
or(cout,o2,o3);
endmodule | 1 |
5,052 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module EN_not(input [31:0]a, input en, output [31:0]c);
xor(c[0],a[0],en);
xor(c[1],a[1],en);
xor(c[2],a[2],en);
xor(c[3],a[3],en);
xor(c[4],a[4],en);
xor(c[5],a[5],en);
xor(c[6],a[6],en);
xor(c[7],a[7],en);
xor(c[8],a[8],en);
xor(c[9],a[9],en);
xor(c[10],a[10],en);
xor(c[11],a[11],en);
xor(c[12],a[12],en);
xor(c[13],a[13],en);
xor(c[14],a[14],en);
xor(c[15],a[15],en);
xor(c[16],a[16],en);
xor(c[17],a[17],en);
xor(c[18],a[18],en);
xor(c[19],a[19],en);
xor(c[20],a[20],en);
xor(c[21],a[21],en);
xor(c[22],a[22],en);
xor(c[23],a[23],en);
xor(c[24],a[24],en);
xor(c[25],a[25],en);
xor(c[26],a[26],en);
xor(c[27],a[27],en);
xor(c[28],a[28],en);
xor(c[29],a[29],en);
xor(c[30],a[30],en);
xor(c[31],a[31],en);
endmodule | module EN_not(input [31:0]a, input en, output [31:0]c); |
xor(c[0],a[0],en);
xor(c[1],a[1],en);
xor(c[2],a[2],en);
xor(c[3],a[3],en);
xor(c[4],a[4],en);
xor(c[5],a[5],en);
xor(c[6],a[6],en);
xor(c[7],a[7],en);
xor(c[8],a[8],en);
xor(c[9],a[9],en);
xor(c[10],a[10],en);
xor(c[11],a[11],en);
xor(c[12],a[12],en);
xor(c[13],a[13],en);
xor(c[14],a[14],en);
xor(c[15],a[15],en);
xor(c[16],a[16],en);
xor(c[17],a[17],en);
xor(c[18],a[18],en);
xor(c[19],a[19],en);
xor(c[20],a[20],en);
xor(c[21],a[21],en);
xor(c[22],a[22],en);
xor(c[23],a[23],en);
xor(c[24],a[24],en);
xor(c[25],a[25],en);
xor(c[26],a[26],en);
xor(c[27],a[27],en);
xor(c[28],a[28],en);
xor(c[29],a[29],en);
xor(c[30],a[30],en);
xor(c[31],a[31],en);
endmodule | 1 |
5,053 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module RCA_4bit (input [3:0]a,b, input cin, output [3:0]s, output cout);
FA_1bit f1 (a[0],b[0],cin,s[0],c0),
f2 (a[1],b[1],c0,s[1],c1),
f3 (a[2],b[2],c1,s[2],c2),
f4 (a[3],b[3],c2,s[3],cout);
endmodule | module RCA_4bit (input [3:0]a,b, input cin, output [3:0]s, output cout); |
FA_1bit f1 (a[0],b[0],cin,s[0],c0),
f2 (a[1],b[1],c0,s[1],c1),
f3 (a[2],b[2],c1,s[2],c2),
f4 (a[3],b[3],c2,s[3],cout);
endmodule | 1 |
5,054 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module RCA_16bit (input [15:0]a,b, input cin, output [15:0]s, output cout);
RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),
f2 (a[7:4],b[7:4],c0,s[7:4],c1),
f3 (a[11:8],b[11:8],c1,s[11:8],c2),
f4 (a[15:12],b[15:12],c2,s[15:12],cout);
endmodule | module RCA_16bit (input [15:0]a,b, input cin, output [15:0]s, output cout); |
RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),
f2 (a[7:4],b[7:4],c0,s[7:4],c1),
f3 (a[11:8],b[11:8],c1,s[11:8],c2),
f4 (a[15:12],b[15:12],c2,s[15:12],cout);
endmodule | 1 |
5,055 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module RCA_32bit (input [31:0]a,b, input en, output [31:0]s, output cout,ovfl);
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),
f2 (a[31:16],c[31:16],c0,s[31:16],cout);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | module RCA_32bit (input [31:0]a,b, input en, output [31:0]s, output cout,ovfl); |
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),
f2 (a[31:16],c[31:16],c0,s[31:16],cout);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | 1 |
5,056 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module mux (input a,b,s, output r);
and(o1,a,~s);
and(o2,b,s);
or(r,o1,o2);
endmodule | module mux (input a,b,s, output r); |
and(o1,a,~s);
and(o2,b,s);
or(r,o1,o2);
endmodule | 1 |
5,057 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CSA_2bit (input [1:0]a,b, input cin, output [1:0]s, output cout);
FA_1bit f1 (a[0],b[0],cin,s[0],c0),
f2 (a[1],b[1],1'b0,o1,c1),
f3 (a[1],b[1],1'b1,o2,c2);
mux m1 (o1,o2,c0,s[1]),
m2 (c1,c2,c0,cout);
endmodule | module CSA_2bit (input [1:0]a,b, input cin, output [1:0]s, output cout); |
FA_1bit f1 (a[0],b[0],cin,s[0],c0),
f2 (a[1],b[1],1'b0,o1,c1),
f3 (a[1],b[1],1'b1,o2,c2);
mux m1 (o1,o2,c0,s[1]),
m2 (c1,c2,c0,cout);
endmodule | 1 |
5,058 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CSA_4bit (input [3:0]a,b, input cin, output [3:0]s, output cout);
wire [1:0]o1,o2;
CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),
f2 (a[3:2],b[3:2],1'b0,o1[1:0],c1),
f3 (a[3:2],b[3:2],1'b1,o2[1:0],c2);
mux m1 (o1[0],o2[0],c0,s[2]),
m2 (o1[1],o2[1],c0,s[3]),
m3 (c1,c2,c0,cout);
endmodule | module CSA_4bit (input [3:0]a,b, input cin, output [3:0]s, output cout); |
wire [1:0]o1,o2;
CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),
f2 (a[3:2],b[3:2],1'b0,o1[1:0],c1),
f3 (a[3:2],b[3:2],1'b1,o2[1:0],c2);
mux m1 (o1[0],o2[0],c0,s[2]),
m2 (o1[1],o2[1],c0,s[3]),
m3 (c1,c2,c0,cout);
endmodule | 1 |
5,059 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CSA_8bit (input [7:0]a,b, input cin, output [7:0]s, output cout);
wire [3:0]o1,o2;
CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),
f2 (a[7:4],b[7:4],1'b0,o1[3:0],c1),
f3 (a[7:4],b[7:4],1'b1,o2[3:0],c2);
mux m1 (o1[0],o2[0],c0,s[4]),
m2 (o1[1],o2[1],c0,s[5]),
m3 (o1[2],o2[2],c0,s[6]),
m4 (o1[3],o2[3],c0,s[7]),
m5 (c1,c2,c0,cout);
endmodule | module CSA_8bit (input [7:0]a,b, input cin, output [7:0]s, output cout); |
wire [3:0]o1,o2;
CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),
f2 (a[7:4],b[7:4],1'b0,o1[3:0],c1),
f3 (a[7:4],b[7:4],1'b1,o2[3:0],c2);
mux m1 (o1[0],o2[0],c0,s[4]),
m2 (o1[1],o2[1],c0,s[5]),
m3 (o1[2],o2[2],c0,s[6]),
m4 (o1[3],o2[3],c0,s[7]),
m5 (c1,c2,c0,cout);
endmodule | 1 |
5,060 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CSA_16bit (input [15:0]a,b, input cin, output [15:0]s, output cout);
wire [7:0]o1,o2;
CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),
f2 (a[15:8],b[15:8],1'b0,o1[7:0],c1),
f3 (a[15:8],b[15:8],1'b1,o2[7:0],c2);
mux m1 (o1[0],o2[0],c0,s[8]),
m2 (o1[1],o2[1],c0,s[9]),
m3 (o1[2],o2[2],c0,s[10]),
m4 (o1[3],o2[3],c0,s[11]),
m5 (o1[4],o2[4],c0,s[12]),
m6 (o1[5],o2[5],c0,s[13]),
m7 (o1[6],o2[6],c0,s[14]),
m8 (o1[7],o2[7],c0,s[15]),
m9 (c1,c2,c0,cout);
endmodule | module CSA_16bit (input [15:0]a,b, input cin, output [15:0]s, output cout); |
wire [7:0]o1,o2;
CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),
f2 (a[15:8],b[15:8],1'b0,o1[7:0],c1),
f3 (a[15:8],b[15:8],1'b1,o2[7:0],c2);
mux m1 (o1[0],o2[0],c0,s[8]),
m2 (o1[1],o2[1],c0,s[9]),
m3 (o1[2],o2[2],c0,s[10]),
m4 (o1[3],o2[3],c0,s[11]),
m5 (o1[4],o2[4],c0,s[12]),
m6 (o1[5],o2[5],c0,s[13]),
m7 (o1[6],o2[6],c0,s[14]),
m8 (o1[7],o2[7],c0,s[15]),
m9 (c1,c2,c0,cout);
endmodule | 1 |
5,061 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CSA_32bit (input [31:0]a,b, input en, output [31:0]s, output cout,ovfl);
wire [15:0]o1,o2;
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),
f2 (a[31:16],c[31:16],1'b0,o1[15:0],c1),
f3 (a[31:16],c[31:16],1'b1,o2[15:0],c2);
mux m1 (o1[0],o2[0],c0,s[16]),
m2 (o1[1],o2[1],c0,s[17]),
m3 (o1[2],o2[2],c0,s[18]),
m4 (o1[3],o2[3],c0,s[19]),
m5 (o1[4],o2[4],c0,s[20]),
m6 (o1[5],o2[5],c0,s[21]),
m7 (o1[6],o2[6],c0,s[22]),
m8 (o1[7],o2[7],c0,s[23]),
m9 (o1[8],o2[8],c0,s[24]),
m10 (o1[9],o2[9],c0,s[25]),
m11 (o1[10],o2[10],c0,s[26]),
m12 (o1[11],o2[11],c0,s[27]),
m13 (o1[12],o2[12],c0,s[28]),
m14 (o1[13],o2[13],c0,s[29]),
m15 (o1[14],o2[14],c0,s[30]),
m16 (o1[15],o2[15],c0,s[31]),
m17 (c1,c2,c0,cout);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | module CSA_32bit (input [31:0]a,b, input en, output [31:0]s, output cout,ovfl); |
wire [15:0]o1,o2;
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),
f2 (a[31:16],c[31:16],1'b0,o1[15:0],c1),
f3 (a[31:16],c[31:16],1'b1,o2[15:0],c2);
mux m1 (o1[0],o2[0],c0,s[16]),
m2 (o1[1],o2[1],c0,s[17]),
m3 (o1[2],o2[2],c0,s[18]),
m4 (o1[3],o2[3],c0,s[19]),
m5 (o1[4],o2[4],c0,s[20]),
m6 (o1[5],o2[5],c0,s[21]),
m7 (o1[6],o2[6],c0,s[22]),
m8 (o1[7],o2[7],c0,s[23]),
m9 (o1[8],o2[8],c0,s[24]),
m10 (o1[9],o2[9],c0,s[25]),
m11 (o1[10],o2[10],c0,s[26]),
m12 (o1[11],o2[11],c0,s[27]),
m13 (o1[12],o2[12],c0,s[28]),
m14 (o1[13],o2[13],c0,s[29]),
m15 (o1[14],o2[14],c0,s[30]),
m16 (o1[15],o2[15],c0,s[31]),
m17 (c1,c2,c0,cout);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | 1 |
5,062 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module PG_FA (input a,b,cin, output s,p,g);
xor(p,a,b);
xor(s,p,cin);
and(g,a,b);
endmodule | module PG_FA (input a,b,cin, output s,p,g); |
xor(p,a,b);
xor(s,p,cin);
and(g,a,b);
endmodule | 1 |
5,063 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CLA_4bit (input [3:0]a,b, input cin, output[3:0]s, output cout,pg,gg);
wire [3:0]p,g;
assign c1=g[0]+(p[0]&cin);
assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);
assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);
assign cout=g[3]+(g[2]&p[3])+(g[1]&p[2]&p[3])+(g[0]&p[1]&p[2]&p[3])+(cin&p[0]&p[1]&p[2]&p[3]);
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]+(p[3]&g[2])+(p[3]&p[2]&g[1])+(p[3]&p[2]&p[1]&g[0]);
PG_FA f1 (a[0],b[0],cin,s[0],p[0],g[0]),
f2 (a[1],b[1],c1,s[1],p[1],g[1]),
f3 (a[2],b[2],c2,s[2],p[2],g[2]),
f4 (a[3],b[3],c3,s[3],p[3],g[3]);
endmodule | module CLA_4bit (input [3:0]a,b, input cin, output[3:0]s, output cout,pg,gg); |
wire [3:0]p,g;
assign c1=g[0]+(p[0]&cin);
assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);
assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);
assign cout=g[3]+(g[2]&p[3])+(g[1]&p[2]&p[3])+(g[0]&p[1]&p[2]&p[3])+(cin&p[0]&p[1]&p[2]&p[3]);
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]+(p[3]&g[2])+(p[3]&p[2]&g[1])+(p[3]&p[2]&p[1]&g[0]);
PG_FA f1 (a[0],b[0],cin,s[0],p[0],g[0]),
f2 (a[1],b[1],c1,s[1],p[1],g[1]),
f3 (a[2],b[2],c2,s[2],p[2],g[2]),
f4 (a[3],b[3],c3,s[3],p[3],g[3]);
endmodule | 1 |
5,064 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CLA_16bit (input [15:0]a,b, input cin, output[15:0]s, output cout,pg,gg);
wire [3:0]p,g;
assign c1=g[0]+(p[0]&cin);
assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);
assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);
assign cout=g[3]+(g[2]&p[3])+(g[1]&p[2]&p[3])+(g[0]&p[1]&p[2]&p[3])+(cin&p[0]&p[1]&p[2]&p[3]);
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]+(p[3]&g[2])+(p[3]&p[2]&g[1])+(p[3]&p[2]&p[1]&g[0]);
CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),
f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),
f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),
f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);
endmodule | module CLA_16bit (input [15:0]a,b, input cin, output[15:0]s, output cout,pg,gg); |
wire [3:0]p,g;
assign c1=g[0]+(p[0]&cin);
assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);
assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);
assign cout=g[3]+(g[2]&p[3])+(g[1]&p[2]&p[3])+(g[0]&p[1]&p[2]&p[3])+(cin&p[0]&p[1]&p[2]&p[3]);
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]+(p[3]&g[2])+(p[3]&p[2]&g[1])+(p[3]&p[2]&p[1]&g[0]);
CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),
f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),
f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),
f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);
endmodule | 1 |
5,065 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module CLA_32bit (input [31:0]a,b, input en, output[31:0]s, output cout,ovfl);
wire [1:0]p,g;
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
assign c1=g[0]+(p[0]&en);
assign cout=g[1]+(g[0]&p[1])+(en&p[0]&p[1]);
CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),
f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | module CLA_32bit (input [31:0]a,b, input en, output[31:0]s, output cout,ovfl); |
wire [1:0]p,g;
wire [31:0]c;
EN_not en1 (b[31:0],en,c[31:0]);
assign c1=g[0]+(p[0]&en);
assign cout=g[1]+(g[0]&p[1])+(en&p[0]&p[1]);
CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),
f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);
wire q,x0,x1,z;
xor(q,a[31],b[31]);
xor(x0,q,en);
not(x1,x0);
xor(z,a[31],s[31]);
and(ovfl,x1,z);
endmodule | 1 |
5,066 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRLogical1 (input [31:0]a, output [31:0]s, output cout,ovfl);
assign s[31]=1'b0;
assign s[30:0]=a[31:1];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRLogical1 (input [31:0]a, output [31:0]s, output cout,ovfl); |
assign s[31]=1'b0;
assign s[30:0]=a[31:1];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,067 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRLogical2 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRLogical2 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,068 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRLogical4 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRLogical4 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,069 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRLogical8 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRLogical8 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,070 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRLogical16 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRLogical16 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftRLogical8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,071 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLLogical1 (input [31:0]a, output [31:0]s, output cout,ovfl);
assign s[0]=1'b0;
assign s[31:1]=a[30:0];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftLLogical1 (input [31:0]a, output [31:0]s, output cout,ovfl); |
assign s[0]=1'b0;
assign s[31:1]=a[30:0];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,072 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLLogical2 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
endmodule | module ShiftLLogical2 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
endmodule | 1 |
5,073 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLLogical4 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftLLogical4 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,074 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLLogical8 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftLLogical8 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,075 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLLogical16 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftLLogical16 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,o,p;
ShiftLLogical8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],o,p);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,076 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLArithmetic1 (input [31:0]a, output [31:0]s, output cout,ovfl);
assign s[0]=1'b0;
assign s[31:1]=a[30:0];
xor(ovfl,a[31],a[30]);
assign cout=1'b0;
endmodule | module ShiftLArithmetic1 (input [31:0]a, output [31:0]s, output cout,ovfl); |
assign s[0]=1'b0;
assign s[31:1]=a[30:0];
xor(ovfl,a[31],a[30]);
assign cout=1'b0;
endmodule | 1 |
5,077 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLArithmetic2 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | module ShiftLArithmetic2 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | 1 |
5,078 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLArithmetic4 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | module ShiftLArithmetic4 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | 1 |
5,079 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLArithmetic8 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | module ShiftLArithmetic8 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | 1 |
5,080 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftLArithmetic16 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | module ShiftLArithmetic16 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
assign cout=1'b0;
ShiftLArithmetic8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
or(ovfl,n,q);
endmodule | 1 |
5,081 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRArithmetic1 (input [31:0]a, output [31:0]s, output cout,ovfl);
assign s[31]=a[31];
assign s[30:0]=a[31:1];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRArithmetic1 (input [31:0]a, output [31:0]s, output cout,ovfl); |
assign s[31]=a[31];
assign s[30:0]=a[31:1];
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,082 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRArithmetic2 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRArithmetic2 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic1 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,083 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRArithmetic4 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRArithmetic4 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic2 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,084 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRArithmetic8 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRArithmetic8 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic4 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,085 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ShiftRArithmetic16 (input [31:0]a, output [31:0]s, output cout,ovfl);
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module ShiftRArithmetic16 (input [31:0]a, output [31:0]s, output cout,ovfl); |
wire [31:0]k;
wire m,n,p,q;
ShiftRArithmetic8 s1 (a[31:0],k[31:0],m,n),
s2 (k[31:0],s[31:0],p,q);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,086 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module multiplier_8x1 (input [7:0]a,input b, output [7:0]s);
and(s[0],a[0],b);
and(s[1],a[1],b);
and(s[2],a[2],b);
and(s[3],a[3],b);
and(s[4],a[4],b);
and(s[5],a[5],b);
and(s[6],a[6],b);
and(s[7],a[7],b);
endmodule | module multiplier_8x1 (input [7:0]a,input b, output [7:0]s); |
and(s[0],a[0],b);
and(s[1],a[1],b);
and(s[2],a[2],b);
and(s[3],a[3],b);
and(s[4],a[4],b);
and(s[5],a[5],b);
and(s[6],a[6],b);
and(s[7],a[7],b);
endmodule | 1 |
5,087 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module multiplier_8x8 (input [7:0]a,b, output [31:0]s,output cout,ovfl);
wire [31:0]r0,r1,r2,r3,r4,r5,r6,r7,k1,k2,k3,k4,k5,k6,k7,l3,l7,m6,m5,m7,s1,s2,s3,s4,s5,s6,s7;
wire c1,c2,c3,c4,c5,c6,c7;
wire [25:8]o;
wire [19:8]c;
assign cout=1'b0;
assign ovfl=1'b0;
multiplier_8x1 n0 (a[7:0],b[0],r0[7:0]),
n1 (a[7:0],b[1],k1[7:0]),
n2 (a[7:0],b[2],k2[7:0]),
n3 (a[7:0],b[3],k3[7:0]),
n4 (a[7:0],b[4],k4[7:0]),
n5 (a[7:0],b[5],k5[7:0]),
n6 (a[7:0],b[6],k6[7:0]),
n7 (a[7:0],b[7],k7[7:0]);
ShiftLLogical1 p1 (k1[31:0],r1[31:0],c[8],o[8]),
p3 (l3[31:0],r3[31:0],c[9],o[9]),
p5 (m5[31:0],r5[31:0],c[10],o[10]),
p7 (l7[31:0],r7[31:0],c[11],o[11]);
ShiftLLogical2 t2 (k2[31:0],r2[31:0],c[12],o[12]),
t3 (k3[31:0],l3[31:0],c[13],o[13]),
t6 (m6[31:0],r6[31:0],c[14],o[14]),
t7 (m7[31:0],l7[31:0],c[15],o[15]);
ShiftLLogical4 u4 (k4[31:0],r4[31:0],c[16],o[16]),
u5 (k5[31:0],m5[31:0],c[17],o[17]),
u6 (k6[31:0],m6[31:0],c[18],o[18]),
u7 (k7[31:0],m7[31:0],c[19],o[19]);
CSA_32bit add0 (r0[31:0],r1[31:0],1'b0,s1[31:0],c1,o[20]),
add1 (s1[31:0],r2[31:0],1'b0,s2[31:0],c2,o[21]),
add2 (s2[31:0],r3[31:0],1'b0,s3[31:0],c3,o[22]),
add3 (s3[31:0],r4[31:0],1'b0,s4[31:0],c4,o[23]),
add4 (s4[31:0],r5[31:0],1'b0,s5[31:0],c5,o[24]),
add5 (s5[31:0],r6[31:0],1'b0,s6[31:0],c6,o[25]),
add6 (s6[31:0],r7[31:0],1'b0,s7[31:0],c7,o[25]);
assign r0[31:8]=24'b0;
assign r1[31:9]=23'b0;
assign r2[31:10]=22'b0;
assign r3[31:11]=21'b0;
assign r4[31:12]=20'b0;
assign r5[31:13]=19'b0;
assign r6[31:14]=18'b0;
assign r7[31:15]=17'b0;
assign s=s7;
endmodule | module multiplier_8x8 (input [7:0]a,b, output [31:0]s,output cout,ovfl); |
wire [31:0]r0,r1,r2,r3,r4,r5,r6,r7,k1,k2,k3,k4,k5,k6,k7,l3,l7,m6,m5,m7,s1,s2,s3,s4,s5,s6,s7;
wire c1,c2,c3,c4,c5,c6,c7;
wire [25:8]o;
wire [19:8]c;
assign cout=1'b0;
assign ovfl=1'b0;
multiplier_8x1 n0 (a[7:0],b[0],r0[7:0]),
n1 (a[7:0],b[1],k1[7:0]),
n2 (a[7:0],b[2],k2[7:0]),
n3 (a[7:0],b[3],k3[7:0]),
n4 (a[7:0],b[4],k4[7:0]),
n5 (a[7:0],b[5],k5[7:0]),
n6 (a[7:0],b[6],k6[7:0]),
n7 (a[7:0],b[7],k7[7:0]);
ShiftLLogical1 p1 (k1[31:0],r1[31:0],c[8],o[8]),
p3 (l3[31:0],r3[31:0],c[9],o[9]),
p5 (m5[31:0],r5[31:0],c[10],o[10]),
p7 (l7[31:0],r7[31:0],c[11],o[11]);
ShiftLLogical2 t2 (k2[31:0],r2[31:0],c[12],o[12]),
t3 (k3[31:0],l3[31:0],c[13],o[13]),
t6 (m6[31:0],r6[31:0],c[14],o[14]),
t7 (m7[31:0],l7[31:0],c[15],o[15]);
ShiftLLogical4 u4 (k4[31:0],r4[31:0],c[16],o[16]),
u5 (k5[31:0],m5[31:0],c[17],o[17]),
u6 (k6[31:0],m6[31:0],c[18],o[18]),
u7 (k7[31:0],m7[31:0],c[19],o[19]);
CSA_32bit add0 (r0[31:0],r1[31:0],1'b0,s1[31:0],c1,o[20]),
add1 (s1[31:0],r2[31:0],1'b0,s2[31:0],c2,o[21]),
add2 (s2[31:0],r3[31:0],1'b0,s3[31:0],c3,o[22]),
add3 (s3[31:0],r4[31:0],1'b0,s4[31:0],c4,o[23]),
add4 (s4[31:0],r5[31:0],1'b0,s5[31:0],c5,o[24]),
add5 (s5[31:0],r6[31:0],1'b0,s6[31:0],c6,o[25]),
add6 (s6[31:0],r7[31:0],1'b0,s7[31:0],c7,o[25]);
assign r0[31:8]=24'b0;
assign r1[31:9]=23'b0;
assign r2[31:10]=22'b0;
assign r3[31:11]=21'b0;
assign r4[31:12]=20'b0;
assign r5[31:13]=19'b0;
assign r6[31:14]=18'b0;
assign r7[31:15]=17'b0;
assign s=s7;
endmodule | 1 |
5,088 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module And_8bit (input [7:0]a,b, output [7:0]s);
and (s[0],a[0],b[0]);
and (s[1],a[1],b[1]);
and (s[2],a[2],b[2]);
and (s[3],a[3],b[3]);
and (s[4],a[4],b[4]);
and (s[5],a[5],b[5]);
and (s[6],a[6],b[6]);
and (s[7],a[7],b[7]);
endmodule | module And_8bit (input [7:0]a,b, output [7:0]s); |
and (s[0],a[0],b[0]);
and (s[1],a[1],b[1]);
and (s[2],a[2],b[2]);
and (s[3],a[3],b[3]);
and (s[4],a[4],b[4]);
and (s[5],a[5],b[5]);
and (s[6],a[6],b[6]);
and (s[7],a[7],b[7]);
endmodule | 1 |
5,089 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module And_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl);
And_8bit and1 (a[7:0],b[7:0],s[7:0]),
and2 (a[15:8],b[15:8],s[15:8]),
and3 (a[23:16],b[23:16],s[23:16]),
and4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module And_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl); |
And_8bit and1 (a[7:0],b[7:0],s[7:0]),
and2 (a[15:8],b[15:8],s[15:8]),
and3 (a[23:16],b[23:16],s[23:16]),
and4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,090 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module Or_8bit (input [7:0]a,b, output [7:0]s);
or (s[0],a[0],b[0]);
or (s[1],a[1],b[1]);
or (s[2],a[2],b[2]);
or (s[3],a[3],b[3]);
or (s[4],a[4],b[4]);
or (s[5],a[5],b[5]);
or (s[6],a[6],b[6]);
or (s[7],a[7],b[7]);
endmodule | module Or_8bit (input [7:0]a,b, output [7:0]s); |
or (s[0],a[0],b[0]);
or (s[1],a[1],b[1]);
or (s[2],a[2],b[2]);
or (s[3],a[3],b[3]);
or (s[4],a[4],b[4]);
or (s[5],a[5],b[5]);
or (s[6],a[6],b[6]);
or (s[7],a[7],b[7]);
endmodule | 1 |
5,091 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module Or_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl);
Or_8bit or1 (a[7:0],b[7:0],s[7:0]),
or2 (a[15:8],b[15:8],s[15:8]),
or3 (a[23:16],b[23:16],s[23:16]),
or4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module Or_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl); |
Or_8bit or1 (a[7:0],b[7:0],s[7:0]),
or2 (a[15:8],b[15:8],s[15:8]),
or3 (a[23:16],b[23:16],s[23:16]),
or4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,092 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module Xor_8bit (input [7:0]a,b, output [7:0]s);
xor (s[0],a[0],b[0]);
xor (s[1],a[1],b[1]);
xor (s[2],a[2],b[2]);
xor (s[3],a[3],b[3]);
xor (s[4],a[4],b[4]);
xor (s[5],a[5],b[5]);
xor (s[6],a[6],b[6]);
xor (s[7],a[7],b[7]);
endmodule | module Xor_8bit (input [7:0]a,b, output [7:0]s); |
xor (s[0],a[0],b[0]);
xor (s[1],a[1],b[1]);
xor (s[2],a[2],b[2]);
xor (s[3],a[3],b[3]);
xor (s[4],a[4],b[4]);
xor (s[5],a[5],b[5]);
xor (s[6],a[6],b[6]);
xor (s[7],a[7],b[7]);
endmodule | 1 |
5,093 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module Xor_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl);
Xor_8bit xor1 (a[7:0],b[7:0],s[7:0]),
xor2 (a[15:8],b[15:8],s[15:8]),
xor3 (a[23:16],b[23:16],s[23:16]),
xor4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module Xor_32bit (input [31:0]a,b, output [31:0]s, output cout,ovfl); |
Xor_8bit xor1 (a[7:0],b[7:0],s[7:0]),
xor2 (a[15:8],b[15:8],s[15:8]),
xor3 (a[23:16],b[23:16],s[23:16]),
xor4 (a[31:24],b[31:24],s[31:24]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,094 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module div_block (input a,b,ci,q , output co,r);
wire s1;
FA_1bit f1(a,b,ci,s1,co);
mux m1(b,s1,q,r);
endmodule | module div_block (input a,b,ci,q , output co,r); |
wire s1;
FA_1bit f1(a,b,ci,s1,co);
mux m1(b,s1,q,r);
endmodule | 1 |
5,095 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);
wire [28:0]c;
div_block d1(b[0],a[1],c[1],q[0],c[0],c[3]),
d2(b[1],a[2],c[4],q[0],c[1],c[5]),
d3(b[2],a[3],c[6],q[0],c[4],c[7]),
d4(b[3],a[4],1'b0,q[0],c[6],c[8]),
d5(b[0],c[5],c[10],q[1],c[9],c[11]),
d6(b[1],c[7],c[12],q[1],c[10],c[13]),
d7(b[2],c[8],c[14],q[1],c[12],c[15]),
d8(b[3],a[5],1'b0,q[1],c[14],c[16]),
d9(b[0],c[13],c[18],q[2],c[17],c[19]),
d10(b[1],c[15],c[20],q[2],c[18],c[21]),
d11(b[2],c[16],c[22],q[2],c[20],c[23]),
d12(b[3],a[6],1'b0,q[2],c[22],c[24]),
d13(b[0],c[21],c[26],q[3],c[25],r[0]),
d14(b[1],c[23],c[27],q[3],c[26],r[1]),
d15(b[2],c[24],c[28],q[3],c[27],r[2]),
d16(b[3],a[7],1'b0,q[3],c[28],r[3]);
or(q[0],a[0],~c[0]);
or(q[1],c[3],~c[9]);
or(q[2],c[11],~c[17]);
or(q[3],c[19],~c[25]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | module div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl); |
wire [28:0]c;
div_block d1(b[0],a[1],c[1],q[0],c[0],c[3]),
d2(b[1],a[2],c[4],q[0],c[1],c[5]),
d3(b[2],a[3],c[6],q[0],c[4],c[7]),
d4(b[3],a[4],1'b0,q[0],c[6],c[8]),
d5(b[0],c[5],c[10],q[1],c[9],c[11]),
d6(b[1],c[7],c[12],q[1],c[10],c[13]),
d7(b[2],c[8],c[14],q[1],c[12],c[15]),
d8(b[3],a[5],1'b0,q[1],c[14],c[16]),
d9(b[0],c[13],c[18],q[2],c[17],c[19]),
d10(b[1],c[15],c[20],q[2],c[18],c[21]),
d11(b[2],c[16],c[22],q[2],c[20],c[23]),
d12(b[3],a[6],1'b0,q[2],c[22],c[24]),
d13(b[0],c[21],c[26],q[3],c[25],r[0]),
d14(b[1],c[23],c[27],q[3],c[26],r[1]),
d15(b[2],c[24],c[28],q[3],c[27],r[2]),
d16(b[3],a[7],1'b0,q[3],c[28],r[3]);
or(q[0],a[0],~c[0]);
or(q[1],c[3],~c[9]);
or(q[2],c[11],~c[17]);
or(q[3],c[19],~c[25]);
assign cout=1'b0;
assign ovfl=1'b0;
endmodule | 1 |
5,096 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module mux_32x1 (input a31,a30,a29,a28,a27,a26,a25,a24,a23,a22,a21,a20,a19,a18,a17,a16,a15,a14,a13,a12,a11,a10,a9,a8,a7,a6,a5,a4,a3,a2,a1,a0,input [4:0]select,output o);
wire [31:0]w;
and(w[0],a0,~select[4],~select[3],~select[2],~select[1],~select[0]);
and(w[1],a1,~select[4],~select[3],~select[2],~select[1],select[0]);
and(w[2],a2,~select[4],~select[3],~select[2],select[1],~select[0]);
and(w[3],a3,~select[4],~select[3],~select[2],select[1],select[0]);
and(w[4],a4,~select[4],~select[3],select[2],~select[1],~select[0]);
and(w[5],a5,~select[4],~select[3],select[2],~select[1],select[0]);
and(w[6],a6,~select[4],~select[3],select[2],select[1],~select[0]);
and(w[7],a7,~select[4],~select[3],select[2],select[1],select[0]);
and(w[8],a8,~select[4],select[3],~select[2],~select[1],~select[0]);
and(w[9],a9,~select[4],select[3],~select[2],~select[1],select[0]);
and(w[10],a10,~select[4],select[3],~select[2],select[1],~select[0]);
and(w[11],a11,~select[4],select[3],~select[2],select[1],select[0]);
and(w[12],a12,~select[4],select[3],select[2],~select[1],~select[0]);
and(w[13],a13,~select[4],select[3],select[2],~select[1],select[0]);
and(w[14],a14,~select[4],select[3],select[2],select[1],~select[0]);
and(w[15],a15,~select[4],select[3],select[2],select[1],select[0]);
and(w[16],a16,select[4],~select[3],~select[2],~select[1],~select[0]);
and(w[17],a17,select[4],~select[3],~select[2],~select[1],select[0]);
and(w[18],a18,select[4],~select[3],~select[2],select[1],~select[0]);
and(w[19],a19,select[4],~select[3],~select[2],select[1],select[0]);
and(w[20],a20,select[4],~select[3],select[2],~select[1],~select[0]);
and(w[21],a21,select[4],~select[3],select[2],~select[1],select[0]);
and(w[22],a22,select[4],~select[3],select[2],select[1],~select[0]);
and(w[23],a23,select[4],~select[3],select[2],select[1],select[0]);
and(w[24],a24,select[4],select[3],~select[2],~select[1],~select[0]);
and(w[25],a25,select[4],select[3],~select[2],~select[1],select[0]);
and(w[26],a26,select[4],select[3],~select[2],select[1],~select[0]);
and(w[27],a27,select[4],select[3],~select[2],select[1],select[0]);
and(w[28],a28,select[4],select[3],select[2],~select[1],~select[0]);
and(w[29],a29,select[4],select[3],select[2],~select[1],select[0]);
and(w[30],a30,select[4],select[3],select[2],select[1],~select[0]);
and(w[31],a31,select[4],select[3],select[2],select[1],select[0]);
or(o,w[0],w[1],w[2],w[3],w[4],w[5],w[6],w[7],w[8],w[9],w[10],w[11],w[12],w[13],w[14],w[15],w[16],w[17],w[18],w[19],w[20],w[21],w[22],w[23],w[24],w[25],w[26],w[27],w[28],w[29],w[30],w[31]);
endmodule | module mux_32x1 (input a31,a30,a29,a28,a27,a26,a25,a24,a23,a22,a21,a20,a19,a18,a17,a16,a15,a14,a13,a12,a11,a10,a9,a8,a7,a6,a5,a4,a3,a2,a1,a0,input [4:0]select,output o); |
wire [31:0]w;
and(w[0],a0,~select[4],~select[3],~select[2],~select[1],~select[0]);
and(w[1],a1,~select[4],~select[3],~select[2],~select[1],select[0]);
and(w[2],a2,~select[4],~select[3],~select[2],select[1],~select[0]);
and(w[3],a3,~select[4],~select[3],~select[2],select[1],select[0]);
and(w[4],a4,~select[4],~select[3],select[2],~select[1],~select[0]);
and(w[5],a5,~select[4],~select[3],select[2],~select[1],select[0]);
and(w[6],a6,~select[4],~select[3],select[2],select[1],~select[0]);
and(w[7],a7,~select[4],~select[3],select[2],select[1],select[0]);
and(w[8],a8,~select[4],select[3],~select[2],~select[1],~select[0]);
and(w[9],a9,~select[4],select[3],~select[2],~select[1],select[0]);
and(w[10],a10,~select[4],select[3],~select[2],select[1],~select[0]);
and(w[11],a11,~select[4],select[3],~select[2],select[1],select[0]);
and(w[12],a12,~select[4],select[3],select[2],~select[1],~select[0]);
and(w[13],a13,~select[4],select[3],select[2],~select[1],select[0]);
and(w[14],a14,~select[4],select[3],select[2],select[1],~select[0]);
and(w[15],a15,~select[4],select[3],select[2],select[1],select[0]);
and(w[16],a16,select[4],~select[3],~select[2],~select[1],~select[0]);
and(w[17],a17,select[4],~select[3],~select[2],~select[1],select[0]);
and(w[18],a18,select[4],~select[3],~select[2],select[1],~select[0]);
and(w[19],a19,select[4],~select[3],~select[2],select[1],select[0]);
and(w[20],a20,select[4],~select[3],select[2],~select[1],~select[0]);
and(w[21],a21,select[4],~select[3],select[2],~select[1],select[0]);
and(w[22],a22,select[4],~select[3],select[2],select[1],~select[0]);
and(w[23],a23,select[4],~select[3],select[2],select[1],select[0]);
and(w[24],a24,select[4],select[3],~select[2],~select[1],~select[0]);
and(w[25],a25,select[4],select[3],~select[2],~select[1],select[0]);
and(w[26],a26,select[4],select[3],~select[2],select[1],~select[0]);
and(w[27],a27,select[4],select[3],~select[2],select[1],select[0]);
and(w[28],a28,select[4],select[3],select[2],~select[1],~select[0]);
and(w[29],a29,select[4],select[3],select[2],~select[1],select[0]);
and(w[30],a30,select[4],select[3],select[2],select[1],~select[0]);
and(w[31],a31,select[4],select[3],select[2],select[1],select[0]);
or(o,w[0],w[1],w[2],w[3],w[4],w[5],w[6],w[7],w[8],w[9],w[10],w[11],w[12],w[13],w[14],w[15],w[16],w[17],w[18],w[19],w[20],w[21],w[22],w[23],w[24],w[25],w[26],w[27],w[28],w[29],w[30],w[31]);
endmodule | 1 |
5,097 | data/full_repos/permissive/113036182/ALU32bit.v | 113,036,182 | ALU32bit.v | v | 629 | 275 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n ^~~~~~~\n : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n and(o1,a,~s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n and(o2,b,s);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],1\'b0,o1,c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n : ... Suggested alternative: \'o1\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[1],b[1],1\'b1,o2,c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[1],b[1],c0,s[1],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[2],b[2],c1,s[2],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n assign c1=g[0]+(p[0]&cin);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c1\'\n assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n : ... Suggested alternative: \'c1\'\n assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n : ... Suggested alternative: \'c2\'\n f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n : ... Suggested alternative: \'c3\'\n f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c\'\n f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c0\'\n f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n : ... Suggested alternative: \'c0\'\n f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n : ... Suggested alternative: \'c\'\n assign c1=g[0]+(p[0]&en);\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n : ... Suggested alternative: \'c1\'\n f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n : ... Suggested alternative: \'c\'\n RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n ^~\n%Error: Exiting due to 43 warning(s)\n' | 5,546 | module | module ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);
wire [31:0]s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,co,ov;
assign co[7]=co[8];
assign ov[7]=ov[8];
RCA_32bit f0 (a,b,1'b0,s0,co[0],ov[0]),
f1 (a,b,1'b1,s3,co[3],ov[3]);
CSA_32bit f2 (a,b,1'b0,s1,co[1],ov[1]),
f3 (a,b,1'b1,s4,co[4],ov[4]);
CLA_32bit f4 (a,b,1'b0,s2,co[2],ov[2]),
f5 (a,b,1'b1,s5,co[5],ov[5]);
multiplier_8x8 f6 (a[7:0],b[7:0],s6,co[6],ov[6]);
EN_not f7 (a,1'b1,s7);
And_32bit f8 (a,b,s8,co[8],ov[8]);
Or_32bit f9 (a,b,s9,co[9],ov[9]);
Xor_32bit f10 (a,b,s10,co[10],ov[10]);
ShiftRLogical1 f11 (a,s11,co[11],ov[11]);
ShiftRLogical2 f12 (a,s12,co[12],ov[12]);
ShiftRLogical4 f13 (a,s13,co[13],ov[13]);
ShiftRLogical8 f14 (a,s14,co[14],ov[14]);
ShiftRLogical16 f15 (a,s15,co[15],ov[15]);
ShiftRArithmetic1 f16 (a,s16,co[16],ov[16]);
ShiftRArithmetic2 f17 (a,s17,co[17],ov[17]);
ShiftRArithmetic4 f18 (a,s18,co[18],ov[18]);
ShiftRArithmetic8 f19(a,s19,co[19],ov[19]);
ShiftRArithmetic16 f20 (a,s20,co[20],ov[20]);
ShiftLLogical1 f21 (a,s21,co[21],ov[21]);
ShiftLLogical2 f22 (a,s22,co[22],ov[22]);
ShiftLLogical4 f23 (a,s23,co[23],ov[23]);
ShiftLLogical8 f24 (a,s24,co[24],ov[24]);
ShiftLLogical16 f25 (a,s25,co[25],ov[25]);
ShiftLArithmetic1 f26 (a,s26,co[26],ov[26]);
ShiftLArithmetic2 f27 (a,s27,co[27],ov[27]);
ShiftLArithmetic4 f28 (a,s28,co[28],ov[28]);
ShiftLArithmetic8 f29 (a,s29,co[29],ov[29]);
ShiftLArithmetic16 f30 (a,s30,co[30],ov[30]);
mux_32x1 m0 (s31[0],s30[0],s29[0],s28[0],s27[0],s26[0],s25[0],s24[0],s23[0],s22[0],s21[0],s20[0],s19[0],s18[0],s17[0],s16[0],s15[0],s14[0],s13[0],s12[0],s11[0],s10[0],s9[0],s8[0],s7[0],s6[0],s5[0],s4[0],s3[0],s2[0],s1[0],s0[0],select,c[0]),
m1 (s31[1],s30[1],s29[1],s28[1],s27[1],s26[1],s25[1],s24[1],s23[1],s22[1],s21[1],s20[1],s19[1],s18[1],s17[1],s16[1],s15[1],s14[1],s13[1],s12[1],s11[1],s10[1],s9[1],s8[1],s7[1],s6[1],s5[1],s4[1],s3[1],s2[1],s1[1],s0[1],select,c[1]),
m2 (s31[2],s30[2],s29[2],s28[2],s27[2],s26[2],s25[2],s24[2],s23[2],s22[2],s21[2],s20[2],s19[2],s18[2],s17[2],s16[2],s15[2],s14[2],s13[2],s12[2],s11[2],s10[2],s9[2],s8[2],s7[2],s6[2],s5[2],s4[2],s3[2],s2[2],s1[2],s0[2],select,c[2]),
m3 (s31[3],s30[3],s29[3],s28[3],s27[3],s26[3],s25[3],s24[3],s23[3],s22[3],s21[3],s20[3],s19[3],s18[3],s17[3],s16[3],s15[3],s14[3],s13[3],s12[3],s11[3],s10[3],s9[3],s8[3],s7[3],s6[3],s5[3],s4[3],s3[3],s2[3],s1[3],s0[3],select,c[3]),
m4 (s31[4],s30[4],s29[4],s28[4],s27[4],s26[4],s25[4],s24[4],s23[4],s22[4],s21[4],s20[4],s19[4],s18[4],s17[4],s16[4],s15[4],s14[4],s13[4],s12[4],s11[4],s10[4],s9[4],s8[4],s7[4],s6[4],s5[4],s4[4],s3[4],s2[4],s1[4],s0[4],select,c[4]),
m5 (s31[5],s30[5],s29[5],s28[5],s27[5],s26[5],s25[5],s24[5],s23[5],s22[5],s21[5],s20[5],s19[5],s18[5],s17[5],s16[5],s15[5],s14[5],s13[5],s12[5],s11[5],s10[5],s9[5],s8[5],s7[5],s6[5],s5[5],s4[5],s3[5],s2[5],s1[5],s0[5],select,c[5]),
m6 (s31[6],s30[6],s29[6],s28[6],s27[6],s26[6],s25[6],s24[6],s23[6],s22[6],s21[6],s20[6],s19[6],s18[6],s17[6],s16[6],s15[6],s14[6],s13[6],s12[6],s11[6],s10[6],s9[6],s8[6],s7[6],s6[6],s5[6],s4[6],s3[6],s2[6],s1[6],s0[6],select,c[6]),
m7 (s31[7],s30[7],s29[7],s28[7],s27[7],s26[7],s25[7],s24[7],s23[7],s22[7],s21[7],s20[7],s19[7],s18[7],s17[7],s16[7],s15[7],s14[7],s13[7],s12[7],s11[7],s10[7],s9[7],s8[7],s7[7],s6[7],s5[7],s4[7],s3[7],s2[7],s1[7],s0[7],select,c[7]),
m8 (s31[8],s30[8],s29[8],s28[8],s27[8],s26[8],s25[8],s24[8],s23[8],s22[8],s21[8],s20[8],s19[8],s18[8],s17[8],s16[8],s15[8],s14[8],s13[8],s12[8],s11[8],s10[8],s9[8],s8[8],s7[8],s6[8],s5[8],s4[8],s3[8],s2[8],s1[8],s0[8],select,c[8]),
m9 (s31[9],s30[9],s29[9],s28[9],s27[9],s26[9],s25[9],s24[9],s23[9],s22[9],s21[9],s20[9],s19[9],s18[9],s17[9],s16[9],s15[9],s14[9],s13[9],s12[9],s11[9],s10[9],s9[9],s8[9],s7[9],s6[9],s5[9],s4[9],s3[9],s2[9],s1[9],s0[9],select,c[9]),
m10 (s31[10],s30[10],s29[10],s28[10],s27[10],s26[10],s25[10],s24[10],s23[10],s22[10],s21[10],s20[10],s19[10],s18[10],s17[10],s16[10],s15[10],s14[10],s13[10],s12[10],s11[10],s10[10],s9[10],s8[10],s7[10],s6[10],s5[10],s4[10],s3[10],s2[10],s1[10],s0[10],select,c[10]),
m11 (s31[11],s30[11],s29[11],s28[11],s27[11],s26[11],s25[11],s24[11],s23[11],s22[11],s21[11],s20[11],s19[11],s18[11],s17[11],s16[11],s15[11],s14[11],s13[11],s12[11],s11[11],s10[11],s9[11],s8[11],s7[11],s6[11],s5[11],s4[11],s3[11],s2[11],s1[11],s0[11],select,c[11]),
m12 (s31[12],s30[12],s29[12],s28[12],s27[12],s26[12],s25[12],s24[12],s23[12],s22[12],s21[12],s20[12],s19[12],s18[12],s17[12],s16[12],s15[12],s14[12],s13[12],s12[12],s11[12],s10[12],s9[12],s8[12],s7[12],s6[12],s5[12],s4[12],s3[12],s2[12],s1[12],s0[12],select,c[12]),
m13 (s31[13],s30[13],s29[13],s28[13],s27[13],s26[13],s25[13],s24[13],s23[13],s22[13],s21[13],s20[13],s19[13],s18[13],s17[13],s16[13],s15[13],s14[13],s13[13],s12[13],s11[13],s10[13],s9[13],s8[13],s7[13],s6[13],s5[13],s4[13],s3[13],s2[13],s1[13],s0[13],select,c[13]),
m14 (s31[14],s30[14],s29[14],s28[14],s27[14],s26[14],s25[14],s24[14],s23[14],s22[14],s21[14],s20[14],s19[14],s18[14],s17[14],s16[14],s15[14],s14[14],s13[14],s12[14],s11[14],s10[14],s9[14],s8[14],s7[14],s6[14],s5[14],s4[14],s3[14],s2[14],s1[14],s0[14],select,c[14]),
m15 (s31[15],s30[15],s29[15],s28[15],s27[15],s26[15],s25[15],s24[15],s23[15],s22[15],s21[15],s20[15],s19[15],s18[15],s17[15],s16[15],s15[15],s14[15],s13[15],s12[15],s11[15],s10[15],s9[15],s8[15],s7[15],s6[15],s5[15],s4[15],s3[15],s2[15],s1[15],s0[15],select,c[15]),
m16 (s31[16],s30[16],s29[16],s28[16],s27[16],s26[16],s25[16],s24[16],s23[16],s22[16],s21[16],s20[16],s19[16],s18[16],s17[16],s16[16],s15[16],s14[16],s13[16],s12[16],s11[16],s10[16],s9[16],s8[16],s7[16],s6[16],s5[16],s4[16],s3[16],s2[16],s1[16],s0[16],select,c[16]),
m17 (s31[17],s30[17],s29[17],s28[17],s27[17],s26[17],s25[17],s24[17],s23[17],s22[17],s21[17],s20[17],s19[17],s18[17],s17[17],s16[17],s15[17],s14[17],s13[17],s12[17],s11[17],s10[17],s9[17],s8[17],s7[17],s6[17],s5[17],s4[17],s3[17],s2[17],s1[17],s0[17],select,c[17]),
m18 (s31[18],s30[18],s29[18],s28[18],s27[18],s26[18],s25[18],s24[18],s23[18],s22[18],s21[18],s20[18],s19[18],s18[18],s17[18],s16[18],s15[18],s14[18],s13[18],s12[18],s11[18],s10[18],s9[18],s8[18],s7[18],s6[18],s5[18],s4[18],s3[18],s2[18],s1[18],s0[18],select,c[18]),
m19 (s31[19],s30[19],s29[19],s28[19],s27[19],s26[19],s25[19],s24[19],s23[19],s22[19],s21[19],s20[19],s19[19],s18[19],s17[19],s16[19],s15[19],s14[19],s13[19],s12[19],s11[19],s10[19],s9[19],s8[19],s7[19],s6[19],s5[19],s4[19],s3[19],s2[19],s1[19],s0[19],select,c[19]),
m20 (s31[20],s30[20],s29[20],s28[20],s27[20],s26[20],s25[20],s24[20],s23[20],s22[20],s21[20],s20[20],s19[20],s18[20],s17[20],s16[20],s15[20],s14[20],s13[20],s12[20],s11[20],s10[20],s9[20],s8[20],s7[20],s6[20],s5[20],s4[20],s3[20],s2[20],s1[20],s0[20],select,c[20]),
m21 (s31[21],s30[21],s29[21],s28[21],s27[21],s26[21],s25[21],s24[21],s23[21],s22[21],s21[21],s20[21],s19[21],s18[21],s17[21],s16[21],s15[21],s14[21],s13[21],s12[21],s11[21],s10[21],s9[21],s8[21],s7[21],s6[21],s5[21],s4[21],s3[21],s2[21],s1[21],s0[21],select,c[21]),
m22 (s31[22],s30[22],s29[22],s28[22],s27[22],s26[22],s25[22],s24[22],s23[22],s22[22],s21[22],s20[22],s19[22],s18[22],s17[22],s16[22],s15[22],s14[22],s13[22],s12[22],s11[22],s10[22],s9[22],s8[22],s7[22],s6[22],s5[22],s4[22],s3[22],s2[22],s1[22],s0[22],select,c[22]),
m23 (s31[23],s30[23],s29[23],s28[23],s27[23],s26[23],s25[23],s24[23],s23[23],s22[23],s21[23],s20[23],s19[23],s18[23],s17[23],s16[23],s15[23],s14[23],s13[23],s12[23],s11[23],s10[23],s9[23],s8[23],s7[23],s6[23],s5[23],s4[23],s3[23],s2[23],s1[23],s0[23],select,c[23]),
m24 (s31[24],s30[24],s29[24],s28[24],s27[24],s26[24],s25[24],s24[24],s23[24],s22[24],s21[24],s20[24],s19[24],s18[24],s17[24],s16[24],s15[24],s14[24],s13[24],s12[24],s11[24],s10[24],s9[24],s8[24],s7[24],s6[24],s5[24],s4[24],s3[24],s2[24],s1[24],s0[24],select,c[24]),
m25 (s31[25],s30[25],s29[25],s28[25],s27[25],s26[25],s25[25],s24[25],s23[25],s22[25],s21[25],s20[25],s19[25],s18[25],s17[25],s16[25],s15[25],s14[25],s13[25],s12[25],s11[25],s10[25],s9[25],s8[25],s7[25],s6[25],s5[25],s4[25],s3[25],s2[25],s1[25],s0[25],select,c[25]),
m26 (s31[26],s30[26],s29[26],s28[26],s27[26],s26[26],s25[26],s24[26],s23[26],s22[26],s21[26],s20[26],s19[26],s18[26],s17[26],s16[26],s15[26],s14[26],s13[26],s12[26],s11[26],s10[26],s9[26],s8[26],s7[26],s6[26],s5[26],s4[26],s3[26],s2[26],s1[26],s0[26],select,c[26]),
m27 (s31[27],s30[27],s29[27],s28[27],s27[27],s26[27],s25[27],s24[27],s23[27],s22[27],s21[27],s20[27],s19[27],s18[27],s17[27],s16[27],s15[27],s14[27],s13[27],s12[27],s11[27],s10[27],s9[27],s8[27],s7[27],s6[27],s5[27],s4[27],s3[27],s2[27],s1[27],s0[27],select,c[27]),
m28 (s31[28],s30[28],s29[28],s28[28],s27[28],s26[28],s25[28],s24[28],s23[28],s22[28],s21[28],s20[28],s19[28],s18[28],s17[28],s16[28],s15[28],s14[28],s13[28],s12[28],s11[28],s10[28],s9[28],s8[28],s7[28],s6[28],s5[28],s4[28],s3[28],s2[28],s1[28],s0[28],select,c[28]),
m29 (s31[29],s30[29],s29[29],s28[29],s27[29],s26[29],s25[29],s24[29],s23[29],s22[29],s21[29],s20[29],s19[29],s18[29],s17[29],s16[29],s15[29],s14[29],s13[29],s12[29],s11[29],s10[29],s9[29],s8[29],s7[29],s6[29],s5[29],s4[29],s3[29],s2[29],s1[29],s0[29],select,c[29]),
m30 (s31[30],s30[30],s29[30],s28[30],s27[30],s26[30],s25[30],s24[30],s23[30],s22[30],s21[30],s20[30],s19[30],s18[30],s17[30],s16[30],s15[30],s14[30],s13[30],s12[30],s11[30],s10[30],s9[30],s8[30],s7[30],s6[30],s5[30],s4[30],s3[30],s2[30],s1[30],s0[30],select,c[30]),
m31 (s31[31],s30[31],s29[31],s28[31],s27[31],s26[31],s25[31],s24[31],s23[31],s22[31],s21[31],s20[31],s19[31],s18[31],s17[31],s16[31],s15[31],s14[31],s13[31],s12[31],s11[31],s10[31],s9[31],s8[31],s7[31],s6[31],s5[31],s4[31],s3[31],s2[31],s1[31],s0[31],select,c[31]),
m32 (co[31],co[30],co[29],co[28],co[27],co[26],co[25],co[24],co[23],co[22],co[21],co[20],co[19],co[18],co[17],co[16],co[15],co[14],co[13],co[12],co[11],co[10],co[9],co[8],co[7],co[6],co[5],co[4],co[3],co[2],co[1],co[0],select,cout),
m33 (ov[31],ov[30],ov[29],ov[28],ov[27],ov[26],ov[25],ov[24],ov[23],ov[22],ov[21],ov[20],ov[19],ov[18],ov[17],ov[16],ov[15],ov[14],ov[13],ov[12],ov[11],ov[10],ov[9],ov[8],ov[7],ov[6],ov[5],ov[4],ov[3],ov[2],ov[1],ov[0],select,ovfl);
endmodule | module ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl); |
wire [31:0]s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,co,ov;
assign co[7]=co[8];
assign ov[7]=ov[8];
RCA_32bit f0 (a,b,1'b0,s0,co[0],ov[0]),
f1 (a,b,1'b1,s3,co[3],ov[3]);
CSA_32bit f2 (a,b,1'b0,s1,co[1],ov[1]),
f3 (a,b,1'b1,s4,co[4],ov[4]);
CLA_32bit f4 (a,b,1'b0,s2,co[2],ov[2]),
f5 (a,b,1'b1,s5,co[5],ov[5]);
multiplier_8x8 f6 (a[7:0],b[7:0],s6,co[6],ov[6]);
EN_not f7 (a,1'b1,s7);
And_32bit f8 (a,b,s8,co[8],ov[8]);
Or_32bit f9 (a,b,s9,co[9],ov[9]);
Xor_32bit f10 (a,b,s10,co[10],ov[10]);
ShiftRLogical1 f11 (a,s11,co[11],ov[11]);
ShiftRLogical2 f12 (a,s12,co[12],ov[12]);
ShiftRLogical4 f13 (a,s13,co[13],ov[13]);
ShiftRLogical8 f14 (a,s14,co[14],ov[14]);
ShiftRLogical16 f15 (a,s15,co[15],ov[15]);
ShiftRArithmetic1 f16 (a,s16,co[16],ov[16]);
ShiftRArithmetic2 f17 (a,s17,co[17],ov[17]);
ShiftRArithmetic4 f18 (a,s18,co[18],ov[18]);
ShiftRArithmetic8 f19(a,s19,co[19],ov[19]);
ShiftRArithmetic16 f20 (a,s20,co[20],ov[20]);
ShiftLLogical1 f21 (a,s21,co[21],ov[21]);
ShiftLLogical2 f22 (a,s22,co[22],ov[22]);
ShiftLLogical4 f23 (a,s23,co[23],ov[23]);
ShiftLLogical8 f24 (a,s24,co[24],ov[24]);
ShiftLLogical16 f25 (a,s25,co[25],ov[25]);
ShiftLArithmetic1 f26 (a,s26,co[26],ov[26]);
ShiftLArithmetic2 f27 (a,s27,co[27],ov[27]);
ShiftLArithmetic4 f28 (a,s28,co[28],ov[28]);
ShiftLArithmetic8 f29 (a,s29,co[29],ov[29]);
ShiftLArithmetic16 f30 (a,s30,co[30],ov[30]);
mux_32x1 m0 (s31[0],s30[0],s29[0],s28[0],s27[0],s26[0],s25[0],s24[0],s23[0],s22[0],s21[0],s20[0],s19[0],s18[0],s17[0],s16[0],s15[0],s14[0],s13[0],s12[0],s11[0],s10[0],s9[0],s8[0],s7[0],s6[0],s5[0],s4[0],s3[0],s2[0],s1[0],s0[0],select,c[0]),
m1 (s31[1],s30[1],s29[1],s28[1],s27[1],s26[1],s25[1],s24[1],s23[1],s22[1],s21[1],s20[1],s19[1],s18[1],s17[1],s16[1],s15[1],s14[1],s13[1],s12[1],s11[1],s10[1],s9[1],s8[1],s7[1],s6[1],s5[1],s4[1],s3[1],s2[1],s1[1],s0[1],select,c[1]),
m2 (s31[2],s30[2],s29[2],s28[2],s27[2],s26[2],s25[2],s24[2],s23[2],s22[2],s21[2],s20[2],s19[2],s18[2],s17[2],s16[2],s15[2],s14[2],s13[2],s12[2],s11[2],s10[2],s9[2],s8[2],s7[2],s6[2],s5[2],s4[2],s3[2],s2[2],s1[2],s0[2],select,c[2]),
m3 (s31[3],s30[3],s29[3],s28[3],s27[3],s26[3],s25[3],s24[3],s23[3],s22[3],s21[3],s20[3],s19[3],s18[3],s17[3],s16[3],s15[3],s14[3],s13[3],s12[3],s11[3],s10[3],s9[3],s8[3],s7[3],s6[3],s5[3],s4[3],s3[3],s2[3],s1[3],s0[3],select,c[3]),
m4 (s31[4],s30[4],s29[4],s28[4],s27[4],s26[4],s25[4],s24[4],s23[4],s22[4],s21[4],s20[4],s19[4],s18[4],s17[4],s16[4],s15[4],s14[4],s13[4],s12[4],s11[4],s10[4],s9[4],s8[4],s7[4],s6[4],s5[4],s4[4],s3[4],s2[4],s1[4],s0[4],select,c[4]),
m5 (s31[5],s30[5],s29[5],s28[5],s27[5],s26[5],s25[5],s24[5],s23[5],s22[5],s21[5],s20[5],s19[5],s18[5],s17[5],s16[5],s15[5],s14[5],s13[5],s12[5],s11[5],s10[5],s9[5],s8[5],s7[5],s6[5],s5[5],s4[5],s3[5],s2[5],s1[5],s0[5],select,c[5]),
m6 (s31[6],s30[6],s29[6],s28[6],s27[6],s26[6],s25[6],s24[6],s23[6],s22[6],s21[6],s20[6],s19[6],s18[6],s17[6],s16[6],s15[6],s14[6],s13[6],s12[6],s11[6],s10[6],s9[6],s8[6],s7[6],s6[6],s5[6],s4[6],s3[6],s2[6],s1[6],s0[6],select,c[6]),
m7 (s31[7],s30[7],s29[7],s28[7],s27[7],s26[7],s25[7],s24[7],s23[7],s22[7],s21[7],s20[7],s19[7],s18[7],s17[7],s16[7],s15[7],s14[7],s13[7],s12[7],s11[7],s10[7],s9[7],s8[7],s7[7],s6[7],s5[7],s4[7],s3[7],s2[7],s1[7],s0[7],select,c[7]),
m8 (s31[8],s30[8],s29[8],s28[8],s27[8],s26[8],s25[8],s24[8],s23[8],s22[8],s21[8],s20[8],s19[8],s18[8],s17[8],s16[8],s15[8],s14[8],s13[8],s12[8],s11[8],s10[8],s9[8],s8[8],s7[8],s6[8],s5[8],s4[8],s3[8],s2[8],s1[8],s0[8],select,c[8]),
m9 (s31[9],s30[9],s29[9],s28[9],s27[9],s26[9],s25[9],s24[9],s23[9],s22[9],s21[9],s20[9],s19[9],s18[9],s17[9],s16[9],s15[9],s14[9],s13[9],s12[9],s11[9],s10[9],s9[9],s8[9],s7[9],s6[9],s5[9],s4[9],s3[9],s2[9],s1[9],s0[9],select,c[9]),
m10 (s31[10],s30[10],s29[10],s28[10],s27[10],s26[10],s25[10],s24[10],s23[10],s22[10],s21[10],s20[10],s19[10],s18[10],s17[10],s16[10],s15[10],s14[10],s13[10],s12[10],s11[10],s10[10],s9[10],s8[10],s7[10],s6[10],s5[10],s4[10],s3[10],s2[10],s1[10],s0[10],select,c[10]),
m11 (s31[11],s30[11],s29[11],s28[11],s27[11],s26[11],s25[11],s24[11],s23[11],s22[11],s21[11],s20[11],s19[11],s18[11],s17[11],s16[11],s15[11],s14[11],s13[11],s12[11],s11[11],s10[11],s9[11],s8[11],s7[11],s6[11],s5[11],s4[11],s3[11],s2[11],s1[11],s0[11],select,c[11]),
m12 (s31[12],s30[12],s29[12],s28[12],s27[12],s26[12],s25[12],s24[12],s23[12],s22[12],s21[12],s20[12],s19[12],s18[12],s17[12],s16[12],s15[12],s14[12],s13[12],s12[12],s11[12],s10[12],s9[12],s8[12],s7[12],s6[12],s5[12],s4[12],s3[12],s2[12],s1[12],s0[12],select,c[12]),
m13 (s31[13],s30[13],s29[13],s28[13],s27[13],s26[13],s25[13],s24[13],s23[13],s22[13],s21[13],s20[13],s19[13],s18[13],s17[13],s16[13],s15[13],s14[13],s13[13],s12[13],s11[13],s10[13],s9[13],s8[13],s7[13],s6[13],s5[13],s4[13],s3[13],s2[13],s1[13],s0[13],select,c[13]),
m14 (s31[14],s30[14],s29[14],s28[14],s27[14],s26[14],s25[14],s24[14],s23[14],s22[14],s21[14],s20[14],s19[14],s18[14],s17[14],s16[14],s15[14],s14[14],s13[14],s12[14],s11[14],s10[14],s9[14],s8[14],s7[14],s6[14],s5[14],s4[14],s3[14],s2[14],s1[14],s0[14],select,c[14]),
m15 (s31[15],s30[15],s29[15],s28[15],s27[15],s26[15],s25[15],s24[15],s23[15],s22[15],s21[15],s20[15],s19[15],s18[15],s17[15],s16[15],s15[15],s14[15],s13[15],s12[15],s11[15],s10[15],s9[15],s8[15],s7[15],s6[15],s5[15],s4[15],s3[15],s2[15],s1[15],s0[15],select,c[15]),
m16 (s31[16],s30[16],s29[16],s28[16],s27[16],s26[16],s25[16],s24[16],s23[16],s22[16],s21[16],s20[16],s19[16],s18[16],s17[16],s16[16],s15[16],s14[16],s13[16],s12[16],s11[16],s10[16],s9[16],s8[16],s7[16],s6[16],s5[16],s4[16],s3[16],s2[16],s1[16],s0[16],select,c[16]),
m17 (s31[17],s30[17],s29[17],s28[17],s27[17],s26[17],s25[17],s24[17],s23[17],s22[17],s21[17],s20[17],s19[17],s18[17],s17[17],s16[17],s15[17],s14[17],s13[17],s12[17],s11[17],s10[17],s9[17],s8[17],s7[17],s6[17],s5[17],s4[17],s3[17],s2[17],s1[17],s0[17],select,c[17]),
m18 (s31[18],s30[18],s29[18],s28[18],s27[18],s26[18],s25[18],s24[18],s23[18],s22[18],s21[18],s20[18],s19[18],s18[18],s17[18],s16[18],s15[18],s14[18],s13[18],s12[18],s11[18],s10[18],s9[18],s8[18],s7[18],s6[18],s5[18],s4[18],s3[18],s2[18],s1[18],s0[18],select,c[18]),
m19 (s31[19],s30[19],s29[19],s28[19],s27[19],s26[19],s25[19],s24[19],s23[19],s22[19],s21[19],s20[19],s19[19],s18[19],s17[19],s16[19],s15[19],s14[19],s13[19],s12[19],s11[19],s10[19],s9[19],s8[19],s7[19],s6[19],s5[19],s4[19],s3[19],s2[19],s1[19],s0[19],select,c[19]),
m20 (s31[20],s30[20],s29[20],s28[20],s27[20],s26[20],s25[20],s24[20],s23[20],s22[20],s21[20],s20[20],s19[20],s18[20],s17[20],s16[20],s15[20],s14[20],s13[20],s12[20],s11[20],s10[20],s9[20],s8[20],s7[20],s6[20],s5[20],s4[20],s3[20],s2[20],s1[20],s0[20],select,c[20]),
m21 (s31[21],s30[21],s29[21],s28[21],s27[21],s26[21],s25[21],s24[21],s23[21],s22[21],s21[21],s20[21],s19[21],s18[21],s17[21],s16[21],s15[21],s14[21],s13[21],s12[21],s11[21],s10[21],s9[21],s8[21],s7[21],s6[21],s5[21],s4[21],s3[21],s2[21],s1[21],s0[21],select,c[21]),
m22 (s31[22],s30[22],s29[22],s28[22],s27[22],s26[22],s25[22],s24[22],s23[22],s22[22],s21[22],s20[22],s19[22],s18[22],s17[22],s16[22],s15[22],s14[22],s13[22],s12[22],s11[22],s10[22],s9[22],s8[22],s7[22],s6[22],s5[22],s4[22],s3[22],s2[22],s1[22],s0[22],select,c[22]),
m23 (s31[23],s30[23],s29[23],s28[23],s27[23],s26[23],s25[23],s24[23],s23[23],s22[23],s21[23],s20[23],s19[23],s18[23],s17[23],s16[23],s15[23],s14[23],s13[23],s12[23],s11[23],s10[23],s9[23],s8[23],s7[23],s6[23],s5[23],s4[23],s3[23],s2[23],s1[23],s0[23],select,c[23]),
m24 (s31[24],s30[24],s29[24],s28[24],s27[24],s26[24],s25[24],s24[24],s23[24],s22[24],s21[24],s20[24],s19[24],s18[24],s17[24],s16[24],s15[24],s14[24],s13[24],s12[24],s11[24],s10[24],s9[24],s8[24],s7[24],s6[24],s5[24],s4[24],s3[24],s2[24],s1[24],s0[24],select,c[24]),
m25 (s31[25],s30[25],s29[25],s28[25],s27[25],s26[25],s25[25],s24[25],s23[25],s22[25],s21[25],s20[25],s19[25],s18[25],s17[25],s16[25],s15[25],s14[25],s13[25],s12[25],s11[25],s10[25],s9[25],s8[25],s7[25],s6[25],s5[25],s4[25],s3[25],s2[25],s1[25],s0[25],select,c[25]),
m26 (s31[26],s30[26],s29[26],s28[26],s27[26],s26[26],s25[26],s24[26],s23[26],s22[26],s21[26],s20[26],s19[26],s18[26],s17[26],s16[26],s15[26],s14[26],s13[26],s12[26],s11[26],s10[26],s9[26],s8[26],s7[26],s6[26],s5[26],s4[26],s3[26],s2[26],s1[26],s0[26],select,c[26]),
m27 (s31[27],s30[27],s29[27],s28[27],s27[27],s26[27],s25[27],s24[27],s23[27],s22[27],s21[27],s20[27],s19[27],s18[27],s17[27],s16[27],s15[27],s14[27],s13[27],s12[27],s11[27],s10[27],s9[27],s8[27],s7[27],s6[27],s5[27],s4[27],s3[27],s2[27],s1[27],s0[27],select,c[27]),
m28 (s31[28],s30[28],s29[28],s28[28],s27[28],s26[28],s25[28],s24[28],s23[28],s22[28],s21[28],s20[28],s19[28],s18[28],s17[28],s16[28],s15[28],s14[28],s13[28],s12[28],s11[28],s10[28],s9[28],s8[28],s7[28],s6[28],s5[28],s4[28],s3[28],s2[28],s1[28],s0[28],select,c[28]),
m29 (s31[29],s30[29],s29[29],s28[29],s27[29],s26[29],s25[29],s24[29],s23[29],s22[29],s21[29],s20[29],s19[29],s18[29],s17[29],s16[29],s15[29],s14[29],s13[29],s12[29],s11[29],s10[29],s9[29],s8[29],s7[29],s6[29],s5[29],s4[29],s3[29],s2[29],s1[29],s0[29],select,c[29]),
m30 (s31[30],s30[30],s29[30],s28[30],s27[30],s26[30],s25[30],s24[30],s23[30],s22[30],s21[30],s20[30],s19[30],s18[30],s17[30],s16[30],s15[30],s14[30],s13[30],s12[30],s11[30],s10[30],s9[30],s8[30],s7[30],s6[30],s5[30],s4[30],s3[30],s2[30],s1[30],s0[30],select,c[30]),
m31 (s31[31],s30[31],s29[31],s28[31],s27[31],s26[31],s25[31],s24[31],s23[31],s22[31],s21[31],s20[31],s19[31],s18[31],s17[31],s16[31],s15[31],s14[31],s13[31],s12[31],s11[31],s10[31],s9[31],s8[31],s7[31],s6[31],s5[31],s4[31],s3[31],s2[31],s1[31],s0[31],select,c[31]),
m32 (co[31],co[30],co[29],co[28],co[27],co[26],co[25],co[24],co[23],co[22],co[21],co[20],co[19],co[18],co[17],co[16],co[15],co[14],co[13],co[12],co[11],co[10],co[9],co[8],co[7],co[6],co[5],co[4],co[3],co[2],co[1],co[0],select,cout),
m33 (ov[31],ov[30],ov[29],ov[28],ov[27],ov[26],ov[25],ov[24],ov[23],ov[22],ov[21],ov[20],ov[19],ov[18],ov[17],ov[16],ov[15],ov[14],ov[13],ov[12],ov[11],ov[10],ov[9],ov[8],ov[7],ov[6],ov[5],ov[4],ov[3],ov[2],ov[1],ov[0],select,ovfl);
endmodule | 1 |
5,100 | data/full_repos/permissive/113036182/DataMemory.v | 113,036,182 | DataMemory.v | v | 109 | 130 | [] | [] | [] | null | line:4 column:14: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/113036182/DataMemory.v:71: Cannot find file containing module: 'CSA_32bit'\nCSA_32bit f1 (Address1,32'b00000000000000000000000000000001,1'b0,address11,co,ov),\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.sv\n CSA_32bit\n CSA_32bit.v\n CSA_32bit.sv\n obj_dir/CSA_32bit\n obj_dir/CSA_32bit.v\n obj_dir/CSA_32bit.sv\n%Error: data/full_repos/permissive/113036182/DataMemory.v:102: Cannot find file containing module: 'mux_2x32'\nmux_2x32 m1 (WriteData2,rData1,select,WrData2),\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,548 | module | module DataMem (input [31:0]Address1,Address2,WriteData1,WriteData2,input MemRead,MemWrite,inout [31:0]Data1,Data2);
reg [7:0] mem [0:63];
initial begin
mem[0]=8'b 00000000;
mem[1]=8'b 00000001;
mem[2]=8'b 00000010;
mem[3]=8'b 00000011;
mem[4]=8'b 00000000;
mem[5]=8'b 00000000;
mem[6]=8'b 00000000;
mem[7]=8'b 00000100;
mem[8]=8'b 00000000;
mem[9]=8'b 00000000;
mem[10]=8'b 00000000;
mem[11]=8'b 00001100;
mem[12]=8'b 00001100;
mem[13]=8'b 00001101;
mem[14]=8'b 00001110;
mem[15]=8'b 00001111;
mem[16]=8'b 00010000;
mem[17]=8'b 00010001;
mem[18]=8'b 00010010;
mem[19]=8'b 00010011;
mem[20]=8'b 00010100;
mem[21]=8'b 00010101;
mem[22]=8'b 00010110;
mem[23]=8'b 00010111;
mem[24]=8'b 00100000;
mem[25]=8'b 00100001;
mem[26]=8'b 00100010;
mem[27]=8'b 00100011;
mem[28]=8'b 00100100;
mem[29]=8'b 00100101;
mem[30]=8'b 00100110;
mem[31]=8'b 00100111;
mem[32]=8'b 00101000;
mem[33]=8'b 00101001;
mem[34]=8'b 00101010;
mem[35]=8'b 00101011;
mem[36]=8'b 00101100;
mem[37]=8'b 00000101;
mem[38]=8'b 00000110;
mem[39]=8'b 00000111;
mem[40]=8'b 00000000;
mem[41]=8'b 00000001;
mem[42]=8'b 00000010;
mem[43]=8'b 00000011;
mem[44]=8'b 00000100;
mem[45]=8'b 00000101;
mem[46]=8'b 00000110;
mem[47]=8'b 00000111;
mem[48]=8'b 00000000;
mem[49]=8'b 00000001;
mem[50]=8'b 00000010;
mem[51]=8'b 00000011;
mem[52]=8'b 00000100;
mem[53]=8'b 00000101;
mem[54]=8'b 00000110;
mem[55]=8'b 00000111;
mem[56]=8'b 00000000;
mem[57]=8'b 00000001;
mem[58]=8'b 00000010;
mem[59]=8'b 00000011;
mem[60]=8'b 00000100;
mem[61]=8'b 00000101;
mem[62]=8'b 00000110;
mem[63]=8'b 00000111;
end
wire [31:0]address11,address12,address13,address21,address22,address23;
wire co,ov;
CSA_32bit f1 (Address1,32'b00000000000000000000000000000001,1'b0,address11,co,ov),
f2 (Address1,32'b00000000000000000000000000000010,1'b0,address12,co,ov),
f3 (Address1,32'b00000000000000000000000000000011,1'b0,address13,co,ov),
f4 (Address2,32'b00000000000000000000000000000001,1'b0,address21,co,ov),
f5 (Address2,32'b00000000000000000000000000000010,1'b0,address22,co,ov),
f6 (Address2,32'b00000000000000000000000000000011,1'b0,address23,co,ov);
assign Data1[31:24]=MemRead ? mem[Address1]:8'b zzzzzzzz;
assign Data1[23:16]=MemRead ? mem[address11]:8'b zzzzzzzz;
assign Data1[15:8]=MemRead ? mem[address12]:8'b zzzzzzzz;
assign Data1[7:0]=MemRead ? mem[address13]:8'b zzzzzzzz;
assign Data2[31:24]=MemRead ? mem[Address2]:8'b zzzzzzzz;
assign Data2[23:16]=MemRead ? mem[address21]:8'b zzzzzzzz;
assign Data2[15:8]=MemRead ? mem[address22]:8'b zzzzzzzz;
assign Data2[7:0]=MemRead ? mem[address23]:8'b zzzzzzzz;
always @ (MemWrite,WriteData1,WriteData2) begin
if (MemWrite) begin
mem[Address1]=WriteData1[31:24];
mem[address11]=WriteData1[23:16];
mem[address12]=WriteData1[15:8];
mem[address13]=WriteData1[7:0];
mem[Address2]=WriteData2[31:24];
mem[address21]=WriteData2[23:16];
mem[address22]=WriteData2[15:8];
mem[address23]=WriteData2[7:0];
end
end
endmodule | module DataMem (input [31:0]Address1,Address2,WriteData1,WriteData2,input MemRead,MemWrite,inout [31:0]Data1,Data2); |
reg [7:0] mem [0:63];
initial begin
mem[0]=8'b 00000000;
mem[1]=8'b 00000001;
mem[2]=8'b 00000010;
mem[3]=8'b 00000011;
mem[4]=8'b 00000000;
mem[5]=8'b 00000000;
mem[6]=8'b 00000000;
mem[7]=8'b 00000100;
mem[8]=8'b 00000000;
mem[9]=8'b 00000000;
mem[10]=8'b 00000000;
mem[11]=8'b 00001100;
mem[12]=8'b 00001100;
mem[13]=8'b 00001101;
mem[14]=8'b 00001110;
mem[15]=8'b 00001111;
mem[16]=8'b 00010000;
mem[17]=8'b 00010001;
mem[18]=8'b 00010010;
mem[19]=8'b 00010011;
mem[20]=8'b 00010100;
mem[21]=8'b 00010101;
mem[22]=8'b 00010110;
mem[23]=8'b 00010111;
mem[24]=8'b 00100000;
mem[25]=8'b 00100001;
mem[26]=8'b 00100010;
mem[27]=8'b 00100011;
mem[28]=8'b 00100100;
mem[29]=8'b 00100101;
mem[30]=8'b 00100110;
mem[31]=8'b 00100111;
mem[32]=8'b 00101000;
mem[33]=8'b 00101001;
mem[34]=8'b 00101010;
mem[35]=8'b 00101011;
mem[36]=8'b 00101100;
mem[37]=8'b 00000101;
mem[38]=8'b 00000110;
mem[39]=8'b 00000111;
mem[40]=8'b 00000000;
mem[41]=8'b 00000001;
mem[42]=8'b 00000010;
mem[43]=8'b 00000011;
mem[44]=8'b 00000100;
mem[45]=8'b 00000101;
mem[46]=8'b 00000110;
mem[47]=8'b 00000111;
mem[48]=8'b 00000000;
mem[49]=8'b 00000001;
mem[50]=8'b 00000010;
mem[51]=8'b 00000011;
mem[52]=8'b 00000100;
mem[53]=8'b 00000101;
mem[54]=8'b 00000110;
mem[55]=8'b 00000111;
mem[56]=8'b 00000000;
mem[57]=8'b 00000001;
mem[58]=8'b 00000010;
mem[59]=8'b 00000011;
mem[60]=8'b 00000100;
mem[61]=8'b 00000101;
mem[62]=8'b 00000110;
mem[63]=8'b 00000111;
end
wire [31:0]address11,address12,address13,address21,address22,address23;
wire co,ov;
CSA_32bit f1 (Address1,32'b00000000000000000000000000000001,1'b0,address11,co,ov),
f2 (Address1,32'b00000000000000000000000000000010,1'b0,address12,co,ov),
f3 (Address1,32'b00000000000000000000000000000011,1'b0,address13,co,ov),
f4 (Address2,32'b00000000000000000000000000000001,1'b0,address21,co,ov),
f5 (Address2,32'b00000000000000000000000000000010,1'b0,address22,co,ov),
f6 (Address2,32'b00000000000000000000000000000011,1'b0,address23,co,ov);
assign Data1[31:24]=MemRead ? mem[Address1]:8'b zzzzzzzz;
assign Data1[23:16]=MemRead ? mem[address11]:8'b zzzzzzzz;
assign Data1[15:8]=MemRead ? mem[address12]:8'b zzzzzzzz;
assign Data1[7:0]=MemRead ? mem[address13]:8'b zzzzzzzz;
assign Data2[31:24]=MemRead ? mem[Address2]:8'b zzzzzzzz;
assign Data2[23:16]=MemRead ? mem[address21]:8'b zzzzzzzz;
assign Data2[15:8]=MemRead ? mem[address22]:8'b zzzzzzzz;
assign Data2[7:0]=MemRead ? mem[address23]:8'b zzzzzzzz;
always @ (MemWrite,WriteData1,WriteData2) begin
if (MemWrite) begin
mem[Address1]=WriteData1[31:24];
mem[address11]=WriteData1[23:16];
mem[address12]=WriteData1[15:8];
mem[address13]=WriteData1[7:0];
mem[Address2]=WriteData2[31:24];
mem[address21]=WriteData2[23:16];
mem[address22]=WriteData2[15:8];
mem[address23]=WriteData2[7:0];
end
end
endmodule | 1 |
5,101 | data/full_repos/permissive/113036182/DataMemory.v | 113,036,182 | DataMemory.v | v | 109 | 130 | [] | [] | [] | null | line:4 column:14: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/113036182/DataMemory.v:71: Cannot find file containing module: 'CSA_32bit'\nCSA_32bit f1 (Address1,32'b00000000000000000000000000000001,1'b0,address11,co,ov),\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.sv\n CSA_32bit\n CSA_32bit.v\n CSA_32bit.sv\n obj_dir/CSA_32bit\n obj_dir/CSA_32bit.v\n obj_dir/CSA_32bit.sv\n%Error: data/full_repos/permissive/113036182/DataMemory.v:102: Cannot find file containing module: 'mux_2x32'\nmux_2x32 m1 (WriteData2,rData1,select,WrData2),\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,548 | module | module Project_test1 (input [31:0]Address1,Address2,WriteData1,WriteData2,input select,MemRead,MemWrite,inout [31:0]Data1,Data2);
reg [31:0] rData1,rData2;
wire [31:0] WrData1,WrData2;
mux_2x32 m1 (WriteData2,rData1,select,WrData2),
m2 (WriteData1,rData2,select,WrData1);
DataMem DM1 (Address1,Address2,WrData1,WrData2,MemRead,MemWrite,Data1,Data2);
always@( Address1,Address2 ) begin
rData1 <= Data1;
rData2 <= Data2;
end
endmodule | module Project_test1 (input [31:0]Address1,Address2,WriteData1,WriteData2,input select,MemRead,MemWrite,inout [31:0]Data1,Data2); |
reg [31:0] rData1,rData2;
wire [31:0] WrData1,WrData2;
mux_2x32 m1 (WriteData2,rData1,select,WrData2),
m2 (WriteData1,rData2,select,WrData1);
DataMem DM1 (Address1,Address2,WrData1,WrData2,MemRead,MemWrite,Data1,Data2);
always@( Address1,Address2 ) begin
rData1 <= Data1;
rData2 <= Data2;
end
endmodule | 1 |
5,102 | data/full_repos/permissive/113036182/InstrMemory.v | 113,036,182 | InstrMemory.v | v | 96 | 81 | [] | [] | [] | null | line:5 column:14: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/113036182/InstrMemory.v:87: Cannot find file containing module: 'CSA_32bit'\nCSA_32bit f1 (address,32'b00000000000000000000000000000001,1'b0,address1,co,ov),\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.sv\n CSA_32bit\n CSA_32bit.v\n CSA_32bit.sv\n obj_dir/CSA_32bit\n obj_dir/CSA_32bit.v\n obj_dir/CSA_32bit.sv\n%Error: Exiting due to 1 error(s)\n" | 5,549 | module | module InstrMem (input [31:0]address, output [31:0]data,output [5:0]lookahead);
reg [7:0] mem [0:63];
wire [7:0]w;
initial begin
mem[0]=8'b 00000000;
mem[1]=8'b 00100010;
mem[2]=8'b 00100000;
mem[3]=8'b 00000001;
mem[4]=8'b 00001100;
mem[5]=8'b 00000000;
mem[6]=8'b 00000000;
mem[7]=8'b 00000000;
mem[8]=8'b 00000000;
mem[9]=8'b 00100010;
mem[10]=8'b 00101000;
mem[11]=8'b 00000000;
mem[12]=8'b 00000000;
mem[13]=8'b 00100010;
mem[14]=8'b 00110000;
mem[15]=8'b 00000010;
mem[16]=8'b 00000000;
mem[17]=8'b 00100010;
mem[18]=8'b 00111000;
mem[19]=8'b 00000001;
mem[20]=8'b 00000000;
mem[21]=8'b 00100011;
mem[22]=8'b 01000000;
mem[23]=8'b 00000000;
mem[24]=8'b 00000000;
mem[25]=8'b 00100011;
mem[26]=8'b 01000000;
mem[27]=8'b 00000000;
mem[28]=8'b 00010000;
mem[29]=8'b 01100100;
mem[30]=8'b 01001000;
mem[31]=8'b 00000000;
mem[32]=8'b 00000000;
mem[33]=8'b 00000001;
mem[34]=8'b 00000010;
mem[35]=8'b 00000011;
mem[36]=8'b 00000000;
mem[37]=8'b 00000001;
mem[38]=8'b 00000010;
mem[39]=8'b 00000011;
mem[40]=8'b 00000000;
mem[41]=8'b 00000001;
mem[42]=8'b 00000010;
mem[43]=8'b 00000011;
mem[44]=8'b 00000000;
mem[45]=8'b 00000101;
mem[46]=8'b 00000110;
mem[47]=8'b 00000111;
mem[48]=8'b 00000000;
mem[49]=8'b 00000001;
mem[50]=8'b 00000010;
mem[51]=8'b 00000011;
mem[52]=8'b 00000100;
mem[53]=8'b 00000101;
mem[54]=8'b 00000110;
mem[55]=8'b 00000111;
mem[56]=8'b 00000000;
mem[57]=8'b 00000001;
mem[58]=8'b 00000010;
mem[59]=8'b 00000011;
mem[60]=8'b 00000100;
mem[61]=8'b 00000101;
mem[62]=8'b 00000110;
mem[63]=8'b 00000111;
end
wire [31:0]address1,address2,address3;
CSA_32bit f1 (address,32'b00000000000000000000000000000001,1'b0,address1,co,ov),
f2 (address,32'b00000000000000000000000000000010,1'b0,address2,co,ov),
f3 (address,32'b00000000000000000000000000000011,1'b0,address3,co,ov);
assign data[31:24]=mem[address];
assign data[23:16]=mem[address1];
assign data[15:8]=mem[address2];
assign data[7:0]=mem[address3];
assign w=mem[address+4];
assign lookahead=w[7:2];
endmodule | module InstrMem (input [31:0]address, output [31:0]data,output [5:0]lookahead); |
reg [7:0] mem [0:63];
wire [7:0]w;
initial begin
mem[0]=8'b 00000000;
mem[1]=8'b 00100010;
mem[2]=8'b 00100000;
mem[3]=8'b 00000001;
mem[4]=8'b 00001100;
mem[5]=8'b 00000000;
mem[6]=8'b 00000000;
mem[7]=8'b 00000000;
mem[8]=8'b 00000000;
mem[9]=8'b 00100010;
mem[10]=8'b 00101000;
mem[11]=8'b 00000000;
mem[12]=8'b 00000000;
mem[13]=8'b 00100010;
mem[14]=8'b 00110000;
mem[15]=8'b 00000010;
mem[16]=8'b 00000000;
mem[17]=8'b 00100010;
mem[18]=8'b 00111000;
mem[19]=8'b 00000001;
mem[20]=8'b 00000000;
mem[21]=8'b 00100011;
mem[22]=8'b 01000000;
mem[23]=8'b 00000000;
mem[24]=8'b 00000000;
mem[25]=8'b 00100011;
mem[26]=8'b 01000000;
mem[27]=8'b 00000000;
mem[28]=8'b 00010000;
mem[29]=8'b 01100100;
mem[30]=8'b 01001000;
mem[31]=8'b 00000000;
mem[32]=8'b 00000000;
mem[33]=8'b 00000001;
mem[34]=8'b 00000010;
mem[35]=8'b 00000011;
mem[36]=8'b 00000000;
mem[37]=8'b 00000001;
mem[38]=8'b 00000010;
mem[39]=8'b 00000011;
mem[40]=8'b 00000000;
mem[41]=8'b 00000001;
mem[42]=8'b 00000010;
mem[43]=8'b 00000011;
mem[44]=8'b 00000000;
mem[45]=8'b 00000101;
mem[46]=8'b 00000110;
mem[47]=8'b 00000111;
mem[48]=8'b 00000000;
mem[49]=8'b 00000001;
mem[50]=8'b 00000010;
mem[51]=8'b 00000011;
mem[52]=8'b 00000100;
mem[53]=8'b 00000101;
mem[54]=8'b 00000110;
mem[55]=8'b 00000111;
mem[56]=8'b 00000000;
mem[57]=8'b 00000001;
mem[58]=8'b 00000010;
mem[59]=8'b 00000011;
mem[60]=8'b 00000100;
mem[61]=8'b 00000101;
mem[62]=8'b 00000110;
mem[63]=8'b 00000111;
end
wire [31:0]address1,address2,address3;
CSA_32bit f1 (address,32'b00000000000000000000000000000001,1'b0,address1,co,ov),
f2 (address,32'b00000000000000000000000000000010,1'b0,address2,co,ov),
f3 (address,32'b00000000000000000000000000000011,1'b0,address3,co,ov);
assign data[31:24]=mem[address];
assign data[23:16]=mem[address1];
assign data[15:8]=mem[address2];
assign data[7:0]=mem[address3];
assign w=mem[address+4];
assign lookahead=w[7:2];
endmodule | 1 |
5,103 | data/full_repos/permissive/113036182/MIPS_Assembled.v | 113,036,182 | MIPS_Assembled.v | v | 127 | 179 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:21: Cannot find file containing module: 'mux_4x32'\n mux_4x32 Mux_PC (PC4IF,PCmux01,PCmux10EX,PCmux11,PCsrc,PCin);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32.sv\n mux_4x32\n mux_4x32.v\n mux_4x32.sv\n obj_dir/mux_4x32\n obj_dir/mux_4x32.v\n obj_dir/mux_4x32.sv\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:23: Cannot find file containing module: 'CSA_32bit'\n CSA_32bit IFCSA (PCout,32'b00000000000000000000000000000100,1'b0,PC4IF,co,ov);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:24: Cannot find file containing module: 'reg_32bit'\n reg_32bit R0 (PCin,1'b1,1'b1,clk,PCout);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:25: Cannot find file containing module: 'InstrMem'\n InstrMem IM0 (PCout,InstrIF,CtrlInstrIF);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:26: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit IF_ID_Instr (InstrIF,clk,InstrID),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:33: Cannot find file containing module: 'mux_4x5'\n mux_4x5 Mux_ReadRegister1 (InstrID[25:21],InstrWB[25:21],InstrWB[20:16],5'b00000,RdReg1sel,ReadAd1),\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:35: Cannot find file containing module: 'mux_2x5'\n mux_2x5 Mux_ReadRegister2 (InstrID[20:16],InstrWB[20:16],RdReg2sel,ReadAd2);\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:36: Cannot find file containing module: 'mux_4x32'\n mux_4x32 Mux_WriteData (AluResWB,PC4EX,ReadData1ID,32'b00000000000000000000000000000000,WrDataWB,WRdata0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:37: Cannot find file containing module: 'RegisterFile'\n RegisterFile RF0 (ReadAd1,ReadAd2,WRdst,WRdata0,RegWriteWB,ExrWriteWB1,clk,ReadData1ID,ReadData2ID,ReadData3ID);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:38: Cannot find file containing module: 'ShiftLLogical2'\n ShiftLLogical2 ShiftForJA (InstrID,JAID,co,ov);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:43: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit ID_EX_ReadData1 (ReadData1ID,clk,ReadData1EX),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:50: Cannot find file containing module: 'CSA_32bit'\n CSA_32bit EXCSA (PC4EX,32'b00000000000000000000000000000100,1'b0,PC8EX,co,ov);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:51: Cannot find file containing module: 'ALU_32bitNEW'\n ALU_32bitNEW ALU_Ex (ALUOPEX,ReadData1EX,ReadData2EX,AluResEX,co,ov);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:52: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit EX_MEM_PC4 (PC4EX,clk,PC4MEM),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:58: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit EXM_Latch_Wr1 (Data1,MemWriteMEM,rData1),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:60: Cannot find file containing module: 'DataMem'\n DataMem MEM_ACCESS(PC4MEM,PC8MEM,rData2,rData1,MemReadMEM,MemWriteMEM,Data1,Data2);\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:61: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit MEM_WB_PC4 (PC4MEM,clk,PC4WB),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:91: Cannot find file containing module: 'Latch_1bit'\nLatch_1bit CtrlLA0 (RegWrite,clk,RegWriteMEM),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:104: Cannot find file containing module: 'Latch_2bit'\nLatch_2bit CtrlLA13 (PCsrc,clk,PCsrcMEM),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:126: Cannot find file containing module: 'ControlUnitMIPS'\n ControlUnitMIPS Controlling_Unit (CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,ALUOP);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n" | 5,550 | module | module CA_MIPS (input [4:0]ALUOP, input clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead, input [1:0]PCsrc,WrData,WrReg,RdReg1, output [5:0]CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func);
wire RegWriteEX,RegWriteMEM,RegWriteWB,MemReadEX,MemReadMEM,MemWriteEX,MemWriteMEM,RdReg2EX,RdReg2MEM,RdReg2WB,ExrWriteEX,ExrWriteMEM,ExrWriteWB;
wire [1:0]PCsrcEX,PCsrcMEM,RdReg1EX,RdReg1MEM,RdReg1WB,WrDataEX,WrDataMEM,WrDataWB,WrRegEX,WrRegMEM,WrRegWB;
wire [4:0]ALUOPEX;
wire [31:0]WRdata0,ReadData1ID,ReadData2ID,ReadData3ID,OffsetID,PC4EX,ReadData1EX,ReadData2EX,InstrEX,JAID;
wire [4:0]ReadAd1,ReadAd2,WRdst;
wire [31:0] AluResEX,PC8EX,PC8MEM,PC4MEM,AluResMEM,InstrMEM;
wire [31:0]Data1,Data2,rData1,rData2,PC4WB,AluResWB,PCmux10EX;
wire [1:0]RdReg1sel;
wire RdReg2sel,ExrWriteWB1;
wire [31:0]PCout,InstrIF,InstrID,PC4IF,PCmux01,PCmux10,PCmux11,PC4ID,InstrWB;
wire co,ov;
wire [31:0]PCin;
mux_4x32 Mux_PC (PC4IF,PCmux01,PCmux10EX,PCmux11,PCsrc,PCin);
assign PCmux01=PCout;
CSA_32bit IFCSA (PCout,32'b00000000000000000000000000000100,1'b0,PC4IF,co,ov);
reg_32bit R0 (PCin,1'b1,1'b1,clk,PCout);
InstrMem IM0 (PCout,InstrIF,CtrlInstrIF);
Latch_32bit IF_ID_Instr (InstrIF,clk,InstrID),
IF_ID_PC4 (PC4IF,clk,PC4ID),
PCin_PCout (PCin,clk,PCout);
assign CtrlInstrIF1=InstrIF[31:26];
assign CtrlInstr=InstrID[31:26];
mux_4x5 Mux_ReadRegister1 (InstrID[25:21],InstrWB[25:21],InstrWB[20:16],5'b00000,RdReg1sel,ReadAd1),
Mux_WriteRegister (InstrWB[15:11],5'b11111,InstrWB[20:16],5'b00000,WrRegWB,WRdst);
mux_2x5 Mux_ReadRegister2 (InstrID[20:16],InstrWB[20:16],RdReg2sel,ReadAd2);
mux_4x32 Mux_WriteData (AluResWB,PC4EX,ReadData1ID,32'b00000000000000000000000000000000,WrDataWB,WRdata0);
RegisterFile RF0 (ReadAd1,ReadAd2,WRdst,WRdata0,RegWriteWB,ExrWriteWB1,clk,ReadData1ID,ReadData2ID,ReadData3ID);
ShiftLLogical2 ShiftForJA (InstrID,JAID,co,ov);
assign PCmux10[31:28]=PC4ID[31:28];
assign PCmux10[27:0]=JAID[27:0];
assign PCmux11=ReadData3ID;
Latch_32bit ID_EX_ReadData1 (ReadData1ID,clk,ReadData1EX),
ID_EX_ReadData2 (ReadData2ID,clk,ReadData2EX),
ID_EX_Instr (InstrID,clk,InstrEX),
ID_EX_PC4 (PC4ID,clk,PC4EX),
ID_EX_PCmux10 (PCmux10,clk,PCmux10EX);
CSA_32bit EXCSA (PC4EX,32'b00000000000000000000000000000100,1'b0,PC8EX,co,ov);
ALU_32bitNEW ALU_Ex (ALUOPEX,ReadData1EX,ReadData2EX,AluResEX,co,ov);
Latch_32bit EX_MEM_PC4 (PC4EX,clk,PC4MEM),
EX_MEM_PC8 (PC8EX,clk,PC8MEM),
EX_MEM_AluRes (AluResEX,clk,AluResMEM),
EX_MEM_Instr (InstrEX,clk,InstrMEM);
assign func=InstrID[5:0];
Latch_32bit EXM_Latch_Wr1 (Data1,MemWriteMEM,rData1),
EXM_Latch_Wr2 (Data2,MemWriteMEM,rData2);
DataMem MEM_ACCESS(PC4MEM,PC8MEM,rData2,rData1,MemReadMEM,MemWriteMEM,Data1,Data2);
Latch_32bit MEM_WB_PC4 (PC4MEM,clk,PC4WB),
MEM_WB_AluRes (AluResMEM,clk,AluResWB),
MEM_WB_Instr (InstrMEM,clk,InstrWB);
reg a,b,c;
initial begin
a=1'b0;
b=1'b0;
c=1'b0;
end
always@ (posedge clk) begin
a=1'b0;
b=1'b0;
c=1'b0;
if (RdReg1WB[0]) begin
a=1'b1;
end
if (RdReg2WB) begin
b=1'b1;
end
if (ExrWriteWB) begin
c=1'b1;
end
end
and(RdReg1sel[1],a,RdReg1WB[1]);
and(RdReg1sel[0],a,1'b1);
and(RdReg2sel,b,RdReg2WB);
and(ExrWriteWB1,c,ExrWriteWB);
Latch_1bit CtrlLA0 (RegWrite,clk,RegWriteMEM),
CtrlLA2 (RegWriteMEM,clk,RegWriteWB),
CtrlLA3 (MemRead,clk,MemReadMEM),
CtrlLA5 (MemWrite,clk,MemWriteMEM),
CtrlLA7 (RdReg2,clk,RdReg2MEM),
CtrlLA9 (RdReg2MEM,clk,RdReg2WB),
CtrlLA10 (ExrWrite,clk,ExrWriteMEM),
CtrlLA12 (ExrWriteMEM,clk,ExrWriteWB);
Latch_2bit CtrlLA13 (PCsrc,clk,PCsrcMEM),
CtrlLA15 (RdReg1,clk,RdReg1MEM),
CtrlLA17 (RdReg1MEM,clk,RdReg1WB),
CtrlLA18 (WrData,clk,WrDataMEM),
CtrlLA20 (WrDataMEM,clk,WrDataWB),
CtrlLA21 (WrReg,clk,WrRegMEM),
CtrlLA23 (WrRegMEM,clk,WrRegWB);
assign ALUOPEX=ALUOP;
endmodule | module CA_MIPS (input [4:0]ALUOP, input clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead, input [1:0]PCsrc,WrData,WrReg,RdReg1, output [5:0]CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func); |
wire RegWriteEX,RegWriteMEM,RegWriteWB,MemReadEX,MemReadMEM,MemWriteEX,MemWriteMEM,RdReg2EX,RdReg2MEM,RdReg2WB,ExrWriteEX,ExrWriteMEM,ExrWriteWB;
wire [1:0]PCsrcEX,PCsrcMEM,RdReg1EX,RdReg1MEM,RdReg1WB,WrDataEX,WrDataMEM,WrDataWB,WrRegEX,WrRegMEM,WrRegWB;
wire [4:0]ALUOPEX;
wire [31:0]WRdata0,ReadData1ID,ReadData2ID,ReadData3ID,OffsetID,PC4EX,ReadData1EX,ReadData2EX,InstrEX,JAID;
wire [4:0]ReadAd1,ReadAd2,WRdst;
wire [31:0] AluResEX,PC8EX,PC8MEM,PC4MEM,AluResMEM,InstrMEM;
wire [31:0]Data1,Data2,rData1,rData2,PC4WB,AluResWB,PCmux10EX;
wire [1:0]RdReg1sel;
wire RdReg2sel,ExrWriteWB1;
wire [31:0]PCout,InstrIF,InstrID,PC4IF,PCmux01,PCmux10,PCmux11,PC4ID,InstrWB;
wire co,ov;
wire [31:0]PCin;
mux_4x32 Mux_PC (PC4IF,PCmux01,PCmux10EX,PCmux11,PCsrc,PCin);
assign PCmux01=PCout;
CSA_32bit IFCSA (PCout,32'b00000000000000000000000000000100,1'b0,PC4IF,co,ov);
reg_32bit R0 (PCin,1'b1,1'b1,clk,PCout);
InstrMem IM0 (PCout,InstrIF,CtrlInstrIF);
Latch_32bit IF_ID_Instr (InstrIF,clk,InstrID),
IF_ID_PC4 (PC4IF,clk,PC4ID),
PCin_PCout (PCin,clk,PCout);
assign CtrlInstrIF1=InstrIF[31:26];
assign CtrlInstr=InstrID[31:26];
mux_4x5 Mux_ReadRegister1 (InstrID[25:21],InstrWB[25:21],InstrWB[20:16],5'b00000,RdReg1sel,ReadAd1),
Mux_WriteRegister (InstrWB[15:11],5'b11111,InstrWB[20:16],5'b00000,WrRegWB,WRdst);
mux_2x5 Mux_ReadRegister2 (InstrID[20:16],InstrWB[20:16],RdReg2sel,ReadAd2);
mux_4x32 Mux_WriteData (AluResWB,PC4EX,ReadData1ID,32'b00000000000000000000000000000000,WrDataWB,WRdata0);
RegisterFile RF0 (ReadAd1,ReadAd2,WRdst,WRdata0,RegWriteWB,ExrWriteWB1,clk,ReadData1ID,ReadData2ID,ReadData3ID);
ShiftLLogical2 ShiftForJA (InstrID,JAID,co,ov);
assign PCmux10[31:28]=PC4ID[31:28];
assign PCmux10[27:0]=JAID[27:0];
assign PCmux11=ReadData3ID;
Latch_32bit ID_EX_ReadData1 (ReadData1ID,clk,ReadData1EX),
ID_EX_ReadData2 (ReadData2ID,clk,ReadData2EX),
ID_EX_Instr (InstrID,clk,InstrEX),
ID_EX_PC4 (PC4ID,clk,PC4EX),
ID_EX_PCmux10 (PCmux10,clk,PCmux10EX);
CSA_32bit EXCSA (PC4EX,32'b00000000000000000000000000000100,1'b0,PC8EX,co,ov);
ALU_32bitNEW ALU_Ex (ALUOPEX,ReadData1EX,ReadData2EX,AluResEX,co,ov);
Latch_32bit EX_MEM_PC4 (PC4EX,clk,PC4MEM),
EX_MEM_PC8 (PC8EX,clk,PC8MEM),
EX_MEM_AluRes (AluResEX,clk,AluResMEM),
EX_MEM_Instr (InstrEX,clk,InstrMEM);
assign func=InstrID[5:0];
Latch_32bit EXM_Latch_Wr1 (Data1,MemWriteMEM,rData1),
EXM_Latch_Wr2 (Data2,MemWriteMEM,rData2);
DataMem MEM_ACCESS(PC4MEM,PC8MEM,rData2,rData1,MemReadMEM,MemWriteMEM,Data1,Data2);
Latch_32bit MEM_WB_PC4 (PC4MEM,clk,PC4WB),
MEM_WB_AluRes (AluResMEM,clk,AluResWB),
MEM_WB_Instr (InstrMEM,clk,InstrWB);
reg a,b,c;
initial begin
a=1'b0;
b=1'b0;
c=1'b0;
end
always@ (posedge clk) begin
a=1'b0;
b=1'b0;
c=1'b0;
if (RdReg1WB[0]) begin
a=1'b1;
end
if (RdReg2WB) begin
b=1'b1;
end
if (ExrWriteWB) begin
c=1'b1;
end
end
and(RdReg1sel[1],a,RdReg1WB[1]);
and(RdReg1sel[0],a,1'b1);
and(RdReg2sel,b,RdReg2WB);
and(ExrWriteWB1,c,ExrWriteWB);
Latch_1bit CtrlLA0 (RegWrite,clk,RegWriteMEM),
CtrlLA2 (RegWriteMEM,clk,RegWriteWB),
CtrlLA3 (MemRead,clk,MemReadMEM),
CtrlLA5 (MemWrite,clk,MemWriteMEM),
CtrlLA7 (RdReg2,clk,RdReg2MEM),
CtrlLA9 (RdReg2MEM,clk,RdReg2WB),
CtrlLA10 (ExrWrite,clk,ExrWriteMEM),
CtrlLA12 (ExrWriteMEM,clk,ExrWriteWB);
Latch_2bit CtrlLA13 (PCsrc,clk,PCsrcMEM),
CtrlLA15 (RdReg1,clk,RdReg1MEM),
CtrlLA17 (RdReg1MEM,clk,RdReg1WB),
CtrlLA18 (WrData,clk,WrDataMEM),
CtrlLA20 (WrDataMEM,clk,WrDataWB),
CtrlLA21 (WrReg,clk,WrRegMEM),
CtrlLA23 (WrRegMEM,clk,WrRegWB);
assign ALUOPEX=ALUOP;
endmodule | 1 |
5,104 | data/full_repos/permissive/113036182/MIPS_Assembled.v | 113,036,182 | MIPS_Assembled.v | v | 127 | 179 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:21: Cannot find file containing module: 'mux_4x32'\n mux_4x32 Mux_PC (PC4IF,PCmux01,PCmux10EX,PCmux11,PCsrc,PCin);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux_4x32.sv\n mux_4x32\n mux_4x32.v\n mux_4x32.sv\n obj_dir/mux_4x32\n obj_dir/mux_4x32.v\n obj_dir/mux_4x32.sv\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:23: Cannot find file containing module: 'CSA_32bit'\n CSA_32bit IFCSA (PCout,32'b00000000000000000000000000000100,1'b0,PC4IF,co,ov);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:24: Cannot find file containing module: 'reg_32bit'\n reg_32bit R0 (PCin,1'b1,1'b1,clk,PCout);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:25: Cannot find file containing module: 'InstrMem'\n InstrMem IM0 (PCout,InstrIF,CtrlInstrIF);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:26: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit IF_ID_Instr (InstrIF,clk,InstrID),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:33: Cannot find file containing module: 'mux_4x5'\n mux_4x5 Mux_ReadRegister1 (InstrID[25:21],InstrWB[25:21],InstrWB[20:16],5'b00000,RdReg1sel,ReadAd1),\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:35: Cannot find file containing module: 'mux_2x5'\n mux_2x5 Mux_ReadRegister2 (InstrID[20:16],InstrWB[20:16],RdReg2sel,ReadAd2);\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:36: Cannot find file containing module: 'mux_4x32'\n mux_4x32 Mux_WriteData (AluResWB,PC4EX,ReadData1ID,32'b00000000000000000000000000000000,WrDataWB,WRdata0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:37: Cannot find file containing module: 'RegisterFile'\n RegisterFile RF0 (ReadAd1,ReadAd2,WRdst,WRdata0,RegWriteWB,ExrWriteWB1,clk,ReadData1ID,ReadData2ID,ReadData3ID);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:38: Cannot find file containing module: 'ShiftLLogical2'\n ShiftLLogical2 ShiftForJA (InstrID,JAID,co,ov);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:43: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit ID_EX_ReadData1 (ReadData1ID,clk,ReadData1EX),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:50: Cannot find file containing module: 'CSA_32bit'\n CSA_32bit EXCSA (PC4EX,32'b00000000000000000000000000000100,1'b0,PC8EX,co,ov);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:51: Cannot find file containing module: 'ALU_32bitNEW'\n ALU_32bitNEW ALU_Ex (ALUOPEX,ReadData1EX,ReadData2EX,AluResEX,co,ov);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:52: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit EX_MEM_PC4 (PC4EX,clk,PC4MEM),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:58: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit EXM_Latch_Wr1 (Data1,MemWriteMEM,rData1),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:60: Cannot find file containing module: 'DataMem'\n DataMem MEM_ACCESS(PC4MEM,PC8MEM,rData2,rData1,MemReadMEM,MemWriteMEM,Data1,Data2);\n ^~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:61: Cannot find file containing module: 'Latch_32bit'\n Latch_32bit MEM_WB_PC4 (PC4MEM,clk,PC4WB),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:91: Cannot find file containing module: 'Latch_1bit'\nLatch_1bit CtrlLA0 (RegWrite,clk,RegWriteMEM),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:104: Cannot find file containing module: 'Latch_2bit'\nLatch_2bit CtrlLA13 (PCsrc,clk,PCsrcMEM),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/MIPS_Assembled.v:126: Cannot find file containing module: 'ControlUnitMIPS'\n ControlUnitMIPS Controlling_Unit (CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,ALUOP);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n" | 5,550 | module | module Assembled_MIPS (input clk);
wire [4:0]ALUOP;
wire RegWrite,ExrWrite,RdReg2,MemWrite,MemRead;
wire [1:0]PCsrc,WrData,WrReg,RdReg1;
wire [5:0]CtrlInstr,func,CtrlInstrIF,CtrlInstrIF1;
CA_MIPS Hardware_Design (ALUOP,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func);
ControlUnitMIPS Controlling_Unit (CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,ALUOP);
endmodule | module Assembled_MIPS (input clk); |
wire [4:0]ALUOP;
wire RegWrite,ExrWrite,RdReg2,MemWrite,MemRead;
wire [1:0]PCsrc,WrData,WrReg,RdReg1;
wire [5:0]CtrlInstr,func,CtrlInstrIF,CtrlInstrIF1;
CA_MIPS Hardware_Design (ALUOP,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func);
ControlUnitMIPS Controlling_Unit (CtrlInstr,CtrlInstrIF,CtrlInstrIF1,func,clk,RegWrite,ExrWrite,RdReg2,MemWrite,MemRead,PCsrc,WrData,WrReg,RdReg1,ALUOP);
endmodule | 1 |
5,105 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module tristate_buffer(input x, enable, output z);
assign z = enable? x : 'bz;
endmodule | module tristate_buffer(input x, enable, output z); |
assign z = enable? x : 'bz;
endmodule | 1 |
5,106 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);
reg[31:0] internal_q;
always@( posedge clk ) begin
if (en) begin
if (wr) internal_q <= d;
end
end
assign q = internal_q;
endmodule | module reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q); |
reg[31:0] internal_q;
always@( posedge clk ) begin
if (en) begin
if (wr) internal_q <= d;
end
end
assign q = internal_q;
endmodule | 1 |
5,107 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module decoder_32bit (input [4:0]x, output [31:0]y);
and(y[0],~x[4],~x[3],~x[2],~x[1],~x[0]);
and(y[1],~x[4],~x[3],~x[2],~x[1],x[0]);
and(y[2],~x[4],~x[3],~x[2],x[1],~x[0]);
and(y[3],~x[4],~x[3],~x[2],x[1],x[0]);
and(y[4],~x[4],~x[3],x[2],~x[1],~x[0]);
and(y[5],~x[4],~x[3],x[2],~x[1],x[0]);
and(y[6],~x[4],~x[3],x[2],x[1],~x[0]);
and(y[7],~x[4],~x[3],x[2],x[1],x[0]);
and(y[8],~x[4],x[3],~x[2],~x[1],~x[0]);
and(y[9],~x[4],x[3],~x[2],~x[1],x[0]);
and(y[10],~x[4],x[3],~x[2],x[1],~x[0]);
and(y[11],~x[4],x[3],~x[2],x[1],x[0]);
and(y[12],~x[4],x[3],x[2],~x[1],~x[0]);
and(y[13],~x[4],x[3],x[2],~x[1],x[0]);
and(y[14],~x[4],x[3],x[2],x[1],~x[0]);
and(y[15],~x[4],x[3],x[2],x[1],x[0]);
and(y[16],x[4],~x[3],~x[2],~x[1],~x[0]);
and(y[17],x[4],~x[3],~x[2],~x[1],x[0]);
and(y[18],x[4],~x[3],~x[2],x[1],~x[0]);
and(y[19],x[4],~x[3],~x[2],x[1],x[0]);
and(y[20],x[4],~x[3],x[2],~x[1],~x[0]);
and(y[21],x[4],~x[3],x[2],~x[1],x[0]);
and(y[22],x[4],~x[3],x[2],x[1],~x[0]);
and(y[23],x[4],~x[3],x[2],x[1],x[0]);
and(y[24],x[4],x[3],~x[2],~x[1],~x[0]);
and(y[25],x[4],x[3],~x[2],~x[1],x[0]);
and(y[26],x[4],x[3],~x[2],x[1],~x[0]);
and(y[27],x[4],x[3],~x[2],x[1],x[0]);
and(y[28],x[4],x[3],x[2],~x[1],~x[0]);
and(y[29],x[4],x[3],x[2],~x[1],x[0]);
and(y[30],x[4],x[3],x[2],x[1],~x[0]);
and(y[31],x[4],x[3],x[2],x[1],x[0]);
endmodule | module decoder_32bit (input [4:0]x, output [31:0]y); |
and(y[0],~x[4],~x[3],~x[2],~x[1],~x[0]);
and(y[1],~x[4],~x[3],~x[2],~x[1],x[0]);
and(y[2],~x[4],~x[3],~x[2],x[1],~x[0]);
and(y[3],~x[4],~x[3],~x[2],x[1],x[0]);
and(y[4],~x[4],~x[3],x[2],~x[1],~x[0]);
and(y[5],~x[4],~x[3],x[2],~x[1],x[0]);
and(y[6],~x[4],~x[3],x[2],x[1],~x[0]);
and(y[7],~x[4],~x[3],x[2],x[1],x[0]);
and(y[8],~x[4],x[3],~x[2],~x[1],~x[0]);
and(y[9],~x[4],x[3],~x[2],~x[1],x[0]);
and(y[10],~x[4],x[3],~x[2],x[1],~x[0]);
and(y[11],~x[4],x[3],~x[2],x[1],x[0]);
and(y[12],~x[4],x[3],x[2],~x[1],~x[0]);
and(y[13],~x[4],x[3],x[2],~x[1],x[0]);
and(y[14],~x[4],x[3],x[2],x[1],~x[0]);
and(y[15],~x[4],x[3],x[2],x[1],x[0]);
and(y[16],x[4],~x[3],~x[2],~x[1],~x[0]);
and(y[17],x[4],~x[3],~x[2],~x[1],x[0]);
and(y[18],x[4],~x[3],~x[2],x[1],~x[0]);
and(y[19],x[4],~x[3],~x[2],x[1],x[0]);
and(y[20],x[4],~x[3],x[2],~x[1],~x[0]);
and(y[21],x[4],~x[3],x[2],~x[1],x[0]);
and(y[22],x[4],~x[3],x[2],x[1],~x[0]);
and(y[23],x[4],~x[3],x[2],x[1],x[0]);
and(y[24],x[4],x[3],~x[2],~x[1],~x[0]);
and(y[25],x[4],x[3],~x[2],~x[1],x[0]);
and(y[26],x[4],x[3],~x[2],x[1],~x[0]);
and(y[27],x[4],x[3],~x[2],x[1],x[0]);
and(y[28],x[4],x[3],x[2],~x[1],~x[0]);
and(y[29],x[4],x[3],x[2],~x[1],x[0]);
and(y[30],x[4],x[3],x[2],x[1],~x[0]);
and(y[31],x[4],x[3],x[2],x[1],x[0]);
endmodule | 1 |
5,108 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);
mux m1 (O1[0],O2[0],select,out1[0]),
m2 (O1[1],O2[1],select,out1[1]),
m3 (O1[2],O2[2],select,out1[2]),
m4 (O1[3],O2[3],select,out1[3]),
m5 (O1[4],O2[4],select,out1[4]);
endmodule | module mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1); |
mux m1 (O1[0],O2[0],select,out1[0]),
m2 (O1[1],O2[1],select,out1[1]),
m3 (O1[2],O2[2],select,out1[2]),
m4 (O1[3],O2[3],select,out1[3]),
m5 (O1[4],O2[4],select,out1[4]);
endmodule | 1 |
5,109 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);
wire [4:0]out1,out2;
mux q1 (O1[0],O2[0],select[0],out1[0]),
q2 (O1[1],O2[1],select[0],out1[1]),
q3 (O1[2],O2[2],select[0],out1[2]),
q4 (O1[3],O2[3],select[0],out1[3]),
q5 (O1[4],O2[4],select[0],out1[4]),
r1 (O3[0],O4[0],select[0],out2[0]),
r2 (O3[1],O4[1],select[0],out2[1]),
r3 (O3[2],O4[2],select[0],out2[2]),
r4 (O3[3],O4[3],select[0],out2[3]),
r5 (O3[4],O4[4],select[0],out2[4]),
t1 (out1[0],out2[0],select[1],out3[0]),
t2 (out1[1],out2[1],select[1],out3[1]),
t3 (out1[2],out2[2],select[1],out3[2]),
t4 (out1[3],out2[3],select[1],out3[3]),
t5 (out1[4],out2[4],select[1],out3[4]);
endmodule | module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3); |
wire [4:0]out1,out2;
mux q1 (O1[0],O2[0],select[0],out1[0]),
q2 (O1[1],O2[1],select[0],out1[1]),
q3 (O1[2],O2[2],select[0],out1[2]),
q4 (O1[3],O2[3],select[0],out1[3]),
q5 (O1[4],O2[4],select[0],out1[4]),
r1 (O3[0],O4[0],select[0],out2[0]),
r2 (O3[1],O4[1],select[0],out2[1]),
r3 (O3[2],O4[2],select[0],out2[2]),
r4 (O3[3],O4[3],select[0],out2[3]),
r5 (O3[4],O4[4],select[0],out2[4]),
t1 (out1[0],out2[0],select[1],out3[0]),
t2 (out1[1],out2[1],select[1],out3[1]),
t3 (out1[2],out2[2],select[1],out3[2]),
t4 (out1[3],out2[3],select[1],out3[3]),
t5 (out1[4],out2[4],select[1],out3[4]);
endmodule | 1 |
5,110 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);
mux m1 (O1[0],O2[0],select,out1[0]),
m2 (O1[1],O2[1],select,out1[1]),
m3 (O1[2],O2[2],select,out1[2]),
m4 (O1[3],O2[3],select,out1[3]),
m5 (O1[4],O2[4],select,out1[4]),
m6 (O1[5],O2[5],select,out1[5]),
m7 (O1[6],O2[6],select,out1[6]),
m8 (O1[7],O2[7],select,out1[7]),
m9 (O1[8],O2[8],select,out1[8]),
m10 (O1[9],O2[9],select,out1[9]),
m11 (O1[10],O2[10],select,out1[10]),
m12 (O1[11],O2[11],select,out1[11]),
m13 (O1[12],O2[12],select,out1[12]),
m14 (O1[13],O2[13],select,out1[13]),
m15 (O1[14],O2[14],select,out1[14]),
m16 (O1[15],O2[15],select,out1[15]),
m17 (O1[16],O2[16],select,out1[16]),
m18 (O1[17],O2[17],select,out1[17]),
m19 (O1[18],O2[18],select,out1[18]),
m20 (O1[19],O2[19],select,out1[19]),
m21 (O1[20],O2[20],select,out1[20]),
m22 (O1[21],O2[21],select,out1[21]),
m23 (O1[22],O2[22],select,out1[22]),
m24 (O1[23],O2[23],select,out1[23]),
m25 (O1[24],O2[24],select,out1[24]),
m26 (O1[25],O2[25],select,out1[25]),
m27 (O1[26],O2[26],select,out1[26]),
m28 (O1[27],O2[27],select,out1[27]),
m29 (O1[28],O2[28],select,out1[28]),
m30 (O1[29],O2[29],select,out1[29]),
m31 (O1[30],O2[30],select,out1[30]),
m32 (O1[31],O2[31],select,out1[31]);
endmodule | module mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1); |
mux m1 (O1[0],O2[0],select,out1[0]),
m2 (O1[1],O2[1],select,out1[1]),
m3 (O1[2],O2[2],select,out1[2]),
m4 (O1[3],O2[3],select,out1[3]),
m5 (O1[4],O2[4],select,out1[4]),
m6 (O1[5],O2[5],select,out1[5]),
m7 (O1[6],O2[6],select,out1[6]),
m8 (O1[7],O2[7],select,out1[7]),
m9 (O1[8],O2[8],select,out1[8]),
m10 (O1[9],O2[9],select,out1[9]),
m11 (O1[10],O2[10],select,out1[10]),
m12 (O1[11],O2[11],select,out1[11]),
m13 (O1[12],O2[12],select,out1[12]),
m14 (O1[13],O2[13],select,out1[13]),
m15 (O1[14],O2[14],select,out1[14]),
m16 (O1[15],O2[15],select,out1[15]),
m17 (O1[16],O2[16],select,out1[16]),
m18 (O1[17],O2[17],select,out1[17]),
m19 (O1[18],O2[18],select,out1[18]),
m20 (O1[19],O2[19],select,out1[19]),
m21 (O1[20],O2[20],select,out1[20]),
m22 (O1[21],O2[21],select,out1[21]),
m23 (O1[22],O2[22],select,out1[22]),
m24 (O1[23],O2[23],select,out1[23]),
m25 (O1[24],O2[24],select,out1[24]),
m26 (O1[25],O2[25],select,out1[25]),
m27 (O1[26],O2[26],select,out1[26]),
m28 (O1[27],O2[27],select,out1[27]),
m29 (O1[28],O2[28],select,out1[28]),
m30 (O1[29],O2[29],select,out1[29]),
m31 (O1[30],O2[30],select,out1[30]),
m32 (O1[31],O2[31],select,out1[31]);
endmodule | 1 |
5,111 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);
wire [31:0]out1,out2;
mux m1 (O1[0],O2[0],select[0],out1[0]),
m2 (O1[1],O2[1],select[0],out1[1]),
m3 (O1[2],O2[2],select[0],out1[2]),
m4 (O1[3],O2[3],select[0],out1[3]),
m5 (O1[4],O2[4],select[0],out1[4]),
m6 (O1[5],O2[5],select[0],out1[5]),
m7 (O1[6],O2[6],select[0],out1[6]),
m8 (O1[7],O2[7],select[0],out1[7]),
m9 (O1[8],O2[8],select[0],out1[8]),
m10 (O1[9],O2[9],select[0],out1[9]),
m11 (O1[10],O2[10],select[0],out1[10]),
m12 (O1[11],O2[11],select[0],out1[11]),
m13 (O1[12],O2[12],select[0],out1[12]),
m14 (O1[13],O2[13],select[0],out1[13]),
m15 (O1[14],O2[14],select[0],out1[14]),
m16 (O1[15],O2[15],select[0],out1[15]),
m17 (O1[16],O2[16],select[0],out1[16]),
m18 (O1[17],O2[17],select[0],out1[17]),
m19 (O1[18],O2[18],select[0],out1[18]),
m20 (O1[19],O2[19],select[0],out1[19]),
m21 (O1[20],O2[20],select[0],out1[20]),
m22 (O1[21],O2[21],select[0],out1[21]),
m23 (O1[22],O2[22],select[0],out1[22]),
m24 (O1[23],O2[23],select[0],out1[23]),
m25 (O1[24],O2[24],select[0],out1[24]),
m26 (O1[25],O2[25],select[0],out1[25]),
m27 (O1[26],O2[26],select[0],out1[26]),
m28 (O1[27],O2[27],select[0],out1[27]),
m29 (O1[28],O2[28],select[0],out1[28]),
m30 (O1[29],O2[29],select[0],out1[29]),
m31 (O1[30],O2[30],select[0],out1[30]),
m32 (O1[31],O2[31],select[0],out1[31]),
n1 (O3[0],O4[0],select[0],out2[0]),
n2 (O3[1],O4[1],select[0],out2[1]),
n3 (O3[2],O4[2],select[0],out2[2]),
n4 (O3[3],O4[3],select[0],out2[3]),
n5 (O3[4],O4[4],select[0],out2[4]),
n6 (O3[5],O4[5],select[0],out2[5]),
n7 (O3[6],O4[6],select[0],out2[6]),
n8 (O3[7],O4[7],select[0],out2[7]),
n9 (O3[8],O4[8],select[0],out2[8]),
n10 (O3[9],O4[9],select[0],out2[9]),
n11 (O3[10],O4[10],select[0],out2[10]),
n12 (O3[11],O4[11],select[0],out2[11]),
n13 (O3[12],O4[12],select[0],out2[12]),
n14 (O3[13],O4[13],select[0],out2[13]),
n15 (O3[14],O4[14],select[0],out2[14]),
n16 (O3[15],O4[15],select[0],out2[15]),
n17 (O3[16],O4[16],select[0],out2[16]),
n18 (O3[17],O4[17],select[0],out2[17]),
n19 (O3[18],O4[18],select[0],out2[18]),
n20 (O3[19],O4[19],select[0],out2[19]),
n21 (O3[20],O4[20],select[0],out2[20]),
n22 (O3[21],O4[21],select[0],out2[21]),
n23 (O3[22],O4[22],select[0],out2[22]),
n24 (O3[23],O4[23],select[0],out2[23]),
n25 (O3[24],O4[24],select[0],out2[24]),
n26 (O3[25],O4[25],select[0],out2[25]),
n27 (O3[26],O4[26],select[0],out2[26]),
n28 (O3[27],O4[27],select[0],out2[27]),
n29 (O3[28],O4[28],select[0],out2[28]),
n30 (O3[29],O4[29],select[0],out2[29]),
n31 (O3[30],O4[30],select[0],out2[30]),
n32 (O3[31],O4[31],select[0],out2[31]),
p1 (out1[0],out2[0],select[1],out3[0]),
p2 (out1[1],out2[1],select[1],out3[1]),
p3 (out1[2],out2[2],select[1],out3[2]),
p4 (out1[3],out2[3],select[1],out3[3]),
p5 (out1[4],out2[4],select[1],out3[4]),
p6 (out1[5],out2[5],select[1],out3[5]),
p7 (out1[6],out2[6],select[1],out3[6]),
p8 (out1[7],out2[7],select[1],out3[7]),
p9 (out1[8],out2[8],select[1],out3[8]),
p10 (out1[9],out2[9],select[1],out3[9]),
p11 (out1[10],out2[10],select[1],out3[10]),
p12 (out1[11],out2[11],select[1],out3[11]),
p13 (out1[12],out2[12],select[1],out3[12]),
p14 (out1[13],out2[13],select[1],out3[13]),
p15 (out1[14],out2[14],select[1],out3[14]),
p16 (out1[15],out2[15],select[1],out3[15]),
p17 (out1[16],out2[16],select[1],out3[16]),
p18 (out1[17],out2[17],select[1],out3[17]),
p19 (out1[18],out2[18],select[1],out3[18]),
p20 (out1[19],out2[19],select[1],out3[19]),
p21 (out1[20],out2[20],select[1],out3[20]),
p22 (out1[21],out2[21],select[1],out3[21]),
p23 (out1[22],out2[22],select[1],out3[22]),
p24 (out1[23],out2[23],select[1],out3[23]),
p25 (out1[24],out2[24],select[1],out3[24]),
p26 (out1[25],out2[25],select[1],out3[25]),
p27 (out1[26],out2[26],select[1],out3[26]),
p28 (out1[27],out2[27],select[1],out3[27]),
p29 (out1[28],out2[28],select[1],out3[28]),
p30 (out1[29],out2[29],select[1],out3[29]),
p31 (out1[30],out2[30],select[1],out3[30]),
p32 (out1[31],out2[31],select[1],out3[31]);
endmodule | module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3); |
wire [31:0]out1,out2;
mux m1 (O1[0],O2[0],select[0],out1[0]),
m2 (O1[1],O2[1],select[0],out1[1]),
m3 (O1[2],O2[2],select[0],out1[2]),
m4 (O1[3],O2[3],select[0],out1[3]),
m5 (O1[4],O2[4],select[0],out1[4]),
m6 (O1[5],O2[5],select[0],out1[5]),
m7 (O1[6],O2[6],select[0],out1[6]),
m8 (O1[7],O2[7],select[0],out1[7]),
m9 (O1[8],O2[8],select[0],out1[8]),
m10 (O1[9],O2[9],select[0],out1[9]),
m11 (O1[10],O2[10],select[0],out1[10]),
m12 (O1[11],O2[11],select[0],out1[11]),
m13 (O1[12],O2[12],select[0],out1[12]),
m14 (O1[13],O2[13],select[0],out1[13]),
m15 (O1[14],O2[14],select[0],out1[14]),
m16 (O1[15],O2[15],select[0],out1[15]),
m17 (O1[16],O2[16],select[0],out1[16]),
m18 (O1[17],O2[17],select[0],out1[17]),
m19 (O1[18],O2[18],select[0],out1[18]),
m20 (O1[19],O2[19],select[0],out1[19]),
m21 (O1[20],O2[20],select[0],out1[20]),
m22 (O1[21],O2[21],select[0],out1[21]),
m23 (O1[22],O2[22],select[0],out1[22]),
m24 (O1[23],O2[23],select[0],out1[23]),
m25 (O1[24],O2[24],select[0],out1[24]),
m26 (O1[25],O2[25],select[0],out1[25]),
m27 (O1[26],O2[26],select[0],out1[26]),
m28 (O1[27],O2[27],select[0],out1[27]),
m29 (O1[28],O2[28],select[0],out1[28]),
m30 (O1[29],O2[29],select[0],out1[29]),
m31 (O1[30],O2[30],select[0],out1[30]),
m32 (O1[31],O2[31],select[0],out1[31]),
n1 (O3[0],O4[0],select[0],out2[0]),
n2 (O3[1],O4[1],select[0],out2[1]),
n3 (O3[2],O4[2],select[0],out2[2]),
n4 (O3[3],O4[3],select[0],out2[3]),
n5 (O3[4],O4[4],select[0],out2[4]),
n6 (O3[5],O4[5],select[0],out2[5]),
n7 (O3[6],O4[6],select[0],out2[6]),
n8 (O3[7],O4[7],select[0],out2[7]),
n9 (O3[8],O4[8],select[0],out2[8]),
n10 (O3[9],O4[9],select[0],out2[9]),
n11 (O3[10],O4[10],select[0],out2[10]),
n12 (O3[11],O4[11],select[0],out2[11]),
n13 (O3[12],O4[12],select[0],out2[12]),
n14 (O3[13],O4[13],select[0],out2[13]),
n15 (O3[14],O4[14],select[0],out2[14]),
n16 (O3[15],O4[15],select[0],out2[15]),
n17 (O3[16],O4[16],select[0],out2[16]),
n18 (O3[17],O4[17],select[0],out2[17]),
n19 (O3[18],O4[18],select[0],out2[18]),
n20 (O3[19],O4[19],select[0],out2[19]),
n21 (O3[20],O4[20],select[0],out2[20]),
n22 (O3[21],O4[21],select[0],out2[21]),
n23 (O3[22],O4[22],select[0],out2[22]),
n24 (O3[23],O4[23],select[0],out2[23]),
n25 (O3[24],O4[24],select[0],out2[24]),
n26 (O3[25],O4[25],select[0],out2[25]),
n27 (O3[26],O4[26],select[0],out2[26]),
n28 (O3[27],O4[27],select[0],out2[27]),
n29 (O3[28],O4[28],select[0],out2[28]),
n30 (O3[29],O4[29],select[0],out2[29]),
n31 (O3[30],O4[30],select[0],out2[30]),
n32 (O3[31],O4[31],select[0],out2[31]),
p1 (out1[0],out2[0],select[1],out3[0]),
p2 (out1[1],out2[1],select[1],out3[1]),
p3 (out1[2],out2[2],select[1],out3[2]),
p4 (out1[3],out2[3],select[1],out3[3]),
p5 (out1[4],out2[4],select[1],out3[4]),
p6 (out1[5],out2[5],select[1],out3[5]),
p7 (out1[6],out2[6],select[1],out3[6]),
p8 (out1[7],out2[7],select[1],out3[7]),
p9 (out1[8],out2[8],select[1],out3[8]),
p10 (out1[9],out2[9],select[1],out3[9]),
p11 (out1[10],out2[10],select[1],out3[10]),
p12 (out1[11],out2[11],select[1],out3[11]),
p13 (out1[12],out2[12],select[1],out3[12]),
p14 (out1[13],out2[13],select[1],out3[13]),
p15 (out1[14],out2[14],select[1],out3[14]),
p16 (out1[15],out2[15],select[1],out3[15]),
p17 (out1[16],out2[16],select[1],out3[16]),
p18 (out1[17],out2[17],select[1],out3[17]),
p19 (out1[18],out2[18],select[1],out3[18]),
p20 (out1[19],out2[19],select[1],out3[19]),
p21 (out1[20],out2[20],select[1],out3[20]),
p22 (out1[21],out2[21],select[1],out3[21]),
p23 (out1[22],out2[22],select[1],out3[22]),
p24 (out1[23],out2[23],select[1],out3[23]),
p25 (out1[24],out2[24],select[1],out3[24]),
p26 (out1[25],out2[25],select[1],out3[25]),
p27 (out1[26],out2[26],select[1],out3[26]),
p28 (out1[27],out2[27],select[1],out3[27]),
p29 (out1[28],out2[28],select[1],out3[28]),
p30 (out1[29],out2[29],select[1],out3[29]),
p31 (out1[30],out2[30],select[1],out3[30]),
p32 (out1[31],out2[31],select[1],out3[31]);
endmodule | 1 |
5,112 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module Latch_1bit (input D, input clk, output reg Q);
always @ (posedge clk)
begin
Q <= D;
end
endmodule | module Latch_1bit (input D, input clk, output reg Q); |
always @ (posedge clk)
begin
Q <= D;
end
endmodule | 1 |
5,113 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module Latch_32bit (input [31:0]D,input clk,output [31:0]Q);
Latch_1bit L0 (D[0],clk,Q[0]),
L1 (D[1],clk,Q[1]),
L2 (D[2],clk,Q[2]),
L3 (D[3],clk,Q[3]),
L4 (D[4],clk,Q[4]),
L5 (D[5],clk,Q[5]),
L6 (D[6],clk,Q[6]),
L7 (D[7],clk,Q[7]),
L8 (D[8],clk,Q[8]),
L9 (D[9],clk,Q[9]),
L10 (D[10],clk,Q[10]),
L11 (D[11],clk,Q[11]),
L12 (D[12],clk,Q[12]),
L13 (D[13],clk,Q[13]),
L14 (D[14],clk,Q[14]),
L15 (D[15],clk,Q[15]),
L16 (D[16],clk,Q[16]),
L17 (D[17],clk,Q[17]),
L18 (D[18],clk,Q[18]),
L19 (D[19],clk,Q[19]),
L20 (D[20],clk,Q[20]),
L21 (D[21],clk,Q[21]),
L22 (D[22],clk,Q[22]),
L23 (D[23],clk,Q[23]),
L24 (D[24],clk,Q[24]),
L25 (D[25],clk,Q[25]),
L26 (D[26],clk,Q[26]),
L27 (D[27],clk,Q[27]),
L28 (D[28],clk,Q[28]),
L29 (D[29],clk,Q[29]),
L30 (D[30],clk,Q[30]),
L31 (D[31],clk,Q[31]);
endmodule | module Latch_32bit (input [31:0]D,input clk,output [31:0]Q); |
Latch_1bit L0 (D[0],clk,Q[0]),
L1 (D[1],clk,Q[1]),
L2 (D[2],clk,Q[2]),
L3 (D[3],clk,Q[3]),
L4 (D[4],clk,Q[4]),
L5 (D[5],clk,Q[5]),
L6 (D[6],clk,Q[6]),
L7 (D[7],clk,Q[7]),
L8 (D[8],clk,Q[8]),
L9 (D[9],clk,Q[9]),
L10 (D[10],clk,Q[10]),
L11 (D[11],clk,Q[11]),
L12 (D[12],clk,Q[12]),
L13 (D[13],clk,Q[13]),
L14 (D[14],clk,Q[14]),
L15 (D[15],clk,Q[15]),
L16 (D[16],clk,Q[16]),
L17 (D[17],clk,Q[17]),
L18 (D[18],clk,Q[18]),
L19 (D[19],clk,Q[19]),
L20 (D[20],clk,Q[20]),
L21 (D[21],clk,Q[21]),
L22 (D[22],clk,Q[22]),
L23 (D[23],clk,Q[23]),
L24 (D[24],clk,Q[24]),
L25 (D[25],clk,Q[25]),
L26 (D[26],clk,Q[26]),
L27 (D[27],clk,Q[27]),
L28 (D[28],clk,Q[28]),
L29 (D[29],clk,Q[29]),
L30 (D[30],clk,Q[30]),
L31 (D[31],clk,Q[31]);
endmodule | 1 |
5,114 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module SignExtend16 (input [15:0]x, output [31:0]y);
assign y[15:0]=x[15:0];
assign y[16]=x[15];
assign y[17]=x[15];
assign y[18]=x[15];
assign y[19]=x[15];
assign y[20]=x[15];
assign y[21]=x[15];
assign y[22]=x[15];
assign y[23]=x[15];
assign y[24]=x[15];
assign y[25]=x[15];
assign y[26]=x[15];
assign y[27]=x[15];
assign y[28]=x[15];
assign y[29]=x[15];
assign y[30]=x[15];
assign y[31]=x[15];
endmodule | module SignExtend16 (input [15:0]x, output [31:0]y); |
assign y[15:0]=x[15:0];
assign y[16]=x[15];
assign y[17]=x[15];
assign y[18]=x[15];
assign y[19]=x[15];
assign y[20]=x[15];
assign y[21]=x[15];
assign y[22]=x[15];
assign y[23]=x[15];
assign y[24]=x[15];
assign y[25]=x[15];
assign y[26]=x[15];
assign y[27]=x[15];
assign y[28]=x[15];
assign y[29]=x[15];
assign y[30]=x[15];
assign y[31]=x[15];
endmodule | 1 |
5,115 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module Latch_5bit (input [4:0]D,input clk,output [4:0]Q);
Latch_1bit L0 (D[0],clk,Q[0]),
L1 (D[1],clk,Q[1]),
L2 (D[2],clk,Q[2]),
L3 (D[3],clk,Q[3]),
L4 (D[4],clk,Q[4]);
endmodule | module Latch_5bit (input [4:0]D,input clk,output [4:0]Q); |
Latch_1bit L0 (D[0],clk,Q[0]),
L1 (D[1],clk,Q[1]),
L2 (D[2],clk,Q[2]),
L3 (D[3],clk,Q[3]),
L4 (D[4],clk,Q[4]);
endmodule | 1 |
5,116 | data/full_repos/permissive/113036182/OtherUnits.v | 113,036,182 | OtherUnits.v | v | 285 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n ^~~~~~~~~~~~~~~\n : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n ^~~~~~~~~\n : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n ^~~~~~~~~~~~~\n : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n ^~~~~~~\n : ... Top module \'mux_4x5\'\n module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n ^~~~~~~\n : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n ^~~~~~~~\n : ... Top module \'mux_4x32\'\n module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n ^~~~~~~~\n : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n ^~~~~~~~~~~\n : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n ^~~~~~~~~~~~\n : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n ^~~~~~~~~~\n : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n ... Looked in:\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n mux\n mux.v\n mux.sv\n obj_dir/mux\n obj_dir/mux.v\n obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 5,551 | module | module Latch_2bit (input [1:0]D,input clk,output [1:0]Q);
Latch_1bit L00 (D[0],clk,Q[0]),
L01 (D[1],clk,Q[1]);
endmodule | module Latch_2bit (input [1:0]D,input clk,output [1:0]Q); |
Latch_1bit L00 (D[0],clk,Q[0]),
L01 (D[1],clk,Q[1]);
endmodule | 1 |
5,118 | data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v | 113,268,705 | FPGA_I2C.v | v | 267 | 69 | [] | [] | [] | null | line:48: before: "integer" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:18: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'SDA_OUT\' generates 1 bits.\n : ... In instance FPGA_I2C\nassign SDA = (RW ? 8\'bz : SDA_OUT); \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:18: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance FPGA_I2C\nassign SDA = (RW ? 8\'bz : SDA_OUT); \n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:19: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'SDA\' generates 1 bits.\n : ... In instance FPGA_I2C\nassign SDA_IN = (RW ? SDA : 8\'bz);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:19: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance FPGA_I2C\nassign SDA_IN = (RW ? SDA : 8\'bz);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:21: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'SCL_OUT\' generates 1 bits.\n : ... In instance FPGA_I2C\nassign SCL = (MS ? SCL_OUT : 8\'bz); \n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:21: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance FPGA_I2C\nassign SCL = (MS ? SCL_OUT : 8\'bz); \n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:22: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'SCL\' generates 1 bits.\n : ... In instance FPGA_I2C\nassign SCL_IN = (MS ? 8\'bz : SCL);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:22: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance FPGA_I2C\nassign SCL_IN = (MS ? 8\'bz : SCL);\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:24: Little bit endian vector: MSB < LSB of bit range: 0:7\noutput reg [0:7] DATA_OUT;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_I2C/FPGA_I2C.v:25: Little bit endian vector: MSB < LSB of bit range: 0:7\noutput reg [0:7] DATA_IN;\n ^\n%Error: Exiting due to 10 warning(s)\n' | 5,553 | module | module FPGA_I2C(CLK,RST,SCL,SDA
,transaction,START_BIT,status,pos,ACK,DATA_OUT,DATA_IN,round);
input CLK;
input RST;
inout wire SCL;
inout wire SDA;
wire SCL_IN;
reg SCL_OUT;
reg MS;
wire SDA_IN;
reg SDA_OUT;
reg RW;
assign SDA = (RW ? 8'bz : SDA_OUT);
assign SDA_IN = (RW ? SDA : 8'bz);
assign SCL = (MS ? SCL_OUT : 8'bz);
assign SCL_IN = (MS ? 8'bz : SCL);
output reg [0:7] DATA_OUT;
output reg [0:7] DATA_IN;
output reg [3:0] pos;
output reg [3:0] status;
output reg transaction;
reg transaction1,transaction2;
output reg START_BIT;
output reg ACK;
wire NACK;
assign NACK = ~ACK;
integer DIV_CLK;
parameter DIV_CLK_LIMIT = 62;
parameter START_CONDITION = 0,
STOP_CONDITION = 1,
READ_CONDITION = 2,
WRITE_CONDITION = 3;
parameter ROUND_LIMIT = 4;
reg [6:0] SLAVE_ADDR;
output integer round;
integer count;
initial begin
MS = 1;
RW = 0;
SDA_OUT = 1;
SCL_OUT = 1;
DIV_CLK = 0;
pos = 0;
transaction = 0;
START_BIT = 0;
ACK = 0;
DATA_IN = 8'h0;
DATA_OUT = 8'h0;
SLAVE_ADDR = 7'h26;
round = 0;
count = 0;
end
always @(posedge CLK) begin
transaction1 <= transaction;
end
always @(posedge CLK or negedge RST) if(!RST) begin
round = 0;
START_BIT <= 0;
status <= START_CONDITION;
count <= 0;
end else begin
if(START_BIT) START_BIT <= 0;
if(status == 5) begin
count <= count + 1;
if(count == 5_000_000) begin
round = 0;
count <= 0;
end
end
if(!transaction & transaction1) begin
if((status == WRITE_CONDITION) && NACK) round = (ROUND_LIMIT - 1);
else round = round + 1;
end
if(!transaction && round <= ROUND_LIMIT) begin
START_BIT <= 1;
case(round)
0 : begin
status <= START_CONDITION;
end
1 : begin
DATA_OUT = {SLAVE_ADDR[6:0],1'b1};
status <= WRITE_CONDITION;
end
2 : begin
status <= READ_CONDITION;
end
3 : begin
status <= STOP_CONDITION;
end
default : begin
status <= 5;
end
endcase
end
end
always @(posedge CLK or negedge RST) if(!RST) begin
RW = 0;
SDA_OUT <= 1;
SCL_OUT = 1;
DIV_CLK <= 0;
pos <= 0;
transaction <= 0;
DATA_IN <= 8'h0;
ACK <= 0;
end else begin
if(!transaction && START_BIT) begin
transaction <= 1;
DIV_CLK <= 0;
pos <= 0;
end else if(transaction) begin
case(status)
START_CONDITION : begin
RW = 0;
if((!SCL_OUT|!SDA_OUT) & (DIV_CLK == 0)) begin
SCL_OUT <= 1;
SDA_OUT <= 1;
end else begin
DIV_CLK <= DIV_CLK + 1;
if(DIV_CLK == (DIV_CLK_LIMIT/2)) SDA_OUT <= 0;
else if (DIV_CLK == DIV_CLK_LIMIT) begin
SCL_OUT = ~SCL_OUT;
DIV_CLK <= 0;
transaction = 0;
end
end
end
STOP_CONDITION : begin
RW = 0;
if((SCL_OUT | SDA_OUT) & (DIV_CLK == 0)) begin
SCL_OUT = 0;
SDA_OUT <= 0;
end else begin
DIV_CLK <= DIV_CLK + 1;
if(DIV_CLK == (DIV_CLK_LIMIT/2)) SCL_OUT = 1;
else if (DIV_CLK == DIV_CLK_LIMIT) begin
SDA_OUT <= 1;
DIV_CLK <= 0;
transaction <= 0;
end
end
end
READ_CONDITION : begin
DIV_CLK <= DIV_CLK + 1;
if(SCL_OUT && pos < 8) begin
RW = 1;
DATA_IN[pos] <= SDA_IN;
end else if(!SCL_OUT && pos == 8) begin
RW = 0;
SDA_OUT <= 0;
end else if(!SCL_OUT && pos > 8) begin
pos <= 0;
transaction <= 0;
RW = 1;
end
if(DIV_CLK == DIV_CLK_LIMIT) begin
DIV_CLK <= 0;
SCL_OUT = ~SCL_OUT;
if(!SCL_OUT) pos <= pos + 1;
end
end
WRITE_CONDITION : begin
DIV_CLK <= DIV_CLK + 1;
if(!SCL_OUT) begin
RW = 0;
if(pos < 8) SDA_OUT <= DATA_OUT[pos];
else if(pos == 8) RW = 1;
else begin
pos <= 0;
transaction <= 0;
RW = 1;
end
end else if(SCL_OUT && pos == 8) begin
RW = 1;
if(SDA_IN) ACK <= 0;
else ACK <= 1;
end
if(DIV_CLK == DIV_CLK_LIMIT) begin
DIV_CLK <= 0;
SCL_OUT = ~SCL_OUT;
if(!SCL_OUT) pos <= pos + 1;
end
end
default : begin
RW = 0;
SDA_OUT <= 1;
SCL_OUT = 1;
DIV_CLK <= 0;
pos <= 0;
transaction <= 0;
ACK <= 0;
end
endcase
end
end
endmodule | module FPGA_I2C(CLK,RST,SCL,SDA
,transaction,START_BIT,status,pos,ACK,DATA_OUT,DATA_IN,round); |
input CLK;
input RST;
inout wire SCL;
inout wire SDA;
wire SCL_IN;
reg SCL_OUT;
reg MS;
wire SDA_IN;
reg SDA_OUT;
reg RW;
assign SDA = (RW ? 8'bz : SDA_OUT);
assign SDA_IN = (RW ? SDA : 8'bz);
assign SCL = (MS ? SCL_OUT : 8'bz);
assign SCL_IN = (MS ? 8'bz : SCL);
output reg [0:7] DATA_OUT;
output reg [0:7] DATA_IN;
output reg [3:0] pos;
output reg [3:0] status;
output reg transaction;
reg transaction1,transaction2;
output reg START_BIT;
output reg ACK;
wire NACK;
assign NACK = ~ACK;
integer DIV_CLK;
parameter DIV_CLK_LIMIT = 62;
parameter START_CONDITION = 0,
STOP_CONDITION = 1,
READ_CONDITION = 2,
WRITE_CONDITION = 3;
parameter ROUND_LIMIT = 4;
reg [6:0] SLAVE_ADDR;
output integer round;
integer count;
initial begin
MS = 1;
RW = 0;
SDA_OUT = 1;
SCL_OUT = 1;
DIV_CLK = 0;
pos = 0;
transaction = 0;
START_BIT = 0;
ACK = 0;
DATA_IN = 8'h0;
DATA_OUT = 8'h0;
SLAVE_ADDR = 7'h26;
round = 0;
count = 0;
end
always @(posedge CLK) begin
transaction1 <= transaction;
end
always @(posedge CLK or negedge RST) if(!RST) begin
round = 0;
START_BIT <= 0;
status <= START_CONDITION;
count <= 0;
end else begin
if(START_BIT) START_BIT <= 0;
if(status == 5) begin
count <= count + 1;
if(count == 5_000_000) begin
round = 0;
count <= 0;
end
end
if(!transaction & transaction1) begin
if((status == WRITE_CONDITION) && NACK) round = (ROUND_LIMIT - 1);
else round = round + 1;
end
if(!transaction && round <= ROUND_LIMIT) begin
START_BIT <= 1;
case(round)
0 : begin
status <= START_CONDITION;
end
1 : begin
DATA_OUT = {SLAVE_ADDR[6:0],1'b1};
status <= WRITE_CONDITION;
end
2 : begin
status <= READ_CONDITION;
end
3 : begin
status <= STOP_CONDITION;
end
default : begin
status <= 5;
end
endcase
end
end
always @(posedge CLK or negedge RST) if(!RST) begin
RW = 0;
SDA_OUT <= 1;
SCL_OUT = 1;
DIV_CLK <= 0;
pos <= 0;
transaction <= 0;
DATA_IN <= 8'h0;
ACK <= 0;
end else begin
if(!transaction && START_BIT) begin
transaction <= 1;
DIV_CLK <= 0;
pos <= 0;
end else if(transaction) begin
case(status)
START_CONDITION : begin
RW = 0;
if((!SCL_OUT|!SDA_OUT) & (DIV_CLK == 0)) begin
SCL_OUT <= 1;
SDA_OUT <= 1;
end else begin
DIV_CLK <= DIV_CLK + 1;
if(DIV_CLK == (DIV_CLK_LIMIT/2)) SDA_OUT <= 0;
else if (DIV_CLK == DIV_CLK_LIMIT) begin
SCL_OUT = ~SCL_OUT;
DIV_CLK <= 0;
transaction = 0;
end
end
end
STOP_CONDITION : begin
RW = 0;
if((SCL_OUT | SDA_OUT) & (DIV_CLK == 0)) begin
SCL_OUT = 0;
SDA_OUT <= 0;
end else begin
DIV_CLK <= DIV_CLK + 1;
if(DIV_CLK == (DIV_CLK_LIMIT/2)) SCL_OUT = 1;
else if (DIV_CLK == DIV_CLK_LIMIT) begin
SDA_OUT <= 1;
DIV_CLK <= 0;
transaction <= 0;
end
end
end
READ_CONDITION : begin
DIV_CLK <= DIV_CLK + 1;
if(SCL_OUT && pos < 8) begin
RW = 1;
DATA_IN[pos] <= SDA_IN;
end else if(!SCL_OUT && pos == 8) begin
RW = 0;
SDA_OUT <= 0;
end else if(!SCL_OUT && pos > 8) begin
pos <= 0;
transaction <= 0;
RW = 1;
end
if(DIV_CLK == DIV_CLK_LIMIT) begin
DIV_CLK <= 0;
SCL_OUT = ~SCL_OUT;
if(!SCL_OUT) pos <= pos + 1;
end
end
WRITE_CONDITION : begin
DIV_CLK <= DIV_CLK + 1;
if(!SCL_OUT) begin
RW = 0;
if(pos < 8) SDA_OUT <= DATA_OUT[pos];
else if(pos == 8) RW = 1;
else begin
pos <= 0;
transaction <= 0;
RW = 1;
end
end else if(SCL_OUT && pos == 8) begin
RW = 1;
if(SDA_IN) ACK <= 0;
else ACK <= 1;
end
if(DIV_CLK == DIV_CLK_LIMIT) begin
DIV_CLK <= 0;
SCL_OUT = ~SCL_OUT;
if(!SCL_OUT) pos <= pos + 1;
end
end
default : begin
RW = 0;
SDA_OUT <= 1;
SCL_OUT = 1;
DIV_CLK <= 0;
pos <= 0;
transaction <= 0;
ACK <= 0;
end
endcase
end
end
endmodule | 0 |
5,119 | data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v | 113,268,705 | tb_I2C.v | v | 173 | 125 | [] | [] | [] | [(3, 173)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:171: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:13: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg[0:7] data_in;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:14: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg[0:7] data_out;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:16: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'sda_out\' generates 1 bits.\n : ... In instance tb_I2C\n assign sda = (rw ? 8\'bz : sda_out);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:16: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance tb_I2C\n assign sda = (rw ? 8\'bz : sda_out);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:17: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'sda\' generates 1 bits.\n : ... In instance tb_I2C\n assign sda_in = (rw ? sda : 8\'bz);\n ^\n%Warning-WIDTH: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n : ... In instance tb_I2C\n assign sda_in = (rw ? sda : 8\'bz);\n ^\n%Error: data/full_repos/permissive/113268705/FPGA_I2C/tb_I2C.v:52: Cannot find file containing module: \'FPGA_I2C\'\n FPGA_I2C i2c(.CLK(clk),.RST(rst),.SCL(scl),.SDA(sda)\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113268705/FPGA_I2C,data/full_repos/permissive/113268705/FPGA_I2C\n data/full_repos/permissive/113268705/FPGA_I2C,data/full_repos/permissive/113268705/FPGA_I2C.v\n data/full_repos/permissive/113268705/FPGA_I2C,data/full_repos/permissive/113268705/FPGA_I2C.sv\n FPGA_I2C\n FPGA_I2C.v\n FPGA_I2C.sv\n obj_dir/FPGA_I2C\n obj_dir/FPGA_I2C.v\n obj_dir/FPGA_I2C.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,554 | module | module tb_I2C;
reg clk;
wire scl;
wire sda;
reg rw;
wire sda_in;
reg sda_out;
reg[0:7] data_in;
reg[0:7] data_out;
assign sda = (rw ? 8'bz : sda_out);
assign sda_in = (rw ? sda : 8'bz);
reg[3:0] pos;
reg[1:0] status;
reg transaction;
reg sda_in1;
reg sda_in2;
reg scl1;
reg scl2;
reg ack;
wire nack;
reg start_con;
reg stop_con;
reg rst;
assign nack = ~ack;
parameter ADDRESS = 7'h26;
parameter READ_ADDRESS = 0;
parameter READ_DATA = 1;
parameter WRITE_DATA = 2;
wire MSTR;
wire MSSB;
wire[2:0] MSST;
wire[3:0] MSPS;
wire MSAK;
wire[7:0] MSDO,MSDI;
wire[31:0] round;
FPGA_I2C i2c(.CLK(clk),.RST(rst),.SCL(scl),.SDA(sda)
,.transaction(MSTR),.START_BIT(MSSB),.status(MSST),.pos(MSPS),.ACK(MSAK),.DATA_OUT(MSDO),.DATA_IN(MSDI),.round(round));
initial begin
data_out = 8'h4C;
data_in = 0;
sda_out = 1;
clk = 0;
rw = 1;
pos = 0;
status = 0;
transaction = 0;
sda_in2 = 1;
sda_in1 = 1;
scl2 = 0;
scl1 = 0;
ack = 0;
start_con = 0;
stop_con = 0;
rst = 0;
#10 rst = 1;
end
always @(posedge clk) begin
if(rw) begin
sda_in2 <= sda_in1;
sda_in1 <= sda_in;
end else begin
sda_in2 <= 1;
sda_in1 <= 1;
end
scl2 <= scl1;
scl1 <= scl;
end
always @(posedge clk) begin
if(scl && rw) begin
if(!sda_in1 & sda_in2) start_con <= 1;
else if(sda_in1 & !sda_in2) stop_con <= 1;
end
if(start_con && (scl1 ^ scl2)) begin
start_con <= 0;
transaction <= 1;
end
if(stop_con) begin
stop_con <= 0;
transaction <= 0;
end
end
always @(posedge clk) begin
if(!transaction) status <= 0;
else if(transaction) begin
case(status)
READ_ADDRESS : begin
if(scl && pos < 8) data_in[pos] <= sda_in;
else if(!scl && pos == 8) begin
rw = 0;
sda_out <= 0;
end else if(!scl && pos > 8) begin
pos <= 0;
if(data_in[0:6] == ADDRESS) begin
if(!data_in[7]) status <= READ_DATA;
else status <= WRITE_DATA;
end else status <= 3;
rw = 1;
end
end
READ_DATA : begin
if(scl && pos < 8) data_in[pos] <= sda_in;
else if(!scl && pos == 8)begin
rw = 0;
sda_out <= 0;
end else if(!scl && pos > 8) begin
pos <= 0;
status <= 3;
rw = 1;
end
end
WRITE_DATA : begin
if(!scl) begin
rw = 0;
if(pos < 8) sda_out <= data_out[pos];
else if(pos == 8) sda_out <= 0;
else begin
pos <= 0;
status <= 3;
end
end else if(scl && pos == 8)begin
rw = 1;
if(sda_in) ack <= 0;
else ack <= 1;
end
end
default : begin
rw = 1;
pos <= 0;
end
endcase
if(scl1^scl2) begin
if(!scl) pos <= pos + 1;
end
end
end
always #10 clk = ~clk;
endmodule | module tb_I2C; |
reg clk;
wire scl;
wire sda;
reg rw;
wire sda_in;
reg sda_out;
reg[0:7] data_in;
reg[0:7] data_out;
assign sda = (rw ? 8'bz : sda_out);
assign sda_in = (rw ? sda : 8'bz);
reg[3:0] pos;
reg[1:0] status;
reg transaction;
reg sda_in1;
reg sda_in2;
reg scl1;
reg scl2;
reg ack;
wire nack;
reg start_con;
reg stop_con;
reg rst;
assign nack = ~ack;
parameter ADDRESS = 7'h26;
parameter READ_ADDRESS = 0;
parameter READ_DATA = 1;
parameter WRITE_DATA = 2;
wire MSTR;
wire MSSB;
wire[2:0] MSST;
wire[3:0] MSPS;
wire MSAK;
wire[7:0] MSDO,MSDI;
wire[31:0] round;
FPGA_I2C i2c(.CLK(clk),.RST(rst),.SCL(scl),.SDA(sda)
,.transaction(MSTR),.START_BIT(MSSB),.status(MSST),.pos(MSPS),.ACK(MSAK),.DATA_OUT(MSDO),.DATA_IN(MSDI),.round(round));
initial begin
data_out = 8'h4C;
data_in = 0;
sda_out = 1;
clk = 0;
rw = 1;
pos = 0;
status = 0;
transaction = 0;
sda_in2 = 1;
sda_in1 = 1;
scl2 = 0;
scl1 = 0;
ack = 0;
start_con = 0;
stop_con = 0;
rst = 0;
#10 rst = 1;
end
always @(posedge clk) begin
if(rw) begin
sda_in2 <= sda_in1;
sda_in1 <= sda_in;
end else begin
sda_in2 <= 1;
sda_in1 <= 1;
end
scl2 <= scl1;
scl1 <= scl;
end
always @(posedge clk) begin
if(scl && rw) begin
if(!sda_in1 & sda_in2) start_con <= 1;
else if(sda_in1 & !sda_in2) stop_con <= 1;
end
if(start_con && (scl1 ^ scl2)) begin
start_con <= 0;
transaction <= 1;
end
if(stop_con) begin
stop_con <= 0;
transaction <= 0;
end
end
always @(posedge clk) begin
if(!transaction) status <= 0;
else if(transaction) begin
case(status)
READ_ADDRESS : begin
if(scl && pos < 8) data_in[pos] <= sda_in;
else if(!scl && pos == 8) begin
rw = 0;
sda_out <= 0;
end else if(!scl && pos > 8) begin
pos <= 0;
if(data_in[0:6] == ADDRESS) begin
if(!data_in[7]) status <= READ_DATA;
else status <= WRITE_DATA;
end else status <= 3;
rw = 1;
end
end
READ_DATA : begin
if(scl && pos < 8) data_in[pos] <= sda_in;
else if(!scl && pos == 8)begin
rw = 0;
sda_out <= 0;
end else if(!scl && pos > 8) begin
pos <= 0;
status <= 3;
rw = 1;
end
end
WRITE_DATA : begin
if(!scl) begin
rw = 0;
if(pos < 8) sda_out <= data_out[pos];
else if(pos == 8) sda_out <= 0;
else begin
pos <= 0;
status <= 3;
end
end else if(scl && pos == 8)begin
rw = 1;
if(sda_in) ack <= 0;
else ack <= 1;
end
end
default : begin
rw = 1;
pos <= 0;
end
endcase
if(scl1^scl2) begin
if(!scl) pos <= pos + 1;
end
end
end
always #10 clk = ~clk;
endmodule | 0 |
5,120 | data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI.v | 113,268,705 | FPGA_SPI.v | v | 64 | 64 | [] | [] | [] | [(1, 64)] | null | null | 1: b"%Error: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI.v:21: Cannot find file containing module: 'FPGA_SPI_MASTER'\nFPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER.v\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER.sv\n FPGA_SPI_MASTER\n FPGA_SPI_MASTER.v\n FPGA_SPI_MASTER.sv\n obj_dir/FPGA_SPI_MASTER\n obj_dir/FPGA_SPI_MASTER.v\n obj_dir/FPGA_SPI_MASTER.sv\n%Error: Exiting due to 1 error(s)\n" | 5,555 | module | module FPGA_SPI(CLK,SCLK,MOSI,MISO,SS);
input CLK;
inout wire SCLK,MOSI,SS,MISO;
wire[7:0] DATA_IN;
reg[7:0] DATA_OUT;
reg START_BIT;
wire END_BIT;
integer counter;
initial begin
DATA_OUT = 8'h0;
START_BIT = 0;
counter = 0;
end
FPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,
DATA_IN,DATA_OUT,START_BIT,END_BIT);
always @(posedge CLK) begin
counter = counter + 1;
if(counter == 50_000_000) begin
counter = 0;
end
end
always @(posedge CLK) begin
if(counter == 0) begin
START_BIT = 0;
end
if(END_BIT == 1) begin
START_BIT = 1;
end
end
always @(posedge SS) begin
DATA_OUT = DATA_OUT + 1;
end
endmodule | module FPGA_SPI(CLK,SCLK,MOSI,MISO,SS); |
input CLK;
inout wire SCLK,MOSI,SS,MISO;
wire[7:0] DATA_IN;
reg[7:0] DATA_OUT;
reg START_BIT;
wire END_BIT;
integer counter;
initial begin
DATA_OUT = 8'h0;
START_BIT = 0;
counter = 0;
end
FPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,
DATA_IN,DATA_OUT,START_BIT,END_BIT);
always @(posedge CLK) begin
counter = counter + 1;
if(counter == 50_000_000) begin
counter = 0;
end
end
always @(posedge CLK) begin
if(counter == 0) begin
START_BIT = 0;
end
if(END_BIT == 1) begin
START_BIT = 1;
end
end
always @(posedge SS) begin
DATA_OUT = DATA_OUT + 1;
end
endmodule | 0 |
5,121 | data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_MASTER.v | 113,268,705 | FPGA_SPI_MASTER.v | v | 66 | 82 | [] | [] | [] | [(1, 66)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_MASTER.v:9: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] DATA_OUT;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_MASTER.v:10: Little bit endian vector: MSB < LSB of bit range: 0:7\noutput reg[0:7] DATA_IN;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,556 | module | module FPGA_SPI_MASTER(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,START_BIT,END_BIT);
integer i;
input wire CLK;
output reg SCLK,MOSI,SS;
input MISO;
input [0:7] DATA_OUT;
output reg[0:7] DATA_IN;
input wire START_BIT;
output reg END_BIT;
integer DIV_CLK;
parameter DIV_CLK_Limit = 24;
initial begin
i = 0;
SCLK = 0;
MOSI = 1;
SS = 1;
DATA_IN = 0;
END_BIT = 0;
DIV_CLK = 0;
end
always @(posedge CLK) begin
if(START_BIT == 0) begin
SS = 0;
DIV_CLK = DIV_CLK + 1;
if(SCLK == 0) begin
MOSI = DATA_OUT[i];
end
if(DIV_CLK == DIV_CLK_Limit) begin
DIV_CLK = 0;
SCLK = ~SCLK;
if(SCLK == 1) begin
DATA_IN[i] = MISO;
i = i + 1;
end else begin
if(i == 8) begin
i = 0;
END_BIT = 1;
end
end
end
end else begin
SCLK = 0;
DIV_CLK = 0;
MOSI = 1;
i = 0;
end
if(END_BIT == 1 && START_BIT == 1) begin
SS = 1;
END_BIT = 0;
end
end
endmodule | module FPGA_SPI_MASTER(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,START_BIT,END_BIT); |
integer i;
input wire CLK;
output reg SCLK,MOSI,SS;
input MISO;
input [0:7] DATA_OUT;
output reg[0:7] DATA_IN;
input wire START_BIT;
output reg END_BIT;
integer DIV_CLK;
parameter DIV_CLK_Limit = 24;
initial begin
i = 0;
SCLK = 0;
MOSI = 1;
SS = 1;
DATA_IN = 0;
END_BIT = 0;
DIV_CLK = 0;
end
always @(posedge CLK) begin
if(START_BIT == 0) begin
SS = 0;
DIV_CLK = DIV_CLK + 1;
if(SCLK == 0) begin
MOSI = DATA_OUT[i];
end
if(DIV_CLK == DIV_CLK_Limit) begin
DIV_CLK = 0;
SCLK = ~SCLK;
if(SCLK == 1) begin
DATA_IN[i] = MISO;
i = i + 1;
end else begin
if(i == 8) begin
i = 0;
END_BIT = 1;
end
end
end
end else begin
SCLK = 0;
DIV_CLK = 0;
MOSI = 1;
i = 0;
end
if(END_BIT == 1 && START_BIT == 1) begin
SS = 1;
END_BIT = 0;
end
end
endmodule | 0 |
5,122 | data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v | 113,268,705 | FPGA_SPI_SLAVE.v | v | 40 | 78 | [] | [] | [] | [(1, 40)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v:7: Little bit endian vector: MSB < LSB of bit range: 0:7\n input[0:7] DATA_OUT;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n output reg[0:7] DATA_IN;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,557 | module | module FPGA_SPI_SLAVE(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,END_BIT);
input wire CLK;
input SCLK,MOSI,SS;
output reg MISO;
input[0:7] DATA_OUT;
output reg[0:7] DATA_IN;
output wire END_BIT;
reg[2:0] Count;
initial begin
Count = 0;
DATA_IN = 8'h0;
MISO = 1;
end
assign END_BIT = Count != 0;
always @(posedge SCLK or posedge SS) if(SS) begin
DATA_IN <= 0;
end else begin
DATA_IN[Count] <= MOSI;
end
always @(negedge SCLK or posedge SS) if(SS) begin
Count = 0;
end else begin
Count = Count + 1;
end
always @(negedge SCLK or negedge SS) if(!SS) begin
MISO <= DATA_OUT[Count];
end
endmodule | module FPGA_SPI_SLAVE(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,END_BIT); |
input wire CLK;
input SCLK,MOSI,SS;
output reg MISO;
input[0:7] DATA_OUT;
output reg[0:7] DATA_IN;
output wire END_BIT;
reg[2:0] Count;
initial begin
Count = 0;
DATA_IN = 8'h0;
MISO = 1;
end
assign END_BIT = Count != 0;
always @(posedge SCLK or posedge SS) if(SS) begin
DATA_IN <= 0;
end else begin
DATA_IN[Count] <= MOSI;
end
always @(negedge SCLK or posedge SS) if(SS) begin
Count = 0;
end else begin
Count = Count + 1;
end
always @(negedge SCLK or negedge SS) if(!SS) begin
MISO <= DATA_OUT[Count];
end
endmodule | 0 |
5,123 | data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v | 113,268,705 | tb_FPGA_SPI.v | v | 92 | 70 | [] | [] | [] | [(3, 92)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:65: Unsupported: Ignoring delay on this delayed statement.\n #500 ss = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:45: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] data_in;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:46: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg[0:7] data_out;\n ^\n%Error: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:90: Cannot find file containing module: \'FPGA_SPI\'\n FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI.v\n data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI.sv\n FPGA_SPI\n FPGA_SPI.v\n FPGA_SPI.sv\n obj_dir/FPGA_SPI\n obj_dir/FPGA_SPI.v\n obj_dir/FPGA_SPI.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,558 | module | module tb_FPGA_SPI;
reg clk;
reg sclk;
reg mosi,ss;
wire miso;
integer div_clk,i;
reg [0:7] data_in;
reg[0:7] data_out;
initial begin
clk = 0;
sclk = 0;
mosi = 0;
ss = 1;
div_clk = 0;
data_in = 8'h0;
data_out = 8'h0;
i = 0;
end
always @(posedge clk) begin
if(ss==1) begin
div_clk = 0;
sclk = 0;
data_out <= data_in;
#500 ss = 0;
end
div_clk = div_clk + 1;
if(sclk == 0) begin
mosi = data_out[i];
end
if(div_clk == 5) begin
div_clk = 0;
sclk = ~sclk;
if(sclk == 1) begin
data_in[i] = miso;
i = i + 1;
end else begin
if(i == 8) begin
i = 0;
ss = 1;
end
end
end
end
always begin
#10 clk = ~clk;
end
FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));
endmodule | module tb_FPGA_SPI; |
reg clk;
reg sclk;
reg mosi,ss;
wire miso;
integer div_clk,i;
reg [0:7] data_in;
reg[0:7] data_out;
initial begin
clk = 0;
sclk = 0;
mosi = 0;
ss = 1;
div_clk = 0;
data_in = 8'h0;
data_out = 8'h0;
i = 0;
end
always @(posedge clk) begin
if(ss==1) begin
div_clk = 0;
sclk = 0;
data_out <= data_in;
#500 ss = 0;
end
div_clk = div_clk + 1;
if(sclk == 0) begin
mosi = data_out[i];
end
if(div_clk == 5) begin
div_clk = 0;
sclk = ~sclk;
if(sclk == 1) begin
data_in[i] = miso;
i = i + 1;
end else begin
if(i == 8) begin
i = 0;
ss = 1;
end
end
end
end
always begin
#10 clk = ~clk;
end
FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));
endmodule | 0 |
5,124 | data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v | 113,268,705 | tb_UART.v | v | 55 | 177 | [] | [] | [] | null | line:23: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:23: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:22: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:25: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:26: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:27: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:28: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:30: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:31: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:32: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:33: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:35: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:37: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:39: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:40: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:41: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:42: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:44: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:45: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:46: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:47: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:49: Unsupported: Ignoring delay on this delayed statement.\n #52080 RX = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:16: Cannot find file containing module: \'UART\'\n UART uart(.CLK(clk),.TX(TX),.RX(RX));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART\n data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART.v\n data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART.sv\n UART\n UART.v\n UART.sv\n obj_dir/UART\n obj_dir/UART.v\n obj_dir/UART.sv\n%Error: Exiting due to 1 error(s), 22 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,559 | module | module tb_UART;
reg clk;
reg RX;
wire TX;
UART uart(.CLK(clk),.TX(TX),.RX(RX));
initial begin
clk = 0;
RX = 1;
#100
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
end
always
#10 clk = ~clk;
endmodule | module tb_UART; |
reg clk;
reg RX;
wire TX;
UART uart(.CLK(clk),.TX(TX),.RX(RX));
initial begin
clk = 0;
RX = 1;
#100
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 0;
#52080 RX = 0;
#52080 RX = 1;
#52080 RX = 1;
end
always
#10 clk = ~clk;
endmodule | 0 |
5,125 | data/full_repos/permissive/113268705/FPGA_UART/UART.v | 113,268,705 | UART.v | v | 133 | 99 | [] | [] | [] | [(1, 133)] | null | data/verilator_xmls/1832aebe-b61b-4b71-b628-31a9b0f1f7eb.xml | null | 5,560 | module | module UART(CLK,TX,RX);
input CLK;
input RX;
output reg TX;
reg[7:0] RXD,TXD;
parameter DATA_BIT = 8;
parameter PARITY_BIT = 0;
parameter STOP_BIT = 1;
parameter BAUDRATE = 2604;
reg[3:0] TX_Status,RX_Status;
integer TX_Count,RX_Count;
reg TX_Start;
reg TX_Transaction, RX_Transaction;
reg BUFF;
integer timer;
initial begin
BUFF = 0;
timer = 0;
TX_Count = 0;
RX_Count = 0;
TX_Start = 1;
TX_Transaction = 1;
RX_Transaction = 1;
TX = 1;
TX_Status = 0;
RX_Status = 0;
TXD = 8'h00;
RXD = 8'h00;
end
always @(posedge CLK) begin
if(RX_Transaction) TXD <= RXD;
else begin
BUFF = 1;
end
if(RX_Transaction && BUFF) begin
TX_Start = 0;
BUFF = 0;
end else if(!BUFF) begin
TX_Start = 1;
end
end
always @(posedge CLK) begin
if(TX_Transaction && !TX_Start) begin
TX_Transaction = 0;
TX = 0;
TX_Status = 1;
TX_Count = 0;
end else if(!TX_Transaction) begin
if(TX_Count == BAUDRATE) begin
if(TX_Status > 0 && TX_Status < 1 + DATA_BIT) begin
TX = TXD[TX_Status -1];
end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT) begin
end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
TX = 1;
end else begin
TX = 1;
TX_Transaction = 1;
end
TX_Count = 0;
TX_Status = TX_Status + 1;
end
TX_Count = TX_Count + 1;
end
end
always @(posedge CLK) begin
if(RX_Transaction && !RX) begin
RX_Transaction = 0;
RX_Status = 1;
RX_Count = 0;
end else if(!RX_Transaction) begin
if(RX_Count == BAUDRATE) begin
if(RX_Status > 0 && RX_Status < 1 + DATA_BIT) begin
RXD[RX_Status - 1] = RX;
RX_Status = RX_Status + 1;
end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT) begin
end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
if(RX) begin
RX_Status = RX_Status + 1;
end else begin
RX_Transaction = 1;
RX_Count = 0;
end
end else begin
RX_Transaction = 1;
RX_Count = 0;
end
RX_Count = 0;
end
RX_Count = RX_Count + 1;
end
end
endmodule | module UART(CLK,TX,RX); |
input CLK;
input RX;
output reg TX;
reg[7:0] RXD,TXD;
parameter DATA_BIT = 8;
parameter PARITY_BIT = 0;
parameter STOP_BIT = 1;
parameter BAUDRATE = 2604;
reg[3:0] TX_Status,RX_Status;
integer TX_Count,RX_Count;
reg TX_Start;
reg TX_Transaction, RX_Transaction;
reg BUFF;
integer timer;
initial begin
BUFF = 0;
timer = 0;
TX_Count = 0;
RX_Count = 0;
TX_Start = 1;
TX_Transaction = 1;
RX_Transaction = 1;
TX = 1;
TX_Status = 0;
RX_Status = 0;
TXD = 8'h00;
RXD = 8'h00;
end
always @(posedge CLK) begin
if(RX_Transaction) TXD <= RXD;
else begin
BUFF = 1;
end
if(RX_Transaction && BUFF) begin
TX_Start = 0;
BUFF = 0;
end else if(!BUFF) begin
TX_Start = 1;
end
end
always @(posedge CLK) begin
if(TX_Transaction && !TX_Start) begin
TX_Transaction = 0;
TX = 0;
TX_Status = 1;
TX_Count = 0;
end else if(!TX_Transaction) begin
if(TX_Count == BAUDRATE) begin
if(TX_Status > 0 && TX_Status < 1 + DATA_BIT) begin
TX = TXD[TX_Status -1];
end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT) begin
end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
TX = 1;
end else begin
TX = 1;
TX_Transaction = 1;
end
TX_Count = 0;
TX_Status = TX_Status + 1;
end
TX_Count = TX_Count + 1;
end
end
always @(posedge CLK) begin
if(RX_Transaction && !RX) begin
RX_Transaction = 0;
RX_Status = 1;
RX_Count = 0;
end else if(!RX_Transaction) begin
if(RX_Count == BAUDRATE) begin
if(RX_Status > 0 && RX_Status < 1 + DATA_BIT) begin
RXD[RX_Status - 1] = RX;
RX_Status = RX_Status + 1;
end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT) begin
end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
if(RX) begin
RX_Status = RX_Status + 1;
end else begin
RX_Transaction = 1;
RX_Count = 0;
end
end else begin
RX_Transaction = 1;
RX_Count = 0;
end
RX_Count = 0;
end
RX_Count = RX_Count + 1;
end
end
endmodule | 0 |
5,128 | data/full_repos/permissive/113344787/src/decimal/bcd_tb.v | 113,344,787 | bcd_tb.v | v | 42 | 51 | [] | [] | [] | [(1, 41)] | null | null | 1: b'%Error: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("src/decimal/bcd_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/bcd_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,565 | module | module bcd_tb;
reg [13:0] number;
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
bcd u_bcd (
.number (number),
.thousands (thousands),
.hundreds (hundreds),
.tens (tens),
.ones (ones)
);
integer i;
initial
begin
$dumpfile ("src/decimal/bcd_tb.vcd");
$dumpvars;
for (i = 5; i < 15; i = i + 1) begin
#1
number = i;
end
for (i = 95; i < 105; i = i + 1) begin
#1
number = i;
end
for (i = 995; i < 1005; i = i + 1) begin
#1
number = i;
end
for (i = 9995; i <= 9999; i = i + 1) begin
#1
number = i;
end
#10
number = 0;
end
endmodule | module bcd_tb; |
reg [13:0] number;
wire [3:0] thousands;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
bcd u_bcd (
.number (number),
.thousands (thousands),
.hundreds (hundreds),
.tens (tens),
.ones (ones)
);
integer i;
initial
begin
$dumpfile ("src/decimal/bcd_tb.vcd");
$dumpvars;
for (i = 5; i < 15; i = i + 1) begin
#1
number = i;
end
for (i = 95; i < 105; i = i + 1) begin
#1
number = i;
end
for (i = 995; i < 1005; i = i + 1) begin
#1
number = i;
end
for (i = 9995; i <= 9999; i = i + 1) begin
#1
number = i;
end
#10
number = 0;
end
endmodule | 3 |
5,130 | data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v | 113,344,787 | dec_to_seg.v | v | 24 | 40 | [] | [] | [] | [(1, 23)] | null | null | 1: b"%Error: data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v:6: Duplicate declaration of signal: 'seg'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [6:0] seg;\n ^~~\n data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v:3: ... Location of original declaration\n output [6:0] seg\n ^~~\n%Error: Exiting due to 1 error(s)\n" | 5,567 | module | module dec_to_seg(
input [3:0] dec_digit,
output [6:0] seg
);
reg [6:0] seg;
always @(dec_digit)
case (dec_digit)
4'h0: seg = 7'b0111111;
4'h1: seg = 7'b0000110;
4'h2: seg = 7'b1011011;
4'h3: seg = 7'b1001111;
4'h4: seg = 7'b1100110;
4'h5: seg = 7'b1101101;
4'h6: seg = 7'b1111101;
4'h7: seg = 7'b0000111;
4'h8: seg = 7'b1111111;
4'h9: seg = 7'b1100111;
default: seg = 7'b1111001;
endcase
endmodule | module dec_to_seg(
input [3:0] dec_digit,
output [6:0] seg
); |
reg [6:0] seg;
always @(dec_digit)
case (dec_digit)
4'h0: seg = 7'b0111111;
4'h1: seg = 7'b0000110;
4'h2: seg = 7'b1011011;
4'h3: seg = 7'b1001111;
4'h4: seg = 7'b1100110;
4'h5: seg = 7'b1101101;
4'h6: seg = 7'b1111101;
4'h7: seg = 7'b0000111;
4'h8: seg = 7'b1111111;
4'h9: seg = 7'b1100111;
default: seg = 7'b1111001;
endcase
endmodule | 3 |
5,131 | data/full_repos/permissive/113344787/src/decimal/dec_to_seg_tb.v | 113,344,787 | dec_to_seg_tb.v | v | 22 | 53 | [] | [] | [] | [(1, 21)] | null | null | 1: b'%Error: data/full_repos/permissive/113344787/src/decimal/dec_to_seg_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("src/decimal/dec_to_seg_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113344787/src/decimal/dec_to_seg_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/decimal/dec_to_seg_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,568 | module | module dec_to_seg_tb;
reg [3:0] dec_digit;
wire [6:0] seg;
dec_to_seg u_dec_to_seg (
.dec_digit (dec_digit),
.seg (seg)
);
integer i;
initial
begin
$dumpfile ("src/decimal/dec_to_seg_tb.vcd");
$dumpvars;
for (i = 0; i <= 12; i = i + 1) begin
#10
dec_digit = i;
end
end
endmodule | module dec_to_seg_tb; |
reg [3:0] dec_digit;
wire [6:0] seg;
dec_to_seg u_dec_to_seg (
.dec_digit (dec_digit),
.seg (seg)
);
integer i;
initial
begin
$dumpfile ("src/decimal/dec_to_seg_tb.vcd");
$dumpvars;
for (i = 0; i <= 12; i = i + 1) begin
#10
dec_digit = i;
end
end
endmodule | 3 |
5,134 | data/full_repos/permissive/113344787/src/hex/hex_to_seg.v | 113,344,787 | hex_to_seg.v | v | 28 | 36 | [] | [] | [] | [(1, 27)] | null | null | 1: b"%Error: data/full_repos/permissive/113344787/src/hex/hex_to_seg.v:6: Duplicate declaration of signal: 'seg'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [6:0] seg;\n ^~~\n data/full_repos/permissive/113344787/src/hex/hex_to_seg.v:3: ... Location of original declaration\n output [6:0] seg\n ^~~\n%Error: Exiting due to 1 error(s)\n" | 5,571 | module | module hex_to_seg(
input [3:0] hex_digit,
output [6:0] seg
);
reg [6:0] seg;
always @(hex_digit)
case (hex_digit)
4'h0: seg = 7'b0111111;
4'h1: seg = 7'b0000110;
4'h2: seg = 7'b1011011;
4'h3: seg = 7'b1001111;
4'h4: seg = 7'b1100110;
4'h5: seg = 7'b1101101;
4'h6: seg = 7'b1111101;
4'h7: seg = 7'b0000111;
4'h8: seg = 7'b1111111;
4'h9: seg = 7'b1100111;
4'ha: seg = 7'b1110111;
4'hb: seg = 7'b1111100;
4'hc: seg = 7'b0111001;
4'hd: seg = 7'b1011110;
4'he: seg = 7'b1111001;
4'hf: seg = 7'b1110001;
endcase
endmodule | module hex_to_seg(
input [3:0] hex_digit,
output [6:0] seg
); |
reg [6:0] seg;
always @(hex_digit)
case (hex_digit)
4'h0: seg = 7'b0111111;
4'h1: seg = 7'b0000110;
4'h2: seg = 7'b1011011;
4'h3: seg = 7'b1001111;
4'h4: seg = 7'b1100110;
4'h5: seg = 7'b1101101;
4'h6: seg = 7'b1111101;
4'h7: seg = 7'b0000111;
4'h8: seg = 7'b1111111;
4'h9: seg = 7'b1100111;
4'ha: seg = 7'b1110111;
4'hb: seg = 7'b1111100;
4'hc: seg = 7'b0111001;
4'hd: seg = 7'b1011110;
4'he: seg = 7'b1111001;
4'hf: seg = 7'b1110001;
endcase
endmodule | 3 |
5,135 | data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v | 113,344,787 | hex_to_seg_tb.v | v | 22 | 49 | [] | [] | [] | [(1, 21)] | null | null | 1: b'%Error: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("src/hex/hex_to_seg_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 5,572 | module | module hex_to_seg_tb;
reg [3:0] hex_digit;
wire [6:0] seg;
hex_to_seg u_hex_to_seg (
.hex_digit (hex_digit),
.seg (seg)
);
integer i;
initial
begin
$dumpfile ("src/hex/hex_to_seg_tb.vcd");
$dumpvars;
for (i = 0; i < 17; i = i + 1) begin
#10
hex_digit = i;
end
end
endmodule | module hex_to_seg_tb; |
reg [3:0] hex_digit;
wire [6:0] seg;
hex_to_seg u_hex_to_seg (
.hex_digit (hex_digit),
.seg (seg)
);
integer i;
initial
begin
$dumpfile ("src/hex/hex_to_seg_tb.vcd");
$dumpvars;
for (i = 0; i < 17; i = i + 1) begin
#10
hex_digit = i;
end
end
endmodule | 3 |
5,139 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v | 113,454,857 | axi_wr_fifo.v | v | 301 | 142 | [] | [] | [] | [(13, 300)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:104: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance axi_wr_fifo\n wr_pt <= 4\'h0 ;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:105: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance axi_wr_fifo\n rd_pt <= 4\'h0 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:136: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 3 bits.\n : ... In instance axi_wr_fifo\nwire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator SUB expects 34 bits on the LHS, but LHS\'s REPLICATE generates 30 bits.\n : ... In instance axi_wr_fifo\nwire [AW :0] next_stop_address = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator SUB expects 34 bits on the RHS, but RHS\'s SEL generates 30 bits.\n : ... In instance axi_wr_fifo\nwire [AW :0] next_stop_address = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s SUB generates 34 bits.\n : ... In instance axi_wr_fifo\nwire [AW :0] next_stop_address = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:170: Operator ADD expects 34 bits on the LHS, but LHS\'s REPLICATE generates 31 bits.\n : ... In instance axi_wr_fifo\nwire [AW+1:0] boundary_condition = {1\'b0,next_address[AW:3]} + {{AW-FW+1{1\'h0}},fill_lvl} - {1\'b0,sys_stop_addr_r[AW-1:3]} ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:170: Operator SUB expects 34 bits on the RHS, but RHS\'s REPLICATE generates 30 bits.\n : ... In instance axi_wr_fifo\nwire [AW+1:0] boundary_condition = {1\'b0,next_address[AW:3]} + {{AW-FW+1{1\'h0}},fill_lvl} - {1\'b0,sys_stop_addr_r[AW-1:3]} ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'fill_lvl\' generates 6 bits.\n : ... In instance axi_wr_fifo\n single_burst <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'dat_cnt\' generates 4 bits.\n : ... In instance axi_wr_fifo\n single_burst <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:193: Operator GTE expects 6 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n : ... In instance axi_wr_fifo\nassign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1\'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl \n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:193: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'dat_cnt\' generates 4 bits.\n : ... In instance axi_wr_fifo\nassign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1\'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl \n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:208: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance axi_wr_fifo\n if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:208: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance axi_wr_fifo\n if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin \n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:207: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance axi_wr_fifo\n if (boundary_cross[1:0] || fill_lvl[FW:4]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:207: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s SEL generates 2 bits.\n : ... In instance axi_wr_fifo\n if (boundary_cross[1:0] || fill_lvl[FW:4]) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:237: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'dat_cnt\' generates 4 bits.\n : ... In instance axi_wr_fifo\n else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:253: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n : ... In instance axi_wr_fifo\nassign pop = (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o)) \n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:254: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n : ... In instance axi_wr_fifo\n && axi_wrdy_i && axi_wvalid_o && fill_lvl) ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:268: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n : ... In instance axi_wr_fifo\n ( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:296: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_address\' generates 33 bits.\n : ... In instance axi_wr_fifo\nassign stat_cur_addr_o = next_address ; \n ^\n%Error: Exiting due to 21 warning(s)\n' | 5,577 | module | module axi_wr_fifo #(
parameter DW = 64 ,
parameter AW = 32 ,
parameter FW = 5 ,
parameter SW = DW >> 3
)
(
input axi_clk_i ,
input axi_rstn_i ,
output reg [ AW-1: 0] axi_waddr_o ,
output reg [ DW-1: 0] axi_wdata_o ,
output reg [ SW-1: 0] axi_wsel_o ,
output reg axi_wvalid_o ,
output reg [ 4-1: 0] axi_wlen_o ,
output reg axi_wfixed_o ,
input axi_werr_i ,
input axi_wrdy_i ,
input [ DW-1: 0] wr_data_i ,
input wr_val_i ,
input [ AW-1: 0] ctrl_start_addr_i ,
input [ AW-1: 0] ctrl_stop_addr_i ,
input [ 4-1: 0] ctrl_trig_size_i ,
input ctrl_wrap_i ,
input ctrl_clr_i ,
output reg stat_overflow_o ,
output [ AW-1: 0] stat_cur_addr_o ,
output reg stat_write_data_o
);
reg [ FW-1: 0] wr_pt ;
reg [ FW-1: 0] rd_pt ;
reg [ FW : 0] fill_lvl ;
reg [ DW-1: 0] fifo[(1<<FW)-1:0] ;
reg data_in_reg ;
reg clear ;
reg [ 4-1: 0] dat_cnt ;
reg [ AW : 0] next_address ;
reg fifo_flush ;
reg [ AW-1: 0] sys_start_addr_r ;
reg [ AW-1: 0] sys_stop_addr_r ;
reg [ 4-1: 0] sys_trig_size_r ;
wire push = wr_val_i && !fill_lvl[FW] ;
wire pop ;
wire new_burst ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_overflow_o <= 'h0 ;
end
else begin
stat_overflow_o <= fill_lvl[FW] && wr_val_i;
end
end
reg clear_do ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
clear <= 1'h1 ;
clear_do <= 1'b0 ;
end
else begin
if (ctrl_clr_i)
clear_do <= 1'b1 ;
else if (clear)
clear_do <= 1'b0 ;
clear <= clear_do && !axi_wvalid_o && !new_burst;
end
end
always @ (posedge axi_clk_i)
begin
if (clear) begin
wr_pt <= 4'h0 ;
rd_pt <= 4'h0 ;
end
else begin
if (push) begin
fifo[wr_pt] <= wr_data_i ;
wr_pt <= wr_pt + {{FW-1{1'b0}},1'b1} ;
end
if (pop) begin
axi_wdata_o <= fifo[rd_pt] ;
rd_pt <= rd_pt + {{FW-1{1'b0}},1'b1} ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
data_in_reg <= 'h0 ;
end
else begin
if (pop)
data_in_reg <= 1'b1 ;
else if ((axi_wrdy_i && axi_wvalid_o) || clear)
data_in_reg <= 1'b0 ;
end
end
wire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];
always @(posedge axi_clk_i)
begin
if (clear) begin
fill_lvl <= {FW+1{1'h0}} ;
fifo_flush <= 1'h0 ;
end
else begin
if (push && !pop)
fill_lvl <= fill_lvl + {{FW{1'b0}}, 1'h1} ;
else if(!push && pop)
fill_lvl <= fill_lvl - {{FW{1'b0}}, 1'h1} ;
if (fifo_flush_cond)
fifo_flush <= 1'b1 ;
else if (axi_wrdy_i)
fifo_flush <= 1'b0 ;
end
end
wire [8 :0] next_end_address = next_address[10:3] + {3'h0,fill_lvl} ;
wire [AW :0] next_stop_address = {1'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1'h0}},fill_lvl} ;
wire [AW+1:0] boundary_condition = {1'b0,next_address[AW:3]} + {{AW-FW+1{1'h0}},fill_lvl} - {1'b0,sys_stop_addr_r[AW-1:3]} ;
wire [2 :0] boundary_cross = {boundary_condition[AW+1], next_end_address[8],next_stop_address[AW]} ;
reg single_burst ;
reg single_burst_r ;
wire single_burst_posedge = !single_burst_r && single_burst;
always @(posedge axi_clk_i)
begin
if (clear) begin
single_burst <= 'h0 ;
single_burst_r <= 'h0 ;
end
else begin
single_burst <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;
single_burst_r <= single_burst ;
end
end
assign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl
|| single_burst_posedge)
&& !clear_do;
always @(posedge axi_clk_i)
begin
if (clear) begin
dat_cnt <= 4'h0 ;
axi_wsel_o <= {SW{1'b1}} ;
axi_wfixed_o <= 1'b0 ;
axi_wlen_o <= 4'h0 ;
end
else begin
if (new_burst && (next_address <= {1'b0,sys_stop_addr_r})) begin
if (boundary_cross[1:0] || fill_lvl[FW:4]) begin
if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin
dat_cnt <= 4'hF ;
axi_wlen_o <= 4'hF ;
end
else begin
if (boundary_cross[2]) begin
dat_cnt <= 4'hF - next_address[6:3];
axi_wlen_o <= 4'hF - next_address[6:3];
end
else begin
dat_cnt <= sys_stop_addr_r[6:3] - next_address[6:3];
axi_wlen_o <= sys_stop_addr_r[6:3] - next_address[6:3];
end
end
end
else begin
if (fifo_flush || fifo_flush_cond) begin
dat_cnt <= fill_lvl[3:0] - 4'h1 ;
axi_wlen_o <= fill_lvl[3:0] - 4'h1 ;
end
else begin
dat_cnt <= fill_lvl[3:0] ;
axi_wlen_o <= fill_lvl[3:0] ;
end
end
end
else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin
dat_cnt <= dat_cnt - 4'h1;
axi_wlen_o <= axi_wlen_o - 4'h1;
end
end
end
wire [4-1: 0] aaaa = 4'hF - next_address[6:3];
wire [4-1: 0] bbbb = sys_stop_addr_r[6:3] - next_address[6:3];
wire [4-1: 0] cccc = fill_lvl[3:0] - 4'h1;
wire [4-1: 0] dddd = fill_lvl[3:0];
assign pop = (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o))
&& axi_wrdy_i && axi_wvalid_o && fill_lvl) ;
always @(posedge axi_clk_i)
begin
if (clear) begin
axi_wvalid_o <= 1'h0 ;
axi_waddr_o <= ctrl_start_addr_i ;
next_address <= {1'b0,ctrl_start_addr_i} ;
sys_start_addr_r <= ctrl_start_addr_i ;
sys_stop_addr_r <= ctrl_stop_addr_i ;
sys_trig_size_r <= ctrl_trig_size_i ;
end
else begin
if ((next_address <= {1'b0,sys_stop_addr_r}) &&
( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin
axi_wvalid_o <= 1'h1 ;
next_address <= next_address + DW/8 ;
axi_waddr_o <= next_address[AW-1:0] ;
end
else if (ctrl_wrap_i && new_burst && (axi_waddr_o==sys_stop_addr_r)) begin
axi_wvalid_o <= 1'h1 ;
next_address <= {1'b0,sys_start_addr_r} + DW/8 ;
axi_waddr_o <= sys_start_addr_r ;
end
else if (axi_wrdy_i) begin
axi_wvalid_o <= 1'h0 ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_write_data_o <= 'h0 ;
end
else begin
stat_write_data_o <= (next_address <= {1'b0,sys_stop_addr_r}) ;
end
end
assign stat_cur_addr_o = next_address ;
endmodule | module axi_wr_fifo #(
parameter DW = 64 ,
parameter AW = 32 ,
parameter FW = 5 ,
parameter SW = DW >> 3
)
(
input axi_clk_i ,
input axi_rstn_i ,
output reg [ AW-1: 0] axi_waddr_o ,
output reg [ DW-1: 0] axi_wdata_o ,
output reg [ SW-1: 0] axi_wsel_o ,
output reg axi_wvalid_o ,
output reg [ 4-1: 0] axi_wlen_o ,
output reg axi_wfixed_o ,
input axi_werr_i ,
input axi_wrdy_i ,
input [ DW-1: 0] wr_data_i ,
input wr_val_i ,
input [ AW-1: 0] ctrl_start_addr_i ,
input [ AW-1: 0] ctrl_stop_addr_i ,
input [ 4-1: 0] ctrl_trig_size_i ,
input ctrl_wrap_i ,
input ctrl_clr_i ,
output reg stat_overflow_o ,
output [ AW-1: 0] stat_cur_addr_o ,
output reg stat_write_data_o
); |
reg [ FW-1: 0] wr_pt ;
reg [ FW-1: 0] rd_pt ;
reg [ FW : 0] fill_lvl ;
reg [ DW-1: 0] fifo[(1<<FW)-1:0] ;
reg data_in_reg ;
reg clear ;
reg [ 4-1: 0] dat_cnt ;
reg [ AW : 0] next_address ;
reg fifo_flush ;
reg [ AW-1: 0] sys_start_addr_r ;
reg [ AW-1: 0] sys_stop_addr_r ;
reg [ 4-1: 0] sys_trig_size_r ;
wire push = wr_val_i && !fill_lvl[FW] ;
wire pop ;
wire new_burst ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_overflow_o <= 'h0 ;
end
else begin
stat_overflow_o <= fill_lvl[FW] && wr_val_i;
end
end
reg clear_do ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
clear <= 1'h1 ;
clear_do <= 1'b0 ;
end
else begin
if (ctrl_clr_i)
clear_do <= 1'b1 ;
else if (clear)
clear_do <= 1'b0 ;
clear <= clear_do && !axi_wvalid_o && !new_burst;
end
end
always @ (posedge axi_clk_i)
begin
if (clear) begin
wr_pt <= 4'h0 ;
rd_pt <= 4'h0 ;
end
else begin
if (push) begin
fifo[wr_pt] <= wr_data_i ;
wr_pt <= wr_pt + {{FW-1{1'b0}},1'b1} ;
end
if (pop) begin
axi_wdata_o <= fifo[rd_pt] ;
rd_pt <= rd_pt + {{FW-1{1'b0}},1'b1} ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
data_in_reg <= 'h0 ;
end
else begin
if (pop)
data_in_reg <= 1'b1 ;
else if ((axi_wrdy_i && axi_wvalid_o) || clear)
data_in_reg <= 1'b0 ;
end
end
wire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];
always @(posedge axi_clk_i)
begin
if (clear) begin
fill_lvl <= {FW+1{1'h0}} ;
fifo_flush <= 1'h0 ;
end
else begin
if (push && !pop)
fill_lvl <= fill_lvl + {{FW{1'b0}}, 1'h1} ;
else if(!push && pop)
fill_lvl <= fill_lvl - {{FW{1'b0}}, 1'h1} ;
if (fifo_flush_cond)
fifo_flush <= 1'b1 ;
else if (axi_wrdy_i)
fifo_flush <= 1'b0 ;
end
end
wire [8 :0] next_end_address = next_address[10:3] + {3'h0,fill_lvl} ;
wire [AW :0] next_stop_address = {1'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1'h0}},fill_lvl} ;
wire [AW+1:0] boundary_condition = {1'b0,next_address[AW:3]} + {{AW-FW+1{1'h0}},fill_lvl} - {1'b0,sys_stop_addr_r[AW-1:3]} ;
wire [2 :0] boundary_cross = {boundary_condition[AW+1], next_end_address[8],next_stop_address[AW]} ;
reg single_burst ;
reg single_burst_r ;
wire single_burst_posedge = !single_burst_r && single_burst;
always @(posedge axi_clk_i)
begin
if (clear) begin
single_burst <= 'h0 ;
single_burst_r <= 'h0 ;
end
else begin
single_burst <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;
single_burst_r <= single_burst ;
end
end
assign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl
|| single_burst_posedge)
&& !clear_do;
always @(posedge axi_clk_i)
begin
if (clear) begin
dat_cnt <= 4'h0 ;
axi_wsel_o <= {SW{1'b1}} ;
axi_wfixed_o <= 1'b0 ;
axi_wlen_o <= 4'h0 ;
end
else begin
if (new_burst && (next_address <= {1'b0,sys_stop_addr_r})) begin
if (boundary_cross[1:0] || fill_lvl[FW:4]) begin
if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin
dat_cnt <= 4'hF ;
axi_wlen_o <= 4'hF ;
end
else begin
if (boundary_cross[2]) begin
dat_cnt <= 4'hF - next_address[6:3];
axi_wlen_o <= 4'hF - next_address[6:3];
end
else begin
dat_cnt <= sys_stop_addr_r[6:3] - next_address[6:3];
axi_wlen_o <= sys_stop_addr_r[6:3] - next_address[6:3];
end
end
end
else begin
if (fifo_flush || fifo_flush_cond) begin
dat_cnt <= fill_lvl[3:0] - 4'h1 ;
axi_wlen_o <= fill_lvl[3:0] - 4'h1 ;
end
else begin
dat_cnt <= fill_lvl[3:0] ;
axi_wlen_o <= fill_lvl[3:0] ;
end
end
end
else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin
dat_cnt <= dat_cnt - 4'h1;
axi_wlen_o <= axi_wlen_o - 4'h1;
end
end
end
wire [4-1: 0] aaaa = 4'hF - next_address[6:3];
wire [4-1: 0] bbbb = sys_stop_addr_r[6:3] - next_address[6:3];
wire [4-1: 0] cccc = fill_lvl[3:0] - 4'h1;
wire [4-1: 0] dddd = fill_lvl[3:0];
assign pop = (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o))
&& axi_wrdy_i && axi_wvalid_o && fill_lvl) ;
always @(posedge axi_clk_i)
begin
if (clear) begin
axi_wvalid_o <= 1'h0 ;
axi_waddr_o <= ctrl_start_addr_i ;
next_address <= {1'b0,ctrl_start_addr_i} ;
sys_start_addr_r <= ctrl_start_addr_i ;
sys_stop_addr_r <= ctrl_stop_addr_i ;
sys_trig_size_r <= ctrl_trig_size_i ;
end
else begin
if ((next_address <= {1'b0,sys_stop_addr_r}) &&
( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin
axi_wvalid_o <= 1'h1 ;
next_address <= next_address + DW/8 ;
axi_waddr_o <= next_address[AW-1:0] ;
end
else if (ctrl_wrap_i && new_burst && (axi_waddr_o==sys_stop_addr_r)) begin
axi_wvalid_o <= 1'h1 ;
next_address <= {1'b0,sys_start_addr_r} + DW/8 ;
axi_waddr_o <= sys_start_addr_r ;
end
else if (axi_wrdy_i) begin
axi_wvalid_o <= 1'h0 ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_write_data_o <= 'h0 ;
end
else begin
stat_write_data_o <= (next_address <= {1'b0,sys_stop_addr_r}) ;
end
end
assign stat_cur_addr_o = next_address ;
endmodule | 21 |
5,141 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v | 113,454,857 | red_pitaya_ams.v | v | 99 | 103 | [] | [] | [] | [(41, 98)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:73: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h20\' generates 16 bits.\n : ... In instance red_pitaya_ams\n if (sys_addr[19:0]==16\'h20) dac_a_o <= sys_wdata[24-1: 0] ;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:74: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h24\' generates 16 bits.\n : ... In instance red_pitaya_ams\n if (sys_addr[19:0]==16\'h24) dac_b_o <= sys_wdata[24-1: 0] ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:75: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h28\' generates 16 bits.\n : ... In instance red_pitaya_ams\n if (sys_addr[19:0]==16\'h28) dac_c_o <= sys_wdata[24-1: 0] ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:76: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h2c\' generates 16 bits.\n : ... In instance red_pitaya_ams\n if (sys_addr[19:0]==16\'h2C) dac_d_o <= sys_wdata[24-1: 0] ;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 5,580 | module | module red_pitaya_ams (
input clk_i ,
input rstn_i ,
output reg [ 24-1: 0] dac_a_o ,
output reg [ 24-1: 0] dac_b_o ,
output reg [ 24-1: 0] dac_c_o ,
output reg [ 24-1: 0] dac_d_o ,
input [ 32-1: 0] sys_addr ,
input [ 32-1: 0] sys_wdata ,
input [ 4-1: 0] sys_sel ,
input sys_wen ,
input sys_ren ,
output reg [ 32-1: 0] sys_rdata ,
output reg sys_err ,
output reg sys_ack
);
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dac_a_o <= 24'h0F_0000 ;
dac_b_o <= 24'h4E_0000 ;
dac_c_o <= 24'h75_0000 ;
dac_d_o <= 24'h9C_0000 ;
end else begin
if (sys_wen) begin
if (sys_addr[19:0]==16'h20) dac_a_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h24) dac_b_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h28) dac_c_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h2C) dac_d_o <= sys_wdata[24-1: 0] ;
end
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;
casez (sys_addr[19:0])
20'h00020 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_a_o} ; end
20'h00024 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_b_o} ; end
20'h00028 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_c_o} ; end
20'h0002C : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_d_o} ; end
default : begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule | module red_pitaya_ams (
input clk_i ,
input rstn_i ,
output reg [ 24-1: 0] dac_a_o ,
output reg [ 24-1: 0] dac_b_o ,
output reg [ 24-1: 0] dac_c_o ,
output reg [ 24-1: 0] dac_d_o ,
input [ 32-1: 0] sys_addr ,
input [ 32-1: 0] sys_wdata ,
input [ 4-1: 0] sys_sel ,
input sys_wen ,
input sys_ren ,
output reg [ 32-1: 0] sys_rdata ,
output reg sys_err ,
output reg sys_ack
); |
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dac_a_o <= 24'h0F_0000 ;
dac_b_o <= 24'h4E_0000 ;
dac_c_o <= 24'h75_0000 ;
dac_d_o <= 24'h9C_0000 ;
end else begin
if (sys_wen) begin
if (sys_addr[19:0]==16'h20) dac_a_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h24) dac_b_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h28) dac_c_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h2C) dac_d_o <= sys_wdata[24-1: 0] ;
end
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;
casez (sys_addr[19:0])
20'h00020 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_a_o} ; end
20'h00024 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_b_o} ; end
20'h00028 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_c_o} ; end
20'h0002C : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_d_o} ; end
default : begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule | 21 |
5,144 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_hk.v | 113,454,857 | red_pitaya_hk.v | v | 164 | 104 | [] | [] | [] | [(29, 163)] | null | null | 1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_hk.v:95: Cannot find file containing module: 'DNA_PORT'\nDNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT.v\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT.sv\n DNA_PORT\n DNA_PORT.v\n DNA_PORT.sv\n obj_dir/DNA_PORT\n obj_dir/DNA_PORT.v\n obj_dir/DNA_PORT.sv\n%Error: Exiting due to 1 error(s)\n" | 5,584 | module | module red_pitaya_hk #(
parameter DWL = 8,
parameter DWE = 8,
parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(
input clk_i ,
input rstn_i ,
output reg [DWL-1:0] led_o ,
output reg digital_loop,
input [DWE-1:0] exp_p_dat_i,
output reg [DWE-1:0] exp_p_dat_o,
output reg [DWE-1:0] exp_p_dir_o,
input [DWE-1:0] exp_n_dat_i,
output reg [ 7-1:0] exp_n_dat_o,
output reg [ 7-1:0] exp_n_dir_o,
input [ 32-1:0] sys_addr ,
input [ 32-1:0] sys_wdata ,
input [ 4-1:0] sys_sel ,
input sys_wen ,
input sys_ren ,
output reg [ 32-1:0] sys_rdata ,
output reg sys_err ,
output reg sys_ack
);
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value;
reg dna_done ;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dna_clk <= 1'b0;
dna_read <= 1'b0;
dna_shift <= 1'b0;
dna_cnt <= 9'd0;
dna_value <= 57'd0;
dna_done <= 1'b0;
end else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
.DOUT ( dna_dout ),
.CLK ( dna_clk ),
.DIN ( 1'b0 ),
.READ ( dna_read ),
.SHIFT ( dna_shift )
);
wire [32-1: 0] id_value;
assign id_value[31: 4] = 28'h0;
assign id_value[ 3: 0] = 4'h1;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
led_o <= {DWL{1'b0}};
exp_p_dat_o <= {DWE{1'b0}};
exp_p_dir_o <= {DWE{1'b0}};
exp_n_dat_o <= {7{1'b0}};
exp_n_dir_o <= {7{1'b0}};
end else if (sys_wen) begin
if (sys_addr[19:0]==20'h0c) digital_loop <= sys_wdata[0];
if (sys_addr[19:0]==20'h10) exp_p_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h14) exp_n_dir_o <= sys_wdata[ 7-1:0];
if (sys_addr[19:0]==20'h18) exp_p_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h1C) exp_n_dat_o <= sys_wdata[ 7-1:0];
if (sys_addr[19:0]==20'h30) led_o <= sys_wdata[DWL-1:0];
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0;
sys_ack <= 1'b0;
end else begin
sys_err <= 1'b0;
casez (sys_addr[19:0])
20'h00000: begin sys_ack <= sys_en; sys_rdata <= { id_value }; end
20'h00004: begin sys_ack <= sys_en; sys_rdata <= { dna_value[32-1: 0]}; end
20'h00008: begin sys_ack <= sys_en; sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
20'h0000c: begin sys_ack <= sys_en; sys_rdata <= {{32- 1{1'b0}}, digital_loop }; end
20'h00010: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o} ; end
20'h00014: begin sys_ack <= sys_en; sys_rdata <= {{32-7{1'b0}} , exp_n_dir_o} ; end
20'h00018: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o} ; end
20'h0001C: begin sys_ack <= sys_en; sys_rdata <= {{32-7{1'b0}} , exp_n_dat_o} ; end
20'h00020: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i} ; end
20'h00024: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i} ; end
20'h00030: begin sys_ack <= sys_en; sys_rdata <= {{32-DWL{1'b0}}, led_o} ; end
default: begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule | module red_pitaya_hk #(
parameter DWL = 8,
parameter DWE = 8,
parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(
input clk_i ,
input rstn_i ,
output reg [DWL-1:0] led_o ,
output reg digital_loop,
input [DWE-1:0] exp_p_dat_i,
output reg [DWE-1:0] exp_p_dat_o,
output reg [DWE-1:0] exp_p_dir_o,
input [DWE-1:0] exp_n_dat_i,
output reg [ 7-1:0] exp_n_dat_o,
output reg [ 7-1:0] exp_n_dir_o,
input [ 32-1:0] sys_addr ,
input [ 32-1:0] sys_wdata ,
input [ 4-1:0] sys_sel ,
input sys_wen ,
input sys_ren ,
output reg [ 32-1:0] sys_rdata ,
output reg sys_err ,
output reg sys_ack
); |
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value;
reg dna_done ;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dna_clk <= 1'b0;
dna_read <= 1'b0;
dna_shift <= 1'b0;
dna_cnt <= 9'd0;
dna_value <= 57'd0;
dna_done <= 1'b0;
end else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
.DOUT ( dna_dout ),
.CLK ( dna_clk ),
.DIN ( 1'b0 ),
.READ ( dna_read ),
.SHIFT ( dna_shift )
);
wire [32-1: 0] id_value;
assign id_value[31: 4] = 28'h0;
assign id_value[ 3: 0] = 4'h1;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
led_o <= {DWL{1'b0}};
exp_p_dat_o <= {DWE{1'b0}};
exp_p_dir_o <= {DWE{1'b0}};
exp_n_dat_o <= {7{1'b0}};
exp_n_dir_o <= {7{1'b0}};
end else if (sys_wen) begin
if (sys_addr[19:0]==20'h0c) digital_loop <= sys_wdata[0];
if (sys_addr[19:0]==20'h10) exp_p_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h14) exp_n_dir_o <= sys_wdata[ 7-1:0];
if (sys_addr[19:0]==20'h18) exp_p_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h1C) exp_n_dat_o <= sys_wdata[ 7-1:0];
if (sys_addr[19:0]==20'h30) led_o <= sys_wdata[DWL-1:0];
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0;
sys_ack <= 1'b0;
end else begin
sys_err <= 1'b0;
casez (sys_addr[19:0])
20'h00000: begin sys_ack <= sys_en; sys_rdata <= { id_value }; end
20'h00004: begin sys_ack <= sys_en; sys_rdata <= { dna_value[32-1: 0]}; end
20'h00008: begin sys_ack <= sys_en; sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
20'h0000c: begin sys_ack <= sys_en; sys_rdata <= {{32- 1{1'b0}}, digital_loop }; end
20'h00010: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o} ; end
20'h00014: begin sys_ack <= sys_en; sys_rdata <= {{32-7{1'b0}} , exp_n_dir_o} ; end
20'h00018: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o} ; end
20'h0001C: begin sys_ack <= sys_en; sys_rdata <= {{32-7{1'b0}} , exp_n_dat_o} ; end
20'h00020: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i} ; end
20'h00024: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i} ; end
20'h00030: begin sys_ack <= sys_en; sys_rdata <= {{32-DWL{1'b0}}, led_o} ; end
default: begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule | 21 |
5,147 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_pll.sv | 113,454,857 | red_pitaya_pll.sv | sv | 86 | 80 | [] | [] | [] | null | line:85: before: ":" | null | 1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_pll.sv:30: Cannot find file containing module: 'PLLE2_ADV'\nPLLE2_ADV #(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/PLLE2_ADV\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/PLLE2_ADV.v\n data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/PLLE2_ADV.sv\n PLLE2_ADV\n PLLE2_ADV.v\n PLLE2_ADV.sv\n obj_dir/PLLE2_ADV\n obj_dir/PLLE2_ADV.v\n obj_dir/PLLE2_ADV.sv\n%Error: Exiting due to 1 error(s)\n" | 5,587 | module | module red_pitaya_pll (
input logic clk ,
input logic rstn ,
output logic clk_adc ,
output logic clk_dac_1x,
output logic clk_dac_2x,
output logic clk_dac_2p,
output logic clk_ser ,
output logic clk_pwm ,
output logic pll_locked
);
logic clk_fb;
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD" ),
.DIVCLK_DIVIDE ( 1 ),
.CLKFBOUT_MULT ( 8 ),
.CLKFBOUT_PHASE ( 0.000 ),
.CLKOUT0_DIVIDE ( 8 ),
.CLKOUT0_PHASE ( 0.000 ),
.CLKOUT0_DUTY_CYCLE ( 0.5 ),
.CLKOUT1_DIVIDE ( 8 ),
.CLKOUT1_PHASE ( 0.000 ),
.CLKOUT1_DUTY_CYCLE ( 0.5 ),
.CLKOUT2_DIVIDE ( 4 ),
.CLKOUT2_PHASE ( 0.000 ),
.CLKOUT2_DUTY_CYCLE ( 0.5 ),
.CLKOUT3_DIVIDE ( 4 ),
.CLKOUT3_PHASE (-45.000 ),
.CLKOUT3_DUTY_CYCLE ( 0.5 ),
.CLKOUT4_DIVIDE ( 4 ),
.CLKOUT4_PHASE ( 0.000 ),
.CLKOUT4_DUTY_CYCLE ( 0.5 ),
.CLKOUT5_DIVIDE ( 4 ),
.CLKOUT5_PHASE ( 0.000 ),
.CLKOUT5_DUTY_CYCLE ( 0.5 ),
.CLKIN1_PERIOD ( 8.000 ),
.REF_JITTER1 ( 0.010 )
) pll (
.CLKFBOUT (clk_fb ),
.CLKOUT0 (clk_adc ),
.CLKOUT1 (clk_dac_1x),
.CLKOUT2 (clk_dac_2x),
.CLKOUT3 (clk_dac_2p),
.CLKOUT4 (clk_ser ),
.CLKOUT5 (clk_pwm ),
.CLKFBIN (clk_fb ),
.CLKIN1 (clk ),
.CLKIN2 (1'b0 ),
.CLKINSEL (1'b1 ),
.DADDR (7'h0 ),
.DCLK (1'b0 ),
.DEN (1'b0 ),
.DI (16'h0),
.DO ( ),
.DRDY ( ),
.DWE (1'b0 ),
.LOCKED (pll_locked),
.PWRDWN (1'b0 ),
.RST (!rstn )
);
endmodule | module red_pitaya_pll (
input logic clk ,
input logic rstn ,
output logic clk_adc ,
output logic clk_dac_1x,
output logic clk_dac_2x,
output logic clk_dac_2p,
output logic clk_ser ,
output logic clk_pwm ,
output logic pll_locked
); |
logic clk_fb;
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD" ),
.DIVCLK_DIVIDE ( 1 ),
.CLKFBOUT_MULT ( 8 ),
.CLKFBOUT_PHASE ( 0.000 ),
.CLKOUT0_DIVIDE ( 8 ),
.CLKOUT0_PHASE ( 0.000 ),
.CLKOUT0_DUTY_CYCLE ( 0.5 ),
.CLKOUT1_DIVIDE ( 8 ),
.CLKOUT1_PHASE ( 0.000 ),
.CLKOUT1_DUTY_CYCLE ( 0.5 ),
.CLKOUT2_DIVIDE ( 4 ),
.CLKOUT2_PHASE ( 0.000 ),
.CLKOUT2_DUTY_CYCLE ( 0.5 ),
.CLKOUT3_DIVIDE ( 4 ),
.CLKOUT3_PHASE (-45.000 ),
.CLKOUT3_DUTY_CYCLE ( 0.5 ),
.CLKOUT4_DIVIDE ( 4 ),
.CLKOUT4_PHASE ( 0.000 ),
.CLKOUT4_DUTY_CYCLE ( 0.5 ),
.CLKOUT5_DIVIDE ( 4 ),
.CLKOUT5_PHASE ( 0.000 ),
.CLKOUT5_DUTY_CYCLE ( 0.5 ),
.CLKIN1_PERIOD ( 8.000 ),
.REF_JITTER1 ( 0.010 )
) pll (
.CLKFBOUT (clk_fb ),
.CLKOUT0 (clk_adc ),
.CLKOUT1 (clk_dac_1x),
.CLKOUT2 (clk_dac_2x),
.CLKOUT3 (clk_dac_2p),
.CLKOUT4 (clk_ser ),
.CLKOUT5 (clk_pwm ),
.CLKFBIN (clk_fb ),
.CLKIN1 (clk ),
.CLKIN2 (1'b0 ),
.CLKINSEL (1'b1 ),
.DADDR (7'h0 ),
.DCLK (1'b0 ),
.DEN (1'b0 ),
.DI (16'h0),
.DO ( ),
.DRDY ( ),
.DWE (1'b0 ),
.LOCKED (pll_locked),
.PWRDWN (1'b0 ),
.RST (!rstn )
);
endmodule | 21 |
5,153 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/debounce.v | 113,454,857 | debounce.v | v | 114 | 118 | [] | [] | [] | [(11, 105)] | null | data/verilator_xmls/e322494c-72b2-49fb-a085-a170c2d7df41.xml | null | 5,595 | module | module debounce #(parameter N0=7 , N1=4)
(
input wire clk, reset,
input wire in,
output reg db_level, db_tick
);
localparam [1:0]
zero = 2'b00,
wait0 = 2'b01,
one = 2'b10,
wait1 = 2'b11;
reg [N0-1:0] q_reg, q_next;
reg [1:0] state_reg, state_next;
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= zero;
q_reg <= 0;
end
else
begin
state_reg <= state_next;
q_reg <= q_next;
end
always @*
begin
state_next = state_reg;
q_next = q_reg;
db_tick = 1'b0;
case (state_reg)
zero:
begin
db_level = 1'b0;
if (in)
begin
state_next = wait1;
q_next = {N0{1'b1}};
end
end
wait1:
begin
db_level = 1'b0;
if (in)
begin
q_next = q_reg - 1;
if (q_next==0)
begin
state_next = one;
db_tick = 1'b1;
end
end
else
state_next = zero;
end
one:
begin
db_level = 1'b1;
if (~in)
begin
state_next = wait0;
q_next = { {N0-N1{1'b0}} , {N1{1'b1}} };
end
end
wait0:
begin
db_level = 1'b1;
if (~in)
begin
q_next = q_reg - 1;
if (q_next==0)
state_next = zero;
end
else
state_next = one;
end
default: state_next = zero;
endcase
end
endmodule | module debounce #(parameter N0=7 , N1=4)
(
input wire clk, reset,
input wire in,
output reg db_level, db_tick
); |
localparam [1:0]
zero = 2'b00,
wait0 = 2'b01,
one = 2'b10,
wait1 = 2'b11;
reg [N0-1:0] q_reg, q_next;
reg [1:0] state_reg, state_next;
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= zero;
q_reg <= 0;
end
else
begin
state_reg <= state_next;
q_reg <= q_next;
end
always @*
begin
state_next = state_reg;
q_next = q_reg;
db_tick = 1'b0;
case (state_reg)
zero:
begin
db_level = 1'b0;
if (in)
begin
state_next = wait1;
q_next = {N0{1'b1}};
end
end
wait1:
begin
db_level = 1'b0;
if (in)
begin
q_next = q_reg - 1;
if (q_next==0)
begin
state_next = one;
db_tick = 1'b1;
end
end
else
state_next = zero;
end
one:
begin
db_level = 1'b1;
if (~in)
begin
state_next = wait0;
q_next = { {N0-N1{1'b0}} , {N1{1'b1}} };
end
end
wait0:
begin
db_level = 1'b1;
if (~in)
begin
q_next = q_reg - 1;
if (q_next==0)
state_next = zero;
end
else
state_next = one;
end
default: state_next = zero;
endcase
end
endmodule | 21 |
5,154 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v | 113,454,857 | gen_mod2.v | v | 433 | 120 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:353: Signal definition not found, creating implicitly: \'clksq_gt_sqp\'\n : ... Suggested alternative: \'clksq_equal_sqp\'\n assign clksq_gt_sqp = ( clk_sq_cnt>=sqp ); \n ^~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:356: Signal definition not found, creating implicitly: \'clksq_equal_phas\'\n : ... Suggested alternative: \'clksq_equal_sqp\'\n assign clksq_equal_phas = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ; \n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:126: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n : ... In instance gen_mod2\n assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14\'b0 : tau_tick_cnt + 14\'b001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:161: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit_next\' generates 3 bits.\n : ... In instance gen_mod2\n quad_bit <= quad_bit_next ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:178: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit_next = quad_add ? quad_bit + tau_tick : quad_bit ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:178: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'quad_bit\' generates 2 bits.\n : ... In instance gen_mod2\n assign quad_bit_next = quad_add ? quad_bit + tau_tick : quad_bit ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:180: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'cnt\' generates 10 bits.\n : ... In instance gen_mod2\n assign cnt_next = quad_add ? cnt :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:181: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit[0] ? cnt - tau_tick : cnt + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:181: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit[0] ? cnt - tau_tick : cnt + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:183: Operator COND expects 13 bits on the Conditional True, but Conditional True\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance gen_mod2\n assign cntu_next = cnt_next_zero ? 12\'b0 : cntu + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:183: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n assign cntu_next = cnt_next_zero ? 12\'b0 : cntu + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:206: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit1_next\' generates 3 bits.\n : ... In instance gen_mod2\n quad_bit1 <= quad_bit1_next ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance gen_mod2\n assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit1 + (tau_tick&quad_add1) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit1 + (tau_tick&quad_add1) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add1\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit1 + (tau_tick&quad_add1) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:217: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s CONST \'10\'h0\' generates 10 bits.\n : ... In instance gen_mod2\n assign cnt1_next = ( cntu == phase_b ) ? 10\'b0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:218: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'cnt1\' generates 10 bits.\n : ... In instance gen_mod2\n quad_add1 ? cnt1 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:219: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit1[0] ? cnt1 - tau_tick : cnt1 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:219: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit1[0] ? cnt1 - tau_tick : cnt1 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:244: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit2_next\' generates 3 bits.\n : ... In instance gen_mod2\n quad_bit2 <= quad_bit2_next ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance gen_mod2\n assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit2 + (tau_tick&quad_add2) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit2 + (tau_tick&quad_add2) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add2\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit2 + (tau_tick&quad_add2) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:256: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s VARREF \'cnt2\' generates 9 bits.\n : ... In instance gen_mod2\n quad_add2 ? cnt2 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:257: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit2[0] ? cnt2 - tau_tick : cnt2 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:257: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit2[0] ? cnt2 - tau_tick : cnt2 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:282: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit3_next\' generates 3 bits.\n : ... In instance gen_mod2\n quad_bit3 <= quad_bit3_next ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance gen_mod2\n assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit3 + (tau_tick&quad_add3) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit3 + (tau_tick&quad_add3) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add3\' generates 1 bits.\n : ... In instance gen_mod2\n assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00 : quad_bit3 + (tau_tick&quad_add3) ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:293: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance gen_mod2\n assign cnt3_next = ( cntu == phase_b ) ? 8\'b0 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:294: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s VARREF \'cnt3\' generates 8 bits.\n : ... In instance gen_mod2\n quad_add3 ? cnt3 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:295: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit3[0] ? cnt3 - tau_tick : cnt3 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:295: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n : ... In instance gen_mod2\n quad_bit3[0] ? cnt3 - tau_tick : cnt3 + tau_tick ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:339: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'cnt_next\' generates 11 bits.\n : ... In instance gen_mod2\n clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:356: Operator EQ expects 33 bits on the RHS, but RHS\'s SEL generates 32 bits.\n : ... In instance gen_mod2\n assign clksq_equal_phas = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:362: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance gen_mod2\n assign clk_sq_cnt_next = clksq_gt_sqp ? 32\'b0 : clk_sq_cnt + 32\'b001;\n ^\n%Error: Exiting due to 37 warning(s)\n' | 5,596 | module | module gen_mod2
(
input clk,rst,
input [12-1:0] phase,
input [32-1:0] phase_sq,
input [14-1:0] hp,
input [32-1:0] sqp,
output signed [14-1:0] sin_ref,
output signed [14-1:0] cos_ref, cos_1f, cos_2f, cos_3f,
output [12-1:0] cntu_w,
output sq_ref, sq_quad, sq_phas,
output harmonic_trig, square_trig
);
reg [12-1:0] phase_b;
wire cnt_next_zero;
reg sq_ref_r;
wire sq_ref_next;
reg sq_quad_r;
wire sq_quad_next;
reg sq_phas_r;
wire sq_phas_next;
wire clksq_equal_sqp, sqp_off;
wire phas_less_than_sqp,clksq_equal_sqp_half;
reg [32-1:0] clk_sq_cnt;
wire [33-1:0] clk_sq_cnt_next;
wire [32-1:0] sqp_half;
wire [33-1:0] sqp_plus_half;
wire [33-1:0] phas_sq;
wire tau_tick;
wire tau_tick_cnt_equal_hp;
reg [14-1:0] tau_tick_cnt;
wire [15-1:0] tau_tick_cnt_next;
reg signed [14-1:0] memory_sin_r [630-1:0];
initial
begin
$readmemb("data_sin_ss.dat", memory_sin_r);
end
reg signed [14-1:0] memory_cos_r [630-1:0];
initial
begin
$readmemb("data_cos_ss.dat", memory_cos_r);
end
reg signed [14-1:0] memory_cos1_r [630-1:0];
initial
begin
$readmemb("data_cos_ss.dat", memory_cos1_r);
end
reg signed [14-1:0] memory_cos2_r [315-1:0];
initial
begin
$readmemb("data_cos2_ss.dat", memory_cos2_r);
end
reg signed [14-1:0] memory_cos3_r [210-1:0];
initial
begin
$readmemb("data_cos3_ss.dat", memory_cos3_r);
end
always @(posedge clk)
if (rst)
tau_tick_cnt <= 0;
else
tau_tick_cnt <= tau_tick_cnt_next[14-1:0];
assign tau_tick_cnt_equal_hp = (tau_tick_cnt==hp) ;
assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14'b0 : tau_tick_cnt + 14'b001;
assign tau_tick = (hp==14'b0) ? 1'b1 : tau_tick_cnt_equal_hp ;
reg [10-1:0] cnt ;
wire [11-1:0] cnt_next ;
reg [12-1:0] cntu ;
wire [13-1:0] cntu_next ;
assign cntu_w = cntu;
reg [ 2-1:0] quad_bit ;
wire [ 3-1:0] quad_bit_next ;
wire quad_add;
always @(posedge clk)
if (rst)
begin
cnt <= 10'b0 ;
quad_bit <= 2'b0 ;
cntu <= 12'b0 ;
phase_b <= 12'd2519 ;
end
else
begin
cnt <= cnt_next[10-1:0] ;
quad_bit <= quad_bit_next ;
cntu <= cntu_next[12-1:0] ;
if(phase==12'b0)
phase_b <= 12'd2519 ;
else
phase_b <= phase[12-1:0] - 12'b1 ;
end
assign quad_add = (cnt==10'd629 & quad_bit==2'b00 ) |
(cnt==10'd000 & quad_bit==2'b01 ) |
(cnt==10'd629 & quad_bit==2'b10 ) |
(cnt==10'd000 & quad_bit==2'b11 ) ;
assign quad_bit_next = quad_add ? quad_bit + tau_tick : quad_bit ;
assign cnt_next = quad_add ? cnt :
quad_bit[0] ? cnt - tau_tick : cnt + tau_tick ;
assign cnt_next_zero = (quad_bit==2'b11)&(cnt==10'd000)&tau_tick ;
assign cntu_next = cnt_next_zero ? 12'b0 : cntu + tau_tick ;
assign harmonic_trig = cnt_next_zero ;
reg [10-1:0] cnt1 ;
wire [11-1:0] cnt1_next ;
reg [ 2-1:0] quad_bit1 ;
wire [ 3-1:0] quad_bit1_next ;
wire quad_add1;
always @(posedge clk)
if (rst)
begin
cnt1 <= 10'b0 ;
quad_bit1 <= 2'b0 ;
end
else
begin
cnt1 <= cnt1_next[10-1:0] ;
quad_bit1 <= quad_bit1_next ;
end
assign quad_add1 = (cnt1==10'd629 & quad_bit1==2'b00 ) |
(cnt1==10'd000 & quad_bit1==2'b01 ) |
(cnt1==10'd629 & quad_bit1==2'b10 ) |
(cnt1==10'd000 & quad_bit1==2'b11 ) ;
assign quad_bit1_next = ( cntu == phase_b ) ? 2'b00 : quad_bit1 + (tau_tick&quad_add1) ;
assign cnt1_next = ( cntu == phase_b )? 10'b0 :
quad_add1 ? cnt1 :
quad_bit1[0] ? cnt1 - tau_tick : cnt1 + tau_tick ;
reg [ 9-1:0] cnt2 ;
wire [10-1:0] cnt2_next ;
reg [ 2-1:0] quad_bit2 ;
wire [ 3-1:0] quad_bit2_next ;
wire quad_add2;
always @(posedge clk)
if (rst)
begin
cnt2 <= 9'b0 ;
quad_bit2 <= 2'b0 ;
end
else
begin
cnt2 <= cnt2_next[ 9-1:0] ;
quad_bit2 <= quad_bit2_next ;
end
assign quad_add2 = (cnt2==9'd314 & quad_bit2==2'b00 ) |
(cnt2==9'd000 & quad_bit2==2'b01 ) |
(cnt2==9'd314 & quad_bit2==2'b10 ) |
(cnt2==9'd000 & quad_bit2==2'b11 ) ;
assign quad_bit2_next = ( cntu == phase_b ) ? 2'b00 : quad_bit2 + (tau_tick&quad_add2) ;
assign cnt2_next = ( cntu == phase_b )? 10'b0 :
quad_add2 ? cnt2 :
quad_bit2[0] ? cnt2 - tau_tick : cnt2 + tau_tick ;
reg [ 8-1:0] cnt3 ;
wire [ 9-1:0] cnt3_next ;
reg [ 2-1:0] quad_bit3 ;
wire [ 3-1:0] quad_bit3_next ;
wire quad_add3;
always @(posedge clk)
if (rst)
begin
cnt3 <= 8'b0 ;
quad_bit3 <= 2'b0 ;
end
else
begin
cnt3 <= cnt3_next[ 8-1:0] ;
quad_bit3 <= quad_bit3_next ;
end
assign quad_add3 = (cnt3==8'd209 & quad_bit3==2'b00 ) |
(cnt3==8'd000 & quad_bit3==2'b01 ) |
(cnt3==8'd209 & quad_bit3==2'b10 ) |
(cnt3==8'd000 & quad_bit3==2'b11 ) ;
assign quad_bit3_next = ( cntu == phase_b ) ? 2'b00 : quad_bit3 + (tau_tick&quad_add3) ;
assign cnt3_next = ( cntu == phase_b )? 8'b0 :
quad_add3 ? cnt3 :
quad_bit3[0] ? cnt3 - tau_tick : cnt3 + tau_tick ;
assign cos_ref = quad_bit[1]^quad_bit[0] ? $signed(-memory_cos_r[cnt]) : memory_cos_r[cnt] ;
assign sin_ref = quad_bit[1] ? $signed(-memory_sin_r[cnt]) : memory_sin_r[cnt] ;
assign cos_1f = quad_bit1[1]^quad_bit1[0] ? $signed(-memory_cos1_r[cnt1] ) : memory_cos1_r[cnt1] ;
assign cos_2f = quad_bit2[1]^quad_bit2[0] ? $signed(-memory_cos2_r[cnt2]) : memory_cos2_r[cnt2] ;
assign cos_3f = quad_bit3[1]^quad_bit3[0] ? $signed(-memory_cos3_r[cnt3]) : memory_cos3_r[cnt3] ;
always @(posedge clk)
if (rst)
begin
clk_sq_cnt <= 0;
sq_ref_r <= 0;
sq_quad_r <= 0;
sq_phas_r <= 0;
end
else
begin
clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];
sq_ref_r <= sq_ref_next ;
sq_quad_r <= sq_quad_next;
sq_phas_r <= sq_phas_next;
end
assign sqp_half = sqp >> 1'b1 ;
assign sqp_plus_half = sqp + sqp_half ;
assign phas_sq = phas_less_than_sqp ? {1'b0,phase_sq} : (phase_sq - sqp) ;
assign clksq_equal_sqp = ( clk_sq_cnt==sqp );
assign clksq_gt_sqp = ( clk_sq_cnt>=sqp );
assign clksq_equal_sqp_half = ( clk_sq_cnt==sqp_half ) ;
assign clksq_equal_phas = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;
assign sqp_off = ( sqp==32'b00 );
assign phas_less_than_sqp = ( phase_sq < sqp + 1'b1 );
assign clk_sq_cnt_next = clksq_gt_sqp ? 32'b0 : clk_sq_cnt + 32'b001;
assign sq_ref_next = clksq_equal_sqp ? ~sq_ref_r : sq_ref_r ;
assign sq_quad_next = clksq_equal_sqp_half ? sq_ref_r : sq_quad_r ;
assign sq_phas_next = clksq_equal_phas ? sq_ref_next^(~phas_less_than_sqp) : sq_phas_r ;
assign sq_ref = sqp_off ? (~cos_ref[13]) : sq_ref_r ;
assign sq_quad = sqp_off ? (~sin_ref[13]) : sq_quad_r ;
assign sq_phas = sqp_off ? (~cos_1f[13] ) : sq_phas_r ;
assign square_trig = clksq_equal_sqp_half & sq_ref ;
endmodule | module gen_mod2
(
input clk,rst,
input [12-1:0] phase,
input [32-1:0] phase_sq,
input [14-1:0] hp,
input [32-1:0] sqp,
output signed [14-1:0] sin_ref,
output signed [14-1:0] cos_ref, cos_1f, cos_2f, cos_3f,
output [12-1:0] cntu_w,
output sq_ref, sq_quad, sq_phas,
output harmonic_trig, square_trig
); |
reg [12-1:0] phase_b;
wire cnt_next_zero;
reg sq_ref_r;
wire sq_ref_next;
reg sq_quad_r;
wire sq_quad_next;
reg sq_phas_r;
wire sq_phas_next;
wire clksq_equal_sqp, sqp_off;
wire phas_less_than_sqp,clksq_equal_sqp_half;
reg [32-1:0] clk_sq_cnt;
wire [33-1:0] clk_sq_cnt_next;
wire [32-1:0] sqp_half;
wire [33-1:0] sqp_plus_half;
wire [33-1:0] phas_sq;
wire tau_tick;
wire tau_tick_cnt_equal_hp;
reg [14-1:0] tau_tick_cnt;
wire [15-1:0] tau_tick_cnt_next;
reg signed [14-1:0] memory_sin_r [630-1:0];
initial
begin
$readmemb("data_sin_ss.dat", memory_sin_r);
end
reg signed [14-1:0] memory_cos_r [630-1:0];
initial
begin
$readmemb("data_cos_ss.dat", memory_cos_r);
end
reg signed [14-1:0] memory_cos1_r [630-1:0];
initial
begin
$readmemb("data_cos_ss.dat", memory_cos1_r);
end
reg signed [14-1:0] memory_cos2_r [315-1:0];
initial
begin
$readmemb("data_cos2_ss.dat", memory_cos2_r);
end
reg signed [14-1:0] memory_cos3_r [210-1:0];
initial
begin
$readmemb("data_cos3_ss.dat", memory_cos3_r);
end
always @(posedge clk)
if (rst)
tau_tick_cnt <= 0;
else
tau_tick_cnt <= tau_tick_cnt_next[14-1:0];
assign tau_tick_cnt_equal_hp = (tau_tick_cnt==hp) ;
assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14'b0 : tau_tick_cnt + 14'b001;
assign tau_tick = (hp==14'b0) ? 1'b1 : tau_tick_cnt_equal_hp ;
reg [10-1:0] cnt ;
wire [11-1:0] cnt_next ;
reg [12-1:0] cntu ;
wire [13-1:0] cntu_next ;
assign cntu_w = cntu;
reg [ 2-1:0] quad_bit ;
wire [ 3-1:0] quad_bit_next ;
wire quad_add;
always @(posedge clk)
if (rst)
begin
cnt <= 10'b0 ;
quad_bit <= 2'b0 ;
cntu <= 12'b0 ;
phase_b <= 12'd2519 ;
end
else
begin
cnt <= cnt_next[10-1:0] ;
quad_bit <= quad_bit_next ;
cntu <= cntu_next[12-1:0] ;
if(phase==12'b0)
phase_b <= 12'd2519 ;
else
phase_b <= phase[12-1:0] - 12'b1 ;
end
assign quad_add = (cnt==10'd629 & quad_bit==2'b00 ) |
(cnt==10'd000 & quad_bit==2'b01 ) |
(cnt==10'd629 & quad_bit==2'b10 ) |
(cnt==10'd000 & quad_bit==2'b11 ) ;
assign quad_bit_next = quad_add ? quad_bit + tau_tick : quad_bit ;
assign cnt_next = quad_add ? cnt :
quad_bit[0] ? cnt - tau_tick : cnt + tau_tick ;
assign cnt_next_zero = (quad_bit==2'b11)&(cnt==10'd000)&tau_tick ;
assign cntu_next = cnt_next_zero ? 12'b0 : cntu + tau_tick ;
assign harmonic_trig = cnt_next_zero ;
reg [10-1:0] cnt1 ;
wire [11-1:0] cnt1_next ;
reg [ 2-1:0] quad_bit1 ;
wire [ 3-1:0] quad_bit1_next ;
wire quad_add1;
always @(posedge clk)
if (rst)
begin
cnt1 <= 10'b0 ;
quad_bit1 <= 2'b0 ;
end
else
begin
cnt1 <= cnt1_next[10-1:0] ;
quad_bit1 <= quad_bit1_next ;
end
assign quad_add1 = (cnt1==10'd629 & quad_bit1==2'b00 ) |
(cnt1==10'd000 & quad_bit1==2'b01 ) |
(cnt1==10'd629 & quad_bit1==2'b10 ) |
(cnt1==10'd000 & quad_bit1==2'b11 ) ;
assign quad_bit1_next = ( cntu == phase_b ) ? 2'b00 : quad_bit1 + (tau_tick&quad_add1) ;
assign cnt1_next = ( cntu == phase_b )? 10'b0 :
quad_add1 ? cnt1 :
quad_bit1[0] ? cnt1 - tau_tick : cnt1 + tau_tick ;
reg [ 9-1:0] cnt2 ;
wire [10-1:0] cnt2_next ;
reg [ 2-1:0] quad_bit2 ;
wire [ 3-1:0] quad_bit2_next ;
wire quad_add2;
always @(posedge clk)
if (rst)
begin
cnt2 <= 9'b0 ;
quad_bit2 <= 2'b0 ;
end
else
begin
cnt2 <= cnt2_next[ 9-1:0] ;
quad_bit2 <= quad_bit2_next ;
end
assign quad_add2 = (cnt2==9'd314 & quad_bit2==2'b00 ) |
(cnt2==9'd000 & quad_bit2==2'b01 ) |
(cnt2==9'd314 & quad_bit2==2'b10 ) |
(cnt2==9'd000 & quad_bit2==2'b11 ) ;
assign quad_bit2_next = ( cntu == phase_b ) ? 2'b00 : quad_bit2 + (tau_tick&quad_add2) ;
assign cnt2_next = ( cntu == phase_b )? 10'b0 :
quad_add2 ? cnt2 :
quad_bit2[0] ? cnt2 - tau_tick : cnt2 + tau_tick ;
reg [ 8-1:0] cnt3 ;
wire [ 9-1:0] cnt3_next ;
reg [ 2-1:0] quad_bit3 ;
wire [ 3-1:0] quad_bit3_next ;
wire quad_add3;
always @(posedge clk)
if (rst)
begin
cnt3 <= 8'b0 ;
quad_bit3 <= 2'b0 ;
end
else
begin
cnt3 <= cnt3_next[ 8-1:0] ;
quad_bit3 <= quad_bit3_next ;
end
assign quad_add3 = (cnt3==8'd209 & quad_bit3==2'b00 ) |
(cnt3==8'd000 & quad_bit3==2'b01 ) |
(cnt3==8'd209 & quad_bit3==2'b10 ) |
(cnt3==8'd000 & quad_bit3==2'b11 ) ;
assign quad_bit3_next = ( cntu == phase_b ) ? 2'b00 : quad_bit3 + (tau_tick&quad_add3) ;
assign cnt3_next = ( cntu == phase_b )? 8'b0 :
quad_add3 ? cnt3 :
quad_bit3[0] ? cnt3 - tau_tick : cnt3 + tau_tick ;
assign cos_ref = quad_bit[1]^quad_bit[0] ? $signed(-memory_cos_r[cnt]) : memory_cos_r[cnt] ;
assign sin_ref = quad_bit[1] ? $signed(-memory_sin_r[cnt]) : memory_sin_r[cnt] ;
assign cos_1f = quad_bit1[1]^quad_bit1[0] ? $signed(-memory_cos1_r[cnt1] ) : memory_cos1_r[cnt1] ;
assign cos_2f = quad_bit2[1]^quad_bit2[0] ? $signed(-memory_cos2_r[cnt2]) : memory_cos2_r[cnt2] ;
assign cos_3f = quad_bit3[1]^quad_bit3[0] ? $signed(-memory_cos3_r[cnt3]) : memory_cos3_r[cnt3] ;
always @(posedge clk)
if (rst)
begin
clk_sq_cnt <= 0;
sq_ref_r <= 0;
sq_quad_r <= 0;
sq_phas_r <= 0;
end
else
begin
clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];
sq_ref_r <= sq_ref_next ;
sq_quad_r <= sq_quad_next;
sq_phas_r <= sq_phas_next;
end
assign sqp_half = sqp >> 1'b1 ;
assign sqp_plus_half = sqp + sqp_half ;
assign phas_sq = phas_less_than_sqp ? {1'b0,phase_sq} : (phase_sq - sqp) ;
assign clksq_equal_sqp = ( clk_sq_cnt==sqp );
assign clksq_gt_sqp = ( clk_sq_cnt>=sqp );
assign clksq_equal_sqp_half = ( clk_sq_cnt==sqp_half ) ;
assign clksq_equal_phas = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;
assign sqp_off = ( sqp==32'b00 );
assign phas_less_than_sqp = ( phase_sq < sqp + 1'b1 );
assign clk_sq_cnt_next = clksq_gt_sqp ? 32'b0 : clk_sq_cnt + 32'b001;
assign sq_ref_next = clksq_equal_sqp ? ~sq_ref_r : sq_ref_r ;
assign sq_quad_next = clksq_equal_sqp_half ? sq_ref_r : sq_quad_r ;
assign sq_phas_next = clksq_equal_phas ? sq_ref_next^(~phas_less_than_sqp) : sq_phas_r ;
assign sq_ref = sqp_off ? (~cos_ref[13]) : sq_ref_r ;
assign sq_quad = sqp_off ? (~sin_ref[13]) : sq_quad_r ;
assign sq_phas = sqp_off ? (~cos_1f[13] ) : sq_phas_r ;
assign square_trig = clksq_equal_sqp_half & sq_ref ;
endmodule | 21 |
5,157 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/jump_control.v | 113,454,857 | jump_control.v | v | 85 | 90 | [] | [] | [] | null | line:85: before: "&" | data/verilator_xmls/1ccee266-3aa4-478a-a270-32efee876f15.xml | null | 5,599 | module | module jump_control
#(parameter N=3)
(
input wire clk, rst,
input wire start,
output wire out ,
output wire tick
);
reg [N-1:0] cnt;
reg [N-1:0] cnt_next;
reg [2-1:0] state, state_next;
wire tirgger;
localparam [2-1:0]
idle = 2'd0,
wait1 = 2'd1,
jump = 2'd2,
wait2 = 2'd3;
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}} ;
state <= 0 ;
end
else begin
cnt <= cnt_next;
state <= state_next ;
end
always @*
begin
case (state)
idle : begin
if (start)
state_next <= wait1 ;
else
state_next <= idle ;
cnt_next <= {N{1'b0}} ;
end
wait1 : begin
if (&cnt)
state_next <= jump ;
else
state_next <= wait1 ;
cnt_next <= cnt + 1 ;
end
jump : begin
state_next <= wait2 ;
cnt_next <= {N{1'b0}} ;
end
wait2 : begin
if (start)
state_next <= wait2 ;
else
state_next <= idle ;
cnt_next <= {N{1'b0}} ;
end
default : begin
state <= idle;
cnt <= {N{1'b0}} ;
end
endcase
end
assign tick = (state==jump) ;
assign out = (state==jump)|(state==wait2) ;
endmodule | module jump_control
#(parameter N=3)
(
input wire clk, rst,
input wire start,
output wire out ,
output wire tick
); |
reg [N-1:0] cnt;
reg [N-1:0] cnt_next;
reg [2-1:0] state, state_next;
wire tirgger;
localparam [2-1:0]
idle = 2'd0,
wait1 = 2'd1,
jump = 2'd2,
wait2 = 2'd3;
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}} ;
state <= 0 ;
end
else begin
cnt <= cnt_next;
state <= state_next ;
end
always @*
begin
case (state)
idle : begin
if (start)
state_next <= wait1 ;
else
state_next <= idle ;
cnt_next <= {N{1'b0}} ;
end
wait1 : begin
if (&cnt)
state_next <= jump ;
else
state_next <= wait1 ;
cnt_next <= cnt + 1 ;
end
jump : begin
state_next <= wait2 ;
cnt_next <= {N{1'b0}} ;
end
wait2 : begin
if (start)
state_next <= wait2 ;
else
state_next <= idle ;
cnt_next <= {N{1'b0}} ;
end
default : begin
state <= idle;
cnt <= {N{1'b0}} ;
end
endcase
end
assign tick = (state==jump) ;
assign out = (state==jump)|(state==wait2) ;
endmodule | 21 |
5,162 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer3.v | 113,454,857 | muxer3.v | v | 83 | 83 | [] | [] | [] | [(7, 65)] | null | data/verilator_xmls/a40bb31b-9fa8-430f-963c-6cdacfb3a67f.xml | null | 5,606 | module | module muxer3 #(
parameter RES = 14
)
(
input [ 3-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
output [RES-1: 0] out
);
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ;
assign ensel0 = (sel==3'd0 );
assign ensel1 = (sel==3'd1 );
assign ensel2 = (sel==3'd2 );
assign ensel3 = (sel==3'd3 );
assign ensel4 = (sel==3'd4 );
assign ensel5 = (sel==3'd5 );
assign ensel6 = (sel==3'd6 );
assign ensel7 = (sel==3'd7 );
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 ;
endmodule | module muxer3 #(
parameter RES = 14
)
(
input [ 3-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
output [RES-1: 0] out
); |
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ;
assign ensel0 = (sel==3'd0 );
assign ensel1 = (sel==3'd1 );
assign ensel2 = (sel==3'd2 );
assign ensel3 = (sel==3'd3 );
assign ensel4 = (sel==3'd4 );
assign ensel5 = (sel==3'd5 );
assign ensel6 = (sel==3'd6 );
assign ensel7 = (sel==3'd7 );
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 ;
endmodule | 21 |
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