Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
5,163 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer4.v | 113,454,857 | muxer4.v | v | 125 | 83 | [] | [] | [] | [(7, 99)] | null | data/verilator_xmls/d9ead4cb-5d68-4870-a0b6-1a6642bf896f.xml | null | 5,607 | module | module muxer4 #(
parameter RES = 14
)
(
input [ 4-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
output [RES-1: 0] out
);
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ,
ensel8 ,ensel9 ,ensel10,ensel11,ensel12,ensel13,ensel14,ensel15;
assign ensel0 = (sel==4'd0 );
assign ensel1 = (sel==4'd1 );
assign ensel2 = (sel==4'd2 );
assign ensel3 = (sel==4'd3 );
assign ensel4 = (sel==4'd4 );
assign ensel5 = (sel==4'd5 );
assign ensel6 = (sel==4'd6 );
assign ensel7 = (sel==4'd7 );
assign ensel8 = (sel==4'd8 );
assign ensel9 = (sel==4'd9 );
assign ensel10 = (sel==4'd10);
assign ensel11 = (sel==4'd11);
assign ensel12 = (sel==4'd12);
assign ensel13 = (sel==4'd13);
assign ensel14 = (sel==4'd14);
assign ensel15 = (sel==4'd15);
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
wire [RES-1: 0] en8 ;
wire [RES-1: 0] en9 ;
wire [RES-1: 0] en10;
wire [RES-1: 0] en11;
wire [RES-1: 0] en12;
wire [RES-1: 0] en13;
wire [RES-1: 0] en14;
wire [RES-1: 0] en15;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign en8 = {RES{ ensel8 }} & in8 ;
assign en9 = {RES{ ensel9 }} & in9 ;
assign en10 = {RES{ ensel10 }} & in10 ;
assign en11 = {RES{ ensel11 }} & in11 ;
assign en12 = {RES{ ensel12 }} & in12 ;
assign en13 = {RES{ ensel13 }} & in13 ;
assign en14 = {RES{ ensel14 }} & in14 ;
assign en15 = {RES{ ensel15 }} & in15 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 |
en8 |en9 |en10|en11|en12|en13|en14|en15;
endmodule | module muxer4 #(
parameter RES = 14
)
(
input [ 4-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
output [RES-1: 0] out
); |
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ,
ensel8 ,ensel9 ,ensel10,ensel11,ensel12,ensel13,ensel14,ensel15;
assign ensel0 = (sel==4'd0 );
assign ensel1 = (sel==4'd1 );
assign ensel2 = (sel==4'd2 );
assign ensel3 = (sel==4'd3 );
assign ensel4 = (sel==4'd4 );
assign ensel5 = (sel==4'd5 );
assign ensel6 = (sel==4'd6 );
assign ensel7 = (sel==4'd7 );
assign ensel8 = (sel==4'd8 );
assign ensel9 = (sel==4'd9 );
assign ensel10 = (sel==4'd10);
assign ensel11 = (sel==4'd11);
assign ensel12 = (sel==4'd12);
assign ensel13 = (sel==4'd13);
assign ensel14 = (sel==4'd14);
assign ensel15 = (sel==4'd15);
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
wire [RES-1: 0] en8 ;
wire [RES-1: 0] en9 ;
wire [RES-1: 0] en10;
wire [RES-1: 0] en11;
wire [RES-1: 0] en12;
wire [RES-1: 0] en13;
wire [RES-1: 0] en14;
wire [RES-1: 0] en15;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign en8 = {RES{ ensel8 }} & in8 ;
assign en9 = {RES{ ensel9 }} & in9 ;
assign en10 = {RES{ ensel10 }} & in10 ;
assign en11 = {RES{ ensel11 }} & in11 ;
assign en12 = {RES{ ensel12 }} & in12 ;
assign en13 = {RES{ ensel13 }} & in13 ;
assign en14 = {RES{ ensel14 }} & in14 ;
assign en15 = {RES{ ensel15 }} & in15 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 |
en8 |en9 |en10|en11|en12|en13|en14|en15;
endmodule | 21 |
5,164 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer5.v | 113,454,857 | muxer5.v | v | 209 | 83 | [] | [] | [] | [(7, 167)] | null | data/verilator_xmls/393146ca-2038-4c94-8b7c-76c55383e03f.xml | null | 5,608 | module | module muxer5 #(
parameter RES = 14
)
(
input [ 5-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
input [RES-1: 0] in16,
input [RES-1: 0] in17,
input [RES-1: 0] in18,
input [RES-1: 0] in19,
input [RES-1: 0] in20,
input [RES-1: 0] in21,
input [RES-1: 0] in22,
input [RES-1: 0] in23,
input [RES-1: 0] in24,
input [RES-1: 0] in25,
input [RES-1: 0] in26,
input [RES-1: 0] in27,
input [RES-1: 0] in28,
input [RES-1: 0] in29,
input [RES-1: 0] in30,
input [RES-1: 0] in31,
output [RES-1: 0] out
);
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ,
ensel8 ,ensel9 ,ensel10,ensel11,ensel12,ensel13,ensel14,ensel15,
ensel16,ensel17,ensel18,ensel19,ensel20,ensel21,ensel22,ensel23,
ensel24,ensel25,ensel26,ensel27,ensel28,ensel29,ensel30,ensel31;
assign ensel0 = (sel==5'd0 );
assign ensel1 = (sel==5'd1 );
assign ensel2 = (sel==5'd2 );
assign ensel3 = (sel==5'd3 );
assign ensel4 = (sel==5'd4 );
assign ensel5 = (sel==5'd5 );
assign ensel6 = (sel==5'd6 );
assign ensel7 = (sel==5'd7 );
assign ensel8 = (sel==5'd8 );
assign ensel9 = (sel==5'd9 );
assign ensel10 = (sel==5'd10);
assign ensel11 = (sel==5'd11);
assign ensel12 = (sel==5'd12);
assign ensel13 = (sel==5'd13);
assign ensel14 = (sel==5'd14);
assign ensel15 = (sel==5'd15);
assign ensel16 = (sel==5'd16);
assign ensel17 = (sel==5'd17);
assign ensel18 = (sel==5'd18);
assign ensel19 = (sel==5'd19);
assign ensel20 = (sel==5'd20);
assign ensel21 = (sel==5'd21);
assign ensel22 = (sel==5'd22);
assign ensel23 = (sel==5'd23);
assign ensel24 = (sel==5'd24);
assign ensel25 = (sel==5'd25);
assign ensel26 = (sel==5'd26);
assign ensel27 = (sel==5'd27);
assign ensel28 = (sel==5'd28);
assign ensel29 = (sel==5'd29);
assign ensel30 = (sel==5'd30);
assign ensel31 = (sel==5'd31);
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
wire [RES-1: 0] en8 ;
wire [RES-1: 0] en9 ;
wire [RES-1: 0] en10;
wire [RES-1: 0] en11;
wire [RES-1: 0] en12;
wire [RES-1: 0] en13;
wire [RES-1: 0] en14;
wire [RES-1: 0] en15;
wire [RES-1: 0] en16;
wire [RES-1: 0] en17;
wire [RES-1: 0] en18;
wire [RES-1: 0] en19;
wire [RES-1: 0] en20;
wire [RES-1: 0] en21;
wire [RES-1: 0] en22;
wire [RES-1: 0] en23;
wire [RES-1: 0] en24;
wire [RES-1: 0] en25;
wire [RES-1: 0] en26;
wire [RES-1: 0] en27;
wire [RES-1: 0] en28;
wire [RES-1: 0] en29;
wire [RES-1: 0] en30;
wire [RES-1: 0] en31;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign en8 = {RES{ ensel8 }} & in8 ;
assign en9 = {RES{ ensel9 }} & in9 ;
assign en10 = {RES{ ensel10 }} & in10 ;
assign en11 = {RES{ ensel11 }} & in11 ;
assign en12 = {RES{ ensel12 }} & in12 ;
assign en13 = {RES{ ensel13 }} & in13 ;
assign en14 = {RES{ ensel14 }} & in14 ;
assign en15 = {RES{ ensel15 }} & in15 ;
assign en16 = {RES{ ensel16 }} & in16 ;
assign en17 = {RES{ ensel17 }} & in17 ;
assign en18 = {RES{ ensel18 }} & in18 ;
assign en19 = {RES{ ensel19 }} & in19 ;
assign en20 = {RES{ ensel20 }} & in20 ;
assign en21 = {RES{ ensel21 }} & in21 ;
assign en22 = {RES{ ensel22 }} & in22 ;
assign en23 = {RES{ ensel23 }} & in23 ;
assign en24 = {RES{ ensel24 }} & in24 ;
assign en25 = {RES{ ensel25 }} & in25 ;
assign en26 = {RES{ ensel26 }} & in26 ;
assign en27 = {RES{ ensel27 }} & in27 ;
assign en28 = {RES{ ensel28 }} & in28 ;
assign en29 = {RES{ ensel29 }} & in29 ;
assign en30 = {RES{ ensel30 }} & in30 ;
assign en31 = {RES{ ensel31 }} & in31 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 |
en8 |en9 |en10|en11|en12|en13|en14|en15|
en16|en17|en18|en19|en20|en21|en22|en23|
en24|en25|en26|en27|en28|en29|en30|en31;
endmodule | module muxer5 #(
parameter RES = 14
)
(
input [ 5-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
input [RES-1: 0] in16,
input [RES-1: 0] in17,
input [RES-1: 0] in18,
input [RES-1: 0] in19,
input [RES-1: 0] in20,
input [RES-1: 0] in21,
input [RES-1: 0] in22,
input [RES-1: 0] in23,
input [RES-1: 0] in24,
input [RES-1: 0] in25,
input [RES-1: 0] in26,
input [RES-1: 0] in27,
input [RES-1: 0] in28,
input [RES-1: 0] in29,
input [RES-1: 0] in30,
input [RES-1: 0] in31,
output [RES-1: 0] out
); |
wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ,
ensel8 ,ensel9 ,ensel10,ensel11,ensel12,ensel13,ensel14,ensel15,
ensel16,ensel17,ensel18,ensel19,ensel20,ensel21,ensel22,ensel23,
ensel24,ensel25,ensel26,ensel27,ensel28,ensel29,ensel30,ensel31;
assign ensel0 = (sel==5'd0 );
assign ensel1 = (sel==5'd1 );
assign ensel2 = (sel==5'd2 );
assign ensel3 = (sel==5'd3 );
assign ensel4 = (sel==5'd4 );
assign ensel5 = (sel==5'd5 );
assign ensel6 = (sel==5'd6 );
assign ensel7 = (sel==5'd7 );
assign ensel8 = (sel==5'd8 );
assign ensel9 = (sel==5'd9 );
assign ensel10 = (sel==5'd10);
assign ensel11 = (sel==5'd11);
assign ensel12 = (sel==5'd12);
assign ensel13 = (sel==5'd13);
assign ensel14 = (sel==5'd14);
assign ensel15 = (sel==5'd15);
assign ensel16 = (sel==5'd16);
assign ensel17 = (sel==5'd17);
assign ensel18 = (sel==5'd18);
assign ensel19 = (sel==5'd19);
assign ensel20 = (sel==5'd20);
assign ensel21 = (sel==5'd21);
assign ensel22 = (sel==5'd22);
assign ensel23 = (sel==5'd23);
assign ensel24 = (sel==5'd24);
assign ensel25 = (sel==5'd25);
assign ensel26 = (sel==5'd26);
assign ensel27 = (sel==5'd27);
assign ensel28 = (sel==5'd28);
assign ensel29 = (sel==5'd29);
assign ensel30 = (sel==5'd30);
assign ensel31 = (sel==5'd31);
wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;
wire [RES-1: 0] en8 ;
wire [RES-1: 0] en9 ;
wire [RES-1: 0] en10;
wire [RES-1: 0] en11;
wire [RES-1: 0] en12;
wire [RES-1: 0] en13;
wire [RES-1: 0] en14;
wire [RES-1: 0] en15;
wire [RES-1: 0] en16;
wire [RES-1: 0] en17;
wire [RES-1: 0] en18;
wire [RES-1: 0] en19;
wire [RES-1: 0] en20;
wire [RES-1: 0] en21;
wire [RES-1: 0] en22;
wire [RES-1: 0] en23;
wire [RES-1: 0] en24;
wire [RES-1: 0] en25;
wire [RES-1: 0] en26;
wire [RES-1: 0] en27;
wire [RES-1: 0] en28;
wire [RES-1: 0] en29;
wire [RES-1: 0] en30;
wire [RES-1: 0] en31;
assign en0 = {RES{ ensel0 }} & in0 ;
assign en1 = {RES{ ensel1 }} & in1 ;
assign en2 = {RES{ ensel2 }} & in2 ;
assign en3 = {RES{ ensel3 }} & in3 ;
assign en4 = {RES{ ensel4 }} & in4 ;
assign en5 = {RES{ ensel5 }} & in5 ;
assign en6 = {RES{ ensel6 }} & in6 ;
assign en7 = {RES{ ensel7 }} & in7 ;
assign en8 = {RES{ ensel8 }} & in8 ;
assign en9 = {RES{ ensel9 }} & in9 ;
assign en10 = {RES{ ensel10 }} & in10 ;
assign en11 = {RES{ ensel11 }} & in11 ;
assign en12 = {RES{ ensel12 }} & in12 ;
assign en13 = {RES{ ensel13 }} & in13 ;
assign en14 = {RES{ ensel14 }} & in14 ;
assign en15 = {RES{ ensel15 }} & in15 ;
assign en16 = {RES{ ensel16 }} & in16 ;
assign en17 = {RES{ ensel17 }} & in17 ;
assign en18 = {RES{ ensel18 }} & in18 ;
assign en19 = {RES{ ensel19 }} & in19 ;
assign en20 = {RES{ ensel20 }} & in20 ;
assign en21 = {RES{ ensel21 }} & in21 ;
assign en22 = {RES{ ensel22 }} & in22 ;
assign en23 = {RES{ ensel23 }} & in23 ;
assign en24 = {RES{ ensel24 }} & in24 ;
assign en25 = {RES{ ensel25 }} & in25 ;
assign en26 = {RES{ ensel26 }} & in26 ;
assign en27 = {RES{ ensel27 }} & in27 ;
assign en28 = {RES{ ensel28 }} & in28 ;
assign en29 = {RES{ ensel29 }} & in29 ;
assign en30 = {RES{ ensel30 }} & in30 ;
assign en31 = {RES{ ensel31 }} & in31 ;
assign out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 |
en8 |en9 |en10|en11|en12|en13|en14|en15|
en16|en17|en18|en19|en20|en21|en22|en23|
en24|en25|en26|en27|en28|en29|en30|en31;
endmodule | 21 |
5,165 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v | 113,454,857 | muxer_reg3.v | v | 60 | 61 | [] | [] | [] | null | line:37: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v:25: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance muxer_reg3\n out <= 3\'b0; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v:36: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance muxer_reg3\n default : out <= 3\'b0 ; \n ^~\n%Error: Exiting due to 2 warning(s)\n' | 5,609 | module | module muxer_reg3 #(
parameter RES = 14
)
(
input clk,rst,
input [ 3-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
output reg [RES-1: 0] out
);
always @(posedge clk)
if (rst)
out <= 3'b0;
else
case (sel)
3'd00 : out <= in0 ;
3'd01 : out <= in1 ;
3'd02 : out <= in2 ;
3'd03 : out <= in3 ;
3'd04 : out <= in4 ;
3'd05 : out <= in5 ;
3'd06 : out <= in6 ;
3'd07 : out <= in7 ;
default : out <= 3'b0 ;
endcase ;
endmodule | module muxer_reg3 #(
parameter RES = 14
)
(
input clk,rst,
input [ 3-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
output reg [RES-1: 0] out
); |
always @(posedge clk)
if (rst)
out <= 3'b0;
else
case (sel)
3'd00 : out <= in0 ;
3'd01 : out <= in1 ;
3'd02 : out <= in2 ;
3'd03 : out <= in3 ;
3'd04 : out <= in4 ;
3'd05 : out <= in5 ;
3'd06 : out <= in6 ;
3'd07 : out <= in7 ;
default : out <= 3'b0 ;
endcase ;
endmodule | 21 |
5,166 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v | 113,454,857 | muxer_reg4.v | v | 90 | 83 | [] | [] | [] | null | line:59: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v:39: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance muxer_reg4\n out <= 4\'b0; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v:58: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance muxer_reg4\n default : out <= 4\'b0 ; \n ^~\n%Error: Exiting due to 2 warning(s)\n' | 5,610 | module | module muxer_reg4 #(
parameter RES = 14
)
(
input clk,rst,
input [ 4-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
output reg [RES-1: 0] out
);
always @(posedge clk)
if (rst)
out <= 4'b0;
else
case (sel)
4'd00 : out <= in0 ;
4'd01 : out <= in1 ;
4'd02 : out <= in2 ;
4'd03 : out <= in3 ;
4'd04 : out <= in4 ;
4'd05 : out <= in5 ;
4'd06 : out <= in6 ;
4'd07 : out <= in7 ;
4'd08 : out <= in8 ;
4'd09 : out <= in9 ;
4'd10 : out <= in10 ;
4'd11 : out <= in11 ;
4'd12 : out <= in12 ;
4'd13 : out <= in13 ;
4'd14 : out <= in14 ;
4'd15 : out <= in15 ;
default : out <= 4'b0 ;
endcase ;
endmodule | module muxer_reg4 #(
parameter RES = 14
)
(
input clk,rst,
input [ 4-1: 0] sel,
input [RES-1: 0] in0,
input [RES-1: 0] in1,
input [RES-1: 0] in2,
input [RES-1: 0] in3,
input [RES-1: 0] in4,
input [RES-1: 0] in5,
input [RES-1: 0] in6,
input [RES-1: 0] in7,
input [RES-1: 0] in8,
input [RES-1: 0] in9,
input [RES-1: 0] in10,
input [RES-1: 0] in11,
input [RES-1: 0] in12,
input [RES-1: 0] in13,
input [RES-1: 0] in14,
input [RES-1: 0] in15,
output reg [RES-1: 0] out
); |
always @(posedge clk)
if (rst)
out <= 4'b0;
else
case (sel)
4'd00 : out <= in0 ;
4'd01 : out <= in1 ;
4'd02 : out <= in2 ;
4'd03 : out <= in3 ;
4'd04 : out <= in4 ;
4'd05 : out <= in5 ;
4'd06 : out <= in6 ;
4'd07 : out <= in7 ;
4'd08 : out <= in8 ;
4'd09 : out <= in9 ;
4'd10 : out <= in10 ;
4'd11 : out <= in11 ;
4'd12 : out <= in12 ;
4'd13 : out <= in13 ;
4'd14 : out <= in14 ;
4'd15 : out <= in15 ;
default : out <= 4'b0 ;
endcase ;
endmodule | 21 |
5,169 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sat14.v | 113,454,857 | sat14.v | v | 86 | 83 | [] | [] | [] | [(27, 53)] | null | data/verilator_xmls/76399544-127a-48d5-a053-a7606d79bcbc.xml | null | 5,613 | module | module sat14 #(
parameter RES = 14
)
(
input signed [RES-1:0] in,
input [RES-1:0] lim,
output signed [RES-1:0] out
);
wire [RES-1:0] shifted_in_pos,shifted_in_neg, mask;
wire pos_sat, neg_sat;
assign mask = {RES{1'b1}}<<lim ;
assign shifted_in_pos = in>>lim ;
assign shifted_in_neg = (~in)>>lim ;
assign pos_sat = ( 2'b01 == { in[RES-1] , |shifted_in_pos } ) ;
assign neg_sat = ( 2'b11 == { in[RES-1] , |shifted_in_neg } ) ;
assign out = pos_sat ? ( ~mask ) :
neg_sat ? mask :
in ;
endmodule | module sat14 #(
parameter RES = 14
)
(
input signed [RES-1:0] in,
input [RES-1:0] lim,
output signed [RES-1:0] out
); |
wire [RES-1:0] shifted_in_pos,shifted_in_neg, mask;
wire pos_sat, neg_sat;
assign mask = {RES{1'b1}}<<lim ;
assign shifted_in_pos = in>>lim ;
assign shifted_in_neg = (~in)>>lim ;
assign pos_sat = ( 2'b01 == { in[RES-1] , |shifted_in_pos } ) ;
assign neg_sat = ( 2'b11 == { in[RES-1] , |shifted_in_neg } ) ;
assign out = pos_sat ? ( ~mask ) :
neg_sat ? mask :
in ;
endmodule | 21 |
5,170 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/satprotect.v | 113,454,857 | satprotect.v | v | 81 | 115 | [] | [] | [] | [(25, 48)] | null | data/verilator_xmls/578ab853-b3ea-41b5-998f-a1debd8ed321.xml | null | 5,614 | module | module satprotect #(
parameter Ri = 15,
parameter Ro = 14,
parameter SAT = 14
)
(
input signed [Ri-1:0] in,
output signed [Ro-1:0] out
);
wire pos_sat, neg_sat;
assign pos_sat = ( ~in[Ri-1] ) & ( |in[Ri-2:SAT-1] );
assign neg_sat = ( in[Ri-1] ) & ( ~ ( &in[Ri-2:SAT-1] ) );
generate
if (SAT<Ro)
assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-SAT+1{in[Ri-1]}} , {SAT-2{~in[Ri-1]}} } : in[Ro-1:0] ;
else
assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-1{~in[Ri-1]}} } : in[Ro-1:0] ;
endgenerate
endmodule | module satprotect #(
parameter Ri = 15,
parameter Ro = 14,
parameter SAT = 14
)
(
input signed [Ri-1:0] in,
output signed [Ro-1:0] out
); |
wire pos_sat, neg_sat;
assign pos_sat = ( ~in[Ri-1] ) & ( |in[Ri-2:SAT-1] );
assign neg_sat = ( in[Ri-1] ) & ( ~ ( &in[Ri-2:SAT-1] ) );
generate
if (SAT<Ro)
assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-SAT+1{in[Ri-1]}} , {SAT-2{~in[Ri-1]}} } : in[Ro-1:0] ;
else
assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-1{~in[Ri-1]}} } : in[Ro-1:0] ;
endgenerate
endmodule | 21 |
5,172 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v | 113,454,857 | sq_mult.v | v | 52 | 94 | [] | [] | [] | [(26, 43)] | null | null | 1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v:29: syntax error, unexpected ref, expecting '['\n input ref,\n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v:36: syntax error, unexpected assign\n assign plus_in = in ;\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 5,616 | module | module sq_mult #(parameter R=14)
(
input clk,rst,
input ref,
input signed [ R-1:0] in,
output signed [ R-1:0] out
);
wire signed [R-1:0] plus_in, minus_in ;
assign plus_in = in ;
assign minus_in = {R{1'b0}}-$signed(in) ;
assign out = ref ? plus_in : minus_in ;
endmodule | module sq_mult #(parameter R=14)
(
input clk,rst,
input ref,
input signed [ R-1:0] in,
output signed [ R-1:0] out
); |
wire signed [R-1:0] plus_in, minus_in ;
assign plus_in = in ;
assign minus_in = {R{1'b0}}-$signed(in) ;
assign out = ref ? plus_in : minus_in ;
endmodule | 21 |
5,175 | data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/trigger_input.v | 113,454,857 | trigger_input.v | v | 78 | 87 | [] | [] | [] | [(11, 77)] | null | data/verilator_xmls/8cae53e5-b5f6-4dcc-bacb-8b337be9eb5d.xml | null | 5,619 | module | module trigger_input
#(parameter R=8 , N=3)
(
input wire clk, rst,
input wire [R-1:0] trig_in,
input wire [R-1:0] trig_sel,
output wire trig_tick
);
reg [N-1:0] cnt;
reg [N-1:0] cnt_next;
reg [2-1:0] state, state_next;
reg tirgger_now, tirgger_last;
localparam [2-1:0]
idle = 2'd0,
wait1 = 2'd1;
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}} ;
state <= 0 ;
tirgger_now <= 0 ;
tirgger_last <= 0 ;
end
else begin
cnt <= cnt_next;
state <= state_next ;
tirgger_now <= |(trig_in & trig_sel) ;
tirgger_last <= tirgger_now ;
end
always @*
begin
if(state==idle) begin
if( {tirgger_now,tirgger_last}==2'b10) begin
state_next = wait1;
cnt_next = { {N-1{1'b0}} , 1'b1 };
end
else begin
state_next = idle ;
cnt_next = {N{1'b0}};
end
end
else begin
if( &cnt ) begin
state_next = idle ;
cnt_next = {N{1'b0}};
end
else begin
state_next = wait1;
cnt_next = cnt + 1'b1 ;
end
end
end
assign trig_tick = (state==wait1) ;
endmodule | module trigger_input
#(parameter R=8 , N=3)
(
input wire clk, rst,
input wire [R-1:0] trig_in,
input wire [R-1:0] trig_sel,
output wire trig_tick
); |
reg [N-1:0] cnt;
reg [N-1:0] cnt_next;
reg [2-1:0] state, state_next;
reg tirgger_now, tirgger_last;
localparam [2-1:0]
idle = 2'd0,
wait1 = 2'd1;
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}} ;
state <= 0 ;
tirgger_now <= 0 ;
tirgger_last <= 0 ;
end
else begin
cnt <= cnt_next;
state <= state_next ;
tirgger_now <= |(trig_in & trig_sel) ;
tirgger_last <= tirgger_now ;
end
always @*
begin
if(state==idle) begin
if( {tirgger_now,tirgger_last}==2'b10) begin
state_next = wait1;
cnt_next = { {N-1{1'b0}} , 1'b1 };
end
else begin
state_next = idle ;
cnt_next = {N{1'b0}};
end
end
else begin
if( &cnt ) begin
state_next = idle ;
cnt_next = {N{1'b0}};
end
else begin
state_next = wait1;
cnt_next = cnt + 1'b1 ;
end
end
end
assign trig_tick = (state==wait1) ;
endmodule | 21 |
5,178 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv | 113,454,857 | axi_slave_tb.sv | sv | 272 | 138 | [] | [] | [] | null | line:238: before: "(" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:238: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:243: Unsupported: Ignoring delay on this delayed statement.\nalways #5 axi_aclk = !axi_aclk ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:252: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h20, 32\'h33445566, 12\'h0, 3\'h2, 2\'h0, 3\'b010, resp); \n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:250: Unsupported: wait statements\n wait (axi_arstn)\n ^~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:253: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h00, 32\'h66666666, 12\'h0, 3\'h2, 2\'h0, 3\'b010, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:254: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h04, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:255: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h00, 12\'h0, 3\'h1, 2\'h0, 3\'b010, rdat, resp); \n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:256: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h14, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp); \n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:258: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h04, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:259: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h00, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:260: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h04, 32\'h00000000, 12\'h0, 3\'h1, 2\'h0, 3\'b010, resp); \n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:261: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h04, 32\'h00000444, 12\'h0, 3\'h2, 2\'h0, 3\'b010, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:262: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h04, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:264: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.rd_single(32\'h08, 12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:265: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h00, 32\'h33445566, 12\'h0, 3\'h2, 2\'h0, 3\'b010, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:266: syntax error, unexpected \'@\'\n repeat(10) @(posedge axi_aclk); master.wr_single(32\'h08, 32\'h00000606, 12\'h0, 3\'h2, 2\'h0, 3\'b010, resp);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:268: syntax error, unexpected \'@\'\n repeat(20000) @(posedge axi_aclk);\n ^\n%Error: Exiting due to 16 error(s), 1 warning(s)\n' | 5,621 | module | module axi_slave_tb ();
wire axi_arvalid ;
wire axi_awvalid ;
wire axi_bready ;
wire axi_rready ;
wire axi_wlast ;
wire axi_wvalid ;
wire [ 12-1: 0] axi_arid ;
wire [ 12-1: 0] axi_awid ;
wire [ 12-1: 0] axi_wid ;
wire [ 2-1: 0] axi_arburst ;
wire [ 2-1: 0] axi_arlock ;
wire [ 3-1: 0] axi_arsize ;
wire [ 2-1: 0] axi_awburst ;
wire [ 2-1: 0] axi_awlock ;
wire [ 3-1: 0] axi_awsize ;
wire [ 3-1: 0] axi_arprot ;
wire [ 3-1: 0] axi_awprot ;
wire [ 32-1: 0] axi_araddr ;
wire [ 32-1: 0] axi_awaddr ;
wire [ 32-1: 0] axi_wdata ;
wire [ 4-1: 0] axi_arcache ;
wire [ 4-1: 0] axi_arlen ;
wire [ 4-1: 0] axi_arqos ;
wire [ 4-1: 0] axi_awcache ;
wire [ 4-1: 0] axi_awlen ;
wire [ 4-1: 0] axi_awqos ;
wire [ 4-1: 0] axi_wstrb ;
reg axi_aclk ;
wire axi_arready ;
wire axi_awready ;
wire axi_bvalid ;
wire axi_rlast ;
wire axi_rvalid ;
wire axi_wready ;
wire [ 12-1: 0] axi_bid ;
wire [ 12-1: 0] axi_rid ;
wire [ 2-1: 0] axi_bresp ;
wire [ 2-1: 0] axi_rresp ;
wire [ 32-1: 0] axi_rdata ;
reg axi_arstn ;
wire sys_clk ;
wire sys_rstn ;
wire [ 32-1: 0] sys_addr ;
wire [ 32-1: 0] sys_wdata ;
wire [ 4-1: 0] sys_sel ;
wire sys_wen ;
wire sys_ren ;
reg [ 32-1: 0] sys_rdata ;
reg sys_err ;
reg sys_ack ;
axi_master_model #(
.AW ( 32 ),
.DW ( 32 ),
.IW ( 12 ),
.LW ( 4 )
) master (
.aclk_i ( axi_aclk ),
.arstn_i ( axi_arstn ),
.awid_o ( axi_awid ),
.awlen_o ( axi_awlen ),
.awsize_o ( axi_awsize ),
.awburst_o ( axi_awburst ),
.awcache_o ( axi_awcache ),
.awaddr_o ( axi_awaddr ),
.awprot_o ( axi_awprot ),
.awvalid_o ( axi_awvalid ),
.awready_i ( axi_awready ),
.awlock_o ( axi_awlock ),
.wdata_o ( axi_wdata ),
.wstrb_o ( axi_wstrb ),
.wlast_o ( axi_wlast ),
.wvalid_o ( axi_wvalid ),
.wready_i ( axi_wready ),
.bid_i ( axi_bid ),
.bresp_i ( axi_bresp ),
.bvalid_i ( axi_bvalid ),
.bready_o ( axi_bready ),
.arid_o ( axi_arid ),
.arlen_o ( axi_arlen ),
.arsize_o ( axi_arsize ),
.arburst_o ( axi_arburst ),
.arprot_o ( axi_arprot ),
.arcache_o ( axi_arcache ),
.arvalid_o ( axi_arvalid ),
.araddr_o ( axi_araddr ),
.arlock_o ( axi_arlock ),
.arready_i ( axi_arready ),
.rid_i ( axi_rid ),
.rdata_i ( axi_rdata ),
.rresp_i ( axi_rresp ),
.rvalid_i ( axi_rvalid ),
.rlast_i ( axi_rlast ),
.rready_o ( axi_rready )
);
axi_slave #(
.AXI_DW ( 32 ),
.AXI_AW ( 32 ),
.AXI_IW ( 12 )
) slave (
.axi_clk_i ( axi_aclk ),
.axi_rstn_i ( axi_arstn ),
.axi_awid_i ( axi_awid ),
.axi_awaddr_i ( axi_awaddr ),
.axi_awlen_i ( axi_awlen ),
.axi_awsize_i ( axi_awsize ),
.axi_awburst_i ( axi_awburst ),
.axi_awlock_i ( axi_awlock ),
.axi_awcache_i ( axi_awcache ),
.axi_awprot_i ( axi_awprot ),
.axi_awvalid_i ( axi_awvalid ),
.axi_awready_o ( axi_awready ),
.axi_wid_i ( axi_wid ),
.axi_wdata_i ( axi_wdata ),
.axi_wstrb_i ( axi_wstrb ),
.axi_wlast_i ( axi_wlast ),
.axi_wvalid_i ( axi_wvalid ),
.axi_wready_o ( axi_wready ),
.axi_bid_o ( axi_bid ),
.axi_bresp_o ( axi_bresp ),
.axi_bvalid_o ( axi_bvalid ),
.axi_bready_i ( axi_bready ),
.axi_arid_i ( axi_arid ),
.axi_araddr_i ( axi_araddr ),
.axi_arlen_i ( axi_arlen ),
.axi_arsize_i ( axi_arsize ),
.axi_arburst_i ( axi_arburst ),
.axi_arlock_i ( axi_arlock ),
.axi_arcache_i ( axi_arcache ),
.axi_arprot_i ( axi_arprot ),
.axi_arvalid_i ( axi_arvalid ),
.axi_arready_o ( axi_arready ),
.axi_rid_o ( axi_rid ),
.axi_rdata_o ( axi_rdata ),
.axi_rresp_o ( axi_rresp ),
.axi_rlast_o ( axi_rlast ),
.axi_rvalid_o ( axi_rvalid ),
.axi_rready_i ( axi_rready ),
.sys_addr_o ( sys_addr ),
.sys_wdata_o ( sys_wdata ),
.sys_sel_o ( sys_sel ),
.sys_wen_o ( sys_wen ),
.sys_ren_o ( sys_ren ),
.sys_rdata_i ( sys_rdata ),
.sys_err_i ( sys_err ),
.sys_ack_i ( sys_ack )
);
assign sys_clk = axi_aclk ;
assign sys_rstn = axi_arstn ;
logic [ 4-1: 0] rd_ack ;
logic [ 32-1: 0] reg_a ;
logic [ 32-1: 0] reg_b ;
logic [ 32-1: 0] reg_c ;
always @(posedge sys_clk)
if (sys_rstn == 1'b0) begin
rd_ack <= 4'h0 ;
reg_a <= 32'h0 ;
reg_b <= 32'h12345678 ;
reg_c <= 32'h505 ;
end else begin
rd_ack <= {rd_ack[2:0], (sys_ren || sys_wen)};
if (sys_wen && (sys_addr[9:0]==10'h0)) reg_a <= sys_wdata ;
if (sys_wen && (sys_addr[9:0]==10'h4)) reg_b <= sys_wdata ;
if (sys_wen && (sys_addr[9:0]==10'h8)) reg_c <= sys_wdata ;
end
always_comb
begin
sys_err = 1'b0 ;
casez (sys_addr[9:0])
10'h0 : begin sys_ack = 1'b1; sys_rdata = reg_a ; end
10'h4 : begin sys_ack = rd_ack[3]; sys_rdata = reg_b ; end
10'h8 : begin sys_ack = 1'b1; sys_rdata = reg_c ; end
default : begin sys_ack = 1'b0; sys_rdata = 32'h0 ; end
endcase
end
initial
begin
axi_arstn = 1'b0;
repeat(10) @(posedge axi_aclk);
axi_arstn = 1'b1;
end
initial axi_aclk = 1'b0;
always #5 axi_aclk = !axi_aclk ;
reg [32-1: 0] rdat ;
reg [ 2-1: 0] resp ;
initial
begin
wait (axi_arstn)
repeat(10) @(posedge axi_aclk); master.wr_single(32'h20, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h00, 32'h66666666, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h00, 12'h0, 3'h1, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h14, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h00, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h04, 32'h00000000, 12'h0, 3'h1, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h04, 32'h00000444, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h08, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h00, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h08, 32'h00000606, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(20000) @(posedge axi_aclk);
end
endmodule | module axi_slave_tb (); |
wire axi_arvalid ;
wire axi_awvalid ;
wire axi_bready ;
wire axi_rready ;
wire axi_wlast ;
wire axi_wvalid ;
wire [ 12-1: 0] axi_arid ;
wire [ 12-1: 0] axi_awid ;
wire [ 12-1: 0] axi_wid ;
wire [ 2-1: 0] axi_arburst ;
wire [ 2-1: 0] axi_arlock ;
wire [ 3-1: 0] axi_arsize ;
wire [ 2-1: 0] axi_awburst ;
wire [ 2-1: 0] axi_awlock ;
wire [ 3-1: 0] axi_awsize ;
wire [ 3-1: 0] axi_arprot ;
wire [ 3-1: 0] axi_awprot ;
wire [ 32-1: 0] axi_araddr ;
wire [ 32-1: 0] axi_awaddr ;
wire [ 32-1: 0] axi_wdata ;
wire [ 4-1: 0] axi_arcache ;
wire [ 4-1: 0] axi_arlen ;
wire [ 4-1: 0] axi_arqos ;
wire [ 4-1: 0] axi_awcache ;
wire [ 4-1: 0] axi_awlen ;
wire [ 4-1: 0] axi_awqos ;
wire [ 4-1: 0] axi_wstrb ;
reg axi_aclk ;
wire axi_arready ;
wire axi_awready ;
wire axi_bvalid ;
wire axi_rlast ;
wire axi_rvalid ;
wire axi_wready ;
wire [ 12-1: 0] axi_bid ;
wire [ 12-1: 0] axi_rid ;
wire [ 2-1: 0] axi_bresp ;
wire [ 2-1: 0] axi_rresp ;
wire [ 32-1: 0] axi_rdata ;
reg axi_arstn ;
wire sys_clk ;
wire sys_rstn ;
wire [ 32-1: 0] sys_addr ;
wire [ 32-1: 0] sys_wdata ;
wire [ 4-1: 0] sys_sel ;
wire sys_wen ;
wire sys_ren ;
reg [ 32-1: 0] sys_rdata ;
reg sys_err ;
reg sys_ack ;
axi_master_model #(
.AW ( 32 ),
.DW ( 32 ),
.IW ( 12 ),
.LW ( 4 )
) master (
.aclk_i ( axi_aclk ),
.arstn_i ( axi_arstn ),
.awid_o ( axi_awid ),
.awlen_o ( axi_awlen ),
.awsize_o ( axi_awsize ),
.awburst_o ( axi_awburst ),
.awcache_o ( axi_awcache ),
.awaddr_o ( axi_awaddr ),
.awprot_o ( axi_awprot ),
.awvalid_o ( axi_awvalid ),
.awready_i ( axi_awready ),
.awlock_o ( axi_awlock ),
.wdata_o ( axi_wdata ),
.wstrb_o ( axi_wstrb ),
.wlast_o ( axi_wlast ),
.wvalid_o ( axi_wvalid ),
.wready_i ( axi_wready ),
.bid_i ( axi_bid ),
.bresp_i ( axi_bresp ),
.bvalid_i ( axi_bvalid ),
.bready_o ( axi_bready ),
.arid_o ( axi_arid ),
.arlen_o ( axi_arlen ),
.arsize_o ( axi_arsize ),
.arburst_o ( axi_arburst ),
.arprot_o ( axi_arprot ),
.arcache_o ( axi_arcache ),
.arvalid_o ( axi_arvalid ),
.araddr_o ( axi_araddr ),
.arlock_o ( axi_arlock ),
.arready_i ( axi_arready ),
.rid_i ( axi_rid ),
.rdata_i ( axi_rdata ),
.rresp_i ( axi_rresp ),
.rvalid_i ( axi_rvalid ),
.rlast_i ( axi_rlast ),
.rready_o ( axi_rready )
);
axi_slave #(
.AXI_DW ( 32 ),
.AXI_AW ( 32 ),
.AXI_IW ( 12 )
) slave (
.axi_clk_i ( axi_aclk ),
.axi_rstn_i ( axi_arstn ),
.axi_awid_i ( axi_awid ),
.axi_awaddr_i ( axi_awaddr ),
.axi_awlen_i ( axi_awlen ),
.axi_awsize_i ( axi_awsize ),
.axi_awburst_i ( axi_awburst ),
.axi_awlock_i ( axi_awlock ),
.axi_awcache_i ( axi_awcache ),
.axi_awprot_i ( axi_awprot ),
.axi_awvalid_i ( axi_awvalid ),
.axi_awready_o ( axi_awready ),
.axi_wid_i ( axi_wid ),
.axi_wdata_i ( axi_wdata ),
.axi_wstrb_i ( axi_wstrb ),
.axi_wlast_i ( axi_wlast ),
.axi_wvalid_i ( axi_wvalid ),
.axi_wready_o ( axi_wready ),
.axi_bid_o ( axi_bid ),
.axi_bresp_o ( axi_bresp ),
.axi_bvalid_o ( axi_bvalid ),
.axi_bready_i ( axi_bready ),
.axi_arid_i ( axi_arid ),
.axi_araddr_i ( axi_araddr ),
.axi_arlen_i ( axi_arlen ),
.axi_arsize_i ( axi_arsize ),
.axi_arburst_i ( axi_arburst ),
.axi_arlock_i ( axi_arlock ),
.axi_arcache_i ( axi_arcache ),
.axi_arprot_i ( axi_arprot ),
.axi_arvalid_i ( axi_arvalid ),
.axi_arready_o ( axi_arready ),
.axi_rid_o ( axi_rid ),
.axi_rdata_o ( axi_rdata ),
.axi_rresp_o ( axi_rresp ),
.axi_rlast_o ( axi_rlast ),
.axi_rvalid_o ( axi_rvalid ),
.axi_rready_i ( axi_rready ),
.sys_addr_o ( sys_addr ),
.sys_wdata_o ( sys_wdata ),
.sys_sel_o ( sys_sel ),
.sys_wen_o ( sys_wen ),
.sys_ren_o ( sys_ren ),
.sys_rdata_i ( sys_rdata ),
.sys_err_i ( sys_err ),
.sys_ack_i ( sys_ack )
);
assign sys_clk = axi_aclk ;
assign sys_rstn = axi_arstn ;
logic [ 4-1: 0] rd_ack ;
logic [ 32-1: 0] reg_a ;
logic [ 32-1: 0] reg_b ;
logic [ 32-1: 0] reg_c ;
always @(posedge sys_clk)
if (sys_rstn == 1'b0) begin
rd_ack <= 4'h0 ;
reg_a <= 32'h0 ;
reg_b <= 32'h12345678 ;
reg_c <= 32'h505 ;
end else begin
rd_ack <= {rd_ack[2:0], (sys_ren || sys_wen)};
if (sys_wen && (sys_addr[9:0]==10'h0)) reg_a <= sys_wdata ;
if (sys_wen && (sys_addr[9:0]==10'h4)) reg_b <= sys_wdata ;
if (sys_wen && (sys_addr[9:0]==10'h8)) reg_c <= sys_wdata ;
end
always_comb
begin
sys_err = 1'b0 ;
casez (sys_addr[9:0])
10'h0 : begin sys_ack = 1'b1; sys_rdata = reg_a ; end
10'h4 : begin sys_ack = rd_ack[3]; sys_rdata = reg_b ; end
10'h8 : begin sys_ack = 1'b1; sys_rdata = reg_c ; end
default : begin sys_ack = 1'b0; sys_rdata = 32'h0 ; end
endcase
end
initial
begin
axi_arstn = 1'b0;
repeat(10) @(posedge axi_aclk);
axi_arstn = 1'b1;
end
initial axi_aclk = 1'b0;
always #5 axi_aclk = !axi_aclk ;
reg [32-1: 0] rdat ;
reg [ 2-1: 0] resp ;
initial
begin
wait (axi_arstn)
repeat(10) @(posedge axi_aclk); master.wr_single(32'h20, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h00, 32'h66666666, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h00, 12'h0, 3'h1, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h14, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h00, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h04, 32'h00000000, 12'h0, 3'h1, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h04, 32'h00000444, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h04, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.rd_single(32'h08, 12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h00, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(10) @(posedge axi_aclk); master.wr_single(32'h08, 32'h00000606, 12'h0, 3'h2, 2'h0, 3'b010, resp);
repeat(20000) @(posedge axi_aclk);
end
endmodule | 21 |
5,179 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv | 113,454,857 | pwm_tb.sv | sv | 82 | 81 | [] | [] | [] | null | line:11: before: "realtime" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:11: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n realtime TP = 4.0ns, \n ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:14: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n bit [CCW-1:0] CCE = 2**CCW-1 \n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:32: syntax error, unexpected initial\ninitial clk = 1\'h0;\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:43: syntax error, unexpected IDENTIFIER\n for (int unsigned i=0; i<=CCE; i++) begin\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:77: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("pwm_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:78: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, pwm_tb);\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 5,622 | module | module pwm_tb #(
realtime TP = 4.0ns,
int unsigned CCW = 4,
bit [CCW-1:0] CCE = 2**CCW-1
);
logic clk ;
logic rstn;
logic [CCW-1:0] str_dat;
logic str_rdy;
logic pwm;
initial clk = 1'h0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
str_dat = '0;
repeat(4) @(posedge clk);
rstn = 1'b1;
for (int unsigned i=0; i<=CCE; i++) begin
while (~str_rdy) @ (posedge clk);
str_dat <= i[CCW-1:0];
@ (posedge clk);
end
repeat(2*CCE+4) @(posedge clk);
$finish();
end
pwm #(
.CCW (CCW),
.CCE (CCE)
) dut (
.clk (clk ),
.rstn (rstn),
.str_dat (str_dat),
.str_rdy (str_rdy),
.pwm (pwm)
);
initial begin
$dumpfile("pwm_tb.vcd");
$dumpvars(0, pwm_tb);
end
endmodule | module pwm_tb #(
realtime TP = 4.0ns,
int unsigned CCW = 4,
bit [CCW-1:0] CCE = 2**CCW-1
); |
logic clk ;
logic rstn;
logic [CCW-1:0] str_dat;
logic str_rdy;
logic pwm;
initial clk = 1'h0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
str_dat = '0;
repeat(4) @(posedge clk);
rstn = 1'b1;
for (int unsigned i=0; i<=CCE; i++) begin
while (~str_rdy) @ (posedge clk);
str_dat <= i[CCW-1:0];
@ (posedge clk);
end
repeat(2*CCE+4) @(posedge clk);
$finish();
end
pwm #(
.CCW (CCW),
.CCE (CCE)
) dut (
.clk (clk ),
.rstn (rstn),
.str_dat (str_dat),
.str_rdy (str_rdy),
.pwm (pwm)
);
initial begin
$dumpfile("pwm_tb.vcd");
$dumpvars(0, pwm_tb);
end
endmodule | 21 |
5,182 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv | 113,454,857 | red_pitaya_dfilt1_tb.sv | sv | 132 | 124 | [] | [] | [] | null | line:29: before: "realtime" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:29: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n realtime TP = 8.0ns \n ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:40: syntax error, unexpected initial\ninitial clk = 1\'b0;\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:69: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:127: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("red_pitaya_dfilt1_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:128: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, red_pitaya_dfilt1_tb);\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 5,625 | module | module red_pitaya_dfilt1_tb #(
realtime TP = 8.0ns
);
logic clk ;
logic rstn;
initial clk = 1'b0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
repeat(4) @(posedge clk);
rstn = 1'b1;
end
logic [ 14-1: 0] adc_read ;
logic [ 14-1: 0] adc_in ;
logic [ 14-1: 0] adc_out ;
logic adc_clk ;
logic adc_rstn ;
logic [ 18-1: 0] cfg_aa ;
logic [ 25-1: 0] cfg_bb ;
logic [ 25-1: 0] cfg_kk ;
logic [ 25-1: 0] cfg_pp ;
integer fp1,fp2;
integer dummy;
initial begin
fp1 = $fopen("../../../../code/bench/dfilt1_sim_values.txt", "r");
fp2 = $fopen("../../../../code/bench/dfilt1_sim_output.txt", "w");
adc_read <= 14'h0 ;
adc_in <= 14'h0 ;
cfg_aa <= 18'd40724 ;
cfg_bb <= 25'd341536 ;
cfg_kk <= 25'd14260634 ;
cfg_pp <= 25'd9830 ;
wait (adc_rstn)
repeat(2) @(posedge adc_clk);
while ( !$feof(fp1) ) begin
@(posedge adc_clk);
dummy = $fscanf(fp1,"%d \n", adc_read);
end
repeat(2) @(posedge adc_clk);
$fclose(fp1);
end
always @(posedge adc_clk) begin
adc_in <= adc_read ;
if(adc_rstn == 1'b1) begin
$fwrite(fp2, "%d %d %d %d %d %d %d \n", $signed(i_filt1.r01_reg), $signed(i_filt1.r02_reg),
$signed(i_filt1.r1_reg), $signed(i_filt1.r2_reg),
$signed(i_filt1.r3_reg), $signed(i_filt1.r4_reg), $signed(i_filt1.r5_reg) ) ;
end
end
red_pitaya_dfilt1 i_filt1 (
.adc_clk_i ( adc_clk ),
.adc_rstn_i ( adc_rstn ),
.adc_dat_i ( adc_in ),
.adc_dat_o ( adc_out ),
.cfg_aa_i ( cfg_aa ),
.cfg_bb_i ( cfg_bb ),
.cfg_kk_i ( cfg_kk ),
.cfg_pp_i ( cfg_pp )
);
initial begin
$dumpfile("red_pitaya_dfilt1_tb.vcd");
$dumpvars(0, red_pitaya_dfilt1_tb);
end
endmodule | module red_pitaya_dfilt1_tb #(
realtime TP = 8.0ns
); |
logic clk ;
logic rstn;
initial clk = 1'b0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
repeat(4) @(posedge clk);
rstn = 1'b1;
end
logic [ 14-1: 0] adc_read ;
logic [ 14-1: 0] adc_in ;
logic [ 14-1: 0] adc_out ;
logic adc_clk ;
logic adc_rstn ;
logic [ 18-1: 0] cfg_aa ;
logic [ 25-1: 0] cfg_bb ;
logic [ 25-1: 0] cfg_kk ;
logic [ 25-1: 0] cfg_pp ;
integer fp1,fp2;
integer dummy;
initial begin
fp1 = $fopen("../../../../code/bench/dfilt1_sim_values.txt", "r");
fp2 = $fopen("../../../../code/bench/dfilt1_sim_output.txt", "w");
adc_read <= 14'h0 ;
adc_in <= 14'h0 ;
cfg_aa <= 18'd40724 ;
cfg_bb <= 25'd341536 ;
cfg_kk <= 25'd14260634 ;
cfg_pp <= 25'd9830 ;
wait (adc_rstn)
repeat(2) @(posedge adc_clk);
while ( !$feof(fp1) ) begin
@(posedge adc_clk);
dummy = $fscanf(fp1,"%d \n", adc_read);
end
repeat(2) @(posedge adc_clk);
$fclose(fp1);
end
always @(posedge adc_clk) begin
adc_in <= adc_read ;
if(adc_rstn == 1'b1) begin
$fwrite(fp2, "%d %d %d %d %d %d %d \n", $signed(i_filt1.r01_reg), $signed(i_filt1.r02_reg),
$signed(i_filt1.r1_reg), $signed(i_filt1.r2_reg),
$signed(i_filt1.r3_reg), $signed(i_filt1.r4_reg), $signed(i_filt1.r5_reg) ) ;
end
end
red_pitaya_dfilt1 i_filt1 (
.adc_clk_i ( adc_clk ),
.adc_rstn_i ( adc_rstn ),
.adc_dat_i ( adc_in ),
.adc_dat_o ( adc_out ),
.cfg_aa_i ( cfg_aa ),
.cfg_bb_i ( cfg_bb ),
.cfg_kk_i ( cfg_kk ),
.cfg_pp_i ( cfg_pp )
);
initial begin
$dumpfile("red_pitaya_dfilt1_tb.vcd");
$dumpvars(0, red_pitaya_dfilt1_tb);
end
endmodule | 21 |
5,187 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv | 113,454,857 | red_pitaya_scope_tb.sv | sv | 257 | 138 | [] | [] | [] | null | line:40: before: "realtime" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:40: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n realtime TP = 8.0ns, \n ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:43: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n int unsigned RSZ = 14 \n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:44: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:65: syntax error, unexpected assign\nassign adc_a = saw_a(adc_cyc);\n^~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:81: syntax error, unexpected always_ff\nalways_ff @ (posedge clk)\n^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:109: Unsupported: Dynamic array new\n rdata_blk = new [len];\n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:116: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:252: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("red_pitaya_scope_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:253: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, red_pitaya_scope_tb);\n ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 5,630 | module | module red_pitaya_scope_tb #(
realtime TP = 8.0ns,
int unsigned ADC_DW = 14,
int unsigned RSZ = 14
);
function [ADC_DW-1:0] saw_a (input int unsigned cyc);
saw_a = ADC_DW'(cyc*23);
endfunction: saw_a
function [ADC_DW-1:0] saw_b (input int unsigned cyc);
cyc = cyc % (2**ADC_DW/5);
saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction: saw_b
logic clk ;
logic rstn;
logic [ADC_DW-1:0] adc_a;
logic [ADC_DW-1:0] adc_b;
assign adc_a = saw_a(adc_cyc);
assign adc_b = saw_b(adc_cyc);
initial clk = 1'b0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
repeat(4) @(posedge clk);
rstn = 1'b1;
end
int unsigned adc_cyc=0;
always_ff @ (posedge clk)
adc_cyc <= adc_cyc+1;
logic trig_ext ;
logic [ 32-1: 0] sys_addr ;
logic [ 32-1: 0] sys_wdata;
logic [ 4-1: 0] sys_sel ;
logic sys_wen ;
logic sys_ren ;
logic [ 32-1: 0] sys_rdata;
logic sys_err ;
logic sys_ack ;
logic [ 32-1: 0] rdata;
logic signed [ 32-1: 0] rdata_blk [];
bit signed [ 32-1: 0] rdata_ref [];
int unsigned rdata_trg [$];
int unsigned blk_size;
task read_blk (
input int adr,
input int unsigned len
);
rdata_blk = new [len];
for (int unsigned i=0; i<len; i++) begin
bus.read(adr+4*i, rdata_blk[i]);
end
endtask: read_blk
initial begin
trig_ext = 1'b0;
blk_size = 20;
wait (rstn)
repeat(10) @(posedge clk);
bus.write(32'h14, 32'd1 );
bus.write(32'h08,-32'd0000 );
bus.write(32'h0C,-32'd7000 );
bus.write(32'h20, 32'd20 );
bus.write(32'h24, 32'd200 );
bus.write(32'h50, 32'd0100);
bus.write(32'h54, 32'd0200);
bus.write(32'h70, 32'd0100);
bus.write(32'h74, 32'd0200);
bus.write(32'h10, blk_size );
fork
begin: scope_trg
repeat(20) @(posedge clk); trig_ext = 1'b1;
repeat( 1) @(posedge clk); trig_ext = 1'b0;
end
begin: scope_run
do begin
bus.read(32'h94, rdata);
repeat(20) @(posedge clk);
end while (rdata & 2);
repeat(20) @(posedge clk);
read_blk (32'h30000, blk_size);
$display ("trigger positions: %p", rdata_trg);
$display ("data reference: %p", rdata_ref);
$display ("data read : %p", rdata_blk);
if (rdata_ref == rdata_blk) $display ("SUCCESS");
else $display ("FAILURE");
end
join
repeat(100) @(posedge clk);
$finish ();
end
sys_bus_model bus (
.clk (clk ),
.rstn (rstn ),
.sys_addr (sys_addr ),
.sys_wdata (sys_wdata),
.sys_sel (sys_sel ),
.sys_wen (sys_wen ),
.sys_ren (sys_ren ),
.sys_rdata (sys_rdata),
.sys_err (sys_err ),
.sys_ack (sys_ack )
);
red_pitaya_scope #(
.RSZ (RSZ)
) scope (
.adc_clk_i (clk ),
.adc_rstn_i (rstn ),
.adc_a_i (adc_a ),
.adc_b_i (adc_b ),
.trig_ext_i (trig_ext ),
.trig_asg_i (trig_ext ),
.axi0_clk_o ( ), .axi1_clk_o ( ),
.axi0_rstn_o ( ), .axi1_rstn_o ( ),
.axi0_waddr_o ( ), .axi1_waddr_o ( ),
.axi0_wdata_o ( ), .axi1_wdata_o ( ),
.axi0_wsel_o ( ), .axi1_wsel_o ( ),
.axi0_wvalid_o ( ), .axi1_wvalid_o ( ),
.axi0_wlen_o ( ), .axi1_wlen_o ( ),
.axi0_wfixed_o ( ), .axi1_wfixed_o ( ),
.axi0_werr_i (1'b0), .axi1_werr_i (1'b0),
.axi0_wrdy_i (1'b1), .axi1_wrdy_i (1'b1),
.sys_addr (sys_addr ),
.sys_wdata (sys_wdata),
.sys_sel (sys_sel ),
.sys_wen (sys_wen ),
.sys_ren (sys_ren ),
.sys_rdata (sys_rdata),
.sys_err (sys_err ),
.sys_ack (sys_ack )
);
initial begin
$dumpfile("red_pitaya_scope_tb.vcd");
$dumpvars(0, red_pitaya_scope_tb);
end
endmodule | module red_pitaya_scope_tb #(
realtime TP = 8.0ns,
int unsigned ADC_DW = 14,
int unsigned RSZ = 14
); |
function [ADC_DW-1:0] saw_a (input int unsigned cyc);
saw_a = ADC_DW'(cyc*23);
endfunction: saw_a
function [ADC_DW-1:0] saw_b (input int unsigned cyc);
cyc = cyc % (2**ADC_DW/5);
saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction: saw_b
logic clk ;
logic rstn;
logic [ADC_DW-1:0] adc_a;
logic [ADC_DW-1:0] adc_b;
assign adc_a = saw_a(adc_cyc);
assign adc_b = saw_b(adc_cyc);
initial clk = 1'b0;
always #(TP/2) clk = ~clk;
initial begin
rstn = 1'b0;
repeat(4) @(posedge clk);
rstn = 1'b1;
end
int unsigned adc_cyc=0;
always_ff @ (posedge clk)
adc_cyc <= adc_cyc+1;
logic trig_ext ;
logic [ 32-1: 0] sys_addr ;
logic [ 32-1: 0] sys_wdata;
logic [ 4-1: 0] sys_sel ;
logic sys_wen ;
logic sys_ren ;
logic [ 32-1: 0] sys_rdata;
logic sys_err ;
logic sys_ack ;
logic [ 32-1: 0] rdata;
logic signed [ 32-1: 0] rdata_blk [];
bit signed [ 32-1: 0] rdata_ref [];
int unsigned rdata_trg [$];
int unsigned blk_size;
task read_blk (
input int adr,
input int unsigned len
);
rdata_blk = new [len];
for (int unsigned i=0; i<len; i++) begin
bus.read(adr+4*i, rdata_blk[i]);
end
endtask: read_blk
initial begin
trig_ext = 1'b0;
blk_size = 20;
wait (rstn)
repeat(10) @(posedge clk);
bus.write(32'h14, 32'd1 );
bus.write(32'h08,-32'd0000 );
bus.write(32'h0C,-32'd7000 );
bus.write(32'h20, 32'd20 );
bus.write(32'h24, 32'd200 );
bus.write(32'h50, 32'd0100);
bus.write(32'h54, 32'd0200);
bus.write(32'h70, 32'd0100);
bus.write(32'h74, 32'd0200);
bus.write(32'h10, blk_size );
fork
begin: scope_trg
repeat(20) @(posedge clk); trig_ext = 1'b1;
repeat( 1) @(posedge clk); trig_ext = 1'b0;
end
begin: scope_run
do begin
bus.read(32'h94, rdata);
repeat(20) @(posedge clk);
end while (rdata & 2);
repeat(20) @(posedge clk);
read_blk (32'h30000, blk_size);
$display ("trigger positions: %p", rdata_trg);
$display ("data reference: %p", rdata_ref);
$display ("data read : %p", rdata_blk);
if (rdata_ref == rdata_blk) $display ("SUCCESS");
else $display ("FAILURE");
end
join
repeat(100) @(posedge clk);
$finish ();
end
sys_bus_model bus (
.clk (clk ),
.rstn (rstn ),
.sys_addr (sys_addr ),
.sys_wdata (sys_wdata),
.sys_sel (sys_sel ),
.sys_wen (sys_wen ),
.sys_ren (sys_ren ),
.sys_rdata (sys_rdata),
.sys_err (sys_err ),
.sys_ack (sys_ack )
);
red_pitaya_scope #(
.RSZ (RSZ)
) scope (
.adc_clk_i (clk ),
.adc_rstn_i (rstn ),
.adc_a_i (adc_a ),
.adc_b_i (adc_b ),
.trig_ext_i (trig_ext ),
.trig_asg_i (trig_ext ),
.axi0_clk_o ( ), .axi1_clk_o ( ),
.axi0_rstn_o ( ), .axi1_rstn_o ( ),
.axi0_waddr_o ( ), .axi1_waddr_o ( ),
.axi0_wdata_o ( ), .axi1_wdata_o ( ),
.axi0_wsel_o ( ), .axi1_wsel_o ( ),
.axi0_wvalid_o ( ), .axi1_wvalid_o ( ),
.axi0_wlen_o ( ), .axi1_wlen_o ( ),
.axi0_wfixed_o ( ), .axi1_wfixed_o ( ),
.axi0_werr_i (1'b0), .axi1_werr_i (1'b0),
.axi0_wrdy_i (1'b1), .axi1_wrdy_i (1'b1),
.sys_addr (sys_addr ),
.sys_wdata (sys_wdata),
.sys_sel (sys_sel ),
.sys_wen (sys_wen ),
.sys_ren (sys_ren ),
.sys_rdata (sys_rdata),
.sys_err (sys_err ),
.sys_ack (sys_ack )
);
initial begin
$dumpfile("red_pitaya_scope_tb.vcd");
$dumpvars(0, red_pitaya_scope_tb);
end
endmodule | 21 |
5,188 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv | 113,454,857 | red_pitaya_scope_tb.sv | sv | 257 | 138 | [] | [] | [] | null | line:40: before: "realtime" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:40: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n realtime TP = 8.0ns, \n ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:43: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n int unsigned RSZ = 14 \n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:44: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:65: syntax error, unexpected assign\nassign adc_a = saw_a(adc_cyc);\n^~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:81: syntax error, unexpected always_ff\nalways_ff @ (posedge clk)\n^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:109: Unsupported: Dynamic array new\n rdata_blk = new [len];\n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:116: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:252: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("red_pitaya_scope_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:253: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, red_pitaya_scope_tb);\n ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 5,630 | function | function [ADC_DW-1:0] saw_a (input int unsigned cyc);
saw_a = ADC_DW'(cyc*23);
endfunction | function [ADC_DW-1:0] saw_a (input int unsigned cyc); |
saw_a = ADC_DW'(cyc*23);
endfunction | 21 |
5,189 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv | 113,454,857 | red_pitaya_scope_tb.sv | sv | 257 | 138 | [] | [] | [] | null | line:40: before: "realtime" | null | 1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:40: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n realtime TP = 8.0ns, \n ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:43: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n int unsigned RSZ = 14 \n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:44: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:65: syntax error, unexpected assign\nassign adc_a = saw_a(adc_cyc);\n^~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:81: syntax error, unexpected always_ff\nalways_ff @ (posedge clk)\n^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:109: Unsupported: Dynamic array new\n rdata_blk = new [len];\n ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:116: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:252: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("red_pitaya_scope_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:253: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, red_pitaya_scope_tb);\n ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 5,630 | function | function [ADC_DW-1:0] saw_b (input int unsigned cyc);
cyc = cyc % (2**ADC_DW/5);
saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction | function [ADC_DW-1:0] saw_b (input int unsigned cyc); |
cyc = cyc % (2**ADC_DW/5);
saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction | 21 |
5,191 | data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv | 113,454,857 | sys_bus_model.sv | sv | 92 | 80 | [] | [] | [] | null | line:29: before: "int" | null | 1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:59: syntax error, unexpected '@'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:65: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:69: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:71: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: Exiting due to 4 error(s)\n" | 5,632 | module | module sys_bus_model #(
int unsigned AXI_DW = 32 ,
int unsigned AXI_AW = 32 ,
int unsigned AXI_SW = AXI_DW/8
)(
input logic clk ,
input logic rstn ,
output logic [AXI_AW-1:0] sys_addr ,
output logic [AXI_DW-1:0] sys_wdata,
output logic [AXI_SW-1:0] sys_sel ,
output logic sys_wen ,
output logic sys_ren ,
input logic [AXI_DW-1:0] sys_rdata,
input logic sys_err ,
input logic sys_ack
);
initial begin
sys_wen <= 1'b0 ;
sys_ren <= 1'b0 ;
end
task transaction (
input logic we,
input logic [32-1:0] addr,
input logic [32-1:0] wdata,
output logic [32-1:0] rdata
);
@(posedge clk)
sys_sel <= '1;
sys_wen <= we ;
sys_ren <= ~we ;
sys_addr <= addr ;
sys_wdata <= wdata ;
@(posedge clk);
sys_wen <= 1'b0 ;
sys_ren <= 1'b0 ;
while (~sys_ack & ~sys_err)
@(posedge clk);
rdata <= sys_rdata ;
@(posedge clk);
endtask: transaction
task write (
input logic [32-1:0] addr,
input logic [32-1:0] wdata
);
logic [32-1:0] rdata;
transaction (.we (1'b1), .addr (addr), .wdata (wdata), .rdata (rdata));
endtask: write
task read (
input logic [32-1:0] addr,
output logic [32-1:0] rdata
);
transaction (.we (1'b0), .addr (addr), .wdata (32'hx), .rdata (rdata));
endtask: read
endmodule | module sys_bus_model #(
int unsigned AXI_DW = 32 ,
int unsigned AXI_AW = 32 ,
int unsigned AXI_SW = AXI_DW/8
)(
input logic clk ,
input logic rstn ,
output logic [AXI_AW-1:0] sys_addr ,
output logic [AXI_DW-1:0] sys_wdata,
output logic [AXI_SW-1:0] sys_sel ,
output logic sys_wen ,
output logic sys_ren ,
input logic [AXI_DW-1:0] sys_rdata,
input logic sys_err ,
input logic sys_ack
); |
initial begin
sys_wen <= 1'b0 ;
sys_ren <= 1'b0 ;
end
task transaction (
input logic we,
input logic [32-1:0] addr,
input logic [32-1:0] wdata,
output logic [32-1:0] rdata
);
@(posedge clk)
sys_sel <= '1;
sys_wen <= we ;
sys_ren <= ~we ;
sys_addr <= addr ;
sys_wdata <= wdata ;
@(posedge clk);
sys_wen <= 1'b0 ;
sys_ren <= 1'b0 ;
while (~sys_ack & ~sys_err)
@(posedge clk);
rdata <= sys_rdata ;
@(posedge clk);
endtask: transaction
task write (
input logic [32-1:0] addr,
input logic [32-1:0] wdata
);
logic [32-1:0] rdata;
transaction (.we (1'b1), .addr (addr), .wdata (wdata), .rdata (rdata));
endtask: write
task read (
input logic [32-1:0] addr,
output logic [32-1:0] rdata
);
transaction (.we (1'b0), .addr (addr), .wdata (32'hx), .rdata (rdata));
endtask: read
endmodule | 21 |
5,192 | data/full_repos/permissive/113471686/baseline/freq/freq.v | 113,471,686 | freq.v | v | 57 | 95 | [] | [] | [] | [(16, 54)] | null | null | 1: b"%Error: data/full_repos/permissive/113471686/baseline/freq/freq.v:43: Cannot find file containing module: 'MERGE_SORTER_TREE'\n MERGE_SORTER_TREE #(9, 64, 32)\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE\n data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE.v\n data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE.sv\n MERGE_SORTER_TREE\n MERGE_SORTER_TREE.v\n MERGE_SORTER_TREE.sv\n obj_dir/MERGE_SORTER_TREE\n obj_dir/MERGE_SORTER_TREE.v\n obj_dir/MERGE_SORTER_TREE.sv\n%Error: Exiting due to 1 error(s)\n" | 5,633 | module | module freq(input wire CLK,
input wire RST_IN,
output wire OUT);
reg RST; always @(posedge CLK) RST <= RST_IN;
wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_dinen;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_ful;
wire [`DATW-1:0] merge_sorter_tree_dot;
wire merge_sorter_tree_doten;
assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
end
assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
end
endgenerate
MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen,
merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);
reg [`DATW-1:0] dot_buf;
always @(posedge CLK) begin
if (merge_sorter_tree_doten) dot_buf <= merge_sorter_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | module freq(input wire CLK,
input wire RST_IN,
output wire OUT); |
reg RST; always @(posedge CLK) RST <= RST_IN;
wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_dinen;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_ful;
wire [`DATW-1:0] merge_sorter_tree_dot;
wire merge_sorter_tree_doten;
assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
end
assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
end
endgenerate
MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen,
merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);
reg [`DATW-1:0] dot_buf;
always @(posedge CLK) begin
if (merge_sorter_tree_doten) dot_buf <= merge_sorter_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | 0 |
5,193 | data/full_repos/permissive/113471686/baseline/src/mtree.v | 113,471,686 | mtree.v | v | 182 | 158 | [] | [] | [] | [(9, 41), (46, 75), (80, 127), (132, 179)] | null | data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml | null | 5,634 | module | module SORTER_CELL #(parameter DATW = 64,
parameter KEYW = 32)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire VLD0,
input wire VLD1,
input wire FULL,
output wire DEQ0,
output wire DEQ1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD);
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire comp_rslt = (DIN0[KEYW-1:0] < DIN1[KEYW-1:0]);
wire enq = &{(~FULL), VLD0, VLD1};
assign DEQ0 = &{enq, comp_rslt};
assign DEQ1 = &{enq, ~comp_rslt};
assign DOUT = mux(DIN1, DIN0, comp_rslt);
assign DOUT_VLD = enq;
endmodule | module SORTER_CELL #(parameter DATW = 64,
parameter KEYW = 32)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire VLD0,
input wire VLD1,
input wire FULL,
output wire DEQ0,
output wire DEQ1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD); |
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire comp_rslt = (DIN0[KEYW-1:0] < DIN1[KEYW-1:0]);
wire enq = &{(~FULL), VLD0, VLD1};
assign DEQ0 = &{enq, comp_rslt};
assign DEQ1 = &{enq, ~comp_rslt};
assign DOUT = mux(DIN1, DIN0, comp_rslt);
assign DOUT_VLD = enq;
endmodule | 0 |
5,194 | data/full_repos/permissive/113471686/baseline/src/mtree.v | 113,471,686 | mtree.v | v | 182 | 158 | [] | [] | [] | [(9, 41), (46, 75), (80, 127), (132, 179)] | null | data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml | null | 5,634 | module | module TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [1:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [1:0];
assign emp = (cnt == 0);
assign full = (cnt == 2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule | module TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [1:0] cnt); |
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [1:0];
assign emp = (cnt == 0);
assign full = (cnt == 2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule | 0 |
5,195 | data/full_repos/permissive/113471686/baseline/src/mtree.v | 113,471,686 | mtree.v | v | 182 | 158 | [] | [] | [] | [(9, 41), (46, 75), (80, 127), (132, 179)] | null | data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml | null | 5,634 | module | module TREE_NODE #(parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [DATW-1:0] DIN0,
input wire ENQ0,
input wire [DATW-1:0] DIN1,
input wire ENQ1,
output wire FUL0,
output wire FUL1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD);
wire fifo0_enq, fifo1_enq;
wire fifo0_deq, fifo1_deq;
wire [DATW-1:0] fifo0_din, fifo1_din;
wire [DATW-1:0] fifo0_dot, fifo1_dot;
wire fifo0_emp, fifo1_emp;
wire fifo0_ful, fifo1_ful;
wire [1:0] fifo0_cnt, fifo1_cnt;
wire [DATW-1:0] scell_dot;
wire scell_doten;
assign fifo0_enq = ENQ0;
assign fifo1_enq = ENQ1;
assign fifo0_din = DIN0;
assign fifo1_din = DIN1;
TWO_ENTRY_FIFO #(DATW)
fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
fifo0_dot, fifo0_emp, fifo0_ful, fifo0_cnt);
TWO_ENTRY_FIFO #(DATW)
fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
fifo1_dot, fifo1_emp, fifo1_ful, fifo1_cnt);
SORTER_CELL #(DATW, KEYW)
sorter_cell(fifo0_dot, fifo1_dot, ~fifo0_emp, ~fifo1_emp, IN_FULL,
fifo0_deq, fifo1_deq, scell_dot, scell_doten);
assign FUL0 = fifo0_ful;
assign FUL1 = fifo1_ful;
assign DOUT = scell_dot;
assign DOUT_VLD = scell_doten;
endmodule | module TREE_NODE #(parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [DATW-1:0] DIN0,
input wire ENQ0,
input wire [DATW-1:0] DIN1,
input wire ENQ1,
output wire FUL0,
output wire FUL1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD); |
wire fifo0_enq, fifo1_enq;
wire fifo0_deq, fifo1_deq;
wire [DATW-1:0] fifo0_din, fifo1_din;
wire [DATW-1:0] fifo0_dot, fifo1_dot;
wire fifo0_emp, fifo1_emp;
wire fifo0_ful, fifo1_ful;
wire [1:0] fifo0_cnt, fifo1_cnt;
wire [DATW-1:0] scell_dot;
wire scell_doten;
assign fifo0_enq = ENQ0;
assign fifo1_enq = ENQ1;
assign fifo0_din = DIN0;
assign fifo1_din = DIN1;
TWO_ENTRY_FIFO #(DATW)
fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
fifo0_dot, fifo0_emp, fifo0_ful, fifo0_cnt);
TWO_ENTRY_FIFO #(DATW)
fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
fifo1_dot, fifo1_emp, fifo1_ful, fifo1_cnt);
SORTER_CELL #(DATW, KEYW)
sorter_cell(fifo0_dot, fifo1_dot, ~fifo0_emp, ~fifo1_emp, IN_FULL,
fifo0_deq, fifo1_deq, scell_dot, scell_doten);
assign FUL0 = fifo0_ful;
assign FUL1 = fifo1_ful;
assign DOUT = scell_dot;
assign DOUT_VLD = scell_doten;
endmodule | 0 |
5,196 | data/full_repos/permissive/113471686/baseline/src/mtree.v | 113,471,686 | mtree.v | v | 182 | 158 | [] | [] | [] | [(9, 41), (46, 75), (80, 127), (132, 179)] | null | data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml | null | 5,634 | module | module MERGE_SORTER_TREE #(parameter W_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<W_LOG)-1:0] DIN,
input wire [(1<<W_LOG)-1:0] DINEN,
output wire [(1<<W_LOG)-1:0] FULL,
output wire [DATW-1:0] DOT,
output wire DOTEN);
genvar i, j;
generate
for (i=0; i<W_LOG; i=i+1) begin: level
wire [(1<<(W_LOG-(i+1)))-1:0] node_in_full;
wire [(DATW<<(W_LOG-i))-1:0] node_din;
wire [(1<<(W_LOG-i))-1:0] node_dinen;
wire [(1<<(W_LOG-i))-1:0] node_full;
wire [(DATW<<(W_LOG-(i+1)))-1:0] node_dot;
wire [(1<<(W_LOG-(i+1)))-1:0] node_doten;
for (j=0; j<(1<<(W_LOG-(i+1))); j=j+1) begin: nodes
TREE_NODE #(DATW, KEYW)
tree_node(CLK, RST, node_in_full[j], node_din[DATW*(2*j+1)-1:DATW*(2*j)], node_dinen[2*j], node_din[DATW*(2*j+2)-1:DATW*(2*j+1)], node_dinen[2*j+1],
node_full[2*j], node_full[2*j+1], node_dot[DATW*(j+1)-1:DATW*j], node_doten[j]);
end
end
endgenerate
generate
for (i=0; i<W_LOG; i=i+1) begin: connection
if (i == 0) begin
assign level[0].node_din = DIN;
assign level[0].node_dinen = DINEN;
assign FULL = level[0].node_full;
end else begin
assign level[i].node_din = level[i-1].node_dot;
assign level[i].node_dinen = level[i-1].node_doten;
assign level[i-1].node_in_full = level[i].node_full;
end
end
endgenerate
assign level[W_LOG-1].node_in_full = IN_FULL;
assign DOT = level[W_LOG-1].node_dot;
assign DOTEN = level[W_LOG-1].node_doten;
endmodule | module MERGE_SORTER_TREE #(parameter W_LOG = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<W_LOG)-1:0] DIN,
input wire [(1<<W_LOG)-1:0] DINEN,
output wire [(1<<W_LOG)-1:0] FULL,
output wire [DATW-1:0] DOT,
output wire DOTEN); |
genvar i, j;
generate
for (i=0; i<W_LOG; i=i+1) begin: level
wire [(1<<(W_LOG-(i+1)))-1:0] node_in_full;
wire [(DATW<<(W_LOG-i))-1:0] node_din;
wire [(1<<(W_LOG-i))-1:0] node_dinen;
wire [(1<<(W_LOG-i))-1:0] node_full;
wire [(DATW<<(W_LOG-(i+1)))-1:0] node_dot;
wire [(1<<(W_LOG-(i+1)))-1:0] node_doten;
for (j=0; j<(1<<(W_LOG-(i+1))); j=j+1) begin: nodes
TREE_NODE #(DATW, KEYW)
tree_node(CLK, RST, node_in_full[j], node_din[DATW*(2*j+1)-1:DATW*(2*j)], node_dinen[2*j], node_din[DATW*(2*j+2)-1:DATW*(2*j+1)], node_dinen[2*j+1],
node_full[2*j], node_full[2*j+1], node_dot[DATW*(j+1)-1:DATW*j], node_doten[j]);
end
end
endgenerate
generate
for (i=0; i<W_LOG; i=i+1) begin: connection
if (i == 0) begin
assign level[0].node_din = DIN;
assign level[0].node_dinen = DINEN;
assign FULL = level[0].node_full;
end else begin
assign level[i].node_din = level[i-1].node_dot;
assign level[i].node_dinen = level[i-1].node_doten;
assign level[i-1].node_in_full = level[i].node_full;
end
end
endgenerate
assign level[W_LOG-1].node_in_full = IN_FULL;
assign DOT = level[W_LOG-1].node_dot;
assign DOTEN = level[W_LOG-1].node_doten;
endmodule | 0 |
5,197 | data/full_repos/permissive/113471686/baseline/src/mtree.v | 113,471,686 | mtree.v | v | 182 | 158 | [] | [] | [] | [(9, 41), (46, 75), (80, 127), (132, 179)] | null | data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml | null | 5,634 | function | function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | function [DATW-1:0] mux; |
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | 0 |
5,198 | data/full_repos/permissive/113471686/baseline/test/tb_mtree.v | 113,471,686 | tb_mtree.v | v | 83 | 95 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:7: Cannot find include file: mtree.v\n`include "mtree.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v\n data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v.v\n data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v.sv\n mtree.v\n mtree.v.v\n mtree.v.sv\n obj_dir/mtree.v\n obj_dir/mtree.v.v\n obj_dir/mtree.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:14: Unsupported: Ignoring delay on this delayed statement.\n reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:15: Unsupported: Ignoring delay on this delayed statement.\n reg RST; initial begin RST=1; #400 RST=0; end\n ^\n%Error: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:49: Unsupported: $fflush of all handles does not map to C++.\n $fflush();\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 5,635 | module | module tb_MERGE_SORTER_TREE();
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_dinen;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_ful;
wire [`DATW-1:0] merge_sorter_tree_dot;
wire merge_sorter_tree_doten;
reg [`DATW-1:0] check_record;
assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
end
assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
end
endgenerate
MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen,
merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);
always @(posedge CLK) begin
if (merge_sorter_tree_doten) begin
$write("%d", merge_sorter_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
end else begin
if (merge_sorter_tree_doten) begin
check_record <= check_record + 1;
if (merge_sorter_tree_dot != check_record) begin
$write("\nError!\n");
$write("%d %d\n", merge_sorter_tree_dot, check_record);
$finish();
end
end
end
end
reg [31:0] cycle;
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
cycle <= cycle + 1;
if (cycle >= 200) $finish();
end
end
endmodule | module tb_MERGE_SORTER_TREE(); |
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_dinen;
wire [(1<<`W_LOG)-1:0] merge_sorter_tree_ful;
wire [`DATW-1:0] merge_sorter_tree_dot;
wire merge_sorter_tree_doten;
reg [`DATW-1:0] check_record;
assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
end
assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
end
endgenerate
MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen,
merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);
always @(posedge CLK) begin
if (merge_sorter_tree_doten) begin
$write("%d", merge_sorter_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
end else begin
if (merge_sorter_tree_doten) begin
check_record <= check_record + 1;
if (merge_sorter_tree_dot != check_record) begin
$write("\nError!\n");
$write("%d %d\n", merge_sorter_tree_dot, check_record);
$finish();
end
end
end
end
reg [31:0] cycle;
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
cycle <= cycle + 1;
if (cycle >= 200) $finish();
end
end
endmodule | 0 |
5,199 | data/full_repos/permissive/113471686/virtualtree/freq/freq.v | 113,471,686 | freq.v | v | 60 | 116 | [] | [] | [] | [(19, 57)] | null | null | 1: b"%Error: data/full_repos/permissive/113471686/virtualtree/freq/freq.v:46: Cannot find file containing module: 'vMERGE_SORTER_TREE'\n vMERGE_SORTER_TREE #(10, 3, 2, 2, 64, 32)\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE\n data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE.v\n data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE.sv\n vMERGE_SORTER_TREE\n vMERGE_SORTER_TREE.v\n vMERGE_SORTER_TREE.sv\n obj_dir/vMERGE_SORTER_TREE\n obj_dir/vMERGE_SORTER_TREE.v\n obj_dir/vMERGE_SORTER_TREE.sv\n%Error: Exiting due to 1 error(s)\n" | 5,636 | module | module freq(input wire CLK,
input wire RST_IN,
output wire OUT);
reg RST; always @(posedge CLK) RST <= RST_IN;
reg [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
reg vmerge_sorter_tree_dinen;
reg [`W_LOG-1:0] vmerge_sorter_tree_din_idx;
wire [`DATW-1:0] vmerge_sorter_tree_dot;
wire vmerge_sorter_tree_doten;
wire [(1<<`W_LOG)-1:0] vmerge_sorter_tree_emp;
always @(posedge CLK) begin
if (RST) begin
vmerge_sorter_tree_din <= 1;
vmerge_sorter_tree_dinen <= 0;
vmerge_sorter_tree_din_idx <= 0;
end else begin
vmerge_sorter_tree_din <= vmerge_sorter_tree_din << 1;
vmerge_sorter_tree_dinen <= ~vmerge_sorter_tree_dinen;
if (vmerge_sorter_tree_dinen) begin
vmerge_sorter_tree_din_idx <= vmerge_sorter_tree_din_idx + 1;
end
end
end
vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx,
vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
reg [`DATW-1:0] dot_buf;
always @(posedge CLK) begin
if (vmerge_sorter_tree_doten) dot_buf <= vmerge_sorter_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | module freq(input wire CLK,
input wire RST_IN,
output wire OUT); |
reg RST; always @(posedge CLK) RST <= RST_IN;
reg [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
reg vmerge_sorter_tree_dinen;
reg [`W_LOG-1:0] vmerge_sorter_tree_din_idx;
wire [`DATW-1:0] vmerge_sorter_tree_dot;
wire vmerge_sorter_tree_doten;
wire [(1<<`W_LOG)-1:0] vmerge_sorter_tree_emp;
always @(posedge CLK) begin
if (RST) begin
vmerge_sorter_tree_din <= 1;
vmerge_sorter_tree_dinen <= 0;
vmerge_sorter_tree_din_idx <= 0;
end else begin
vmerge_sorter_tree_din <= vmerge_sorter_tree_din << 1;
vmerge_sorter_tree_dinen <= ~vmerge_sorter_tree_dinen;
if (vmerge_sorter_tree_dinen) begin
vmerge_sorter_tree_din_idx <= vmerge_sorter_tree_din_idx + 1;
end
end
end
vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx,
vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
reg [`DATW-1:0] dot_buf;
always @(posedge CLK) begin
if (vmerge_sorter_tree_doten) dot_buf <= vmerge_sorter_tree_dot;
end
assign OUT = ^dot_buf;
endmodule | 0 |
5,200 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module SORTER_CELL #(parameter DATW = 64,
parameter KEYW = 32)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire DINs_VALID,
output wire DEQ0,
output wire DEQ1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD);
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire comp_rslt = (DIN0[KEYW-1:0] < DIN1[KEYW-1:0]);
wire enq = DINs_VALID;
assign DEQ0 = &{enq, comp_rslt};
assign DEQ1 = &{enq, ~comp_rslt};
assign DOUT = mux(DIN1, DIN0, comp_rslt);
assign DOUT_VLD = enq;
endmodule | module SORTER_CELL #(parameter DATW = 64,
parameter KEYW = 32)
(input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
input wire DINs_VALID,
output wire DEQ0,
output wire DEQ1,
output wire [DATW-1:0] DOUT,
output wire DOUT_VLD); |
function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire comp_rslt = (DIN0[KEYW-1:0] < DIN1[KEYW-1:0]);
wire enq = DINs_VALID;
assign DEQ0 = &{enq, comp_rslt};
assign DEQ1 = &{enq, ~comp_rslt};
assign DOUT = mux(DIN1, DIN0, comp_rslt);
assign DOUT_VLD = enq;
endmodule | 0 |
5,201 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [1:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [1:0];
assign emp = (cnt == 0);
assign full = (cnt >= 1);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule | module TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [1:0] cnt); |
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [1:0];
assign emp = (cnt == 0);
assign full = (cnt >= 1);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule | 0 |
5,202 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module DFIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt>=(1<<FIFO_SIZE)-1);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule | module DFIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt); |
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt>=(1<<FIFO_SIZE)-1);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule | 0 |
5,203 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module SRL_FIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule | module SRL_FIFO #(parameter FIFO_SIZE = 4,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt); |
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule | 0 |
5,204 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module MULTI_CHANNEL_FIFO #(parameter C_LOG = 2,
parameter FIFO_SIZE = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire same_request,
input wire enq,
input wire [C_LOG-1:0] enq_idx,
input wire deq,
input wire [C_LOG-1:0] deq_idx,
input wire [C_LOG-1:0] _deq_idx,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire [(1<<C_LOG)-1:0] emp,
output wire [(1<<C_LOG)-1:0] full,
output wire [(1<<C_LOG)-1:0] one_elem);
reg [FIFO_SIZE:0] head_list [(1<<C_LOG)-1:0];
reg [FIFO_SIZE:0] tail_list [(1<<C_LOG)-1:0];
reg [FIFO_WIDTH-1:0] mem [(1<<(C_LOG+FIFO_SIZE))-1:0];
genvar i;
generate
for (i=0; i<(1<<C_LOG); i=i+1) begin: channels
wire [FIFO_SIZE:0] next_head = head_list[i] + 1;
assign emp[i] = (head_list[i] == tail_list[i]);
assign full[i] = (head_list[i] == {~tail_list[i][FIFO_SIZE], tail_list[i][FIFO_SIZE-1:0]});
assign one_elem[i] = (next_head == tail_list[i]);
end
endgenerate
wire [(C_LOG+FIFO_SIZE)-1:0] raddr = {_deq_idx, head_list[_deq_idx][FIFO_SIZE-1:0]};
wire [(C_LOG+FIFO_SIZE)-1:0] waddr = {enq_idx, tail_list[enq_idx][FIFO_SIZE-1:0]};
wire [(C_LOG+FIFO_SIZE)-1:0] raddr_4_same_req = {_deq_idx, (head_list[_deq_idx][FIFO_SIZE-1:0] + 1'b1)};
always @(posedge CLK) dot <= mem[(same_request) ? raddr_4_same_req : raddr];
integer p;
always @(posedge CLK) begin
if (RST) begin
for (p=0; p<(1<<C_LOG); p=p+1) begin
head_list[p] <= 0;
tail_list[p] <= 0;
end
end else begin
case ({enq, deq})
2'b01: begin
head_list[deq_idx] <= head_list[deq_idx] + 1;
end
2'b10: begin
mem[waddr] <= din;
tail_list[enq_idx] <= tail_list[enq_idx] + 1;
end
2'b11: begin
mem[waddr] <= din;
head_list[deq_idx] <= head_list[deq_idx] + 1;
tail_list[enq_idx] <= tail_list[enq_idx] + 1;
end
endcase
end
end
endmodule | module MULTI_CHANNEL_FIFO #(parameter C_LOG = 2,
parameter FIFO_SIZE = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire same_request,
input wire enq,
input wire [C_LOG-1:0] enq_idx,
input wire deq,
input wire [C_LOG-1:0] deq_idx,
input wire [C_LOG-1:0] _deq_idx,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire [(1<<C_LOG)-1:0] emp,
output wire [(1<<C_LOG)-1:0] full,
output wire [(1<<C_LOG)-1:0] one_elem); |
reg [FIFO_SIZE:0] head_list [(1<<C_LOG)-1:0];
reg [FIFO_SIZE:0] tail_list [(1<<C_LOG)-1:0];
reg [FIFO_WIDTH-1:0] mem [(1<<(C_LOG+FIFO_SIZE))-1:0];
genvar i;
generate
for (i=0; i<(1<<C_LOG); i=i+1) begin: channels
wire [FIFO_SIZE:0] next_head = head_list[i] + 1;
assign emp[i] = (head_list[i] == tail_list[i]);
assign full[i] = (head_list[i] == {~tail_list[i][FIFO_SIZE], tail_list[i][FIFO_SIZE-1:0]});
assign one_elem[i] = (next_head == tail_list[i]);
end
endgenerate
wire [(C_LOG+FIFO_SIZE)-1:0] raddr = {_deq_idx, head_list[_deq_idx][FIFO_SIZE-1:0]};
wire [(C_LOG+FIFO_SIZE)-1:0] waddr = {enq_idx, tail_list[enq_idx][FIFO_SIZE-1:0]};
wire [(C_LOG+FIFO_SIZE)-1:0] raddr_4_same_req = {_deq_idx, (head_list[_deq_idx][FIFO_SIZE-1:0] + 1'b1)};
always @(posedge CLK) dot <= mem[(same_request) ? raddr_4_same_req : raddr];
integer p;
always @(posedge CLK) begin
if (RST) begin
for (p=0; p<(1<<C_LOG); p=p+1) begin
head_list[p] <= 0;
tail_list[p] <= 0;
end
end else begin
case ({enq, deq})
2'b01: begin
head_list[deq_idx] <= head_list[deq_idx] + 1;
end
2'b10: begin
mem[waddr] <= din;
tail_list[enq_idx] <= tail_list[enq_idx] + 1;
end
2'b11: begin
mem[waddr] <= din;
head_list[deq_idx] <= head_list[deq_idx] + 1;
tail_list[enq_idx] <= tail_list[enq_idx] + 1;
end
endcase
end
end
endmodule | 0 |
5,205 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module RAM_LAYER #(parameter W_LOG = 2,
parameter FIFO_SIZE = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire SAME_REQUEST,
input wire ENQ,
input wire [W_LOG-1:0] ENQ_IDX,
input wire DEQ0,
input wire DEQ1,
input wire [W_LOG-2:0] DEQ_IDX,
input wire [W_LOG-2:0] _DEQ_IDX,
input wire [FIFO_WIDTH-1:0] DIN,
output wire [FIFO_WIDTH-1:0] DOT0,
output wire [FIFO_WIDTH-1:0] DOT1,
output wire EMP0,
output wire EMP1,
output wire ONE_ELEM0,
output wire ONE_ELEM1);
wire even_enq = &{ENQ, ~ENQ_IDX[0]};
wire odd_enq = &{ENQ, ENQ_IDX[0]};
wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);
wire even_deq = DEQ0;
wire odd_deq = DEQ1;
wire [W_LOG-2:0] deq_idx = DEQ_IDX;
wire [W_LOG-2:0] _deq_idx = _DEQ_IDX;
wire [FIFO_WIDTH-1:0] din = DIN;
wire [FIFO_WIDTH-1:0] even_dot, odd_dot;
wire [(1<<(W_LOG-1))-1:0] even_emp, odd_emp;
wire [(1<<(W_LOG-1))-1:0] even_full, odd_full;
wire [(1<<(W_LOG-1))-1:0] even_one_elem, odd_one_elem;
MULTI_CHANNEL_FIFO #((W_LOG-1), FIFO_SIZE, FIFO_WIDTH)
even_numbered_fifo(CLK, RST, SAME_REQUEST, even_enq, enq_idx, even_deq, deq_idx, _deq_idx, din,
even_dot, even_emp, even_full, even_one_elem);
MULTI_CHANNEL_FIFO #((W_LOG-1), FIFO_SIZE, FIFO_WIDTH)
odd_numbered_fifo(CLK, RST, SAME_REQUEST, odd_enq, enq_idx, odd_deq, deq_idx, _deq_idx, din,
odd_dot, odd_emp, odd_full, odd_one_elem);
assign DOT0 = even_dot;
assign DOT1 = odd_dot;
assign EMP0 = even_emp[_deq_idx];
assign EMP1 = odd_emp[_deq_idx];
assign ONE_ELEM0 = even_one_elem[_deq_idx];
assign ONE_ELEM1 = odd_one_elem[_deq_idx];
endmodule | module RAM_LAYER #(parameter W_LOG = 2,
parameter FIFO_SIZE = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire SAME_REQUEST,
input wire ENQ,
input wire [W_LOG-1:0] ENQ_IDX,
input wire DEQ0,
input wire DEQ1,
input wire [W_LOG-2:0] DEQ_IDX,
input wire [W_LOG-2:0] _DEQ_IDX,
input wire [FIFO_WIDTH-1:0] DIN,
output wire [FIFO_WIDTH-1:0] DOT0,
output wire [FIFO_WIDTH-1:0] DOT1,
output wire EMP0,
output wire EMP1,
output wire ONE_ELEM0,
output wire ONE_ELEM1); |
wire even_enq = &{ENQ, ~ENQ_IDX[0]};
wire odd_enq = &{ENQ, ENQ_IDX[0]};
wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);
wire even_deq = DEQ0;
wire odd_deq = DEQ1;
wire [W_LOG-2:0] deq_idx = DEQ_IDX;
wire [W_LOG-2:0] _deq_idx = _DEQ_IDX;
wire [FIFO_WIDTH-1:0] din = DIN;
wire [FIFO_WIDTH-1:0] even_dot, odd_dot;
wire [(1<<(W_LOG-1))-1:0] even_emp, odd_emp;
wire [(1<<(W_LOG-1))-1:0] even_full, odd_full;
wire [(1<<(W_LOG-1))-1:0] even_one_elem, odd_one_elem;
MULTI_CHANNEL_FIFO #((W_LOG-1), FIFO_SIZE, FIFO_WIDTH)
even_numbered_fifo(CLK, RST, SAME_REQUEST, even_enq, enq_idx, even_deq, deq_idx, _deq_idx, din,
even_dot, even_emp, even_full, even_one_elem);
MULTI_CHANNEL_FIFO #((W_LOG-1), FIFO_SIZE, FIFO_WIDTH)
odd_numbered_fifo(CLK, RST, SAME_REQUEST, odd_enq, enq_idx, odd_deq, deq_idx, _deq_idx, din,
odd_dot, odd_emp, odd_full, odd_one_elem);
assign DOT0 = even_dot;
assign DOT1 = odd_dot;
assign EMP0 = even_emp[_deq_idx];
assign EMP1 = odd_emp[_deq_idx];
assign ONE_ELEM0 = even_one_elem[_deq_idx];
assign ONE_ELEM1 = odd_one_elem[_deq_idx];
endmodule | 0 |
5,206 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module SORTER_STAGE_BODY #(parameter W_LOG = 2,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire [W_LOG-2:0] I_REQUEST,
input wire I_REQUEST_VALID,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire QUEUE_FULL,
output wire [W_LOG-1:0] O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [W_LOG-2:0] DOT_IDX);
function [W_LOG-1:0] request_gen;
input [W_LOG-1:0] in;
input [1:0] sel;
begin
case (sel)
2'b01: request_gen = (in << 1);
2'b10: request_gen = (in << 1) + 1;
endcase
end
endfunction
wire queue_enq;
wire queue_deq;
wire [W_LOG-2:0] queue_din;
wire [W_LOG-2:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [Q_SIZE:0] queue_cnt;
wire ram_layer_enq;
wire [W_LOG-1:0] ram_layer_enq_idx;
wire ram_layer_deq0;
wire ram_layer_deq1;
wire [W_LOG-2:0] ram_layer_deq_idx;
wire [W_LOG-2:0] ram_layer__deq_idx;
wire [DATW-1:0] ram_layer_din;
wire [DATW-1:0] ram_layer_dot0;
wire [DATW-1:0] ram_layer_dot1;
wire ram_layer_emp0;
wire ram_layer_emp1;
wire ram_layer_almost_emp0;
wire ram_layer_almost_emp1;
wire [DATW-1:0] sorter_cell_din0;
wire [DATW-1:0] sorter_cell_din1;
wire sorter_cell_din_rdy;
wire [DATW-1:0] sorter_cell_dot;
wire sorter_cell_doten;
reg [W_LOG-1:0] request_4_emp;
reg [W_LOG-2:0] queue_dot_buf;
reg state;
reg comp_data_ready;
reg request_valid;
reg [DATW-1:0] unselected_data;
reg unselected_0;
reg unselected_1;
reg ram_layer_almost_emp0_buf;
reg ram_layer_almost_emp1_buf;
wire same_request;
reg same_request_buf;
assign queue_enq = I_REQUEST_VALID;
assign queue_deq = ~|{QUEUE_IN_FULL,queue_emp,ram_layer_emp0,ram_layer_emp1};
assign queue_din = I_REQUEST;
assign ram_layer_enq = DINEN;
assign ram_layer_enq_idx = DIN_IDX;
assign ram_layer_deq_idx = queue_dot_buf;
assign ram_layer__deq_idx = queue_dot;
assign ram_layer_din = DIN;
assign sorter_cell_din0 = (same_request_buf && unselected_0) ? unselected_data : ram_layer_dot0;
assign sorter_cell_din1 = (same_request_buf && unselected_1) ? unselected_data : ram_layer_dot1;
assign sorter_cell_din_rdy = (same_request_buf) ? (~|{ram_layer_almost_emp0_buf,ram_layer_almost_emp1_buf}) : comp_data_ready;
assign same_request = &{sorter_cell_doten, queue_deq, (queue_dot_buf == queue_dot)};
DFIFO #(Q_SIZE, W_LOG-1)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
RAM_LAYER #(W_LOG, FIFO_SIZE, DATW)
ram_layer(CLK, RST, same_request, ram_layer_enq, ram_layer_enq_idx, ram_layer_deq0, ram_layer_deq1, ram_layer_deq_idx, ram_layer__deq_idx, ram_layer_din,
ram_layer_dot0, ram_layer_dot1, ram_layer_emp0, ram_layer_emp1, ram_layer_almost_emp0, ram_layer_almost_emp1);
SORTER_CELL #(DATW, KEYW)
sorter_cell(sorter_cell_din0, sorter_cell_din1, sorter_cell_din_rdy,
ram_layer_deq0, ram_layer_deq1, sorter_cell_dot, sorter_cell_doten);
always @(posedge CLK) begin
if (ram_layer_emp0) request_4_emp <= ({1'b0, queue_dot} << 1);
else if (ram_layer_emp1) request_4_emp <= ({1'b0, queue_dot} << 1) + 1 ;
end
always @(posedge CLK) begin
if (RST) begin
queue_dot_buf <= 0;
state <= 0;
comp_data_ready <= 0;
request_valid <= 0;
end else begin
queue_dot_buf <= queue_dot;
case (state)
0: begin
request_valid <= (~|{QUEUE_IN_FULL,queue_emp});
if (queue_deq) begin state <= 1; comp_data_ready <= 1; end
end
1: begin
if (!queue_deq) begin state <= 0; comp_data_ready <= 0; request_valid <= 0; end
end
endcase
end
end
always @(posedge CLK) same_request_buf <= same_request;
always @(posedge CLK) begin
case ({ram_layer_deq1,ram_layer_deq0})
2'b01: begin
unselected_data <= sorter_cell_din1;
unselected_0 <= 0;
unselected_1 <= 1;
ram_layer_almost_emp0_buf <= ram_layer_almost_emp0;
ram_layer_almost_emp1_buf <= 0;
end
2'b10: begin
unselected_data <= sorter_cell_din0;
unselected_0 <= 1;
unselected_1 <= 0;
ram_layer_almost_emp0_buf <= 0;
ram_layer_almost_emp1_buf <= ram_layer_almost_emp1;
end
endcase
end
assign QUEUE_FULL = queue_ful;
assign O_REQUEST = (comp_data_ready) ? request_gen({1'b0, queue_dot_buf}, {ram_layer_deq1,ram_layer_deq0}) : request_4_emp;
assign O_REQUEST_VALID = (same_request_buf) ? (~|{ram_layer_almost_emp0_buf,ram_layer_almost_emp1_buf}) : request_valid;
assign DOT = sorter_cell_dot;
assign DOTEN = sorter_cell_doten;
assign DOT_IDX = queue_dot_buf;
endmodule | module SORTER_STAGE_BODY #(parameter W_LOG = 2,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire [W_LOG-2:0] I_REQUEST,
input wire I_REQUEST_VALID,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire QUEUE_FULL,
output wire [W_LOG-1:0] O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [W_LOG-2:0] DOT_IDX); |
function [W_LOG-1:0] request_gen;
input [W_LOG-1:0] in;
input [1:0] sel;
begin
case (sel)
2'b01: request_gen = (in << 1);
2'b10: request_gen = (in << 1) + 1;
endcase
end
endfunction
wire queue_enq;
wire queue_deq;
wire [W_LOG-2:0] queue_din;
wire [W_LOG-2:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [Q_SIZE:0] queue_cnt;
wire ram_layer_enq;
wire [W_LOG-1:0] ram_layer_enq_idx;
wire ram_layer_deq0;
wire ram_layer_deq1;
wire [W_LOG-2:0] ram_layer_deq_idx;
wire [W_LOG-2:0] ram_layer__deq_idx;
wire [DATW-1:0] ram_layer_din;
wire [DATW-1:0] ram_layer_dot0;
wire [DATW-1:0] ram_layer_dot1;
wire ram_layer_emp0;
wire ram_layer_emp1;
wire ram_layer_almost_emp0;
wire ram_layer_almost_emp1;
wire [DATW-1:0] sorter_cell_din0;
wire [DATW-1:0] sorter_cell_din1;
wire sorter_cell_din_rdy;
wire [DATW-1:0] sorter_cell_dot;
wire sorter_cell_doten;
reg [W_LOG-1:0] request_4_emp;
reg [W_LOG-2:0] queue_dot_buf;
reg state;
reg comp_data_ready;
reg request_valid;
reg [DATW-1:0] unselected_data;
reg unselected_0;
reg unselected_1;
reg ram_layer_almost_emp0_buf;
reg ram_layer_almost_emp1_buf;
wire same_request;
reg same_request_buf;
assign queue_enq = I_REQUEST_VALID;
assign queue_deq = ~|{QUEUE_IN_FULL,queue_emp,ram_layer_emp0,ram_layer_emp1};
assign queue_din = I_REQUEST;
assign ram_layer_enq = DINEN;
assign ram_layer_enq_idx = DIN_IDX;
assign ram_layer_deq_idx = queue_dot_buf;
assign ram_layer__deq_idx = queue_dot;
assign ram_layer_din = DIN;
assign sorter_cell_din0 = (same_request_buf && unselected_0) ? unselected_data : ram_layer_dot0;
assign sorter_cell_din1 = (same_request_buf && unselected_1) ? unselected_data : ram_layer_dot1;
assign sorter_cell_din_rdy = (same_request_buf) ? (~|{ram_layer_almost_emp0_buf,ram_layer_almost_emp1_buf}) : comp_data_ready;
assign same_request = &{sorter_cell_doten, queue_deq, (queue_dot_buf == queue_dot)};
DFIFO #(Q_SIZE, W_LOG-1)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
RAM_LAYER #(W_LOG, FIFO_SIZE, DATW)
ram_layer(CLK, RST, same_request, ram_layer_enq, ram_layer_enq_idx, ram_layer_deq0, ram_layer_deq1, ram_layer_deq_idx, ram_layer__deq_idx, ram_layer_din,
ram_layer_dot0, ram_layer_dot1, ram_layer_emp0, ram_layer_emp1, ram_layer_almost_emp0, ram_layer_almost_emp1);
SORTER_CELL #(DATW, KEYW)
sorter_cell(sorter_cell_din0, sorter_cell_din1, sorter_cell_din_rdy,
ram_layer_deq0, ram_layer_deq1, sorter_cell_dot, sorter_cell_doten);
always @(posedge CLK) begin
if (ram_layer_emp0) request_4_emp <= ({1'b0, queue_dot} << 1);
else if (ram_layer_emp1) request_4_emp <= ({1'b0, queue_dot} << 1) + 1 ;
end
always @(posedge CLK) begin
if (RST) begin
queue_dot_buf <= 0;
state <= 0;
comp_data_ready <= 0;
request_valid <= 0;
end else begin
queue_dot_buf <= queue_dot;
case (state)
0: begin
request_valid <= (~|{QUEUE_IN_FULL,queue_emp});
if (queue_deq) begin state <= 1; comp_data_ready <= 1; end
end
1: begin
if (!queue_deq) begin state <= 0; comp_data_ready <= 0; request_valid <= 0; end
end
endcase
end
end
always @(posedge CLK) same_request_buf <= same_request;
always @(posedge CLK) begin
case ({ram_layer_deq1,ram_layer_deq0})
2'b01: begin
unselected_data <= sorter_cell_din1;
unselected_0 <= 0;
unselected_1 <= 1;
ram_layer_almost_emp0_buf <= ram_layer_almost_emp0;
ram_layer_almost_emp1_buf <= 0;
end
2'b10: begin
unselected_data <= sorter_cell_din0;
unselected_0 <= 1;
unselected_1 <= 0;
ram_layer_almost_emp0_buf <= 0;
ram_layer_almost_emp1_buf <= ram_layer_almost_emp1;
end
endcase
end
assign QUEUE_FULL = queue_ful;
assign O_REQUEST = (comp_data_ready) ? request_gen({1'b0, queue_dot_buf}, {ram_layer_deq1,ram_layer_deq0}) : request_4_emp;
assign O_REQUEST_VALID = (same_request_buf) ? (~|{ram_layer_almost_emp0_buf,ram_layer_almost_emp1_buf}) : request_valid;
assign DOT = sorter_cell_dot;
assign DOTEN = sorter_cell_doten;
assign DOT_IDX = queue_dot_buf;
endmodule | 0 |
5,207 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module SORTER_STAGE_ROOT #(parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire IN_FULL,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire DIN_IDX,
output wire O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN);
wire fifo0_enq;
wire fifo0_deq;
wire [DATW-1:0] fifo0_din;
wire [DATW-1:0] fifo0_dot;
wire fifo0_emp;
wire fifo0_ful;
wire [FIFO_SIZE:0] fifo0_cnt;
wire fifo1_enq;
wire fifo1_deq;
wire [DATW-1:0] fifo1_din;
wire [DATW-1:0] fifo1_dot;
wire fifo1_emp;
wire fifo1_ful;
wire [FIFO_SIZE:0] fifo1_cnt;
wire comp_data_ready;
wire [DATW-1:0] sorter_cell_dot;
wire sorter_cell_doten;
assign fifo0_enq = &{DINEN, ~DIN_IDX};
assign fifo0_din = DIN;
assign fifo1_enq = &{DINEN, DIN_IDX};
assign fifo1_din = DIN;
assign comp_data_ready = ~|{IN_FULL,fifo0_emp,fifo1_emp};
SRL_FIFO #(FIFO_SIZE, DATW)
fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
fifo0_dot, fifo0_emp, fifo0_ful ,fifo0_cnt);
SRL_FIFO #(FIFO_SIZE, DATW)
fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
fifo1_dot, fifo1_emp, fifo1_ful ,fifo1_cnt);
SORTER_CELL #(DATW, KEYW)
sorter_cell(fifo0_dot, fifo1_dot, comp_data_ready,
fifo0_deq, fifo1_deq, sorter_cell_dot, sorter_cell_doten);
assign O_REQUEST = (comp_data_ready) ? fifo1_deq : ~fifo0_emp;
assign O_REQUEST_VALID = ~|{QUEUE_IN_FULL, IN_FULL};
assign DOT = sorter_cell_dot;
assign DOTEN = sorter_cell_doten;
endmodule | module SORTER_STAGE_ROOT #(parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire IN_FULL,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire DIN_IDX,
output wire O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN); |
wire fifo0_enq;
wire fifo0_deq;
wire [DATW-1:0] fifo0_din;
wire [DATW-1:0] fifo0_dot;
wire fifo0_emp;
wire fifo0_ful;
wire [FIFO_SIZE:0] fifo0_cnt;
wire fifo1_enq;
wire fifo1_deq;
wire [DATW-1:0] fifo1_din;
wire [DATW-1:0] fifo1_dot;
wire fifo1_emp;
wire fifo1_ful;
wire [FIFO_SIZE:0] fifo1_cnt;
wire comp_data_ready;
wire [DATW-1:0] sorter_cell_dot;
wire sorter_cell_doten;
assign fifo0_enq = &{DINEN, ~DIN_IDX};
assign fifo0_din = DIN;
assign fifo1_enq = &{DINEN, DIN_IDX};
assign fifo1_din = DIN;
assign comp_data_ready = ~|{IN_FULL,fifo0_emp,fifo1_emp};
SRL_FIFO #(FIFO_SIZE, DATW)
fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
fifo0_dot, fifo0_emp, fifo0_ful ,fifo0_cnt);
SRL_FIFO #(FIFO_SIZE, DATW)
fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
fifo1_dot, fifo1_emp, fifo1_ful ,fifo1_cnt);
SORTER_CELL #(DATW, KEYW)
sorter_cell(fifo0_dot, fifo1_dot, comp_data_ready,
fifo0_deq, fifo1_deq, sorter_cell_dot, sorter_cell_doten);
assign O_REQUEST = (comp_data_ready) ? fifo1_deq : ~fifo0_emp;
assign O_REQUEST_VALID = ~|{QUEUE_IN_FULL, IN_FULL};
assign DOT = sorter_cell_dot;
assign DOTEN = sorter_cell_doten;
endmodule | 0 |
5,208 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module SORTER_STAGE_TREE #(parameter W_LOG = 2,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire IN_FULL,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire [W_LOG-1:0] O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN);
genvar i;
generate
for (i=0; i<W_LOG; i=i+1) begin: stage
wire queue_in_full;
wire [DATW-1:0] din;
wire dinen;
wire [i:0] din_idx;
wire [i:0] o_request;
wire o_request_valid;
wire [DATW-1:0] dot;
wire doten;
if (i == 0) begin: root
wire in_full;
SORTER_STAGE_ROOT #(FIFO_SIZE, DATW, KEYW)
sorter_stage_root(CLK, RST, queue_in_full, in_full, din, dinen, din_idx,
o_request, o_request_valid, dot, doten);
end else begin: body
wire [i-1:0] i_request;
wire i_request_valid;
wire queue_full;
wire [i-1:0] dot_idx;
SORTER_STAGE_BODY #((i+1), Q_SIZE, FIFO_SIZE, DATW, KEYW)
sorter_stage_body(CLK, RST, queue_in_full, i_request, i_request_valid, din, dinen, din_idx,
queue_full, o_request, o_request_valid, dot, doten, dot_idx);
end
end
endgenerate
generate
for (i=0; i<W_LOG; i=i+1) begin: connection
if (i == W_LOG-1) begin
assign stage[W_LOG-1].queue_in_full = QUEUE_IN_FULL;
assign O_REQUEST = stage[W_LOG-1].o_request;
assign O_REQUEST_VALID = stage[W_LOG-1].o_request_valid;
assign stage[W_LOG-1].din = DIN;
assign stage[W_LOG-1].dinen = DINEN;
assign stage[W_LOG-1].din_idx = DIN_IDX;
end else begin
assign stage[i].queue_in_full = stage[i+1].body.queue_full;
assign stage[i+1].body.i_request = stage[i].o_request;
assign stage[i+1].body.i_request_valid = stage[i].o_request_valid;
assign stage[i].din = stage[i+1].dot;
assign stage[i].dinen = stage[i+1].doten;
assign stage[i].din_idx = stage[i+1].body.dot_idx;
end
end
endgenerate
assign stage[0].root.in_full = IN_FULL;
assign DOT = stage[0].dot;
assign DOTEN = stage[0].doten;
endmodule | module SORTER_STAGE_TREE #(parameter W_LOG = 2,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire QUEUE_IN_FULL,
input wire IN_FULL,
input wire [DATW-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire [W_LOG-1:0] O_REQUEST,
output wire O_REQUEST_VALID,
output wire [DATW-1:0] DOT,
output wire DOTEN); |
genvar i;
generate
for (i=0; i<W_LOG; i=i+1) begin: stage
wire queue_in_full;
wire [DATW-1:0] din;
wire dinen;
wire [i:0] din_idx;
wire [i:0] o_request;
wire o_request_valid;
wire [DATW-1:0] dot;
wire doten;
if (i == 0) begin: root
wire in_full;
SORTER_STAGE_ROOT #(FIFO_SIZE, DATW, KEYW)
sorter_stage_root(CLK, RST, queue_in_full, in_full, din, dinen, din_idx,
o_request, o_request_valid, dot, doten);
end else begin: body
wire [i-1:0] i_request;
wire i_request_valid;
wire queue_full;
wire [i-1:0] dot_idx;
SORTER_STAGE_BODY #((i+1), Q_SIZE, FIFO_SIZE, DATW, KEYW)
sorter_stage_body(CLK, RST, queue_in_full, i_request, i_request_valid, din, dinen, din_idx,
queue_full, o_request, o_request_valid, dot, doten, dot_idx);
end
end
endgenerate
generate
for (i=0; i<W_LOG; i=i+1) begin: connection
if (i == W_LOG-1) begin
assign stage[W_LOG-1].queue_in_full = QUEUE_IN_FULL;
assign O_REQUEST = stage[W_LOG-1].o_request;
assign O_REQUEST_VALID = stage[W_LOG-1].o_request_valid;
assign stage[W_LOG-1].din = DIN;
assign stage[W_LOG-1].dinen = DINEN;
assign stage[W_LOG-1].din_idx = DIN_IDX;
end else begin
assign stage[i].queue_in_full = stage[i+1].body.queue_full;
assign stage[i+1].body.i_request = stage[i].o_request;
assign stage[i+1].body.i_request_valid = stage[i].o_request_valid;
assign stage[i].din = stage[i+1].dot;
assign stage[i].dinen = stage[i+1].doten;
assign stage[i].din_idx = stage[i+1].body.dot_idx;
end
end
endgenerate
assign stage[0].root.in_full = IN_FULL;
assign DOT = stage[0].dot;
assign DOTEN = stage[0].doten;
endmodule | 0 |
5,209 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire [C_LOG-1:0] enq_idx,
input wire deq,
input wire [C_LOG-1:0] deq_idx,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire [(1<<C_LOG)-1:0] emp,
output wire [(1<<C_LOG)-1:0] full);
reg [(1<<C_LOG)-1:0] head_list;
reg [(1<<C_LOG)-1:0] tail_list;
reg [FIFO_WIDTH-1:0] mem [(1<<C_LOG)-1:0];
genvar i;
generate
for (i=0; i<(1<<C_LOG); i=i+1) begin: channels
assign emp[i] = (head_list[i] == tail_list[i]);
assign full[i] = (head_list[i] == ~tail_list[i]);
end
endgenerate
wire [C_LOG-1:0] raddr = deq_idx;
wire [C_LOG-1:0] waddr = enq_idx;
always @(posedge CLK) dot <= mem[raddr];
always @(posedge CLK) begin
if (RST) begin
head_list <= 0;
tail_list <= 0;
end else begin
case ({enq, deq})
2'b01: begin
head_list[deq_idx] <= ~head_list[deq_idx];
end
2'b10: begin
mem[waddr] <= din;
tail_list[enq_idx] <= ~tail_list[enq_idx];
end
2'b11: begin
mem[waddr] <= din;
head_list[deq_idx] <= ~head_list[deq_idx];
tail_list[enq_idx] <= ~tail_list[enq_idx];
end
endcase
end
end
endmodule | module _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2,
parameter FIFO_WIDTH = 32)
(input wire CLK,
input wire RST,
input wire enq,
input wire [C_LOG-1:0] enq_idx,
input wire deq,
input wire [C_LOG-1:0] deq_idx,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire [(1<<C_LOG)-1:0] emp,
output wire [(1<<C_LOG)-1:0] full); |
reg [(1<<C_LOG)-1:0] head_list;
reg [(1<<C_LOG)-1:0] tail_list;
reg [FIFO_WIDTH-1:0] mem [(1<<C_LOG)-1:0];
genvar i;
generate
for (i=0; i<(1<<C_LOG); i=i+1) begin: channels
assign emp[i] = (head_list[i] == tail_list[i]);
assign full[i] = (head_list[i] == ~tail_list[i]);
end
endgenerate
wire [C_LOG-1:0] raddr = deq_idx;
wire [C_LOG-1:0] waddr = enq_idx;
always @(posedge CLK) dot <= mem[raddr];
always @(posedge CLK) begin
if (RST) begin
head_list <= 0;
tail_list <= 0;
end else begin
case ({enq, deq})
2'b01: begin
head_list[deq_idx] <= ~head_list[deq_idx];
end
2'b10: begin
mem[waddr] <= din;
tail_list[enq_idx] <= ~tail_list[enq_idx];
end
2'b11: begin
mem[waddr] <= din;
head_list[deq_idx] <= ~head_list[deq_idx];
tail_list[enq_idx] <= ~tail_list[enq_idx];
end
endcase
end
end
endmodule | 0 |
5,210 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module BRAM #(parameter M_LOG = 2,
parameter DATW = 64)
(input wire CLK,
input wire WE,
input wire [M_LOG-1:0] RADDR,
input wire [M_LOG-1:0] WADDR,
input wire [DATW-1:0] DIN,
output reg [DATW-1:0] DOT);
reg [DATW-1:0] mem [(1<<M_LOG)-1:0];
always @(posedge CLK) DOT <= mem[RADDR];
always @(posedge CLK) if (WE) mem[WADDR] <= DIN;
endmodule | module BRAM #(parameter M_LOG = 2,
parameter DATW = 64)
(input wire CLK,
input wire WE,
input wire [M_LOG-1:0] RADDR,
input wire [M_LOG-1:0] WADDR,
input wire [DATW-1:0] DIN,
output reg [DATW-1:0] DOT); |
reg [DATW-1:0] mem [(1<<M_LOG)-1:0];
always @(posedge CLK) DOT <= mem[RADDR];
always @(posedge CLK) if (WE) mem[WADDR] <= DIN;
endmodule | 0 |
5,211 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module TREE_FILLER #(parameter W_LOG = 2,
parameter P_LOG = 3,
parameter Q_SIZE = 2,
parameter DATW = 64)
(input wire CLK,
input wire RST,
input wire [W_LOG-1:0] I_REQUEST,
input wire I_REQUEST_VALID,
input wire [(DATW<<P_LOG)-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire QUEUE_FULL,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [W_LOG-1:0] DOT_IDX,
output wire [(1<<W_LOG)-1:0] emp);
localparam NUM_RECORD = (1<<P_LOG);
wire queue_enq;
wire queue_deq;
wire [W_LOG-1:0] queue_din;
wire [W_LOG-1:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [Q_SIZE:0] queue_cnt;
reg [W_LOG-1:0] queue_dot_buf;
wire bram_we;
wire [W_LOG-1:0] bram_raddr;
wire [W_LOG-1:0] bram_waddr;
wire [DATW-1:0] bram_din [NUM_RECORD-1:0];
wire [DATW-1:0] bram_dot [NUM_RECORD-1:0];
reg [P_LOG-1:0] head_list [(1<<W_LOG)-1:0];
wire [(1<<W_LOG)-1:0] emp_list;
reg data_ready;
assign queue_enq = I_REQUEST_VALID;
assign queue_deq = ~|{queue_emp, emp_list[queue_dot]};
assign queue_din = I_REQUEST;
assign bram_we = DINEN;
assign bram_raddr = queue_dot;
assign bram_waddr = DIN_IDX;
DFIFO #(Q_SIZE, W_LOG)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
genvar i;
generate
for (i=0; i<NUM_RECORD; i=i+1) begin: entries
assign bram_din[i] = DIN[DATW*(i+1)-1:DATW*i];
BRAM #(W_LOG, DATW)
bram(CLK, bram_we, bram_raddr, bram_waddr, bram_din[i], bram_dot[i]);
end
for (i=0; i<(1<<W_LOG); i=i+1) begin: logical_fifo
reg [P_LOG:0] head;
always @(posedge CLK) begin
if (RST) begin
head <= NUM_RECORD;
end else begin
case ({&{bram_we,(bram_waddr == i)}, &{queue_deq,(bram_raddr == i)}})
2'b01: head <= head + 1;
2'b10: head <= 0;
endcase
end
end
always @(posedge CLK) begin
head_list[i] <= head[P_LOG-1:0];
end
assign emp_list[i] = head[P_LOG];
end
endgenerate
always @(posedge CLK) queue_dot_buf <= queue_dot;
always @(posedge CLK) data_ready <= (RST) ? 0 : queue_deq;
assign QUEUE_FULL = queue_ful;
assign DOT = bram_dot[head_list[queue_dot_buf]];
assign DOTEN = data_ready;
assign DOT_IDX = queue_dot_buf;
assign emp = emp_list;
endmodule | module TREE_FILLER #(parameter W_LOG = 2,
parameter P_LOG = 3,
parameter Q_SIZE = 2,
parameter DATW = 64)
(input wire CLK,
input wire RST,
input wire [W_LOG-1:0] I_REQUEST,
input wire I_REQUEST_VALID,
input wire [(DATW<<P_LOG)-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire QUEUE_FULL,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [W_LOG-1:0] DOT_IDX,
output wire [(1<<W_LOG)-1:0] emp); |
localparam NUM_RECORD = (1<<P_LOG);
wire queue_enq;
wire queue_deq;
wire [W_LOG-1:0] queue_din;
wire [W_LOG-1:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [Q_SIZE:0] queue_cnt;
reg [W_LOG-1:0] queue_dot_buf;
wire bram_we;
wire [W_LOG-1:0] bram_raddr;
wire [W_LOG-1:0] bram_waddr;
wire [DATW-1:0] bram_din [NUM_RECORD-1:0];
wire [DATW-1:0] bram_dot [NUM_RECORD-1:0];
reg [P_LOG-1:0] head_list [(1<<W_LOG)-1:0];
wire [(1<<W_LOG)-1:0] emp_list;
reg data_ready;
assign queue_enq = I_REQUEST_VALID;
assign queue_deq = ~|{queue_emp, emp_list[queue_dot]};
assign queue_din = I_REQUEST;
assign bram_we = DINEN;
assign bram_raddr = queue_dot;
assign bram_waddr = DIN_IDX;
DFIFO #(Q_SIZE, W_LOG)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
genvar i;
generate
for (i=0; i<NUM_RECORD; i=i+1) begin: entries
assign bram_din[i] = DIN[DATW*(i+1)-1:DATW*i];
BRAM #(W_LOG, DATW)
bram(CLK, bram_we, bram_raddr, bram_waddr, bram_din[i], bram_dot[i]);
end
for (i=0; i<(1<<W_LOG); i=i+1) begin: logical_fifo
reg [P_LOG:0] head;
always @(posedge CLK) begin
if (RST) begin
head <= NUM_RECORD;
end else begin
case ({&{bram_we,(bram_waddr == i)}, &{queue_deq,(bram_raddr == i)}})
2'b01: head <= head + 1;
2'b10: head <= 0;
endcase
end
end
always @(posedge CLK) begin
head_list[i] <= head[P_LOG-1:0];
end
assign emp_list[i] = head[P_LOG];
end
endgenerate
always @(posedge CLK) queue_dot_buf <= queue_dot;
always @(posedge CLK) data_ready <= (RST) ? 0 : queue_deq;
assign QUEUE_FULL = queue_ful;
assign DOT = bram_dot[head_list[queue_dot_buf]];
assign DOTEN = data_ready;
assign DOT_IDX = queue_dot_buf;
assign emp = emp_list;
endmodule | 0 |
5,212 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | module | module vMERGE_SORTER_TREE #(parameter W_LOG = 2,
parameter P_LOG = 3,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<P_LOG)-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [(1<<W_LOG)-1:0] emp);
wire [W_LOG-1:0] tree_filler_i_request;
wire tree_filler_i_request_valid;
wire [(DATW<<P_LOG)-1:0] tree_filler_din;
wire tree_filler_dinen;
wire [W_LOG-1:0] tree_filler_din_idx;
wire tree_filler_queue_full;
wire [DATW-1:0] tree_filler_dot;
wire tree_filler_doten;
wire [W_LOG-1:0] tree_filler_dot_idx;
wire [(1<<W_LOG)-1:0] tree_filler_emp;
wire sorter_stage_tree_in_full;
wire [DATW-1:0] sorter_stage_tree_dot;
wire sorter_stage_tree_doten;
assign tree_filler_din = DIN;
assign tree_filler_dinen = DINEN;
assign tree_filler_din_idx = DIN_IDX;
assign sorter_stage_tree_in_full = IN_FULL;
TREE_FILLER #(W_LOG, P_LOG, Q_SIZE, DATW)
tree_filler(CLK, RST, tree_filler_i_request, tree_filler_i_request_valid, tree_filler_din, tree_filler_dinen, tree_filler_din_idx,
tree_filler_queue_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx, tree_filler_emp);
SORTER_STAGE_TREE #(W_LOG, Q_SIZE, FIFO_SIZE, DATW, KEYW)
sorter_stage_tree(CLK, RST, tree_filler_queue_full, sorter_stage_tree_in_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx,
tree_filler_i_request, tree_filler_i_request_valid, sorter_stage_tree_dot, sorter_stage_tree_doten);
assign DOT = sorter_stage_tree_dot;
assign DOTEN = sorter_stage_tree_doten;
assign emp = tree_filler_emp;
endmodule | module vMERGE_SORTER_TREE #(parameter W_LOG = 2,
parameter P_LOG = 3,
parameter Q_SIZE = 2,
parameter FIFO_SIZE = 2,
parameter DATW = 64,
parameter KEYW = 32)
(input wire CLK,
input wire RST,
input wire IN_FULL,
input wire [(DATW<<P_LOG)-1:0] DIN,
input wire DINEN,
input wire [W_LOG-1:0] DIN_IDX,
output wire [DATW-1:0] DOT,
output wire DOTEN,
output wire [(1<<W_LOG)-1:0] emp); |
wire [W_LOG-1:0] tree_filler_i_request;
wire tree_filler_i_request_valid;
wire [(DATW<<P_LOG)-1:0] tree_filler_din;
wire tree_filler_dinen;
wire [W_LOG-1:0] tree_filler_din_idx;
wire tree_filler_queue_full;
wire [DATW-1:0] tree_filler_dot;
wire tree_filler_doten;
wire [W_LOG-1:0] tree_filler_dot_idx;
wire [(1<<W_LOG)-1:0] tree_filler_emp;
wire sorter_stage_tree_in_full;
wire [DATW-1:0] sorter_stage_tree_dot;
wire sorter_stage_tree_doten;
assign tree_filler_din = DIN;
assign tree_filler_dinen = DINEN;
assign tree_filler_din_idx = DIN_IDX;
assign sorter_stage_tree_in_full = IN_FULL;
TREE_FILLER #(W_LOG, P_LOG, Q_SIZE, DATW)
tree_filler(CLK, RST, tree_filler_i_request, tree_filler_i_request_valid, tree_filler_din, tree_filler_dinen, tree_filler_din_idx,
tree_filler_queue_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx, tree_filler_emp);
SORTER_STAGE_TREE #(W_LOG, Q_SIZE, FIFO_SIZE, DATW, KEYW)
sorter_stage_tree(CLK, RST, tree_filler_queue_full, sorter_stage_tree_in_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx,
tree_filler_i_request, tree_filler_i_request_valid, sorter_stage_tree_dot, sorter_stage_tree_doten);
assign DOT = sorter_stage_tree_dot;
assign DOTEN = sorter_stage_tree_doten;
assign emp = tree_filler_emp;
endmodule | 0 |
5,213 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | function | function [DATW-1:0] mux;
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | function [DATW-1:0] mux; |
input [DATW-1:0] a;
input [DATW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction | 0 |
5,214 | data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v | 113,471,686 | virtualtree.v | v | 958 | 157 | [] | [] | [] | [(9, 39), (44, 74), (79, 108), (113, 152), (157, 221), (226, 274), (279, 435), (440, 500), (505, 574), (579, 632), (637, 651), (656, 744), (904, 955)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter FIFO_WIDTH = 64) \n ^~~~~~~~~~~~~~\n : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter C_LOG = 2, \n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter W_LOG = 2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n wire [W_LOG-2:0] enq_idx = (ENQ_IDX >> 1);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 5,637 | function | function [W_LOG-1:0] request_gen;
input [W_LOG-1:0] in;
input [1:0] sel;
begin
case (sel)
2'b01: request_gen = (in << 1);
2'b10: request_gen = (in << 1) + 1;
endcase
end
endfunction | function [W_LOG-1:0] request_gen; |
input [W_LOG-1:0] in;
input [1:0] sel;
begin
case (sel)
2'b01: request_gen = (in << 1);
2'b10: request_gen = (in << 1) + 1;
endcase
end
endfunction | 0 |
5,215 | data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree.v | 113,471,686 | tb_virtualtree.v | v | 255 | 770 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree.v:7: Cannot find include file: virtualtree.v\n`include "virtualtree.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v.v\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v.sv\n virtualtree.v\n virtualtree.v.v\n virtualtree.v.sv\n obj_dir/virtualtree.v\n obj_dir/virtualtree.v.v\n obj_dir/virtualtree.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree.v:142: Unsupported: Ignoring delay on this delayed statement.\n reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree.v:143: Unsupported: Ignoring delay on this delayed statement.\n reg RST; initial begin RST=1; #400 RST=0; end\n ^\n%Error: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree.v:220: Unsupported: $fflush of all handles does not map to C++.\n $fflush();\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 5,638 | module | module tb_vMERGE_SORTER_TREE();
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
wire [(`DATW<<(`W_LOG+`P_LOG))-1:0] tree_filler_din_all_way;
wire [(`DATW<<(`W_LOG+`P_LOG))-1:0] tree_filler_din_shifted;
wire [(1<<`W_LOG)-1:0] tree_filler_dinen_all_way;
wire [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
wire vmerge_sorter_tree_dinen;
wire [`W_LOG-1:0] vmerge_sorter_tree_din_idx;
wire [`DATW-1:0] vmerge_sorter_tree_dot;
wire vmerge_sorter_tree_doten;
wire [(1<<`W_LOG)-1:0] vmerge_sorter_tree_emp;
reg [`W_LOG-1:0] round_robin_sel;
reg [`DATW-1:0] check_record;
genvar i, j;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: way
wire [(`DATW<<`P_LOG)-1:0] din_per_way;
for (j=0; j<(1<<`P_LOG); j=j+1) begin: record
wire [`KEYW-1:0] init_key = i + 1 + j * (1<<`W_LOG);
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (tree_filler_dinen_all_way[i]) init_record <= init_record + (1<<(`W_LOG+`P_LOG));
end
assign din_per_way[`DATW*(j+1)-1:`DATW*j] = init_record;
end
assign tree_filler_din_all_way[(`DATW<<`P_LOG)*(i+1)-1:(`DATW<<`P_LOG)*i] = din_per_way;
assign tree_filler_dinen_all_way[i] = (round_robin_sel == i) && vmerge_sorter_tree_emp[i];
end
endgenerate
always @(posedge CLK) begin
if (RST) round_robin_sel <= 0;
else round_robin_sel <= round_robin_sel + 1;
end
assign tree_filler_din_shifted = (tree_filler_din_all_way >> ((`DATW<<`P_LOG) * round_robin_sel));
assign vmerge_sorter_tree_din = tree_filler_din_shifted[(`DATW<<`P_LOG)-1:0];
assign vmerge_sorter_tree_dinen = (|tree_filler_dinen_all_way) && (~RST);
assign vmerge_sorter_tree_din_idx = round_robin_sel;
vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx,
vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
always @(posedge CLK) begin
if (!RST) begin
$write("| %d, %b ", round_robin_sel, vmerge_sorter_tree_emp);
$write("| %d ", vmerge_sorter_tree.tree_filler.queue_cnt);
if (vmerge_sorter_tree.tree_filler_doten) $write("%8d(%4d) ", vmerge_sorter_tree.tree_filler_dot[`KEYW-1:0], vmerge_sorter_tree.tree_filler_dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.QUEUE_IN_FULL, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_emp, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp0, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp1, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request);
$write("| %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_cnt);
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].o_request_valid) $write(" %4d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].o_request);
else $write(" ");
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].doten) $write("%8d(%3d) ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].dot[`KEYW-1:0], vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.QUEUE_IN_FULL, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_emp, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp0, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp1, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request);
$write("| %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_cnt);
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].o_request_valid) $write(" %3d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].o_request);
else $write(" ");
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].doten) $write("%8d(%3d) ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].dot[`KEYW-1:0], vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.dot_idx);
else $write(" ");
$write("||");
if (vmerge_sorter_tree_doten) $write(" %d ", vmerge_sorter_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
end else begin
if (vmerge_sorter_tree_doten) begin
check_record <= check_record + 1;
if (vmerge_sorter_tree_dot != check_record) begin
$write("\nError!\n");
$write("%d %d\n", vmerge_sorter_tree_dot[`KEYW-1:0], check_record[`KEYW-1:0]);
$finish();
end
end
end
end
reg [31:0] cycle;
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
cycle <= cycle + 1;
if (cycle >= 10000) $finish();
end
end
endmodule | module tb_vMERGE_SORTER_TREE(); |
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
wire [(`DATW<<(`W_LOG+`P_LOG))-1:0] tree_filler_din_all_way;
wire [(`DATW<<(`W_LOG+`P_LOG))-1:0] tree_filler_din_shifted;
wire [(1<<`W_LOG)-1:0] tree_filler_dinen_all_way;
wire [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
wire vmerge_sorter_tree_dinen;
wire [`W_LOG-1:0] vmerge_sorter_tree_din_idx;
wire [`DATW-1:0] vmerge_sorter_tree_dot;
wire vmerge_sorter_tree_doten;
wire [(1<<`W_LOG)-1:0] vmerge_sorter_tree_emp;
reg [`W_LOG-1:0] round_robin_sel;
reg [`DATW-1:0] check_record;
genvar i, j;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: way
wire [(`DATW<<`P_LOG)-1:0] din_per_way;
for (j=0; j<(1<<`P_LOG); j=j+1) begin: record
wire [`KEYW-1:0] init_key = i + 1 + j * (1<<`W_LOG);
reg [`DATW-1:0] init_record;
always @(posedge CLK) begin
if (RST) init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
else if (tree_filler_dinen_all_way[i]) init_record <= init_record + (1<<(`W_LOG+`P_LOG));
end
assign din_per_way[`DATW*(j+1)-1:`DATW*j] = init_record;
end
assign tree_filler_din_all_way[(`DATW<<`P_LOG)*(i+1)-1:(`DATW<<`P_LOG)*i] = din_per_way;
assign tree_filler_dinen_all_way[i] = (round_robin_sel == i) && vmerge_sorter_tree_emp[i];
end
endgenerate
always @(posedge CLK) begin
if (RST) round_robin_sel <= 0;
else round_robin_sel <= round_robin_sel + 1;
end
assign tree_filler_din_shifted = (tree_filler_din_all_way >> ((`DATW<<`P_LOG) * round_robin_sel));
assign vmerge_sorter_tree_din = tree_filler_din_shifted[(`DATW<<`P_LOG)-1:0];
assign vmerge_sorter_tree_dinen = (|tree_filler_dinen_all_way) && (~RST);
assign vmerge_sorter_tree_din_idx = round_robin_sel;
vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx,
vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
always @(posedge CLK) begin
if (!RST) begin
$write("| %d, %b ", round_robin_sel, vmerge_sorter_tree_emp);
$write("| %d ", vmerge_sorter_tree.tree_filler.queue_cnt);
if (vmerge_sorter_tree.tree_filler_doten) $write("%8d(%4d) ", vmerge_sorter_tree.tree_filler_dot[`KEYW-1:0], vmerge_sorter_tree.tree_filler_dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.QUEUE_IN_FULL, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_emp, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp0, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp1, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request);
$write("| %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_cnt);
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].o_request_valid) $write(" %4d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].o_request);
else $write(" ");
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].doten) $write("%8d(%3d) ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].dot[`KEYW-1:0], vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-1].body.dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.QUEUE_IN_FULL, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_emp, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp0, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp1, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request_buf, vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request);
$write("| %d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_cnt);
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].o_request_valid) $write(" %3d ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].o_request);
else $write(" ");
if (vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].doten) $write("%8d(%3d) ", vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].dot[`KEYW-1:0], vmerge_sorter_tree.sorter_stage_tree.stage[`W_LOG-2].body.dot_idx);
else $write(" ");
$write("||");
if (vmerge_sorter_tree_doten) $write(" %d ", vmerge_sorter_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
end else begin
if (vmerge_sorter_tree_doten) begin
check_record <= check_record + 1;
if (vmerge_sorter_tree_dot != check_record) begin
$write("\nError!\n");
$write("%d %d\n", vmerge_sorter_tree_dot[`KEYW-1:0], check_record[`KEYW-1:0]);
$finish();
end
end
end
end
reg [31:0] cycle;
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
cycle <= cycle + 1;
if (cycle >= 10000) $finish();
end
end
endmodule | 0 |
5,216 | data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v | 113,471,686 | tb_virtualtree_random.v | v | 190 | 618 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v:3: Cannot find include file: virtualtree.v\n`include "virtualtree.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v.v\n data/full_repos/permissive/113471686/virtualtree/test,data/full_repos/permissive/113471686/virtualtree.v.sv\n virtualtree.v\n virtualtree.v.v\n virtualtree.v.sv\n obj_dir/virtualtree.v\n obj_dir/virtualtree.v.v\n obj_dir/virtualtree.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v:15: Unsupported: Ignoring delay on this delayed statement.\n reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v:16: Unsupported: Ignoring delay on this delayed statement.\n reg RST; initial begin RST=1; #400 RST=0; end\n ^\n%Error: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v:112: Unsupported: $fflush of all handles does not map to C++.\n $fflush();\n ^~~~~~~\n%Error: data/full_repos/permissive/113471686/virtualtree/test/tb_virtualtree_random.v:164: Unsupported: $fflush of all handles does not map to C++.\n $fflush();\n ^~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n' | 5,639 | module | module tb_SORTER_STAGE_TREE_RANDOM();
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
reg [`KEYW-1:0] datamem [`DATANUM_PER_WAY*(1<<`W_LOG)-1:0];
reg [31:0] index [(1<<`W_LOG)-1:0];
reg [31:0] read_cnt [(1<<`W_LOG)-1:0];
wire queue_enq;
wire queue_deq;
wire [`W_LOG-1:0] queue_din;
wire [`W_LOG-1:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [`Q_SIZE:0] queue_cnt;
wire [`W_LOG-1:0] tree_filler_i_request;
wire tree_filler_i_request_valid;
wire tree_filler_queue_full;
wire [`DATW-1:0] tree_filler_dot;
wire tree_filler_doten;
wire [`W_LOG-1:0] tree_filler_dot_idx;
wire sorter_stage_tree_in_full;
wire [`DATW-1:0] sorter_stage_tree_dot;
wire sorter_stage_tree_doten;
initial begin
$readmemh("initdata.hex", datamem, 0, `DATANUM_PER_WAY*(1<<`W_LOG)-1);
end
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: way
always @(posedge CLK) begin
if (RST) begin
index[i] <= `DATANUM_PER_WAY * i;
read_cnt[i] <= 0;
end else if ((queue_dot == i) && !queue_emp && (read_cnt[i] != `DATANUM_PER_WAY)) begin
index[i] <= index[i] + 1;
read_cnt[i] <= read_cnt[i] + 1;
end
end
end
endgenerate
assign queue_enq = tree_filler_i_request_valid;
assign queue_deq = !queue_emp;
assign queue_din = tree_filler_i_request;
assign tree_filler_queue_full = queue_ful;
assign sorter_stage_tree_in_full = 1'b0;
assign tree_filler_dot = (read_cnt[queue_dot] != `DATANUM_PER_WAY) ? {{(`DATW-`KEYW){1'b1}}, datamem[index[queue_dot]]} : {(`DATW){1'b1}};
assign tree_filler_doten = queue_deq;
assign tree_filler_dot_idx = queue_dot;
DFIFO #(`Q_SIZE, `W_LOG)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
SORTER_STAGE_TREE #(`W_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
sorter_stage_tree(CLK, RST, tree_filler_queue_full, sorter_stage_tree_in_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx,
tree_filler_i_request, tree_filler_i_request_valid, sorter_stage_tree_dot, sorter_stage_tree_doten);
reg [31:0] sorter_stage_tree_dotnum;
reg sort_done;
reg [31:0] cycle;
reg [31:0] perf_cnt;
reg count_start;
always @(posedge CLK) begin
if (!RST && !sort_done) begin
$write("%d | %d ", cycle, queue_cnt);
if (tree_filler_doten) $write("%08x(%4d) ", tree_filler_dot[`KEYW-1:0], tree_filler_dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.QUEUE_IN_FULL, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_emp, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp0, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp1, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot_buf, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request_buf, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request);
$write("| %d ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_cnt);
if (sorter_stage_tree.stage[`W_LOG-1].o_request_valid) $write(" %4d ", sorter_stage_tree.stage[`W_LOG-1].o_request);
else $write(" ");
if (sorter_stage_tree.stage[`W_LOG-1].doten) $write("%08x(%3d) ", sorter_stage_tree.stage[`W_LOG-1].dot[`KEYW-1:0], sorter_stage_tree.stage[`W_LOG-1].body.dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.QUEUE_IN_FULL, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_emp, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp0, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp1, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot_buf, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request_buf, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request);
$write("| %d ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_cnt);
if (sorter_stage_tree.stage[`W_LOG-2].o_request_valid) $write(" %3d ", sorter_stage_tree.stage[`W_LOG-2].o_request);
else $write(" ");
if (sorter_stage_tree.stage[`W_LOG-2].doten) $write("%08x(%3d) ", sorter_stage_tree.stage[`W_LOG-2].dot[`KEYW-1:0], sorter_stage_tree.stage[`W_LOG-2].body.dot_idx);
else $write(" ");
$write("||");
if (sorter_stage_tree_doten) $write(" %08x ", sorter_stage_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
if (!sort_done) cycle <= cycle + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
perf_cnt <= 0;
count_start <= 0;
end else begin
if ((sorter_stage_tree_doten || count_start) && !sort_done) begin
perf_cnt <= perf_cnt + 1;
end
if (sorter_stage_tree_doten) count_start <= 1;
end
end
always @(posedge CLK) begin
if (RST) begin
sorter_stage_tree_dotnum <= 0;
sort_done <= 0;
end else begin
if (sorter_stage_tree_doten && !sort_done) begin
sorter_stage_tree_dotnum <= sorter_stage_tree_dotnum + 1;
sort_done <= (sorter_stage_tree_dotnum == `DATANUM_PER_WAY*(1<<`W_LOG)-1);
end
end
end
always @(posedge CLK) begin
if (sort_done) begin: simulation_finish
$write("\nIt takes %d (%d) cycles\n", cycle, perf_cnt);
$write("Sorting finished!\n");
$finish();
end
end
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (sorter_stage_tree_doten && !sort_done) begin
$fwrite(fp, "%08x\n", sorter_stage_tree_dot[`KEYW-1:0]);
$fflush();
end
if (sort_done) $fclose(fp);
end
endmodule | module tb_SORTER_STAGE_TREE_RANDOM(); |
reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
reg RST; initial begin RST=1; #400 RST=0; end
reg [`KEYW-1:0] datamem [`DATANUM_PER_WAY*(1<<`W_LOG)-1:0];
reg [31:0] index [(1<<`W_LOG)-1:0];
reg [31:0] read_cnt [(1<<`W_LOG)-1:0];
wire queue_enq;
wire queue_deq;
wire [`W_LOG-1:0] queue_din;
wire [`W_LOG-1:0] queue_dot;
wire queue_emp;
wire queue_ful;
wire [`Q_SIZE:0] queue_cnt;
wire [`W_LOG-1:0] tree_filler_i_request;
wire tree_filler_i_request_valid;
wire tree_filler_queue_full;
wire [`DATW-1:0] tree_filler_dot;
wire tree_filler_doten;
wire [`W_LOG-1:0] tree_filler_dot_idx;
wire sorter_stage_tree_in_full;
wire [`DATW-1:0] sorter_stage_tree_dot;
wire sorter_stage_tree_doten;
initial begin
$readmemh("initdata.hex", datamem, 0, `DATANUM_PER_WAY*(1<<`W_LOG)-1);
end
genvar i;
generate
for (i=0; i<(1<<`W_LOG); i=i+1) begin: way
always @(posedge CLK) begin
if (RST) begin
index[i] <= `DATANUM_PER_WAY * i;
read_cnt[i] <= 0;
end else if ((queue_dot == i) && !queue_emp && (read_cnt[i] != `DATANUM_PER_WAY)) begin
index[i] <= index[i] + 1;
read_cnt[i] <= read_cnt[i] + 1;
end
end
end
endgenerate
assign queue_enq = tree_filler_i_request_valid;
assign queue_deq = !queue_emp;
assign queue_din = tree_filler_i_request;
assign tree_filler_queue_full = queue_ful;
assign sorter_stage_tree_in_full = 1'b0;
assign tree_filler_dot = (read_cnt[queue_dot] != `DATANUM_PER_WAY) ? {{(`DATW-`KEYW){1'b1}}, datamem[index[queue_dot]]} : {(`DATW){1'b1}};
assign tree_filler_doten = queue_deq;
assign tree_filler_dot_idx = queue_dot;
DFIFO #(`Q_SIZE, `W_LOG)
request_queue(CLK, RST, queue_enq, queue_deq, queue_din,
queue_dot, queue_emp, queue_ful, queue_cnt);
SORTER_STAGE_TREE #(`W_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
sorter_stage_tree(CLK, RST, tree_filler_queue_full, sorter_stage_tree_in_full, tree_filler_dot, tree_filler_doten, tree_filler_dot_idx,
tree_filler_i_request, tree_filler_i_request_valid, sorter_stage_tree_dot, sorter_stage_tree_doten);
reg [31:0] sorter_stage_tree_dotnum;
reg sort_done;
reg [31:0] cycle;
reg [31:0] perf_cnt;
reg count_start;
always @(posedge CLK) begin
if (!RST && !sort_done) begin
$write("%d | %d ", cycle, queue_cnt);
if (tree_filler_doten) $write("%08x(%4d) ", tree_filler_dot[`KEYW-1:0], tree_filler_dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.QUEUE_IN_FULL, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_emp, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp0, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.ram_layer_emp1, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot_buf, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_dot, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request_buf, sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.same_request);
$write("| %d ", sorter_stage_tree.stage[`W_LOG-1].body.sorter_stage_body.queue_cnt);
if (sorter_stage_tree.stage[`W_LOG-1].o_request_valid) $write(" %4d ", sorter_stage_tree.stage[`W_LOG-1].o_request);
else $write(" ");
if (sorter_stage_tree.stage[`W_LOG-1].doten) $write("%08x(%3d) ", sorter_stage_tree.stage[`W_LOG-1].dot[`KEYW-1:0], sorter_stage_tree.stage[`W_LOG-1].body.dot_idx);
else $write(" ");
$write("||");
$write("state: %d ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.state);
$write("| %b %b %b %b, %d %d, %b %b ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.QUEUE_IN_FULL, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_emp, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp0, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.ram_layer_emp1, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot_buf, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_dot, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request_buf, sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.same_request);
$write("| %d ", sorter_stage_tree.stage[`W_LOG-2].body.sorter_stage_body.queue_cnt);
if (sorter_stage_tree.stage[`W_LOG-2].o_request_valid) $write(" %3d ", sorter_stage_tree.stage[`W_LOG-2].o_request);
else $write(" ");
if (sorter_stage_tree.stage[`W_LOG-2].doten) $write("%08x(%3d) ", sorter_stage_tree.stage[`W_LOG-2].dot[`KEYW-1:0], sorter_stage_tree.stage[`W_LOG-2].body.dot_idx);
else $write(" ");
$write("||");
if (sorter_stage_tree_doten) $write(" %08x ", sorter_stage_tree_dot[`KEYW-1:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (RST) begin
cycle <= 0;
end else begin
if (!sort_done) cycle <= cycle + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
perf_cnt <= 0;
count_start <= 0;
end else begin
if ((sorter_stage_tree_doten || count_start) && !sort_done) begin
perf_cnt <= perf_cnt + 1;
end
if (sorter_stage_tree_doten) count_start <= 1;
end
end
always @(posedge CLK) begin
if (RST) begin
sorter_stage_tree_dotnum <= 0;
sort_done <= 0;
end else begin
if (sorter_stage_tree_doten && !sort_done) begin
sorter_stage_tree_dotnum <= sorter_stage_tree_dotnum + 1;
sort_done <= (sorter_stage_tree_dotnum == `DATANUM_PER_WAY*(1<<`W_LOG)-1);
end
end
end
always @(posedge CLK) begin
if (sort_done) begin: simulation_finish
$write("\nIt takes %d (%d) cycles\n", cycle, perf_cnt);
$write("Sorting finished!\n");
$finish();
end
end
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (sorter_stage_tree_doten && !sort_done) begin
$fwrite(fp, "%08x\n", sorter_stage_tree_dot[`KEYW-1:0]);
$fflush();
end
if (sort_done) $fclose(fp);
end
endmodule | 0 |
5,218 | data/full_repos/permissive/113582216/Experiment/design/controller.v | 113,582,216 | controller.v | v | 216 | 83 | [] | [] | [] | [(21, 215)] | null | data/verilator_xmls/3b21e8bc-70ae-4a5c-a85c-727077792d2e.xml | null | 5,641 | module | module controller(
input rst_i,
input toggle_i,
input clk_i,
output [3:0] dsec_o,
output [3:0] sec0_o,
output [3:0] sec1_o,
output [3:0] min_o
);
parameter RESET = 0, STOP = 1, RUN = 2, OVERFLOW = 3;
parameter BASE = 20;
reg [3:0] dsec_reg;
reg [3:0] sec0_reg;
reg [3:0] sec1_reg;
reg [3:0] min_reg;
reg [1:0] current_state, next_state;
wire overflow;
initial
begin
current_state <= RESET;
end
always@(posedge clk_i)
begin
current_state <= next_state;
end
always@(current_state or rst_i or toggle_i or overflow)
begin
case(current_state)
RESET:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= RUN;
else
next_state <= STOP;
end
STOP:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= RUN;
else if(overflow)
next_state <= OVERFLOW;
else
next_state <= STOP;
end
RUN:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= STOP;
else if(overflow)
next_state <= OVERFLOW;
else
next_state <= RUN;
end
OVERFLOW:
begin
if(rst_i || toggle_i)
next_state <= RESET;
else
next_state <= OVERFLOW;
end
default:
next_state <= RESET;
endcase
end
reg [4:0] basecnt;
always@(posedge clk_i)
begin
case(current_state)
RESET:
basecnt <= 0;
STOP:
basecnt <= basecnt;
RUN:
begin
if(basecnt == (BASE-1))
basecnt <= 0;
else
basecnt <= basecnt + 1;
end
OVERFLOW:
basecnt <= 0;
endcase
end
wire carry_dsec;
assign carry_dsec = ((dsec_reg == 9) && (basecnt == (BASE-1)));
always@(posedge clk_i)
begin
case(current_state)
RESET:
dsec_reg <= 0;
STOP:
dsec_reg <= dsec_reg;
RUN:
begin
if(carry_dsec)
dsec_reg <= 0;
else if(basecnt == (BASE-1))
dsec_reg <= dsec_reg + 1;
else
dsec_reg <= dsec_reg;
end
OVERFLOW:
dsec_reg <= 9;
endcase
end
wire carry_sec0;
assign carry_sec0 = (carry_dsec && (sec0_reg == 9));
always@(posedge clk_i)
begin
case(current_state)
RESET:
sec0_reg <= 0;
STOP:
sec0_reg <= sec0_reg;
RUN:
begin
if(carry_sec0)
sec0_reg <= 0;
else if(carry_dsec)
sec0_reg <= sec0_reg + 1;
else
sec0_reg <= sec0_reg;
end
OVERFLOW:
sec0_reg <= 9;
endcase
end
wire carry_sec1;
assign carry_sec1 = (carry_sec0 && (sec1_reg == 5));
always@(posedge clk_i)
begin
case(current_state)
RESET:
sec1_reg <= 0;
STOP:
sec1_reg <= sec1_reg;
RUN:
begin
if(carry_sec1)
sec1_reg <= 0;
else if(carry_sec0)
sec1_reg <= sec1_reg + 1;
else
sec1_reg <= sec1_reg;
end
OVERFLOW:
sec1_reg <= 5;
endcase
end
assign overflow = (carry_sec1 && (min_reg == 9));
always@(posedge clk_i)
begin
case(current_state)
RESET:
min_reg <= 0;
STOP:
min_reg <= min_reg;
RUN:
begin
if(overflow)
min_reg <= 9;
else if(carry_sec1)
min_reg <= min_reg + 1;
else
min_reg <= min_reg;
end
OVERFLOW:
min_reg <= 9;
endcase
end
assign dsec_o = dsec_reg;
assign sec0_o = sec0_reg;
assign sec1_o = sec1_reg;
assign min_o = min_reg;
endmodule | module controller(
input rst_i,
input toggle_i,
input clk_i,
output [3:0] dsec_o,
output [3:0] sec0_o,
output [3:0] sec1_o,
output [3:0] min_o
); |
parameter RESET = 0, STOP = 1, RUN = 2, OVERFLOW = 3;
parameter BASE = 20;
reg [3:0] dsec_reg;
reg [3:0] sec0_reg;
reg [3:0] sec1_reg;
reg [3:0] min_reg;
reg [1:0] current_state, next_state;
wire overflow;
initial
begin
current_state <= RESET;
end
always@(posedge clk_i)
begin
current_state <= next_state;
end
always@(current_state or rst_i or toggle_i or overflow)
begin
case(current_state)
RESET:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= RUN;
else
next_state <= STOP;
end
STOP:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= RUN;
else if(overflow)
next_state <= OVERFLOW;
else
next_state <= STOP;
end
RUN:
begin
if(rst_i)
next_state <= RESET;
else if(toggle_i)
next_state <= STOP;
else if(overflow)
next_state <= OVERFLOW;
else
next_state <= RUN;
end
OVERFLOW:
begin
if(rst_i || toggle_i)
next_state <= RESET;
else
next_state <= OVERFLOW;
end
default:
next_state <= RESET;
endcase
end
reg [4:0] basecnt;
always@(posedge clk_i)
begin
case(current_state)
RESET:
basecnt <= 0;
STOP:
basecnt <= basecnt;
RUN:
begin
if(basecnt == (BASE-1))
basecnt <= 0;
else
basecnt <= basecnt + 1;
end
OVERFLOW:
basecnt <= 0;
endcase
end
wire carry_dsec;
assign carry_dsec = ((dsec_reg == 9) && (basecnt == (BASE-1)));
always@(posedge clk_i)
begin
case(current_state)
RESET:
dsec_reg <= 0;
STOP:
dsec_reg <= dsec_reg;
RUN:
begin
if(carry_dsec)
dsec_reg <= 0;
else if(basecnt == (BASE-1))
dsec_reg <= dsec_reg + 1;
else
dsec_reg <= dsec_reg;
end
OVERFLOW:
dsec_reg <= 9;
endcase
end
wire carry_sec0;
assign carry_sec0 = (carry_dsec && (sec0_reg == 9));
always@(posedge clk_i)
begin
case(current_state)
RESET:
sec0_reg <= 0;
STOP:
sec0_reg <= sec0_reg;
RUN:
begin
if(carry_sec0)
sec0_reg <= 0;
else if(carry_dsec)
sec0_reg <= sec0_reg + 1;
else
sec0_reg <= sec0_reg;
end
OVERFLOW:
sec0_reg <= 9;
endcase
end
wire carry_sec1;
assign carry_sec1 = (carry_sec0 && (sec1_reg == 5));
always@(posedge clk_i)
begin
case(current_state)
RESET:
sec1_reg <= 0;
STOP:
sec1_reg <= sec1_reg;
RUN:
begin
if(carry_sec1)
sec1_reg <= 0;
else if(carry_sec0)
sec1_reg <= sec1_reg + 1;
else
sec1_reg <= sec1_reg;
end
OVERFLOW:
sec1_reg <= 5;
endcase
end
assign overflow = (carry_sec1 && (min_reg == 9));
always@(posedge clk_i)
begin
case(current_state)
RESET:
min_reg <= 0;
STOP:
min_reg <= min_reg;
RUN:
begin
if(overflow)
min_reg <= 9;
else if(carry_sec1)
min_reg <= min_reg + 1;
else
min_reg <= min_reg;
end
OVERFLOW:
min_reg <= 9;
endcase
end
assign dsec_o = dsec_reg;
assign sec0_o = sec0_reg;
assign sec1_o = sec1_reg;
assign min_o = min_reg;
endmodule | 1 |
5,220 | data/full_repos/permissive/113582216/Experiment/design/digitSeg.v | 113,582,216 | digitSeg.v | v | 46 | 83 | [] | [] | [] | [(21, 45)] | null | data/verilator_xmls/0ab3e60d-1466-4520-bb49-fb655648b05a.xml | null | 5,643 | module | module digitSeg(
input [3:0] bcd_i,
output a_o,
output b_o,
output c_o,
output d_o,
output e_o,
output f_o,
output g_o
);
assign {a_o,b_o,c_o,d_o,e_o,f_o,g_o} =
(bcd_i == 4'd0) ? 7'b0000001 :
(bcd_i == 4'd1) ? 7'b1001111 :
(bcd_i == 4'd2) ? 7'b0010010 :
(bcd_i == 4'd3) ? 7'b0000110 :
(bcd_i == 4'd4) ? 7'b1001100 :
(bcd_i == 4'd5) ? 7'b0100100 :
(bcd_i == 4'd6) ? 7'b0100000 :
(bcd_i == 4'd7) ? 7'b0001111 :
(bcd_i == 4'd8) ? 7'b0000000 :
(bcd_i == 4'd9) ? 7'b0000100 :
7'bx;
endmodule | module digitSeg(
input [3:0] bcd_i,
output a_o,
output b_o,
output c_o,
output d_o,
output e_o,
output f_o,
output g_o
); |
assign {a_o,b_o,c_o,d_o,e_o,f_o,g_o} =
(bcd_i == 4'd0) ? 7'b0000001 :
(bcd_i == 4'd1) ? 7'b1001111 :
(bcd_i == 4'd2) ? 7'b0010010 :
(bcd_i == 4'd3) ? 7'b0000110 :
(bcd_i == 4'd4) ? 7'b1001100 :
(bcd_i == 4'd5) ? 7'b0100100 :
(bcd_i == 4'd6) ? 7'b0100000 :
(bcd_i == 4'd7) ? 7'b0001111 :
(bcd_i == 4'd8) ? 7'b0000000 :
(bcd_i == 4'd9) ? 7'b0000100 :
7'bx;
endmodule | 1 |
5,221 | data/full_repos/permissive/113582216/Experiment/design/keyClick.v | 113,582,216 | keyClick.v | v | 49 | 83 | [] | [] | [] | [(21, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/113582216/Experiment/design/keyClick.v:40: Cannot find file containing module: 'keyPress'\n keyPress u1(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/keyPress\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/keyPress.v\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/keyPress.sv\n keyPress\n keyPress.v\n keyPress.sv\n obj_dir/keyPress\n obj_dir/keyPress.v\n obj_dir/keyPress.sv\n%Error: Exiting due to 1 error(s)\n" | 5,644 | module | module keyClick(
input key_i,
output clicked_o,
input clk_i
);
wire pressed;
reg current, post;
always@(posedge clk_i)
begin
current <= pressed;
end
always@(posedge clk_i)
begin
post <= current;
end
keyPress u1(
.key_i (key_i),
.pressed_o (pressed),
.clk_i (clk_i)
);
assign clicked_o = (post == 0) && (current == 1);
endmodule | module keyClick(
input key_i,
output clicked_o,
input clk_i
); |
wire pressed;
reg current, post;
always@(posedge clk_i)
begin
current <= pressed;
end
always@(posedge clk_i)
begin
post <= current;
end
keyPress u1(
.key_i (key_i),
.pressed_o (pressed),
.clk_i (clk_i)
);
assign clicked_o = (post == 0) && (current == 1);
endmodule | 1 |
5,222 | data/full_repos/permissive/113582216/Experiment/design/keyPress.v | 113,582,216 | keyPress.v | v | 52 | 83 | [] | [] | [] | [(21, 51)] | null | data/verilator_xmls/16ec990a-8b84-4ef9-b01e-f035ebdabf0c.xml | null | 5,645 | module | module keyPress(
input key_i,
output pressed_o,
input clk_i
);
parameter DURATION = 10;
reg [3:0] cnt;
initial
begin
cnt <= 0;
end
always@(posedge clk_i)
begin
if(key_i == 1)
begin
if(cnt < DURATION)
cnt <= cnt + 1;
else
cnt <= DURATION;
end
else
cnt <= 0;
end
assign pressed_o = (cnt == DURATION);
endmodule | module keyPress(
input key_i,
output pressed_o,
input clk_i
); |
parameter DURATION = 10;
reg [3:0] cnt;
initial
begin
cnt <= 0;
end
always@(posedge clk_i)
begin
if(key_i == 1)
begin
if(cnt < DURATION)
cnt <= cnt + 1;
else
cnt <= DURATION;
end
else
cnt <= 0;
end
assign pressed_o = (cnt == DURATION);
endmodule | 1 |
5,223 | data/full_repos/permissive/113582216/Experiment/design/main.v | 113,582,216 | main.v | v | 88 | 83 | [] | [] | [] | [(21, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:42: Cannot find file containing module: 'clkGen'\n clkGen u1(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen.v\n data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen.sv\n clkGen\n clkGen.v\n clkGen.sv\n obj_dir/clkGen\n obj_dir/clkGen.v\n obj_dir/clkGen.sv\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:47: Cannot find file containing module: 'controller'\n controller u2(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:57: Cannot find file containing module: 'digitDisplay'\n digitDisplay u3(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:75: Cannot find file containing module: 'keyPress'\n keyPress u4(\n ^~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:81: Cannot find file containing module: 'keyClick'\n keyClick u5(\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 5,646 | module | module main(
input clk,
input [1:0] btn,
output [3:0] an,
output ca,
output cb,
output cc,
output cd,
output ce,
output cf,
output cg,
output dp
);
wire clk5ms;
wire rst, toggle;
wire [3:0] dsec;
wire [3:0] sec0;
wire [3:0] sec1;
wire [3:0] min;
clkGen u1(
.clk50MHz_i (clk),
.clk5ms_o (clk5ms)
);
controller u2(
.rst_i (rst),
.toggle_i (toggle),
.clk_i (clk5ms),
.dsec_o (dsec),
.sec0_o (sec0),
.sec1_o (sec1),
.min_o (min)
);
digitDisplay u3(
.bcd_i0 (dsec),
.bcd_i1 (sec0),
.bcd_i2 (sec1),
.bcd_i3 (min),
.dp_i (4'b0101),
.clk_i (clk5ms),
.sel_o (an),
.a_o (ca),
.b_o (cb),
.c_o (cc),
.d_o (cd),
.e_o (ce),
.f_o (cf),
.g_o (cg),
.dp_o (dp)
);
keyPress u4(
.key_i (btn[1]),
.pressed_o (rst),
.clk_i (clk5ms)
);
keyClick u5(
.key_i (btn[0]),
.clicked_o (toggle),
.clk_i (clk5ms)
);
endmodule | module main(
input clk,
input [1:0] btn,
output [3:0] an,
output ca,
output cb,
output cc,
output cd,
output ce,
output cf,
output cg,
output dp
); |
wire clk5ms;
wire rst, toggle;
wire [3:0] dsec;
wire [3:0] sec0;
wire [3:0] sec1;
wire [3:0] min;
clkGen u1(
.clk50MHz_i (clk),
.clk5ms_o (clk5ms)
);
controller u2(
.rst_i (rst),
.toggle_i (toggle),
.clk_i (clk5ms),
.dsec_o (dsec),
.sec0_o (sec0),
.sec1_o (sec1),
.min_o (min)
);
digitDisplay u3(
.bcd_i0 (dsec),
.bcd_i1 (sec0),
.bcd_i2 (sec1),
.bcd_i3 (min),
.dp_i (4'b0101),
.clk_i (clk5ms),
.sel_o (an),
.a_o (ca),
.b_o (cb),
.c_o (cc),
.d_o (cd),
.e_o (ce),
.f_o (cf),
.g_o (cg),
.dp_o (dp)
);
keyPress u4(
.key_i (btn[1]),
.pressed_o (rst),
.clk_i (clk5ms)
);
keyClick u5(
.key_i (btn[0]),
.clicked_o (toggle),
.clk_i (clk5ms)
);
endmodule | 1 |
5,224 | data/full_repos/permissive/113582216/Experiment/FPGA1/checkOddEven/checkOddEven.v | 113,582,216 | checkOddEven.v | v | 12 | 44 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/4f8891d5-321f-450a-b809-f6b8dd9d3629.xml | null | 5,647 | module | module checkOddEven(
input [7:0] in,
output odd,
output even
);
assign odd = in[0] ^ in[1] ^ in[2] ^ in[3]
^ in[4] ^ in[5] ^ in[6] ^ in[7];
assign even = ~odd;
endmodule | module checkOddEven(
input [7:0] in,
output odd,
output even
); |
assign odd = in[0] ^ in[1] ^ in[2] ^ in[3]
^ in[4] ^ in[5] ^ in[6] ^ in[7];
assign even = ~odd;
endmodule | 1 |
5,225 | data/full_repos/permissive/113582216/Experiment/FPGA1/vFullAdd/vFullAdd.v | 113,582,216 | vFullAdd.v | v | 12 | 28 | [] | [] | [] | [(1, 11)] | null | data/verilator_xmls/c010f426-f35d-4c40-905a-4265d3039199.xml | null | 5,648 | module | module vFullAdd(
input a,
input b,
input c0,
output s,
output c
);
assign {c,s} = a + b + c0;
endmodule | module vFullAdd(
input a,
input b,
input c0,
output s,
output c
); |
assign {c,s} = a + b + c0;
endmodule | 1 |
5,229 | data/full_repos/permissive/113582216/Homework/decoder38.v | 113,582,216 | decoder38.v | v | 41 | 83 | [] | [] | [] | [(23, 40)] | null | data/verilator_xmls/a9836816-00a2-4e7b-b746-5efcfb1f77fb.xml | null | 5,652 | module | module decoder38(
input [2:0] in,
output [7:0] out,
input en
);
assign out = (en == 0) ? 8'b0:
(in == 3'b000) ? 8'b0000_0001 :
(in == 3'b001) ? 8'b0000_0010 :
(in == 3'b010) ? 8'b0000_0100 :
(in == 3'b011) ? 8'b0000_1000 :
(in == 3'b100) ? 8'b0001_0000 :
(in == 3'b101) ? 8'b0010_0000 :
(in == 3'b110) ? 8'b0100_0000 :
(in == 3'b111) ? 8'b1000_0000 :
8'bx;
endmodule | module decoder38(
input [2:0] in,
output [7:0] out,
input en
); |
assign out = (en == 0) ? 8'b0:
(in == 3'b000) ? 8'b0000_0001 :
(in == 3'b001) ? 8'b0000_0010 :
(in == 3'b010) ? 8'b0000_0100 :
(in == 3'b011) ? 8'b0000_1000 :
(in == 3'b100) ? 8'b0001_0000 :
(in == 3'b101) ? 8'b0010_0000 :
(in == 3'b110) ? 8'b0100_0000 :
(in == 3'b111) ? 8'b1000_0000 :
8'bx;
endmodule | 1 |
5,232 | data/full_repos/permissive/113582216/Homework/timer.v | 113,582,216 | timer.v | v | 68 | 83 | [] | [] | [] | [(23, 67)] | null | data/verilator_xmls/542711e8-5b05-4250-a1f2-50b51d6944e8.xml | null | 5,655 | module | module timer(
input clk,
input reset,
output [3:0] bcdout
);
reg [25:0] count;
reg [3:0] out;
initial
begin
count = 26'b0;
out = 4'd9;
end
always @ (negedge clk)
begin
if (reset)
begin
count <= 26'b0;
end
else
begin
count <= count + 1;
end
end
always @ (negedge clk)
begin
if (reset)
out <= 4'd9;
else
begin
if(count==(~26'b0))
begin
if (out==4'd0)
out <= 4'd9;
else
out <= out - 1;
end
end
end
assign bcdout = out;
endmodule | module timer(
input clk,
input reset,
output [3:0] bcdout
); |
reg [25:0] count;
reg [3:0] out;
initial
begin
count = 26'b0;
out = 4'd9;
end
always @ (negedge clk)
begin
if (reset)
begin
count <= 26'b0;
end
else
begin
count <= count + 1;
end
end
always @ (negedge clk)
begin
if (reset)
out <= 4'd9;
else
begin
if(count==(~26'b0))
begin
if (out==4'd0)
out <= 4'd9;
else
out <= out - 1;
end
end
end
assign bcdout = out;
endmodule | 1 |
5,233 | data/full_repos/permissive/113654920/hdl/CheckDNA.v | 113,654,920 | CheckDNA.v | v | 369 | 139 | [] | [] | [] | [(21, 368)] | null | null | 1: b'%Error: data/full_repos/permissive/113654920/hdl/CheckDNA.v:94: Cannot find file containing module: \'multi_16\'\nmulti_16 inst_multi_16 (\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/multi_16\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/multi_16.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/multi_16.sv\n multi_16\n multi_16.v\n multi_16.sv\n obj_dir/multi_16\n obj_dir/multi_16.v\n obj_dir/multi_16.sv\n%Warning-WIDTH: data/full_repos/permissive/113654920/hdl/CheckDNA.v:119: Operator XOR expects 17 bits on the LHS, but LHS\'s SEL generates 16 bits.\n : ... In instance CheckDNA\nassign mb[15:0] = ROM_Data[15:0] ^ dna[20:4]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113654920/hdl/CheckDNA.v:119: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s XOR generates 17 bits.\n : ... In instance CheckDNA\nassign mb[15:0] = ROM_Data[15:0] ^ dna[20:4]; \n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 5,656 | module | module CheckDNA(
input clk4,
input reset,
input [63:0] DNA_64,
input dna_valid,
input [15:0] ROM_Data,
input IDE_CS,
output reg DNA_ENA,
output reg DNA_REG,
output reg [9:0] DNA_Addr,
output dna_pass,
output [3:0] KILL
);
parameter no_of_ran_no = 1016;
reg [15:0] xor_check;
reg [63:0] dna;
reg [9:0] L_Addr;
reg [15:0] check;
reg multi_ce;
reg [4:0] dna_gen_st;
reg [3:0] DNA_FailR;
parameter DcIdle = 5'b00000;
parameter Dc01 = 5'b00001;
parameter Dc02 = 5'b00010;
parameter Dc03 = 5'b00011;
parameter Dc04 = 5'b00100;
parameter Dc10 = 5'b00101;
parameter Dc11 = 5'b00110;
parameter Dc12 = 5'b00111;
parameter Dc13 = 5'b01000;
parameter Dc14 = 5'b01001;
parameter Dc20 = 5'b01010;
parameter Dc21 = 5'b01011;
parameter Dc22 = 5'b01100;
parameter Dc23 = 5'b01101;
parameter Dc24 = 5'b01110;
parameter Dc25 = 5'b01111;
parameter Dc26 = 5'b10000;
parameter Dc27 = 5'b10001;
parameter Dc28 = 5'b10010;
parameter Dc29 = 5'b10011;
parameter Dc30 = 5'b10100;
parameter Dc31 = 5'b10101;
parameter Dc32 = 5'b10110;
parameter Dc33 = 5'b10111;
parameter Dc34 = 5'b11000;
parameter Dc35 = 5'b11001;
parameter Dc90 = 5'b11010;
parameter Dc91 = 5'b11011;
parameter Dc92 = 5'b11100;
reg [15:0] multi_a;
reg [15:0] multi_b;
reg [15:0] Simp_XOR;
reg FinishCheck;
wire [15:0] multi_p;
wire [15:0] ma;
wire [15:0] mb;
wire K_WINDOW;
multi_16 inst_multi_16 (
.ce(multi_ce),
.clk(clk4),
.a(multi_a),
.b(multi_b),
.p(multi_p));
assign ma[15:10] = multi_p[15:10] ^ dna[47:42];
assign ma[9:8] = multi_p[7:6] ^ dna[37:36];
assign ma[7:6] = multi_p[9:8] ^ dna[33:32];
assign ma[5:0] = multi_p[5:0] ^ dna[30:25];
assign mb[15:0] = ROM_Data[15:0] ^ dna[20:4];
assign KILL[0] = DNA_FailR[0];
assign KILL[1] = ~DNA_FailR[0] & DNA_FailR[1] & K_WINDOW & Simp_XOR[2];
assign KILL[2] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[2] & K_WINDOW & ~Simp_XOR[2];
assign KILL[3] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[3] & K_WINDOW & Simp_XOR[2];
assign K_WINDOW = Simp_XOR[9] & Simp_XOR[8] & ~Simp_XOR[7] & Simp_XOR[6] & ~Simp_XOR[5] & ~Simp_XOR[3];
assign dna_pass = FinishCheck & ~DNA_FailR[3] & ~DNA_FailR[2] & ~DNA_FailR[1] & ~DNA_FailR[0];
always @(posedge clk4) begin
if(reset) begin
DNA_Addr <= 10'b00_0000_0000;
L_Addr <= 10'b00_0000_0000;
xor_check <= 16'b0000_0000_0000_0000;
multi_a <= 16'b0000_0000_0000_0000;
multi_b <= 16'b0000_0000_0000_0000;
Simp_XOR <= 16'b0000_0000_0000_0000;
DNA_FailR <= 4'b0000;
FinishCheck <= 1'b0;
DNA_ENA <= 1'b0;
DNA_REG <= 1'b0;
multi_ce <= 1'b0;
dna_gen_st <= DcIdle;
end else begin
case(dna_gen_st)
DcIdle : begin
if(dna_valid == 1'b1) begin
dna_gen_st <= Dc01;
end
end
Dc01 : begin
DNA_ENA <= 1'b1;
multi_ce <= 1'b1;
dna <= DNA_64;
dna_gen_st <= Dc02;
end
Dc02 : begin
DNA_ENA <= 1'b0;
DNA_REG <= 1'b1;
dna_gen_st <= Dc03;
end
Dc03 : begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc04;
end
Dc04 : begin
multi_ce <= 1'b0;
multi_a[15:0] <= ma[15:0];
multi_b[15:0] <= mb[15:0];
L_Addr[9] <= ~mb[10];
L_Addr[8:0] <= mb[10:2];
dna_gen_st <= Dc10;
end
Dc10: begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc11;
end
Dc11: begin
multi_ce <= 1'b1;
multi_a[15:0] <= ma[15:0];
multi_b[15:0] <= mb[15:0];
dna_gen_st <= Dc12;
end
Dc12: begin
dna[63:1] <= dna[62:0];
dna[0] <= dna[63] ^ ROM_Data[1];
DNA_ENA <= 1'b0;
if (DNA_Addr == L_Addr) check <= multi_a;
DNA_Addr <= DNA_Addr + 1;
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
xor_check <= xor_check ^ multi_b;
dna_gen_st <= Dc13;
end
Dc13: begin
DNA_ENA <= 1'b1;
dna_gen_st <= Dc14;
end
Dc14: begin
DNA_ENA <= 1'b0;
DNA_REG <= 1'b1;
if (DNA_Addr == no_of_ran_no) begin
DNA_Addr <= DNA_Addr + 1;
dna_gen_st <= Dc20;
end else begin
dna_gen_st <= Dc10;
end
end
Dc20 : begin
multi_ce <= 1'b0;
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc21;
end
Dc21 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (multi_a != ROM_Data) begin
DNA_FailR[3] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc22;
end
Dc22 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc23;
end
Dc23 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (xor_check != ROM_Data) begin
DNA_FailR[2] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc24;
end
Dc24 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc25;
end
Dc25 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (check != ROM_Data) begin
DNA_FailR[1] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc26;
end
Dc26 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc27;
end
Dc27 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[63:48] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc28;
end
Dc28 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc29;
end
Dc29 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[47:32] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc30;
end
Dc30 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc31;
end
Dc31 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[31:16] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc32;
end
Dc32 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc33;
end
Dc33 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[15:0] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
dna_gen_st <= Dc34;
end
Dc34 : begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc35;
end
Dc35 : begin
if (Simp_XOR[15:0] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
FinishCheck <= 1'b1;
dna_gen_st <= Dc90;
end
Dc90: begin
if (IDE_CS == 1'b0) begin
dna_gen_st <= Dc91;
end else begin
dna_gen_st <= Dc90;
end
end
Dc91: begin
Simp_XOR <= Simp_XOR + 1;
dna_gen_st <= Dc92;
end
Dc92: begin
if (IDE_CS == 1'b1) begin
dna_gen_st <= Dc90;
end else begin
dna_gen_st <= Dc92;
end
end
default : begin
dna_gen_st <= DcIdle;
end
endcase
end
end
endmodule | module CheckDNA(
input clk4,
input reset,
input [63:0] DNA_64,
input dna_valid,
input [15:0] ROM_Data,
input IDE_CS,
output reg DNA_ENA,
output reg DNA_REG,
output reg [9:0] DNA_Addr,
output dna_pass,
output [3:0] KILL
); |
parameter no_of_ran_no = 1016;
reg [15:0] xor_check;
reg [63:0] dna;
reg [9:0] L_Addr;
reg [15:0] check;
reg multi_ce;
reg [4:0] dna_gen_st;
reg [3:0] DNA_FailR;
parameter DcIdle = 5'b00000;
parameter Dc01 = 5'b00001;
parameter Dc02 = 5'b00010;
parameter Dc03 = 5'b00011;
parameter Dc04 = 5'b00100;
parameter Dc10 = 5'b00101;
parameter Dc11 = 5'b00110;
parameter Dc12 = 5'b00111;
parameter Dc13 = 5'b01000;
parameter Dc14 = 5'b01001;
parameter Dc20 = 5'b01010;
parameter Dc21 = 5'b01011;
parameter Dc22 = 5'b01100;
parameter Dc23 = 5'b01101;
parameter Dc24 = 5'b01110;
parameter Dc25 = 5'b01111;
parameter Dc26 = 5'b10000;
parameter Dc27 = 5'b10001;
parameter Dc28 = 5'b10010;
parameter Dc29 = 5'b10011;
parameter Dc30 = 5'b10100;
parameter Dc31 = 5'b10101;
parameter Dc32 = 5'b10110;
parameter Dc33 = 5'b10111;
parameter Dc34 = 5'b11000;
parameter Dc35 = 5'b11001;
parameter Dc90 = 5'b11010;
parameter Dc91 = 5'b11011;
parameter Dc92 = 5'b11100;
reg [15:0] multi_a;
reg [15:0] multi_b;
reg [15:0] Simp_XOR;
reg FinishCheck;
wire [15:0] multi_p;
wire [15:0] ma;
wire [15:0] mb;
wire K_WINDOW;
multi_16 inst_multi_16 (
.ce(multi_ce),
.clk(clk4),
.a(multi_a),
.b(multi_b),
.p(multi_p));
assign ma[15:10] = multi_p[15:10] ^ dna[47:42];
assign ma[9:8] = multi_p[7:6] ^ dna[37:36];
assign ma[7:6] = multi_p[9:8] ^ dna[33:32];
assign ma[5:0] = multi_p[5:0] ^ dna[30:25];
assign mb[15:0] = ROM_Data[15:0] ^ dna[20:4];
assign KILL[0] = DNA_FailR[0];
assign KILL[1] = ~DNA_FailR[0] & DNA_FailR[1] & K_WINDOW & Simp_XOR[2];
assign KILL[2] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[2] & K_WINDOW & ~Simp_XOR[2];
assign KILL[3] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[3] & K_WINDOW & Simp_XOR[2];
assign K_WINDOW = Simp_XOR[9] & Simp_XOR[8] & ~Simp_XOR[7] & Simp_XOR[6] & ~Simp_XOR[5] & ~Simp_XOR[3];
assign dna_pass = FinishCheck & ~DNA_FailR[3] & ~DNA_FailR[2] & ~DNA_FailR[1] & ~DNA_FailR[0];
always @(posedge clk4) begin
if(reset) begin
DNA_Addr <= 10'b00_0000_0000;
L_Addr <= 10'b00_0000_0000;
xor_check <= 16'b0000_0000_0000_0000;
multi_a <= 16'b0000_0000_0000_0000;
multi_b <= 16'b0000_0000_0000_0000;
Simp_XOR <= 16'b0000_0000_0000_0000;
DNA_FailR <= 4'b0000;
FinishCheck <= 1'b0;
DNA_ENA <= 1'b0;
DNA_REG <= 1'b0;
multi_ce <= 1'b0;
dna_gen_st <= DcIdle;
end else begin
case(dna_gen_st)
DcIdle : begin
if(dna_valid == 1'b1) begin
dna_gen_st <= Dc01;
end
end
Dc01 : begin
DNA_ENA <= 1'b1;
multi_ce <= 1'b1;
dna <= DNA_64;
dna_gen_st <= Dc02;
end
Dc02 : begin
DNA_ENA <= 1'b0;
DNA_REG <= 1'b1;
dna_gen_st <= Dc03;
end
Dc03 : begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc04;
end
Dc04 : begin
multi_ce <= 1'b0;
multi_a[15:0] <= ma[15:0];
multi_b[15:0] <= mb[15:0];
L_Addr[9] <= ~mb[10];
L_Addr[8:0] <= mb[10:2];
dna_gen_st <= Dc10;
end
Dc10: begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc11;
end
Dc11: begin
multi_ce <= 1'b1;
multi_a[15:0] <= ma[15:0];
multi_b[15:0] <= mb[15:0];
dna_gen_st <= Dc12;
end
Dc12: begin
dna[63:1] <= dna[62:0];
dna[0] <= dna[63] ^ ROM_Data[1];
DNA_ENA <= 1'b0;
if (DNA_Addr == L_Addr) check <= multi_a;
DNA_Addr <= DNA_Addr + 1;
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
xor_check <= xor_check ^ multi_b;
dna_gen_st <= Dc13;
end
Dc13: begin
DNA_ENA <= 1'b1;
dna_gen_st <= Dc14;
end
Dc14: begin
DNA_ENA <= 1'b0;
DNA_REG <= 1'b1;
if (DNA_Addr == no_of_ran_no) begin
DNA_Addr <= DNA_Addr + 1;
dna_gen_st <= Dc20;
end else begin
dna_gen_st <= Dc10;
end
end
Dc20 : begin
multi_ce <= 1'b0;
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc21;
end
Dc21 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (multi_a != ROM_Data) begin
DNA_FailR[3] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc22;
end
Dc22 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc23;
end
Dc23 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (xor_check != ROM_Data) begin
DNA_FailR[2] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc24;
end
Dc24 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc25;
end
Dc25 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (check != ROM_Data) begin
DNA_FailR[1] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc26;
end
Dc26 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc27;
end
Dc27 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[63:48] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc28;
end
Dc28 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc29;
end
Dc29 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[47:32] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc30;
end
Dc30 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc31;
end
Dc31 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[31:16] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
DNA_Addr <= DNA_Addr+1;
dna_gen_st <= Dc32;
end
Dc32 : begin
DNA_REG <= 1'b0;
DNA_ENA <= 1'b1;
dna_gen_st <= Dc33;
end
Dc33 : begin
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0];
if (DNA_64[15:0] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
DNA_REG <= 1'b1;
DNA_ENA <= 1'b0;
dna_gen_st <= Dc34;
end
Dc34 : begin
DNA_REG <= 1'b0;
dna_gen_st <= Dc35;
end
Dc35 : begin
if (Simp_XOR[15:0] != ROM_Data[15:0]) begin
DNA_FailR[0] <= 1'b1;
end
FinishCheck <= 1'b1;
dna_gen_st <= Dc90;
end
Dc90: begin
if (IDE_CS == 1'b0) begin
dna_gen_st <= Dc91;
end else begin
dna_gen_st <= Dc90;
end
end
Dc91: begin
Simp_XOR <= Simp_XOR + 1;
dna_gen_st <= Dc92;
end
Dc92: begin
if (IDE_CS == 1'b1) begin
dna_gen_st <= Dc90;
end else begin
dna_gen_st <= Dc92;
end
end
default : begin
dna_gen_st <= DcIdle;
end
endcase
end
end
endmodule | 0 |
5,234 | data/full_repos/permissive/113654920/hdl/chip.v | 113,654,920 | chip.v | v | 758 | 141 | [] | [] | [] | [(23, 757)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/113654920/hdl/chip.v:661: Signal definition not found, creating implicitly: \'IDE_DSTB\'\n : ... Suggested alternative: \'IDE_CS\'\n if (IDE_DSTB == 1\'b1) DIn2 <= DIn1;\n ^~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:206: Cannot find file containing module: \'dcm3\'\ndcm3 Inst_DCM(\n^~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3.sv\n dcm3\n dcm3.v\n dcm3.sv\n obj_dir/dcm3\n obj_dir/dcm3.v\n obj_dir/dcm3.sv\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:216: Cannot find file containing module: \'TF_Stub\'\nTF_Stub Inst_TF_Stub(\n^~~~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:230: Cannot find file containing module: \'Top\'\nTop dna1 (\n^~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:239: Cannot find file containing module: \'Reg38\'\nReg38 R_38(\n^~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:252: Cannot find file containing module: \'PS2_DMA\'\nPS2_DMA PS2DMA(\n^~~~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:276: Cannot find file containing module: \'D_RAM\'\nD_RAM DMARAM(\n^~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:318: Cannot find file containing module: \'IDE_DMA\'\nIDE_DMA IDEDMA (\n^~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 5,657 | module | module chip(
inout [15:0] iD ,
output [2:0] iA,
output ibCS0 ,
output ibCS1 ,
output ibRST ,
input iIRQ ,
output ibWr ,
output ibRd ,
input iDQ ,
output ibDK ,
input iRdy ,
input ibDASP ,
input CLKin ,
input bCSRST ,
input bCRST ,
inout [15:0] cDP ,
inout [15:0] cAP ,
input bcCS ,
input bcWr ,
input bcRd ,
input bCRT ,
output bcWait ,
output bcIRQ ,
output cDQ ,
input cDK ,
output DR245 ,
output OE245 ,
input ACS_LED ,
input HDD_ACK ,
inout TFD0 ,
inout TFD1 ,
inout TFD2 ,
inout TFD3 ,
output TFCLK ,
input TFSENSE ,
output TFCMD ,
output JT_Result ,
output JT_Pin1 ,
input JT_bTest
);
wire DCM_RST,CLK1,CLK4,DCM_LOCKED ;
reg DWrite;
wire IDERd,IDEWr;
reg iIRQ1;
reg iDQ1,SiIRQ,SiDQ;
wire iDMARd,iDMAWr ;
wire BufEmpty ;
wire PA_HvSpace,PA_OD_Rdy ;
wire PB_HvSpace,PB_OD_Rdy ;
wire WithinBBlock,BBurstEnd;
wire WithinABlock;
wire iCS0,iCS1,cWr,cRd,iWr,iRd,iDK ;
wire [15:0] RegData;
wire [31:0] DMARAMQ;
reg [31:0] DMARAMD;
reg [15:0] DIn1,DIn2;
wire cDMA_OE ;
wire cRdt;
wire RegEB;
wire [7:0] Reg0038 ;
wire [15:0] Reg0028 ;
reg [7:0] Reg002A;
wire [7:0] Reg002E;
reg [7:0] Reg0064;
wire cDOE,cAOE ;
wire IDE_CS;
reg DMA_ARM,DMARMC,PS2WrIDE ;
wire PA_AlmostFull ;
wire [3:0] BufSize;
reg [2:0] R44;
wire INT9,INT9OE,DMA_IrqCond;
reg DMA_IrqMask, DMA_IrqFF;
wire DMA_IrqCTRL ;
wire bHardReset;
reg ATV1,ATV2,ATV;
wire UDMAC,CmdIsEF,UDMA_SEL,MDMA_SEL,D_UnChg ;
reg R42Is03,R44Is2X,R44Is4X;
wire [2:0] UDMA,MDMA;
reg [2:0] UDO;
reg [2:1] MDO;
wire Combo_CS,Combo_OE ;
reg cWr1,cRd1,ScWr,ScRd,ScWr1,ScRd1 ;
wire [15:0] cAi,cDi,CRC_Q,iDi,iDO,DOutA;
wire iDOEnb,CRC_MUX ;
wire IDEiOE,iDMA_OE ;
reg [6:0] cRgA;
reg [7:0] cRgD;
wire cRgRd2E,cRgWr;
reg bcRd2E;
reg cRgWrEnb ;
reg [5:0] Rd2ECnt;
reg [3:0] cWaitCnt;
reg cWait;
wire iD_245_In,IDE_Rd_Env ;
reg SiRdy2,SiRdy1;
reg IgnoreIRdyPin;
reg Ph0,Ph1,Ph2,Phase3;
wire Reg002E_0, Reg002E_1, Reg002E_2, Reg002E_3, Reg002E_5, Reg002E_6, Reg002E_7;
reg Reg002E_4;
assign Reg002E = {Reg002E_7, Reg002E_6, Reg002E_5, Reg002E_4, Reg002E_3, Reg002E_2, Reg002E_1, Reg002E_0};
wire DNA_Pass,DNA_RST;
wire [3:0] KILL;
dcm3 Inst_DCM(
.CLKIN_IN (CLKin),
.RST_IN (DCM_RST),
.CLKFX_OUT (CLK4),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT (CLK1),
.LOCKED_OUT (DCM_LOCKED)
);
TF_Stub Inst_TF_Stub(
.RESET (DNA_RST),
.CLK4 (CLK4),
.TFD0 (TFD0),
.TFD1 (TFD1),
.TFD2 (TFD2),
.TFD3 (TFD3),
.TF_CLK (TFCLK),
.TF_CMD (TFCMD),
.TF_SENSE (TFSENSE)
);
Top dna1 (
.reset(DNA_RST),
.clk4(CLK4),
.IDE_CS(IDE_CS),
.dna_pass(DNA_Pass),
.KILL(KILL)
);
Reg38 R_38(
.UDMAC (UDMAC),
.PS2WrIDE (PS2WrIDE),
.iIRQ (SiIRQ),
.cDQ (cDQ),
.iDQ (SiDQ),
.iDK (iDK),
.BufEmpty (BufEmpty),
.PB_HvSpace (PB_HvSpace),
.BufSize (BufSize),
.DOut (Reg0038)
);
PS2_DMA PS2DMA(
.CLK4 (CLK4),
.Phase3 (Phase3),
.cDQ (cDQ),
.cDK (cDK),
.cRd (cRd),
.DWrite (DWrite),
.DMA_ARM (DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.PB_HvSpace (PB_HvSpace),
.PB_OD_Rdy (PB_OD_Rdy),
.WithinBBlock (WithinBBlock),
.BBurstEnd (BBurstEnd),
.IncAddrB (IncAddrB),
.RegEB (RegEB),
.EnbB (EnbB),
.WrB (WrB )
);
D_RAM DMARAM(
.CLK4 (CLK4),
.DMA_ARM (DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.CRC_Q (CRC_Q),
.PA_HvSpace (PA_HvSpace),
.PA_OD_Rdy (PA_OD_Rdy),
.PA_AlmostFull (PA_AlmostFull),
.PA_Full (PA_Full),
.PA_Empty (PA_Empty),
.WithinABlock (WithinABlock),
.PB_HvSpace (PB_HvSpace),
.PB_OD_Rdy (PB_OD_Rdy),
.BufSize (BufSize),
.BufEmpty (BufEmpty),
.DInA (DIn2),
.DOutA (DOutA),
.DInB (DMARAMD),
.A0 (A0),
.HWOE (HWOE),
.IncAddrA (IncAddrA),
.EnbA (EnbA),
.WrA (WrA),
.RegEA (RegEA),
.WithinBBlock (WithinBBlock),
.BBurstEnd (BBurstEnd),
.IncAddrB (IncAddrB),
.EnbB (EnbB),
.RegEB (RegEB),
.WrB (WrB),
.DOutB (DMARAMQ)
);
IDE_DMA IDEDMA (
.CLK4 (CLK4),
.Phase3 (Phase3),
.iDK (iDK),
.iDQ (SiDQ),
.SiRdy1 (SiRdy1),
.SiRdy2 (SiRdy2),
.DMA_ARM(DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.UDMA (UDMA),
.MDMA (MDMA),
.iDMARd (iDMARd),
.iDMAWr (iDMAWr),
.iDMA_OE (iDMA_OE),
.iD_245_In (iD_245_In),
.CRC_MUX (CRC_MUX),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.PA_HvSpace (PA_HvSpace),
.PA_OD_Rdy (PA_OD_Rdy),
.WithinABlock (WithinABlock),
.PA_AlmostFull(PA_AlmostFull),
.PA_Full (PA_Full),
.PA_Empty (PA_Empty),
.IDE_DSTB (IDE_DSTB),
.IncAddrA (IncAddrA),
.A0 (A0),
.HWOE (HWOE),
.EnbA (EnbA),
.WrA (WrA),
.RegEA (RegEA)
);
assign JT_Result = (JT_bTest == 1'b0) ? ( ~DNA_Pass ) : ( HDD_ACK | ACS_LED | ibDASP | bCRT );
assign JT_Pin1 = TFCLK;
assign DCM_RST = ~bCRST | ~bCSRST;
assign bHardReset = bCRST & DCM_LOCKED;
assign DNA_RST = ~DCM_LOCKED;
always @(negedge CLK1) begin
if (DCM_LOCKED == 1'b0) begin
Ph0 <= 1'b0;
end else begin
Ph0 <= ~Ph0;
end
end
always @(negedge CLK4) begin
Ph1 <= Ph0;
Ph2 <= Ph1;
end
always @(posedge CLK4) begin
Phase3 <= Ph1 ^ Ph2;
end
assign ibRST = ~(Reg0064[7]);
assign ibCS0 = ~(iCS0);
assign ibCS1 = ~(iCS1);
assign ibRd = ~(iRd);
assign ibWr = ~(iWr);
assign ibDK = ~(iDK);
assign iRd = ( IDERd & ~iDK ) | (iDMARd & iDK);
assign iWr = ( IDEWr & ~iDK ) | (iDMAWr & iDK);
assign cRd = ~bcRd & ~KILL[0];
assign cRdt = ~bCRT & ~KILL[0];
assign cWr = ~bcWr & ~KILL[0];
assign INT9OE = Reg002A[1] | Reg002A[0];
assign bcIRQ = (INT9OE == 1'b1) ? ~(INT9) : 1'bZ;
assign INT9 = (SiIRQ & Reg002A[0]) | (DMA_IrqFF & DMA_IrqCTRL);
assign cDMA_OE = cRdt & cDK;
assign cDOE = ATV & (cDMA_OE | Combo_OE);
assign cDP = (cDOE == 1'b0) ? {16{1'bZ}} :
(cDK == 1'b1) ? DMARAMQ[15:0] :
(IDE_CS == 1'b1) ? iDi[15:0] : RegData[15:0];
assign cDi = cDP;
assign cAOE = ATV & cDMA_OE;
assign cAP = (cAOE == 1'b0) ? {16{1'bZ}} : DMARAMQ[31:16];
assign cAi = cAP;
assign Combo_CS = ATV & ~cDK & ~(bcCS | cAi[15] | cAi[14] | cAi[13] | cAi[12] |
cAi[11] | cAi[10] | cAi[9] | cAi[8] | cAi[7]);
assign Combo_OE = cRd & Combo_CS;
assign iD[15:0] = (iDOEnb == 1'b1) ? iDO[15:0] : {16{1'bZ}};
assign iDOEnb = IDEiOE | iDMA_OE;
assign iDi[15:0] = iD[15:0];
assign iDO[15:0] = (IDE_CS == 1'b1) ? cDi[15:0] :
(CRC_MUX == 1'b1) ? CRC_Q[15:0] : DOutA[15:0];
assign IDE_CS = Combo_CS & ~iDK & cAi[6] & ~cAi[5];
assign iCS1 = IDE_CS & cAi[4] & ~KILL[2];
assign iCS0 = IDE_CS & ~cAi[4] & ~KILL[2];
assign iA[2] = IDE_CS & cAi[3] & ~KILL[1];
assign iA[1] = IDE_CS & cAi[2] & ~KILL[2];
assign iA[0] = IDE_CS & cAi[1] & ~KILL[3];
assign IDERd = IDE_CS & cRd & ~KILL[1];
assign IDEWr = IDE_CS & cWr & ~KILL[2];
assign IDEiOE = IDE_CS & cWr;
assign IDE_Rd_Env = IDE_CS & cRd;
assign Reg0028[15] = BufSize[3];
assign Reg0028[14] = BufEmpty;
assign Reg0028[13:2] = 12'b0000_0000_0000;
assign Reg0028[1] = cDQ;
assign Reg0028[0] = SiIRQ;
assign RegData[15:8] = (cAi[6:0] == 7'h28) ? Reg0028[15:8] : 8'h00;
assign RegData[7:0] = (cAi[6:0] == 7'h02) ? 8'h13 :
(cAi[6:0] == 7'h04) ? 8'h0B :
(cAi[6:0] == 7'h0E) ? 8'h02 :
(cAi[6:0] == 7'h28) ? Reg0028[7:0] :
(cAi[6:0] == 7'h2A) ? Reg002A[7:0] :
(cAi[6:0] == 7'h2E) ? Reg002E[7:0] :
(cAi[6:0] == 7'h38) ? Reg0038[7:0] :
(cAi[6:0] == 7'h64) ? Reg0064[7:0] : 8'h00;
assign DMA_IrqCond = (~(PS2WrIDE) & PB_OD_Rdy) | (PS2WrIDE & PB_HvSpace);
assign DMA_IrqCTRL = Reg002A[1];
assign UDMAC = UDO[2] | UDO[1] | UDO[0];
assign CmdIsEF = cRgD[7] & cRgD[6] & cRgD[5] & ~(cRgD[4]) & cRgD[3] & cRgD[2] & cRgD[1] & cRgD[0];
assign UDMA_SEL = CmdIsEF & R44Is4X & R42Is03;
assign MDMA_SEL = CmdIsEF & R44Is2X & R42Is03;
assign D_UnChg = ~(UDMA_SEL | MDMA_SEL);
assign UDMA[2:0] = UDO[2:0];
assign MDMA[2] = MDO[2];
assign MDMA[1] = MDO[1];
assign MDMA[0] = ~(UDO[2] | UDO[1] | UDO[0] | MDO[2] | MDO[1]);
assign Reg002E_7 = 1'b1;
assign Reg002E_6 = 1'b1;
assign Reg002E_5 = 1'b0;
assign Reg002E_3 = 1'b1;
assign Reg002E_2 = 1'b1;
assign Reg002E_1 = 1'b1;
assign Reg002E_0 = 1'b0;
assign cRgWr = ATV & ScWr1 & ~(ScWr) & cRgWrEnb;
assign cRgRd2E = ATV & ScRd1 & ~(ScRd) & bcRd2E;
assign OE245 = ~(ATV);
assign DR245 = ~(IDE_Rd_Env | iD_245_In);
always @(posedge bcWr) begin
cRgWrEnb <= Combo_CS & ScWr & ScWr1;
cRgA[6:0] <= cAi[6:0];
cRgD[7:0] <= cDi[7:0];
end
always @(posedge bcRd) begin
bcRd2E <= Combo_CS & ScRd & ScRd1 & ~(cAi[6]) & cAi[5] & ~(cAi[4]) & cAi[3] & cAi[2] & cAi[1] & ~(cAi[0]);
end
always @(posedge CLK4) begin
if ((Ph1 ^ Ph2) == 1'b1) begin
DMARAMD[15:0] <= cDi[15:0];
DMARAMD[31:16] <= cAi[15:0];
end
end
always @(posedge CLK1) begin
DWrite <= cWr & cDK;
end
assign bcWait = (IDE_CS == 1'b1) ? ~cWait : 1'bZ;
always @(posedge CLK4) begin
if (IDE_CS == 1'b0) begin
cWaitCnt <= 4'b0000;
cWait <= 1'b1;
IgnoreIRdyPin <= ~SiRdy2;
end else begin
if (cWaitCnt == 4'b1010) begin
if ((IgnoreIRdyPin == 1'b1) || (SiRdy2 == 1'b1)) begin
cWait <= 1'b0;
end
end else begin
cWaitCnt <= cWaitCnt + 1;
end
end
end
always @(posedge CLK4) begin
if (bHardReset == 1'b0) begin
Reg002A <= 8'h00;
Reg002E_4 <= 1'b0;
Rd2ECnt <= 6'b000001;
Reg0064 <= 8'h80;
DMA_IrqMask <= 1'b0;
DMA_IrqFF <= 1'b0;
PS2WrIDE <= 1'b0;
MDO[2] <= 1'b0;
MDO[1] <= 1'b0;
UDO <= 3'b000;
DMARMC <= 1'b0;
DMA_ARM <= 1'b0;
iDQ1 <= 1'b0;
iIRQ1 <= 1'b0;
cWr1 <= 1'b0;
cRd1 <= 1'b0;
SiRdy1 <= 1'b1;
SiDQ <= 1'b0;
SiIRQ <= 1'b0;
ScWr <= 1'b0;
ScRd <= 1'b0;
SiRdy2 <= 1'b1;
ScRd1 <= 1'b0;
ScWr1 <= 1'b0;
ATV1 <= 1'b0;
ATV2 <= 1'b0;
ATV <= 1'b0;
end else begin
ATV1 <= 1'b1;
ATV2 <= ATV1;
ATV <= ATV2;
iDQ1 <= iDQ;
iIRQ1 <= iIRQ;
cWr1 <= cWr;
cRd1 <= cRd;
SiRdy1 <= iRdy;
DIn1 <= iDi;
SiDQ <= iDQ1;
SiIRQ <= iIRQ1;
ScWr <= cWr1;
ScRd <= cRd1;
SiRdy2 <= SiRdy1;
if (IDE_DSTB == 1'b1) DIn2 <= DIn1;
ScRd1 <= ScRd;
ScWr1 <= ScWr;
if (cRgRd2E == 1'b1) begin
if ((Rd2ECnt == 6'b000110) || (Rd2ECnt == 6'b010010) || (Rd2ECnt == 6'b010011) || (Rd2ECnt == 6'b010101) ||
(Rd2ECnt == 6'b010111) || (Rd2ECnt == 6'b011100) || (Rd2ECnt == 6'b011101) || (Rd2ECnt == 6'b011110) ||
(Rd2ECnt == 6'b011111) || (Rd2ECnt == 6'b100000) || (Rd2ECnt == 6'b100011) || (Rd2ECnt == 6'b100100) ||
(Rd2ECnt == 6'b100101) || (Rd2ECnt == 6'b100110) || (Rd2ECnt == 6'b100111) || (Rd2ECnt == 6'b101000) ||
(Rd2ECnt == 6'b101001) || (Rd2ECnt == 6'b101110) || (Rd2ECnt == 6'b110000) || (Rd2ECnt == 6'b110001) ||
(Rd2ECnt == 6'b110011) || (Rd2ECnt == 6'b110101) || (Rd2ECnt == 6'b110110) || (Rd2ECnt == 6'b111000) ||
(Rd2ECnt == 6'b111001) || (Rd2ECnt == 6'b111011) || (Rd2ECnt == 6'b111110))
begin
Reg002E_4 <= 1'b1;
end else begin
Reg002E_4 <= 1'b0;
end
Rd2ECnt <= Rd2ECnt + 1;
end
if (cRgWr == 1'b0) begin
DMARMC <= ATV;
DMA_ARM <= DMARMC;
if (DMA_IrqMask == 1'b1) begin
DMA_IrqMask <= DMA_IrqCond;
end
if ((DMA_IrqCond == 1'b1) && (DMA_IrqMask == 1'b0)) begin
DMA_IrqMask <= DMA_IrqCTRL;
DMA_IrqFF <= DMA_IrqCTRL;
end
end else begin
case (cRgA[6:0])
7'b0101010: begin
Reg002A[7:0] <= cRgD[7:0];
if (cRgD[7:0] == 8'h00) DMA_IrqFF <= 1'b0;
end
7'b0101100: begin
if (cRgD == 8'hE1) begin
Rd2ECnt <= 6'b00_0001;
end
end
7'b0110010: begin
DMARMC <= 1'b0;
DMA_ARM <= 1'b0;
DMA_IrqFF <= 1'b0;
Reg0064[2] <= 1'b0;
PS2WrIDE <= cRgD[0];
end
7'b1000010: begin
R42Is03 <= ~(cRgD[7] | cRgD[6] | cRgD[5] | cRgD[4] | cRgD[3] | cRgD[2]) & cRgD[1] & cRgD[0];
end
7'b1000100: begin
R44Is2X <= ~(cRgD[7] | cRgD[6] | cRgD[4] | cRgD[3]) & cRgD[5];
R44Is4X <= ~(cRgD[7] | cRgD[5] | cRgD[4] | cRgD[3]) & cRgD[6];
R44[2] <= cRgD[2];
R44[1] <= cRgD[1];
R44[0] <= cRgD[0];
end
7'b1001110: begin
UDO[2] <= (D_UnChg & UDO[2]) | (~(D_UnChg) & UDMA_SEL & R44[2]);
UDO[1] <= (D_UnChg & UDO[1]) | (~(D_UnChg) & UDMA_SEL & R44[1]);
UDO[0] <= (D_UnChg & UDO[0]) | (~(D_UnChg) & UDMA_SEL & R44[0]);
MDO[2] <= (D_UnChg & MDO[2]) | (~(D_UnChg) & MDMA_SEL & R44[2]);
MDO[1] <= (D_UnChg & MDO[1]) | (~(D_UnChg) & MDMA_SEL & R44[1]);
end
7'b1100100: begin
Reg0064[7:0] <= cRgD[7:0];
end
endcase
end
end
end
endmodule | module chip(
inout [15:0] iD ,
output [2:0] iA,
output ibCS0 ,
output ibCS1 ,
output ibRST ,
input iIRQ ,
output ibWr ,
output ibRd ,
input iDQ ,
output ibDK ,
input iRdy ,
input ibDASP ,
input CLKin ,
input bCSRST ,
input bCRST ,
inout [15:0] cDP ,
inout [15:0] cAP ,
input bcCS ,
input bcWr ,
input bcRd ,
input bCRT ,
output bcWait ,
output bcIRQ ,
output cDQ ,
input cDK ,
output DR245 ,
output OE245 ,
input ACS_LED ,
input HDD_ACK ,
inout TFD0 ,
inout TFD1 ,
inout TFD2 ,
inout TFD3 ,
output TFCLK ,
input TFSENSE ,
output TFCMD ,
output JT_Result ,
output JT_Pin1 ,
input JT_bTest
); |
wire DCM_RST,CLK1,CLK4,DCM_LOCKED ;
reg DWrite;
wire IDERd,IDEWr;
reg iIRQ1;
reg iDQ1,SiIRQ,SiDQ;
wire iDMARd,iDMAWr ;
wire BufEmpty ;
wire PA_HvSpace,PA_OD_Rdy ;
wire PB_HvSpace,PB_OD_Rdy ;
wire WithinBBlock,BBurstEnd;
wire WithinABlock;
wire iCS0,iCS1,cWr,cRd,iWr,iRd,iDK ;
wire [15:0] RegData;
wire [31:0] DMARAMQ;
reg [31:0] DMARAMD;
reg [15:0] DIn1,DIn2;
wire cDMA_OE ;
wire cRdt;
wire RegEB;
wire [7:0] Reg0038 ;
wire [15:0] Reg0028 ;
reg [7:0] Reg002A;
wire [7:0] Reg002E;
reg [7:0] Reg0064;
wire cDOE,cAOE ;
wire IDE_CS;
reg DMA_ARM,DMARMC,PS2WrIDE ;
wire PA_AlmostFull ;
wire [3:0] BufSize;
reg [2:0] R44;
wire INT9,INT9OE,DMA_IrqCond;
reg DMA_IrqMask, DMA_IrqFF;
wire DMA_IrqCTRL ;
wire bHardReset;
reg ATV1,ATV2,ATV;
wire UDMAC,CmdIsEF,UDMA_SEL,MDMA_SEL,D_UnChg ;
reg R42Is03,R44Is2X,R44Is4X;
wire [2:0] UDMA,MDMA;
reg [2:0] UDO;
reg [2:1] MDO;
wire Combo_CS,Combo_OE ;
reg cWr1,cRd1,ScWr,ScRd,ScWr1,ScRd1 ;
wire [15:0] cAi,cDi,CRC_Q,iDi,iDO,DOutA;
wire iDOEnb,CRC_MUX ;
wire IDEiOE,iDMA_OE ;
reg [6:0] cRgA;
reg [7:0] cRgD;
wire cRgRd2E,cRgWr;
reg bcRd2E;
reg cRgWrEnb ;
reg [5:0] Rd2ECnt;
reg [3:0] cWaitCnt;
reg cWait;
wire iD_245_In,IDE_Rd_Env ;
reg SiRdy2,SiRdy1;
reg IgnoreIRdyPin;
reg Ph0,Ph1,Ph2,Phase3;
wire Reg002E_0, Reg002E_1, Reg002E_2, Reg002E_3, Reg002E_5, Reg002E_6, Reg002E_7;
reg Reg002E_4;
assign Reg002E = {Reg002E_7, Reg002E_6, Reg002E_5, Reg002E_4, Reg002E_3, Reg002E_2, Reg002E_1, Reg002E_0};
wire DNA_Pass,DNA_RST;
wire [3:0] KILL;
dcm3 Inst_DCM(
.CLKIN_IN (CLKin),
.RST_IN (DCM_RST),
.CLKFX_OUT (CLK4),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT (CLK1),
.LOCKED_OUT (DCM_LOCKED)
);
TF_Stub Inst_TF_Stub(
.RESET (DNA_RST),
.CLK4 (CLK4),
.TFD0 (TFD0),
.TFD1 (TFD1),
.TFD2 (TFD2),
.TFD3 (TFD3),
.TF_CLK (TFCLK),
.TF_CMD (TFCMD),
.TF_SENSE (TFSENSE)
);
Top dna1 (
.reset(DNA_RST),
.clk4(CLK4),
.IDE_CS(IDE_CS),
.dna_pass(DNA_Pass),
.KILL(KILL)
);
Reg38 R_38(
.UDMAC (UDMAC),
.PS2WrIDE (PS2WrIDE),
.iIRQ (SiIRQ),
.cDQ (cDQ),
.iDQ (SiDQ),
.iDK (iDK),
.BufEmpty (BufEmpty),
.PB_HvSpace (PB_HvSpace),
.BufSize (BufSize),
.DOut (Reg0038)
);
PS2_DMA PS2DMA(
.CLK4 (CLK4),
.Phase3 (Phase3),
.cDQ (cDQ),
.cDK (cDK),
.cRd (cRd),
.DWrite (DWrite),
.DMA_ARM (DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.PB_HvSpace (PB_HvSpace),
.PB_OD_Rdy (PB_OD_Rdy),
.WithinBBlock (WithinBBlock),
.BBurstEnd (BBurstEnd),
.IncAddrB (IncAddrB),
.RegEB (RegEB),
.EnbB (EnbB),
.WrB (WrB )
);
D_RAM DMARAM(
.CLK4 (CLK4),
.DMA_ARM (DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.CRC_Q (CRC_Q),
.PA_HvSpace (PA_HvSpace),
.PA_OD_Rdy (PA_OD_Rdy),
.PA_AlmostFull (PA_AlmostFull),
.PA_Full (PA_Full),
.PA_Empty (PA_Empty),
.WithinABlock (WithinABlock),
.PB_HvSpace (PB_HvSpace),
.PB_OD_Rdy (PB_OD_Rdy),
.BufSize (BufSize),
.BufEmpty (BufEmpty),
.DInA (DIn2),
.DOutA (DOutA),
.DInB (DMARAMD),
.A0 (A0),
.HWOE (HWOE),
.IncAddrA (IncAddrA),
.EnbA (EnbA),
.WrA (WrA),
.RegEA (RegEA),
.WithinBBlock (WithinBBlock),
.BBurstEnd (BBurstEnd),
.IncAddrB (IncAddrB),
.EnbB (EnbB),
.RegEB (RegEB),
.WrB (WrB),
.DOutB (DMARAMQ)
);
IDE_DMA IDEDMA (
.CLK4 (CLK4),
.Phase3 (Phase3),
.iDK (iDK),
.iDQ (SiDQ),
.SiRdy1 (SiRdy1),
.SiRdy2 (SiRdy2),
.DMA_ARM(DMA_ARM),
.PS2WrIDE (PS2WrIDE),
.UDMA (UDMA),
.MDMA (MDMA),
.iDMARd (iDMARd),
.iDMAWr (iDMAWr),
.iDMA_OE (iDMA_OE),
.iD_245_In (iD_245_In),
.CRC_MUX (CRC_MUX),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.PA_HvSpace (PA_HvSpace),
.PA_OD_Rdy (PA_OD_Rdy),
.WithinABlock (WithinABlock),
.PA_AlmostFull(PA_AlmostFull),
.PA_Full (PA_Full),
.PA_Empty (PA_Empty),
.IDE_DSTB (IDE_DSTB),
.IncAddrA (IncAddrA),
.A0 (A0),
.HWOE (HWOE),
.EnbA (EnbA),
.WrA (WrA),
.RegEA (RegEA)
);
assign JT_Result = (JT_bTest == 1'b0) ? ( ~DNA_Pass ) : ( HDD_ACK | ACS_LED | ibDASP | bCRT );
assign JT_Pin1 = TFCLK;
assign DCM_RST = ~bCRST | ~bCSRST;
assign bHardReset = bCRST & DCM_LOCKED;
assign DNA_RST = ~DCM_LOCKED;
always @(negedge CLK1) begin
if (DCM_LOCKED == 1'b0) begin
Ph0 <= 1'b0;
end else begin
Ph0 <= ~Ph0;
end
end
always @(negedge CLK4) begin
Ph1 <= Ph0;
Ph2 <= Ph1;
end
always @(posedge CLK4) begin
Phase3 <= Ph1 ^ Ph2;
end
assign ibRST = ~(Reg0064[7]);
assign ibCS0 = ~(iCS0);
assign ibCS1 = ~(iCS1);
assign ibRd = ~(iRd);
assign ibWr = ~(iWr);
assign ibDK = ~(iDK);
assign iRd = ( IDERd & ~iDK ) | (iDMARd & iDK);
assign iWr = ( IDEWr & ~iDK ) | (iDMAWr & iDK);
assign cRd = ~bcRd & ~KILL[0];
assign cRdt = ~bCRT & ~KILL[0];
assign cWr = ~bcWr & ~KILL[0];
assign INT9OE = Reg002A[1] | Reg002A[0];
assign bcIRQ = (INT9OE == 1'b1) ? ~(INT9) : 1'bZ;
assign INT9 = (SiIRQ & Reg002A[0]) | (DMA_IrqFF & DMA_IrqCTRL);
assign cDMA_OE = cRdt & cDK;
assign cDOE = ATV & (cDMA_OE | Combo_OE);
assign cDP = (cDOE == 1'b0) ? {16{1'bZ}} :
(cDK == 1'b1) ? DMARAMQ[15:0] :
(IDE_CS == 1'b1) ? iDi[15:0] : RegData[15:0];
assign cDi = cDP;
assign cAOE = ATV & cDMA_OE;
assign cAP = (cAOE == 1'b0) ? {16{1'bZ}} : DMARAMQ[31:16];
assign cAi = cAP;
assign Combo_CS = ATV & ~cDK & ~(bcCS | cAi[15] | cAi[14] | cAi[13] | cAi[12] |
cAi[11] | cAi[10] | cAi[9] | cAi[8] | cAi[7]);
assign Combo_OE = cRd & Combo_CS;
assign iD[15:0] = (iDOEnb == 1'b1) ? iDO[15:0] : {16{1'bZ}};
assign iDOEnb = IDEiOE | iDMA_OE;
assign iDi[15:0] = iD[15:0];
assign iDO[15:0] = (IDE_CS == 1'b1) ? cDi[15:0] :
(CRC_MUX == 1'b1) ? CRC_Q[15:0] : DOutA[15:0];
assign IDE_CS = Combo_CS & ~iDK & cAi[6] & ~cAi[5];
assign iCS1 = IDE_CS & cAi[4] & ~KILL[2];
assign iCS0 = IDE_CS & ~cAi[4] & ~KILL[2];
assign iA[2] = IDE_CS & cAi[3] & ~KILL[1];
assign iA[1] = IDE_CS & cAi[2] & ~KILL[2];
assign iA[0] = IDE_CS & cAi[1] & ~KILL[3];
assign IDERd = IDE_CS & cRd & ~KILL[1];
assign IDEWr = IDE_CS & cWr & ~KILL[2];
assign IDEiOE = IDE_CS & cWr;
assign IDE_Rd_Env = IDE_CS & cRd;
assign Reg0028[15] = BufSize[3];
assign Reg0028[14] = BufEmpty;
assign Reg0028[13:2] = 12'b0000_0000_0000;
assign Reg0028[1] = cDQ;
assign Reg0028[0] = SiIRQ;
assign RegData[15:8] = (cAi[6:0] == 7'h28) ? Reg0028[15:8] : 8'h00;
assign RegData[7:0] = (cAi[6:0] == 7'h02) ? 8'h13 :
(cAi[6:0] == 7'h04) ? 8'h0B :
(cAi[6:0] == 7'h0E) ? 8'h02 :
(cAi[6:0] == 7'h28) ? Reg0028[7:0] :
(cAi[6:0] == 7'h2A) ? Reg002A[7:0] :
(cAi[6:0] == 7'h2E) ? Reg002E[7:0] :
(cAi[6:0] == 7'h38) ? Reg0038[7:0] :
(cAi[6:0] == 7'h64) ? Reg0064[7:0] : 8'h00;
assign DMA_IrqCond = (~(PS2WrIDE) & PB_OD_Rdy) | (PS2WrIDE & PB_HvSpace);
assign DMA_IrqCTRL = Reg002A[1];
assign UDMAC = UDO[2] | UDO[1] | UDO[0];
assign CmdIsEF = cRgD[7] & cRgD[6] & cRgD[5] & ~(cRgD[4]) & cRgD[3] & cRgD[2] & cRgD[1] & cRgD[0];
assign UDMA_SEL = CmdIsEF & R44Is4X & R42Is03;
assign MDMA_SEL = CmdIsEF & R44Is2X & R42Is03;
assign D_UnChg = ~(UDMA_SEL | MDMA_SEL);
assign UDMA[2:0] = UDO[2:0];
assign MDMA[2] = MDO[2];
assign MDMA[1] = MDO[1];
assign MDMA[0] = ~(UDO[2] | UDO[1] | UDO[0] | MDO[2] | MDO[1]);
assign Reg002E_7 = 1'b1;
assign Reg002E_6 = 1'b1;
assign Reg002E_5 = 1'b0;
assign Reg002E_3 = 1'b1;
assign Reg002E_2 = 1'b1;
assign Reg002E_1 = 1'b1;
assign Reg002E_0 = 1'b0;
assign cRgWr = ATV & ScWr1 & ~(ScWr) & cRgWrEnb;
assign cRgRd2E = ATV & ScRd1 & ~(ScRd) & bcRd2E;
assign OE245 = ~(ATV);
assign DR245 = ~(IDE_Rd_Env | iD_245_In);
always @(posedge bcWr) begin
cRgWrEnb <= Combo_CS & ScWr & ScWr1;
cRgA[6:0] <= cAi[6:0];
cRgD[7:0] <= cDi[7:0];
end
always @(posedge bcRd) begin
bcRd2E <= Combo_CS & ScRd & ScRd1 & ~(cAi[6]) & cAi[5] & ~(cAi[4]) & cAi[3] & cAi[2] & cAi[1] & ~(cAi[0]);
end
always @(posedge CLK4) begin
if ((Ph1 ^ Ph2) == 1'b1) begin
DMARAMD[15:0] <= cDi[15:0];
DMARAMD[31:16] <= cAi[15:0];
end
end
always @(posedge CLK1) begin
DWrite <= cWr & cDK;
end
assign bcWait = (IDE_CS == 1'b1) ? ~cWait : 1'bZ;
always @(posedge CLK4) begin
if (IDE_CS == 1'b0) begin
cWaitCnt <= 4'b0000;
cWait <= 1'b1;
IgnoreIRdyPin <= ~SiRdy2;
end else begin
if (cWaitCnt == 4'b1010) begin
if ((IgnoreIRdyPin == 1'b1) || (SiRdy2 == 1'b1)) begin
cWait <= 1'b0;
end
end else begin
cWaitCnt <= cWaitCnt + 1;
end
end
end
always @(posedge CLK4) begin
if (bHardReset == 1'b0) begin
Reg002A <= 8'h00;
Reg002E_4 <= 1'b0;
Rd2ECnt <= 6'b000001;
Reg0064 <= 8'h80;
DMA_IrqMask <= 1'b0;
DMA_IrqFF <= 1'b0;
PS2WrIDE <= 1'b0;
MDO[2] <= 1'b0;
MDO[1] <= 1'b0;
UDO <= 3'b000;
DMARMC <= 1'b0;
DMA_ARM <= 1'b0;
iDQ1 <= 1'b0;
iIRQ1 <= 1'b0;
cWr1 <= 1'b0;
cRd1 <= 1'b0;
SiRdy1 <= 1'b1;
SiDQ <= 1'b0;
SiIRQ <= 1'b0;
ScWr <= 1'b0;
ScRd <= 1'b0;
SiRdy2 <= 1'b1;
ScRd1 <= 1'b0;
ScWr1 <= 1'b0;
ATV1 <= 1'b0;
ATV2 <= 1'b0;
ATV <= 1'b0;
end else begin
ATV1 <= 1'b1;
ATV2 <= ATV1;
ATV <= ATV2;
iDQ1 <= iDQ;
iIRQ1 <= iIRQ;
cWr1 <= cWr;
cRd1 <= cRd;
SiRdy1 <= iRdy;
DIn1 <= iDi;
SiDQ <= iDQ1;
SiIRQ <= iIRQ1;
ScWr <= cWr1;
ScRd <= cRd1;
SiRdy2 <= SiRdy1;
if (IDE_DSTB == 1'b1) DIn2 <= DIn1;
ScRd1 <= ScRd;
ScWr1 <= ScWr;
if (cRgRd2E == 1'b1) begin
if ((Rd2ECnt == 6'b000110) || (Rd2ECnt == 6'b010010) || (Rd2ECnt == 6'b010011) || (Rd2ECnt == 6'b010101) ||
(Rd2ECnt == 6'b010111) || (Rd2ECnt == 6'b011100) || (Rd2ECnt == 6'b011101) || (Rd2ECnt == 6'b011110) ||
(Rd2ECnt == 6'b011111) || (Rd2ECnt == 6'b100000) || (Rd2ECnt == 6'b100011) || (Rd2ECnt == 6'b100100) ||
(Rd2ECnt == 6'b100101) || (Rd2ECnt == 6'b100110) || (Rd2ECnt == 6'b100111) || (Rd2ECnt == 6'b101000) ||
(Rd2ECnt == 6'b101001) || (Rd2ECnt == 6'b101110) || (Rd2ECnt == 6'b110000) || (Rd2ECnt == 6'b110001) ||
(Rd2ECnt == 6'b110011) || (Rd2ECnt == 6'b110101) || (Rd2ECnt == 6'b110110) || (Rd2ECnt == 6'b111000) ||
(Rd2ECnt == 6'b111001) || (Rd2ECnt == 6'b111011) || (Rd2ECnt == 6'b111110))
begin
Reg002E_4 <= 1'b1;
end else begin
Reg002E_4 <= 1'b0;
end
Rd2ECnt <= Rd2ECnt + 1;
end
if (cRgWr == 1'b0) begin
DMARMC <= ATV;
DMA_ARM <= DMARMC;
if (DMA_IrqMask == 1'b1) begin
DMA_IrqMask <= DMA_IrqCond;
end
if ((DMA_IrqCond == 1'b1) && (DMA_IrqMask == 1'b0)) begin
DMA_IrqMask <= DMA_IrqCTRL;
DMA_IrqFF <= DMA_IrqCTRL;
end
end else begin
case (cRgA[6:0])
7'b0101010: begin
Reg002A[7:0] <= cRgD[7:0];
if (cRgD[7:0] == 8'h00) DMA_IrqFF <= 1'b0;
end
7'b0101100: begin
if (cRgD == 8'hE1) begin
Rd2ECnt <= 6'b00_0001;
end
end
7'b0110010: begin
DMARMC <= 1'b0;
DMA_ARM <= 1'b0;
DMA_IrqFF <= 1'b0;
Reg0064[2] <= 1'b0;
PS2WrIDE <= cRgD[0];
end
7'b1000010: begin
R42Is03 <= ~(cRgD[7] | cRgD[6] | cRgD[5] | cRgD[4] | cRgD[3] | cRgD[2]) & cRgD[1] & cRgD[0];
end
7'b1000100: begin
R44Is2X <= ~(cRgD[7] | cRgD[6] | cRgD[4] | cRgD[3]) & cRgD[5];
R44Is4X <= ~(cRgD[7] | cRgD[5] | cRgD[4] | cRgD[3]) & cRgD[6];
R44[2] <= cRgD[2];
R44[1] <= cRgD[1];
R44[0] <= cRgD[0];
end
7'b1001110: begin
UDO[2] <= (D_UnChg & UDO[2]) | (~(D_UnChg) & UDMA_SEL & R44[2]);
UDO[1] <= (D_UnChg & UDO[1]) | (~(D_UnChg) & UDMA_SEL & R44[1]);
UDO[0] <= (D_UnChg & UDO[0]) | (~(D_UnChg) & UDMA_SEL & R44[0]);
MDO[2] <= (D_UnChg & MDO[2]) | (~(D_UnChg) & MDMA_SEL & R44[2]);
MDO[1] <= (D_UnChg & MDO[1]) | (~(D_UnChg) & MDMA_SEL & R44[1]);
end
7'b1100100: begin
Reg0064[7:0] <= cRgD[7:0];
end
endcase
end
end
end
endmodule | 0 |
5,235 | data/full_repos/permissive/113654920/hdl/CRC_CAL.v | 113,654,920 | CRC_CAL.v | v | 50 | 83 | [] | [] | [] | [(21, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/113654920/hdl/CRC_CAL.v:33: Cannot find file containing module: 'CRC_CL'\nCRC_CL CF( .D(D), \n^~~~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL.sv\n CRC_CL\n CRC_CL.v\n CRC_CL.sv\n obj_dir/CRC_CL\n obj_dir/CRC_CL.v\n obj_dir/CRC_CL.sv\n%Error: Exiting due to 1 error(s)\n" | 5,658 | module | module CRC_CAL(CLK4, D, CRC_ARM, CRC_ENB, CRC_Q);
input CLK4;
input [15:0] D;
input CRC_ARM;
input CRC_ENB;
output [15:0] CRC_Q;
wire [15:0] R_D;
reg [15:0] R_Q;
CRC_CL CF( .D(D),
.C(R_Q),
.Q(R_D)
);
assign CRC_Q = R_Q;
always @(posedge CLK4) begin
if(CRC_ARM == 1'b0) begin
R_Q <= 16'h4ABA;
end else if(CRC_ENB == 1'b1) begin
R_Q <= R_D;
end
end
endmodule | module CRC_CAL(CLK4, D, CRC_ARM, CRC_ENB, CRC_Q); |
input CLK4;
input [15:0] D;
input CRC_ARM;
input CRC_ENB;
output [15:0] CRC_Q;
wire [15:0] R_D;
reg [15:0] R_Q;
CRC_CL CF( .D(D),
.C(R_Q),
.Q(R_D)
);
assign CRC_Q = R_Q;
always @(posedge CLK4) begin
if(CRC_ARM == 1'b0) begin
R_Q <= 16'h4ABA;
end else if(CRC_ENB == 1'b1) begin
R_Q <= R_D;
end
end
endmodule | 0 |
5,236 | data/full_repos/permissive/113654920/hdl/CRC_CL.v | 113,654,920 | CRC_CL.v | v | 66 | 83 | [] | [] | [] | [(21, 65)] | null | data/verilator_xmls/262f5571-7ded-4f43-b4cb-30a658ec9d70.xml | null | 5,659 | module | module CRC_CL(
input [15:0] D,
input [15:0] C,
output [15:0] Q
);
wire [16:1] f;
assign f[1] = D[0] ^ C[15];
assign f[2] = D[1] ^ C[14];
assign f[3] = D[2] ^ C[13];
assign f[4] = D[3] ^ C[12];
assign f[5] = D[4] ^ C[11] ^ f[1];
assign f[6] = D[5] ^ C[10] ^ f[2];
assign f[7] = D[6] ^ C[9] ^ f[3];
assign f[8] = D[7] ^ C[8] ^ f[4];
assign f[9] = D[8] ^ C[7] ^ f[5];
assign f[10] = D[9] ^ C[6] ^ f[6];
assign f[11] = D[10] ^ C[5] ^ f[7];
assign f[12] = D[11] ^ C[4] ^ f[8] ^ f[1];
assign f[13] = D[12] ^ C[3] ^ f[9] ^ f[2];
assign f[14] = D[13] ^ C[2] ^ f[10] ^ f[3];
assign f[15] = D[14] ^ C[1] ^ f[11] ^ f[4];
assign f[16] = D[15] ^ C[0] ^ f[12] ^ f[5];
assign Q[0] = f[16];
assign Q[1] = f[15];
assign Q[2] = f[14];
assign Q[3] = f[13];
assign Q[4] = f[12];
assign Q[5] = f[11] ^ f[16];
assign Q[6] = f[10] ^ f[15];
assign Q[7] = f[9] ^ f[14];
assign Q[8] = f[8] ^ f[13];
assign Q[9] = f[7] ^ f[12];
assign Q[10] = f[6] ^ f[11];
assign Q[11] = f[5] ^ f[10];
assign Q[12] = f[4] ^ f[9] ^ f[16];
assign Q[13] = f[3] ^ f[8] ^ f[15];
assign Q[14] = f[2] ^ f[7] ^ f[14];
assign Q[15] = f[1] ^ f[6] ^ f[13];
endmodule | module CRC_CL(
input [15:0] D,
input [15:0] C,
output [15:0] Q
); |
wire [16:1] f;
assign f[1] = D[0] ^ C[15];
assign f[2] = D[1] ^ C[14];
assign f[3] = D[2] ^ C[13];
assign f[4] = D[3] ^ C[12];
assign f[5] = D[4] ^ C[11] ^ f[1];
assign f[6] = D[5] ^ C[10] ^ f[2];
assign f[7] = D[6] ^ C[9] ^ f[3];
assign f[8] = D[7] ^ C[8] ^ f[4];
assign f[9] = D[8] ^ C[7] ^ f[5];
assign f[10] = D[9] ^ C[6] ^ f[6];
assign f[11] = D[10] ^ C[5] ^ f[7];
assign f[12] = D[11] ^ C[4] ^ f[8] ^ f[1];
assign f[13] = D[12] ^ C[3] ^ f[9] ^ f[2];
assign f[14] = D[13] ^ C[2] ^ f[10] ^ f[3];
assign f[15] = D[14] ^ C[1] ^ f[11] ^ f[4];
assign f[16] = D[15] ^ C[0] ^ f[12] ^ f[5];
assign Q[0] = f[16];
assign Q[1] = f[15];
assign Q[2] = f[14];
assign Q[3] = f[13];
assign Q[4] = f[12];
assign Q[5] = f[11] ^ f[16];
assign Q[6] = f[10] ^ f[15];
assign Q[7] = f[9] ^ f[14];
assign Q[8] = f[8] ^ f[13];
assign Q[9] = f[7] ^ f[12];
assign Q[10] = f[6] ^ f[11];
assign Q[11] = f[5] ^ f[10];
assign Q[12] = f[4] ^ f[9] ^ f[16];
assign Q[13] = f[3] ^ f[8] ^ f[15];
assign Q[14] = f[2] ^ f[7] ^ f[14];
assign Q[15] = f[1] ^ f[6] ^ f[13];
endmodule | 0 |
5,237 | data/full_repos/permissive/113654920/hdl/dna_p1.v | 113,654,920 | dna_p1.v | v | 173 | 94 | [] | [] | [] | [(21, 172)] | null | null | 1: b"%Error: data/full_repos/permissive/113654920/hdl/dna_p1.v:36: Cannot find file containing module: 'DNA_PORT'\nDNA_PORT #(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/DNA_PORT\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/DNA_PORT.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/DNA_PORT.sv\n DNA_PORT\n DNA_PORT.v\n DNA_PORT.sv\n obj_dir/DNA_PORT\n obj_dir/DNA_PORT.v\n obj_dir/DNA_PORT.sv\n%Error: Exiting due to 1 error(s)\n" | 5,661 | module | module dna_p1(
input ATV,
input CLK4,
output [63:0] DNA_64,
output reg DNA_Valid
);
reg dna_read,dna_shift,dna_clk;
wire dna_out;
reg [5:0] dna_counter;
reg [3:0] dna_ST;
reg [5:0] Adder1;
reg Parity;
reg [56:0] DNA_R;
DNA_PORT #(
.SIM_DNA_VALUE(57'b101010110001111111010110000011000101010111101011110000000)
) dna_code(
.DIN(1'b0),
.READ(dna_read),
.SHIFT(dna_shift),
.DOUT(dna_out),
.CLK(dna_clk)
);
parameter DnIdle = 4'b0000;
parameter Dn01 = 4'b0001;
parameter Dn02 = 4'b0011;
parameter Dn03 = 4'b0010;
parameter Dn04 = 4'b0110;
parameter Dn10 = 4'b0111;
parameter Dn11 = 4'b0101;
parameter Dn12 = 4'b0100;
parameter Dn13 = 4'b1100;
parameter Dn20 = 4'b1101;
parameter Dn99 = 4'b1111;
assign DNA_64[63:7] = DNA_R[56:0];
assign DNA_64[6:1] = Adder1[5:0];
assign DNA_64[0] = Parity;
always @(posedge CLK4) begin
if (ATV == 1'b0) begin
dna_read <= 0;
dna_shift <= 0;
dna_clk <= 0;
dna_counter <= 6'b00_0000;
Adder1 <= 6'b00_0000;
Parity <= 1'b0;
DNA_Valid <= 1'b0;
dna_ST <= DnIdle;
end else begin
case (dna_ST)
DnIdle: begin
dna_read <= 0;
dna_shift <= 0;
dna_clk <= 0;
dna_counter <= 6'b00_0000;
Adder1 <= 6'b00_0000;
Parity <= 1'b0;
DNA_Valid <= 1'b0;
dna_ST <= Dn01;
end
Dn01 : begin
dna_read <= 1;
dna_ST <= Dn02;
end
Dn02 : begin
dna_clk <= 1;
dna_ST <= Dn03;
end
Dn03 : begin
dna_clk <= 0;
dna_ST <= Dn04;
end
Dn04 : begin
dna_read <= 0;
dna_shift <= 1;
dna_ST <= Dn10;
end
Dn10 : begin
DNA_R[55:0] <= DNA_R[56:1];
DNA_R[56] <= dna_out;
if (dna_out == 1'b1) begin
Adder1 <= Adder1 + 1;
Parity <= ~Parity;
end
dna_ST <= Dn11;
end
Dn11 : begin
dna_counter <= dna_counter + 1;
dna_ST <= Dn12;
end
Dn12 : begin
dna_clk <= 1'b1;
dna_ST <= Dn13;
end
Dn13 : begin
dna_clk <= 1'b0;
if (dna_counter == 6'b11_1001) begin
dna_ST <= Dn20;
end else begin
dna_ST <= Dn10;
end
end
Dn20 : begin
Parity <= Parity ^ Adder1[5] ^ Adder1[4] ^ Adder1[3] ^ Adder1[2] ^ Adder1[1] ^ Adder1[0];
dna_ST <= Dn99;
end
Dn99 : begin
DNA_Valid <= 1'b1;
dna_ST <= Dn99;
end
default: begin
dna_ST <= DnIdle;
end
endcase
end
end
endmodule | module dna_p1(
input ATV,
input CLK4,
output [63:0] DNA_64,
output reg DNA_Valid
); |
reg dna_read,dna_shift,dna_clk;
wire dna_out;
reg [5:0] dna_counter;
reg [3:0] dna_ST;
reg [5:0] Adder1;
reg Parity;
reg [56:0] DNA_R;
DNA_PORT #(
.SIM_DNA_VALUE(57'b101010110001111111010110000011000101010111101011110000000)
) dna_code(
.DIN(1'b0),
.READ(dna_read),
.SHIFT(dna_shift),
.DOUT(dna_out),
.CLK(dna_clk)
);
parameter DnIdle = 4'b0000;
parameter Dn01 = 4'b0001;
parameter Dn02 = 4'b0011;
parameter Dn03 = 4'b0010;
parameter Dn04 = 4'b0110;
parameter Dn10 = 4'b0111;
parameter Dn11 = 4'b0101;
parameter Dn12 = 4'b0100;
parameter Dn13 = 4'b1100;
parameter Dn20 = 4'b1101;
parameter Dn99 = 4'b1111;
assign DNA_64[63:7] = DNA_R[56:0];
assign DNA_64[6:1] = Adder1[5:0];
assign DNA_64[0] = Parity;
always @(posedge CLK4) begin
if (ATV == 1'b0) begin
dna_read <= 0;
dna_shift <= 0;
dna_clk <= 0;
dna_counter <= 6'b00_0000;
Adder1 <= 6'b00_0000;
Parity <= 1'b0;
DNA_Valid <= 1'b0;
dna_ST <= DnIdle;
end else begin
case (dna_ST)
DnIdle: begin
dna_read <= 0;
dna_shift <= 0;
dna_clk <= 0;
dna_counter <= 6'b00_0000;
Adder1 <= 6'b00_0000;
Parity <= 1'b0;
DNA_Valid <= 1'b0;
dna_ST <= Dn01;
end
Dn01 : begin
dna_read <= 1;
dna_ST <= Dn02;
end
Dn02 : begin
dna_clk <= 1;
dna_ST <= Dn03;
end
Dn03 : begin
dna_clk <= 0;
dna_ST <= Dn04;
end
Dn04 : begin
dna_read <= 0;
dna_shift <= 1;
dna_ST <= Dn10;
end
Dn10 : begin
DNA_R[55:0] <= DNA_R[56:1];
DNA_R[56] <= dna_out;
if (dna_out == 1'b1) begin
Adder1 <= Adder1 + 1;
Parity <= ~Parity;
end
dna_ST <= Dn11;
end
Dn11 : begin
dna_counter <= dna_counter + 1;
dna_ST <= Dn12;
end
Dn12 : begin
dna_clk <= 1'b1;
dna_ST <= Dn13;
end
Dn13 : begin
dna_clk <= 1'b0;
if (dna_counter == 6'b11_1001) begin
dna_ST <= Dn20;
end else begin
dna_ST <= Dn10;
end
end
Dn20 : begin
Parity <= Parity ^ Adder1[5] ^ Adder1[4] ^ Adder1[3] ^ Adder1[2] ^ Adder1[1] ^ Adder1[0];
dna_ST <= Dn99;
end
Dn99 : begin
DNA_Valid <= 1'b1;
dna_ST <= Dn99;
end
default: begin
dna_ST <= DnIdle;
end
endcase
end
end
endmodule | 0 |
5,238 | data/full_repos/permissive/113654920/hdl/D_RAM.v | 113,654,920 | D_RAM.v | v | 209 | 108 | [] | [] | [] | [(23, 208)] | null | null | 1: b"%Error: data/full_repos/permissive/113654920/hdl/D_RAM.v:74: Cannot find file containing module: 'RAM1'\nRAM1 RAM_Lo (\n^~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/RAM1\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/RAM1.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/RAM1.sv\n RAM1\n RAM1.v\n RAM1.sv\n obj_dir/RAM1\n obj_dir/RAM1.v\n obj_dir/RAM1.sv\n%Error: data/full_repos/permissive/113654920/hdl/D_RAM.v:92: Cannot find file containing module: 'RAM1'\nRAM1 RAM_Hi(\n^~~~\n%Error: data/full_repos/permissive/113654920/hdl/D_RAM.v:111: Cannot find file containing module: 'CRC_CAL'\nCRC_CAL CRC(\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 5,662 | module | module D_RAM(
input CLK4 ,
input DMA_ARM ,
input PS2WrIDE ,
input CRC_ARM ,
input CRC_ENB ,
output [15:0] CRC_Q ,
output [3:0] BufSize ,
output BufEmpty ,
input [15:0] DInA ,
output [15:0] DOutA ,
input [31:0] DInB ,
output [31:0] DOutB ,
output PA_HvSpace ,
output PA_OD_Rdy ,
output PA_AlmostFull ,
output PA_Empty,
output PA_Full,
output WithinABlock ,
output reg A0,
input HWOE,
input RegEA,
input IncAddrA ,
input EnbA ,
input WrA ,
output PB_HvSpace ,
output PB_OD_Rdy ,
output WithinBBlock ,
output BBurstEnd ,
input IncAddrB ,
input RegEB ,
input EnbB ,
input WrB
);
wire R0Enb,R1Enb,R0Wr,R1Wr,RegEA0,RegEA1;
wire [15:0] DOutA0,DOutA1,DInBL,DInBH,DOutBL,DOutBH;
reg [9:0] AddrA,AddrB;
reg [3:0] Page;
wire IncPgA,IncPgB;
wire PageNZ,PageZR;
wire HvSpaceA,HvSpaceB;
wire A_Zero,B_Zero;
RAM1 RAM_Lo (
.clka (CLK4),
.dina (DInA),
.addra (AddrA),
.ena (R0Enb),
.wea (R0Wr),
.regcea (RegEA0),
.douta (DOutA0),
.clkb (CLK4),
.dinb (DInBL),
.addrb (AddrB),
.enb (EnbB),
.regceb (RegEB),
.web (WrB),
.doutb (DOutBL)
);
RAM1 RAM_Hi(
.clka (CLK4),
.dina (DInA),
.addra (AddrA),
.ena (R1Enb),
.wea (R1Wr),
.regcea (RegEA1),
.douta (DOutA1),
.clkb (CLK4),
.dinb (DInBH),
.addrb (AddrB),
.enb (EnbB),
.regceb (RegEB),
.web (WrB),
.doutb (DOutBH)
);
CRC_CAL CRC(
.CLK4 (CLK4),
.D (DInA),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.CRC_Q (CRC_Q)
);
assign DOutA[15:0] = (HWOE == 1'b1) ? DOutA1[15:0] : DOutA0[15:0];
assign DOutB[31:16] = DOutBH[15:0];
assign DOutB[15:0] = DOutBL[15:0];
assign DInBH[15:0] = DInB[31:16];
assign DInBL[15:0] = DInB[15:0];
assign R0Enb = EnbA & ~A0;
assign R1Enb = EnbA & A0;
assign R0Wr = WrA & ~A0;
assign R1Wr = WrA & A0;
assign RegEA0 = RegEA & ~A0;
assign RegEA1 = RegEA & A0;
assign IncPgA = IncAddrA & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3] & AddrA[2] & AddrA[1] & AddrA[0] & A0;
assign IncPgB = IncAddrB & AddrB[6] & AddrB[5] & AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
assign BufEmpty = PageZR & A_Zero & B_Zero;
assign HvSpaceA = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | A_Zero );
assign HvSpaceB = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | B_Zero );
assign PageNZ = Page[3] | Page[2] | Page[1] | Page[0];
assign PageZR = ~(Page[3] | Page[2] | Page[1] | Page[0]);
assign A_Zero = ~(AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0]);
assign PA_Empty = PageZR & A_Zero & ~A0;
assign B_Zero = ~(AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0]);
assign PA_OD_Rdy = PageNZ;
assign PA_HvSpace = HvSpaceA;
assign PA_AlmostFull = Page[3] | (Page[2] & Page[1] & Page[0] & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3]);
assign PA_Full = Page[3];
assign WithinABlock = AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0] | A0;
assign PB_OD_Rdy = PageNZ;
assign PB_HvSpace = HvSpaceB;
assign WithinBBlock = AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0];
assign BBurstEnd = AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
assign BufSize[3:0] = Page[3:0];
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0)
AddrB <= 10'b00_0000_0000;
else
if(IncAddrB == 1'b1)
AddrB <= AddrB + 1;
end
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
AddrA <= 10'b00_0000_0000;
A0 <= 1'b0;
end else begin
if(IncAddrA == 1'b1) begin
if (A0 == 1'b1) begin
AddrA <= AddrA + 1;
A0 <= 1'b0;
end else begin
A0 <= 1'b1;
end
end
end
end
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
Page <= 4'b0000;
end else begin
if (PS2WrIDE == 1'b1) begin
if (IncPgB == 1'b1) begin
if (IncPgA == 1'b0) Page <= Page + 1;
end else begin
if (IncPgA == 1'b1) Page <= Page - 1;
end
end else begin
if (IncPgA == 1'b1) begin
if (IncPgB == 1'b0) Page <= Page + 1;
end else begin
if (IncPgB == 1'b1) Page <= Page - 1;
end
end
end
end
endmodule | module D_RAM(
input CLK4 ,
input DMA_ARM ,
input PS2WrIDE ,
input CRC_ARM ,
input CRC_ENB ,
output [15:0] CRC_Q ,
output [3:0] BufSize ,
output BufEmpty ,
input [15:0] DInA ,
output [15:0] DOutA ,
input [31:0] DInB ,
output [31:0] DOutB ,
output PA_HvSpace ,
output PA_OD_Rdy ,
output PA_AlmostFull ,
output PA_Empty,
output PA_Full,
output WithinABlock ,
output reg A0,
input HWOE,
input RegEA,
input IncAddrA ,
input EnbA ,
input WrA ,
output PB_HvSpace ,
output PB_OD_Rdy ,
output WithinBBlock ,
output BBurstEnd ,
input IncAddrB ,
input RegEB ,
input EnbB ,
input WrB
); |
wire R0Enb,R1Enb,R0Wr,R1Wr,RegEA0,RegEA1;
wire [15:0] DOutA0,DOutA1,DInBL,DInBH,DOutBL,DOutBH;
reg [9:0] AddrA,AddrB;
reg [3:0] Page;
wire IncPgA,IncPgB;
wire PageNZ,PageZR;
wire HvSpaceA,HvSpaceB;
wire A_Zero,B_Zero;
RAM1 RAM_Lo (
.clka (CLK4),
.dina (DInA),
.addra (AddrA),
.ena (R0Enb),
.wea (R0Wr),
.regcea (RegEA0),
.douta (DOutA0),
.clkb (CLK4),
.dinb (DInBL),
.addrb (AddrB),
.enb (EnbB),
.regceb (RegEB),
.web (WrB),
.doutb (DOutBL)
);
RAM1 RAM_Hi(
.clka (CLK4),
.dina (DInA),
.addra (AddrA),
.ena (R1Enb),
.wea (R1Wr),
.regcea (RegEA1),
.douta (DOutA1),
.clkb (CLK4),
.dinb (DInBH),
.addrb (AddrB),
.enb (EnbB),
.regceb (RegEB),
.web (WrB),
.doutb (DOutBH)
);
CRC_CAL CRC(
.CLK4 (CLK4),
.D (DInA),
.CRC_ARM (CRC_ARM),
.CRC_ENB (CRC_ENB),
.CRC_Q (CRC_Q)
);
assign DOutA[15:0] = (HWOE == 1'b1) ? DOutA1[15:0] : DOutA0[15:0];
assign DOutB[31:16] = DOutBH[15:0];
assign DOutB[15:0] = DOutBL[15:0];
assign DInBH[15:0] = DInB[31:16];
assign DInBL[15:0] = DInB[15:0];
assign R0Enb = EnbA & ~A0;
assign R1Enb = EnbA & A0;
assign R0Wr = WrA & ~A0;
assign R1Wr = WrA & A0;
assign RegEA0 = RegEA & ~A0;
assign RegEA1 = RegEA & A0;
assign IncPgA = IncAddrA & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3] & AddrA[2] & AddrA[1] & AddrA[0] & A0;
assign IncPgB = IncAddrB & AddrB[6] & AddrB[5] & AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
assign BufEmpty = PageZR & A_Zero & B_Zero;
assign HvSpaceA = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | A_Zero );
assign HvSpaceB = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | B_Zero );
assign PageNZ = Page[3] | Page[2] | Page[1] | Page[0];
assign PageZR = ~(Page[3] | Page[2] | Page[1] | Page[0]);
assign A_Zero = ~(AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0]);
assign PA_Empty = PageZR & A_Zero & ~A0;
assign B_Zero = ~(AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0]);
assign PA_OD_Rdy = PageNZ;
assign PA_HvSpace = HvSpaceA;
assign PA_AlmostFull = Page[3] | (Page[2] & Page[1] & Page[0] & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3]);
assign PA_Full = Page[3];
assign WithinABlock = AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0] | A0;
assign PB_OD_Rdy = PageNZ;
assign PB_HvSpace = HvSpaceB;
assign WithinBBlock = AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0];
assign BBurstEnd = AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
assign BufSize[3:0] = Page[3:0];
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0)
AddrB <= 10'b00_0000_0000;
else
if(IncAddrB == 1'b1)
AddrB <= AddrB + 1;
end
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
AddrA <= 10'b00_0000_0000;
A0 <= 1'b0;
end else begin
if(IncAddrA == 1'b1) begin
if (A0 == 1'b1) begin
AddrA <= AddrA + 1;
A0 <= 1'b0;
end else begin
A0 <= 1'b1;
end
end
end
end
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
Page <= 4'b0000;
end else begin
if (PS2WrIDE == 1'b1) begin
if (IncPgB == 1'b1) begin
if (IncPgA == 1'b0) Page <= Page + 1;
end else begin
if (IncPgA == 1'b1) Page <= Page - 1;
end
end else begin
if (IncPgA == 1'b1) begin
if (IncPgB == 1'b0) Page <= Page + 1;
end else begin
if (IncPgB == 1'b1) Page <= Page - 1;
end
end
end
end
endmodule | 0 |
5,239 | data/full_repos/permissive/113654920/hdl/IDE_DMA.v | 113,654,920 | IDE_DMA.v | v | 673 | 117 | [] | [] | [] | [(27, 672)] | null | data/verilator_xmls/24876274-6682-4532-96a6-769826a2d186.xml | null | 5,663 | module | module IDE_DMA(
input CLK4 ,
input Phase3 ,
output reg iDK ,
input iDQ ,
input SiRdy1 ,
input SiRdy2 ,
input DMA_ARM ,
input PS2WrIDE ,
input [2:0] UDMA ,
input [2:0] MDMA,
output iDMARd ,
output iDMAWr ,
output reg iDMA_OE ,
output reg iD_245_In ,
output reg CRC_MUX ,
output reg CRC_ARM ,
output reg CRC_ENB ,
input A0 ,
input PA_Full ,
input PA_HvSpace ,
input PA_OD_Rdy ,
input WithinABlock ,
input PA_AlmostFull ,
input PA_Empty ,
output IDE_DSTB,
output reg HWOE,
output reg RegEA,
output reg IncAddrA ,
output reg EnbA ,
output reg WrA
);
reg HDMARDY,HSTROBE,STOP;
reg ND_Rd,ND_Wr;
wire NBrkOut;
reg iWait;
wire UDMAC,MDMAC;
reg ND_ARM;
reg UHO_ARM;
reg UDI_ARM;
reg ILatch;
wire Proceed;
wire XiRdy1;
parameter iIdle1 = 6'b00_0000;
parameter iIdle2 = 6'b00_0001;
parameter ND_2 = 6'b00_0010;
parameter ND_3 = 6'b00_0011;
parameter ND_4 = 6'b00_0100;
parameter ND_5 = 6'b00_0101;
parameter ND_6 = 6'b00_0110;
parameter ND_7 = 6'b00_0111;
parameter ND_8 = 6'b00_1000;
parameter ND_9 = 6'b00_1001;
parameter ND_A = 6'b00_1010;
parameter ND_B = 6'b00_1011;
parameter ND_C = 6'b00_1100;
parameter Udi1 = 6'b01_0000;
parameter Udi2 = 6'b01_0001;
parameter Udi3 = 6'b01_0010;
parameter Udi10 = 6'b01_0100;
parameter Udi11 = 6'b01_0101;
parameter Udix1 = 6'b10_0001;
parameter Udix2 = 6'b10_0010;
parameter Udix3 = 6'b10_0011;
parameter Udix4 = 6'b10_0100;
parameter Udix5 = 6'b10_0101;
parameter Udix6 = 6'b10_0110;
parameter Uho_G = 6'b10_0111;
parameter Uhx_0 = 6'b10_1000;
parameter Uhx_1 = 6'b10_1001;
parameter Uhx_2 = 6'b10_1010;
parameter Uhx_3 = 6'b10_1011;
parameter Uhx_4 = 6'b10_1100;
parameter Uhx_5 = 6'b10_1101;
parameter Uhx_6 = 6'b10_1110;
parameter Uho_0 = 6'b11_0000;
parameter Uho_1 = 6'b11_0001;
parameter Uho_2 = 6'b11_0010;
parameter Uho_3 = 6'b11_0011;
parameter Uho_4 = 6'b11_0100;
parameter Uho_5 = 6'b11_0101;
parameter Uho_6 = 6'b11_0110;
parameter Uho_7 = 6'b11_0111;
parameter Uho_8 = 6'b11_1000;
parameter Uho_9 = 6'b11_1001;
parameter Uho_A = 6'b11_1010;
parameter Uho_B = 6'b11_1011;
parameter Uho_C = 6'b11_1100;
parameter Uho_D = 6'b11_1101;
parameter Uho_E = 6'b11_1110;
parameter Uho_F = 6'b11_1111;
reg [5:0] iSTATE;
reg [4:0] iCount;
reg PipeEmpty;
reg IDE_DSTB1;
assign iDMAWr = (ND_ARM & ND_Wr) | ((UDI_ARM | UHO_ARM) & ~(STOP));
assign iDMARd = (ND_ARM & ND_Rd) |
(UDI_ARM & HDMARDY) |
(UHO_ARM & ~HSTROBE);
assign NBrkOut = ~iDQ | (PS2WrIDE & PA_Empty) | (~PS2WrIDE & PA_Full);
assign UDMAC = (UDMA[2] | UDMA[1] | UDMA[0]) & ~(MDMAC);
assign MDMAC = MDMA[2] | MDMA[1] | MDMA[0];
assign Proceed = PA_OD_Rdy | WithinABlock;
assign XiRdy1 = SiRdy1 ^ SiRdy2;
assign IDE_DSTB = (XiRdy1 & UDI_ARM) | ((UHO_ARM | ND_ARM) & ILatch );
always @(posedge CLK4) begin
IDE_DSTB1 <= IDE_DSTB;
CRC_ENB <= IDE_DSTB1 & ~IDE_DSTB;
end
always @(posedge CLK4)begin
if (DMA_ARM == 1'b0) begin
UDI_ARM <= 1'b0;
UHO_ARM <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
iWait <= 1'b0;
HSTROBE <= 1'b1;
ND_ARM <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
iD_245_In <= 1'b0;
CRC_ARM <= 1'b0;
CRC_MUX <= 1'b0;
RegEA <= 1'b0;
IncAddrA <= 1'b0;
EnbA <= 1'b0;
WrA <= 1'b0;
iCount <= 5'b0000;
HWOE <= 1'b0;
PipeEmpty <= 1'b1;
iSTATE <= iIdle1;
end else begin
if (UHO_ARM == 1'b1) begin
if (SiRdy2 == 1'b1) begin
iWait <= 1'b1;
iCount <= 5'd00;
end else begin
iCount <= iCount + 1;
if (iCount[4] == 1'b1) begin
iWait <= 1'b0;
end
end
end
case (iSTATE)
iIdle1: begin
UDI_ARM <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
UHO_ARM <= 1'b0;
HSTROBE <= 1'b1;
ND_ARM <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
iD_245_In <= 1'b0;
CRC_ARM <= 1'b0;
CRC_MUX <= 1'b0;
RegEA <= 1'b0;
IncAddrA <= 1'b0;
EnbA <= 1'b0;
WrA <= 1'b0;
iCount <= 5'b0000;
iSTATE <= iIdle2;
end
iIdle2: begin
iCount <= 5'd00;
if (iDQ == 1'b1) begin
if (UDMAC == 1'b1) begin
if (PS2WrIDE == 1'b1) begin
if (Proceed == 1'b1) begin
iSTATE <= Uho_0;
end
end else begin
if (PA_HvSpace == 1'b1) begin
iSTATE <= Udi1;
end
end
end else begin
if (PS2WrIDE == 1'b1) begin
if (Proceed == 1'b1) begin
iSTATE <= ND_2;
end
end else begin
if (PA_HvSpace == 1'b1) begin
iSTATE <= ND_2;
end
end
end
end else begin
iSTATE <= iIdle2;
end
end
ND_2: begin
iSTATE <= ND_3;
iDK <= iDQ;
ND_ARM <= 1'b1;
iD_245_In <= ~PS2WrIDE;
end
ND_3: begin
iDK <= iDQ;
if (NBrkOut == 1'b0) begin
EnbA <= PS2WrIDE;
iSTATE <= ND_4;
end else begin
iD_245_In <= 1'b0;
ND_ARM <= 1'b0;
iSTATE <= iIdle1;
end
end
ND_4: begin
iSTATE <= ND_5;
EnbA <= 1'b0;
RegEA <= PS2WrIDE;
end
ND_5: begin
iSTATE <= ND_6;
RegEA <= 1'b0;
iCount <= 5'd00;
iDMA_OE <= PS2WrIDE;
end
ND_6: begin
iSTATE <= ND_7;
ND_Rd <= ~PS2WrIDE;
ND_Wr <= PS2WrIDE;
end
ND_7: begin
iCount <= iCount + 1;
if (((iCount == 5'd05) && (MDMA[2] == 1'b1)) ||
((iCount == 5'd07) && (MDMA[1] == 1'b1)) ||
(iCount == 5'd31) ) begin
iSTATE <= ND_8;
end
end
ND_8: begin
ILatch <= ~PS2WrIDE;
iSTATE <= ND_9;
end
ND_9: begin
iSTATE <= ND_A;
end
ND_A: begin
WrA <= ~PS2WrIDE;
EnbA <= ~PS2WrIDE;
iCount <= 5'd00;
iSTATE <= ND_B;
end
ND_B: begin
WrA <= 1'b0;
EnbA <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
IncAddrA <= 1'b1;
iSTATE <= ND_C;
end
ND_C: begin
iDMA_OE <= 1'b0;
IncAddrA <= 1'b0;
HWOE <= A0;
iCount <= iCount + 1;
if (((iCount == 5'd03) && (MDMA[2] == 1'b1)) ||
((iCount == 5'd05) && (MDMA[1] == 1'b1)) ||
(iCount == 5'd31) ) begin
iSTATE <= ND_3;
end
end
Udi1: begin
UDI_ARM <= 1'b1;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udi2;
end
end
Udi2: begin
if (iDQ == 1'b1) begin
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
iSTATE <= Udi3;
end
end else begin
iSTATE <= iIdle1;
end
end
Udi3: begin
iDK <= 1'b1;
iD_245_In <= 1'b1;
CRC_ARM <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Udi10;
end
end
Udi10: begin
IncAddrA <= 1'b0;
if (XiRdy1 == 1'b1) begin
EnbA <= 1'b1;
WrA <= 1'b1;
iSTATE <= Udi11;
end else begin
if (iDQ == 1'b1) begin
HDMARDY <= ~PA_AlmostFull;
STOP <= 1'b0;
iSTATE <= Udi10;
end else begin
HDMARDY <= 1'b0;
STOP <= 1'b1;
iSTATE <= Udix1;
end
end
end
Udi11: begin
iSTATE <= Udi10;
EnbA <= 1'b0;
WrA <= 1'b0;
IncAddrA <= 1'b1;
end
Udix1: begin
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
iSTATE <= Udix2;
end
end
Udix2: begin
CRC_MUX <= 1'b1;
iD_245_In <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udix3;
end
end
Udix3: begin
iDMA_OE <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Udix4;
end
end
Udix4: begin
if (Phase3 == 1'b1) begin
iSTATE <= Udix5;
end
end
Udix5: begin
iDK <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udix6;
end
end
Udix6: begin
if (Phase3 == 1'b1) begin
iSTATE <= iIdle1;
end
end
Uho_0: begin
UHO_ARM <= 1'b1;
iDK <= 1'b1;
STOP <= 1'b1;
HSTROBE <= 1'b1;
EnbA <= PipeEmpty;
iSTATE <= Uho_1;
end
Uho_1: begin
iDK <= 1'b1;
EnbA <= 1'b0;
RegEA <= PipeEmpty;
iD_245_In <= 1'b0;
iSTATE <= Uho_2;
end
Uho_2: begin
RegEA <= 1'b0;
HWOE <= ~PipeEmpty ^ A0;
iSTATE <= Uho_3;
end
Uho_3: begin
STOP <= 1'b0;
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
iSTATE <= Uho_4;
iDMA_OE <= 1'b1;
end
end
Uho_4: begin
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
IncAddrA <= PipeEmpty;
iSTATE <= Uho_5;
end
end
Uho_5: begin
IncAddrA <= 1'b0;
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
EnbA <= 1'b1;
iSTATE <= Uho_6;
end
end
Uho_6: begin
iSTATE <= Uho_7;
EnbA <= 1'b0;
iWait <= 1'b0;
HSTROBE <= 1'b0;
CRC_ARM <= 1'b1;
end
Uho_7: begin
ILatch <= 1'b1;
if (PA_Empty == 1'b1) begin
iSTATE <= Uho_F;
end else begin
RegEA <= UDMA[2];
iSTATE <= Uho_8;
end
end
Uho_8: begin
RegEA <= UDMA[1];
ILatch <= 1'b0;
HWOE <= (UDMA[2] == 1'b1) ? A0 : HWOE;
if (UDMA[2] == 1'b1) begin
IncAddrA <= 1'b1;
iSTATE <= Uho_D;
end else begin
iSTATE <= Uho_9;
end
end
Uho_9: begin
RegEA <= 1'b0;
HWOE <= (UDMA[1] == 1'b1) ? A0 : HWOE;
if (UDMA[1] == 1'b1) begin
iSTATE <= Uho_C;
end else begin
iSTATE <= Uho_A;
end
end
Uho_A: begin
RegEA <= UDMA[0];
iSTATE <= Uho_B;
end
Uho_B: begin
RegEA <= 1'b0;
HWOE <= (UDMA[0] == 1'b1) ? A0 : HWOE;
iSTATE <= Uho_C;
end
Uho_C: begin
iSTATE <= Uho_D;
IncAddrA <= 1'b1;
end
Uho_D: begin
iSTATE <= Uho_E;
IncAddrA <= 1'b0;
EnbA <= 1'b1;
end
Uho_E: begin
EnbA <= 1'b0;
if (iDQ == 1'b0) begin
iSTATE <= Uhx_0;
end else begin
if (iWait == 1'b0) begin
HSTROBE <= ~HSTROBE;
iSTATE <= Uho_7;
end else begin
iSTATE <= Uho_E;
end
end
end
Uho_F: begin
PipeEmpty <= 1'b1;
ILatch <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uho_G;
end
end
Uho_G: begin
STOP <= 1'b1;
if (Phase3 == 1'b1) begin
if ((SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
iSTATE <= Uhx_3;
end else begin
if (PA_OD_Rdy == 1'b1) begin
EnbA <= PipeEmpty;
iSTATE <= Uho_1;
end
end
end
end
Uhx_0: begin
PipeEmpty <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_1;
end
end
Uhx_1: begin
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_2;
end
end
Uhx_2: begin
STOP <= 1'b1;
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
iSTATE <= Uhx_3;
end
end
Uhx_3: begin
HSTROBE <= 1'b1;
CRC_MUX <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_4;
end
end
Uhx_4: begin
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_5;
end
end
Uhx_5: begin
iDK <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_6;
end
end
Uhx_6: begin
if (Phase3 == 1'b1) begin
iSTATE <= iIdle1;
end
end
default: begin
iSTATE <= iIdle1;
end
endcase
end
end
endmodule | module IDE_DMA(
input CLK4 ,
input Phase3 ,
output reg iDK ,
input iDQ ,
input SiRdy1 ,
input SiRdy2 ,
input DMA_ARM ,
input PS2WrIDE ,
input [2:0] UDMA ,
input [2:0] MDMA,
output iDMARd ,
output iDMAWr ,
output reg iDMA_OE ,
output reg iD_245_In ,
output reg CRC_MUX ,
output reg CRC_ARM ,
output reg CRC_ENB ,
input A0 ,
input PA_Full ,
input PA_HvSpace ,
input PA_OD_Rdy ,
input WithinABlock ,
input PA_AlmostFull ,
input PA_Empty ,
output IDE_DSTB,
output reg HWOE,
output reg RegEA,
output reg IncAddrA ,
output reg EnbA ,
output reg WrA
); |
reg HDMARDY,HSTROBE,STOP;
reg ND_Rd,ND_Wr;
wire NBrkOut;
reg iWait;
wire UDMAC,MDMAC;
reg ND_ARM;
reg UHO_ARM;
reg UDI_ARM;
reg ILatch;
wire Proceed;
wire XiRdy1;
parameter iIdle1 = 6'b00_0000;
parameter iIdle2 = 6'b00_0001;
parameter ND_2 = 6'b00_0010;
parameter ND_3 = 6'b00_0011;
parameter ND_4 = 6'b00_0100;
parameter ND_5 = 6'b00_0101;
parameter ND_6 = 6'b00_0110;
parameter ND_7 = 6'b00_0111;
parameter ND_8 = 6'b00_1000;
parameter ND_9 = 6'b00_1001;
parameter ND_A = 6'b00_1010;
parameter ND_B = 6'b00_1011;
parameter ND_C = 6'b00_1100;
parameter Udi1 = 6'b01_0000;
parameter Udi2 = 6'b01_0001;
parameter Udi3 = 6'b01_0010;
parameter Udi10 = 6'b01_0100;
parameter Udi11 = 6'b01_0101;
parameter Udix1 = 6'b10_0001;
parameter Udix2 = 6'b10_0010;
parameter Udix3 = 6'b10_0011;
parameter Udix4 = 6'b10_0100;
parameter Udix5 = 6'b10_0101;
parameter Udix6 = 6'b10_0110;
parameter Uho_G = 6'b10_0111;
parameter Uhx_0 = 6'b10_1000;
parameter Uhx_1 = 6'b10_1001;
parameter Uhx_2 = 6'b10_1010;
parameter Uhx_3 = 6'b10_1011;
parameter Uhx_4 = 6'b10_1100;
parameter Uhx_5 = 6'b10_1101;
parameter Uhx_6 = 6'b10_1110;
parameter Uho_0 = 6'b11_0000;
parameter Uho_1 = 6'b11_0001;
parameter Uho_2 = 6'b11_0010;
parameter Uho_3 = 6'b11_0011;
parameter Uho_4 = 6'b11_0100;
parameter Uho_5 = 6'b11_0101;
parameter Uho_6 = 6'b11_0110;
parameter Uho_7 = 6'b11_0111;
parameter Uho_8 = 6'b11_1000;
parameter Uho_9 = 6'b11_1001;
parameter Uho_A = 6'b11_1010;
parameter Uho_B = 6'b11_1011;
parameter Uho_C = 6'b11_1100;
parameter Uho_D = 6'b11_1101;
parameter Uho_E = 6'b11_1110;
parameter Uho_F = 6'b11_1111;
reg [5:0] iSTATE;
reg [4:0] iCount;
reg PipeEmpty;
reg IDE_DSTB1;
assign iDMAWr = (ND_ARM & ND_Wr) | ((UDI_ARM | UHO_ARM) & ~(STOP));
assign iDMARd = (ND_ARM & ND_Rd) |
(UDI_ARM & HDMARDY) |
(UHO_ARM & ~HSTROBE);
assign NBrkOut = ~iDQ | (PS2WrIDE & PA_Empty) | (~PS2WrIDE & PA_Full);
assign UDMAC = (UDMA[2] | UDMA[1] | UDMA[0]) & ~(MDMAC);
assign MDMAC = MDMA[2] | MDMA[1] | MDMA[0];
assign Proceed = PA_OD_Rdy | WithinABlock;
assign XiRdy1 = SiRdy1 ^ SiRdy2;
assign IDE_DSTB = (XiRdy1 & UDI_ARM) | ((UHO_ARM | ND_ARM) & ILatch );
always @(posedge CLK4) begin
IDE_DSTB1 <= IDE_DSTB;
CRC_ENB <= IDE_DSTB1 & ~IDE_DSTB;
end
always @(posedge CLK4)begin
if (DMA_ARM == 1'b0) begin
UDI_ARM <= 1'b0;
UHO_ARM <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
iWait <= 1'b0;
HSTROBE <= 1'b1;
ND_ARM <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
iD_245_In <= 1'b0;
CRC_ARM <= 1'b0;
CRC_MUX <= 1'b0;
RegEA <= 1'b0;
IncAddrA <= 1'b0;
EnbA <= 1'b0;
WrA <= 1'b0;
iCount <= 5'b0000;
HWOE <= 1'b0;
PipeEmpty <= 1'b1;
iSTATE <= iIdle1;
end else begin
if (UHO_ARM == 1'b1) begin
if (SiRdy2 == 1'b1) begin
iWait <= 1'b1;
iCount <= 5'd00;
end else begin
iCount <= iCount + 1;
if (iCount[4] == 1'b1) begin
iWait <= 1'b0;
end
end
end
case (iSTATE)
iIdle1: begin
UDI_ARM <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
UHO_ARM <= 1'b0;
HSTROBE <= 1'b1;
ND_ARM <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
iD_245_In <= 1'b0;
CRC_ARM <= 1'b0;
CRC_MUX <= 1'b0;
RegEA <= 1'b0;
IncAddrA <= 1'b0;
EnbA <= 1'b0;
WrA <= 1'b0;
iCount <= 5'b0000;
iSTATE <= iIdle2;
end
iIdle2: begin
iCount <= 5'd00;
if (iDQ == 1'b1) begin
if (UDMAC == 1'b1) begin
if (PS2WrIDE == 1'b1) begin
if (Proceed == 1'b1) begin
iSTATE <= Uho_0;
end
end else begin
if (PA_HvSpace == 1'b1) begin
iSTATE <= Udi1;
end
end
end else begin
if (PS2WrIDE == 1'b1) begin
if (Proceed == 1'b1) begin
iSTATE <= ND_2;
end
end else begin
if (PA_HvSpace == 1'b1) begin
iSTATE <= ND_2;
end
end
end
end else begin
iSTATE <= iIdle2;
end
end
ND_2: begin
iSTATE <= ND_3;
iDK <= iDQ;
ND_ARM <= 1'b1;
iD_245_In <= ~PS2WrIDE;
end
ND_3: begin
iDK <= iDQ;
if (NBrkOut == 1'b0) begin
EnbA <= PS2WrIDE;
iSTATE <= ND_4;
end else begin
iD_245_In <= 1'b0;
ND_ARM <= 1'b0;
iSTATE <= iIdle1;
end
end
ND_4: begin
iSTATE <= ND_5;
EnbA <= 1'b0;
RegEA <= PS2WrIDE;
end
ND_5: begin
iSTATE <= ND_6;
RegEA <= 1'b0;
iCount <= 5'd00;
iDMA_OE <= PS2WrIDE;
end
ND_6: begin
iSTATE <= ND_7;
ND_Rd <= ~PS2WrIDE;
ND_Wr <= PS2WrIDE;
end
ND_7: begin
iCount <= iCount + 1;
if (((iCount == 5'd05) && (MDMA[2] == 1'b1)) ||
((iCount == 5'd07) && (MDMA[1] == 1'b1)) ||
(iCount == 5'd31) ) begin
iSTATE <= ND_8;
end
end
ND_8: begin
ILatch <= ~PS2WrIDE;
iSTATE <= ND_9;
end
ND_9: begin
iSTATE <= ND_A;
end
ND_A: begin
WrA <= ~PS2WrIDE;
EnbA <= ~PS2WrIDE;
iCount <= 5'd00;
iSTATE <= ND_B;
end
ND_B: begin
WrA <= 1'b0;
EnbA <= 1'b0;
ND_Rd <= 1'b0;
ND_Wr <= 1'b0;
ILatch <= 1'b0;
IncAddrA <= 1'b1;
iSTATE <= ND_C;
end
ND_C: begin
iDMA_OE <= 1'b0;
IncAddrA <= 1'b0;
HWOE <= A0;
iCount <= iCount + 1;
if (((iCount == 5'd03) && (MDMA[2] == 1'b1)) ||
((iCount == 5'd05) && (MDMA[1] == 1'b1)) ||
(iCount == 5'd31) ) begin
iSTATE <= ND_3;
end
end
Udi1: begin
UDI_ARM <= 1'b1;
iDK <= 1'b0;
iDMA_OE <= 1'b0;
STOP <= 1'b1;
HDMARDY <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udi2;
end
end
Udi2: begin
if (iDQ == 1'b1) begin
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
iSTATE <= Udi3;
end
end else begin
iSTATE <= iIdle1;
end
end
Udi3: begin
iDK <= 1'b1;
iD_245_In <= 1'b1;
CRC_ARM <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Udi10;
end
end
Udi10: begin
IncAddrA <= 1'b0;
if (XiRdy1 == 1'b1) begin
EnbA <= 1'b1;
WrA <= 1'b1;
iSTATE <= Udi11;
end else begin
if (iDQ == 1'b1) begin
HDMARDY <= ~PA_AlmostFull;
STOP <= 1'b0;
iSTATE <= Udi10;
end else begin
HDMARDY <= 1'b0;
STOP <= 1'b1;
iSTATE <= Udix1;
end
end
end
Udi11: begin
iSTATE <= Udi10;
EnbA <= 1'b0;
WrA <= 1'b0;
IncAddrA <= 1'b1;
end
Udix1: begin
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
iSTATE <= Udix2;
end
end
Udix2: begin
CRC_MUX <= 1'b1;
iD_245_In <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udix3;
end
end
Udix3: begin
iDMA_OE <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Udix4;
end
end
Udix4: begin
if (Phase3 == 1'b1) begin
iSTATE <= Udix5;
end
end
Udix5: begin
iDK <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Udix6;
end
end
Udix6: begin
if (Phase3 == 1'b1) begin
iSTATE <= iIdle1;
end
end
Uho_0: begin
UHO_ARM <= 1'b1;
iDK <= 1'b1;
STOP <= 1'b1;
HSTROBE <= 1'b1;
EnbA <= PipeEmpty;
iSTATE <= Uho_1;
end
Uho_1: begin
iDK <= 1'b1;
EnbA <= 1'b0;
RegEA <= PipeEmpty;
iD_245_In <= 1'b0;
iSTATE <= Uho_2;
end
Uho_2: begin
RegEA <= 1'b0;
HWOE <= ~PipeEmpty ^ A0;
iSTATE <= Uho_3;
end
Uho_3: begin
STOP <= 1'b0;
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
iSTATE <= Uho_4;
iDMA_OE <= 1'b1;
end
end
Uho_4: begin
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
IncAddrA <= PipeEmpty;
iSTATE <= Uho_5;
end
end
Uho_5: begin
IncAddrA <= 1'b0;
if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
EnbA <= 1'b1;
iSTATE <= Uho_6;
end
end
Uho_6: begin
iSTATE <= Uho_7;
EnbA <= 1'b0;
iWait <= 1'b0;
HSTROBE <= 1'b0;
CRC_ARM <= 1'b1;
end
Uho_7: begin
ILatch <= 1'b1;
if (PA_Empty == 1'b1) begin
iSTATE <= Uho_F;
end else begin
RegEA <= UDMA[2];
iSTATE <= Uho_8;
end
end
Uho_8: begin
RegEA <= UDMA[1];
ILatch <= 1'b0;
HWOE <= (UDMA[2] == 1'b1) ? A0 : HWOE;
if (UDMA[2] == 1'b1) begin
IncAddrA <= 1'b1;
iSTATE <= Uho_D;
end else begin
iSTATE <= Uho_9;
end
end
Uho_9: begin
RegEA <= 1'b0;
HWOE <= (UDMA[1] == 1'b1) ? A0 : HWOE;
if (UDMA[1] == 1'b1) begin
iSTATE <= Uho_C;
end else begin
iSTATE <= Uho_A;
end
end
Uho_A: begin
RegEA <= UDMA[0];
iSTATE <= Uho_B;
end
Uho_B: begin
RegEA <= 1'b0;
HWOE <= (UDMA[0] == 1'b1) ? A0 : HWOE;
iSTATE <= Uho_C;
end
Uho_C: begin
iSTATE <= Uho_D;
IncAddrA <= 1'b1;
end
Uho_D: begin
iSTATE <= Uho_E;
IncAddrA <= 1'b0;
EnbA <= 1'b1;
end
Uho_E: begin
EnbA <= 1'b0;
if (iDQ == 1'b0) begin
iSTATE <= Uhx_0;
end else begin
if (iWait == 1'b0) begin
HSTROBE <= ~HSTROBE;
iSTATE <= Uho_7;
end else begin
iSTATE <= Uho_E;
end
end
end
Uho_F: begin
PipeEmpty <= 1'b1;
ILatch <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uho_G;
end
end
Uho_G: begin
STOP <= 1'b1;
if (Phase3 == 1'b1) begin
if ((SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
iSTATE <= Uhx_3;
end else begin
if (PA_OD_Rdy == 1'b1) begin
EnbA <= PipeEmpty;
iSTATE <= Uho_1;
end
end
end
end
Uhx_0: begin
PipeEmpty <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_1;
end
end
Uhx_1: begin
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_2;
end
end
Uhx_2: begin
STOP <= 1'b1;
if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
iSTATE <= Uhx_3;
end
end
Uhx_3: begin
HSTROBE <= 1'b1;
CRC_MUX <= 1'b1;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_4;
end
end
Uhx_4: begin
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_5;
end
end
Uhx_5: begin
iDK <= 1'b0;
if (Phase3 == 1'b1) begin
iSTATE <= Uhx_6;
end
end
Uhx_6: begin
if (Phase3 == 1'b1) begin
iSTATE <= iIdle1;
end
end
default: begin
iSTATE <= iIdle1;
end
endcase
end
end
endmodule | 0 |
5,240 | data/full_repos/permissive/113654920/hdl/PS2_DMA.v | 113,654,920 | PS2_DMA.v | v | 293 | 117 | [] | [] | [] | [(22, 291)] | null | data/verilator_xmls/6d27558d-a9f9-4764-8f6a-d0f5e118419c.xml | null | 5,664 | module | module PS2_DMA (
input CLK4,
input Phase3,
output reg cDQ,
input cDK,
input cRd,
input DWrite,
input DMA_ARM ,
input PS2WrIDE ,
input PB_OD_Rdy ,
input PB_HvSpace ,
input WithinBBlock ,
input BBurstEnd ,
output reg IncAddrB ,
output RegEB ,
output reg EnbB ,
output reg WrB
);
reg DTook;
reg DWrote;
parameter PIdle = 5'b00000;
parameter PR20 = 5'b00100;
parameter PR21 = 5'b00101;
parameter PR22 = 5'b00110;
parameter PR23 = 5'b00111;
parameter PR32 = 5'b01000;
parameter PR37 = 5'b01001;
parameter PR38 = 5'b01010;
parameter PR38A = 5'b01011;
parameter PR38B = 5'b01100;
parameter PW01A = 5'b10001;
parameter PW01B = 5'b10010;
parameter PW01C = 5'b10011;
parameter PW01D = 5'b10100;
parameter PW32 = 5'b10101;
parameter PW35 = 5'b10110;
parameter PW36 = 5'b10111;
parameter PW37 = 5'b11000;
parameter PW38A = 5'b11001;
parameter PW38B = 5'b11010;
parameter PW38C = 5'b11011;
parameter PW38D = 5'b11100;
parameter PW40 = 5'b11101;
reg [4:0] PSST;
reg OPOvrRide;
assign RegEB = Phase3 & ( cRd | OPOvrRide );
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
cDQ <= 1'b0;
DTook <= 1'b0;
DWrote <= 1'b0;
IncAddrB <= 1'b0;
OPOvrRide <= 1'b0;
EnbB <= 1'b0;
WrB <= 1'b0;
PSST <= PIdle;
end else begin
case (PSST)
PIdle: begin
if (PS2WrIDE == 1'b0) begin
cDQ <= 1'b0;
if ((PB_OD_Rdy == 1'b1) && (Phase3 == 1'b1)) begin
PSST <= PR38;
end
end else begin
cDQ <= PB_HvSpace;
if ((cDK == 1'b1) && (Phase3 == 1'b1)) begin
PSST <= PW40;
end
end
end
PR38: begin
cDQ <= 1'b0;
DTook <= 1'b1;
if (Phase3 == 1'b1) begin
PSST <= PR38A;
end
end
PR38A: begin
EnbB <= DTook;
if (Phase3 == 1'b1) begin
PSST <= PR38B;
end
end
PR38B: begin
EnbB <= 1'b0;
OPOvrRide <= 1'b1;
cDQ <= 1'b1;
if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
PSST <= PR20;
DTook <= cRd;
end
end
PR20: begin
OPOvrRide <= 1'b0;
IncAddrB <= DTook;
if ((DTook == 1'b1) && (BBurstEnd == 1'b1)) begin
PSST <= PR32;
end else begin
PSST <= PR21;
end
end
PR21: begin
IncAddrB <= 1'b0;
EnbB <= DTook;
PSST <= PR22;
end
PR22: begin
EnbB <= 1'b0;
cDQ <= cDQ & ~DTook;
PSST <= PR23;
end
PR23: begin
DTook <= cRd;
if (cDK == 1'b1) begin
PSST <= PR20;
end else begin
PSST <= PR37;
end
end
PR32: begin
IncAddrB <= 1'b0;
if (cDK == 1'b1) begin
PSST <= PR32;
end else begin
PSST <= PR37;
end
end
PR37: begin
if (WithinBBlock == 1'b1) begin
if (Phase3 == 1'b1) begin
PSST <= PR38;
end else begin
PSST <= PR37;
end
end else begin
PSST <= PIdle;
end
end
PW40: begin
if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
PSST <= PW01A;
end
end
PW01A: begin
IncAddrB <= 1'b0;
PSST <= PW01B;
end
PW01B: begin
DWrote <= DWrite;
PSST <= PW01C;
end
PW01C: begin
EnbB <= DWrote;
WrB <= DWrote;
PSST <= PW01D;
end
PW01D: begin
EnbB <= 1'b0;
WrB <= 1'b0;
IncAddrB <= DWrote;
if (DWrote == 1'b1) begin
if (BBurstEnd == 1'b1) begin
PSST <= PW32;
end else begin
PSST <= PW01A;
end
end else begin
PSST <= PW01A;
end
end
PW32: begin
IncAddrB <= 1'b0;
if (cDK == 1'b1) begin
PSST <= PW32;
end else begin
PSST <= PW35;
end
end
PW35: begin
if (Phase3 == 1'b1) begin
PSST <= PW36;
end
end
PW36: begin
if (WithinBBlock == 1'b1) begin
if (Phase3 == 1'b1) begin
PSST <= PW37;
end else begin
PSST <= PW36;
end
end else begin
PSST <= PIdle;
end
end
PW37: begin
if (Phase3 == 1'b1) begin
PSST <= PW38A;
end
end
PW38A: begin
PSST <= PW38B;
end
PW38B: begin
PSST <= PW38C;
end
PW38C: begin
cDQ <= 1'b1;
PSST <= PW38D;
end
PW38D: begin
PSST <= PW40;
end
default: begin
PSST <= PIdle;
end
endcase
end
end
endmodule | module PS2_DMA (
input CLK4,
input Phase3,
output reg cDQ,
input cDK,
input cRd,
input DWrite,
input DMA_ARM ,
input PS2WrIDE ,
input PB_OD_Rdy ,
input PB_HvSpace ,
input WithinBBlock ,
input BBurstEnd ,
output reg IncAddrB ,
output RegEB ,
output reg EnbB ,
output reg WrB
); |
reg DTook;
reg DWrote;
parameter PIdle = 5'b00000;
parameter PR20 = 5'b00100;
parameter PR21 = 5'b00101;
parameter PR22 = 5'b00110;
parameter PR23 = 5'b00111;
parameter PR32 = 5'b01000;
parameter PR37 = 5'b01001;
parameter PR38 = 5'b01010;
parameter PR38A = 5'b01011;
parameter PR38B = 5'b01100;
parameter PW01A = 5'b10001;
parameter PW01B = 5'b10010;
parameter PW01C = 5'b10011;
parameter PW01D = 5'b10100;
parameter PW32 = 5'b10101;
parameter PW35 = 5'b10110;
parameter PW36 = 5'b10111;
parameter PW37 = 5'b11000;
parameter PW38A = 5'b11001;
parameter PW38B = 5'b11010;
parameter PW38C = 5'b11011;
parameter PW38D = 5'b11100;
parameter PW40 = 5'b11101;
reg [4:0] PSST;
reg OPOvrRide;
assign RegEB = Phase3 & ( cRd | OPOvrRide );
always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
cDQ <= 1'b0;
DTook <= 1'b0;
DWrote <= 1'b0;
IncAddrB <= 1'b0;
OPOvrRide <= 1'b0;
EnbB <= 1'b0;
WrB <= 1'b0;
PSST <= PIdle;
end else begin
case (PSST)
PIdle: begin
if (PS2WrIDE == 1'b0) begin
cDQ <= 1'b0;
if ((PB_OD_Rdy == 1'b1) && (Phase3 == 1'b1)) begin
PSST <= PR38;
end
end else begin
cDQ <= PB_HvSpace;
if ((cDK == 1'b1) && (Phase3 == 1'b1)) begin
PSST <= PW40;
end
end
end
PR38: begin
cDQ <= 1'b0;
DTook <= 1'b1;
if (Phase3 == 1'b1) begin
PSST <= PR38A;
end
end
PR38A: begin
EnbB <= DTook;
if (Phase3 == 1'b1) begin
PSST <= PR38B;
end
end
PR38B: begin
EnbB <= 1'b0;
OPOvrRide <= 1'b1;
cDQ <= 1'b1;
if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
PSST <= PR20;
DTook <= cRd;
end
end
PR20: begin
OPOvrRide <= 1'b0;
IncAddrB <= DTook;
if ((DTook == 1'b1) && (BBurstEnd == 1'b1)) begin
PSST <= PR32;
end else begin
PSST <= PR21;
end
end
PR21: begin
IncAddrB <= 1'b0;
EnbB <= DTook;
PSST <= PR22;
end
PR22: begin
EnbB <= 1'b0;
cDQ <= cDQ & ~DTook;
PSST <= PR23;
end
PR23: begin
DTook <= cRd;
if (cDK == 1'b1) begin
PSST <= PR20;
end else begin
PSST <= PR37;
end
end
PR32: begin
IncAddrB <= 1'b0;
if (cDK == 1'b1) begin
PSST <= PR32;
end else begin
PSST <= PR37;
end
end
PR37: begin
if (WithinBBlock == 1'b1) begin
if (Phase3 == 1'b1) begin
PSST <= PR38;
end else begin
PSST <= PR37;
end
end else begin
PSST <= PIdle;
end
end
PW40: begin
if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
PSST <= PW01A;
end
end
PW01A: begin
IncAddrB <= 1'b0;
PSST <= PW01B;
end
PW01B: begin
DWrote <= DWrite;
PSST <= PW01C;
end
PW01C: begin
EnbB <= DWrote;
WrB <= DWrote;
PSST <= PW01D;
end
PW01D: begin
EnbB <= 1'b0;
WrB <= 1'b0;
IncAddrB <= DWrote;
if (DWrote == 1'b1) begin
if (BBurstEnd == 1'b1) begin
PSST <= PW32;
end else begin
PSST <= PW01A;
end
end else begin
PSST <= PW01A;
end
end
PW32: begin
IncAddrB <= 1'b0;
if (cDK == 1'b1) begin
PSST <= PW32;
end else begin
PSST <= PW35;
end
end
PW35: begin
if (Phase3 == 1'b1) begin
PSST <= PW36;
end
end
PW36: begin
if (WithinBBlock == 1'b1) begin
if (Phase3 == 1'b1) begin
PSST <= PW37;
end else begin
PSST <= PW36;
end
end else begin
PSST <= PIdle;
end
end
PW37: begin
if (Phase3 == 1'b1) begin
PSST <= PW38A;
end
end
PW38A: begin
PSST <= PW38B;
end
PW38B: begin
PSST <= PW38C;
end
PW38C: begin
cDQ <= 1'b1;
PSST <= PW38D;
end
PW38D: begin
PSST <= PW40;
end
default: begin
PSST <= PIdle;
end
endcase
end
end
endmodule | 0 |
5,241 | data/full_repos/permissive/113654920/hdl/Reg38.v | 113,654,920 | Reg38.v | v | 119 | 125 | [] | [] | [] | [(45, 118)] | null | data/verilator_xmls/87f0a72d-6eb7-43a5-8a87-6bdce528bdbf.xml | null | 5,665 | module | module Reg38(
input UDMAC ,
input PS2WrIDE ,
input iIRQ ,
input cDQ ,
input iDQ ,
input iDK ,
input BufEmpty ,
input PB_HvSpace ,
input [3:0] BufSize ,
output [7:0] DOut
);
wire [7:0] R381;
wire [7:0] W381;
wire WCond1;
wire WCond2,WCond2A,WCond2B1,WCond2B2;
wire WCond3;
wire Activity;
assign Activity = cDQ | iIRQ | iDQ | iDK | BufSize[3] | BufSize[2] | BufSize[1] | BufSize[0];
assign R381[7] = 1'b0;
assign R381[6] = ~Activity;
assign R381[5:4] = 2'b10;
assign R381[3:0] = BufSize[3:0];
assign W381[7:0] =
(BufSize[3:0] == 4'b1000) ? 8'h20 :
(BufSize[3:0] == 4'b0111) ? 8'h21 :
(BufSize[3:0] == 4'b0110) ? 8'h22 :
(BufSize[3:0] == 4'b0000) ? 8'h24 :
8'h23;
assign WCond1 = PS2WrIDE & ~(PB_HvSpace);
assign WCond2 = PS2WrIDE & ~(iDK);
assign WCond2A = WCond2 & BufEmpty;
assign WCond2B1 = WCond2 & ~(BufEmpty) & UDMAC;
assign WCond2B2 = WCond2 & ~(BufEmpty) & ~(UDMAC);
assign WCond3 = PS2WrIDE & iDK;
assign DOut =
(PS2WrIDE == 1'b0) ? R381 :
(WCond1 == 1'b1) ? 8'hA0 :
(WCond2A == 1'b1) ? 8'h50 :
(WCond2B1 == 1'b1) ? 8'h22 :
(WCond2B2 == 1'b1) ? 8'h21 :
(WCond3 == 1'b1) ? W381 :
8'hFF;
endmodule | module Reg38(
input UDMAC ,
input PS2WrIDE ,
input iIRQ ,
input cDQ ,
input iDQ ,
input iDK ,
input BufEmpty ,
input PB_HvSpace ,
input [3:0] BufSize ,
output [7:0] DOut
); |
wire [7:0] R381;
wire [7:0] W381;
wire WCond1;
wire WCond2,WCond2A,WCond2B1,WCond2B2;
wire WCond3;
wire Activity;
assign Activity = cDQ | iIRQ | iDQ | iDK | BufSize[3] | BufSize[2] | BufSize[1] | BufSize[0];
assign R381[7] = 1'b0;
assign R381[6] = ~Activity;
assign R381[5:4] = 2'b10;
assign R381[3:0] = BufSize[3:0];
assign W381[7:0] =
(BufSize[3:0] == 4'b1000) ? 8'h20 :
(BufSize[3:0] == 4'b0111) ? 8'h21 :
(BufSize[3:0] == 4'b0110) ? 8'h22 :
(BufSize[3:0] == 4'b0000) ? 8'h24 :
8'h23;
assign WCond1 = PS2WrIDE & ~(PB_HvSpace);
assign WCond2 = PS2WrIDE & ~(iDK);
assign WCond2A = WCond2 & BufEmpty;
assign WCond2B1 = WCond2 & ~(BufEmpty) & UDMAC;
assign WCond2B2 = WCond2 & ~(BufEmpty) & ~(UDMAC);
assign WCond3 = PS2WrIDE & iDK;
assign DOut =
(PS2WrIDE == 1'b0) ? R381 :
(WCond1 == 1'b1) ? 8'hA0 :
(WCond2A == 1'b1) ? 8'h50 :
(WCond2B1 == 1'b1) ? 8'h22 :
(WCond2B2 == 1'b1) ? 8'h21 :
(WCond3 == 1'b1) ? W381 :
8'hFF;
endmodule | 0 |
5,242 | data/full_repos/permissive/113654920/hdl/TF_Stub.v | 113,654,920 | TF_Stub.v | v | 91 | 114 | [] | [] | [] | [(21, 90)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113654920/hdl/TF_Stub.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance TF_Stub\n TF_COUNT <= 2\'b00; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 5,667 | module | module TF_Stub(
input RESET,
input CLK4,
inout TFD0,
inout TFD1,
inout TFD2,
inout TFD3,
output TF_CMD,
output TF_CLK,
input TF_SENSE
);
reg TF_CLKSO;
reg [7:0] TF_COUNT;
wire TFD0i,TFD1i,TFD2i,TFD3i;
reg [3:0] TFDD;
wire TerminateCount;
wire FAST;
assign TFD0 = (TF_SENSE == 1'b1) ? TFDD[0] : 1'bZ;
assign TFD0i = TFD0;
assign TFD1 = (TF_SENSE == 1'b1) ? TFDD[1] : 1'bZ;
assign TFD1i = TFD1;
assign TFD2 = (TF_SENSE == 1'b1) ? TFDD[2] : 1'bZ;
assign TFD2i = TFD2;
assign TFD3 = (TF_SENSE == 1'b1) ? TFDD[3] : 1'bZ;
assign TFD3i = TFD3;
assign TF_CLK = (TF_SENSE == 1'b1) ? TF_CLKSO : 1'b0;
assign TF_CMD = (TF_SENSE == 1'b1) ? TFD0i ^ TFD1i ^ TFD2i ^ TFD3i : 1'b0;
assign FAST = TFD0i;
assign TerminateCount = (FAST & TF_COUNT[1] & ~TF_COUNT[0] ) |
(TF_COUNT[7] & TF_COUNT[5] & TF_COUNT[4] & TF_COUNT[2] & TF_COUNT[1]);
always @(posedge CLK4)begin
if (RESET == 1'b1) begin
TF_COUNT <= 2'b00;
TF_CLKSO <= 1'b0;
TFDD <= 4'b0000;
end else begin
TFDD <= TFDD + 1;
if (TerminateCount == 1'b1) begin
TF_COUNT[7:0] <= 8'b0000_0000;
TF_CLKSO <= ~TF_CLKSO;
end else begin
TF_COUNT <= TF_COUNT + 1;
end
end
end
endmodule | module TF_Stub(
input RESET,
input CLK4,
inout TFD0,
inout TFD1,
inout TFD2,
inout TFD3,
output TF_CMD,
output TF_CLK,
input TF_SENSE
); |
reg TF_CLKSO;
reg [7:0] TF_COUNT;
wire TFD0i,TFD1i,TFD2i,TFD3i;
reg [3:0] TFDD;
wire TerminateCount;
wire FAST;
assign TFD0 = (TF_SENSE == 1'b1) ? TFDD[0] : 1'bZ;
assign TFD0i = TFD0;
assign TFD1 = (TF_SENSE == 1'b1) ? TFDD[1] : 1'bZ;
assign TFD1i = TFD1;
assign TFD2 = (TF_SENSE == 1'b1) ? TFDD[2] : 1'bZ;
assign TFD2i = TFD2;
assign TFD3 = (TF_SENSE == 1'b1) ? TFDD[3] : 1'bZ;
assign TFD3i = TFD3;
assign TF_CLK = (TF_SENSE == 1'b1) ? TF_CLKSO : 1'b0;
assign TF_CMD = (TF_SENSE == 1'b1) ? TFD0i ^ TFD1i ^ TFD2i ^ TFD3i : 1'b0;
assign FAST = TFD0i;
assign TerminateCount = (FAST & TF_COUNT[1] & ~TF_COUNT[0] ) |
(TF_COUNT[7] & TF_COUNT[5] & TF_COUNT[4] & TF_COUNT[2] & TF_COUNT[1]);
always @(posedge CLK4)begin
if (RESET == 1'b1) begin
TF_COUNT <= 2'b00;
TF_CLKSO <= 1'b0;
TFDD <= 4'b0000;
end else begin
TFDD <= TFDD + 1;
if (TerminateCount == 1'b1) begin
TF_COUNT[7:0] <= 8'b0000_0000;
TF_CLKSO <= ~TF_CLKSO;
end else begin
TF_COUNT <= TF_COUNT + 1;
end
end
end
endmodule | 0 |
5,243 | data/full_repos/permissive/113654920/hdl/Top.v | 113,654,920 | Top.v | v | 83 | 73 | [] | [] | [] | [(2, 72)] | null | null | 1: b"%Error: data/full_repos/permissive/113654920/hdl/Top.v:25: Cannot find file containing module: 'dna_p1'\ndna_p1 inst_ReadDNA(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dna_p1\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dna_p1.v\n data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dna_p1.sv\n dna_p1\n dna_p1.v\n dna_p1.sv\n obj_dir/dna_p1\n obj_dir/dna_p1.v\n obj_dir/dna_p1.sv\n%Error: data/full_repos/permissive/113654920/hdl/Top.v:32: Cannot find file containing module: 'CheckDNA'\nCheckDNA inst_CheckDNA (\n^~~~~~~~\n%Error: data/full_repos/permissive/113654920/hdl/Top.v:50: Cannot find file containing module: 'RAM'\nRAM inst_RAM (\n^~~\n%Error: Exiting due to 3 error(s)\n" | 5,668 | module | module Top(
input reset,
input clk4,
input IDE_CS,
output dna_pass,
output [3:0] KILL
);
wire [63:0] dna64bits;
wire dna_valid;
wire SR_ena;
wire [9:0] addra;
wire [15:0] douta;
dna_p1 inst_ReadDNA(
.ATV(~reset),
.CLK4(clk4),
.DNA_64(dna64bits),
.DNA_Valid(dna_valid)
);
CheckDNA inst_CheckDNA (
.clk4 (clk4),
.reset (reset),
.DNA_64 (dna64bits),
.dna_valid (dna_valid),
.ROM_Data (douta),
.IDE_CS (IDE_CS),
.DNA_ENA (SR_ena),
.DNA_REG (SR_reg),
.DNA_Addr (addra),
.dna_pass (dna_pass),
.KILL (KILL)
);
RAM inst_RAM (
.clka(clk4),
.addra(addra),
.ena(SR_ena),
.regcea(SR_reg),
.douta(douta));
endmodule | module Top(
input reset,
input clk4,
input IDE_CS,
output dna_pass,
output [3:0] KILL
); |
wire [63:0] dna64bits;
wire dna_valid;
wire SR_ena;
wire [9:0] addra;
wire [15:0] douta;
dna_p1 inst_ReadDNA(
.ATV(~reset),
.CLK4(clk4),
.DNA_64(dna64bits),
.DNA_Valid(dna_valid)
);
CheckDNA inst_CheckDNA (
.clk4 (clk4),
.reset (reset),
.DNA_64 (dna64bits),
.dna_valid (dna_valid),
.ROM_Data (douta),
.IDE_CS (IDE_CS),
.DNA_ENA (SR_ena),
.DNA_REG (SR_reg),
.DNA_Addr (addra),
.dna_pass (dna_pass),
.KILL (KILL)
);
RAM inst_RAM (
.clka(clk4),
.addra(addra),
.ena(SR_ena),
.regcea(SR_reg),
.douta(douta));
endmodule | 0 |
5,244 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v | 113,756,623 | base_ctr_11.v | v | 47 | 75 | [] | [] | [] | null | line:22: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:22: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance base_ctr_11\n reg [4:0] M_val_d, M_val_q = 1\'h0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:28: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'M_val_q\' generates 5 bits.\n : ... In instance base_ctr_11\n ovf = M_val_q == 6\'h0f && inc;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance base_ctr_11\n M_val_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:30: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'M_val_q\' generates 5 bits.\n : ... In instance base_ctr_11\n if (M_val_q == 6\'h0f) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:40: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance base_ctr_11\n M_val_q <= 1\'h0;\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 5,669 | module | module base_ctr_11 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [4:0] value
);
localparam BASE = 5'h10;
reg [4:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 6'h0f && inc;
if (inc) begin
if (M_val_q == 6'h0f) begin
M_val_d = 1'h0;
end else begin
M_val_d = M_val_q + 1'h1;
end
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_val_q <= 1'h0;
end else begin
M_val_q <= M_val_d;
end
end
endmodule | module base_ctr_11 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [4:0] value
); |
localparam BASE = 5'h10;
reg [4:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 6'h0f && inc;
if (inc) begin
if (M_val_q == 6'h0f) begin
M_val_d = 1'h0;
end else begin
M_val_d = M_val_q + 1'h1;
end
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_val_q <= 1'h0;
end else begin
M_val_q <= M_val_d;
end
end
endmodule | 4 |
5,245 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v | 113,756,623 | counter_9.v | v | 56 | 75 | [] | [] | [] | null | line:26: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:26: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance counter_9\n reg [3:0] M_ctr_d, M_ctr_q = 1\'h0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:37: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance counter_9\n M_ctr_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:36: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'M_ctr_q\' generates 4 bits.\n : ... In instance counter_9\n if (1\'h1 && M_ctr_q == 6\'h0f) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:42: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'hf\' generates 6 bits.\n : ... In instance counter_9\n M_ctr_d = 6\'h0f;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:41: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance counter_9\n if (1\'h1 && M_ctr_q == 1\'h0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/counter_9.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance counter_9\n M_ctr_q <= 1\'h0;\n ^~\n%Error: Exiting due to 6 warning(s)\n' | 5,672 | module | module counter_9 (
input clk,
input rst,
output reg [2:0] value
);
localparam SIZE = 2'h3;
localparam DIV = 1'h1;
localparam TOP = 5'h07;
localparam UP = 1'h1;
reg [3:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 6'h0f;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[1+2-:3];
if (1'h1) begin
M_ctr_d = M_ctr_q + 1'h1;
if (1'h1 && M_ctr_q == 6'h0f) begin
M_ctr_d = 1'h0;
end
end else begin
M_ctr_d = M_ctr_q - 1'h1;
if (1'h1 && M_ctr_q == 1'h0) begin
M_ctr_d = 6'h0f;
end
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_ctr_q <= 1'h0;
end else begin
M_ctr_q <= M_ctr_d;
end
end
endmodule | module counter_9 (
input clk,
input rst,
output reg [2:0] value
); |
localparam SIZE = 2'h3;
localparam DIV = 1'h1;
localparam TOP = 5'h07;
localparam UP = 1'h1;
reg [3:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 6'h0f;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[1+2-:3];
if (1'h1) begin
M_ctr_d = M_ctr_q + 1'h1;
if (1'h1 && M_ctr_q == 6'h0f) begin
M_ctr_d = 1'h0;
end
end else begin
M_ctr_d = M_ctr_q - 1'h1;
if (1'h1 && M_ctr_q == 1'h0) begin
M_ctr_d = 6'h0f;
end
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_ctr_q <= 1'h0;
end else begin
M_ctr_q <= M_ctr_d;
end
end
endmodule | 4 |
5,246 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v | 113,756,623 | max7219_3.v | v | 126 | 75 | [] | [] | [] | null | line:25: before: "=" | null | 1: b'%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:33: Cannot find file containing module: \'spi_master_7\'\n spi_master_7 spi (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/spi_master_7\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/spi_master_7.v\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/spi_master_7.sv\n spi_master_7\n spi_master_7.v\n spi_master_7.sv\n obj_dir/spi_master_7\n obj_dir/spi_master_7.v\n obj_dir/spi_master_7.sv\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:45: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance max7219_3\n reg [7:0] M_data_d, M_data_q = 1\'h0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance max7219_3\n reg [7:0] M_addr_d, M_addr_q = 1\'h0;\n ^~~~\n%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:56: Cannot find file containing module: \'counter_8\'\n counter_8 count (\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:92: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance max7219_3\n if (M_count_value == 4\'h8) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:100: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n : ... In instance max7219_3\n if (M_count_value == 5\'h10) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:113: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance max7219_3\n M_data_q <= 1\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:114: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance max7219_3\n M_addr_q <= 1\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/max7219_3.v:116: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance max7219_3\n M_state_q <= 1\'h0;\n ^~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n' | 5,674 | module | module max7219_3 (
input clk,
input rst,
input [7:0] addr_in,
input [7:0] din,
input start,
output reg cs,
output reg dout,
output reg sck,
output reg busy
);
localparam IDLE_state = 2'd0;
localparam TRANSFER_ADDR_state = 2'd1;
localparam TRANSFER_DATA_state = 2'd2;
reg [1:0] M_state_d, M_state_q = IDLE_state;
wire [1-1:0] M_spi_mosi;
wire [1-1:0] M_spi_sck;
wire [8-1:0] M_spi_data_out;
wire [1-1:0] M_spi_new_data;
wire [1-1:0] M_spi_busy;
reg [1-1:0] M_spi_start;
reg [8-1:0] M_spi_data_in;
spi_master_7 spi (
.clk(clk),
.rst(rst),
.miso(1'h0),
.start(M_spi_start),
.data_in(M_spi_data_in),
.mosi(M_spi_mosi),
.sck(M_spi_sck),
.data_out(M_spi_data_out),
.new_data(M_spi_new_data),
.busy(M_spi_busy)
);
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [7:0] M_addr_d, M_addr_q = 1'h0;
reg M_load_state_d, M_load_state_q = 1'h0;
reg [7:0] data_out;
reg mosi;
wire [8-1:0] M_count_value;
reg [1-1:0] M_count_clk;
reg [1-1:0] M_count_rst;
counter_8 count (
.clk(M_count_clk),
.rst(M_count_rst),
.value(M_count_value)
);
always @* begin
M_state_d = M_state_q;
M_load_state_d = M_load_state_q;
M_data_d = M_data_q;
M_addr_d = M_addr_q;
sck = M_spi_sck;
M_count_clk = M_spi_sck;
M_count_rst = 1'h0;
data_out = 8'h00;
M_spi_start = 1'h0;
mosi = 1'h0;
busy = M_state_q != IDLE_state;
dout = 1'h0;
case (M_state_q)
IDLE_state: begin
M_load_state_d = 1'h1;
if (start) begin
M_addr_d = addr_in;
M_data_d = din;
M_count_rst = 1'h1;
M_load_state_d = 1'h0;
M_state_d = TRANSFER_ADDR_state;
end
end
TRANSFER_ADDR_state: begin
M_spi_start = 1'h1;
data_out = M_addr_q;
dout = M_spi_mosi;
if (M_count_value == 4'h8) begin
M_state_d = TRANSFER_DATA_state;
end
end
TRANSFER_DATA_state: begin
M_spi_start = 1'h1;
data_out = M_data_q;
dout = M_spi_mosi;
if (M_count_value == 5'h10) begin
M_load_state_d = 1'h1;
M_count_rst = 1'h1;
M_state_d = IDLE_state;
end
end
endcase
cs = M_load_state_q;
M_spi_data_in = data_out;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_data_q <= 1'h0;
M_addr_q <= 1'h0;
M_load_state_q <= 1'h0;
M_state_q <= 1'h0;
end else begin
M_data_q <= M_data_d;
M_addr_q <= M_addr_d;
M_load_state_q <= M_load_state_d;
M_state_q <= M_state_d;
end
end
endmodule | module max7219_3 (
input clk,
input rst,
input [7:0] addr_in,
input [7:0] din,
input start,
output reg cs,
output reg dout,
output reg sck,
output reg busy
); |
localparam IDLE_state = 2'd0;
localparam TRANSFER_ADDR_state = 2'd1;
localparam TRANSFER_DATA_state = 2'd2;
reg [1:0] M_state_d, M_state_q = IDLE_state;
wire [1-1:0] M_spi_mosi;
wire [1-1:0] M_spi_sck;
wire [8-1:0] M_spi_data_out;
wire [1-1:0] M_spi_new_data;
wire [1-1:0] M_spi_busy;
reg [1-1:0] M_spi_start;
reg [8-1:0] M_spi_data_in;
spi_master_7 spi (
.clk(clk),
.rst(rst),
.miso(1'h0),
.start(M_spi_start),
.data_in(M_spi_data_in),
.mosi(M_spi_mosi),
.sck(M_spi_sck),
.data_out(M_spi_data_out),
.new_data(M_spi_new_data),
.busy(M_spi_busy)
);
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [7:0] M_addr_d, M_addr_q = 1'h0;
reg M_load_state_d, M_load_state_q = 1'h0;
reg [7:0] data_out;
reg mosi;
wire [8-1:0] M_count_value;
reg [1-1:0] M_count_clk;
reg [1-1:0] M_count_rst;
counter_8 count (
.clk(M_count_clk),
.rst(M_count_rst),
.value(M_count_value)
);
always @* begin
M_state_d = M_state_q;
M_load_state_d = M_load_state_q;
M_data_d = M_data_q;
M_addr_d = M_addr_q;
sck = M_spi_sck;
M_count_clk = M_spi_sck;
M_count_rst = 1'h0;
data_out = 8'h00;
M_spi_start = 1'h0;
mosi = 1'h0;
busy = M_state_q != IDLE_state;
dout = 1'h0;
case (M_state_q)
IDLE_state: begin
M_load_state_d = 1'h1;
if (start) begin
M_addr_d = addr_in;
M_data_d = din;
M_count_rst = 1'h1;
M_load_state_d = 1'h0;
M_state_d = TRANSFER_ADDR_state;
end
end
TRANSFER_ADDR_state: begin
M_spi_start = 1'h1;
data_out = M_addr_q;
dout = M_spi_mosi;
if (M_count_value == 4'h8) begin
M_state_d = TRANSFER_DATA_state;
end
end
TRANSFER_DATA_state: begin
M_spi_start = 1'h1;
data_out = M_data_q;
dout = M_spi_mosi;
if (M_count_value == 5'h10) begin
M_load_state_d = 1'h1;
M_count_rst = 1'h1;
M_state_d = IDLE_state;
end
end
endcase
cs = M_load_state_q;
M_spi_data_in = data_out;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_data_q <= 1'h0;
M_addr_q <= 1'h0;
M_load_state_q <= 1'h0;
M_state_q <= 1'h0;
end else begin
M_data_q <= M_data_d;
M_addr_q <= M_addr_d;
M_load_state_q <= M_load_state_d;
M_state_q <= M_state_d;
end
end
endmodule | 4 |
5,248 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_base_ctr_6.v | 113,756,623 | multi_base_ctr_6.v | v | 46 | 75 | [] | [] | [] | [(12, 45)] | null | null | 1: b"%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_base_ctr_6.v:30: Cannot find file containing module: 'base_ctr_11'\n base_ctr_11 dctr (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11.v\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11.sv\n base_ctr_11\n base_ctr_11.v\n base_ctr_11.sv\n obj_dir/base_ctr_11\n obj_dir/base_ctr_11.v\n obj_dir/base_ctr_11.sv\n%Error: Exiting due to 1 error(s)\n" | 5,676 | module | module multi_base_ctr_6 (
input clk,
input rst,
input inc,
output reg [39:0] digits
);
localparam DIGITS = 4'h8;
localparam BASE = 5'h10;
wire [(4'h8+0)-1:0] M_dctr_ovf;
wire [(4'h8+0)*5-1:0] M_dctr_value;
reg [(4'h8+0)-1:0] M_dctr_inc;
genvar GEN_dctr0;
generate
for (GEN_dctr0=0;GEN_dctr0<4'h8;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
base_ctr_11 dctr (
.clk(clk),
.rst(rst),
.inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
.ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
.value(M_dctr_value[GEN_dctr0*(3'h5)+(3'h5)-1-:(3'h5)])
);
end
endgenerate
always @* begin
M_dctr_inc[0+0-:1] = inc;
digits = M_dctr_value;
M_dctr_inc[1+6-:7] = M_dctr_ovf[0+6-:7];
end
endmodule | module multi_base_ctr_6 (
input clk,
input rst,
input inc,
output reg [39:0] digits
); |
localparam DIGITS = 4'h8;
localparam BASE = 5'h10;
wire [(4'h8+0)-1:0] M_dctr_ovf;
wire [(4'h8+0)*5-1:0] M_dctr_value;
reg [(4'h8+0)-1:0] M_dctr_inc;
genvar GEN_dctr0;
generate
for (GEN_dctr0=0;GEN_dctr0<4'h8;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
base_ctr_11 dctr (
.clk(clk),
.rst(rst),
.inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
.ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
.value(M_dctr_value[GEN_dctr0*(3'h5)+(3'h5)-1-:(3'h5)])
);
end
endgenerate
always @* begin
M_dctr_inc[0+0-:1] = inc;
digits = M_dctr_value;
M_dctr_inc[1+6-:7] = M_dctr_ovf[0+6-:7];
end
endmodule | 4 |
5,249 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v | 113,756,623 | multi_seven_seg_5.v | v | 46 | 75 | [] | [] | [] | [(12, 45)] | null | null | 1: b'%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:27: Cannot find file containing module: \'counter_9\'\n counter_9 ctr (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9.v\n data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9.sv\n counter_9\n counter_9.v\n counter_9.sv\n obj_dir/counter_9\n obj_dir/counter_9.v\n obj_dir/counter_9.sv\n%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:35: Cannot find file containing module: \'seven_seg_10\'\n seven_seg_10 seg_dec (\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_ctr_value\' generates 3 bits.\n : ... In instance multi_seven_seg_5\n sel = M_ctr_value;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 5,677 | module | module multi_seven_seg_5 (
input clk,
input rst,
input [39:0] values,
output reg [6:0] seg,
output reg [7:0] sel
);
localparam DIGITS = 4'h8;
localparam DIV = 1'h1;
localparam DIGIT_BITS = 2'h3;
wire [3-1:0] M_ctr_value;
counter_9 ctr (
.clk(clk),
.rst(rst),
.value(M_ctr_value)
);
wire [7-1:0] M_seg_dec_segs;
reg [5-1:0] M_seg_dec_char;
seven_seg_10 seg_dec (
.char(M_seg_dec_char),
.segs(M_seg_dec_segs)
);
always @* begin
M_seg_dec_char = values[(M_ctr_value)*5+4-:5];
seg = M_seg_dec_segs;
sel = M_ctr_value;
end
endmodule | module multi_seven_seg_5 (
input clk,
input rst,
input [39:0] values,
output reg [6:0] seg,
output reg [7:0] sel
); |
localparam DIGITS = 4'h8;
localparam DIV = 1'h1;
localparam DIGIT_BITS = 2'h3;
wire [3-1:0] M_ctr_value;
counter_9 ctr (
.clk(clk),
.rst(rst),
.value(M_ctr_value)
);
wire [7-1:0] M_seg_dec_segs;
reg [5-1:0] M_seg_dec_char;
seven_seg_10 seg_dec (
.char(M_seg_dec_char),
.segs(M_seg_dec_segs)
);
always @* begin
M_seg_dec_char = values[(M_ctr_value)*5+4-:5];
seg = M_seg_dec_segs;
sel = M_ctr_value;
end
endmodule | 4 |
5,251 | data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v | 113,756,623 | spi_master_7.v | v | 97 | 81 | [] | [] | [] | null | line:34: before: "=" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n reg [7:0] M_data_d, M_data_q = 1\'h0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n reg [4:0] M_sck_reg_d, M_sck_reg_q = 1\'h0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:38: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n reg [2:0] M_ctr_d, M_ctr_q = 1\'h0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n M_sck_reg_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:56: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n M_ctr_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:67: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance spi_master_7\n if (M_sck_reg_q == 4\'hf) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:64: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance spi_master_7\n if (M_sck_reg_q == 1\'h0) begin\n ^~\n%Error: Exiting due to 7 warning(s)\n' | 5,680 | module | module spi_master_7 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h5;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [4:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[4+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 4'hf) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 5'h1f) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule | module spi_master_7 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
); |
localparam CLK_DIV = 3'h5;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [4:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[4+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 4'hf) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 5'h1f) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule | 4 |
5,252 | data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v | 113,756,623 | mojo_top_0.v | v | 208 | 75 | [] | [] | [] | null | line:62: before: "=" | null | 1: b'%Error: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:31: Cannot find file containing module: \'reset_conditioner_1\'\n reset_conditioner_1 reset_cond (\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1\n data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1.v\n data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1.sv\n reset_conditioner_1\n reset_conditioner_1.v\n reset_conditioner_1.sv\n obj_dir/reset_conditioner_1\n obj_dir/reset_conditioner_1.v\n obj_dir/reset_conditioner_1.sv\n%Error: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:43: Cannot find file containing module: \'max7219_2\'\n max7219_2 max (\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:63: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n reg [63:0] M_segments_d, M_segments_q = 1\'h0;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:64: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n reg [2:0] M_segment_index_d, M_segment_index_q = 1\'h0;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:135: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n M_segment_index_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:157: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n max_data = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:173: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'M_segment_index_q\' generates 3 bits.\n : ... In instance mojo_top_0\n max_addr = M_segment_index_q + 1\'h1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:179: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n M_segment_index_d = 1\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:171: Operator LT expects 4 bits on the LHS, but LHS\'s VARREF \'M_segment_index_q\' generates 3 bits.\n : ... In instance mojo_top_0\n if (M_segment_index_q < 4\'h8) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:197: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n M_segments_q <= 1\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:198: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n M_segment_index_q <= 1\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:199: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mojo_top_0\n M_state_q <= 1\'h0;\n ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n' | 5,683 | module | module mojo_top_0 (
input clk,
input rst_n,
output reg [7:0] led,
input cclk,
output reg spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output reg [3:0] spi_channel,
input avr_tx,
output reg avr_rx,
input avr_rx_busy,
output reg max7219_load,
output reg max7219_data,
output reg max7219_clock
);
reg rst;
wire [1-1:0] M_reset_cond_out;
reg [1-1:0] M_reset_cond_in;
reset_conditioner_1 reset_cond (
.clk(clk),
.in(M_reset_cond_in),
.out(M_reset_cond_out)
);
wire [1-1:0] M_max_cs;
wire [1-1:0] M_max_dout;
wire [1-1:0] M_max_sck;
wire [1-1:0] M_max_busy;
reg [8-1:0] M_max_addr_in;
reg [8-1:0] M_max_din;
reg [1-1:0] M_max_start;
max7219_2 max (
.clk(clk),
.rst(rst),
.addr_in(M_max_addr_in),
.din(M_max_din),
.start(M_max_start),
.cs(M_max_cs),
.dout(M_max_dout),
.sck(M_max_sck),
.busy(M_max_busy)
);
localparam IDLE_state = 3'd0;
localparam SEND_SHUTDOWN_state = 3'd1;
localparam SEND_RESET_state = 3'd2;
localparam SEND_NO_DECODE_state = 3'd3;
localparam SEND_ALL_DIGITS_state = 3'd4;
localparam SEND_WORD_state = 3'd5;
localparam HALT_state = 3'd6;
reg [2:0] M_state_d, M_state_q = IDLE_state;
reg [63:0] M_segments_d, M_segments_q = 1'h0;
reg [2:0] M_segment_index_d, M_segment_index_q = 1'h0;
reg [7:0] max_addr;
reg [7:0] max_data;
localparam C0 = 8'h7e;
localparam C1 = 8'h30;
localparam C2 = 8'h6d;
localparam C3 = 8'h79;
localparam C4 = 8'h33;
localparam C5 = 8'h5b;
localparam C6 = 8'h5f;
localparam C7 = 8'h70;
localparam C8 = 8'h7f;
localparam C9 = 8'h7b;
localparam A = 8'h77;
localparam B = 8'h1f;
localparam C = 8'h4e;
localparam D = 8'h3d;
localparam E = 8'h4f;
localparam F = 8'h47;
localparam O = 8'h1d;
localparam R = 8'h05;
localparam MINUS = 8'h40;
localparam BLANK = 8'h00;
always @* begin
M_state_d = M_state_q;
M_segments_d = M_segments_q;
M_segment_index_d = M_segment_index_q;
M_segments_d[56+7-:8] = 8'h3d;
M_segments_d[48+7-:8] = 8'h4f;
M_segments_d[40+7-:8] = 8'h77;
M_segments_d[32+7-:8] = 8'h3d;
M_segments_d[24+7-:8] = 8'h1f;
M_segments_d[16+7-:8] = 8'h4f;
M_segments_d[8+7-:8] = 8'h4f;
M_segments_d[0+7-:8] = 8'h47;
M_reset_cond_in = ~rst_n;
rst = M_reset_cond_out;
led = 8'h00;
spi_miso = 1'bz;
spi_channel = 4'bzzzz;
avr_rx = 1'bz;
max_addr = 8'h00;
max_data = 8'h00;
M_max_start = 1'h0;
case (M_state_q)
IDLE_state: begin
M_segment_index_d = 1'h0;
M_state_d = SEND_SHUTDOWN_state;
end
SEND_SHUTDOWN_state: begin
M_max_start = 1'h1;
max_addr = 8'h0c;
max_data = 8'h00;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_RESET_state;
end
end
SEND_RESET_state: begin
M_max_start = 1'h1;
max_addr = 8'h0c;
max_data = 8'h01;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_NO_DECODE_state;
end
end
SEND_NO_DECODE_state: begin
M_max_start = 1'h1;
max_addr = 8'h09;
max_data = 1'h0;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_ALL_DIGITS_state;
end
end
SEND_ALL_DIGITS_state: begin
M_max_start = 1'h1;
max_addr = 8'h0b;
max_data = 8'h07;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_WORD_state;
end
end
SEND_WORD_state: begin
if (M_segment_index_q < 4'h8) begin
M_max_start = 1'h1;
max_addr = M_segment_index_q + 1'h1;
max_data = M_segments_q[(M_segment_index_q)*8+7-:8];
if (M_max_busy != 1'h1) begin
M_segment_index_d = M_segment_index_q + 1'h1;
end
end else begin
M_segment_index_d = 1'h0;
M_state_d = HALT_state;
end
end
HALT_state: begin
max_addr = 8'h00;
max_data = 8'h00;
end
endcase
M_max_addr_in = max_addr;
M_max_din = max_data;
max7219_clock = M_max_sck;
max7219_data = M_max_dout;
max7219_load = M_max_cs;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_segments_q <= 1'h0;
M_segment_index_q <= 1'h0;
M_state_q <= 1'h0;
end else begin
M_segments_q <= M_segments_d;
M_segment_index_q <= M_segment_index_d;
M_state_q <= M_state_d;
end
end
endmodule | module mojo_top_0 (
input clk,
input rst_n,
output reg [7:0] led,
input cclk,
output reg spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output reg [3:0] spi_channel,
input avr_tx,
output reg avr_rx,
input avr_rx_busy,
output reg max7219_load,
output reg max7219_data,
output reg max7219_clock
); |
reg rst;
wire [1-1:0] M_reset_cond_out;
reg [1-1:0] M_reset_cond_in;
reset_conditioner_1 reset_cond (
.clk(clk),
.in(M_reset_cond_in),
.out(M_reset_cond_out)
);
wire [1-1:0] M_max_cs;
wire [1-1:0] M_max_dout;
wire [1-1:0] M_max_sck;
wire [1-1:0] M_max_busy;
reg [8-1:0] M_max_addr_in;
reg [8-1:0] M_max_din;
reg [1-1:0] M_max_start;
max7219_2 max (
.clk(clk),
.rst(rst),
.addr_in(M_max_addr_in),
.din(M_max_din),
.start(M_max_start),
.cs(M_max_cs),
.dout(M_max_dout),
.sck(M_max_sck),
.busy(M_max_busy)
);
localparam IDLE_state = 3'd0;
localparam SEND_SHUTDOWN_state = 3'd1;
localparam SEND_RESET_state = 3'd2;
localparam SEND_NO_DECODE_state = 3'd3;
localparam SEND_ALL_DIGITS_state = 3'd4;
localparam SEND_WORD_state = 3'd5;
localparam HALT_state = 3'd6;
reg [2:0] M_state_d, M_state_q = IDLE_state;
reg [63:0] M_segments_d, M_segments_q = 1'h0;
reg [2:0] M_segment_index_d, M_segment_index_q = 1'h0;
reg [7:0] max_addr;
reg [7:0] max_data;
localparam C0 = 8'h7e;
localparam C1 = 8'h30;
localparam C2 = 8'h6d;
localparam C3 = 8'h79;
localparam C4 = 8'h33;
localparam C5 = 8'h5b;
localparam C6 = 8'h5f;
localparam C7 = 8'h70;
localparam C8 = 8'h7f;
localparam C9 = 8'h7b;
localparam A = 8'h77;
localparam B = 8'h1f;
localparam C = 8'h4e;
localparam D = 8'h3d;
localparam E = 8'h4f;
localparam F = 8'h47;
localparam O = 8'h1d;
localparam R = 8'h05;
localparam MINUS = 8'h40;
localparam BLANK = 8'h00;
always @* begin
M_state_d = M_state_q;
M_segments_d = M_segments_q;
M_segment_index_d = M_segment_index_q;
M_segments_d[56+7-:8] = 8'h3d;
M_segments_d[48+7-:8] = 8'h4f;
M_segments_d[40+7-:8] = 8'h77;
M_segments_d[32+7-:8] = 8'h3d;
M_segments_d[24+7-:8] = 8'h1f;
M_segments_d[16+7-:8] = 8'h4f;
M_segments_d[8+7-:8] = 8'h4f;
M_segments_d[0+7-:8] = 8'h47;
M_reset_cond_in = ~rst_n;
rst = M_reset_cond_out;
led = 8'h00;
spi_miso = 1'bz;
spi_channel = 4'bzzzz;
avr_rx = 1'bz;
max_addr = 8'h00;
max_data = 8'h00;
M_max_start = 1'h0;
case (M_state_q)
IDLE_state: begin
M_segment_index_d = 1'h0;
M_state_d = SEND_SHUTDOWN_state;
end
SEND_SHUTDOWN_state: begin
M_max_start = 1'h1;
max_addr = 8'h0c;
max_data = 8'h00;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_RESET_state;
end
end
SEND_RESET_state: begin
M_max_start = 1'h1;
max_addr = 8'h0c;
max_data = 8'h01;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_NO_DECODE_state;
end
end
SEND_NO_DECODE_state: begin
M_max_start = 1'h1;
max_addr = 8'h09;
max_data = 1'h0;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_ALL_DIGITS_state;
end
end
SEND_ALL_DIGITS_state: begin
M_max_start = 1'h1;
max_addr = 8'h0b;
max_data = 8'h07;
if (M_max_busy != 1'h1) begin
M_state_d = SEND_WORD_state;
end
end
SEND_WORD_state: begin
if (M_segment_index_q < 4'h8) begin
M_max_start = 1'h1;
max_addr = M_segment_index_q + 1'h1;
max_data = M_segments_q[(M_segment_index_q)*8+7-:8];
if (M_max_busy != 1'h1) begin
M_segment_index_d = M_segment_index_q + 1'h1;
end
end else begin
M_segment_index_d = 1'h0;
M_state_d = HALT_state;
end
end
HALT_state: begin
max_addr = 8'h00;
max_data = 8'h00;
end
endcase
M_max_addr_in = max_addr;
M_max_din = max_data;
max7219_clock = M_max_sck;
max7219_data = M_max_dout;
max7219_load = M_max_cs;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_segments_q <= 1'h0;
M_segment_index_q <= 1'h0;
M_state_q <= 1'h0;
end else begin
M_segments_q <= M_segments_d;
M_segment_index_q <= M_segment_index_d;
M_state_q <= M_state_d;
end
end
endmodule | 4 |
5,257 | data/full_repos/permissive/113780415/src/ACounter.v | 113,780,415 | ACounter.v | v | 163 | 76 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113780415/src/ACounter.v:17: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:61: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:66: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:67: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:71: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:76: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:81: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:86: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:91: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:96: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:106: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n" | 5,687 | module | module SevenSegment(HEXleft, HEXright, num);
output reg [6:0] HEXleft, HEXright;
input [4:0] num;
always @(num)
case (num)
5'b00000: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000001;
end
5'b00001: begin
HEXleft = 7'b0000001;
HEXright = 7'b10011111;
end
5'b00010: begin
HEXleft = 7'b0000001;
HEXright = 7'b0010010;
end
5'b00011: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000110;
end
5'b0100: begin
HEXleft = 7'b0000001;
HEXright = 7'b1001101;
end
5'b00101: begin
HEXleft = 7'b0000001;
HEXright = 7'b0100100;
end
5'b00110: begin
HEXleft = 7'b0000001;
HEXright = 7'b0100000;
end
5'b00111: begin
HEXleft = 7'b0000001;
HEXright = 7'b0001111;
end
5'b01000: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000000;
end
5'b01001: begin
HEXleft = 7'b0000001;
HEXright = 7'b0001100;
end
5'b01010: begin
HEXleft = 7'b10011111;
HEXright = 7'b0000001;
end
5'b01011: begin
HEXleft = 7'b10011111;
HEXright = 7'b10011111;
end
5'b01100: begin
HEXleft = 7'b10011111;
HEXright = 7'b0010010;
end
5'b01101: begin
HEXleft = 7'b10011111;
HEXright = 7'b0000110;
end
5'b01110: begin
HEXleft = 7'b10011111;
HEXright = 7'b1001101;
end
5'b01111: begin
HEXleft = 7'b10011111;
HEXright = 7'b0100100;
end
5'b10000: begin
HEXleft = 7'b10011111;
HEXright = 7'b0100000;
end
5'b10001: begin
HEXleft = 7'b10011111;
HEXright = 7'b0001111;
end
5'b10010: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
5'b10011: begin
HEXleft = 7'b10011111;
HEXright = 7'b0001100;
end
5'b10100: begin
HEXleft = 7'b0010010;
HEXright = 7'b0000001;
end
default: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
endcase
endmodule | module SevenSegment(HEXleft, HEXright, num); |
output reg [6:0] HEXleft, HEXright;
input [4:0] num;
always @(num)
case (num)
5'b00000: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000001;
end
5'b00001: begin
HEXleft = 7'b0000001;
HEXright = 7'b10011111;
end
5'b00010: begin
HEXleft = 7'b0000001;
HEXright = 7'b0010010;
end
5'b00011: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000110;
end
5'b0100: begin
HEXleft = 7'b0000001;
HEXright = 7'b1001101;
end
5'b00101: begin
HEXleft = 7'b0000001;
HEXright = 7'b0100100;
end
5'b00110: begin
HEXleft = 7'b0000001;
HEXright = 7'b0100000;
end
5'b00111: begin
HEXleft = 7'b0000001;
HEXright = 7'b0001111;
end
5'b01000: begin
HEXleft = 7'b0000001;
HEXright = 7'b0000000;
end
5'b01001: begin
HEXleft = 7'b0000001;
HEXright = 7'b0001100;
end
5'b01010: begin
HEXleft = 7'b10011111;
HEXright = 7'b0000001;
end
5'b01011: begin
HEXleft = 7'b10011111;
HEXright = 7'b10011111;
end
5'b01100: begin
HEXleft = 7'b10011111;
HEXright = 7'b0010010;
end
5'b01101: begin
HEXleft = 7'b10011111;
HEXright = 7'b0000110;
end
5'b01110: begin
HEXleft = 7'b10011111;
HEXright = 7'b1001101;
end
5'b01111: begin
HEXleft = 7'b10011111;
HEXright = 7'b0100100;
end
5'b10000: begin
HEXleft = 7'b10011111;
HEXright = 7'b0100000;
end
5'b10001: begin
HEXleft = 7'b10011111;
HEXright = 7'b0001111;
end
5'b10010: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
5'b10011: begin
HEXleft = 7'b10011111;
HEXright = 7'b0001100;
end
5'b10100: begin
HEXleft = 7'b0010010;
HEXright = 7'b0000001;
end
default: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
endcase
endmodule | 1 |
5,258 | data/full_repos/permissive/113780415/src/ACounter.v | 113,780,415 | ACounter.v | v | 163 | 76 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113780415/src/ACounter.v:17: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:61: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:66: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:67: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:71: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:76: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:81: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:86: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:91: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:96: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:106: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n" | 5,687 | module | module counter(clk, clear_b, stop, q);
input clk;
input clear_b;
input stop;
output reg [4:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else
q <= q + 1'b1;
end
end
endmodule | module counter(clk, clear_b, stop, q); |
input clk;
input clear_b;
input stop;
output reg [4:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else
q <= q + 1'b1;
end
end
endmodule | 1 |
5,259 | data/full_repos/permissive/113780415/src/ACounter.v | 113,780,415 | ACounter.v | v | 163 | 76 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/113780415/src/ACounter.v:17: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:61: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:66: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:67: Too many digits for 7 bit number: 7'b10011111\n HEXright = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:71: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:76: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:81: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:86: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:91: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:96: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:106: Too many digits for 7 bit number: 7'b10011111\n HEXleft = 7'b10011111;\n ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n" | 5,687 | module | module displaycounter(clk, clear_b, out);
input clk;
input clear_b;
output [5:0] out;
reg [5:0] q = 0;
assign out = q;
always @(posedge clk)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else if (clk == 1'b1)
q <= q + 1'b1;
end
endmodule | module displaycounter(clk, clear_b, out); |
input clk;
input clear_b;
output [5:0] out;
reg [5:0] q = 0;
assign out = q;
always @(posedge clk)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else if (clk == 1'b1)
q <= q + 1'b1;
end
endmodule | 1 |
5,260 | data/full_repos/permissive/113780415/src/Control.v | 113,780,415 | Control.v | v | 56 | 90 | [] | [] | [] | [(3, 56)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:18: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n : ... In instance control\n LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:18: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n : ... In instance control\n LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:19: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n : ... In instance control\n LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:19: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n : ... In instance control\n LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:20: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n : ... In instance control\n LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:20: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n : ... In instance control\n LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:21: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n : ... In instance control\n LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:21: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_USER\' generates 5 bits.\n : ... In instance control\n LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:22: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_USER_WAIT\' generates 5 bits.\n : ... In instance control\n LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:22: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_USER\' generates 5 bits.\n : ... In instance control\n LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:24: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n : ... In instance control\n default: next_state = LOAD_LEFT;\n ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n : ... In instance control\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n : ... In instance control\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n : ... In instance control\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n : ... In instance control\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_USER\' generates 5 bits.\n : ... In instance control\n case(current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n : ... In instance control\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n : ... In instance control\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_USER\' generates 5 bits.\n : ... In instance control\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:52: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n : ... In instance control\n current_state <= LOAD_LEFT; \n ^~\n%Error: Exiting due to 20 warning(s)\n' | 5,688 | module | module control(clk, resetn, ld_user, ld_left, ld_right, stop_left, stop_right, stop_rps);
input clk, resetn;
input stop_left, stop_right, stop_rps;
output reg ld_user, ld_left, ld_right;
reg[5:0] current_state, next_state;
localparam LOAD_LEFT = 5'd0,
LOAD_LEFT_WAIT = 5'd1,
LOAD_RIGHT = 5'd2,
LOAD_RIGHT_WAIT = 5'd3,
LOAD_USER = 5'd4,
LOAD_USER_WAIT = 5'd5;
always@(*)
begin: state_table
case(current_state)
LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;
LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;
default: next_state = LOAD_LEFT;
endcase
end
always @(*)
begin: enable_signals
ld_left = 1'b0;
ld_right = 1'b0;
ld_user = 1'b0;
case (current_state)
LOAD_LEFT: begin
ld_left = 1'b1;
end
LOAD_RIGHT: begin
ld_right = 1'b1;
end
LOAD_USER: begin
ld_user = 1'b1;
end
endcase
end
always @(posedge clk)
begin: state_FFs
if (resetn == 1'b0)
current_state <= LOAD_LEFT;
else
current_state <= next_state;
end
endmodule | module control(clk, resetn, ld_user, ld_left, ld_right, stop_left, stop_right, stop_rps); |
input clk, resetn;
input stop_left, stop_right, stop_rps;
output reg ld_user, ld_left, ld_right;
reg[5:0] current_state, next_state;
localparam LOAD_LEFT = 5'd0,
LOAD_LEFT_WAIT = 5'd1,
LOAD_RIGHT = 5'd2,
LOAD_RIGHT_WAIT = 5'd3,
LOAD_USER = 5'd4,
LOAD_USER_WAIT = 5'd5;
always@(*)
begin: state_table
case(current_state)
LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;
LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;
default: next_state = LOAD_LEFT;
endcase
end
always @(*)
begin: enable_signals
ld_left = 1'b0;
ld_right = 1'b0;
ld_user = 1'b0;
case (current_state)
LOAD_LEFT: begin
ld_left = 1'b1;
end
LOAD_RIGHT: begin
ld_right = 1'b1;
end
LOAD_USER: begin
ld_user = 1'b1;
end
endcase
end
always @(posedge clk)
begin: state_FFs
if (resetn == 1'b0)
current_state <= LOAD_LEFT;
else
current_state <= next_state;
end
endmodule | 1 |
5,278 | data/full_repos/permissive/113780415/src/RPSGame.v | 113,780,415 | RPSGame.v | v | 96 | 51 | [] | [] | [] | null | line:14: before: "[" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/RPSGame.v:14: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n .q([1:0]computer)\n ^\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:19: Define or directive not defined: '`b0'\n if (stop == 1`b0)\n ^~~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:20: syntax error, unexpected IDENTIFIER\n winner_indicator wi (\n ^~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:43: syntax error, unexpected IDENTIFIER\n if (player == 2b'00 && computer == 2b'00)\n ^\n%Error: Exiting due to 4 error(s)\n" | 5,692 | module | module RPSGame(player, clk, stop, clear, winner);
input [1:0] player;
input clk;
input stop;
input clear;
output reg [1:0] winner;
wire reg [1:0] computer;
RPScounter rps(
.clk(clk),
.clear_b(clear),
.stop(stop),
.q([1:0]computer)
);
always @(stop)
begin
if (stop == 1`b0)
winner_indicator wi (
.player(player),
.computer([1:0]computer),
.winner(winner)
);
end
endmodule | module RPSGame(player, clk, stop, clear, winner); |
input [1:0] player;
input clk;
input stop;
input clear;
output reg [1:0] winner;
wire reg [1:0] computer;
RPScounter rps(
.clk(clk),
.clear_b(clear),
.stop(stop),
.q([1:0]computer)
);
always @(stop)
begin
if (stop == 1`b0)
winner_indicator wi (
.player(player),
.computer([1:0]computer),
.winner(winner)
);
end
endmodule | 1 |
5,279 | data/full_repos/permissive/113780415/src/RPSGame.v | 113,780,415 | RPSGame.v | v | 96 | 51 | [] | [] | [] | null | line:14: before: "[" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/RPSGame.v:14: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n .q([1:0]computer)\n ^\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:19: Define or directive not defined: '`b0'\n if (stop == 1`b0)\n ^~~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:20: syntax error, unexpected IDENTIFIER\n winner_indicator wi (\n ^~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:43: syntax error, unexpected IDENTIFIER\n if (player == 2b'00 && computer == 2b'00)\n ^\n%Error: Exiting due to 4 error(s)\n" | 5,692 | module | module winner_indicator(player, computer, winner);
input [1:0] player;
input [1:0] computer;
output reg [1:0] winner;
always @(*)
begin
if (player == 2b'00 && computer == 2b'00)
winner <= 2b'11;
else if (player == 2b'00 && computer == 2b'01)
winner <= 2b'01;
else if (player == 2b'00 && computer == 2b'10)
winner <= 2b'00;
else if (player == 2b'01 && computer == 2b'01)
winner <= 2b'11;
else if (player == 2b'01 && computer == 2b'10)
winner <= 2b'01;
else if (player == 2b'01 && computer == 2b'00)
winner <= 2b'00;
else if (player == 2b'10 && computer == 2b'10)
winner <= 2b'11;
else if (player == 2b'10 && computer == 2b'00)
winner <= 2b'01;
else
winner <= 2b'00;
end
endmodule | module winner_indicator(player, computer, winner); |
input [1:0] player;
input [1:0] computer;
output reg [1:0] winner;
always @(*)
begin
if (player == 2b'00 && computer == 2b'00)
winner <= 2b'11;
else if (player == 2b'00 && computer == 2b'01)
winner <= 2b'01;
else if (player == 2b'00 && computer == 2b'10)
winner <= 2b'00;
else if (player == 2b'01 && computer == 2b'01)
winner <= 2b'11;
else if (player == 2b'01 && computer == 2b'10)
winner <= 2b'01;
else if (player == 2b'01 && computer == 2b'00)
winner <= 2b'00;
else if (player == 2b'10 && computer == 2b'10)
winner <= 2b'11;
else if (player == 2b'10 && computer == 2b'00)
winner <= 2b'01;
else
winner <= 2b'00;
end
endmodule | 1 |
5,280 | data/full_repos/permissive/113780415/src/RPSGame.v | 113,780,415 | RPSGame.v | v | 96 | 51 | [] | [] | [] | null | line:14: before: "[" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/RPSGame.v:14: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n .q([1:0]computer)\n ^\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:19: Define or directive not defined: '`b0'\n if (stop == 1`b0)\n ^~~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:20: syntax error, unexpected IDENTIFIER\n winner_indicator wi (\n ^~\n%Error: data/full_repos/permissive/113780415/src/RPSGame.v:43: syntax error, unexpected IDENTIFIER\n if (player == 2b'00 && computer == 2b'00)\n ^\n%Error: Exiting due to 4 error(s)\n" | 5,692 | module | module RPScounter(clk, clear_b, stop, q);
input clk;
input clear_b;
input stop;
output reg [1:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1)
if (clear_b == 1'b0)
q <= 0;
else if (q == 2'b10)
q <= 0;
else
q <= q + 1'b1;
end
endmodule | module RPScounter(clk, clear_b, stop, q); |
input clk;
input clear_b;
input stop;
output reg [1:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1)
if (clear_b == 1'b0)
q <= 0;
else if (q == 2'b10)
q <= 0;
else
q <= q + 1'b1;
end
endmodule | 1 |
5,281 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module top(SW, KEY, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
input CLOCK_50;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [9:0] LEDR;
wire load_left, load_right, load_user;
wire [1:0] status;
wire three_wins;
wire same_leftright;
wire [1:0] consecutive_win;
wire enable_winner_indicator;
wire [1:0] computer;
wire enable_aalu;
wire [4:0] score;
reg enable_high_score;
wire clear_done;
reg return_to_load_left;
reg go_to_get_user;
wire plot;
wire [2:0] color;
wire [7:0] x;
wire [6:0] y;
wire clk;
wire [5:0] current_state;
control cont (
.clk(clk),
.resetn(KEY[3]),
.confirm(SW[2:2]),
.status(status[1:0]),
.return_to_load_left(return_to_load_left),
.go_to_get_user(go_to_get_user),
.stop_left(KEY[2]),
.stop_right(KEY[0]),
.stop_user(KEY[1]),
.enable_winner_indicator(enable_winner_indicator),
.enable_aalu(enable_aalu),
.ld_user(load_user),
.ld_left(load_left),
.ld_right(load_right),
.curr_state(current_state[5:0]),
.opponent(computer[1:0]),
.plot(plot),
.color(color[2:0]),
.xOut(x),
.yOut(y)
);
data data (
.clk(clk),
.load_left(load_left),
.load_right(load_right),
.stop_left(KEY[2]),
.stop_right(KEY[0]),
.resetn(KEY[3]),
.enable_aalu(enable_aalu),
.enable_winner_indicator(enable_winner_indicator),
.load_user(load_user),
.user_input_player(SW[1:0]),
.computer(computer[1:0]),
.HEX0(HEX0[6:0]),
.HEX1(HEX1[6:0]),
.HEX4(HEX4[6:0]),
.HEX5(HEX5[6:0]),
.LEDR(LEDR[9:8]),
.score(score[4:0]),
.status(status[1:0]),
.same_leftright(same_leftright)
);
assign LEDR[7:3] = score[4:0];
assign LEDR[1:0] = consecutive_win[1:0];
always@(*)
begin
if (same_leftright == 1'b1 || status == 2'b01)
return_to_load_left <= 1'b1;
else
return_to_load_left <= 1'b0;
end
SevenSegment seg(
.HEXleft(HEX3[6:0]),
.HEXright(HEX2[6:0]),
.num({3'b000 ,consecutive_win[1:0]})
);
ratedivider rd (
.clk(CLOCK_50),
.clear_b(KEY[3]),
.out(clk)
);
always@(posedge three_wins)
begin
if (three_wins == 1'b1)
enable_high_score <= 1'b1;
else
enable_high_score <= 1'b0;
end
consecutive_win_counter cwc (
.clk(clk),
.clear_b(KEY[3]),
.q(consecutive_win),
.enable(status[1:0]),
.three_wins(three_wins)
);
endmodule | module top(SW, KEY, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); |
input CLOCK_50;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [9:0] LEDR;
wire load_left, load_right, load_user;
wire [1:0] status;
wire three_wins;
wire same_leftright;
wire [1:0] consecutive_win;
wire enable_winner_indicator;
wire [1:0] computer;
wire enable_aalu;
wire [4:0] score;
reg enable_high_score;
wire clear_done;
reg return_to_load_left;
reg go_to_get_user;
wire plot;
wire [2:0] color;
wire [7:0] x;
wire [6:0] y;
wire clk;
wire [5:0] current_state;
control cont (
.clk(clk),
.resetn(KEY[3]),
.confirm(SW[2:2]),
.status(status[1:0]),
.return_to_load_left(return_to_load_left),
.go_to_get_user(go_to_get_user),
.stop_left(KEY[2]),
.stop_right(KEY[0]),
.stop_user(KEY[1]),
.enable_winner_indicator(enable_winner_indicator),
.enable_aalu(enable_aalu),
.ld_user(load_user),
.ld_left(load_left),
.ld_right(load_right),
.curr_state(current_state[5:0]),
.opponent(computer[1:0]),
.plot(plot),
.color(color[2:0]),
.xOut(x),
.yOut(y)
);
data data (
.clk(clk),
.load_left(load_left),
.load_right(load_right),
.stop_left(KEY[2]),
.stop_right(KEY[0]),
.resetn(KEY[3]),
.enable_aalu(enable_aalu),
.enable_winner_indicator(enable_winner_indicator),
.load_user(load_user),
.user_input_player(SW[1:0]),
.computer(computer[1:0]),
.HEX0(HEX0[6:0]),
.HEX1(HEX1[6:0]),
.HEX4(HEX4[6:0]),
.HEX5(HEX5[6:0]),
.LEDR(LEDR[9:8]),
.score(score[4:0]),
.status(status[1:0]),
.same_leftright(same_leftright)
);
assign LEDR[7:3] = score[4:0];
assign LEDR[1:0] = consecutive_win[1:0];
always@(*)
begin
if (same_leftright == 1'b1 || status == 2'b01)
return_to_load_left <= 1'b1;
else
return_to_load_left <= 1'b0;
end
SevenSegment seg(
.HEXleft(HEX3[6:0]),
.HEXright(HEX2[6:0]),
.num({3'b000 ,consecutive_win[1:0]})
);
ratedivider rd (
.clk(CLOCK_50),
.clear_b(KEY[3]),
.out(clk)
);
always@(posedge three_wins)
begin
if (three_wins == 1'b1)
enable_high_score <= 1'b1;
else
enable_high_score <= 1'b0;
end
consecutive_win_counter cwc (
.clk(clk),
.clear_b(KEY[3]),
.q(consecutive_win),
.enable(status[1:0]),
.three_wins(three_wins)
);
endmodule | 1 |
5,282 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module data(load_left, load_right, user_input_player, computer, load_user, enable_aalu,enable_winner_indicator,
clk, stop_left, stop_right, resetn, HEX0, HEX1, HEX4, HEX5, LEDR, status, same_leftright, score);
input load_left, load_right, clk, stop_left, stop_right, resetn, enable_aalu, enable_winner_indicator, load_user;
input [1:0] user_input_player;
input [1:0] computer;
reg [1:0] player;
output [6:0] HEX0, HEX1, HEX4, HEX5;
output [9:8] LEDR;
output [4:0] score;
output [1:0] status;
output reg same_leftright;
wire [4:0] left;
wire [4:0] right;
wire lose;
wire [4:0] bonus;
wire [1:0] winner;
counter left_counter(
.clk(clk),
.clear_b(resetn),
.enable(load_left),
.stop(stop_left),
.q(left[4:0])
);
counter right_counter(
.clk(clk),
.clear_b(resetn),
.enable(load_right),
.stop(stop_right),
.q(right[4:0])
);
AALU aalu(
.x(left[4:0]),
.y(right[4:0]),
.lose(lose),
.bonus(bonus[4:0]),
.enable(enable_aalu)
);
always @(*)
begin
if (lose == 1'b1)
same_leftright <= 1'b1;
else
same_leftright <= 1'b0;
end
always @(*)
begin
if (load_user == 1'b1)
player <= user_input_player;
end
winner_indicator wi (
.player(player[1:0]),
.computer(computer[1:0]),
.winner(winner[1:0]),
.enable(enable_winner_indicator)
);
SevenSegment display_left (
.HEXleft(HEX5[6:0]),
.HEXright(HEX4[6:0]),
.num(left[4:0])
);
SevenSegment display_right (
.HEXleft(HEX1[6:0]),
.HEXright(HEX0[6:0]),
.num(right[4:0])
);
assign score[4:0] = bonus[4:0];
assign LEDR[9:8] = winner[1:0];
assign status[1:0] = winner[1:0];
endmodule | module data(load_left, load_right, user_input_player, computer, load_user, enable_aalu,enable_winner_indicator,
clk, stop_left, stop_right, resetn, HEX0, HEX1, HEX4, HEX5, LEDR, status, same_leftright, score); |
input load_left, load_right, clk, stop_left, stop_right, resetn, enable_aalu, enable_winner_indicator, load_user;
input [1:0] user_input_player;
input [1:0] computer;
reg [1:0] player;
output [6:0] HEX0, HEX1, HEX4, HEX5;
output [9:8] LEDR;
output [4:0] score;
output [1:0] status;
output reg same_leftright;
wire [4:0] left;
wire [4:0] right;
wire lose;
wire [4:0] bonus;
wire [1:0] winner;
counter left_counter(
.clk(clk),
.clear_b(resetn),
.enable(load_left),
.stop(stop_left),
.q(left[4:0])
);
counter right_counter(
.clk(clk),
.clear_b(resetn),
.enable(load_right),
.stop(stop_right),
.q(right[4:0])
);
AALU aalu(
.x(left[4:0]),
.y(right[4:0]),
.lose(lose),
.bonus(bonus[4:0]),
.enable(enable_aalu)
);
always @(*)
begin
if (lose == 1'b1)
same_leftright <= 1'b1;
else
same_leftright <= 1'b0;
end
always @(*)
begin
if (load_user == 1'b1)
player <= user_input_player;
end
winner_indicator wi (
.player(player[1:0]),
.computer(computer[1:0]),
.winner(winner[1:0]),
.enable(enable_winner_indicator)
);
SevenSegment display_left (
.HEXleft(HEX5[6:0]),
.HEXright(HEX4[6:0]),
.num(left[4:0])
);
SevenSegment display_right (
.HEXleft(HEX1[6:0]),
.HEXright(HEX0[6:0]),
.num(right[4:0])
);
assign score[4:0] = bonus[4:0];
assign LEDR[9:8] = winner[1:0];
assign status[1:0] = winner[1:0];
endmodule | 1 |
5,283 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module control(confirm, clk, resetn, ld_user, enable_aalu, ld_left, ld_right, stop_left, stop_right, stop_user, status,
return_to_load_left, go_to_get_user, curr_state, plot, color, xOut, yOut, opponent, enable_winner_indicator);
input clk, resetn;
input confirm;
input [1:0] status;
input return_to_load_left;
input stop_left, stop_right, stop_user;
input go_to_get_user;
output reg enable_winner_indicator;
output reg ld_user, ld_left, ld_right;
output [5:0] curr_state;
reg [1:0] current_opponent;
output reg [1:0] opponent;
reg[5:0] current_state, next_state;
reg enable_counter_clear, enable_counter_fill;
output reg plot;
reg [7:0] initialX_rock = 80;
reg [6:0] initialY_rock = 40;
reg [7:0] initialX_scissors = 110;
reg [6:0] initialY_scissors = 80;
reg [7:0] initialX_paper = 50;
reg [6:0] initialY_paper = 80;
output reg [2:0] color;
output reg [7:0] xOut;
output reg [6:0] yOut;
output reg enable_aalu;
wire [3:0] counter_count_fill, counter_count_clear;
wire fill_done, clear_done;
localparam LOAD_LEFT = 5'd0,
LOAD_LEFT_WAIT = 5'd1,
LOAD_RIGHT = 5'd2,
LOAD_RIGHT_WAIT = 5'd3,
GET_USER = 5'd4,
DRAW_SQUARE_ROCK = 5'd5,
CLEAR_SCISSORS = 5'd6,
DRAW_SQUARE_PAPER = 5'd7,
CLEAR_ROCK = 5'd8,
DRAW_SQUARE_SCISSORS = 5'd9,
CLEAR_PAPER = 5'd10,
COMPARE = 5'd11;
assign curr_state[5:0] = current_state[5:0];
always@(*)
begin: state_table
case(current_state)
LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: GET_USER;
GET_USER: next_state = (confirm == 1'b1)? DRAW_SQUARE_ROCK: GET_USER;
DRAW_SQUARE_ROCK: if (fill_done == 1'b1) begin
next_state <= CLEAR_SCISSORS;
end else begin
next_state <= DRAW_SQUARE_ROCK;
end
CLEAR_SCISSORS: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_PAPER;
end else begin
next_state <= CLEAR_SCISSORS;
end
DRAW_SQUARE_PAPER: if (fill_done == 1'b1) begin
next_state <= CLEAR_ROCK;
end else begin
next_state <= DRAW_SQUARE_PAPER;
end
CLEAR_ROCK: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_SCISSORS;
end else begin
next_state <= CLEAR_ROCK;
end
DRAW_SQUARE_SCISSORS: if (fill_done == 1'b1) begin
next_state <= CLEAR_PAPER;
end else begin
next_state <= DRAW_SQUARE_SCISSORS;
end
CLEAR_PAPER: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_ROCK;
end else begin
next_state <= CLEAR_PAPER;
end
COMPARE: next_state = (status == 2'b00 || status == 2'b11)? GET_USER: LOAD_LEFT;
default: next_state = LOAD_LEFT;
endcase
end
always @(posedge clear_done) begin
if (stop_user == 1'b0) begin
opponent <= current_opponent;
end
end
always @(*)
begin: enable_signals
ld_left = 1'b0;
ld_right = 1'b0;
ld_user = 1'b0;
enable_aalu = 1'b0;
plot = 1'b0;
enable_counter_fill = 1'b0;
enable_winner_indicator = 1'b0;
case (current_state)
LOAD_LEFT: begin
ld_left <= 1'b1;
end
LOAD_RIGHT: begin
ld_right <= 1'b1;
enable_aalu <= 1'b1;
end
GET_USER: begin
ld_user <= 1'b1;
end
DRAW_SQUARE_ROCK: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_rock + counter_count_fill[1:0];
yOut <= initialY_rock + counter_count_fill[3:2];
current_opponent <= 2'b00;
end
CLEAR_SCISSORS: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_scissors + counter_count_fill[1:0];
yOut <= initialY_scissors + counter_count_fill[3:2];
current_opponent <= 2'b00;
end
DRAW_SQUARE_PAPER: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_paper + counter_count_fill[1:0];
yOut <= initialY_paper + counter_count_fill[3:2];
current_opponent <= 2'b01;
end
CLEAR_ROCK: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_rock + counter_count_fill[1:0];
yOut <= initialY_rock + counter_count_fill[3:2];
current_opponent <= 2'b01;
end
DRAW_SQUARE_SCISSORS: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_scissors + counter_count_fill[1:0];
yOut <= initialY_scissors + counter_count_fill[3:2];
current_opponent <= 2'b10;
end
CLEAR_PAPER: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_paper + counter_count_fill[1:0];
yOut <= initialY_paper + counter_count_fill[3:2];
current_opponent <= 2'b10;
end
COMPARE: begin
enable_winner_indicator <= 1'b1;
end
endcase
end
always @(posedge clk)
begin: state_FFs
if (resetn == 1'b0)
current_state <= LOAD_LEFT;
else
current_state <= next_state;
end
counter4Bit drawCount(
.clock(clk),
.reset(resetn),
.enable(enable_counter_fill),
.count(counter_count_fill[3:0]),
.count_done(fill_done)
);
endmodule | module control(confirm, clk, resetn, ld_user, enable_aalu, ld_left, ld_right, stop_left, stop_right, stop_user, status,
return_to_load_left, go_to_get_user, curr_state, plot, color, xOut, yOut, opponent, enable_winner_indicator); |
input clk, resetn;
input confirm;
input [1:0] status;
input return_to_load_left;
input stop_left, stop_right, stop_user;
input go_to_get_user;
output reg enable_winner_indicator;
output reg ld_user, ld_left, ld_right;
output [5:0] curr_state;
reg [1:0] current_opponent;
output reg [1:0] opponent;
reg[5:0] current_state, next_state;
reg enable_counter_clear, enable_counter_fill;
output reg plot;
reg [7:0] initialX_rock = 80;
reg [6:0] initialY_rock = 40;
reg [7:0] initialX_scissors = 110;
reg [6:0] initialY_scissors = 80;
reg [7:0] initialX_paper = 50;
reg [6:0] initialY_paper = 80;
output reg [2:0] color;
output reg [7:0] xOut;
output reg [6:0] yOut;
output reg enable_aalu;
wire [3:0] counter_count_fill, counter_count_clear;
wire fill_done, clear_done;
localparam LOAD_LEFT = 5'd0,
LOAD_LEFT_WAIT = 5'd1,
LOAD_RIGHT = 5'd2,
LOAD_RIGHT_WAIT = 5'd3,
GET_USER = 5'd4,
DRAW_SQUARE_ROCK = 5'd5,
CLEAR_SCISSORS = 5'd6,
DRAW_SQUARE_PAPER = 5'd7,
CLEAR_ROCK = 5'd8,
DRAW_SQUARE_SCISSORS = 5'd9,
CLEAR_PAPER = 5'd10,
COMPARE = 5'd11;
assign curr_state[5:0] = current_state[5:0];
always@(*)
begin: state_table
case(current_state)
LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: GET_USER;
GET_USER: next_state = (confirm == 1'b1)? DRAW_SQUARE_ROCK: GET_USER;
DRAW_SQUARE_ROCK: if (fill_done == 1'b1) begin
next_state <= CLEAR_SCISSORS;
end else begin
next_state <= DRAW_SQUARE_ROCK;
end
CLEAR_SCISSORS: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_PAPER;
end else begin
next_state <= CLEAR_SCISSORS;
end
DRAW_SQUARE_PAPER: if (fill_done == 1'b1) begin
next_state <= CLEAR_ROCK;
end else begin
next_state <= DRAW_SQUARE_PAPER;
end
CLEAR_ROCK: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_SCISSORS;
end else begin
next_state <= CLEAR_ROCK;
end
DRAW_SQUARE_SCISSORS: if (fill_done == 1'b1) begin
next_state <= CLEAR_PAPER;
end else begin
next_state <= DRAW_SQUARE_SCISSORS;
end
CLEAR_PAPER: if (stop_user == 1'b0 && fill_done == 1'b1) begin
next_state <= COMPARE;
end else if (stop_user == 1'b1 && fill_done == 1'b1) begin
next_state <= DRAW_SQUARE_ROCK;
end else begin
next_state <= CLEAR_PAPER;
end
COMPARE: next_state = (status == 2'b00 || status == 2'b11)? GET_USER: LOAD_LEFT;
default: next_state = LOAD_LEFT;
endcase
end
always @(posedge clear_done) begin
if (stop_user == 1'b0) begin
opponent <= current_opponent;
end
end
always @(*)
begin: enable_signals
ld_left = 1'b0;
ld_right = 1'b0;
ld_user = 1'b0;
enable_aalu = 1'b0;
plot = 1'b0;
enable_counter_fill = 1'b0;
enable_winner_indicator = 1'b0;
case (current_state)
LOAD_LEFT: begin
ld_left <= 1'b1;
end
LOAD_RIGHT: begin
ld_right <= 1'b1;
enable_aalu <= 1'b1;
end
GET_USER: begin
ld_user <= 1'b1;
end
DRAW_SQUARE_ROCK: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_rock + counter_count_fill[1:0];
yOut <= initialY_rock + counter_count_fill[3:2];
current_opponent <= 2'b00;
end
CLEAR_SCISSORS: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_scissors + counter_count_fill[1:0];
yOut <= initialY_scissors + counter_count_fill[3:2];
current_opponent <= 2'b00;
end
DRAW_SQUARE_PAPER: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_paper + counter_count_fill[1:0];
yOut <= initialY_paper + counter_count_fill[3:2];
current_opponent <= 2'b01;
end
CLEAR_ROCK: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_rock + counter_count_fill[1:0];
yOut <= initialY_rock + counter_count_fill[3:2];
current_opponent <= 2'b01;
end
DRAW_SQUARE_SCISSORS: begin
enable_counter_fill = 1'b1;
color = 3'b001;
plot = 1'b1;
xOut <= initialX_scissors + counter_count_fill[1:0];
yOut <= initialY_scissors + counter_count_fill[3:2];
current_opponent <= 2'b10;
end
CLEAR_PAPER: begin
enable_counter_fill = 1'b1;
color = 3'b000;
plot = 1'b1;
xOut <= initialX_paper + counter_count_fill[1:0];
yOut <= initialY_paper + counter_count_fill[3:2];
current_opponent <= 2'b10;
end
COMPARE: begin
enable_winner_indicator <= 1'b1;
end
endcase
end
always @(posedge clk)
begin: state_FFs
if (resetn == 1'b0)
current_state <= LOAD_LEFT;
else
current_state <= next_state;
end
counter4Bit drawCount(
.clock(clk),
.reset(resetn),
.enable(enable_counter_fill),
.count(counter_count_fill[3:0]),
.count_done(fill_done)
);
endmodule | 1 |
5,284 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module counter(clk, clear_b, stop, q, enable);
input clk;
input clear_b;
input enable;
input stop;
output reg [4:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1 && enable == 1'b1)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else
q <= q + 1'b1;
end
end
endmodule | module counter(clk, clear_b, stop, q, enable); |
input clk;
input clear_b;
input enable;
input stop;
output reg [4:0] q = 0;
always @(posedge clk)
begin
if (stop == 1'b1 && enable == 1'b1)
begin
if (clear_b == 1'b0)
q <= 0;
else if (q == 5'b10100)
q <= 0;
else
q <= q + 1'b1;
end
end
endmodule | 1 |
5,285 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module counter4Bit(clock, reset, enable, count, count_done);
input clock;
input reset, enable;
output reg [3:0] count;
output reg count_done;
always@ (posedge clock) begin
if(reset == 0) begin
count<=0;
count_done <= 1'b0;
end
else if(count == 4'b1111) begin
count <= 4'b0000;
count_done <= 1'b1;
end
else if(enable) begin
count<= count+1;
count_done <= 1'b0;
end
else
count_done <= 1'b0;
end
endmodule | module counter4Bit(clock, reset, enable, count, count_done); |
input clock;
input reset, enable;
output reg [3:0] count;
output reg count_done;
always@ (posedge clock) begin
if(reset == 0) begin
count<=0;
count_done <= 1'b0;
end
else if(count == 4'b1111) begin
count <= 4'b0000;
count_done <= 1'b1;
end
else if(enable) begin
count<= count+1;
count_done <= 1'b0;
end
else
count_done <= 1'b0;
end
endmodule | 1 |
5,286 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module consecutive_win_counter(clk, clear_b, q, enable, three_wins);
input clk;
input clear_b;
input [1:0] enable;
output reg [1:0] q = 0;
output reg three_wins = 0;
always @(negedge enable)
begin
if (enable == 2'b00)
begin
if (clear_b == 1'b0) begin
q <= 0;
three_wins <= 1'b0;
end
else if (q == 2'b11) begin
q <= 0;
three_wins <= 1'b1;
end
else
begin
q <= q + 1'b1;
three_wins <= 1'b0;
end
end
end
endmodule | module consecutive_win_counter(clk, clear_b, q, enable, three_wins); |
input clk;
input clear_b;
input [1:0] enable;
output reg [1:0] q = 0;
output reg three_wins = 0;
always @(negedge enable)
begin
if (enable == 2'b00)
begin
if (clear_b == 1'b0) begin
q <= 0;
three_wins <= 1'b0;
end
else if (q == 2'b11) begin
q <= 0;
three_wins <= 1'b1;
end
else
begin
q <= q + 1'b1;
three_wins <= 1'b0;
end
end
end
endmodule | 1 |
5,287 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module d_ff(reg_input, reg_output, clk, reset);
input reg_input;
output reg reg_output;
input clk;
input reset;
always @(posedge clk)
begin
if (reset == 1'b1)
reg_output <= 1'b0;
else
if (reg_input >= reg_output)
reg_output <= reg_input;
end
endmodule | module d_ff(reg_input, reg_output, clk, reset); |
input reg_input;
output reg reg_output;
input clk;
input reset;
always @(posedge clk)
begin
if (reset == 1'b1)
reg_output <= 1'b0;
else
if (reg_input >= reg_output)
reg_output <= reg_input;
end
endmodule | 1 |
5,288 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module AALU(x, y, lose, bonus, enable);
input [4:0] x;
input [4:0] y;
input enable;
output [4:0] bonus;
output lose;
wire [4:0] greater;
wire [4:0] lower;
comparator comp(
.x(x[4:0]),
.y(y[4:0]),
.greater(greater[4:0]),
.enable(enable),
.lower(lower[4:0]),
.same(lose)
);
subtractor sub(
.operandone(greater[4:0]),
.operandtwo(lower[4:0]),
.enable(enable),
.result(bonus[4:0])
);
endmodule | module AALU(x, y, lose, bonus, enable); |
input [4:0] x;
input [4:0] y;
input enable;
output [4:0] bonus;
output lose;
wire [4:0] greater;
wire [4:0] lower;
comparator comp(
.x(x[4:0]),
.y(y[4:0]),
.greater(greater[4:0]),
.enable(enable),
.lower(lower[4:0]),
.same(lose)
);
subtractor sub(
.operandone(greater[4:0]),
.operandtwo(lower[4:0]),
.enable(enable),
.result(bonus[4:0])
);
endmodule | 1 |
5,289 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module comparator(x, y, greater, lower, same, enable);
input [4:0] x;
input [4:0] y;
output reg [4:0] greater;
input enable;
output reg [4:0] lower;
output reg same;
always @(*)
begin
if (enable == 1'b1)
if (x > y)
begin
greater <= x;
lower <= y;
same <= 1'b0;
end
else if (x < y)
begin
greater <= y;
lower <= x;
same <= 1'b0;
end
else
begin
greater <= 5'b00000;
lower <= 5'b00000;
same <= 1'b1;
end
end
endmodule | module comparator(x, y, greater, lower, same, enable); |
input [4:0] x;
input [4:0] y;
output reg [4:0] greater;
input enable;
output reg [4:0] lower;
output reg same;
always @(*)
begin
if (enable == 1'b1)
if (x > y)
begin
greater <= x;
lower <= y;
same <= 1'b0;
end
else if (x < y)
begin
greater <= y;
lower <= x;
same <= 1'b0;
end
else
begin
greater <= 5'b00000;
lower <= 5'b00000;
same <= 1'b1;
end
end
endmodule | 1 |
5,290 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module subtractor(operandone, operandtwo, result, enable);
input [4:0] operandone;
input [4:0] operandtwo;
input enable;
output reg [4:0] result;
always@(*) begin
if (enable == 1'b1)
result <= operandone - operandtwo;
end
endmodule | module subtractor(operandone, operandtwo, result, enable); |
input [4:0] operandone;
input [4:0] operandtwo;
input enable;
output reg [4:0] result;
always@(*) begin
if (enable == 1'b1)
result <= operandone - operandtwo;
end
endmodule | 1 |
5,291 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module SevenSegment(HEXleft, HEXright, num);
output reg [6:0] HEXleft, HEXright;
input [4:0] num;
always @(num) begin
case (num)
5'b00000: begin
HEXleft = 7'b100_0000;
HEXright = 7'b100_0000;
end
5'b00001: begin
HEXleft = 7'b100_0000;
HEXright = 7'b111_1001;
end
5'b00010: begin
HEXleft = 7'b100_0000;
HEXright = 7'b010_0100;
end
5'b00011: begin
HEXleft = 7'b100_0000;
HEXright = 7'b011_0000;
end
5'b0100: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_1001;
end
5'b00101: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_0010;
end
5'b00110: begin
HEXleft = 7'b100_0000;
HEXright = 7'b000_0010;
end
5'b00111: begin
HEXleft = 7'b100_0000;
HEXright = 7'b111_1000;
end
5'b01000: begin
HEXleft = 7'b100_0000;
HEXright = 7'b000_0000;
end
5'b01001: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_1000;
end
5'b01010: begin
HEXleft = 7'b111_1001;
HEXright = 7'b100_0000;
end
5'b01011: begin
HEXleft = 7'b111_1001;
HEXright = 7'b111_1001;
end
5'b01100: begin
HEXleft = 7'b111_1001;
HEXright = 7'b010_0100;
end
5'b01101: begin
HEXleft = 7'b111_1001;
HEXright = 7'b011_0000;
end
5'b01110: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_1001;
end
5'b01111: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_0010;
end
5'b10000: begin
HEXleft = 7'b111_1001;
HEXright = 7'b000_0010;
end
5'b10001: begin
HEXleft = 7'b111_1001;
HEXright = 7'b111_1000;
end
5'b10010: begin
HEXleft = 7'b111_1001;
HEXright = 7'b000_0000;
end
5'b10011: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_1000;
end
5'b10100: begin
HEXleft = 7'b010_0100;
HEXright = 7'b100_0000;
end
default: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
endcase
end
endmodule | module SevenSegment(HEXleft, HEXright, num); |
output reg [6:0] HEXleft, HEXright;
input [4:0] num;
always @(num) begin
case (num)
5'b00000: begin
HEXleft = 7'b100_0000;
HEXright = 7'b100_0000;
end
5'b00001: begin
HEXleft = 7'b100_0000;
HEXright = 7'b111_1001;
end
5'b00010: begin
HEXleft = 7'b100_0000;
HEXright = 7'b010_0100;
end
5'b00011: begin
HEXleft = 7'b100_0000;
HEXright = 7'b011_0000;
end
5'b0100: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_1001;
end
5'b00101: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_0010;
end
5'b00110: begin
HEXleft = 7'b100_0000;
HEXright = 7'b000_0010;
end
5'b00111: begin
HEXleft = 7'b100_0000;
HEXright = 7'b111_1000;
end
5'b01000: begin
HEXleft = 7'b100_0000;
HEXright = 7'b000_0000;
end
5'b01001: begin
HEXleft = 7'b100_0000;
HEXright = 7'b001_1000;
end
5'b01010: begin
HEXleft = 7'b111_1001;
HEXright = 7'b100_0000;
end
5'b01011: begin
HEXleft = 7'b111_1001;
HEXright = 7'b111_1001;
end
5'b01100: begin
HEXleft = 7'b111_1001;
HEXright = 7'b010_0100;
end
5'b01101: begin
HEXleft = 7'b111_1001;
HEXright = 7'b011_0000;
end
5'b01110: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_1001;
end
5'b01111: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_0010;
end
5'b10000: begin
HEXleft = 7'b111_1001;
HEXright = 7'b000_0010;
end
5'b10001: begin
HEXleft = 7'b111_1001;
HEXright = 7'b111_1000;
end
5'b10010: begin
HEXleft = 7'b111_1001;
HEXright = 7'b000_0000;
end
5'b10011: begin
HEXleft = 7'b111_1001;
HEXright = 7'b001_1000;
end
5'b10100: begin
HEXleft = 7'b010_0100;
HEXright = 7'b100_0000;
end
default: begin
HEXleft = 7'b0000000;
HEXright = 7'b0000000;
end
endcase
end
endmodule | 1 |
5,292 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module RPSGame(player, clk, stop, clear, winner, enable);
input [1:0] player;
input clk;
input enable;
input stop;
input clear;
output [1:0] winner;
wire [1:0] computer;
RPScounter rps(
.clk(clk),
.clear_b(clear),
.stop(stop),
.enable(enable),
.q(computer[1:0])
);
winner_indicator wi (
.player(player),
.computer(computer[1:0]),
.stop(stop),
.winner(winner)
);
endmodule | module RPSGame(player, clk, stop, clear, winner, enable); |
input [1:0] player;
input clk;
input enable;
input stop;
input clear;
output [1:0] winner;
wire [1:0] computer;
RPScounter rps(
.clk(clk),
.clear_b(clear),
.stop(stop),
.enable(enable),
.q(computer[1:0])
);
winner_indicator wi (
.player(player),
.computer(computer[1:0]),
.stop(stop),
.winner(winner)
);
endmodule | 1 |
5,293 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module winner_indicator(player, computer, winner, enable);
input [1:0] player;
input [1:0] computer;
input enable;
output reg [1:0] winner;
always @(*)
begin
if (enable == 1'b1)
if (player == 2'b00 && computer == 2'b00)
winner <= 2'b11;
else if (player == 2'b00 && computer == 2'b01)
winner <= 2'b01;
else if (player == 2'b00 && computer == 2'b10)
winner <= 2'b00;
else if (player == 2'b01 && computer == 2'b01)
winner <= 2'b11;
else if (player == 2'b01 && computer == 2'b10)
winner <= 2'b01;
else if (player == 2'b01 && computer == 2'b00)
winner <= 2'b00;
else if (player == 2'b10 && computer == 2'b10)
winner <= 2'b11;
else if (player == 2'b10 && computer == 2'b00)
winner <= 2'b01;
else
winner <= 2'b00;
else
winner <= 2'b11;
end
endmodule | module winner_indicator(player, computer, winner, enable); |
input [1:0] player;
input [1:0] computer;
input enable;
output reg [1:0] winner;
always @(*)
begin
if (enable == 1'b1)
if (player == 2'b00 && computer == 2'b00)
winner <= 2'b11;
else if (player == 2'b00 && computer == 2'b01)
winner <= 2'b01;
else if (player == 2'b00 && computer == 2'b10)
winner <= 2'b00;
else if (player == 2'b01 && computer == 2'b01)
winner <= 2'b11;
else if (player == 2'b01 && computer == 2'b10)
winner <= 2'b01;
else if (player == 2'b01 && computer == 2'b00)
winner <= 2'b00;
else if (player == 2'b10 && computer == 2'b10)
winner <= 2'b11;
else if (player == 2'b10 && computer == 2'b00)
winner <= 2'b01;
else
winner <= 2'b00;
else
winner <= 2'b11;
end
endmodule | 1 |
5,294 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module ratedivider(clear_b, clk, out);
input clear_b;
input clk;
output out;
reg [30:0] q;
reg [30:0] t = 125000;
assign out = (q == 0) ? 1 : 0;
always @(posedge clk)
begin
if (clear_b == 1'b0)
q <= t;
else if (q == 1'b0)
q <= t;
else
q <= q - 1'b1;
end
endmodule | module ratedivider(clear_b, clk, out); |
input clear_b;
input clk;
output out;
reg [30:0] q;
reg [30:0] t = 125000;
assign out = (q == 0) ? 1 : 0;
always @(posedge clk)
begin
if (clear_b == 1'b0)
q <= t;
else if (q == 1'b0)
q <= t;
else
q <= q - 1'b1;
end
endmodule | 1 |
5,295 | data/full_repos/permissive/113780415/src/top_test.v | 113,780,415 | top_test.v | v | 882 | 121 | [] | [] | [] | null | line:1736: before: "&&" | null | 1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n always @(posedge clk && enable == 1'b1)\n ^~\n%Error: Cannot continue\n" | 5,694 | module | module RPScounter(clk, clear_b, stop, q, enable);
input clk;
input clear_b;
input stop;
input enable;
output reg [1:0] q = 0;
always @(posedge clk && enable == 1'b1)
begin
if (stop == 1'b1)
if (clear_b == 1'b0)
q <= 0;
else if (q == 2'b10)
q <= 0;
else
q <= q + 1'b1;
else
q <= q;
end
endmodule | module RPScounter(clk, clear_b, stop, q, enable); |
input clk;
input clear_b;
input stop;
input enable;
output reg [1:0] q = 0;
always @(posedge clk && enable == 1'b1)
begin
if (stop == 1'b1)
if (clear_b == 1'b0)
q <= 0;
else if (q == 2'b10)
q <= 0;
else
q <= q + 1'b1;
else
q <= q;
end
endmodule | 1 |
5,304 | data/full_repos/permissive/113839829/Attempt/Chapter 4/id_ex.v | 113,839,829 | id_ex.v | v | 57 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.sv\n 4,data/full_repos/permissive/113839829\n 4,data/full_repos/permissive/113839829.v\n 4,data/full_repos/permissive/113839829.sv\n obj_dir/4,data/full_repos/permissive/113839829\n obj_dir/4,data/full_repos/permissive/113839829.v\n obj_dir/4,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Attempt/Chapter\n%Error: Cannot find file containing module: 4/id_ex.v\n%Error: Exiting due to 3 error(s)\n' | 5,710 | module | module id_ex(
input wire clk,
input wire rst,
input wire [`AluOpBus] id_aluop,
input wire [`AluSelBus] id_alusel,
input wire [`RegBus] id_reg1,
input wire [`RegBus] id_reg2,
input wire [`RegAddrBus] id_wd,
input wire id_wreg,
output reg [`AluOpBus] ex_aluop,
output reg [`AluSelBus] ex_alusel,
output reg [`RegBus] ex_reg1,
output reg [`RegBus] ex_reg2,
output reg [`RegAddrBus] ex_wd,
output reg ex_wreg
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
end
else
begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
end
end
endmodule | module id_ex(
input wire clk,
input wire rst,
input wire [`AluOpBus] id_aluop,
input wire [`AluSelBus] id_alusel,
input wire [`RegBus] id_reg1,
input wire [`RegBus] id_reg2,
input wire [`RegAddrBus] id_wd,
input wire id_wreg,
output reg [`AluOpBus] ex_aluop,
output reg [`AluSelBus] ex_alusel,
output reg [`RegBus] ex_reg1,
output reg [`RegBus] ex_reg2,
output reg [`RegAddrBus] ex_wd,
output reg ex_wreg
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
end
else
begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
end
end
endmodule | 48 |
5,305 | data/full_repos/permissive/113839829/Attempt/Chapter 4/openmips_min_sopc.v | 113,839,829 | openmips_min_sopc.v | v | 40 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.sv\n 4,data/full_repos/permissive/113839829\n 4,data/full_repos/permissive/113839829.v\n 4,data/full_repos/permissive/113839829.sv\n obj_dir/4,data/full_repos/permissive/113839829\n obj_dir/4,data/full_repos/permissive/113839829.v\n obj_dir/4,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Attempt/Chapter\n%Error: Cannot find file containing module: 4/openmips_min_sopc.v\n%Error: Exiting due to 3 error(s)\n' | 5,716 | module | module openmips_min_sopc(
input wire clk,
input wire rst
);
wire [`InstAddrBus] inst_addr;
wire [`InstBus] inst;
wire rom_ce;
openmips openmips0(
.clk(clk),
.rst(rst),
.rom_addr_o(inst_addr),
.rom_data_i(inst),
.rom_ce_o(rom_ce)
);
inst_rom inst_rom0(
.addr(inst_addr),
.inst(inst),
.ce(rom_ce)
);
endmodule | module openmips_min_sopc(
input wire clk,
input wire rst
); |
wire [`InstAddrBus] inst_addr;
wire [`InstBus] inst;
wire rom_ce;
openmips openmips0(
.clk(clk),
.rst(rst),
.rom_addr_o(inst_addr),
.rom_data_i(inst),
.rom_ce_o(rom_ce)
);
inst_rom inst_rom0(
.addr(inst_addr),
.inst(inst),
.ce(rom_ce)
);
endmodule | 48 |
5,307 | data/full_repos/permissive/113839829/Attempt/Chapter 4/regfile.v | 113,839,829 | regfile.v | v | 92 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.sv\n 4,data/full_repos/permissive/113839829\n 4,data/full_repos/permissive/113839829.v\n 4,data/full_repos/permissive/113839829.sv\n obj_dir/4,data/full_repos/permissive/113839829\n obj_dir/4,data/full_repos/permissive/113839829.v\n obj_dir/4,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Attempt/Chapter\n%Error: Cannot find file containing module: 4/regfile.v\n%Error: Exiting due to 3 error(s)\n' | 5,719 | module | module regfile(
input wire clk,
input wire rst,
input wire we,
input wire [`RegAddrBus] waddr,
input wire [`RegBus] wdata,
input wire re1,
input wire [`RegAddrBus] raddr1,
output reg [`RegBus] rdata1,
input wire re2,
input wire [`RegAddrBus] raddr2,
output reg [`RegBus] rdata2
);
reg [`RegBus] regs[0:`RegNum-1];
always @ (posedge clk)
begin
if (rst == `RstDisable)
if((we == `WriteEnable) && (waddr != `RegNumLog2'h0))
begin
regs[waddr] <= wdata;
$display(wdata);
end
end
`define READ(re,raddr,rdata) \
always @ (*) \
begin \
if(rst == `RstEnable) \
rdata <= `ZeroWord; \
else if(raddr == `RegNumLog2'h0) \
rdata <= `ZeroWord; \
else if((raddr == waddr) && (we == `WriteEnable) \
&& (re == `ReadEnable)) \
rdata <= wdata; \
else if(re == `ReadEnable) \
rdata <= regs[raddr]; \
else \
rdata <= `ZeroWord; \
end
`READ(re1,raddr1,rdata1)
`READ(re2,raddr2,rdata2)
endmodule | module regfile(
input wire clk,
input wire rst,
input wire we,
input wire [`RegAddrBus] waddr,
input wire [`RegBus] wdata,
input wire re1,
input wire [`RegAddrBus] raddr1,
output reg [`RegBus] rdata1,
input wire re2,
input wire [`RegAddrBus] raddr2,
output reg [`RegBus] rdata2
); |
reg [`RegBus] regs[0:`RegNum-1];
always @ (posedge clk)
begin
if (rst == `RstDisable)
if((we == `WriteEnable) && (waddr != `RegNumLog2'h0))
begin
regs[waddr] <= wdata;
$display(wdata);
end
end
`define READ(re,raddr,rdata) \
always @ (*) \
begin \
if(rst == `RstEnable) \
rdata <= `ZeroWord; \
else if(raddr == `RegNumLog2'h0) \
rdata <= `ZeroWord; \
else if((raddr == waddr) && (we == `WriteEnable) \
&& (re == `ReadEnable)) \
rdata <= wdata; \
else if(re == `ReadEnable) \
rdata <= regs[raddr]; \
else \
rdata <= `ZeroWord; \
end
`READ(re1,raddr1,rdata1)
`READ(re2,raddr2,rdata2)
endmodule | 48 |
5,309 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter10/data_ram.v | 113,839,829 | data_ram.v | v | 84 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xca in position 1818: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter10,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter10/data_ram.v\n%Error: Exiting due to 3 error(s)\n' | 5,736 | module | module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o
);
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
end else if(we == `WriteEnable) begin
if (sel[3] == 1'b1) begin
data_mem3[addr[`DataMemNumLog2+1:2]] <= data_i[31:24];
end
if (sel[2] == 1'b1) begin
data_mem2[addr[`DataMemNumLog2+1:2]] <= data_i[23:16];
end
if (sel[1] == 1'b1) begin
data_mem1[addr[`DataMemNumLog2+1:2]] <= data_i[15:8];
end
if (sel[0] == 1'b1) begin
data_mem0[addr[`DataMemNumLog2+1:2]] <= data_i[7:0];
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem3[addr[`DataMemNumLog2+1:2]],
data_mem2[addr[`DataMemNumLog2+1:2]],
data_mem1[addr[`DataMemNumLog2+1:2]],
data_mem0[addr[`DataMemNumLog2+1:2]]};
end else begin
data_o <= `ZeroWord;
end
end
endmodule | module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o
); |
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
end else if(we == `WriteEnable) begin
if (sel[3] == 1'b1) begin
data_mem3[addr[`DataMemNumLog2+1:2]] <= data_i[31:24];
end
if (sel[2] == 1'b1) begin
data_mem2[addr[`DataMemNumLog2+1:2]] <= data_i[23:16];
end
if (sel[1] == 1'b1) begin
data_mem1[addr[`DataMemNumLog2+1:2]] <= data_i[15:8];
end
if (sel[0] == 1'b1) begin
data_mem0[addr[`DataMemNumLog2+1:2]] <= data_i[7:0];
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem3[addr[`DataMemNumLog2+1:2]],
data_mem2[addr[`DataMemNumLog2+1:2]],
data_mem1[addr[`DataMemNumLog2+1:2]],
data_mem0[addr[`DataMemNumLog2+1:2]]};
end else begin
data_o <= `ZeroWord;
end
end
endmodule | 48 |
5,314 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter11/mem_wb.v | 113,839,829 | mem_wb.v | v | 129 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xbd in position 1820: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter11,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter11/mem_wb.v\n%Error: Exiting due to 3 error(s)\n' | 5,768 | module | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire flush,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value,
output reg wb_cp0_reg_we,
output reg[4:0] wb_cp0_reg_write_addr,
output reg[`RegBus] wb_cp0_reg_data
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(flush == 1'b1 ) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
wb_cp0_reg_we <= mem_cp0_reg_we;
wb_cp0_reg_write_addr <= mem_cp0_reg_write_addr;
wb_cp0_reg_data <= mem_cp0_reg_data;
end
end
endmodule | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire flush,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value,
output reg wb_cp0_reg_we,
output reg[4:0] wb_cp0_reg_write_addr,
output reg[`RegBus] wb_cp0_reg_data
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(flush == 1'b1 ) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
wb_cp0_reg_we <= mem_cp0_reg_we;
wb_cp0_reg_write_addr <= mem_cp0_reg_write_addr;
wb_cp0_reg_data <= mem_cp0_reg_data;
end
end
endmodule | 48 |
5,319 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter13/flash/wb_flash.v | 113,839,829 | wb_flash.v | v | 118 | 73 | [] | ['general public license', 'free software foundation'] | [] | [(33, 117)] | null | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter13/flash,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/flash/wb_flash.v\n%Error: Exiting due to 3 error(s)\n' | 5,792 | module | module flash_top(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
wb_stb_i, wb_cyc_i, wb_ack_o,
flash_adr_o, flash_dat_i, flash_rst,
flash_oe, flash_ce, flash_we
);
parameter aw = 19;
parameter dw = 32;
parameter ws = 4'h3;
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
output reg [dw-1:0] wb_dat_o;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output reg wb_ack_o;
output reg [31:0] flash_adr_o;
input [7:0] flash_dat_i;
output flash_rst;
output flash_oe;
output flash_ce;
output flash_we;
reg [3:0] waitstate;
wire [1:0] adr_low;
wire wb_acc = wb_cyc_i & wb_stb_i;
wire wb_wr = wb_acc & wb_we_i;
wire wb_rd = wb_acc & !wb_we_i;
always @(posedge wb_clk_i) begin
if( wb_rst_i == 1'b1 ) begin
waitstate <= 4'h0;
wb_ack_o <= 1'b0;
end else if(wb_acc == 1'b0) begin
waitstate <= 4'h0;
wb_ack_o <= 1'b0;
wb_dat_o <= 32'h00000000;
end else if(waitstate == 4'h0) begin
wb_ack_o <= 1'b0;
if(wb_acc) begin
waitstate <= waitstate + 4'h1;
end
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b00};
end else begin
waitstate <= waitstate + 4'h1;
if(waitstate == 4'h3) begin
wb_dat_o[31:24] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b01};
end else if(waitstate == 4'h6) begin
wb_dat_o[23:16] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b10};
end else if(waitstate == 4'h9) begin
wb_dat_o[15:8] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b11};
end else if(waitstate == 4'hc) begin
wb_dat_o[7:0] <= flash_dat_i;
wb_ack_o <= 1'b1;
end else if(waitstate == 4'hd) begin
wb_ack_o <= 1'b0;
waitstate <= 4'h0;
end
end
end
assign flash_ce = !wb_acc;
assign flash_we = 1'b1;
assign flash_oe = !wb_rd;
assign flash_rst = !wb_rst_i;
endmodule | module flash_top(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
wb_stb_i, wb_cyc_i, wb_ack_o,
flash_adr_o, flash_dat_i, flash_rst,
flash_oe, flash_ce, flash_we
); |
parameter aw = 19;
parameter dw = 32;
parameter ws = 4'h3;
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
output reg [dw-1:0] wb_dat_o;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output reg wb_ack_o;
output reg [31:0] flash_adr_o;
input [7:0] flash_dat_i;
output flash_rst;
output flash_oe;
output flash_ce;
output flash_we;
reg [3:0] waitstate;
wire [1:0] adr_low;
wire wb_acc = wb_cyc_i & wb_stb_i;
wire wb_wr = wb_acc & wb_we_i;
wire wb_rd = wb_acc & !wb_we_i;
always @(posedge wb_clk_i) begin
if( wb_rst_i == 1'b1 ) begin
waitstate <= 4'h0;
wb_ack_o <= 1'b0;
end else if(wb_acc == 1'b0) begin
waitstate <= 4'h0;
wb_ack_o <= 1'b0;
wb_dat_o <= 32'h00000000;
end else if(waitstate == 4'h0) begin
wb_ack_o <= 1'b0;
if(wb_acc) begin
waitstate <= waitstate + 4'h1;
end
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b00};
end else begin
waitstate <= waitstate + 4'h1;
if(waitstate == 4'h3) begin
wb_dat_o[31:24] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b01};
end else if(waitstate == 4'h6) begin
wb_dat_o[23:16] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b10};
end else if(waitstate == 4'h9) begin
wb_dat_o[15:8] <= flash_dat_i;
flash_adr_o <= {10'b0000000000,wb_adr_i[21:2],2'b11};
end else if(waitstate == 4'hc) begin
wb_dat_o[7:0] <= flash_dat_i;
wb_ack_o <= 1'b1;
end else if(waitstate == 4'hd) begin
wb_ack_o <= 1'b0;
waitstate <= 4'h0;
end
end
end
assign flash_ce = !wb_acc;
assign flash_we = 1'b1;
assign flash_oe = !wb_rd;
assign flash_rst = !wb_rst_i;
endmodule | 48 |
5,328 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter13/sdram_controller/sdrc_bs_convert.v | 113,839,829 | sdrc_bs_convert.v | v | 229 | 101 | [] | [] | [] | [(82, 258)] | null | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/sdram_controller/sdrc_bs_convert.v\n%Error: Exiting due to 3 error(s)\n' | 5,815 | module | module sdrc_bs_convert (
clk ,
reset_n ,
sdr_width ,
x2a_rdstart ,
x2a_wrstart ,
x2a_rdlast ,
x2a_wrlast ,
x2a_rddt ,
x2a_rdok ,
a2x_wrdt ,
a2x_wren_n ,
x2a_wrnext ,
app_wr_data ,
app_wr_en_n ,
app_wr_next ,
app_last_wr ,
app_rd_data ,
app_rd_valid ,
app_last_rd
);
parameter APP_AW = 30;
parameter APP_DW = 32;
parameter APP_BW = 4;
parameter SDR_DW = 16;
parameter SDR_BW = 2;
input clk ;
input reset_n ;
input [1:0] sdr_width ;
input x2a_rdstart ;
input x2a_rdlast ;
input [SDR_DW-1:0] x2a_rddt ;
input x2a_rdok ;
input x2a_wrstart ;
input x2a_wrlast ;
input x2a_wrnext ;
output [SDR_DW-1:0] a2x_wrdt ;
output [SDR_BW-1:0] a2x_wren_n ;
input [APP_DW-1:0] app_wr_data ;
input [APP_BW-1:0] app_wr_en_n ;
output app_wr_next ;
output app_last_wr ;
output [APP_DW-1:0] app_rd_data ;
output app_rd_valid ;
output app_last_rd ;
reg [APP_DW-1:0] app_rd_data ;
reg app_rd_valid ;
reg [SDR_DW-1:0] a2x_wrdt ;
reg [SDR_BW-1:0] a2x_wren_n ;
reg app_wr_next ;
reg [23:0] saved_rd_data ;
reg [1:0] rd_xfr_count ;
reg [1:0] wr_xfr_count ;
assign app_last_wr = x2a_wrlast;
assign app_last_rd = x2a_rdlast;
always @(*) begin
if(sdr_width == 2'b00)
begin
a2x_wrdt = app_wr_data;
a2x_wren_n = app_wr_en_n;
app_wr_next = x2a_wrnext;
app_rd_data = x2a_rddt;
app_rd_valid = x2a_rdok;
end
else if(sdr_width == 2'b01)
begin
app_wr_next = (x2a_wrnext & wr_xfr_count[0]);
app_rd_valid = (x2a_rdok & rd_xfr_count[0]);
if(wr_xfr_count[0] == 1'b1)
begin
a2x_wren_n = app_wr_en_n[3:2];
a2x_wrdt = app_wr_data[31:16];
end
else
begin
a2x_wren_n = app_wr_en_n[1:0];
a2x_wrdt = app_wr_data[15:0];
end
app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
end else
begin
app_wr_next = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
app_rd_valid = (x2a_rdok & (rd_xfr_count[1:0]== 2'b11));
if(wr_xfr_count[1:0] == 2'b11)
begin
a2x_wren_n = app_wr_en_n[3];
a2x_wrdt = app_wr_data[31:24];
end
else if(wr_xfr_count[1:0] == 2'b10)
begin
a2x_wren_n = app_wr_en_n[2];
a2x_wrdt = app_wr_data[23:16];
end
else if(wr_xfr_count[1:0] == 2'b01)
begin
a2x_wren_n = app_wr_en_n[1];
a2x_wrdt = app_wr_data[15:8];
end
else begin
a2x_wren_n = app_wr_en_n[0];
a2x_wrdt = app_wr_data[7:0];
end
app_rd_data = {x2a_rddt,saved_rd_data[23:0]};
end
end
always @(posedge clk)
begin
if(!reset_n)
begin
rd_xfr_count <= 8'b0;
wr_xfr_count <= 8'b0;
saved_rd_data <= 24'h0;
end
else begin
if(x2a_wrlast) begin
wr_xfr_count <= 0;
end
else if(x2a_wrnext) begin
wr_xfr_count <= wr_xfr_count + 1'b1;
end
if(x2a_rdlast) begin
rd_xfr_count <= 0;
end
else if(x2a_rdok) begin
rd_xfr_count <= rd_xfr_count + 1'b1;
end
if(x2a_rdok) begin
if(sdr_width == 2'b01)
saved_rd_data[15:0] <= x2a_rddt;
else begin
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
end
end
end
end
endmodule | module sdrc_bs_convert (
clk ,
reset_n ,
sdr_width ,
x2a_rdstart ,
x2a_wrstart ,
x2a_rdlast ,
x2a_wrlast ,
x2a_rddt ,
x2a_rdok ,
a2x_wrdt ,
a2x_wren_n ,
x2a_wrnext ,
app_wr_data ,
app_wr_en_n ,
app_wr_next ,
app_last_wr ,
app_rd_data ,
app_rd_valid ,
app_last_rd
); |
parameter APP_AW = 30;
parameter APP_DW = 32;
parameter APP_BW = 4;
parameter SDR_DW = 16;
parameter SDR_BW = 2;
input clk ;
input reset_n ;
input [1:0] sdr_width ;
input x2a_rdstart ;
input x2a_rdlast ;
input [SDR_DW-1:0] x2a_rddt ;
input x2a_rdok ;
input x2a_wrstart ;
input x2a_wrlast ;
input x2a_wrnext ;
output [SDR_DW-1:0] a2x_wrdt ;
output [SDR_BW-1:0] a2x_wren_n ;
input [APP_DW-1:0] app_wr_data ;
input [APP_BW-1:0] app_wr_en_n ;
output app_wr_next ;
output app_last_wr ;
output [APP_DW-1:0] app_rd_data ;
output app_rd_valid ;
output app_last_rd ;
reg [APP_DW-1:0] app_rd_data ;
reg app_rd_valid ;
reg [SDR_DW-1:0] a2x_wrdt ;
reg [SDR_BW-1:0] a2x_wren_n ;
reg app_wr_next ;
reg [23:0] saved_rd_data ;
reg [1:0] rd_xfr_count ;
reg [1:0] wr_xfr_count ;
assign app_last_wr = x2a_wrlast;
assign app_last_rd = x2a_rdlast;
always @(*) begin
if(sdr_width == 2'b00)
begin
a2x_wrdt = app_wr_data;
a2x_wren_n = app_wr_en_n;
app_wr_next = x2a_wrnext;
app_rd_data = x2a_rddt;
app_rd_valid = x2a_rdok;
end
else if(sdr_width == 2'b01)
begin
app_wr_next = (x2a_wrnext & wr_xfr_count[0]);
app_rd_valid = (x2a_rdok & rd_xfr_count[0]);
if(wr_xfr_count[0] == 1'b1)
begin
a2x_wren_n = app_wr_en_n[3:2];
a2x_wrdt = app_wr_data[31:16];
end
else
begin
a2x_wren_n = app_wr_en_n[1:0];
a2x_wrdt = app_wr_data[15:0];
end
app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
end else
begin
app_wr_next = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
app_rd_valid = (x2a_rdok & (rd_xfr_count[1:0]== 2'b11));
if(wr_xfr_count[1:0] == 2'b11)
begin
a2x_wren_n = app_wr_en_n[3];
a2x_wrdt = app_wr_data[31:24];
end
else if(wr_xfr_count[1:0] == 2'b10)
begin
a2x_wren_n = app_wr_en_n[2];
a2x_wrdt = app_wr_data[23:16];
end
else if(wr_xfr_count[1:0] == 2'b01)
begin
a2x_wren_n = app_wr_en_n[1];
a2x_wrdt = app_wr_data[15:8];
end
else begin
a2x_wren_n = app_wr_en_n[0];
a2x_wrdt = app_wr_data[7:0];
end
app_rd_data = {x2a_rddt,saved_rd_data[23:0]};
end
end
always @(posedge clk)
begin
if(!reset_n)
begin
rd_xfr_count <= 8'b0;
wr_xfr_count <= 8'b0;
saved_rd_data <= 24'h0;
end
else begin
if(x2a_wrlast) begin
wr_xfr_count <= 0;
end
else if(x2a_wrnext) begin
wr_xfr_count <= wr_xfr_count + 1'b1;
end
if(x2a_rdlast) begin
rd_xfr_count <= 0;
end
else if(x2a_rdok) begin
rd_xfr_count <= rd_xfr_count + 1'b1;
end
if(x2a_rdok) begin
if(sdr_width == 2'b01)
saved_rd_data[15:0] <= x2a_rddt;
else begin
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
end
end
end
end
endmodule | 48 |
5,329 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter13/sdram_controller/sdrc_req_gen.v | 113,839,829 | sdrc_req_gen.v | v | 341 | 116 | [] | [] | [] | [(109, 370)] | null | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter13/sdram_controller,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/sdram_controller/sdrc_req_gen.v\n%Error: Exiting due to 3 error(s)\n' | 5,818 | module | module sdrc_req_gen (clk,
reset_n,
cfg_colbits,
sdr_width,
req,
req_id,
req_addr,
req_len,
req_wrap,
req_wr_n,
req_ack,
r2x_idle,
r2b_req,
r2b_req_id,
r2b_start,
r2b_last,
r2b_wrap,
r2b_ba,
r2b_raddr,
r2b_caddr,
r2b_len,
r2b_write,
b2r_ack,
b2r_arb_ok
);
parameter APP_AW = 26;
parameter APP_DW = 32;
parameter APP_BW = 4;
parameter APP_RW = 9;
parameter SDR_DW = 16;
parameter SDR_BW = 2;
input clk ;
input reset_n ;
input [1:0] cfg_colbits ;
input req ;
input [`SDR_REQ_ID_W-1:0] req_id ;
input [APP_AW-1:0] req_addr ;
input [APP_RW-1:0] req_len ;
input req_wr_n ;
input req_wrap ;
output req_ack ;
output r2x_idle ;
output r2b_req ;
output r2b_start ;
output r2b_last ;
output r2b_write ;
output r2b_wrap ;
output [`SDR_REQ_ID_W-1:0] r2b_req_id;
output [1:0] r2b_ba ;
output [12:0] r2b_raddr ;
output [12:0] r2b_caddr ;
output [`REQ_BW-1:0] r2b_len ;
input b2r_ack ;
input b2r_arb_ok ;
input [1:0] sdr_width;
`define REQ_IDLE 2'b00
`define REQ_ACTIVE 2'b01
`define REQ_PAGE_WRAP 2'b10
reg [1:0] req_st, next_req_st;
reg r2x_idle, req_ack, r2b_req, r2b_start,
r2b_write, req_idle, req_ld, lcl_wrap;
reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
reg [`REQ_BW-1:0] lcl_req_len;
wire r2b_last, page_ovflw;
reg page_ovflw_r;
wire [`REQ_BW-1:0] r2b_len, next_req_len;
wire [12:0] max_r2b_len;
reg [12:0] max_r2b_len_r;
reg [1:0] r2b_ba;
reg [12:0] r2b_raddr;
reg [12:0] r2b_caddr;
reg [APP_AW-1:0] curr_sdr_addr ;
wire [APP_AW-1:0] next_sdr_addr ;
reg [APP_AW:0] req_addr_int;
reg [APP_RW-1:0] req_len_int;
always @(*) begin
if(sdr_width == 2'b00) begin
req_addr_int = {1'b0,req_addr};
req_len_int = req_len;
end else if(sdr_width == 2'b01) begin
req_addr_int = {req_addr,1'b0};
req_len_int = {req_len,1'b0};
end else begin
req_addr_int = {req_addr,2'b0};
req_len_int = {req_len,2'b0};
end
end
assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) :
(cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) :
(cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]});
assign page_ovflw = ({1'b0, req_len_int} > max_r2b_len) ? ~r2b_wrap : 1'b0;
assign r2b_len = r2b_start ? ((page_ovflw_r) ? max_r2b_len_r : lcl_req_len) :
lcl_req_len;
assign next_req_len = lcl_req_len - r2b_len;
assign next_sdr_addr = curr_sdr_addr + r2b_len;
assign r2b_wrap = lcl_wrap;
assign r2b_last = (r2b_start & !page_ovflw_r) | (req_st == `REQ_PAGE_WRAP);
always @ (posedge clk) begin
page_ovflw_r <= (req_ack) ? page_ovflw: 'h0;
max_r2b_len_r <= (req_ack) ? max_r2b_len: 'h0;
r2b_start <= (req_ack) ? 1'b1 :
(b2r_ack) ? 1'b0 : r2b_start;
r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
r2b_req_id <= (req_ack) ? req_id : r2b_req_id;
lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap;
lcl_req_len <= (req_ack) ? req_len_int :
(req_ld) ? next_req_len : lcl_req_len;
curr_sdr_addr <= (req_ack) ? req_addr_int :
(req_ld) ? next_sdr_addr : curr_sdr_addr;
end
always @ (*) begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = 1'b0;
r2b_req = 1'b0;
next_req_st = `REQ_IDLE;
case (req_st)
`REQ_IDLE : begin
r2x_idle = ~req;
req_idle = 1'b1;
req_ack = req & b2r_arb_ok;
req_ld = 1'b0;
r2b_req = 1'b0;
next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE;
end
`REQ_ACTIVE : begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1;
next_req_st = (b2r_ack ) ? ((page_ovflw_r) ? `REQ_PAGE_WRAP :`REQ_IDLE) : `REQ_ACTIVE;
end
`REQ_PAGE_WRAP : begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1;
next_req_st = (b2r_ack) ? `REQ_IDLE : `REQ_PAGE_WRAP;
end
endcase
end
always @ (posedge clk)
if (~reset_n) begin
req_st <= `REQ_IDLE;
end
else begin
req_st <= next_req_st;
end
wire [APP_AW-1:0] map_address ;
assign map_address = (req_ack) ? req_addr_int :
(req_ld) ? next_sdr_addr : curr_sdr_addr;
always @ (posedge clk) begin
r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} :
(cfg_colbits == 2'b01) ? {map_address[10:9]} :
(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} :
(cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} :
(cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]};
r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[22:10] :
(cfg_colbits == 2'b01) ? map_address[23:11] :
(cfg_colbits == 2'b10) ? map_address[24:12] : map_address[25:13];
end
endmodule | module sdrc_req_gen (clk,
reset_n,
cfg_colbits,
sdr_width,
req,
req_id,
req_addr,
req_len,
req_wrap,
req_wr_n,
req_ack,
r2x_idle,
r2b_req,
r2b_req_id,
r2b_start,
r2b_last,
r2b_wrap,
r2b_ba,
r2b_raddr,
r2b_caddr,
r2b_len,
r2b_write,
b2r_ack,
b2r_arb_ok
); |
parameter APP_AW = 26;
parameter APP_DW = 32;
parameter APP_BW = 4;
parameter APP_RW = 9;
parameter SDR_DW = 16;
parameter SDR_BW = 2;
input clk ;
input reset_n ;
input [1:0] cfg_colbits ;
input req ;
input [`SDR_REQ_ID_W-1:0] req_id ;
input [APP_AW-1:0] req_addr ;
input [APP_RW-1:0] req_len ;
input req_wr_n ;
input req_wrap ;
output req_ack ;
output r2x_idle ;
output r2b_req ;
output r2b_start ;
output r2b_last ;
output r2b_write ;
output r2b_wrap ;
output [`SDR_REQ_ID_W-1:0] r2b_req_id;
output [1:0] r2b_ba ;
output [12:0] r2b_raddr ;
output [12:0] r2b_caddr ;
output [`REQ_BW-1:0] r2b_len ;
input b2r_ack ;
input b2r_arb_ok ;
input [1:0] sdr_width;
`define REQ_IDLE 2'b00
`define REQ_ACTIVE 2'b01
`define REQ_PAGE_WRAP 2'b10
reg [1:0] req_st, next_req_st;
reg r2x_idle, req_ack, r2b_req, r2b_start,
r2b_write, req_idle, req_ld, lcl_wrap;
reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
reg [`REQ_BW-1:0] lcl_req_len;
wire r2b_last, page_ovflw;
reg page_ovflw_r;
wire [`REQ_BW-1:0] r2b_len, next_req_len;
wire [12:0] max_r2b_len;
reg [12:0] max_r2b_len_r;
reg [1:0] r2b_ba;
reg [12:0] r2b_raddr;
reg [12:0] r2b_caddr;
reg [APP_AW-1:0] curr_sdr_addr ;
wire [APP_AW-1:0] next_sdr_addr ;
reg [APP_AW:0] req_addr_int;
reg [APP_RW-1:0] req_len_int;
always @(*) begin
if(sdr_width == 2'b00) begin
req_addr_int = {1'b0,req_addr};
req_len_int = req_len;
end else if(sdr_width == 2'b01) begin
req_addr_int = {req_addr,1'b0};
req_len_int = {req_len,1'b0};
end else begin
req_addr_int = {req_addr,2'b0};
req_len_int = {req_len,2'b0};
end
end
assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) :
(cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) :
(cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]});
assign page_ovflw = ({1'b0, req_len_int} > max_r2b_len) ? ~r2b_wrap : 1'b0;
assign r2b_len = r2b_start ? ((page_ovflw_r) ? max_r2b_len_r : lcl_req_len) :
lcl_req_len;
assign next_req_len = lcl_req_len - r2b_len;
assign next_sdr_addr = curr_sdr_addr + r2b_len;
assign r2b_wrap = lcl_wrap;
assign r2b_last = (r2b_start & !page_ovflw_r) | (req_st == `REQ_PAGE_WRAP);
always @ (posedge clk) begin
page_ovflw_r <= (req_ack) ? page_ovflw: 'h0;
max_r2b_len_r <= (req_ack) ? max_r2b_len: 'h0;
r2b_start <= (req_ack) ? 1'b1 :
(b2r_ack) ? 1'b0 : r2b_start;
r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
r2b_req_id <= (req_ack) ? req_id : r2b_req_id;
lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap;
lcl_req_len <= (req_ack) ? req_len_int :
(req_ld) ? next_req_len : lcl_req_len;
curr_sdr_addr <= (req_ack) ? req_addr_int :
(req_ld) ? next_sdr_addr : curr_sdr_addr;
end
always @ (*) begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = 1'b0;
r2b_req = 1'b0;
next_req_st = `REQ_IDLE;
case (req_st)
`REQ_IDLE : begin
r2x_idle = ~req;
req_idle = 1'b1;
req_ack = req & b2r_arb_ok;
req_ld = 1'b0;
r2b_req = 1'b0;
next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE;
end
`REQ_ACTIVE : begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1;
next_req_st = (b2r_ack ) ? ((page_ovflw_r) ? `REQ_PAGE_WRAP :`REQ_IDLE) : `REQ_ACTIVE;
end
`REQ_PAGE_WRAP : begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1;
next_req_st = (b2r_ack) ? `REQ_IDLE : `REQ_PAGE_WRAP;
end
endcase
end
always @ (posedge clk)
if (~reset_n) begin
req_st <= `REQ_IDLE;
end
else begin
req_st <= next_req_st;
end
wire [APP_AW-1:0] map_address ;
assign map_address = (req_ack) ? req_addr_int :
(req_ld) ? next_sdr_addr : curr_sdr_addr;
always @ (posedge clk) begin
r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} :
(cfg_colbits == 2'b01) ? {map_address[10:9]} :
(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} :
(cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} :
(cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]};
r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[22:10] :
(cfg_colbits == 2'b01) ? map_address[23:11] :
(cfg_colbits == 2'b10) ? map_address[24:12] : map_address[25:13];
end
endmodule | 48 |
5,331 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter13/wb_conmax/wb_conmax_master_if.v | 113,839,829 | wb_conmax_master_if.v | v | 657 | 99 | [] | [] | [] | [(122, 715)] | null | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/wb_conmax/wb_conmax_master_if.v\n%Error: Exiting due to 3 error(s)\n' | 5,837 | module | module wb_conmax_master_if(
clk_i, rst_i,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o,
s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i,
s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o,
s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i,
s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o,
s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i,
s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o,
s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i,
s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o,
s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i,
s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o,
s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i,
s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o,
s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i,
s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o,
s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i,
s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o,
s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i,
s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o,
s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i,
s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o,
s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i,
s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o,
s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i,
s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o,
s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i,
s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o,
s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i,
s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o,
s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i,
s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o,
s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i
);
parameter dw = 32;
parameter aw = 32;
parameter sw = dw / 8;
input clk_i, rst_i;
input [dw-1:0] wb_data_i;
output [dw-1:0] wb_data_o;
input [aw-1:0] wb_addr_i;
input [sw-1:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
input [dw-1:0] s0_data_i;
output [dw-1:0] s0_data_o;
output [aw-1:0] s0_addr_o;
output [sw-1:0] s0_sel_o;
output s0_we_o;
output s0_cyc_o;
output s0_stb_o;
input s0_ack_i;
input s0_err_i;
input s0_rty_i;
input [dw-1:0] s1_data_i;
output [dw-1:0] s1_data_o;
output [aw-1:0] s1_addr_o;
output [sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
input s1_ack_i;
input s1_err_i;
input s1_rty_i;
input [dw-1:0] s2_data_i;
output [dw-1:0] s2_data_o;
output [aw-1:0] s2_addr_o;
output [sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
input s2_ack_i;
input s2_err_i;
input s2_rty_i;
input [dw-1:0] s3_data_i;
output [dw-1:0] s3_data_o;
output [aw-1:0] s3_addr_o;
output [sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
input s3_ack_i;
input s3_err_i;
input s3_rty_i;
input [dw-1:0] s4_data_i;
output [dw-1:0] s4_data_o;
output [aw-1:0] s4_addr_o;
output [sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
input s4_ack_i;
input s4_err_i;
input s4_rty_i;
input [dw-1:0] s5_data_i;
output [dw-1:0] s5_data_o;
output [aw-1:0] s5_addr_o;
output [sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
input s5_ack_i;
input s5_err_i;
input s5_rty_i;
input [dw-1:0] s6_data_i;
output [dw-1:0] s6_data_o;
output [aw-1:0] s6_addr_o;
output [sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
input s6_ack_i;
input s6_err_i;
input s6_rty_i;
input [dw-1:0] s7_data_i;
output [dw-1:0] s7_data_o;
output [aw-1:0] s7_addr_o;
output [sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
input s7_ack_i;
input s7_err_i;
input s7_rty_i;
input [dw-1:0] s8_data_i;
output [dw-1:0] s8_data_o;
output [aw-1:0] s8_addr_o;
output [sw-1:0] s8_sel_o;
output s8_we_o;
output s8_cyc_o;
output s8_stb_o;
input s8_ack_i;
input s8_err_i;
input s8_rty_i;
input [dw-1:0] s9_data_i;
output [dw-1:0] s9_data_o;
output [aw-1:0] s9_addr_o;
output [sw-1:0] s9_sel_o;
output s9_we_o;
output s9_cyc_o;
output s9_stb_o;
input s9_ack_i;
input s9_err_i;
input s9_rty_i;
input [dw-1:0] s10_data_i;
output [dw-1:0] s10_data_o;
output [aw-1:0] s10_addr_o;
output [sw-1:0] s10_sel_o;
output s10_we_o;
output s10_cyc_o;
output s10_stb_o;
input s10_ack_i;
input s10_err_i;
input s10_rty_i;
input [dw-1:0] s11_data_i;
output [dw-1:0] s11_data_o;
output [aw-1:0] s11_addr_o;
output [sw-1:0] s11_sel_o;
output s11_we_o;
output s11_cyc_o;
output s11_stb_o;
input s11_ack_i;
input s11_err_i;
input s11_rty_i;
input [dw-1:0] s12_data_i;
output [dw-1:0] s12_data_o;
output [aw-1:0] s12_addr_o;
output [sw-1:0] s12_sel_o;
output s12_we_o;
output s12_cyc_o;
output s12_stb_o;
input s12_ack_i;
input s12_err_i;
input s12_rty_i;
input [dw-1:0] s13_data_i;
output [dw-1:0] s13_data_o;
output [aw-1:0] s13_addr_o;
output [sw-1:0] s13_sel_o;
output s13_we_o;
output s13_cyc_o;
output s13_stb_o;
input s13_ack_i;
input s13_err_i;
input s13_rty_i;
input [dw-1:0] s14_data_i;
output [dw-1:0] s14_data_o;
output [aw-1:0] s14_addr_o;
output [sw-1:0] s14_sel_o;
output s14_we_o;
output s14_cyc_o;
output s14_stb_o;
input s14_ack_i;
input s14_err_i;
input s14_rty_i;
input [dw-1:0] s15_data_i;
output [dw-1:0] s15_data_o;
output [aw-1:0] s15_addr_o;
output [sw-1:0] s15_sel_o;
output s15_we_o;
output s15_cyc_o;
output s15_stb_o;
input s15_ack_i;
input s15_err_i;
input s15_rty_i;
reg [dw-1:0] wb_data_o;
reg wb_ack_o;
reg wb_err_o;
reg wb_rty_o;
wire [3:0] slv_sel;
wire s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next;
wire s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next;
wire s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next;
wire s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next;
reg s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o;
reg s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o;
reg s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o;
reg s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o;
assign slv_sel = wb_addr_i[aw-1:aw-4];
assign s0_addr_o = wb_addr_i;
assign s1_addr_o = wb_addr_i;
assign s2_addr_o = wb_addr_i;
assign s3_addr_o = wb_addr_i;
assign s4_addr_o = wb_addr_i;
assign s5_addr_o = wb_addr_i;
assign s6_addr_o = wb_addr_i;
assign s7_addr_o = wb_addr_i;
assign s8_addr_o = wb_addr_i;
assign s9_addr_o = wb_addr_i;
assign s10_addr_o = wb_addr_i;
assign s11_addr_o = wb_addr_i;
assign s12_addr_o = wb_addr_i;
assign s13_addr_o = wb_addr_i;
assign s14_addr_o = wb_addr_i;
assign s15_addr_o = wb_addr_i;
assign s0_sel_o = wb_sel_i;
assign s1_sel_o = wb_sel_i;
assign s2_sel_o = wb_sel_i;
assign s3_sel_o = wb_sel_i;
assign s4_sel_o = wb_sel_i;
assign s5_sel_o = wb_sel_i;
assign s6_sel_o = wb_sel_i;
assign s7_sel_o = wb_sel_i;
assign s8_sel_o = wb_sel_i;
assign s9_sel_o = wb_sel_i;
assign s10_sel_o = wb_sel_i;
assign s11_sel_o = wb_sel_i;
assign s12_sel_o = wb_sel_i;
assign s13_sel_o = wb_sel_i;
assign s14_sel_o = wb_sel_i;
assign s15_sel_o = wb_sel_i;
assign s0_data_o = wb_data_i;
assign s1_data_o = wb_data_i;
assign s2_data_o = wb_data_i;
assign s3_data_o = wb_data_i;
assign s4_data_o = wb_data_i;
assign s5_data_o = wb_data_i;
assign s6_data_o = wb_data_i;
assign s7_data_o = wb_data_i;
assign s8_data_o = wb_data_i;
assign s9_data_o = wb_data_i;
assign s10_data_o = wb_data_i;
assign s11_data_o = wb_data_i;
assign s12_data_o = wb_data_i;
assign s13_data_o = wb_data_i;
assign s14_data_o = wb_data_i;
assign s15_data_o = wb_data_i;
always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or
s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or
s9_data_i or s10_data_i or s11_data_i or s12_data_i or
s13_data_i or s14_data_i or s15_data_i)
case(slv_sel)
4'd0: wb_data_o = s0_data_i;
4'd1: wb_data_o = s1_data_i;
4'd2: wb_data_o = s2_data_i;
4'd3: wb_data_o = s3_data_i;
4'd4: wb_data_o = s4_data_i;
4'd5: wb_data_o = s5_data_i;
4'd6: wb_data_o = s6_data_i;
4'd7: wb_data_o = s7_data_i;
4'd8: wb_data_o = s8_data_i;
4'd9: wb_data_o = s9_data_i;
4'd10: wb_data_o = s10_data_i;
4'd11: wb_data_o = s11_data_i;
4'd12: wb_data_o = s12_data_i;
4'd13: wb_data_o = s13_data_i;
4'd14: wb_data_o = s14_data_i;
4'd15: wb_data_o = s15_data_i;
default: wb_data_o = {dw{1'bx}};
endcase
assign s0_we_o = wb_we_i;
assign s1_we_o = wb_we_i;
assign s2_we_o = wb_we_i;
assign s3_we_o = wb_we_i;
assign s4_we_o = wb_we_i;
assign s5_we_o = wb_we_i;
assign s6_we_o = wb_we_i;
assign s7_we_o = wb_we_i;
assign s8_we_o = wb_we_i;
assign s9_we_o = wb_we_i;
assign s10_we_o = wb_we_i;
assign s11_we_o = wb_we_i;
assign s12_we_o = wb_we_i;
assign s13_we_o = wb_we_i;
assign s14_we_o = wb_we_i;
assign s15_we_o = wb_we_i;
assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0);
assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0);
assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0);
assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0);
assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0);
assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0);
assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0);
assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0);
assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0);
assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0);
assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0);
assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0);
assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0);
assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0);
assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0);
assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0);
always @(posedge clk_i or posedge rst_i)
if(rst_i) s0_cyc_o <= #1 1'b0;
else s0_cyc_o <= #1 s0_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s1_cyc_o <= #1 1'b0;
else s1_cyc_o <= #1 s1_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s2_cyc_o <= #1 1'b0;
else s2_cyc_o <= #1 s2_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s3_cyc_o <= #1 1'b0;
else s3_cyc_o <= #1 s3_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s4_cyc_o <= #1 1'b0;
else s4_cyc_o <= #1 s4_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s5_cyc_o <= #1 1'b0;
else s5_cyc_o <= #1 s5_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s6_cyc_o <= #1 1'b0;
else s6_cyc_o <= #1 s6_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s7_cyc_o <= #1 1'b0;
else s7_cyc_o <= #1 s7_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s8_cyc_o <= #1 1'b0;
else s8_cyc_o <= #1 s8_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s9_cyc_o <= #1 1'b0;
else s9_cyc_o <= #1 s9_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s10_cyc_o <= #1 1'b0;
else s10_cyc_o <= #1 s10_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s11_cyc_o <= #1 1'b0;
else s11_cyc_o <= #1 s11_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s12_cyc_o <= #1 1'b0;
else s12_cyc_o <= #1 s12_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s13_cyc_o <= #1 1'b0;
else s13_cyc_o <= #1 s13_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s14_cyc_o <= #1 1'b0;
else s14_cyc_o <= #1 s14_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s15_cyc_o <= #1 1'b0;
else s15_cyc_o <= #1 s15_cyc_o_next;
assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0;
assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0;
assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0;
assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0;
assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0;
assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0;
assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0;
assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0;
assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0;
assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0;
assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0;
assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0;
assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0;
assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0;
assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0;
assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0;
always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or
s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or
s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or
s13_ack_i or s14_ack_i or s15_ack_i)
case(slv_sel)
4'd0: wb_ack_o = s0_ack_i;
4'd1: wb_ack_o = s1_ack_i;
4'd2: wb_ack_o = s2_ack_i;
4'd3: wb_ack_o = s3_ack_i;
4'd4: wb_ack_o = s4_ack_i;
4'd5: wb_ack_o = s5_ack_i;
4'd6: wb_ack_o = s6_ack_i;
4'd7: wb_ack_o = s7_ack_i;
4'd8: wb_ack_o = s8_ack_i;
4'd9: wb_ack_o = s9_ack_i;
4'd10: wb_ack_o = s10_ack_i;
4'd11: wb_ack_o = s11_ack_i;
4'd12: wb_ack_o = s12_ack_i;
4'd13: wb_ack_o = s13_ack_i;
4'd14: wb_ack_o = s14_ack_i;
4'd15: wb_ack_o = s15_ack_i;
default: wb_ack_o = 1'b0;
endcase
always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or
s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or
s9_err_i or s10_err_i or s11_err_i or s12_err_i or
s13_err_i or s14_err_i or s15_err_i)
case(slv_sel)
4'd0: wb_err_o = s0_err_i;
4'd1: wb_err_o = s1_err_i;
4'd2: wb_err_o = s2_err_i;
4'd3: wb_err_o = s3_err_i;
4'd4: wb_err_o = s4_err_i;
4'd5: wb_err_o = s5_err_i;
4'd6: wb_err_o = s6_err_i;
4'd7: wb_err_o = s7_err_i;
4'd8: wb_err_o = s8_err_i;
4'd9: wb_err_o = s9_err_i;
4'd10: wb_err_o = s10_err_i;
4'd11: wb_err_o = s11_err_i;
4'd12: wb_err_o = s12_err_i;
4'd13: wb_err_o = s13_err_i;
4'd14: wb_err_o = s14_err_i;
4'd15: wb_err_o = s15_err_i;
default: wb_err_o = 1'b0;
endcase
always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or
s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or
s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or
s13_rty_i or s14_rty_i or s15_rty_i)
case(slv_sel)
4'd0: wb_rty_o = s0_rty_i;
4'd1: wb_rty_o = s1_rty_i;
4'd2: wb_rty_o = s2_rty_i;
4'd3: wb_rty_o = s3_rty_i;
4'd4: wb_rty_o = s4_rty_i;
4'd5: wb_rty_o = s5_rty_i;
4'd6: wb_rty_o = s6_rty_i;
4'd7: wb_rty_o = s7_rty_i;
4'd8: wb_rty_o = s8_rty_i;
4'd9: wb_rty_o = s9_rty_i;
4'd10: wb_rty_o = s10_rty_i;
4'd11: wb_rty_o = s11_rty_i;
4'd12: wb_rty_o = s12_rty_i;
4'd13: wb_rty_o = s13_rty_i;
4'd14: wb_rty_o = s14_rty_i;
4'd15: wb_rty_o = s15_rty_i;
default: wb_rty_o = 1'b0;
endcase
endmodule | module wb_conmax_master_if(
clk_i, rst_i,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o,
s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i,
s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o,
s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i,
s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o,
s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i,
s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o,
s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i,
s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o,
s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i,
s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o,
s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i,
s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o,
s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i,
s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o,
s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i,
s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o,
s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i,
s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o,
s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i,
s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o,
s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i,
s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o,
s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i,
s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o,
s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i,
s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o,
s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i,
s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o,
s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i,
s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o,
s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i
); |
parameter dw = 32;
parameter aw = 32;
parameter sw = dw / 8;
input clk_i, rst_i;
input [dw-1:0] wb_data_i;
output [dw-1:0] wb_data_o;
input [aw-1:0] wb_addr_i;
input [sw-1:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
input [dw-1:0] s0_data_i;
output [dw-1:0] s0_data_o;
output [aw-1:0] s0_addr_o;
output [sw-1:0] s0_sel_o;
output s0_we_o;
output s0_cyc_o;
output s0_stb_o;
input s0_ack_i;
input s0_err_i;
input s0_rty_i;
input [dw-1:0] s1_data_i;
output [dw-1:0] s1_data_o;
output [aw-1:0] s1_addr_o;
output [sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
input s1_ack_i;
input s1_err_i;
input s1_rty_i;
input [dw-1:0] s2_data_i;
output [dw-1:0] s2_data_o;
output [aw-1:0] s2_addr_o;
output [sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
input s2_ack_i;
input s2_err_i;
input s2_rty_i;
input [dw-1:0] s3_data_i;
output [dw-1:0] s3_data_o;
output [aw-1:0] s3_addr_o;
output [sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
input s3_ack_i;
input s3_err_i;
input s3_rty_i;
input [dw-1:0] s4_data_i;
output [dw-1:0] s4_data_o;
output [aw-1:0] s4_addr_o;
output [sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
input s4_ack_i;
input s4_err_i;
input s4_rty_i;
input [dw-1:0] s5_data_i;
output [dw-1:0] s5_data_o;
output [aw-1:0] s5_addr_o;
output [sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
input s5_ack_i;
input s5_err_i;
input s5_rty_i;
input [dw-1:0] s6_data_i;
output [dw-1:0] s6_data_o;
output [aw-1:0] s6_addr_o;
output [sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
input s6_ack_i;
input s6_err_i;
input s6_rty_i;
input [dw-1:0] s7_data_i;
output [dw-1:0] s7_data_o;
output [aw-1:0] s7_addr_o;
output [sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
input s7_ack_i;
input s7_err_i;
input s7_rty_i;
input [dw-1:0] s8_data_i;
output [dw-1:0] s8_data_o;
output [aw-1:0] s8_addr_o;
output [sw-1:0] s8_sel_o;
output s8_we_o;
output s8_cyc_o;
output s8_stb_o;
input s8_ack_i;
input s8_err_i;
input s8_rty_i;
input [dw-1:0] s9_data_i;
output [dw-1:0] s9_data_o;
output [aw-1:0] s9_addr_o;
output [sw-1:0] s9_sel_o;
output s9_we_o;
output s9_cyc_o;
output s9_stb_o;
input s9_ack_i;
input s9_err_i;
input s9_rty_i;
input [dw-1:0] s10_data_i;
output [dw-1:0] s10_data_o;
output [aw-1:0] s10_addr_o;
output [sw-1:0] s10_sel_o;
output s10_we_o;
output s10_cyc_o;
output s10_stb_o;
input s10_ack_i;
input s10_err_i;
input s10_rty_i;
input [dw-1:0] s11_data_i;
output [dw-1:0] s11_data_o;
output [aw-1:0] s11_addr_o;
output [sw-1:0] s11_sel_o;
output s11_we_o;
output s11_cyc_o;
output s11_stb_o;
input s11_ack_i;
input s11_err_i;
input s11_rty_i;
input [dw-1:0] s12_data_i;
output [dw-1:0] s12_data_o;
output [aw-1:0] s12_addr_o;
output [sw-1:0] s12_sel_o;
output s12_we_o;
output s12_cyc_o;
output s12_stb_o;
input s12_ack_i;
input s12_err_i;
input s12_rty_i;
input [dw-1:0] s13_data_i;
output [dw-1:0] s13_data_o;
output [aw-1:0] s13_addr_o;
output [sw-1:0] s13_sel_o;
output s13_we_o;
output s13_cyc_o;
output s13_stb_o;
input s13_ack_i;
input s13_err_i;
input s13_rty_i;
input [dw-1:0] s14_data_i;
output [dw-1:0] s14_data_o;
output [aw-1:0] s14_addr_o;
output [sw-1:0] s14_sel_o;
output s14_we_o;
output s14_cyc_o;
output s14_stb_o;
input s14_ack_i;
input s14_err_i;
input s14_rty_i;
input [dw-1:0] s15_data_i;
output [dw-1:0] s15_data_o;
output [aw-1:0] s15_addr_o;
output [sw-1:0] s15_sel_o;
output s15_we_o;
output s15_cyc_o;
output s15_stb_o;
input s15_ack_i;
input s15_err_i;
input s15_rty_i;
reg [dw-1:0] wb_data_o;
reg wb_ack_o;
reg wb_err_o;
reg wb_rty_o;
wire [3:0] slv_sel;
wire s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next;
wire s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next;
wire s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next;
wire s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next;
reg s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o;
reg s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o;
reg s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o;
reg s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o;
assign slv_sel = wb_addr_i[aw-1:aw-4];
assign s0_addr_o = wb_addr_i;
assign s1_addr_o = wb_addr_i;
assign s2_addr_o = wb_addr_i;
assign s3_addr_o = wb_addr_i;
assign s4_addr_o = wb_addr_i;
assign s5_addr_o = wb_addr_i;
assign s6_addr_o = wb_addr_i;
assign s7_addr_o = wb_addr_i;
assign s8_addr_o = wb_addr_i;
assign s9_addr_o = wb_addr_i;
assign s10_addr_o = wb_addr_i;
assign s11_addr_o = wb_addr_i;
assign s12_addr_o = wb_addr_i;
assign s13_addr_o = wb_addr_i;
assign s14_addr_o = wb_addr_i;
assign s15_addr_o = wb_addr_i;
assign s0_sel_o = wb_sel_i;
assign s1_sel_o = wb_sel_i;
assign s2_sel_o = wb_sel_i;
assign s3_sel_o = wb_sel_i;
assign s4_sel_o = wb_sel_i;
assign s5_sel_o = wb_sel_i;
assign s6_sel_o = wb_sel_i;
assign s7_sel_o = wb_sel_i;
assign s8_sel_o = wb_sel_i;
assign s9_sel_o = wb_sel_i;
assign s10_sel_o = wb_sel_i;
assign s11_sel_o = wb_sel_i;
assign s12_sel_o = wb_sel_i;
assign s13_sel_o = wb_sel_i;
assign s14_sel_o = wb_sel_i;
assign s15_sel_o = wb_sel_i;
assign s0_data_o = wb_data_i;
assign s1_data_o = wb_data_i;
assign s2_data_o = wb_data_i;
assign s3_data_o = wb_data_i;
assign s4_data_o = wb_data_i;
assign s5_data_o = wb_data_i;
assign s6_data_o = wb_data_i;
assign s7_data_o = wb_data_i;
assign s8_data_o = wb_data_i;
assign s9_data_o = wb_data_i;
assign s10_data_o = wb_data_i;
assign s11_data_o = wb_data_i;
assign s12_data_o = wb_data_i;
assign s13_data_o = wb_data_i;
assign s14_data_o = wb_data_i;
assign s15_data_o = wb_data_i;
always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or
s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or
s9_data_i or s10_data_i or s11_data_i or s12_data_i or
s13_data_i or s14_data_i or s15_data_i)
case(slv_sel)
4'd0: wb_data_o = s0_data_i;
4'd1: wb_data_o = s1_data_i;
4'd2: wb_data_o = s2_data_i;
4'd3: wb_data_o = s3_data_i;
4'd4: wb_data_o = s4_data_i;
4'd5: wb_data_o = s5_data_i;
4'd6: wb_data_o = s6_data_i;
4'd7: wb_data_o = s7_data_i;
4'd8: wb_data_o = s8_data_i;
4'd9: wb_data_o = s9_data_i;
4'd10: wb_data_o = s10_data_i;
4'd11: wb_data_o = s11_data_i;
4'd12: wb_data_o = s12_data_i;
4'd13: wb_data_o = s13_data_i;
4'd14: wb_data_o = s14_data_i;
4'd15: wb_data_o = s15_data_i;
default: wb_data_o = {dw{1'bx}};
endcase
assign s0_we_o = wb_we_i;
assign s1_we_o = wb_we_i;
assign s2_we_o = wb_we_i;
assign s3_we_o = wb_we_i;
assign s4_we_o = wb_we_i;
assign s5_we_o = wb_we_i;
assign s6_we_o = wb_we_i;
assign s7_we_o = wb_we_i;
assign s8_we_o = wb_we_i;
assign s9_we_o = wb_we_i;
assign s10_we_o = wb_we_i;
assign s11_we_o = wb_we_i;
assign s12_we_o = wb_we_i;
assign s13_we_o = wb_we_i;
assign s14_we_o = wb_we_i;
assign s15_we_o = wb_we_i;
assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0);
assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0);
assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0);
assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0);
assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0);
assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0);
assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0);
assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0);
assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0);
assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0);
assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0);
assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0);
assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0);
assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0);
assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0);
assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0);
always @(posedge clk_i or posedge rst_i)
if(rst_i) s0_cyc_o <= #1 1'b0;
else s0_cyc_o <= #1 s0_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s1_cyc_o <= #1 1'b0;
else s1_cyc_o <= #1 s1_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s2_cyc_o <= #1 1'b0;
else s2_cyc_o <= #1 s2_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s3_cyc_o <= #1 1'b0;
else s3_cyc_o <= #1 s3_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s4_cyc_o <= #1 1'b0;
else s4_cyc_o <= #1 s4_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s5_cyc_o <= #1 1'b0;
else s5_cyc_o <= #1 s5_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s6_cyc_o <= #1 1'b0;
else s6_cyc_o <= #1 s6_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s7_cyc_o <= #1 1'b0;
else s7_cyc_o <= #1 s7_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s8_cyc_o <= #1 1'b0;
else s8_cyc_o <= #1 s8_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s9_cyc_o <= #1 1'b0;
else s9_cyc_o <= #1 s9_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s10_cyc_o <= #1 1'b0;
else s10_cyc_o <= #1 s10_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s11_cyc_o <= #1 1'b0;
else s11_cyc_o <= #1 s11_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s12_cyc_o <= #1 1'b0;
else s12_cyc_o <= #1 s12_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s13_cyc_o <= #1 1'b0;
else s13_cyc_o <= #1 s13_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s14_cyc_o <= #1 1'b0;
else s14_cyc_o <= #1 s14_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s15_cyc_o <= #1 1'b0;
else s15_cyc_o <= #1 s15_cyc_o_next;
assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0;
assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0;
assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0;
assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0;
assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0;
assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0;
assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0;
assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0;
assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0;
assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0;
assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0;
assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0;
assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0;
assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0;
assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0;
assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0;
always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or
s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or
s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or
s13_ack_i or s14_ack_i or s15_ack_i)
case(slv_sel)
4'd0: wb_ack_o = s0_ack_i;
4'd1: wb_ack_o = s1_ack_i;
4'd2: wb_ack_o = s2_ack_i;
4'd3: wb_ack_o = s3_ack_i;
4'd4: wb_ack_o = s4_ack_i;
4'd5: wb_ack_o = s5_ack_i;
4'd6: wb_ack_o = s6_ack_i;
4'd7: wb_ack_o = s7_ack_i;
4'd8: wb_ack_o = s8_ack_i;
4'd9: wb_ack_o = s9_ack_i;
4'd10: wb_ack_o = s10_ack_i;
4'd11: wb_ack_o = s11_ack_i;
4'd12: wb_ack_o = s12_ack_i;
4'd13: wb_ack_o = s13_ack_i;
4'd14: wb_ack_o = s14_ack_i;
4'd15: wb_ack_o = s15_ack_i;
default: wb_ack_o = 1'b0;
endcase
always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or
s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or
s9_err_i or s10_err_i or s11_err_i or s12_err_i or
s13_err_i or s14_err_i or s15_err_i)
case(slv_sel)
4'd0: wb_err_o = s0_err_i;
4'd1: wb_err_o = s1_err_i;
4'd2: wb_err_o = s2_err_i;
4'd3: wb_err_o = s3_err_i;
4'd4: wb_err_o = s4_err_i;
4'd5: wb_err_o = s5_err_i;
4'd6: wb_err_o = s6_err_i;
4'd7: wb_err_o = s7_err_i;
4'd8: wb_err_o = s8_err_i;
4'd9: wb_err_o = s9_err_i;
4'd10: wb_err_o = s10_err_i;
4'd11: wb_err_o = s11_err_i;
4'd12: wb_err_o = s12_err_i;
4'd13: wb_err_o = s13_err_i;
4'd14: wb_err_o = s14_err_i;
4'd15: wb_err_o = s15_err_i;
default: wb_err_o = 1'b0;
endcase
always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or
s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or
s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or
s13_rty_i or s14_rty_i or s15_rty_i)
case(slv_sel)
4'd0: wb_rty_o = s0_rty_i;
4'd1: wb_rty_o = s1_rty_i;
4'd2: wb_rty_o = s2_rty_i;
4'd3: wb_rty_o = s3_rty_i;
4'd4: wb_rty_o = s4_rty_i;
4'd5: wb_rty_o = s5_rty_i;
4'd6: wb_rty_o = s6_rty_i;
4'd7: wb_rty_o = s7_rty_i;
4'd8: wb_rty_o = s8_rty_i;
4'd9: wb_rty_o = s9_rty_i;
4'd10: wb_rty_o = s10_rty_i;
4'd11: wb_rty_o = s11_rty_i;
4'd12: wb_rty_o = s12_rty_i;
4'd13: wb_rty_o = s13_rty_i;
4'd14: wb_rty_o = s14_rty_i;
4'd15: wb_rty_o = s15_rty_i;
default: wb_rty_o = 1'b0;
endcase
endmodule | 48 |
5,334 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter13/wb_conmax/wb_conmax_pri_enc.v | 113,839,829 | wb_conmax_pri_enc.v | v | 184 | 85 | [] | [] | [] | [(122, 242)] | null | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter13/wb_conmax,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter13/wb_conmax/wb_conmax_pri_enc.v\n%Error: Exiting due to 3 error(s)\n' | 5,840 | module | module wb_conmax_pri_enc(
valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri_out
);
parameter [1:0] pri_sel = 2'd0;
input [7:0] valid;
input [1:0] pri0, pri1, pri2, pri3;
input [1:0] pri4, pri5, pri6, pri7;
output [1:0] pri_out;
wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [3:0] pri_out_tmp;
reg [1:0] pri_out0, pri_out1;
wire [1:0] pri_out;
wb_conmax_pri_dec #(pri_sel) pd0(
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_conmax_pri_dec #(pri_sel) pd1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_conmax_pri_dec #(pri_sel) pd2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_conmax_pri_dec #(pri_sel) pd3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_conmax_pri_dec #(pri_sel) pd4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_conmax_pri_dec #(pri_sel) pd5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_conmax_pri_dec #(pri_sel) pd6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_conmax_pri_dec #(pri_sel) pd7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out;
always @(pri_out_tmp)
if(pri_out_tmp[3]) pri_out1 = 2'h3;
else
if(pri_out_tmp[2]) pri_out1 = 2'h2;
else
if(pri_out_tmp[1]) pri_out1 = 2'h1;
else pri_out1 = 2'h0;
always @(pri_out_tmp)
if(pri_out_tmp[1]) pri_out0 = 2'h1;
else pri_out0 = 2'h0;
assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 );
endmodule | module wb_conmax_pri_enc(
valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri_out
); |
parameter [1:0] pri_sel = 2'd0;
input [7:0] valid;
input [1:0] pri0, pri1, pri2, pri3;
input [1:0] pri4, pri5, pri6, pri7;
output [1:0] pri_out;
wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [3:0] pri_out_tmp;
reg [1:0] pri_out0, pri_out1;
wire [1:0] pri_out;
wb_conmax_pri_dec #(pri_sel) pd0(
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_conmax_pri_dec #(pri_sel) pd1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_conmax_pri_dec #(pri_sel) pd2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_conmax_pri_dec #(pri_sel) pd3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_conmax_pri_dec #(pri_sel) pd4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_conmax_pri_dec #(pri_sel) pd5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_conmax_pri_dec #(pri_sel) pd6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_conmax_pri_dec #(pri_sel) pd7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out;
always @(pri_out_tmp)
if(pri_out_tmp[3]) pri_out1 = 2'h3;
else
if(pri_out_tmp[2]) pri_out1 = 2'h2;
else
if(pri_out_tmp[1]) pri_out1 = 2'h1;
else pri_out1 = 2'h0;
always @(pri_out_tmp)
if(pri_out_tmp[1]) pri_out0 = 2'h1;
else pri_out0 = 2'h0;
assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 );
endmodule | 48 |
5,336 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter2/inst_fetch_tb.v | 113,839,829 | inst_fetch_tb.v | v | 26 | 38 | [] | [] | [] | null | line:17: before: "$" | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter2,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter2/inst_fetch_tb.v\n%Error: Exiting due to 3 error(s)\n' | 5,898 | module | module inst_fetch_tb;
reg CLOCK_50;
reg rst;
wire[31:0] inst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
#1000 $stop;
end
inst_fetch inst_fetch0(
.clk(CLOCK_50),
.rst(rst),
.inst_o(inst)
);
endmodule | module inst_fetch_tb; |
reg CLOCK_50;
reg rst;
wire[31:0] inst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
#1000 $stop;
end
inst_fetch inst_fetch0(
.clk(CLOCK_50),
.rst(rst),
.inst_o(inst)
);
endmodule | 48 |
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